/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _SYS_CTRL_H_ #define _SYS_CTRL_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_SYS_CTRL_SET_OFFSET (1024) #define REG_SYS_CTRL_CLR_OFFSET (2048) #define REG_SYS_CTRL_BASE (0x51500000) typedef volatile struct { uint32_t aon_soft_rst_ctrl0; // 0x00000000 uint32_t clken_lte; // 0x00000004 uint32_t clken_lte_intf; // 0x00000008 uint32_t rstctrl_lte; // 0x0000000c uint32_t lte_autogate_mode; // 0x00000010 uint32_t lte_autogate_en; // 0x00000014 uint32_t lte_autogate_delay_num; // 0x00000018 uint32_t aon_lpc_ctrl; // 0x0000001c uint32_t aon_clock_en0; // 0x00000020 uint32_t aon_clock_en1; // 0x00000024 uint32_t aon_clock_auto_sel0; // 0x00000028 uint32_t aon_clock_auto_sel1; // 0x0000002c uint32_t aon_clock_auto_sel2; // 0x00000030 uint32_t aon_clock_auto_sel3; // 0x00000034 uint32_t aon_clock_force_en0; // 0x00000038 uint32_t aon_clock_force_en1; // 0x0000003c uint32_t aon_clock_force_en2; // 0x00000040 uint32_t aon_clock_force_en3; // 0x00000044 uint32_t aon_soft_rst_ctrl1; // 0x00000048 uint32_t mipi_csi_cfg_reg; // 0x0000004c uint32_t cfg_clk_uart2; // 0x00000050 uint32_t cfg_clk_uart3; // 0x00000054 uint32_t cfg_clk_debug_host; // 0x00000058 uint32_t __92[1]; // 0x0000005c uint32_t rc_calib_ctrl; // 0x00000060 uint32_t rc_calib_th_val; // 0x00000064 uint32_t rc_calib_out_val; // 0x00000068 uint32_t emmc_slice_phy_ctrl; // 0x0000006c uint32_t dma_req_ctrl; // 0x00000070 uint32_t apt_trigger_sel; // 0x00000074 uint32_t ahb2ahb_ab_funcdma_ctrl; // 0x00000078 uint32_t ahb2ahb_ab_funcdma_sts; // 0x0000007c uint32_t ahb2ahb_ab_dap_ctrl; // 0x00000080 uint32_t ahb2ahb_ab_dap_sts; // 0x00000084 uint32_t ahb2axi_pub_ctrl; // 0x00000088 uint32_t ahb2axi_pub_sts; // 0x0000008c uint32_t axi2axi_pub_sts_0; // 0x00000090 uint32_t axi2axi_pub_sts_1; // 0x00000094 uint32_t ahb2ahb_ab_aon2lps_ctrl; // 0x00000098 uint32_t ahb2ahb_ab_aon2lps_sts; // 0x0000009c uint32_t ahb2ahb_ab_lps2aon_ctrl; // 0x000000a0 uint32_t ahb2ahb_ab_lps2aon_sts; // 0x000000a4 uint32_t sysctrl_reg0; // 0x000000a8 uint32_t plls_sts; // 0x000000ac uint32_t cfg_aon_anti_hang; // 0x000000b0 uint32_t cfg_aon_qos; // 0x000000b4 uint32_t aon_ahb_mtx_slice_autogate_en; // 0x000000b8 uint32_t dap_djtag_en_cfg; // 0x000000bc uint32_t lte_ahb2ahb_sync_cfg; // 0x000000c0 uint32_t cfg_aon_io_core_ie_0; // 0x000000c4 uint32_t cfg_aon_io_core_ie_1; // 0x000000c8 uint32_t cfg_aon_io_core_ie_2; // 0x000000cc uint32_t cfg_aon_io_core_ie_3; // 0x000000d0 uint32_t __212[203]; // 0x000000d4 uint32_t aon_soft_rst_ctrl0_set; // 0x00000400 uint32_t clken_lte_set; // 0x00000404 uint32_t clken_lte_intf_set; // 0x00000408 uint32_t rstctrl_lte_set; // 0x0000040c uint32_t __1040[1]; // 0x00000410 uint32_t lte_autogate_en_set; // 0x00000414 uint32_t __1048[1]; // 0x00000418 uint32_t aon_lpc_ctrl_set; // 0x0000041c uint32_t aon_clock_en0_set; // 0x00000420 uint32_t aon_clock_en1_set; // 0x00000424 uint32_t aon_clock_auto_sel0_set; // 0x00000428 uint32_t aon_clock_auto_sel1_set; // 0x0000042c uint32_t aon_clock_auto_sel2_set; // 0x00000430 uint32_t aon_clock_auto_sel3_set; // 0x00000434 uint32_t aon_clock_force_en0_set; // 0x00000438 uint32_t aon_clock_force_en1_set; // 0x0000043c uint32_t aon_clock_force_en2_set; // 0x00000440 uint32_t aon_clock_force_en3_set; // 0x00000444 uint32_t aon_soft_rst_ctrl1_set; // 0x00000448 uint32_t mipi_csi_cfg_reg_set; // 0x0000044c uint32_t cfg_clk_uart2_set; // 0x00000450 uint32_t cfg_clk_uart3_set; // 0x00000454 uint32_t cfg_clk_debug_host_set; // 0x00000458 uint32_t __1116[1]; // 0x0000045c uint32_t rc_calib_ctrl_set; // 0x00000460 uint32_t __1124[2]; // 0x00000464 uint32_t emmc_slice_phy_ctrl_set; // 0x0000046c uint32_t dma_req_ctrl_set; // 0x00000470 uint32_t apt_trigger_sel_set; // 0x00000474 uint32_t ahb2ahb_ab_funcdma_ctrl_set; // 0x00000478 uint32_t __1148[1]; // 0x0000047c uint32_t ahb2ahb_ab_dap_ctrl_set; // 0x00000480 uint32_t __1156[1]; // 0x00000484 uint32_t ahb2axi_pub_ctrl_set; // 0x00000488 uint32_t __1164[3]; // 0x0000048c uint32_t ahb2ahb_ab_aon2lps_ctrl_set; // 0x00000498 uint32_t __1180[1]; // 0x0000049c uint32_t ahb2ahb_ab_lps2aon_ctrl_set; // 0x000004a0 uint32_t __1188[1]; // 0x000004a4 uint32_t sysctrl_reg0_set; // 0x000004a8 uint32_t __1196[1]; // 0x000004ac uint32_t cfg_aon_anti_hang_set; // 0x000004b0 uint32_t __1204[1]; // 0x000004b4 uint32_t aon_ahb_mtx_slice_autogate_en_set; // 0x000004b8 uint32_t dap_djtag_en_cfg_set; // 0x000004bc uint32_t lte_ahb2ahb_sync_cfg_set; // 0x000004c0 uint32_t cfg_aon_io_core_ie_0_set; // 0x000004c4 uint32_t cfg_aon_io_core_ie_1_set; // 0x000004c8 uint32_t cfg_aon_io_core_ie_2_set; // 0x000004cc uint32_t cfg_aon_io_core_ie_3_set; // 0x000004d0 uint32_t __1236[203]; // 0x000004d4 uint32_t aon_soft_rst_ctrl0_clr; // 0x00000800 uint32_t clken_lte_clr; // 0x00000804 uint32_t clken_lte_intf_clr; // 0x00000808 uint32_t rstctrl_lte_clr; // 0x0000080c uint32_t __2064[1]; // 0x00000810 uint32_t lte_autogate_en_clr; // 0x00000814 uint32_t __2072[1]; // 0x00000818 uint32_t aon_lpc_ctrl_clr; // 0x0000081c uint32_t aon_clock_en0_clr; // 0x00000820 uint32_t aon_clock_en1_clr; // 0x00000824 uint32_t aon_clock_auto_sel0_clr; // 0x00000828 uint32_t aon_clock_auto_sel1_clr; // 0x0000082c uint32_t aon_clock_auto_sel2_clr; // 0x00000830 uint32_t aon_clock_auto_sel3_clr; // 0x00000834 uint32_t aon_clock_force_en0_clr; // 0x00000838 uint32_t aon_clock_force_en1_clr; // 0x0000083c uint32_t aon_clock_force_en2_clr; // 0x00000840 uint32_t aon_clock_force_en3_clr; // 0x00000844 uint32_t aon_soft_rst_ctrl1_clr; // 0x00000848 uint32_t mipi_csi_cfg_reg_clr; // 0x0000084c uint32_t cfg_clk_uart2_clr; // 0x00000850 uint32_t cfg_clk_uart3_clr; // 0x00000854 uint32_t cfg_clk_debug_host_clr; // 0x00000858 uint32_t __2140[1]; // 0x0000085c uint32_t rc_calib_ctrl_clr; // 0x00000860 uint32_t __2148[2]; // 0x00000864 uint32_t emmc_slice_phy_ctrl_clr; // 0x0000086c uint32_t dma_req_ctrl_clr; // 0x00000870 uint32_t apt_trigger_sel_clr; // 0x00000874 uint32_t ahb2ahb_ab_funcdma_ctrl_clr; // 0x00000878 uint32_t __2172[1]; // 0x0000087c uint32_t ahb2ahb_ab_dap_ctrl_clr; // 0x00000880 uint32_t __2180[1]; // 0x00000884 uint32_t ahb2axi_pub_ctrl_clr; // 0x00000888 uint32_t __2188[3]; // 0x0000088c uint32_t ahb2ahb_ab_aon2lps_ctrl_clr; // 0x00000898 uint32_t __2204[1]; // 0x0000089c uint32_t ahb2ahb_ab_lps2aon_ctrl_clr; // 0x000008a0 uint32_t __2212[1]; // 0x000008a4 uint32_t sysctrl_reg0_clr; // 0x000008a8 uint32_t __2220[1]; // 0x000008ac uint32_t cfg_aon_anti_hang_clr; // 0x000008b0 uint32_t __2228[1]; // 0x000008b4 uint32_t aon_ahb_mtx_slice_autogate_en_clr; // 0x000008b8 uint32_t dap_djtag_en_cfg_clr; // 0x000008bc uint32_t lte_ahb2ahb_sync_cfg_clr; // 0x000008c0 uint32_t cfg_aon_io_core_ie_0_clr; // 0x000008c4 uint32_t cfg_aon_io_core_ie_1_clr; // 0x000008c8 uint32_t cfg_aon_io_core_ie_2_clr; // 0x000008cc uint32_t cfg_aon_io_core_ie_3_clr; // 0x000008d0 } HWP_SYS_CTRL_T; #define hwp_sysCtrl ((HWP_SYS_CTRL_T *)REG_ACCESS_ADDRESS(REG_SYS_CTRL_BASE)) // aon_soft_rst_ctrl0 typedef union { uint32_t v; struct { uint32_t ahbmux_soft_rst : 1; // [0] uint32_t ahb2axi_soft_rst : 1; // [1] uint32_t async_bridge_soft_rst : 1; // [2] uint32_t dap_soft_rst : 1; // [3] uint32_t djtag_ctrl_soft_rst : 1; // [4] uint32_t efuse_soft_rst : 1; // [5] uint32_t lps_ifc_soft_rst : 1; // [6] uint32_t aon2lps_soft_rst : 1; // [7] uint32_t lps2aon_soft_rst : 1; // [8] uint32_t adimst_soft_rst : 1; // [9] uint32_t spinlock_soft_rst : 1; // [10] uint32_t aon_ifc_soft_rst : 1; // [11] uint32_t dbg_host_soft_rst : 1; // [12] uint32_t aif_soft_rst : 1; // [13] uint32_t uart2_soft_rst : 1; // [14] uint32_t uart3_soft_rst : 1; // [15] uint32_t idle_timer_soft_rst : 1; // [16] uint32_t aud_2ad_soft_rst : 1; // [17] uint32_t gpio2_soft_rst : 1; // [18] uint32_t gpt2_soft_rst : 1; // [19] uint32_t i2c3_soft_rst : 1; // [20] uint32_t mon_ctrl_soft_rst : 1; // [21] uint32_t sysmail_soft_rst : 1; // [22] uint32_t spi2_soft_rst : 1; // [23] uint32_t iomux_soft_rst : 1; // [24] uint32_t aon_imem_soft_rst : 1; // [25] uint32_t ana_wrap1_soft_rst : 1; // [26] uint32_t ana_wrap2_soft_rst : 1; // [27] uint32_t usbphy_soft_rst : 1; // [28] uint32_t scc_soft_rst : 1; // [29] uint32_t __31_30 : 2; // [31:30] } b; } REG_SYS_CTRL_AON_SOFT_RST_CTRL0_T; // clken_lte typedef union { uint32_t v; struct { uint32_t txrx_func_en : 1; // [0] uint32_t coeff_func_en : 1; // [1] uint32_t ldtc_func_en : 1; // [2] uint32_t ldtc1_func_en : 1; // [3] uint32_t measpwr_func_en : 1; // [4] uint32_t iddet_func_en : 1; // [5] uint32_t otdoa_func_en : 1; // [6] uint32_t uldft_func_en : 1; // [7] uint32_t pusch_func_en : 1; // [8] uint32_t csirs_func_en : 1; // [9] uint32_t dlfft_func_en : 1; // [10] uint32_t rfad_func_en : 1; // [11] uint32_t rxcapt_func_en : 1; // [12] uint32_t hsdl_func_en : 1; // [13] uint32_t dbgio_func_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_SYS_CTRL_CLKEN_LTE_T; // clken_lte_intf typedef union { uint32_t v; struct { uint32_t txrx_intf_en : 1; // [0] uint32_t coeff_intf_en : 1; // [1] uint32_t ldtc_intf_en : 1; // [2] uint32_t ldtc1_intf_en : 1; // [3] uint32_t measpwr_intf_en : 1; // [4] uint32_t iddet_intf_en : 1; // [5] uint32_t otdoa_intf_en : 1; // [6] uint32_t uldft_intf_en : 1; // [7] uint32_t pusch_intf_en : 1; // [8] uint32_t csirs_intf_en : 1; // [9] uint32_t dlfft_intf_en : 1; // [10] uint32_t rfad_intf_en : 1; // [11] uint32_t rxcapt_intf_en : 1; // [12] uint32_t hsdl_intf_en : 1; // [13] uint32_t dbgio_intf_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_SYS_CTRL_CLKEN_LTE_INTF_T; // rstctrl_lte typedef union { uint32_t v; struct { uint32_t txrx_tx_soft_rst : 1; // [0] uint32_t txrx_rx_soft_rst : 1; // [1] uint32_t coeff_soft_rst : 1; // [2] uint32_t ldtc_soft_rst : 1; // [3] uint32_t ldtc1_soft_rst : 1; // [4] uint32_t measpwr_soft_rst : 1; // [5] uint32_t iddet_soft_rst : 1; // [6] uint32_t otdoa_soft_rst : 1; // [7] uint32_t uldft_soft_rst : 1; // [8] uint32_t pusch_soft_rst : 1; // [9] uint32_t csirs_soft_rst : 1; // [10] uint32_t dlfft_soft_rst : 1; // [11] uint32_t rfad_soft_rst : 1; // [12] uint32_t rxcapt_soft_rst : 1; // [13] uint32_t hsdl_soft_rst : 1; // [14] uint32_t dbgio_soft_rst : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_SYS_CTRL_RSTCTRL_LTE_T; // lte_autogate_mode typedef union { uint32_t v; struct { uint32_t lte_autogate_mode : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_SYS_CTRL_LTE_AUTOGATE_MODE_T; // lte_autogate_en typedef union { uint32_t v; struct { uint32_t txrx_func_autogate_en : 1; // [0] uint32_t coeff_func_autogate_en : 1; // [1] uint32_t ldtc_func_autogate_en : 1; // [2] uint32_t ldtc1_func_autogate_en : 1; // [3] uint32_t measpwr_func_autogate_en : 1; // [4] uint32_t iddet_func_autogate_en : 1; // [5] uint32_t otdoa_func_autogate_en : 1; // [6] uint32_t uldft_func_autogate_en : 1; // [7] uint32_t pusch_func_autogate_en : 1; // [8] uint32_t csirs_func_autogate_en : 1; // [9] uint32_t dlfft_func_autogate_en : 1; // [10] uint32_t txrx_intf_autogate_en : 1; // [11] uint32_t coeff_intf_autogate_en : 1; // [12] uint32_t ldtc_intf_autogate_en : 1; // [13] uint32_t ldtc1_intf_autogate_en : 1; // [14] uint32_t measpwr_intf_autogate_en : 1; // [15] uint32_t iddet_intf_autogate_en : 1; // [16] uint32_t otdoa_intf_autogate_en : 1; // [17] uint32_t uldft_intf_autogate_en : 1; // [18] uint32_t pusch_intf_autogate_en : 1; // [19] uint32_t csirs_intf_autogate_en : 1; // [20] uint32_t dlfft_intf_autogate_en : 1; // [21] uint32_t __23_22 : 2; // [23:22] uint32_t downlink_func_autogate_en : 1; // [24] uint32_t uplink_func_autogate_en : 1; // [25] uint32_t downlink_intf_autogate_en : 1; // [26] uint32_t uplink_intf_autogate_en : 1; // [27] uint32_t __31_28 : 4; // [31:28] } b; } REG_SYS_CTRL_LTE_AUTOGATE_EN_T; // lte_autogate_delay_num typedef union { uint32_t v; struct { uint32_t lte_autogate_delay_number : 8; // [7:0] uint32_t __31_8 : 24; // [31:8] } b; } REG_SYS_CTRL_LTE_AUTOGATE_DELAY_NUM_T; // aon_lpc_ctrl typedef union { uint32_t v; struct { uint32_t lpc_en : 1; // [0] uint32_t lpc_frc_en : 1; // [1] uint32_t __7_2 : 6; // [7:2] uint32_t lpc_pu_num : 8; // [15:8] uint32_t lpc_pd_num : 16; // [31:16] } b; } REG_SYS_CTRL_AON_LPC_CTRL_T; // aon_clock_en0 typedef union { uint32_t v; struct { uint32_t aon_ahb_matrix_en : 1; // [0] uint32_t aon_ahbmux_en : 1; // [1] uint32_t aon2lps_en : 1; // [2] uint32_t lps2aon_en : 1; // [3] uint32_t aon_imem_en : 1; // [4] uint32_t spinlock_en : 1; // [5] uint32_t efuse_ctrl_en : 1; // [6] uint32_t adimst_en : 1; // [7] uint32_t aon2pub_en : 1; // [8] uint32_t aonifc_en : 1; // [9] uint32_t lpsifc_en : 1; // [10] uint32_t gpt2_en : 1; // [11] uint32_t aud2ad_en : 1; // [12] uint32_t spi2_en : 1; // [13] uint32_t gpio2_en : 1; // [14] uint32_t mon_ctrl_en : 1; // [15] uint32_t aif_en : 1; // [16] uint32_t idle_timer_en : 1; // [17] uint32_t uart2_en : 1; // [18] uint32_t uart3_en : 1; // [19] uint32_t dbg_host_en : 1; // [20] uint32_t funcdma_en : 1; // [21] uint32_t dap_en : 1; // [22] uint32_t gnss_32k_en : 1; // [23] uint32_t usb_32k_en : 1; // [24] uint32_t sdio_1x_ap_en : 1; // [25] uint32_t sdio_1x_lte_en : 1; // [26] uint32_t sdio_aon_en : 1; // [27] uint32_t djtag_cfg_en : 1; // [28] uint32_t codec_mclock_en : 1; // [29] uint32_t clock_out_dbg_en : 1; // [30] uint32_t tsx_cal_en : 1; // [31] } b; } REG_SYS_CTRL_AON_CLOCK_EN0_T; // aon_clock_en1 typedef union { uint32_t v; struct { uint32_t djtag_tck_en : 1; // [0] uint32_t usb_ref_en : 1; // [1] uint32_t psram_en : 1; // [2] uint32_t aon_ahb_ap_en : 1; // [3] uint32_t aon_ahb_cp_en : 1; // [4] uint32_t aon_ahb_pub_en : 1; // [5] uint32_t aon_ahb_rf_en : 1; // [6] uint32_t calib_rc_en : 1; // [7] uint32_t fw_aon_en : 1; // [8] uint32_t scc_en : 1; // [9] uint32_t usb_ahb_usb_en : 1; // [10] uint32_t usb_ahb_ap_en : 1; // [11] uint32_t __31_12 : 20; // [31:12] } b; } REG_SYS_CTRL_AON_CLOCK_EN1_T; // aon_soft_rst_ctrl1 typedef union { uint32_t v; struct { uint32_t aon_djtag_soft_rst : 1; // [0] uint32_t ap_djtag_soft_rst : 1; // [1] uint32_t cp_djtag_soft_rst : 1; // [2] uint32_t rf_djtag_soft_rst : 1; // [3] uint32_t gnss_djtag_soft_rst : 1; // [4] uint32_t pub_djtag_soft_rst : 1; // [5] uint32_t lte_djtag_soft_rst : 1; // [6] uint32_t usb_djtag_soft_rst : 1; // [7] uint32_t emmc_phy_soft_rst : 1; // [8] uint32_t rc_calib_soft_rst : 1; // [9] uint32_t __31_10 : 22; // [31:10] } b; } REG_SYS_CTRL_AON_SOFT_RST_CTRL1_T; // mipi_csi_cfg_reg typedef union { uint32_t v; struct { uint32_t csi_lvds_mode_sel : 1; // [0] uint32_t lvds_rx_terminal_enable : 1; // [1] uint32_t __31_2 : 30; // [31:2] } b; } REG_SYS_CTRL_MIPI_CSI_CFG_REG_T; // cfg_clk_uart2 typedef union { uint32_t v; struct { uint32_t cfg_clk_uart2_num : 10; // [9:0] uint32_t __15_10 : 6; // [15:10] uint32_t cfg_clk_uart2_demod : 14; // [29:16] uint32_t __30_30 : 1; // [30] uint32_t cfg_clk_uart2_update : 1; // [31] } b; } REG_SYS_CTRL_CFG_CLK_UART2_T; // cfg_clk_uart3 typedef union { uint32_t v; struct { uint32_t cfg_clk_uart3_num : 10; // [9:0] uint32_t __15_10 : 6; // [15:10] uint32_t cfg_clk_uart3_demod : 14; // [29:16] uint32_t __30_30 : 1; // [30] uint32_t cfg_clk_uart3_update : 1; // [31] } b; } REG_SYS_CTRL_CFG_CLK_UART3_T; // cfg_clk_debug_host typedef union { uint32_t v; struct { uint32_t cfg_clk_debug_host_num : 10; // [9:0] uint32_t __15_10 : 6; // [15:10] uint32_t cfg_clk_debug_host_demod : 14; // [29:16] uint32_t __30_30 : 1; // [30] uint32_t cfg_clk_debug_host_update : 1; // [31] } b; } REG_SYS_CTRL_CFG_CLK_DEBUG_HOST_T; // rc_calib_ctrl typedef union { uint32_t v; struct { uint32_t rc_calib_en : 1; // [0] uint32_t rc_calib_int_en : 1; // [1] uint32_t rc_calib_int_clr : 1; // [2] uint32_t __31_3 : 29; // [31:3] } b; } REG_SYS_CTRL_RC_CALIB_CTRL_T; // emmc_slice_phy_ctrl typedef union { uint32_t v; struct { uint32_t emmc_module_sel : 1; // [0] uint32_t emmc_lte_slice_en : 1; // [1] uint32_t __31_2 : 30; // [31:2] } b; } REG_SYS_CTRL_EMMC_SLICE_PHY_CTRL_T; // dma_req_ctrl typedef union { uint32_t v; struct { uint32_t busmon_dma_sel : 1; // [0] uint32_t spi2_dma_sel : 1; // [1] uint32_t __31_2 : 30; // [31:2] } b; } REG_SYS_CTRL_DMA_REQ_CTRL_T; // apt_trigger_sel typedef union { uint32_t v; struct { uint32_t apt_trig_sel : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_SYS_CTRL_APT_TRIGGER_SEL_T; // ahb2ahb_ab_funcdma_ctrl typedef union { uint32_t v; struct { uint32_t funcdma_bridge_incr_r_byte : 2; // [1:0] uint32_t funcdma_bridge_incr_r_half : 2; // [3:2] uint32_t funcdma_bridge_incr_r_word : 2; // [5:4] uint32_t funcdma_bridge_pause_req : 1; // [6] uint32_t funcdma_bridge_sleep_req : 1; // [7] uint32_t funcdma_bridge_timeout_en : 1; // [8] uint32_t funcdma_bridge_mode : 1; // [9] uint32_t funcdma_bridge_bypass : 1; // [10] uint32_t funcdma_bridge_en : 1; // [11] uint32_t funcdma_bridge_s_valid : 1; // [12] uint32_t funcdma_bridge_s_endian_sel : 1; // [13] uint32_t funcdma_bridge_m_endian_sel : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_SYS_CTRL_AHB2AHB_AB_FUNCDMA_CTRL_T; // ahb2ahb_ab_funcdma_sts typedef union { uint32_t v; struct { uint32_t funcdma_bridge_sts_m_st : 2; // [1:0], read only uint32_t funcdma_bridge_pause_ready : 1; // [2], read only uint32_t funcdma_bridge_sleep_ready : 1; // [3], read only uint32_t funcdma_bridge_sts_m_idle : 1; // [4], read only uint32_t funcdma_bridge_sts_m_rfifo_empty : 1; // [5], read only uint32_t funcdma_bridge_sts_m_rfifo_full : 1; // [6], read only uint32_t funcdma_bridge_sts_m_cmdfifo_empty : 1; // [7], read only uint32_t funcdma_bridge_sts_m_cmdfifo_full : 1; // [8], read only uint32_t funcdma_bridge_sts_s_idle : 1; // [9], read only uint32_t funcdma_bridge_sts_s_rfifo_empty : 1; // [10], read only uint32_t funcdma_bridge_sts_s_rfifo_full : 1; // [11], read only uint32_t funcdma_bridge_sts_s_cmdfifo_empty : 1; // [12], read only uint32_t funcdma_bridge_sts_s_cmdfifo_full : 1; // [13], read only uint32_t __31_14 : 18; // [31:14] } b; } REG_SYS_CTRL_AHB2AHB_AB_FUNCDMA_STS_T; // ahb2ahb_ab_dap_ctrl typedef union { uint32_t v; struct { uint32_t dap_bridge_incr_r_byte : 2; // [1:0] uint32_t dap_bridge_incr_r_half : 2; // [3:2] uint32_t dap_bridge_incr_r_word : 2; // [5:4] uint32_t dap_bridge_pause_req : 1; // [6] uint32_t dap_bridge_sleep_req : 1; // [7] uint32_t dap_bridge_timeout_en : 1; // [8] uint32_t dap_bridge_mode : 1; // [9] uint32_t dap_bridge_bypass : 1; // [10] uint32_t dap_bridge_en : 1; // [11] uint32_t dap_bridge_s_valid : 1; // [12] uint32_t dap_bridge_s_endian_sel : 1; // [13] uint32_t dap_bridge_m_endian_sel : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_SYS_CTRL_AHB2AHB_AB_DAP_CTRL_T; // ahb2ahb_ab_dap_sts typedef union { uint32_t v; struct { uint32_t dap_bridge_sts_m_st : 2; // [1:0], read only uint32_t dap_bridge_pause_ready : 1; // [2], read only uint32_t dap_bridge_sleep_ready : 1; // [3], read only uint32_t dap_bridge_sts_m_idle : 1; // [4], read only uint32_t dap_bridge_sts_m_rfifo_empty : 1; // [5], read only uint32_t dap_bridge_sts_m_rfifo_full : 1; // [6], read only uint32_t dap_bridge_sts_m_cmdfifo_empty : 1; // [7], read only uint32_t dap_bridge_sts_m_cmdfifo_full : 1; // [8], read only uint32_t dap_bridge_sts_s_idle : 1; // [9], read only uint32_t dap_bridge_sts_s_rfifo_empty : 1; // [10], read only uint32_t dap_bridge_sts_s_rfifo_full : 1; // [11], read only uint32_t dap_bridge_sts_s_cmdfifo_empty : 1; // [12], read only uint32_t dap_bridge_sts_s_cmdfifo_full : 1; // [13], read only uint32_t __31_14 : 18; // [31:14] } b; } REG_SYS_CTRL_AHB2AHB_AB_DAP_STS_T; // ahb2axi_pub_ctrl typedef union { uint32_t v; struct { uint32_t ahb2axi_pub_mclk_next_on : 1; // [0] uint32_t ahb2axi_pub_sclk_next_on : 1; // [1] uint32_t ahb2axi_pub_clk_auto_gate_en : 1; // [2] uint32_t ahb2axi_pub_slv_disable_req : 1; // [3] uint32_t ahb2axi_pub_nonbuf_early_reqp_en : 1; // [4] uint32_t ahb2axi_pub_trans_fencing_req : 1; // [5] uint32_t __31_6 : 26; // [31:6] } b; } REG_SYS_CTRL_AHB2AXI_PUB_CTRL_T; // ahb2axi_pub_sts typedef union { uint32_t v; struct { uint32_t ahb2axi_pub_slv_disable_ack : 1; // [0], read only uint32_t ahb2axi_pub_bus_busy : 1; // [1], read only uint32_t ahb2axi_pub_trans_fencing_ack : 1; // [2], read only uint32_t ahb2axi_pub_mclk_req : 1; // [3], read only uint32_t __31_4 : 28; // [31:4] } b; } REG_SYS_CTRL_AHB2AXI_PUB_STS_T; // axi2axi_pub_sts_0 typedef union { uint32_t v; struct { uint32_t axi2axi_pub_axi_detector_overflow : 1; // [0], read only uint32_t axi2axi_pub_pwr_handshk_clk_req : 1; // [1], read only uint32_t axi2axi_pub_bridge_trans_idle : 1; // [2], read only uint32_t __31_3 : 29; // [31:3] } b; } REG_SYS_CTRL_AXI2AXI_PUB_STS_0_T; // ahb2ahb_ab_aon2lps_ctrl typedef union { uint32_t v; struct { uint32_t ahb2ahb_ab_aon2lps_slv_disable_req : 1; // [0] uint32_t ahb2ahb_ab_aon2lps_nonbuf_early_resp_en : 1; // [1] uint32_t ahb2ahb_ab_aon2lps_sync_mode : 1; // [2] uint32_t ahb2ahb_ab_aon2lps_fifo_clr : 1; // [3] uint32_t ahb2ahb_ab_aon2lps_mclk_auto_gate_en : 1; // [4] uint32_t ahb2ahb_ab_aon2lps_sclk_auto_gate_en : 1; // [5] uint32_t ahb2ahb_ab_aon2lps_trans_fencing_req : 1; // [6] uint32_t __31_7 : 25; // [31:7] } b; } REG_SYS_CTRL_AHB2AHB_AB_AON2LPS_CTRL_T; // ahb2ahb_ab_aon2lps_sts typedef union { uint32_t v; struct { uint32_t ahb2ahb_ab_aon2lps_slv_disable_ack : 1; // [0], read only uint32_t ahb2ahb_ab_aon2lps_m_bus_busy : 1; // [1], read only uint32_t ahb2ahb_ab_aon2lps_mclk_req : 1; // [2], read only uint32_t ahb2ahb_ab_aon2lps_sclk_req : 1; // [3], read only uint32_t ahb2ahb_ab_aon2lps_s_bus_busy : 1; // [4], read only uint32_t ahb2ahb_ab_aon2lps_trans_fencing_ack : 1; // [5], read only uint32_t __31_6 : 26; // [31:6] } b; } REG_SYS_CTRL_AHB2AHB_AB_AON2LPS_STS_T; // ahb2ahb_ab_lps2aon_ctrl typedef union { uint32_t v; struct { uint32_t ahb2ahb_ab_lps2aon_slv_disable_req : 1; // [0] uint32_t ahb2ahb_ab_lps2aon_nonbuf_early_resp_en : 1; // [1] uint32_t ahb2ahb_ab_lps2aon_sync_mode : 1; // [2] uint32_t ahb2ahb_ab_lps2aon_fifo_clr : 1; // [3] uint32_t ahb2ahb_ab_lps2aon_mclk_auto_gate_en : 1; // [4] uint32_t ahb2ahb_ab_lps2aon_sclk_auto_gate_en : 1; // [5] uint32_t ahb2ahb_ab_lps2aon_trans_fencing_req : 1; // [6] uint32_t __31_7 : 25; // [31:7] } b; } REG_SYS_CTRL_AHB2AHB_AB_LPS2AON_CTRL_T; // ahb2ahb_ab_lps2aon_sts typedef union { uint32_t v; struct { uint32_t ahb2ahb_ab_lps2aon_slv_disable_ack : 1; // [0], read only uint32_t ahb2ahb_ab_lps2aon_m_bus_busy : 1; // [1], read only uint32_t ahb2ahb_ab_lps2aon_mclk_req : 1; // [2], read only uint32_t ahb2ahb_ab_lps2aon_sclk_req : 1; // [3], read only uint32_t ahb2ahb_ab_lps2aon_s_bus_busy : 1; // [4], read only uint32_t ahb2ahb_ab_lps2aon_trans_fencing_ack : 1; // [5], read only uint32_t __31_6 : 26; // [31:6] } b; } REG_SYS_CTRL_AHB2AHB_AB_LPS2AON_STS_T; // sysctrl_reg0 typedef union { uint32_t v; struct { uint32_t spiflash2_nand_sel : 1; // [0] uint32_t ptest_func_atspeed_sel : 1; // [1] uint32_t exit_suspend_wait_xtal26m : 1; // [2] uint32_t usb20_vbus_valid_sw : 1; // [3] uint32_t usb20_vbus_valid_sel : 1; // [4] uint32_t usb20_iddig : 1; // [5] uint32_t usb20_con_testmode : 1; // [6] uint32_t usb20_utmi_width_sel : 1; // [7] uint32_t aud_sclk_o_pn_sel : 1; // [8] uint32_t apll_ref_en : 1; // [9] uint32_t mpll_ref_en : 1; // [10] uint32_t iis_pll_ref_en : 1; // [11] uint32_t pmic_26m_en : 1; // [12] uint32_t rf_idle_enable : 1; // [13] uint32_t __31_14 : 18; // [31:14] } b; } REG_SYS_CTRL_SYSCTRL_REG0_T; // plls_sts typedef union { uint32_t v; struct { uint32_t apll_state : 3; // [2:0], read only uint32_t __3_3 : 1; // [3] uint32_t mpll_state : 3; // [6:4], read only uint32_t __7_7 : 1; // [7] uint32_t iispll_state : 3; // [10:8], read only uint32_t __31_11 : 21; // [31:11] } b; } REG_SYS_CTRL_PLLS_STS_T; // cfg_aon_anti_hang typedef union { uint32_t v; struct { uint32_t aon_ahbmux_err_resp_en : 1; // [0] uint32_t aon_apbmux_err_resp_en : 1; // [1] uint32_t aonifc_err_resp_en : 1; // [2] uint32_t lpsifc_err_resp_en : 1; // [3] uint32_t aon2pub_slv_disable_req_force : 1; // [4] uint32_t aon2pub_slv_disable_req_sel : 1; // [5] uint32_t lte_err_resp_en : 1; // [6] uint32_t aon2ap_err_resp_en : 1; // [7] uint32_t aon2cp_err_resp_en : 1; // [8] uint32_t aon2rf_err_resp_en : 1; // [9] uint32_t aon2ap_slv_disable_req_force : 1; // [10] uint32_t aon2ap_slv_disable_req_sel : 1; // [11] uint32_t aon2cp_slv_disable_req_force : 1; // [12] uint32_t aon2cp_slv_disable_req_sel : 1; // [13] uint32_t aon2rf_slv_disable_req_force : 1; // [14] uint32_t aon2rf_slv_disable_req_sel : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_SYS_CTRL_CFG_AON_ANTI_HANG_T; // cfg_aon_qos typedef union { uint32_t v; struct { uint32_t awqos_aon : 4; // [3:0] uint32_t arqos_aon : 4; // [7:4] uint32_t __31_8 : 24; // [31:8] } b; } REG_SYS_CTRL_CFG_AON_QOS_T; // aon_ahb_mtx_slice_autogate_en typedef union { uint32_t v; struct { uint32_t aon_ahb_mtx_slice_s0_auto_gate_en : 1; // [0] uint32_t aon_ahb_mtx_slice_s1_auto_gate_en : 1; // [1] uint32_t aon_ahb_mtx_slice_s2_auto_gate_en : 1; // [2] uint32_t aon_ahb_mtx_slice_s3_auto_gate_en : 1; // [3] uint32_t aon_ahb_mtx_slice_s4_auto_gate_en : 1; // [4] uint32_t aon_ahb_mtx_slice_s5_auto_gate_en : 1; // [5] uint32_t aon_ahb_mtx_slice_m0_auto_gate_en : 1; // [6] uint32_t aon_ahb_mtx_slice_m1_auto_gate_en : 1; // [7] uint32_t aon_ahb_mtx_slice_m2_auto_gate_en : 1; // [8] uint32_t aon_ahb_mtx_slice_m3_auto_gate_en : 1; // [9] uint32_t aon_ahb_mtx_slice_m4_auto_gate_en : 1; // [10] uint32_t aon_ahb_mtx_slice_m5_auto_gate_en : 1; // [11] uint32_t __31_12 : 20; // [31:12] } b; } REG_SYS_CTRL_AON_AHB_MTX_SLICE_AUTOGATE_EN_T; // dap_djtag_en_cfg typedef union { uint32_t v; struct { uint32_t dap_djtag_en : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_SYS_CTRL_DAP_DJTAG_EN_CFG_T; // lte_ahb2ahb_sync_cfg typedef union { uint32_t v; struct { uint32_t dma2phy_wr_early_resp_en : 1; // [0] uint32_t dma2phy_auto_gating_en : 1; // [1] uint32_t cpu2phy_wr_early_resp_en : 1; // [2] uint32_t cpu2phy_auto_gating_en : 1; // [3] uint32_t __31_4 : 28; // [31:4] } b; } REG_SYS_CTRL_LTE_AHB2AHB_SYNC_CFG_T; // aon_soft_rst_ctrl0 #define SYS_CTRL_AHBMUX_SOFT_RST (1 << 0) #define SYS_CTRL_AHB2AXI_SOFT_RST (1 << 1) #define SYS_CTRL_ASYNC_BRIDGE_SOFT_RST (1 << 2) #define SYS_CTRL_DAP_SOFT_RST (1 << 3) #define SYS_CTRL_DJTAG_CTRL_SOFT_RST (1 << 4) #define SYS_CTRL_EFUSE_SOFT_RST (1 << 5) #define SYS_CTRL_LPS_IFC_SOFT_RST (1 << 6) #define SYS_CTRL_AON2LPS_SOFT_RST (1 << 7) #define SYS_CTRL_LPS2AON_SOFT_RST (1 << 8) #define SYS_CTRL_ADIMST_SOFT_RST (1 << 9) #define SYS_CTRL_SPINLOCK_SOFT_RST (1 << 10) #define SYS_CTRL_AON_IFC_SOFT_RST (1 << 11) #define SYS_CTRL_DBG_HOST_SOFT_RST (1 << 12) #define SYS_CTRL_AIF_SOFT_RST (1 << 13) #define SYS_CTRL_UART2_SOFT_RST (1 << 14) #define SYS_CTRL_UART3_SOFT_RST (1 << 15) #define SYS_CTRL_IDLE_TIMER_SOFT_RST (1 << 16) #define SYS_CTRL_AUD_2AD_SOFT_RST (1 << 17) #define SYS_CTRL_GPIO2_SOFT_RST (1 << 18) #define SYS_CTRL_GPT2_SOFT_RST (1 << 19) #define SYS_CTRL_I2C3_SOFT_RST (1 << 20) #define SYS_CTRL_MON_CTRL_SOFT_RST (1 << 21) #define SYS_CTRL_SYSMAIL_SOFT_RST (1 << 22) #define SYS_CTRL_SPI2_SOFT_RST (1 << 23) #define SYS_CTRL_IOMUX_SOFT_RST (1 << 24) #define SYS_CTRL_AON_IMEM_SOFT_RST (1 << 25) #define SYS_CTRL_ANA_WRAP1_SOFT_RST (1 << 26) #define SYS_CTRL_ANA_WRAP2_SOFT_RST (1 << 27) #define SYS_CTRL_USBPHY_SOFT_RST (1 << 28) #define SYS_CTRL_SCC_SOFT_RST (1 << 29) // clken_lte #define SYS_CTRL_TXRX_FUNC_EN (1 << 0) #define SYS_CTRL_COEFF_FUNC_EN (1 << 1) #define SYS_CTRL_LDTC_FUNC_EN (1 << 2) #define SYS_CTRL_LDTC1_FUNC_EN (1 << 3) #define SYS_CTRL_MEASPWR_FUNC_EN (1 << 4) #define SYS_CTRL_IDDET_FUNC_EN (1 << 5) #define SYS_CTRL_OTDOA_FUNC_EN (1 << 6) #define SYS_CTRL_ULDFT_FUNC_EN (1 << 7) #define SYS_CTRL_PUSCH_FUNC_EN (1 << 8) #define SYS_CTRL_CSIRS_FUNC_EN (1 << 9) #define SYS_CTRL_DLFFT_FUNC_EN (1 << 10) #define SYS_CTRL_RFAD_FUNC_EN (1 << 11) #define SYS_CTRL_RXCAPT_FUNC_EN (1 << 12) #define SYS_CTRL_HSDL_FUNC_EN (1 << 13) #define SYS_CTRL_DBGIO_FUNC_EN (1 << 14) // clken_lte_intf #define SYS_CTRL_TXRX_INTF_EN (1 << 0) #define SYS_CTRL_COEFF_INTF_EN (1 << 1) #define SYS_CTRL_LDTC_INTF_EN (1 << 2) #define SYS_CTRL_LDTC1_INTF_EN (1 << 3) #define SYS_CTRL_MEASPWR_INTF_EN (1 << 4) #define SYS_CTRL_IDDET_INTF_EN (1 << 5) #define SYS_CTRL_OTDOA_INTF_EN (1 << 6) #define SYS_CTRL_ULDFT_INTF_EN (1 << 7) #define SYS_CTRL_PUSCH_INTF_EN (1 << 8) #define SYS_CTRL_CSIRS_INTF_EN (1 << 9) #define SYS_CTRL_DLFFT_INTF_EN (1 << 10) #define SYS_CTRL_RFAD_INTF_EN (1 << 11) #define SYS_CTRL_RXCAPT_INTF_EN (1 << 12) #define SYS_CTRL_HSDL_INTF_EN (1 << 13) #define SYS_CTRL_DBGIO_INTF_EN (1 << 14) // rstctrl_lte #define SYS_CTRL_TXRX_TX_SOFT_RST (1 << 0) #define SYS_CTRL_TXRX_RX_SOFT_RST (1 << 1) #define SYS_CTRL_COEFF_SOFT_RST (1 << 2) #define SYS_CTRL_LDTC_SOFT_RST (1 << 3) #define SYS_CTRL_LDTC1_SOFT_RST (1 << 4) #define SYS_CTRL_MEASPWR_SOFT_RST (1 << 5) #define SYS_CTRL_IDDET_SOFT_RST (1 << 6) #define SYS_CTRL_OTDOA_SOFT_RST (1 << 7) #define SYS_CTRL_ULDFT_SOFT_RST (1 << 8) #define SYS_CTRL_PUSCH_SOFT_RST (1 << 9) #define SYS_CTRL_CSIRS_SOFT_RST (1 << 10) #define SYS_CTRL_DLFFT_SOFT_RST (1 << 11) #define SYS_CTRL_RFAD_SOFT_RST (1 << 12) #define SYS_CTRL_RXCAPT_SOFT_RST (1 << 13) #define SYS_CTRL_HSDL_SOFT_RST (1 << 14) #define SYS_CTRL_DBGIO_SOFT_RST (1 << 15) // lte_autogate_mode #define SYS_CTRL_LTE_AUTOGATE_MODE (1 << 0) // lte_autogate_en #define SYS_CTRL_TXRX_FUNC_AUTOGATE_EN (1 << 0) #define SYS_CTRL_COEFF_FUNC_AUTOGATE_EN (1 << 1) #define SYS_CTRL_LDTC_FUNC_AUTOGATE_EN (1 << 2) #define SYS_CTRL_LDTC1_FUNC_AUTOGATE_EN (1 << 3) #define SYS_CTRL_MEASPWR_FUNC_AUTOGATE_EN (1 << 4) #define SYS_CTRL_IDDET_FUNC_AUTOGATE_EN (1 << 5) #define SYS_CTRL_OTDOA_FUNC_AUTOGATE_EN (1 << 6) #define SYS_CTRL_ULDFT_FUNC_AUTOGATE_EN (1 << 7) #define SYS_CTRL_PUSCH_FUNC_AUTOGATE_EN (1 << 8) #define SYS_CTRL_CSIRS_FUNC_AUTOGATE_EN (1 << 9) #define SYS_CTRL_DLFFT_FUNC_AUTOGATE_EN (1 << 10) #define SYS_CTRL_TXRX_INTF_AUTOGATE_EN (1 << 11) #define SYS_CTRL_COEFF_INTF_AUTOGATE_EN (1 << 12) #define SYS_CTRL_LDTC_INTF_AUTOGATE_EN (1 << 13) #define SYS_CTRL_LDTC1_INTF_AUTOGATE_EN (1 << 14) #define SYS_CTRL_MEASPWR_INTF_AUTOGATE_EN (1 << 15) #define SYS_CTRL_IDDET_INTF_AUTOGATE_EN (1 << 16) #define SYS_CTRL_OTDOA_INTF_AUTOGATE_EN (1 << 17) #define SYS_CTRL_ULDFT_INTF_AUTOGATE_EN (1 << 18) #define SYS_CTRL_PUSCH_INTF_AUTOGATE_EN (1 << 19) #define SYS_CTRL_CSIRS_INTF_AUTOGATE_EN (1 << 20) #define SYS_CTRL_DLFFT_INTF_AUTOGATE_EN (1 << 21) #define SYS_CTRL_DOWNLINK_FUNC_AUTOGATE_EN (1 << 24) #define SYS_CTRL_UPLINK_FUNC_AUTOGATE_EN (1 << 25) #define SYS_CTRL_DOWNLINK_INTF_AUTOGATE_EN (1 << 26) #define SYS_CTRL_UPLINK_INTF_AUTOGATE_EN (1 << 27) // lte_autogate_delay_num #define SYS_CTRL_LTE_AUTOGATE_DELAY_NUMBER(n) (((n)&0xff) << 0) // aon_lpc_ctrl #define SYS_CTRL_LPC_EN (1 << 0) #define SYS_CTRL_LPC_FRC_EN (1 << 1) #define SYS_CTRL_LPC_PU_NUM(n) (((n)&0xff) << 8) #define SYS_CTRL_LPC_PD_NUM(n) (((n)&0xffff) << 16) // aon_clock_en0 #define SYS_CTRL_AON_AHB_MATRIX_EN (1 << 0) #define SYS_CTRL_AON_AHBMUX_EN (1 << 1) #define SYS_CTRL_AON2LPS_EN (1 << 2) #define SYS_CTRL_LPS2AON_EN (1 << 3) #define SYS_CTRL_AON_IMEM_EN (1 << 4) #define SYS_CTRL_SPINLOCK_EN (1 << 5) #define SYS_CTRL_EFUSE_CTRL_EN (1 << 6) #define SYS_CTRL_ADIMST_EN (1 << 7) #define SYS_CTRL_AON2PUB_EN (1 << 8) #define SYS_CTRL_AONIFC_EN (1 << 9) #define SYS_CTRL_LPSIFC_EN (1 << 10) #define SYS_CTRL_GPT2_EN (1 << 11) #define SYS_CTRL_AUD2AD_EN (1 << 12) #define SYS_CTRL_SPI2_EN (1 << 13) #define SYS_CTRL_GPIO2_EN (1 << 14) #define SYS_CTRL_MON_CTRL_EN (1 << 15) #define SYS_CTRL_AIF_EN (1 << 16) #define SYS_CTRL_IDLE_TIMER_EN (1 << 17) #define SYS_CTRL_UART2_EN (1 << 18) #define SYS_CTRL_UART3_EN (1 << 19) #define SYS_CTRL_DBG_HOST_EN (1 << 20) #define SYS_CTRL_FUNCDMA_EN (1 << 21) #define SYS_CTRL_DAP_EN (1 << 22) #define SYS_CTRL_GNSS_32K_EN (1 << 23) #define SYS_CTRL_USB_32K_EN (1 << 24) #define SYS_CTRL_SDIO_1X_AP_EN (1 << 25) #define SYS_CTRL_SDIO_1X_LTE_EN (1 << 26) #define SYS_CTRL_SDIO_AON_EN (1 << 27) #define SYS_CTRL_DJTAG_CFG_EN (1 << 28) #define SYS_CTRL_CODEC_MCLOCK_EN (1 << 29) #define SYS_CTRL_CLOCK_OUT_DBG_EN (1 << 30) #define SYS_CTRL_TSX_CAL_EN (1 << 31) // aon_clock_en1 #define SYS_CTRL_DJTAG_TCK_EN (1 << 0) #define SYS_CTRL_USB_REF_EN (1 << 1) #define SYS_CTRL_PSRAM_EN (1 << 2) #define SYS_CTRL_AON_AHB_AP_EN (1 << 3) #define SYS_CTRL_AON_AHB_CP_EN (1 << 4) #define SYS_CTRL_AON_AHB_PUB_EN (1 << 5) #define SYS_CTRL_AON_AHB_RF_EN (1 << 6) #define SYS_CTRL_CALIB_RC_EN (1 << 7) #define SYS_CTRL_FW_AON_EN (1 << 8) #define SYS_CTRL_SCC_EN (1 << 9) #define SYS_CTRL_USB_AHB_USB_EN (1 << 10) #define SYS_CTRL_USB_AHB_AP_EN (1 << 11) // aon_soft_rst_ctrl1 #define SYS_CTRL_AON_DJTAG_SOFT_RST (1 << 0) #define SYS_CTRL_AP_DJTAG_SOFT_RST (1 << 1) #define SYS_CTRL_CP_DJTAG_SOFT_RST (1 << 2) #define SYS_CTRL_RF_DJTAG_SOFT_RST (1 << 3) #define SYS_CTRL_GNSS_DJTAG_SOFT_RST (1 << 4) #define SYS_CTRL_PUB_DJTAG_SOFT_RST (1 << 5) #define SYS_CTRL_LTE_DJTAG_SOFT_RST (1 << 6) #define SYS_CTRL_USB_DJTAG_SOFT_RST (1 << 7) #define SYS_CTRL_EMMC_PHY_SOFT_RST (1 << 8) #define SYS_CTRL_RC_CALIB_SOFT_RST (1 << 9) // mipi_csi_cfg_reg #define SYS_CTRL_CSI_LVDS_MODE_SEL (1 << 0) #define SYS_CTRL_LVDS_RX_TERMINAL_ENABLE (1 << 1) // cfg_clk_uart2 #define SYS_CTRL_CFG_CLK_UART2_NUM(n) (((n)&0x3ff) << 0) #define SYS_CTRL_CFG_CLK_UART2_DEMOD(n) (((n)&0x3fff) << 16) #define SYS_CTRL_CFG_CLK_UART2_UPDATE (1 << 31) // cfg_clk_uart3 #define SYS_CTRL_CFG_CLK_UART3_NUM(n) (((n)&0x3ff) << 0) #define SYS_CTRL_CFG_CLK_UART3_DEMOD(n) (((n)&0x3fff) << 16) #define SYS_CTRL_CFG_CLK_UART3_UPDATE (1 << 31) // cfg_clk_debug_host #define SYS_CTRL_CFG_CLK_DEBUG_HOST_NUM(n) (((n)&0x3ff) << 0) #define SYS_CTRL_CFG_CLK_DEBUG_HOST_DEMOD(n) (((n)&0x3fff) << 16) #define SYS_CTRL_CFG_CLK_DEBUG_HOST_UPDATE (1 << 31) // rc_calib_ctrl #define SYS_CTRL_RC_CALIB_EN (1 << 0) #define SYS_CTRL_RC_CALIB_INT_EN (1 << 1) #define SYS_CTRL_RC_CALIB_INT_CLR (1 << 2) // emmc_slice_phy_ctrl #define SYS_CTRL_EMMC_MODULE_SEL (1 << 0) #define SYS_CTRL_EMMC_LTE_SLICE_EN (1 << 1) // dma_req_ctrl #define SYS_CTRL_BUSMON_DMA_SEL (1 << 0) #define SYS_CTRL_SPI2_DMA_SEL (1 << 1) // apt_trigger_sel #define SYS_CTRL_APT_TRIG_SEL (1 << 0) // ahb2ahb_ab_funcdma_ctrl #define SYS_CTRL_FUNCDMA_BRIDGE_INCR_R_BYTE(n) (((n)&0x3) << 0) #define SYS_CTRL_FUNCDMA_BRIDGE_INCR_R_HALF(n) (((n)&0x3) << 2) #define SYS_CTRL_FUNCDMA_BRIDGE_INCR_R_WORD(n) (((n)&0x3) << 4) #define SYS_CTRL_FUNCDMA_BRIDGE_PAUSE_REQ (1 << 6) #define SYS_CTRL_FUNCDMA_BRIDGE_SLEEP_REQ (1 << 7) #define SYS_CTRL_FUNCDMA_BRIDGE_TIMEOUT_EN (1 << 8) #define SYS_CTRL_FUNCDMA_BRIDGE_MODE (1 << 9) #define SYS_CTRL_FUNCDMA_BRIDGE_BYPASS (1 << 10) #define SYS_CTRL_FUNCDMA_BRIDGE_EN (1 << 11) #define SYS_CTRL_FUNCDMA_BRIDGE_S_VALID (1 << 12) #define SYS_CTRL_FUNCDMA_BRIDGE_S_ENDIAN_SEL (1 << 13) #define SYS_CTRL_FUNCDMA_BRIDGE_M_ENDIAN_SEL (1 << 14) // ahb2ahb_ab_funcdma_sts #define SYS_CTRL_FUNCDMA_BRIDGE_STS_M_ST(n) (((n)&0x3) << 0) #define SYS_CTRL_FUNCDMA_BRIDGE_PAUSE_READY (1 << 2) #define SYS_CTRL_FUNCDMA_BRIDGE_SLEEP_READY (1 << 3) #define SYS_CTRL_FUNCDMA_BRIDGE_STS_M_IDLE (1 << 4) #define SYS_CTRL_FUNCDMA_BRIDGE_STS_M_RFIFO_EMPTY (1 << 5) #define SYS_CTRL_FUNCDMA_BRIDGE_STS_M_RFIFO_FULL (1 << 6) #define SYS_CTRL_FUNCDMA_BRIDGE_STS_M_CMDFIFO_EMPTY (1 << 7) #define SYS_CTRL_FUNCDMA_BRIDGE_STS_M_CMDFIFO_FULL (1 << 8) #define SYS_CTRL_FUNCDMA_BRIDGE_STS_S_IDLE (1 << 9) #define SYS_CTRL_FUNCDMA_BRIDGE_STS_S_RFIFO_EMPTY (1 << 10) #define SYS_CTRL_FUNCDMA_BRIDGE_STS_S_RFIFO_FULL (1 << 11) #define SYS_CTRL_FUNCDMA_BRIDGE_STS_S_CMDFIFO_EMPTY (1 << 12) #define SYS_CTRL_FUNCDMA_BRIDGE_STS_S_CMDFIFO_FULL (1 << 13) // ahb2ahb_ab_dap_ctrl #define SYS_CTRL_DAP_BRIDGE_INCR_R_BYTE(n) (((n)&0x3) << 0) #define SYS_CTRL_DAP_BRIDGE_INCR_R_HALF(n) (((n)&0x3) << 2) #define SYS_CTRL_DAP_BRIDGE_INCR_R_WORD(n) (((n)&0x3) << 4) #define SYS_CTRL_DAP_BRIDGE_PAUSE_REQ (1 << 6) #define SYS_CTRL_DAP_BRIDGE_SLEEP_REQ (1 << 7) #define SYS_CTRL_DAP_BRIDGE_TIMEOUT_EN (1 << 8) #define SYS_CTRL_DAP_BRIDGE_MODE (1 << 9) #define SYS_CTRL_DAP_BRIDGE_BYPASS (1 << 10) #define SYS_CTRL_DAP_BRIDGE_EN (1 << 11) #define SYS_CTRL_DAP_BRIDGE_S_VALID (1 << 12) #define SYS_CTRL_DAP_BRIDGE_S_ENDIAN_SEL (1 << 13) #define SYS_CTRL_DAP_BRIDGE_M_ENDIAN_SEL (1 << 14) // ahb2ahb_ab_dap_sts #define SYS_CTRL_DAP_BRIDGE_STS_M_ST(n) (((n)&0x3) << 0) #define SYS_CTRL_DAP_BRIDGE_PAUSE_READY (1 << 2) #define SYS_CTRL_DAP_BRIDGE_SLEEP_READY (1 << 3) #define SYS_CTRL_DAP_BRIDGE_STS_M_IDLE (1 << 4) #define SYS_CTRL_DAP_BRIDGE_STS_M_RFIFO_EMPTY (1 << 5) #define SYS_CTRL_DAP_BRIDGE_STS_M_RFIFO_FULL (1 << 6) #define SYS_CTRL_DAP_BRIDGE_STS_M_CMDFIFO_EMPTY (1 << 7) #define SYS_CTRL_DAP_BRIDGE_STS_M_CMDFIFO_FULL (1 << 8) #define SYS_CTRL_DAP_BRIDGE_STS_S_IDLE (1 << 9) #define SYS_CTRL_DAP_BRIDGE_STS_S_RFIFO_EMPTY (1 << 10) #define SYS_CTRL_DAP_BRIDGE_STS_S_RFIFO_FULL (1 << 11) #define SYS_CTRL_DAP_BRIDGE_STS_S_CMDFIFO_EMPTY (1 << 12) #define SYS_CTRL_DAP_BRIDGE_STS_S_CMDFIFO_FULL (1 << 13) // ahb2axi_pub_ctrl #define SYS_CTRL_AHB2AXI_PUB_MCLK_NEXT_ON (1 << 0) #define SYS_CTRL_AHB2AXI_PUB_SCLK_NEXT_ON (1 << 1) #define SYS_CTRL_AHB2AXI_PUB_CLK_AUTO_GATE_EN (1 << 2) #define SYS_CTRL_AHB2AXI_PUB_SLV_DISABLE_REQ (1 << 3) #define SYS_CTRL_AHB2AXI_PUB_NONBUF_EARLY_REQP_EN (1 << 4) #define SYS_CTRL_AHB2AXI_PUB_TRANS_FENCING_REQ (1 << 5) // ahb2axi_pub_sts #define SYS_CTRL_AHB2AXI_PUB_SLV_DISABLE_ACK (1 << 0) #define SYS_CTRL_AHB2AXI_PUB_BUS_BUSY (1 << 1) #define SYS_CTRL_AHB2AXI_PUB_TRANS_FENCING_ACK (1 << 2) #define SYS_CTRL_AHB2AXI_PUB_MCLK_REQ (1 << 3) // axi2axi_pub_sts_0 #define SYS_CTRL_AXI2AXI_PUB_AXI_DETECTOR_OVERFLOW (1 << 0) #define SYS_CTRL_AXI2AXI_PUB_PWR_HANDSHK_CLK_REQ (1 << 1) #define SYS_CTRL_AXI2AXI_PUB_BRIDGE_TRANS_IDLE (1 << 2) // ahb2ahb_ab_aon2lps_ctrl #define SYS_CTRL_AHB2AHB_AB_AON2LPS_SLV_DISABLE_REQ (1 << 0) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_NONBUF_EARLY_RESP_EN (1 << 1) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_SYNC_MODE (1 << 2) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_FIFO_CLR (1 << 3) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_MCLK_AUTO_GATE_EN (1 << 4) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_SCLK_AUTO_GATE_EN (1 << 5) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_TRANS_FENCING_REQ (1 << 6) // ahb2ahb_ab_aon2lps_sts #define SYS_CTRL_AHB2AHB_AB_AON2LPS_SLV_DISABLE_ACK (1 << 0) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_M_BUS_BUSY (1 << 1) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_MCLK_REQ (1 << 2) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_SCLK_REQ (1 << 3) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_S_BUS_BUSY (1 << 4) #define SYS_CTRL_AHB2AHB_AB_AON2LPS_TRANS_FENCING_ACK (1 << 5) // ahb2ahb_ab_lps2aon_ctrl #define SYS_CTRL_AHB2AHB_AB_LPS2AON_SLV_DISABLE_REQ (1 << 0) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_NONBUF_EARLY_RESP_EN (1 << 1) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_SYNC_MODE (1 << 2) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_FIFO_CLR (1 << 3) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_MCLK_AUTO_GATE_EN (1 << 4) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_SCLK_AUTO_GATE_EN (1 << 5) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_TRANS_FENCING_REQ (1 << 6) // ahb2ahb_ab_lps2aon_sts #define SYS_CTRL_AHB2AHB_AB_LPS2AON_SLV_DISABLE_ACK (1 << 0) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_M_BUS_BUSY (1 << 1) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_MCLK_REQ (1 << 2) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_SCLK_REQ (1 << 3) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_S_BUS_BUSY (1 << 4) #define SYS_CTRL_AHB2AHB_AB_LPS2AON_TRANS_FENCING_ACK (1 << 5) // sysctrl_reg0 #define SYS_CTRL_SPIFLASH2_NAND_SEL (1 << 0) #define SYS_CTRL_PTEST_FUNC_ATSPEED_SEL (1 << 1) #define SYS_CTRL_EXIT_SUSPEND_WAIT_XTAL26M (1 << 2) #define SYS_CTRL_USB20_VBUS_VALID_SW (1 << 3) #define SYS_CTRL_USB20_VBUS_VALID_SEL (1 << 4) #define SYS_CTRL_USB20_IDDIG (1 << 5) #define SYS_CTRL_USB20_CON_TESTMODE (1 << 6) #define SYS_CTRL_USB20_UTMI_WIDTH_SEL (1 << 7) #define SYS_CTRL_AUD_SCLK_O_PN_SEL (1 << 8) #define SYS_CTRL_APLL_REF_EN (1 << 9) #define SYS_CTRL_MPLL_REF_EN (1 << 10) #define SYS_CTRL_IIS_PLL_REF_EN (1 << 11) #define SYS_CTRL_PMIC_26M_EN (1 << 12) #define SYS_CTRL_RF_IDLE_ENABLE (1 << 13) // plls_sts #define SYS_CTRL_APLL_STATE(n) (((n)&0x7) << 0) #define SYS_CTRL_MPLL_STATE(n) (((n)&0x7) << 4) #define SYS_CTRL_IISPLL_STATE(n) (((n)&0x7) << 8) // cfg_aon_anti_hang #define SYS_CTRL_AON_AHBMUX_ERR_RESP_EN (1 << 0) #define SYS_CTRL_AON_APBMUX_ERR_RESP_EN (1 << 1) #define SYS_CTRL_AONIFC_ERR_RESP_EN (1 << 2) #define SYS_CTRL_LPSIFC_ERR_RESP_EN (1 << 3) #define SYS_CTRL_AON2PUB_SLV_DISABLE_REQ_FORCE (1 << 4) #define SYS_CTRL_AON2PUB_SLV_DISABLE_REQ_SEL (1 << 5) #define SYS_CTRL_LTE_ERR_RESP_EN (1 << 6) #define SYS_CTRL_AON2AP_ERR_RESP_EN (1 << 7) #define SYS_CTRL_AON2CP_ERR_RESP_EN (1 << 8) #define SYS_CTRL_AON2RF_ERR_RESP_EN (1 << 9) #define SYS_CTRL_AON2AP_SLV_DISABLE_REQ_FORCE (1 << 10) #define SYS_CTRL_AON2AP_SLV_DISABLE_REQ_SEL (1 << 11) #define SYS_CTRL_AON2CP_SLV_DISABLE_REQ_FORCE (1 << 12) #define SYS_CTRL_AON2CP_SLV_DISABLE_REQ_SEL (1 << 13) #define SYS_CTRL_AON2RF_SLV_DISABLE_REQ_FORCE (1 << 14) #define SYS_CTRL_AON2RF_SLV_DISABLE_REQ_SEL (1 << 15) // cfg_aon_qos #define SYS_CTRL_AWQOS_AON(n) (((n)&0xf) << 0) #define SYS_CTRL_ARQOS_AON(n) (((n)&0xf) << 4) // aon_ahb_mtx_slice_autogate_en #define SYS_CTRL_AON_AHB_MTX_SLICE_S0_AUTO_GATE_EN (1 << 0) #define SYS_CTRL_AON_AHB_MTX_SLICE_S1_AUTO_GATE_EN (1 << 1) #define SYS_CTRL_AON_AHB_MTX_SLICE_S2_AUTO_GATE_EN (1 << 2) #define SYS_CTRL_AON_AHB_MTX_SLICE_S3_AUTO_GATE_EN (1 << 3) #define SYS_CTRL_AON_AHB_MTX_SLICE_S4_AUTO_GATE_EN (1 << 4) #define SYS_CTRL_AON_AHB_MTX_SLICE_S5_AUTO_GATE_EN (1 << 5) #define SYS_CTRL_AON_AHB_MTX_SLICE_M0_AUTO_GATE_EN (1 << 6) #define SYS_CTRL_AON_AHB_MTX_SLICE_M1_AUTO_GATE_EN (1 << 7) #define SYS_CTRL_AON_AHB_MTX_SLICE_M2_AUTO_GATE_EN (1 << 8) #define SYS_CTRL_AON_AHB_MTX_SLICE_M3_AUTO_GATE_EN (1 << 9) #define SYS_CTRL_AON_AHB_MTX_SLICE_M4_AUTO_GATE_EN (1 << 10) #define SYS_CTRL_AON_AHB_MTX_SLICE_M5_AUTO_GATE_EN (1 << 11) // dap_djtag_en_cfg #define SYS_CTRL_DAP_DJTAG_EN (1 << 0) // lte_ahb2ahb_sync_cfg #define SYS_CTRL_DMA2PHY_WR_EARLY_RESP_EN (1 << 0) #define SYS_CTRL_DMA2PHY_AUTO_GATING_EN (1 << 1) #define SYS_CTRL_CPU2PHY_WR_EARLY_RESP_EN (1 << 2) #define SYS_CTRL_CPU2PHY_AUTO_GATING_EN (1 << 3) #endif // _SYS_CTRL_H_