/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _UL_DFT_H_ #define _UL_DFT_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_UL_DFT_BASE (0x18700000) typedef volatile struct { uint32_t dft_ctrl_next; // 0x00000000 uint32_t puc_mod_data_next; // 0x00000004 uint32_t srs_map_cfg_next; // 0x00000008 uint32_t srs_zc_len_next; // 0x0000000c uint32_t puc_map_cfg_next; // 0x00000010 uint32_t pus_map_cfg_next; // 0x00000014 uint32_t hard_para_next1; // 0x00000018 uint32_t hard_para__next2; // 0x0000001c uint32_t hard_para__next3; // 0x00000020 uint32_t ofdm_offset_next; // 0x00000024 uint32_t dft_fft_inten_next; // 0x00000028 uint32_t dft_fft_intf_next; // 0x0000002c uint32_t ofdm_zero_next; // 0x00000030 uint32_t dft_fft_ctrl_next; // 0x00000034 uint32_t fft_lnum_srs_next; // 0x00000038 uint32_t fft_lnum_scr_next; // 0x0000003c uint32_t npus_map_cfg_next; // 0x00000040 uint32_t npus_dmrs_cfg_next; // 0x00000044 uint32_t npra__cfg_next; // 0x00000048 uint32_t inout_para; // 0x0000004c uint32_t id_para; // 0x00000050 uint32_t pucch_dummy_id; // 0x00000054 uint32_t puc_rbmap_config; // 0x00000058 uint32_t sysband_config; // 0x0000005c uint32_t dftfft_launch; // 0x00000060 uint32_t dft_fft_sw_stop; // 0x00000064 uint32_t dft_fft_sw_stop_flag; // 0x00000068 uint32_t dft_ctrl_curr1; // 0x0000006c uint32_t puc_mod_data_curr1; // 0x00000070 uint32_t srs_map_cfg_curr1; // 0x00000074 uint32_t srs_zc_len_curr1; // 0x00000078 uint32_t puc_map_cfg_curr1; // 0x0000007c uint32_t pus_map_cfg_curr1; // 0x00000080 uint32_t hard_para_curr11; // 0x00000084 uint32_t hard_para__curr21; // 0x00000088 uint32_t hard_para__curr31; // 0x0000008c uint32_t ofdm_offset_curr1; // 0x00000090 uint32_t dft_fft_inten_curr1; // 0x00000094 uint32_t ofdm_zero_curr1; // 0x00000098 uint32_t dft_fft_ctrl_curr1; // 0x0000009c uint32_t fft_lnum_srs_curr1; // 0x000000a0 uint32_t fft_lnum_scr_curr1; // 0x000000a4 uint32_t npus_map_cfg_curr1; // 0x000000a8 uint32_t npus_dmrs_cfg_curr1; // 0x000000ac uint32_t npra__cfg_curr1; // 0x000000b0 uint32_t dft_ctrl_curr2; // 0x000000b4 uint32_t puc_mod_data_curr2; // 0x000000b8 uint32_t srs_map_cfg_curr2; // 0x000000bc uint32_t srs_zc_len_curr2; // 0x000000c0 uint32_t puc_map_cfg_curr2; // 0x000000c4 uint32_t pus_map_cfg_curr2; // 0x000000c8 uint32_t hard_para_curr12; // 0x000000cc uint32_t hard_para__curr22; // 0x000000d0 uint32_t hard_para__curr32; // 0x000000d4 uint32_t ofdm_offset_curr2; // 0x000000d8 uint32_t dft_fft_inten_curr2; // 0x000000dc uint32_t ofdm_zero_curr2; // 0x000000e0 uint32_t dft_fft_ctrl_curr2; // 0x000000e4 uint32_t fft_lnum_srs_curr2; // 0x000000e8 uint32_t fft_lnum_scr_curr2; // 0x000000ec uint32_t npus_map_cfg_curr2; // 0x000000f0 uint32_t npus_dmrs_cfg_curr2; // 0x000000f4 uint32_t npra__cfg_curr2; // 0x000000f8 uint32_t fsm_state; // 0x000000fc uint32_t ofdm_count; // 0x00000100 uint32_t fsm_state_assert; // 0x00000104 uint32_t ofdm_assert; // 0x00000108 uint32_t __268[957]; // 0x0000010c uint32_t uldft_mem1; // 0x00001000 uint32_t __4100[255]; // 0x00001004 uint32_t uldft_mem2; // 0x00001400 uint32_t __5124[255]; // 0x00001404 uint32_t uldft_mem3; // 0x00001800 uint32_t __6148[255]; // 0x00001804 uint32_t uldft_mem4; // 0x00001c00 uint32_t __7172[255]; // 0x00001c04 uint32_t uldft_mem5; // 0x00002000 uint32_t __8196[255]; // 0x00002004 uint32_t uldft_mem6; // 0x00002400 uint32_t __9220[255]; // 0x00002404 uint32_t uldft_mem7; // 0x00002800 uint32_t __10244[255]; // 0x00002804 uint32_t uldft_mem8; // 0x00002c00 uint32_t __11268[255]; // 0x00002c04 uint32_t uldft_mem9; // 0x00003000 uint32_t __12292[511]; // 0x00003004 uint32_t uldft_mem10; // 0x00003800 } HWP_UL_DFT_T; #define hwp_ulDft ((HWP_UL_DFT_T *)REG_ACCESS_ADDRESS(REG_UL_DFT_BASE)) // dft_ctrl_next typedef union { uint32_t v; struct { uint32_t dft_idft_sel_next : 1; // [0] uint32_t pus_mod_en_next : 1; // [1] uint32_t dft_en_next : 1; // [2] uint32_t pus_modu_sel_next : 2; // [4:3] uint32_t dft_npts_next : 6; // [10:5] uint32_t anti_drop_lnum_next : 1; // [11] uint32_t anti_drop_en_next : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_UL_DFT_DFT_CTRL_NEXT_T; // puc_mod_data_next typedef union { uint32_t v; struct { uint32_t puc_mod_data_next : 22; // [21:0] uint32_t __31_22 : 10; // [31:22] } b; } REG_UL_DFT_PUC_MOD_DATA_NEXT_T; // srs_map_cfg_next typedef union { uint32_t v; struct { uint32_t srs_map_start1_next : 7; // [6:0] uint32_t __7_7 : 1; // [7] uint32_t srs_map_start2_next : 7; // [14:8] uint32_t __15_15 : 1; // [15] uint32_t srs_map_len_next : 7; // [22:16] uint32_t __23_23 : 1; // [23] uint32_t k_tc_next : 2; // [25:24] uint32_t k_tc_num_next : 1; // [26] uint32_t __31_27 : 5; // [31:27] } b; } REG_UL_DFT_SRS_MAP_CFG_NEXT_T; // srs_zc_len_next typedef union { uint32_t v; struct { uint32_t srs_zc_len_next : 11; // [10:0] uint32_t __11_11 : 1; // [11] uint32_t special_frame_start_next : 4; // [15:12] uint32_t sra_map_ofdm1_next : 4; // [19:16] uint32_t srs_map_ofdm2_next : 4; // [23:20] uint32_t srs_num_next : 1; // [24] uint32_t __31_25 : 7; // [31:25] } b; } REG_UL_DFT_SRS_ZC_LEN_NEXT_T; // puc_map_cfg_next typedef union { uint32_t v; struct { uint32_t puc_map_start1_next : 7; // [6:0] uint32_t __7_7 : 1; // [7] uint32_t puc_map_start2_next : 7; // [14:8] uint32_t __15_15 : 1; // [15] uint32_t tx_nb_start1_next : 7; // [22:16] uint32_t __23_23 : 1; // [23] uint32_t tx_nb_start2_next : 7; // [30:24] uint32_t tx_fir_en_next : 1; // [31] } b; } REG_UL_DFT_PUC_MAP_CFG_NEXT_T; // pus_map_cfg_next typedef union { uint32_t v; struct { uint32_t pus_map_start1_next : 7; // [6:0] uint32_t __7_7 : 1; // [7] uint32_t pus_map_start2_next : 7; // [14:8] uint32_t __15_15 : 1; // [15] uint32_t pus_map_len1_next : 7; // [22:16] uint32_t __23_23 : 1; // [23] uint32_t pus_map_len2_next : 7; // [30:24] uint32_t pus_map_sel_next : 1; // [31] } b; } REG_UL_DFT_PUS_MAP_CFG_NEXT_T; // hard_para_next1 typedef union { uint32_t v; struct { uint32_t cyclic_shift_field_next : 3; // [2:0] uint32_t ta_overlap_next : 6; // [8:3] uint32_t seq_hop_flag_next : 1; // [9] uint32_t group_hop_flag_next : 1; // [10] uint32_t pucpus_shortened_mode_next : 4; // [14:11] uint32_t pus_dmrs_w_flag : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_UL_DFT_HARD_PARA_NEXT1_T; // hard_para__next2 typedef union { uint32_t v; struct { uint32_t delta_apc_scr_next : 16; // [15:0] uint32_t delta_apc_srs_next : 16; // [31:16] } b; } REG_UL_DFT_HARD_PARA__NEXT2_T; // hard_para__next3 typedef union { uint32_t v; struct { uint32_t nf_next : 10; // [9:0] uint32_t subframe_slot_cnt_next : 5; // [14:10] uint32_t __15_15 : 1; // [15] uint32_t srs_cycle_shift_next : 4; // [19:16] uint32_t n1_pucch_next : 12; // [31:20] } b; } REG_UL_DFT_HARD_PARA__NEXT3_T; // ofdm_offset_next typedef union { uint32_t v; struct { uint32_t ofdm_offset_first_next : 16; // [15:0] uint32_t ofdm_offset_last_next : 16; // [31:16] } b; } REG_UL_DFT_OFDM_OFFSET_NEXT_T; // dft_fft_inten_next typedef union { uint32_t v; struct { uint32_t dft_fft_inten0_next : 1; // [0] uint32_t dft_fft_inten1_next : 1; // [1] uint32_t dft_fft_inten2_next : 1; // [2] uint32_t dft_fft_inten3_next : 1; // [3] uint32_t dft_fft_inten4_next : 1; // [4] uint32_t dft_fft_inten5_next : 1; // [5] uint32_t dft_fft_inten6_next : 1; // [6] uint32_t dft_fft_inten7_next : 1; // [7] uint32_t dft_fft_inten8_next : 1; // [8] uint32_t dft_fft_inten9_next : 1; // [9] uint32_t dft_fft_inten10_next : 1; // [10] uint32_t dft_fft_inten11_next : 1; // [11] uint32_t dft_fft_inten12_next : 1; // [12] uint32_t dft_fft_inten13_next : 1; // [13] uint32_t dma_inten_next : 1; // [14] uint32_t err_inten_next : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_UL_DFT_DFT_FFT_INTEN_NEXT_T; // dft_fft_intf_next typedef union { uint32_t v; struct { uint32_t txrx_wr_errf : 1; // [0], write clear uint32_t pus_rd_errf : 1; // [1], write clear uint32_t dft_fft_intf0_next : 1; // [2], write clear uint32_t dft_fft_intf1_next : 1; // [3], write clear uint32_t dft_fft_intf2_next : 1; // [4], write clear uint32_t dft_fft_intf3_next : 1; // [5], write clear uint32_t dft_fft_intf4_next : 1; // [6], write clear uint32_t dft_fft_intf5_next : 1; // [7], write clear uint32_t dft_fft_intf6_next : 1; // [8], write clear uint32_t dft_fft_intf7_next : 1; // [9], write clear uint32_t dft_fft_intf8_next : 1; // [10], write clear uint32_t dft_fft_intf9_next : 1; // [11], write clear uint32_t dft_fft_intf10_next : 1; // [12], write clear uint32_t dft_fft_intf11_next : 1; // [13], write clear uint32_t dft_fft_intf12_next : 1; // [14], write clear uint32_t dft_fft_intf13_next : 1; // [15], write clear uint32_t __31_16 : 16; // [31:16] } b; } REG_UL_DFT_DFT_FFT_INTF_NEXT_T; // ofdm_zero_next typedef union { uint32_t v; struct { uint32_t ofdm_zero_next : 14; // [13:0] uint32_t __31_14 : 18; // [31:14] } b; } REG_UL_DFT_OFDM_ZERO_NEXT_T; // dft_fft_ctrl_next typedef union { uint32_t v; struct { uint32_t dftfft_irqen_next : 1; // [0] uint32_t fft_npts : 3; // [3:1] uint32_t chan_mode_next : 3; // [6:4] uint32_t __7_7 : 1; // [7] uint32_t pus_buf_sel_next : 2; // [9:8] uint32_t datadrive_en_next : 1; // [10] uint32_t __11_11 : 1; // [11] uint32_t ofdm_num_next : 4; // [15:12] uint32_t npusch_formatsel_next : 1; // [16] uint32_t pucch_format_sel_next : 3; // [19:17] uint32_t prach_format_sel_next : 3; // [22:20] uint32_t pwradj_en_next : 1; // [23] uint32_t fft_cal_next : 1; // [24] uint32_t fft_ifft_sel_next : 1; // [25] uint32_t clear_en_next : 1; // [26] uint32_t srs_en_next : 1; // [27] uint32_t launch_en_next : 1; // [28] uint32_t dft_trig_mode : 1; // [29] uint32_t dftfft_soft_start : 1; // [30] uint32_t __31_31 : 1; // [31] } b; } REG_UL_DFT_DFT_FFT_CTRL_NEXT_T; // fft_lnum_srs_next typedef union { uint32_t v; struct { uint32_t fft_lnum1_srs_next : 2; // [1:0] uint32_t fft_lnum2_srs_next : 2; // [3:2] uint32_t fft_lnum3_srs_next : 2; // [5:4] uint32_t fft_lnum4_srs_next : 2; // [7:6] uint32_t fft_lnum5_srs_next : 2; // [9:8] uint32_t fft_lnum6_srs_next : 2; // [11:10] uint32_t fft_lnum7_srs_next : 2; // [13:12] uint32_t fft_lnum8_srs_next : 2; // [15:14] uint32_t fft_lnum9_srs_next : 2; // [17:16] uint32_t fft_lnum10_srs_next : 2; // [19:18] uint32_t fft_lnum11_srs_next : 2; // [21:20] uint32_t __31_22 : 10; // [31:22] } b; } REG_UL_DFT_FFT_LNUM_SRS_NEXT_T; // fft_lnum_scr_next typedef union { uint32_t v; struct { uint32_t fft_lnum1_scr_next : 2; // [1:0] uint32_t fft_lnum2_scr_next : 2; // [3:2] uint32_t fft_lnum3_scr_next : 2; // [5:4] uint32_t fft_lnum4_scr_next : 2; // [7:6] uint32_t fft_lnum5_scr_next : 2; // [9:8] uint32_t fft_lnum6_scr_next : 2; // [11:10] uint32_t fft_lnum7_scr_next : 2; // [13:12] uint32_t fft_lnum8_scr_next : 2; // [15:14] uint32_t fft_lnum9_scr_next : 2; // [17:16] uint32_t fft_lnum10_scr_next : 2; // [19:18] uint32_t fft_lnum11_scr_next : 2; // [21:20] uint32_t __31_22 : 10; // [31:22] } b; } REG_UL_DFT_FFT_LNUM_SCR_NEXT_T; // npus_map_cfg_next typedef union { uint32_t v; struct { uint32_t npus_sub_space_next : 1; // [0] uint32_t n_slot_cnt_next : 8; // [8:1] uint32_t isc_start_index_next : 6; // [14:9] uint32_t n_ru_sc_next : 2; // [16:15] uint32_t npus_rep_cnt_next : 7; // [23:17] uint32_t __31_24 : 8; // [31:24] } b; } REG_UL_DFT_NPUS_MAP_CFG_NEXT_T; // npus_dmrs_cfg_next typedef union { uint32_t v; struct { uint32_t cyclic_shift_next : 2; // [1:0] uint32_t base_seq_next : 5; // [6:2] uint32_t slot_n_next : 15; // [21:7] uint32_t first_ru_slot_next : 5; // [26:22] uint32_t __31_27 : 5; // [31:27] } b; } REG_UL_DFT_NPUS_DMRS_CFG_NEXT_T; // npra__cfg_next typedef union { uint32_t v; struct { uint32_t init_sc_next : 6; // [5:0] uint32_t nprach_sc_offset_next : 3; // [8:6] uint32_t sym_group_rep_cnt_next : 8; // [16:9] uint32_t __31_17 : 15; // [31:17] } b; } REG_UL_DFT_NPRA__CFG_NEXT_T; // inout_para typedef union { uint32_t v; struct { uint32_t inout_ctrl : 1; // [0] uint32_t tdd_fdd_mode_sel : 1; // [1] uint32_t cp_mode : 1; // [2] uint32_t __5_3 : 3; // [5:3] uint32_t cyclic_shift : 3; // [8:6] uint32_t n2_pucch : 11; // [19:9] uint32_t delta_ss : 5; // [24:20] uint32_t fir_bit_sel : 4; // [28:25] uint32_t __31_29 : 3; // [31:29] } b; } REG_UL_DFT_INOUT_PARA_T; // id_para typedef union { uint32_t v; struct { uint32_t cell_id : 9; // [8:0] uint32_t rs_id : 10; // [18:9] uint32_t csh_dmrs_id : 10; // [28:19] uint32_t ncs_u_gold_mode : 1; // [29] uint32_t __31_30 : 2; // [31:30] } b; } REG_UL_DFT_ID_PARA_T; // pucch_dummy_id typedef union { uint32_t v; struct { uint32_t puc_dummy_id : 9; // [8:0] uint32_t __31_9 : 23; // [31:9] } b; } REG_UL_DFT_PUCCH_DUMMY_ID_T; // puc_rbmap_config typedef union { uint32_t v; struct { uint32_t nrb2 : 7; // [6:0] uint32_t __7_7 : 1; // [7] uint32_t delta_shift_puc : 2; // [9:8] uint32_t ce_mode_flag : 1; // [10] uint32_t __11_11 : 1; // [11] uint32_t ncs1_puc : 3; // [14:12] uint32_t __31_15 : 17; // [31:15] } b; } REG_UL_DFT_PUC_RBMAP_CONFIG_T; // sysband_config typedef union { uint32_t v; struct { uint32_t sys_band : 3; // [2:0] uint32_t __31_3 : 29; // [31:3] } b; } REG_UL_DFT_SYSBAND_CONFIG_T; // dftfft_launch typedef union { uint32_t v; struct { uint32_t dftfft_launch : 1; // [0] uint32_t dma_start_en : 1; // [1] uint32_t __31_2 : 30; // [31:2] } b; } REG_UL_DFT_DFTFFT_LAUNCH_T; // dft_fft_sw_stop typedef union { uint32_t v; struct { uint32_t sw_stop_en : 1; // [0] uint32_t sw_tmp_en : 1; // [1] uint32_t sw_pause_en : 1; // [2] uint32_t sw_pause_way : 1; // [3] uint32_t sw_pause_ofdm : 14; // [17:4] uint32_t __31_18 : 14; // [31:18] } b; } REG_UL_DFT_DFT_FFT_SW_STOP_T; // dft_fft_sw_stop_flag typedef union { uint32_t v; struct { uint32_t sw_stop_flag : 1; // [0], write clear uint32_t sw_pause_flag : 1; // [1], write clear uint32_t __31_2 : 30; // [31:2] } b; } REG_UL_DFT_DFT_FFT_SW_STOP_FLAG_T; // dft_ctrl_curr1 typedef union { uint32_t v; struct { uint32_t dft_idft_sel_curr : 1; // [0] uint32_t pus_mod_en_curr : 1; // [1] uint32_t dft_en_curr : 1; // [2] uint32_t pus_modu_sel_curr : 2; // [4:3] uint32_t dft_npts_curr : 6; // [10:5] uint32_t anti_drop_lnum_curr : 1; // [11] uint32_t anti_drop_en_curr : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_UL_DFT_DFT_CTRL_CURR1_T; // puc_mod_data_curr1 typedef union { uint32_t v; struct { uint32_t puc_mod_data_curr : 22; // [21:0] uint32_t __31_22 : 10; // [31:22] } b; } REG_UL_DFT_PUC_MOD_DATA_CURR1_T; // srs_map_cfg_curr1 typedef union { uint32_t v; struct { uint32_t srs_map_start1_curr : 7; // [6:0] uint32_t __7_7 : 1; // [7] uint32_t srs_map_start2_curr : 7; // [14:8] uint32_t __15_15 : 1; // [15] uint32_t srs_map_len_curr : 7; // [22:16] uint32_t __23_23 : 1; // [23] uint32_t k_tc_curr : 2; // [25:24] uint32_t k_tc_num_curr : 1; // [26] uint32_t __31_27 : 5; // [31:27] } b; } REG_UL_DFT_SRS_MAP_CFG_CURR1_T; // srs_zc_len_curr1 typedef union { uint32_t v; struct { uint32_t srs_zc_len_curr : 11; // [10:0] uint32_t __11_11 : 1; // [11] uint32_t special_frame_start_curr : 4; // [15:12] uint32_t sra_map_ofdm1_curr : 4; // [19:16] uint32_t srs_map_ofdm2_curr : 4; // [23:20] uint32_t srs_num_curr : 1; // [24] uint32_t __31_25 : 7; // [31:25] } b; } REG_UL_DFT_SRS_ZC_LEN_CURR1_T; // puc_map_cfg_curr1 typedef union { uint32_t v; struct { uint32_t puc_map_start1_curr : 7; // [6:0] uint32_t __7_7 : 1; // [7] uint32_t puc_map_start2_curr : 7; // [14:8] uint32_t __15_15 : 1; // [15] uint32_t tx_nb_start1_curr : 7; // [22:16] uint32_t __23_23 : 1; // [23] uint32_t tx_nb_start2_curr : 7; // [30:24] uint32_t tx_fir_en_curr : 1; // [31] } b; } REG_UL_DFT_PUC_MAP_CFG_CURR1_T; // pus_map_cfg_curr1 typedef union { uint32_t v; struct { uint32_t pus_map_start1_curr : 7; // [6:0] uint32_t __7_7 : 1; // [7] uint32_t pus_map_start2_curr : 7; // [14:8] uint32_t __15_15 : 1; // [15] uint32_t pus_map_len1_curr : 7; // [22:16] uint32_t __23_23 : 1; // [23] uint32_t pus_map_len2_curr : 7; // [30:24] uint32_t pus_map_sel_curr : 1; // [31] } b; } REG_UL_DFT_PUS_MAP_CFG_CURR1_T; // hard_para_curr11 typedef union { uint32_t v; struct { uint32_t cyclic_shift_field_curr : 3; // [2:0] uint32_t ta_overlap_curr : 6; // [8:3] uint32_t seq_hop_flag_curr : 1; // [9] uint32_t group_hop_flag_curr : 1; // [10] uint32_t pucpus_shortened_mode_curr : 4; // [14:11] uint32_t __31_15 : 17; // [31:15] } b; } REG_UL_DFT_HARD_PARA_CURR11_T; // hard_para__curr21 typedef union { uint32_t v; struct { uint32_t delta_apc_scr_curr : 16; // [15:0] uint32_t delta_apc_srs_curr : 16; // [31:16] } b; } REG_UL_DFT_HARD_PARA__CURR21_T; // hard_para__curr31 typedef union { uint32_t v; struct { uint32_t nf_curr : 10; // [9:0] uint32_t subframe_slot_cnt_curr : 5; // [14:10] uint32_t __15_15 : 1; // [15] uint32_t srs_cycle_shift_curr : 4; // [19:16] uint32_t n1_pucch_curr : 12; // [31:20] } b; } REG_UL_DFT_HARD_PARA__CURR31_T; // ofdm_offset_curr1 typedef union { uint32_t v; struct { uint32_t ofdm_offset_first_curr : 16; // [15:0] uint32_t ofdm_offset_last_curr : 16; // [31:16] } b; } REG_UL_DFT_OFDM_OFFSET_CURR1_T; // dft_fft_inten_curr1 typedef union { uint32_t v; struct { uint32_t dft_fft_inten0_curr : 1; // [0] uint32_t dft_fft_inten1_curr : 1; // [1] uint32_t dft_fft_inten2_curr : 1; // [2] uint32_t dft_fft_inten3_curr : 1; // [3] uint32_t dft_fft_inten4_curr : 1; // [4] uint32_t dft_fft_inten5_curr : 1; // [5] uint32_t dft_fft_inten6_curr : 1; // [6] uint32_t dft_fft_inten7_curr : 1; // [7] uint32_t dft_fft_inten8_curr : 1; // [8] uint32_t dft_fft_inten9_curr : 1; // [9] uint32_t dft_fft_inten10_curr : 1; // [10] uint32_t dft_fft_inten11_curr : 1; // [11] uint32_t dft_fft_inten12_curr : 1; // [12] uint32_t dft_fft_inten13_curr : 1; // [13] uint32_t dma_inten_curr : 1; // [14] uint32_t err_inten_curr : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_UL_DFT_DFT_FFT_INTEN_CURR1_T; // ofdm_zero_curr1 typedef union { uint32_t v; struct { uint32_t ofdm_zero_curr : 14; // [13:0] uint32_t __31_14 : 18; // [31:14] } b; } REG_UL_DFT_OFDM_ZERO_CURR1_T; // dft_fft_ctrl_curr1 typedef union { uint32_t v; struct { uint32_t dftfft_irqen_curr : 1; // [0] uint32_t fft_npts : 3; // [3:1] uint32_t chan_mode_curr : 3; // [6:4] uint32_t __7_7 : 1; // [7] uint32_t pus_buf_sel_curr : 2; // [9:8] uint32_t datadrive_en_curr : 1; // [10] uint32_t __11_11 : 1; // [11] uint32_t ofdm_num_curr : 4; // [15:12] uint32_t npusch_formatsel_curr : 1; // [16] uint32_t pucch_format_sel_curr : 3; // [19:17] uint32_t prach_format_sel_curr : 3; // [22:20] uint32_t pwradj_en_curr : 1; // [23] uint32_t fft_cal_curr : 1; // [24] uint32_t fft_ifft_sel_curr : 1; // [25] uint32_t clear_en_curr : 1; // [26] uint32_t srs_en_curr : 1; // [27] uint32_t launch_en_curr : 1; // [28] uint32_t dft_trig_mode : 1; // [29] uint32_t dftfft_soft_start : 1; // [30] uint32_t __31_31 : 1; // [31] } b; } REG_UL_DFT_DFT_FFT_CTRL_CURR1_T; // fft_lnum_srs_curr1 typedef union { uint32_t v; struct { uint32_t fft_lnum1_srs_curr : 2; // [1:0] uint32_t fft_lnum2_srs_curr : 2; // [3:2] uint32_t fft_lnum3_srs_curr : 2; // [5:4] uint32_t fft_lnum4_srs_curr : 2; // [7:6] uint32_t fft_lnum5_srs_curr : 2; // [9:8] uint32_t fft_lnum6_srs_curr : 2; // [11:10] uint32_t fft_lnum7_srs_curr : 2; // [13:12] uint32_t fft_lnum8_srs_curr : 2; // [15:14] uint32_t fft_lnum9_srs_curr : 2; // [17:16] uint32_t fft_lnum10_srs_curr : 2; // [19:18] uint32_t fft_lnum11_srs_curr : 2; // [21:20] uint32_t __31_22 : 10; // [31:22] } b; } REG_UL_DFT_FFT_LNUM_SRS_CURR1_T; // fft_lnum_scr_curr1 typedef union { uint32_t v; struct { uint32_t fft_lnum1_scr_curr : 2; // [1:0] uint32_t fft_lnum2_scr_curr : 2; // [3:2] uint32_t fft_lnum3_scr_curr : 2; // [5:4] uint32_t fft_lnum4_scr_curr : 2; // [7:6] uint32_t fft_lnum5_scr_curr : 2; // [9:8] uint32_t fft_lnum6_scr_curr : 2; // [11:10] uint32_t fft_lnum7_scr_curr : 2; // [13:12] uint32_t fft_lnum8_scr_curr : 2; // [15:14] uint32_t fft_lnum9_scr_curr : 2; // [17:16] uint32_t fft_lnum10_scr_curr : 2; // [19:18] uint32_t fft_lnum11_scr_curr : 2; // [21:20] uint32_t __31_22 : 10; // [31:22] } b; } REG_UL_DFT_FFT_LNUM_SCR_CURR1_T; // npus_map_cfg_curr1 typedef union { uint32_t v; struct { uint32_t npus_sub_space_curr : 1; // [0] uint32_t n_slot_cnt_curr : 8; // [8:1] uint32_t isc_start_index_curr : 6; // [14:9] uint32_t n_ru_sc_curr : 2; // [16:15] uint32_t npus_rep_cnt_curr : 7; // [23:17] uint32_t __31_24 : 8; // [31:24] } b; } REG_UL_DFT_NPUS_MAP_CFG_CURR1_T; // npus_dmrs_cfg_curr1 typedef union { uint32_t v; struct { uint32_t cyclic_shift_curr : 2; // [1:0] uint32_t base_seq_curr : 5; // [6:2] uint32_t slot_n_curr : 15; // [21:7] uint32_t first_ru_slot_curr : 5; // [26:22] uint32_t __31_27 : 5; // [31:27] } b; } REG_UL_DFT_NPUS_DMRS_CFG_CURR1_T; // npra__cfg_curr1 typedef union { uint32_t v; struct { uint32_t init_sc_curr : 6; // [5:0] uint32_t nprach_sc_offset_curr : 3; // [8:6] uint32_t sym_group_rep_cnt_curr : 8; // [16:9] uint32_t __31_17 : 15; // [31:17] } b; } REG_UL_DFT_NPRA__CFG_CURR1_T; // dft_ctrl_curr2 typedef union { uint32_t v; struct { uint32_t dft_idft_sel_curr : 1; // [0] uint32_t pus_mod_en_curr : 1; // [1] uint32_t dft_en_curr : 1; // [2] uint32_t pus_modu_sel_curr : 2; // [4:3] uint32_t dft_npts_curr : 6; // [10:5] uint32_t anti_drop_lnum_curr : 1; // [11] uint32_t anti_drop_en_curr : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_UL_DFT_DFT_CTRL_CURR2_T; // puc_mod_data_curr2 typedef union { uint32_t v; struct { uint32_t puc_mod_data_curr : 22; // [21:0] uint32_t __31_22 : 10; // [31:22] } b; } REG_UL_DFT_PUC_MOD_DATA_CURR2_T; // srs_map_cfg_curr2 typedef union { uint32_t v; struct { uint32_t srs_map_start1_curr : 7; // [6:0] uint32_t __7_7 : 1; // [7] uint32_t srs_map_start2_curr : 7; // [14:8] uint32_t __15_15 : 1; // [15] uint32_t srs_map_len_curr : 7; // [22:16] uint32_t __23_23 : 1; // [23] uint32_t k_tc_curr : 2; // [25:24] uint32_t k_tc_num_curr : 1; // [26] uint32_t __31_27 : 5; // [31:27] } b; } REG_UL_DFT_SRS_MAP_CFG_CURR2_T; // srs_zc_len_curr2 typedef union { uint32_t v; struct { uint32_t srs_zc_len_curr : 11; // [10:0] uint32_t __11_11 : 1; // [11] uint32_t special_frame_start_curr : 4; // [15:12] uint32_t sra_map_ofdm1_curr : 4; // [19:16] uint32_t srs_map_ofdm2_curr : 4; // [23:20] uint32_t srs_num_curr : 1; // [24] uint32_t __31_25 : 7; // [31:25] } b; } REG_UL_DFT_SRS_ZC_LEN_CURR2_T; // puc_map_cfg_curr2 typedef union { uint32_t v; struct { uint32_t puc_map_start1_curr : 7; // [6:0] uint32_t __7_7 : 1; // [7] uint32_t puc_map_start2_curr : 7; // [14:8] uint32_t __15_15 : 1; // [15] uint32_t tx_nb_start1_curr : 7; // [22:16] uint32_t __23_23 : 1; // [23] uint32_t tx_nb_start2_curr : 7; // [30:24] uint32_t tx_fir_en_curr : 1; // [31] } b; } REG_UL_DFT_PUC_MAP_CFG_CURR2_T; // pus_map_cfg_curr2 typedef union { uint32_t v; struct { uint32_t pus_map_start1_curr : 7; // [6:0] uint32_t __7_7 : 1; // [7] uint32_t pus_map_start2_curr : 7; // [14:8] uint32_t __15_15 : 1; // [15] uint32_t pus_map_len1_curr : 7; // [22:16] uint32_t __23_23 : 1; // [23] uint32_t pus_map_len2_curr : 7; // [30:24] uint32_t pus_map_sel_curr : 1; // [31] } b; } REG_UL_DFT_PUS_MAP_CFG_CURR2_T; // hard_para_curr12 typedef union { uint32_t v; struct { uint32_t cyclic_shift_field_curr : 3; // [2:0] uint32_t ta_overlap_curr : 6; // [8:3] uint32_t seq_hop_flag_curr : 1; // [9] uint32_t group_hop_flag_curr : 1; // [10] uint32_t pucpus_shortened_mode_curr : 4; // [14:11] uint32_t __31_15 : 17; // [31:15] } b; } REG_UL_DFT_HARD_PARA_CURR12_T; // hard_para__curr22 typedef union { uint32_t v; struct { uint32_t delta_apc_scr_curr : 16; // [15:0] uint32_t delta_apc_srs_curr : 16; // [31:16] } b; } REG_UL_DFT_HARD_PARA__CURR22_T; // hard_para__curr32 typedef union { uint32_t v; struct { uint32_t nf_curr : 10; // [9:0] uint32_t subframe_slot_cnt_curr : 5; // [14:10] uint32_t __15_15 : 1; // [15] uint32_t srs_cycle_shift_curr : 4; // [19:16] uint32_t n1_pucch_curr : 12; // [31:20] } b; } REG_UL_DFT_HARD_PARA__CURR32_T; // ofdm_offset_curr2 typedef union { uint32_t v; struct { uint32_t ofdm_offset_first_curr : 16; // [15:0] uint32_t ofdm_offset_last_curr : 16; // [31:16] } b; } REG_UL_DFT_OFDM_OFFSET_CURR2_T; // dft_fft_inten_curr2 typedef union { uint32_t v; struct { uint32_t dft_fft_inten0_curr : 1; // [0] uint32_t dft_fft_inten1_curr : 1; // [1] uint32_t dft_fft_inten2_curr : 1; // [2] uint32_t dft_fft_inten3_curr : 1; // [3] uint32_t dft_fft_inten4_curr : 1; // [4] uint32_t dft_fft_inten5_curr : 1; // [5] uint32_t dft_fft_inten6_curr : 1; // [6] uint32_t dft_fft_inten7_curr : 1; // [7] uint32_t dft_fft_inten8_curr : 1; // [8] uint32_t dft_fft_inten9_curr : 1; // [9] uint32_t dft_fft_inten10_curr : 1; // [10] uint32_t dft_fft_inten11_curr : 1; // [11] uint32_t dft_fft_inten12_curr : 1; // [12] uint32_t dft_fft_inten13_curr : 1; // [13] uint32_t dma_inten_curr : 1; // [14] uint32_t err_inten_curr : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_UL_DFT_DFT_FFT_INTEN_CURR2_T; // ofdm_zero_curr2 typedef union { uint32_t v; struct { uint32_t ofdm_zero_curr : 14; // [13:0] uint32_t __31_14 : 18; // [31:14] } b; } REG_UL_DFT_OFDM_ZERO_CURR2_T; // dft_fft_ctrl_curr2 typedef union { uint32_t v; struct { uint32_t dftfft_irqen_curr : 1; // [0] uint32_t fft_npts : 3; // [3:1] uint32_t chan_mode_curr : 3; // [6:4] uint32_t __7_7 : 1; // [7] uint32_t pus_buf_sel_curr : 2; // [9:8] uint32_t datadrive_en_curr : 1; // [10] uint32_t __11_11 : 1; // [11] uint32_t ofdm_num_curr : 4; // [15:12] uint32_t npusch_formatsel_curr : 1; // [16] uint32_t pucch_format_sel_curr : 3; // [19:17] uint32_t prach_format_sel_curr : 3; // [22:20] uint32_t pwradj_en_curr : 1; // [23] uint32_t fft_cal_curr : 1; // [24] uint32_t fft_ifft_sel_curr : 1; // [25] uint32_t clear_en_curr : 1; // [26] uint32_t srs_en_curr : 1; // [27] uint32_t launch_en_curr : 1; // [28] uint32_t dft_trig_mode : 1; // [29] uint32_t dftfft_soft_start : 1; // [30] uint32_t __31_31 : 1; // [31] } b; } REG_UL_DFT_DFT_FFT_CTRL_CURR2_T; // fft_lnum_srs_curr2 typedef union { uint32_t v; struct { uint32_t fft_lnum1_srs_curr : 2; // [1:0] uint32_t fft_lnum2_srs_curr : 2; // [3:2] uint32_t fft_lnum3_srs_curr : 2; // [5:4] uint32_t fft_lnum4_srs_curr : 2; // [7:6] uint32_t fft_lnum5_srs_curr : 2; // [9:8] uint32_t fft_lnum6_srs_curr : 2; // [11:10] uint32_t fft_lnum7_srs_curr : 2; // [13:12] uint32_t fft_lnum8_srs_curr : 2; // [15:14] uint32_t fft_lnum9_srs_curr : 2; // [17:16] uint32_t fft_lnum10_srs_curr : 2; // [19:18] uint32_t fft_lnum11_srs_curr : 2; // [21:20] uint32_t __31_22 : 10; // [31:22] } b; } REG_UL_DFT_FFT_LNUM_SRS_CURR2_T; // fft_lnum_scr_curr2 typedef union { uint32_t v; struct { uint32_t fft_lnum1_scr_curr : 2; // [1:0] uint32_t fft_lnum2_scr_curr : 2; // [3:2] uint32_t fft_lnum3_scr_curr : 2; // [5:4] uint32_t fft_lnum4_scr_curr : 2; // [7:6] uint32_t fft_lnum5_scr_curr : 2; // [9:8] uint32_t fft_lnum6_scr_curr : 2; // [11:10] uint32_t fft_lnum7_scr_curr : 2; // [13:12] uint32_t fft_lnum8_scr_curr : 2; // [15:14] uint32_t fft_lnum9_scr_curr : 2; // [17:16] uint32_t fft_lnum10_scr_curr : 2; // [19:18] uint32_t fft_lnum11_scr_curr : 2; // [21:20] uint32_t __31_22 : 10; // [31:22] } b; } REG_UL_DFT_FFT_LNUM_SCR_CURR2_T; // npus_map_cfg_curr2 typedef union { uint32_t v; struct { uint32_t npus_sub_space_curr : 1; // [0] uint32_t n_slot_cnt_curr : 8; // [8:1] uint32_t isc_start_index_curr : 6; // [14:9] uint32_t n_ru_sc_curr : 2; // [16:15] uint32_t npus_rep_cnt_curr : 7; // [23:17] uint32_t __31_24 : 8; // [31:24] } b; } REG_UL_DFT_NPUS_MAP_CFG_CURR2_T; // npus_dmrs_cfg_curr2 typedef union { uint32_t v; struct { uint32_t cyclic_shift_curr : 2; // [1:0] uint32_t base_seq_curr : 5; // [6:2] uint32_t slot_n_curr : 15; // [21:7] uint32_t first_ru_slot_curr : 5; // [26:22] uint32_t __31_27 : 5; // [31:27] } b; } REG_UL_DFT_NPUS_DMRS_CFG_CURR2_T; // npra__cfg_curr2 typedef union { uint32_t v; struct { uint32_t init_sc_curr : 6; // [5:0] uint32_t nprach_sc_offset_curr : 3; // [8:6] uint32_t sym_group_rep_cnt_curr : 8; // [16:9] uint32_t __31_17 : 15; // [31:17] } b; } REG_UL_DFT_NPRA__CFG_CURR2_T; // fsm_state typedef union { uint32_t v; struct { uint32_t ofdm_state : 16; // [15:0], read only uint32_t frame_state : 14; // [29:16], read only uint32_t ocp_pa : 1; // [30], read only uint32_t ocp_pi : 1; // [31], read only } b; } REG_UL_DFT_FSM_STATE_T; // ofdm_count typedef union { uint32_t v; struct { uint32_t ofdm_count : 4; // [3:0], read only uint32_t __31_4 : 28; // [31:4] } b; } REG_UL_DFT_OFDM_COUNT_T; // fsm_state_assert typedef union { uint32_t v; struct { uint32_t ofdm_state_assert : 16; // [15:0], read only uint32_t frame_state_assert : 14; // [29:16], read only uint32_t ocp_pa_assert : 1; // [30], read only uint32_t ocp_pi_assert : 1; // [31], read only } b; } REG_UL_DFT_FSM_STATE_ASSERT_T; // ofdm_assert typedef union { uint32_t v; struct { uint32_t ofdm_assert : 4; // [3:0], read only uint32_t __31_4 : 28; // [31:4] } b; } REG_UL_DFT_OFDM_ASSERT_T; // dft_ctrl_next #define UL_DFT_DFT_IDFT_SEL_NEXT (1 << 0) #define UL_DFT_PUS_MOD_EN_NEXT (1 << 1) #define UL_DFT_DFT_EN_NEXT (1 << 2) #define UL_DFT_PUS_MODU_SEL_NEXT(n) (((n)&0x3) << 3) #define UL_DFT_DFT_NPTS_NEXT(n) (((n)&0x3f) << 5) #define UL_DFT_ANTI_DROP_LNUM_NEXT (1 << 11) #define UL_DFT_ANTI_DROP_EN_NEXT (1 << 12) // puc_mod_data_next #define UL_DFT_PUC_MOD_DATA_NEXT(n) (((n)&0x3fffff) << 0) // srs_map_cfg_next #define UL_DFT_SRS_MAP_START1_NEXT(n) (((n)&0x7f) << 0) #define UL_DFT_SRS_MAP_START2_NEXT(n) (((n)&0x7f) << 8) #define UL_DFT_SRS_MAP_LEN_NEXT(n) (((n)&0x7f) << 16) #define UL_DFT_K_TC_NEXT(n) (((n)&0x3) << 24) #define UL_DFT_K_TC_NUM_NEXT (1 << 26) // srs_zc_len_next #define UL_DFT_SRS_ZC_LEN_NEXT(n) (((n)&0x7ff) << 0) #define UL_DFT_SPECIAL_FRAME_START_NEXT(n) (((n)&0xf) << 12) #define UL_DFT_SRA_MAP_OFDM1_NEXT(n) (((n)&0xf) << 16) #define UL_DFT_SRS_MAP_OFDM2_NEXT(n) (((n)&0xf) << 20) #define UL_DFT_SRS_NUM_NEXT (1 << 24) // puc_map_cfg_next #define UL_DFT_PUC_MAP_START1_NEXT(n) (((n)&0x7f) << 0) #define UL_DFT_PUC_MAP_START2_NEXT(n) (((n)&0x7f) << 8) #define UL_DFT_TX_NB_START1_NEXT(n) (((n)&0x7f) << 16) #define UL_DFT_TX_NB_START2_NEXT(n) (((n)&0x7f) << 24) #define UL_DFT_TX_FIR_EN_NEXT (1 << 31) // pus_map_cfg_next #define UL_DFT_PUS_MAP_START1_NEXT(n) (((n)&0x7f) << 0) #define UL_DFT_PUS_MAP_START2_NEXT(n) (((n)&0x7f) << 8) #define UL_DFT_PUS_MAP_LEN1_NEXT(n) (((n)&0x7f) << 16) #define UL_DFT_PUS_MAP_LEN2_NEXT(n) (((n)&0x7f) << 24) #define UL_DFT_PUS_MAP_SEL_NEXT (1 << 31) // hard_para_next1 #define UL_DFT_CYCLIC_SHIFT_FIELD_NEXT(n) (((n)&0x7) << 0) #define UL_DFT_TA_OVERLAP_NEXT(n) (((n)&0x3f) << 3) #define UL_DFT_SEQ_HOP_FLAG_NEXT (1 << 9) #define UL_DFT_GROUP_HOP_FLAG_NEXT (1 << 10) #define UL_DFT_PUCPUS_SHORTENED_MODE_NEXT(n) (((n)&0xf) << 11) #define UL_DFT_PUS_DMRS_W_FLAG (1 << 15) // hard_para__next2 #define UL_DFT_DELTA_APC_SCR_NEXT(n) (((n)&0xffff) << 0) #define UL_DFT_DELTA_APC_SRS_NEXT(n) (((n)&0xffff) << 16) // hard_para__next3 #define UL_DFT_NF_NEXT(n) (((n)&0x3ff) << 0) #define UL_DFT_SUBFRAME_SLOT_CNT_NEXT(n) (((n)&0x1f) << 10) #define UL_DFT_SRS_CYCLE_SHIFT_NEXT(n) (((n)&0xf) << 16) #define UL_DFT_N1_PUCCH_NEXT(n) (((n)&0xfff) << 20) // ofdm_offset_next #define UL_DFT_OFDM_OFFSET_FIRST_NEXT(n) (((n)&0xffff) << 0) #define UL_DFT_OFDM_OFFSET_LAST_NEXT(n) (((n)&0xffff) << 16) // dft_fft_inten_next #define UL_DFT_DFT_FFT_INTEN0_NEXT (1 << 0) #define UL_DFT_DFT_FFT_INTEN1_NEXT (1 << 1) #define UL_DFT_DFT_FFT_INTEN2_NEXT (1 << 2) #define UL_DFT_DFT_FFT_INTEN3_NEXT (1 << 3) #define UL_DFT_DFT_FFT_INTEN4_NEXT (1 << 4) #define UL_DFT_DFT_FFT_INTEN5_NEXT (1 << 5) #define UL_DFT_DFT_FFT_INTEN6_NEXT (1 << 6) #define UL_DFT_DFT_FFT_INTEN7_NEXT (1 << 7) #define UL_DFT_DFT_FFT_INTEN8_NEXT (1 << 8) #define UL_DFT_DFT_FFT_INTEN9_NEXT (1 << 9) #define UL_DFT_DFT_FFT_INTEN10_NEXT (1 << 10) #define UL_DFT_DFT_FFT_INTEN11_NEXT (1 << 11) #define UL_DFT_DFT_FFT_INTEN12_NEXT (1 << 12) #define UL_DFT_DFT_FFT_INTEN13_NEXT (1 << 13) #define UL_DFT_DMA_INTEN_NEXT (1 << 14) #define UL_DFT_ERR_INTEN_NEXT (1 << 15) // dft_fft_intf_next #define UL_DFT_TXRX_WR_ERRF (1 << 0) #define UL_DFT_PUS_RD_ERRF (1 << 1) #define UL_DFT_DFT_FFT_INTF0_NEXT (1 << 2) #define UL_DFT_DFT_FFT_INTF1_NEXT (1 << 3) #define UL_DFT_DFT_FFT_INTF2_NEXT (1 << 4) #define UL_DFT_DFT_FFT_INTF3_NEXT (1 << 5) #define UL_DFT_DFT_FFT_INTF4_NEXT (1 << 6) #define UL_DFT_DFT_FFT_INTF5_NEXT (1 << 7) #define UL_DFT_DFT_FFT_INTF6_NEXT (1 << 8) #define UL_DFT_DFT_FFT_INTF7_NEXT (1 << 9) #define UL_DFT_DFT_FFT_INTF8_NEXT (1 << 10) #define UL_DFT_DFT_FFT_INTF9_NEXT (1 << 11) #define UL_DFT_DFT_FFT_INTF10_NEXT (1 << 12) #define UL_DFT_DFT_FFT_INTF11_NEXT (1 << 13) #define UL_DFT_DFT_FFT_INTF12_NEXT (1 << 14) #define UL_DFT_DFT_FFT_INTF13_NEXT (1 << 15) // ofdm_zero_next #define UL_DFT_OFDM_ZERO_NEXT(n) (((n)&0x3fff) << 0) // dft_fft_ctrl_next #define UL_DFT_DFTFFT_IRQEN_NEXT (1 << 0) #define UL_DFT_FFT_NPTS(n) (((n)&0x7) << 1) #define UL_DFT_CHAN_MODE_NEXT(n) (((n)&0x7) << 4) #define UL_DFT_PUS_BUF_SEL_NEXT(n) (((n)&0x3) << 8) #define UL_DFT_DATADRIVE_EN_NEXT (1 << 10) #define UL_DFT_OFDM_NUM_NEXT(n) (((n)&0xf) << 12) #define UL_DFT_NPUSCH_FORMATSEL_NEXT (1 << 16) #define UL_DFT_PUCCH_FORMAT_SEL_NEXT(n) (((n)&0x7) << 17) #define UL_DFT_PRACH_FORMAT_SEL_NEXT(n) (((n)&0x7) << 20) #define UL_DFT_PWRADJ_EN_NEXT (1 << 23) #define UL_DFT_FFT_CAL_NEXT (1 << 24) #define UL_DFT_FFT_IFFT_SEL_NEXT (1 << 25) #define UL_DFT_CLEAR_EN_NEXT (1 << 26) #define UL_DFT_SRS_EN_NEXT (1 << 27) #define UL_DFT_LAUNCH_EN_NEXT (1 << 28) #define UL_DFT_DFT_TRIG_MODE (1 << 29) #define UL_DFT_DFTFFT_SOFT_START (1 << 30) // fft_lnum_srs_next #define UL_DFT_FFT_LNUM1_SRS_NEXT(n) (((n)&0x3) << 0) #define UL_DFT_FFT_LNUM2_SRS_NEXT(n) (((n)&0x3) << 2) #define UL_DFT_FFT_LNUM3_SRS_NEXT(n) (((n)&0x3) << 4) #define UL_DFT_FFT_LNUM4_SRS_NEXT(n) (((n)&0x3) << 6) #define UL_DFT_FFT_LNUM5_SRS_NEXT(n) (((n)&0x3) << 8) #define UL_DFT_FFT_LNUM6_SRS_NEXT(n) (((n)&0x3) << 10) #define UL_DFT_FFT_LNUM7_SRS_NEXT(n) (((n)&0x3) << 12) #define UL_DFT_FFT_LNUM8_SRS_NEXT(n) (((n)&0x3) << 14) #define UL_DFT_FFT_LNUM9_SRS_NEXT(n) (((n)&0x3) << 16) #define UL_DFT_FFT_LNUM10_SRS_NEXT(n) (((n)&0x3) << 18) #define UL_DFT_FFT_LNUM11_SRS_NEXT(n) (((n)&0x3) << 20) // fft_lnum_scr_next #define UL_DFT_FFT_LNUM1_SCR_NEXT(n) (((n)&0x3) << 0) #define UL_DFT_FFT_LNUM2_SCR_NEXT(n) (((n)&0x3) << 2) #define UL_DFT_FFT_LNUM3_SCR_NEXT(n) (((n)&0x3) << 4) #define UL_DFT_FFT_LNUM4_SCR_NEXT(n) (((n)&0x3) << 6) #define UL_DFT_FFT_LNUM5_SCR_NEXT(n) (((n)&0x3) << 8) #define UL_DFT_FFT_LNUM6_SCR_NEXT(n) (((n)&0x3) << 10) #define UL_DFT_FFT_LNUM7_SCR_NEXT(n) (((n)&0x3) << 12) #define UL_DFT_FFT_LNUM8_SCR_NEXT(n) (((n)&0x3) << 14) #define UL_DFT_FFT_LNUM9_SCR_NEXT(n) (((n)&0x3) << 16) #define UL_DFT_FFT_LNUM10_SCR_NEXT(n) (((n)&0x3) << 18) #define UL_DFT_FFT_LNUM11_SCR_NEXT(n) (((n)&0x3) << 20) // npus_map_cfg_next #define UL_DFT_NPUS_SUB_SPACE_NEXT (1 << 0) #define UL_DFT_N_SLOT_CNT_NEXT(n) (((n)&0xff) << 1) #define UL_DFT_ISC_START_INDEX_NEXT(n) (((n)&0x3f) << 9) #define UL_DFT_N_RU_SC_NEXT(n) (((n)&0x3) << 15) #define UL_DFT_NPUS_REP_CNT_NEXT(n) (((n)&0x7f) << 17) // npus_dmrs_cfg_next #define UL_DFT_CYCLIC_SHIFT_NEXT(n) (((n)&0x3) << 0) #define UL_DFT_BASE_SEQ_NEXT(n) (((n)&0x1f) << 2) #define UL_DFT_SLOT_N_NEXT(n) (((n)&0x7fff) << 7) #define UL_DFT_FIRST_RU_SLOT_NEXT(n) (((n)&0x1f) << 22) // npra__cfg_next #define UL_DFT_INIT_SC_NEXT(n) (((n)&0x3f) << 0) #define UL_DFT_NPRACH_SC_OFFSET_NEXT(n) (((n)&0x7) << 6) #define UL_DFT_SYM_GROUP_REP_CNT_NEXT(n) (((n)&0xff) << 9) // inout_para #define UL_DFT_INOUT_CTRL (1 << 0) #define UL_DFT_TDD_FDD_MODE_SEL (1 << 1) #define UL_DFT_CP_MODE (1 << 2) #define UL_DFT_CYCLIC_SHIFT(n) (((n)&0x7) << 6) #define UL_DFT_N2_PUCCH(n) (((n)&0x7ff) << 9) #define UL_DFT_DELTA_SS(n) (((n)&0x1f) << 20) #define UL_DFT_FIR_BIT_SEL(n) (((n)&0xf) << 25) // id_para #define UL_DFT_CELL_ID(n) (((n)&0x1ff) << 0) #define UL_DFT_RS_ID(n) (((n)&0x3ff) << 9) #define UL_DFT_CSH_DMRS_ID(n) (((n)&0x3ff) << 19) #define UL_DFT_NCS_U_GOLD_MODE (1 << 29) // pucch_dummy_id #define UL_DFT_PUC_DUMMY_ID(n) (((n)&0x1ff) << 0) // puc_rbmap_config #define UL_DFT_NRB2(n) (((n)&0x7f) << 0) #define UL_DFT_DELTA_SHIFT_PUC(n) (((n)&0x3) << 8) #define UL_DFT_CE_MODE_FLAG (1 << 10) #define UL_DFT_NCS1_PUC(n) (((n)&0x7) << 12) // sysband_config #define UL_DFT_SYS_BAND(n) (((n)&0x7) << 0) // dftfft_launch #define UL_DFT_DFTFFT_LAUNCH (1 << 0) #define UL_DFT_DMA_START_EN (1 << 1) // dft_fft_sw_stop #define UL_DFT_SW_STOP_EN (1 << 0) #define UL_DFT_SW_TMP_EN (1 << 1) #define UL_DFT_SW_PAUSE_EN (1 << 2) #define UL_DFT_SW_PAUSE_WAY (1 << 3) #define UL_DFT_SW_PAUSE_OFDM(n) (((n)&0x3fff) << 4) // dft_fft_sw_stop_flag #define UL_DFT_SW_STOP_FLAG (1 << 0) #define UL_DFT_SW_PAUSE_FLAG (1 << 1) // dft_ctrl_curr1 #define UL_DFT_DFT_IDFT_SEL_CURR (1 << 0) #define UL_DFT_PUS_MOD_EN_CURR (1 << 1) #define UL_DFT_DFT_EN_CURR (1 << 2) #define UL_DFT_PUS_MODU_SEL_CURR(n) (((n)&0x3) << 3) #define UL_DFT_DFT_NPTS_CURR(n) (((n)&0x3f) << 5) #define UL_DFT_ANTI_DROP_LNUM_CURR (1 << 11) #define UL_DFT_ANTI_DROP_EN_CURR (1 << 12) // puc_mod_data_curr1 #define UL_DFT_PUC_MOD_DATA_CURR(n) (((n)&0x3fffff) << 0) // srs_map_cfg_curr1 #define UL_DFT_SRS_MAP_START1_CURR(n) (((n)&0x7f) << 0) #define UL_DFT_SRS_MAP_START2_CURR(n) (((n)&0x7f) << 8) #define UL_DFT_SRS_MAP_LEN_CURR(n) (((n)&0x7f) << 16) #define UL_DFT_K_TC_CURR(n) (((n)&0x3) << 24) #define UL_DFT_K_TC_NUM_CURR (1 << 26) // srs_zc_len_curr1 #define UL_DFT_SRS_ZC_LEN_CURR(n) (((n)&0x7ff) << 0) #define UL_DFT_SPECIAL_FRAME_START_CURR(n) (((n)&0xf) << 12) #define UL_DFT_SRA_MAP_OFDM1_CURR(n) (((n)&0xf) << 16) #define UL_DFT_SRS_MAP_OFDM2_CURR(n) (((n)&0xf) << 20) #define UL_DFT_SRS_NUM_CURR (1 << 24) // puc_map_cfg_curr1 #define UL_DFT_PUC_MAP_START1_CURR(n) (((n)&0x7f) << 0) #define UL_DFT_PUC_MAP_START2_CURR(n) (((n)&0x7f) << 8) #define UL_DFT_TX_NB_START1_CURR(n) (((n)&0x7f) << 16) #define UL_DFT_TX_NB_START2_CURR(n) (((n)&0x7f) << 24) #define UL_DFT_TX_FIR_EN_CURR (1 << 31) // pus_map_cfg_curr1 #define UL_DFT_PUS_MAP_START1_CURR(n) (((n)&0x7f) << 0) #define UL_DFT_PUS_MAP_START2_CURR(n) (((n)&0x7f) << 8) #define UL_DFT_PUS_MAP_LEN1_CURR(n) (((n)&0x7f) << 16) #define UL_DFT_PUS_MAP_LEN2_CURR(n) (((n)&0x7f) << 24) #define UL_DFT_PUS_MAP_SEL_CURR (1 << 31) // hard_para_curr11 #define UL_DFT_CYCLIC_SHIFT_FIELD_CURR(n) (((n)&0x7) << 0) #define UL_DFT_TA_OVERLAP_CURR(n) (((n)&0x3f) << 3) #define UL_DFT_SEQ_HOP_FLAG_CURR (1 << 9) #define UL_DFT_GROUP_HOP_FLAG_CURR (1 << 10) #define UL_DFT_PUCPUS_SHORTENED_MODE_CURR(n) (((n)&0xf) << 11) // hard_para__curr21 #define UL_DFT_DELTA_APC_SCR_CURR(n) (((n)&0xffff) << 0) #define UL_DFT_DELTA_APC_SRS_CURR(n) (((n)&0xffff) << 16) // hard_para__curr31 #define UL_DFT_NF_CURR(n) (((n)&0x3ff) << 0) #define UL_DFT_SUBFRAME_SLOT_CNT_CURR(n) (((n)&0x1f) << 10) #define UL_DFT_SRS_CYCLE_SHIFT_CURR(n) (((n)&0xf) << 16) #define UL_DFT_N1_PUCCH_CURR(n) (((n)&0xfff) << 20) // ofdm_offset_curr1 #define UL_DFT_OFDM_OFFSET_FIRST_CURR(n) (((n)&0xffff) << 0) #define UL_DFT_OFDM_OFFSET_LAST_CURR(n) (((n)&0xffff) << 16) // dft_fft_inten_curr1 #define UL_DFT_DFT_FFT_INTEN0_CURR (1 << 0) #define UL_DFT_DFT_FFT_INTEN1_CURR (1 << 1) #define UL_DFT_DFT_FFT_INTEN2_CURR (1 << 2) #define UL_DFT_DFT_FFT_INTEN3_CURR (1 << 3) #define UL_DFT_DFT_FFT_INTEN4_CURR (1 << 4) #define UL_DFT_DFT_FFT_INTEN5_CURR (1 << 5) #define UL_DFT_DFT_FFT_INTEN6_CURR (1 << 6) #define UL_DFT_DFT_FFT_INTEN7_CURR (1 << 7) #define UL_DFT_DFT_FFT_INTEN8_CURR (1 << 8) #define UL_DFT_DFT_FFT_INTEN9_CURR (1 << 9) #define UL_DFT_DFT_FFT_INTEN10_CURR (1 << 10) #define UL_DFT_DFT_FFT_INTEN11_CURR (1 << 11) #define UL_DFT_DFT_FFT_INTEN12_CURR (1 << 12) #define UL_DFT_DFT_FFT_INTEN13_CURR (1 << 13) #define UL_DFT_DMA_INTEN_CURR (1 << 14) #define UL_DFT_ERR_INTEN_CURR (1 << 15) // ofdm_zero_curr1 #define UL_DFT_OFDM_ZERO_CURR(n) (((n)&0x3fff) << 0) // dft_fft_ctrl_curr1 #define UL_DFT_DFTFFT_IRQEN_CURR (1 << 0) #define UL_DFT_FFT_NPTS(n) (((n)&0x7) << 1) #define UL_DFT_CHAN_MODE_CURR(n) (((n)&0x7) << 4) #define UL_DFT_PUS_BUF_SEL_CURR(n) (((n)&0x3) << 8) #define UL_DFT_DATADRIVE_EN_CURR (1 << 10) #define UL_DFT_OFDM_NUM_CURR(n) (((n)&0xf) << 12) #define UL_DFT_NPUSCH_FORMATSEL_CURR (1 << 16) #define UL_DFT_PUCCH_FORMAT_SEL_CURR(n) (((n)&0x7) << 17) #define UL_DFT_PRACH_FORMAT_SEL_CURR(n) (((n)&0x7) << 20) #define UL_DFT_PWRADJ_EN_CURR (1 << 23) #define UL_DFT_FFT_CAL_CURR (1 << 24) #define UL_DFT_FFT_IFFT_SEL_CURR (1 << 25) #define UL_DFT_CLEAR_EN_CURR (1 << 26) #define UL_DFT_SRS_EN_CURR (1 << 27) #define UL_DFT_LAUNCH_EN_CURR (1 << 28) #define UL_DFT_DFT_TRIG_MODE (1 << 29) #define UL_DFT_DFTFFT_SOFT_START (1 << 30) // fft_lnum_srs_curr1 #define UL_DFT_FFT_LNUM1_SRS_CURR(n) (((n)&0x3) << 0) #define UL_DFT_FFT_LNUM2_SRS_CURR(n) (((n)&0x3) << 2) #define UL_DFT_FFT_LNUM3_SRS_CURR(n) (((n)&0x3) << 4) #define UL_DFT_FFT_LNUM4_SRS_CURR(n) (((n)&0x3) << 6) #define UL_DFT_FFT_LNUM5_SRS_CURR(n) (((n)&0x3) << 8) #define UL_DFT_FFT_LNUM6_SRS_CURR(n) (((n)&0x3) << 10) #define UL_DFT_FFT_LNUM7_SRS_CURR(n) (((n)&0x3) << 12) #define UL_DFT_FFT_LNUM8_SRS_CURR(n) (((n)&0x3) << 14) #define UL_DFT_FFT_LNUM9_SRS_CURR(n) (((n)&0x3) << 16) #define UL_DFT_FFT_LNUM10_SRS_CURR(n) (((n)&0x3) << 18) #define UL_DFT_FFT_LNUM11_SRS_CURR(n) (((n)&0x3) << 20) // fft_lnum_scr_curr1 #define UL_DFT_FFT_LNUM1_SCR_CURR(n) (((n)&0x3) << 0) #define UL_DFT_FFT_LNUM2_SCR_CURR(n) (((n)&0x3) << 2) #define UL_DFT_FFT_LNUM3_SCR_CURR(n) (((n)&0x3) << 4) #define UL_DFT_FFT_LNUM4_SCR_CURR(n) (((n)&0x3) << 6) #define UL_DFT_FFT_LNUM5_SCR_CURR(n) (((n)&0x3) << 8) #define UL_DFT_FFT_LNUM6_SCR_CURR(n) (((n)&0x3) << 10) #define UL_DFT_FFT_LNUM7_SCR_CURR(n) (((n)&0x3) << 12) #define UL_DFT_FFT_LNUM8_SCR_CURR(n) (((n)&0x3) << 14) #define UL_DFT_FFT_LNUM9_SCR_CURR(n) (((n)&0x3) << 16) #define UL_DFT_FFT_LNUM10_SCR_CURR(n) (((n)&0x3) << 18) #define UL_DFT_FFT_LNUM11_SCR_CURR(n) (((n)&0x3) << 20) // npus_map_cfg_curr1 #define UL_DFT_NPUS_SUB_SPACE_CURR (1 << 0) #define UL_DFT_N_SLOT_CNT_CURR(n) (((n)&0xff) << 1) #define UL_DFT_ISC_START_INDEX_CURR(n) (((n)&0x3f) << 9) #define UL_DFT_N_RU_SC_CURR(n) (((n)&0x3) << 15) #define UL_DFT_NPUS_REP_CNT_CURR(n) (((n)&0x7f) << 17) // npus_dmrs_cfg_curr1 #define UL_DFT_CYCLIC_SHIFT_CURR(n) (((n)&0x3) << 0) #define UL_DFT_BASE_SEQ_CURR(n) (((n)&0x1f) << 2) #define UL_DFT_SLOT_N_CURR(n) (((n)&0x7fff) << 7) #define UL_DFT_FIRST_RU_SLOT_CURR(n) (((n)&0x1f) << 22) // npra__cfg_curr1 #define UL_DFT_INIT_SC_CURR(n) (((n)&0x3f) << 0) #define UL_DFT_NPRACH_SC_OFFSET_CURR(n) (((n)&0x7) << 6) #define UL_DFT_SYM_GROUP_REP_CNT_CURR(n) (((n)&0xff) << 9) // dft_ctrl_curr2 #define UL_DFT_DFT_IDFT_SEL_CURR (1 << 0) #define UL_DFT_PUS_MOD_EN_CURR (1 << 1) #define UL_DFT_DFT_EN_CURR (1 << 2) #define UL_DFT_PUS_MODU_SEL_CURR(n) (((n)&0x3) << 3) #define UL_DFT_DFT_NPTS_CURR(n) (((n)&0x3f) << 5) #define UL_DFT_ANTI_DROP_LNUM_CURR (1 << 11) #define UL_DFT_ANTI_DROP_EN_CURR (1 << 12) // puc_mod_data_curr2 #define UL_DFT_PUC_MOD_DATA_CURR(n) (((n)&0x3fffff) << 0) // srs_map_cfg_curr2 #define UL_DFT_SRS_MAP_START1_CURR(n) (((n)&0x7f) << 0) #define UL_DFT_SRS_MAP_START2_CURR(n) (((n)&0x7f) << 8) #define UL_DFT_SRS_MAP_LEN_CURR(n) (((n)&0x7f) << 16) #define UL_DFT_K_TC_CURR(n) (((n)&0x3) << 24) #define UL_DFT_K_TC_NUM_CURR (1 << 26) // srs_zc_len_curr2 #define UL_DFT_SRS_ZC_LEN_CURR(n) (((n)&0x7ff) << 0) #define UL_DFT_SPECIAL_FRAME_START_CURR(n) (((n)&0xf) << 12) #define UL_DFT_SRA_MAP_OFDM1_CURR(n) (((n)&0xf) << 16) #define UL_DFT_SRS_MAP_OFDM2_CURR(n) (((n)&0xf) << 20) #define UL_DFT_SRS_NUM_CURR (1 << 24) // puc_map_cfg_curr2 #define UL_DFT_PUC_MAP_START1_CURR(n) (((n)&0x7f) << 0) #define UL_DFT_PUC_MAP_START2_CURR(n) (((n)&0x7f) << 8) #define UL_DFT_TX_NB_START1_CURR(n) (((n)&0x7f) << 16) #define UL_DFT_TX_NB_START2_CURR(n) (((n)&0x7f) << 24) #define UL_DFT_TX_FIR_EN_CURR (1 << 31) // pus_map_cfg_curr2 #define UL_DFT_PUS_MAP_START1_CURR(n) (((n)&0x7f) << 0) #define UL_DFT_PUS_MAP_START2_CURR(n) (((n)&0x7f) << 8) #define UL_DFT_PUS_MAP_LEN1_CURR(n) (((n)&0x7f) << 16) #define UL_DFT_PUS_MAP_LEN2_CURR(n) (((n)&0x7f) << 24) #define UL_DFT_PUS_MAP_SEL_CURR (1 << 31) // hard_para_curr12 #define UL_DFT_CYCLIC_SHIFT_FIELD_CURR(n) (((n)&0x7) << 0) #define UL_DFT_TA_OVERLAP_CURR(n) (((n)&0x3f) << 3) #define UL_DFT_SEQ_HOP_FLAG_CURR (1 << 9) #define UL_DFT_GROUP_HOP_FLAG_CURR (1 << 10) #define UL_DFT_PUCPUS_SHORTENED_MODE_CURR(n) (((n)&0xf) << 11) // hard_para__curr22 #define UL_DFT_DELTA_APC_SCR_CURR(n) (((n)&0xffff) << 0) #define UL_DFT_DELTA_APC_SRS_CURR(n) (((n)&0xffff) << 16) // hard_para__curr32 #define UL_DFT_NF_CURR(n) (((n)&0x3ff) << 0) #define UL_DFT_SUBFRAME_SLOT_CNT_CURR(n) (((n)&0x1f) << 10) #define UL_DFT_SRS_CYCLE_SHIFT_CURR(n) (((n)&0xf) << 16) #define UL_DFT_N1_PUCCH_CURR(n) (((n)&0xfff) << 20) // ofdm_offset_curr2 #define UL_DFT_OFDM_OFFSET_FIRST_CURR(n) (((n)&0xffff) << 0) #define UL_DFT_OFDM_OFFSET_LAST_CURR(n) (((n)&0xffff) << 16) // dft_fft_inten_curr2 #define UL_DFT_DFT_FFT_INTEN0_CURR (1 << 0) #define UL_DFT_DFT_FFT_INTEN1_CURR (1 << 1) #define UL_DFT_DFT_FFT_INTEN2_CURR (1 << 2) #define UL_DFT_DFT_FFT_INTEN3_CURR (1 << 3) #define UL_DFT_DFT_FFT_INTEN4_CURR (1 << 4) #define UL_DFT_DFT_FFT_INTEN5_CURR (1 << 5) #define UL_DFT_DFT_FFT_INTEN6_CURR (1 << 6) #define UL_DFT_DFT_FFT_INTEN7_CURR (1 << 7) #define UL_DFT_DFT_FFT_INTEN8_CURR (1 << 8) #define UL_DFT_DFT_FFT_INTEN9_CURR (1 << 9) #define UL_DFT_DFT_FFT_INTEN10_CURR (1 << 10) #define UL_DFT_DFT_FFT_INTEN11_CURR (1 << 11) #define UL_DFT_DFT_FFT_INTEN12_CURR (1 << 12) #define UL_DFT_DFT_FFT_INTEN13_CURR (1 << 13) #define UL_DFT_DMA_INTEN_CURR (1 << 14) #define UL_DFT_ERR_INTEN_CURR (1 << 15) // ofdm_zero_curr2 #define UL_DFT_OFDM_ZERO_CURR(n) (((n)&0x3fff) << 0) // dft_fft_ctrl_curr2 #define UL_DFT_DFTFFT_IRQEN_CURR (1 << 0) #define UL_DFT_FFT_NPTS(n) (((n)&0x7) << 1) #define UL_DFT_CHAN_MODE_CURR(n) (((n)&0x7) << 4) #define UL_DFT_PUS_BUF_SEL_CURR(n) (((n)&0x3) << 8) #define UL_DFT_DATADRIVE_EN_CURR (1 << 10) #define UL_DFT_OFDM_NUM_CURR(n) (((n)&0xf) << 12) #define UL_DFT_NPUSCH_FORMATSEL_CURR (1 << 16) #define UL_DFT_PUCCH_FORMAT_SEL_CURR(n) (((n)&0x7) << 17) #define UL_DFT_PRACH_FORMAT_SEL_CURR(n) (((n)&0x7) << 20) #define UL_DFT_PWRADJ_EN_CURR (1 << 23) #define UL_DFT_FFT_CAL_CURR (1 << 24) #define UL_DFT_FFT_IFFT_SEL_CURR (1 << 25) #define UL_DFT_CLEAR_EN_CURR (1 << 26) #define UL_DFT_SRS_EN_CURR (1 << 27) #define UL_DFT_LAUNCH_EN_CURR (1 << 28) #define UL_DFT_DFT_TRIG_MODE (1 << 29) #define UL_DFT_DFTFFT_SOFT_START (1 << 30) // fft_lnum_srs_curr2 #define UL_DFT_FFT_LNUM1_SRS_CURR(n) (((n)&0x3) << 0) #define UL_DFT_FFT_LNUM2_SRS_CURR(n) (((n)&0x3) << 2) #define UL_DFT_FFT_LNUM3_SRS_CURR(n) (((n)&0x3) << 4) #define UL_DFT_FFT_LNUM4_SRS_CURR(n) (((n)&0x3) << 6) #define UL_DFT_FFT_LNUM5_SRS_CURR(n) (((n)&0x3) << 8) #define UL_DFT_FFT_LNUM6_SRS_CURR(n) (((n)&0x3) << 10) #define UL_DFT_FFT_LNUM7_SRS_CURR(n) (((n)&0x3) << 12) #define UL_DFT_FFT_LNUM8_SRS_CURR(n) (((n)&0x3) << 14) #define UL_DFT_FFT_LNUM9_SRS_CURR(n) (((n)&0x3) << 16) #define UL_DFT_FFT_LNUM10_SRS_CURR(n) (((n)&0x3) << 18) #define UL_DFT_FFT_LNUM11_SRS_CURR(n) (((n)&0x3) << 20) // fft_lnum_scr_curr2 #define UL_DFT_FFT_LNUM1_SCR_CURR(n) (((n)&0x3) << 0) #define UL_DFT_FFT_LNUM2_SCR_CURR(n) (((n)&0x3) << 2) #define UL_DFT_FFT_LNUM3_SCR_CURR(n) (((n)&0x3) << 4) #define UL_DFT_FFT_LNUM4_SCR_CURR(n) (((n)&0x3) << 6) #define UL_DFT_FFT_LNUM5_SCR_CURR(n) (((n)&0x3) << 8) #define UL_DFT_FFT_LNUM6_SCR_CURR(n) (((n)&0x3) << 10) #define UL_DFT_FFT_LNUM7_SCR_CURR(n) (((n)&0x3) << 12) #define UL_DFT_FFT_LNUM8_SCR_CURR(n) (((n)&0x3) << 14) #define UL_DFT_FFT_LNUM9_SCR_CURR(n) (((n)&0x3) << 16) #define UL_DFT_FFT_LNUM10_SCR_CURR(n) (((n)&0x3) << 18) #define UL_DFT_FFT_LNUM11_SCR_CURR(n) (((n)&0x3) << 20) // npus_map_cfg_curr2 #define UL_DFT_NPUS_SUB_SPACE_CURR (1 << 0) #define UL_DFT_N_SLOT_CNT_CURR(n) (((n)&0xff) << 1) #define UL_DFT_ISC_START_INDEX_CURR(n) (((n)&0x3f) << 9) #define UL_DFT_N_RU_SC_CURR(n) (((n)&0x3) << 15) #define UL_DFT_NPUS_REP_CNT_CURR(n) (((n)&0x7f) << 17) // npus_dmrs_cfg_curr2 #define UL_DFT_CYCLIC_SHIFT_CURR(n) (((n)&0x3) << 0) #define UL_DFT_BASE_SEQ_CURR(n) (((n)&0x1f) << 2) #define UL_DFT_SLOT_N_CURR(n) (((n)&0x7fff) << 7) #define UL_DFT_FIRST_RU_SLOT_CURR(n) (((n)&0x1f) << 22) // npra__cfg_curr2 #define UL_DFT_INIT_SC_CURR(n) (((n)&0x3f) << 0) #define UL_DFT_NPRACH_SC_OFFSET_CURR(n) (((n)&0x7) << 6) #define UL_DFT_SYM_GROUP_REP_CNT_CURR(n) (((n)&0xff) << 9) // fsm_state #define UL_DFT_OFDM_STATE(n) (((n)&0xffff) << 0) #define UL_DFT_FRAME_STATE(n) (((n)&0x3fff) << 16) #define UL_DFT_OCP_PA (1 << 30) #define UL_DFT_OCP_PI (1 << 31) // ofdm_count #define UL_DFT_OFDM_COUNT(n) (((n)&0xf) << 0) // fsm_state_assert #define UL_DFT_OFDM_STATE_ASSERT(n) (((n)&0xffff) << 0) #define UL_DFT_FRAME_STATE_ASSERT(n) (((n)&0x3fff) << 16) #define UL_DFT_OCP_PA_ASSERT (1 << 30) #define UL_DFT_OCP_PI_ASSERT (1 << 31) // ofdm_assert #define UL_DFT_OFDM_ASSERT(n) (((n)&0xf) << 0) #endif // _UL_DFT_H_