EC600G/components/hal/include/hwregs/8850/lps_clk_gen.h

/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _LPS_CLK_GEN_H_
#define _LPS_CLK_GEN_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_LPS_CLK_GEN_BASE (0x51708000)

typedef volatile struct
{
    uint32_t __0[8];                           // 0x00000000
    uint32_t soft_cnt_done0_cfg;               // 0x00000020
    uint32_t pll_wait_sel0_cfg;                // 0x00000024
    uint32_t pll_wait_sw_ctl0_cfg;             // 0x00000028
    uint32_t __44[2];                          // 0x0000002c
    uint32_t gate_en_sel0_cfg;                 // 0x00000034
    uint32_t gate_en_sw_ctl0_cfg;              // 0x00000038
    uint32_t monitor_wait_en_status0_cfg;      // 0x0000003c
    uint32_t monitor_gate_auto_en_status0_cfg; // 0x00000040
} HWP_LPS_CLK_GEN_T;

#define hwp_lpsClkGen ((HWP_LPS_CLK_GEN_T *)REG_ACCESS_ADDRESS(REG_LPS_CLK_GEN_BASE))

// soft_cnt_done0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rc26m_26m_soft_cnt_done : 1; // [0]
        uint32_t __31_1 : 31;                 // [31:1]
    } b;
} REG_LPS_CLK_GEN_SOFT_CNT_DONE0_CFG_T;

// pll_wait_sel0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rc26m_26m_wait_auto_gate_sel : 1; // [0]
        uint32_t __31_1 : 31;                      // [31:1]
    } b;
} REG_LPS_CLK_GEN_PLL_WAIT_SEL0_CFG_T;

// pll_wait_sw_ctl0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rc26m_26m_wait_force_en : 1; // [0]
        uint32_t __31_1 : 31;                 // [31:1]
    } b;
} REG_LPS_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_T;

// gate_en_sel0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_rc_26m_lps_auto_gate_sel : 1;  // [0]
        uint32_t cgm_rtc_32k_lps_auto_gate_sel : 1; // [1]
        uint32_t cgm_rc_26m_aon_auto_gate_sel : 1;  // [2]
        uint32_t cgm_rtc_32k_aon_auto_gate_sel : 1; // [3]
        uint32_t cgm_rtc_32k_cp_auto_gate_sel : 1;  // [4]
        uint32_t cgm_rc_26m_ap_auto_gate_sel : 1;   // [5]
        uint32_t cgm_rtc_32k_ap_auto_gate_sel : 1;  // [6]
        uint32_t __31_7 : 25;                       // [31:7]
    } b;
} REG_LPS_CLK_GEN_GATE_EN_SEL0_CFG_T;

// gate_en_sw_ctl0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_rc_26m_lps_force_en : 1;  // [0]
        uint32_t cgm_rtc_32k_lps_force_en : 1; // [1]
        uint32_t cgm_rc_26m_aon_force_en : 1;  // [2]
        uint32_t cgm_rtc_32k_aon_force_en : 1; // [3]
        uint32_t cgm_rtc_32k_cp_force_en : 1;  // [4]
        uint32_t cgm_rc_26m_ap_force_en : 1;   // [5]
        uint32_t cgm_rtc_32k_ap_force_en : 1;  // [6]
        uint32_t __31_7 : 25;                  // [31:7]
    } b;
} REG_LPS_CLK_GEN_GATE_EN_SW_CTL0_CFG_T;

// monitor_wait_en_status0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t monitor_wait_en_status : 1; // [0], read only
        uint32_t __31_1 : 31;                // [31:1]
    } b;
} REG_LPS_CLK_GEN_MONITOR_WAIT_EN_STATUS0_CFG_T;

// monitor_gate_auto_en_status0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t monitor_gate_auto_en_status : 7; // [6:0], read only
        uint32_t __31_7 : 25;                     // [31:7]
    } b;
} REG_LPS_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS0_CFG_T;

// soft_cnt_done0_cfg
#define LPS_CLK_GEN_RC26M_26M_SOFT_CNT_DONE (1 << 0)

// pll_wait_sel0_cfg
#define LPS_CLK_GEN_RC26M_26M_WAIT_AUTO_GATE_SEL (1 << 0)

// pll_wait_sw_ctl0_cfg
#define LPS_CLK_GEN_RC26M_26M_WAIT_FORCE_EN (1 << 0)

// gate_en_sel0_cfg
#define LPS_CLK_GEN_CGM_RC_26M_LPS_AUTO_GATE_SEL (1 << 0)
#define LPS_CLK_GEN_CGM_RTC_32K_LPS_AUTO_GATE_SEL (1 << 1)
#define LPS_CLK_GEN_CGM_RC_26M_AON_AUTO_GATE_SEL (1 << 2)
#define LPS_CLK_GEN_CGM_RTC_32K_AON_AUTO_GATE_SEL (1 << 3)
#define LPS_CLK_GEN_CGM_RTC_32K_CP_AUTO_GATE_SEL (1 << 4)
#define LPS_CLK_GEN_CGM_RC_26M_AP_AUTO_GATE_SEL (1 << 5)
#define LPS_CLK_GEN_CGM_RTC_32K_AP_AUTO_GATE_SEL (1 << 6)

// gate_en_sw_ctl0_cfg
#define LPS_CLK_GEN_CGM_RC_26M_LPS_FORCE_EN (1 << 0)
#define LPS_CLK_GEN_CGM_RTC_32K_LPS_FORCE_EN (1 << 1)
#define LPS_CLK_GEN_CGM_RC_26M_AON_FORCE_EN (1 << 2)
#define LPS_CLK_GEN_CGM_RTC_32K_AON_FORCE_EN (1 << 3)
#define LPS_CLK_GEN_CGM_RTC_32K_CP_FORCE_EN (1 << 4)
#define LPS_CLK_GEN_CGM_RC_26M_AP_FORCE_EN (1 << 5)
#define LPS_CLK_GEN_CGM_RTC_32K_AP_FORCE_EN (1 << 6)

// monitor_wait_en_status0_cfg
#define LPS_CLK_GEN_MONITOR_WAIT_EN_STATUS (1 << 0)

// monitor_gate_auto_en_status0_cfg
#define LPS_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS(n) (((n)&0x7f) << 0)

#endif // _LPS_CLK_GEN_H_