EC600G/components/hal/include/hwregs/8850/rf_dfe.h

/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _RF_DFE_H_
#define _RF_DFE_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_RF_DFE_BASE (0x50032000)

typedef volatile struct
{
    uint32_t general_mode;                   // 0x00000000
    uint32_t dfe_clock_gate_enable_reg;      // 0x00000004
    uint32_t rxdp_dcc;                       // 0x00000008
    uint32_t rxdp_dc_calib_re;               // 0x0000000c
    uint32_t rxdp_dc_calib_im;               // 0x00000010
    uint32_t rxdp_dc_delta_re;               // 0x00000014
    uint32_t rxdp_dc_delta_im;               // 0x00000018
    uint32_t rxdp_dc_cr;                     // 0x0000001c
    uint32_t rxdp_gain_ct_reg;               // 0x00000020
    uint32_t __36[5];                        // 0x00000024
    uint32_t rxdp_gdeq_coef0_rg_1;           // 0x00000038
    uint32_t rxdp_gdeq_coef0_rg_2;           // 0x0000003c
    uint32_t rxdp_gdeq_coef1_rg_1;           // 0x00000040
    uint32_t rxdp_gdeq_coef1_rg_2;           // 0x00000044
    uint32_t rxdp_gdeq_coef2_rg_1;           // 0x00000048
    uint32_t rxdp_gdeq_coef2_rg_2;           // 0x0000004c
    uint32_t rxdp_gdeq_coef3_rg_1;           // 0x00000050
    uint32_t rxdp_gdeq_coef3_rg_2;           // 0x00000054
    uint32_t rxdp_adc_wr_buf_fifo;           // 0x00000058
    uint32_t __92[2];                        // 0x0000005c
    uint32_t rxdp_dcc_valid_o_reg;           // 0x00000064
    uint32_t rxdp_dcc_re_o_reg;              // 0x00000068
    uint32_t rxdp_dcc_im_o_reg;              // 0x0000006c
    uint32_t rxdp_notch_ct;                  // 0x00000070
    uint32_t rxdp_notch_a0_i_reg;            // 0x00000074
    uint32_t rxdp_notch_a0_q_reg;            // 0x00000078
    uint32_t rxdp_notch_k_reg;               // 0x0000007c
    uint32_t rxdp_mirror_remove;             // 0x00000080
    uint32_t rxdp_notch2_ct;                 // 0x00000084
    uint32_t rxdp_notch2_a0_i_reg;           // 0x00000088
    uint32_t rxdp_notch2_a0_q_reg;           // 0x0000008c
    uint32_t rxdp_notch2_a1_i_reg;           // 0x00000090
    uint32_t rxdp_notch2_a1_q_reg;           // 0x00000094
    uint32_t rxdp_notch2_k_reg;              // 0x00000098
    uint32_t rxdp_aci_filter_coef0_reg;      // 0x0000009c
    uint32_t rxdp_aci_filter_coef1_reg;      // 0x000000a0
    uint32_t rxdp_aci_filter_coef2_reg;      // 0x000000a4
    uint32_t rxdp_aci_filter_coef3_reg;      // 0x000000a8
    uint32_t rxdp_aci_filter_coef4_reg;      // 0x000000ac
    uint32_t rxdp_aci_filter_coef5_reg;      // 0x000000b0
    uint32_t rxdp_aci_filter_coef6_reg;      // 0x000000b4
    uint32_t rxdp_aci_filter_coef7_reg;      // 0x000000b8
    uint32_t rxdp_aci_filter_coef8_reg;      // 0x000000bc
    uint32_t rxdp_aci_filter_coef9_reg;      // 0x000000c0
    uint32_t rxdp_aci_filter_coef10_reg;     // 0x000000c4
    uint32_t rxdp_aci_filter_coef11_reg;     // 0x000000c8
    uint32_t rxdp_aci_filter_coef12_reg;     // 0x000000cc
    uint32_t rxdp_aci_filter_coef13_reg;     // 0x000000d0
    uint32_t rxdp_aci_filter_coef14_reg;     // 0x000000d4
    uint32_t rxdp_aci_filter_coef15_reg;     // 0x000000d8
    uint32_t rxdp_aci_filter_coef16_reg;     // 0x000000dc
    uint32_t rxdp_aci_filter_coef17_reg;     // 0x000000e0
    uint32_t rxdp_aci_filter_coef18_reg;     // 0x000000e4
    uint32_t rxdp_aci_filter_coef19_reg;     // 0x000000e8
    uint32_t rxdp_aci_filter_coef20_reg;     // 0x000000ec
    uint32_t rxdp_aci_filter_coef21_reg;     // 0x000000f0
    uint32_t rxdp_aci_filter_coef22_reg;     // 0x000000f4
    uint32_t rxdp_aci_filter_coef23_reg;     // 0x000000f8
    uint32_t rxdp_mixer_freq_in_reg0;        // 0x000000fc
    uint32_t rxdp_mixer_freq_in_reg1;        // 0x00000100
    uint32_t rxdp_rssi_reg;                  // 0x00000104
    uint32_t rxdp_imbc_wa_reg;               // 0x00000108
    uint32_t rxdp_imbc_wq_reg;               // 0x0000010c
    uint32_t rxdp_imbc_misc_reg;             // 0x00000110
    uint32_t rxdp_imbc_wa_out_reg;           // 0x00000114
    uint32_t rxdp_imbc_wq_out_reg;           // 0x00000118
    uint32_t rxdp_imbc_out_reg;              // 0x0000011c
    uint32_t rxdp_rc_rate_ofs_period_reg;    // 0x00000120
    uint32_t rxdp_rc_rate_ofs_hi_reg;        // 0x00000124
    uint32_t rxdp_rc_rate_ofs_lo_reg;        // 0x00000128
    uint32_t start_max_min_ib_rssi_reg;      // 0x0000012c
    uint32_t count_16lsb_ib_rssi_reg;        // 0x00000130
    uint32_t count_16msb_ib_rssi_reg;        // 0x00000134
    uint32_t load_max_min_ib_rssi_reg;       // 0x00000138
    uint32_t rssi_min_ib_rssi;               // 0x0000013c
    uint32_t rssi_max_ib_rssi;               // 0x00000140
    uint32_t int_ib_rssi;                    // 0x00000144
    uint32_t load_ib_rssi_reg;               // 0x00000148
    uint32_t rssi_val_ib_rssi;               // 0x0000014c
    uint32_t rssi_ib_rssi;                   // 0x00000150
    uint32_t start_max_min_ob_rssi_reg;      // 0x00000154
    uint32_t count_16lsb_ob_rssi_reg;        // 0x00000158
    uint32_t count_16msb_ob_rssi_reg;        // 0x0000015c
    uint32_t load_max_min_ob_rssi_reg;       // 0x00000160
    uint32_t rssi_max_min_val_ob_rssi;       // 0x00000164
    uint32_t rssi_min_ob_rssi;               // 0x00000168
    uint32_t rssi_max_ob_rssi;               // 0x0000016c
    uint32_t int_ob_rssi;                    // 0x00000170
    uint32_t load_ob_rssi_reg;               // 0x00000174
    uint32_t rssi_val_ob_rssi;               // 0x00000178
    uint32_t rssi_wd_ob_rssi;                // 0x0000017c
    uint32_t rssi_up_ob_rssi;                // 0x00000180
    uint32_t rssi_dn_ob_rssi;                // 0x00000184
    uint32_t rxdp_rc_stretch_reg;            // 0x00000188
    uint32_t rxdp_rc_rate_ofs_rest_reg;      // 0x0000018c
    uint32_t rxdp_bypass_control_reg1;       // 0x00000190
    uint32_t rxdp_bypass_control_reg2;       // 0x00000194
    uint32_t rxdp_bypass_mode_control_reg1;  // 0x00000198
    uint32_t rxdp_bypass_mode_control_reg2;  // 0x0000019c
    uint32_t rxdp_dcc_re_real_reg;           // 0x000001a0
    uint32_t rxdp_dcc_im_real_reg;           // 0x000001a4
    uint32_t rssi_real_ib_rssi;              // 0x000001a8
    uint32_t rssi_wd_real_ob_rssi;           // 0x000001ac
    uint32_t rssi_up_real_ob_rssi;           // 0x000001b0
    uint32_t rssi_dn_real_ob_rssi;           // 0x000001b4
    uint32_t rxdp_imbc_wa_out_real_reg;      // 0x000001b8
    uint32_t rxdp_imbc_wq_out_real_reg;      // 0x000001bc
    uint32_t start_max_min_rssi3_reg;        // 0x000001c0
    uint32_t count_16lsb_rssi3_reg;          // 0x000001c4
    uint32_t count_16msb_rssi3_reg;          // 0x000001c8
    uint32_t load_max_min_rssi3_reg;         // 0x000001cc
    uint32_t rssi_min_rssi3;                 // 0x000001d0
    uint32_t rssi_max_rssi3;                 // 0x000001d4
    uint32_t int_rssi3;                      // 0x000001d8
    uint32_t load_rssi3_reg;                 // 0x000001dc
    uint32_t rssi_val_rssi3;                 // 0x000001e0
    uint32_t rssi_rssi3;                     // 0x000001e4
    uint32_t rssi_real_rssi3;                // 0x000001e8
    uint32_t rxdp_notch_cordic_enable_reg;   // 0x000001ec
    uint32_t rxdp_notch1_cordic_amp_reg;     // 0x000001f0
    uint32_t rxdp_notch1_cordic_zin_reg;     // 0x000001f4
    uint32_t rxdp_notch2_cordic0_amp_reg;    // 0x000001f8
    uint32_t rxdp_notch2_cordic0_zin_reg;    // 0x000001fc
    uint32_t rxdp_notch2_cordic1_amp_reg;    // 0x00000200
    uint32_t rxdp_notch2_cordic1_zin_reg;    // 0x00000204
    uint32_t txdp_cfr_th_liner_reg;          // 0x00000208
    uint32_t txdp_sine_rate_reg;             // 0x0000020c
    uint32_t txdp_rc_stretch_reg;            // 0x00000210
    uint32_t txdp_rc_rate_ofs_rest_reg;      // 0x00000214
    uint32_t txdp_rc_rate_ofs_period_reg;    // 0x00000218
    uint32_t txdp_rc_rate_ofs_hi_reg;        // 0x0000021c
    uint32_t txdp_rc_rate_ofs_lo_reg;        // 0x00000220
    uint32_t clk_convert_rate_reg;           // 0x00000224
    uint32_t rxdp_notch1_cordic_dout_i_reg;  // 0x00000228
    uint32_t rxdp_notch1_cordic_dout_q_reg;  // 0x0000022c
    uint32_t rxdp_notch2_cordic0_dout_i_reg; // 0x00000230
    uint32_t rxdp_notch2_cordic0_dout_q_reg; // 0x00000234
    uint32_t rxdp_notch2_cordic1_dout_i_reg; // 0x00000238
    uint32_t rxdp_notch2_cordic1_dout_q_reg; // 0x0000023c
    uint32_t rxdp_notch_gen_val_reg;         // 0x00000240
    uint32_t resetn_notch_gen_reg;           // 0x00000244
    uint32_t dfe_dump_smp_rate_reg;          // 0x00000248
    uint32_t __588[45];                      // 0x0000024c
    uint32_t txdp_wedge_gain_ct_reg;         // 0x00000300
    uint32_t __772[21];                      // 0x00000304
    uint32_t txdp_wedge_am_shrink_reg;       // 0x00000358
    uint32_t __860[1];                       // 0x0000035c
    uint32_t txdp_wedge_pm_shift_reg;        // 0x00000360
    uint32_t txdp_wedge_am_p0_reg;           // 0x00000364
    uint32_t txdp_wedge_am_p1_reg;           // 0x00000368
    uint32_t txdp_wedge_am_p2_reg;           // 0x0000036c
    uint32_t txdp_wedge_am_p3_reg;           // 0x00000370
    uint32_t txdp_wedge_am_p4_reg;           // 0x00000374
    uint32_t txdp_wedge_am_p5_reg;           // 0x00000378
    uint32_t txdp_wedge_am_p6_reg;           // 0x0000037c
    uint32_t txdp_wedge_am_p7_reg;           // 0x00000380
    uint32_t txdp_wedge_am_p8_reg;           // 0x00000384
    uint32_t txdp_wedge_am_p9_reg;           // 0x00000388
    uint32_t txdp_wedge_am_p10_reg;          // 0x0000038c
    uint32_t txdp_wedge_am_p11_reg;          // 0x00000390
    uint32_t txdp_wedge_am_p12_reg;          // 0x00000394
    uint32_t txdp_wedge_am_p13_reg;          // 0x00000398
    uint32_t txdp_wedge_am_p14_reg;          // 0x0000039c
    uint32_t txdp_wedge_am_p15_reg;          // 0x000003a0
    uint32_t txdp_wedge_am_p16_reg;          // 0x000003a4
    uint32_t txdp_wedge_pm_p0_reg;           // 0x000003a8
    uint32_t txdp_wedge_pm_p1_reg;           // 0x000003ac
    uint32_t txdp_wedge_pm_p2_reg;           // 0x000003b0
    uint32_t txdp_wedge_pm_p3_reg;           // 0x000003b4
    uint32_t txdp_wedge_pm_p4_reg;           // 0x000003b8
    uint32_t txdp_wedge_pm_p5_reg;           // 0x000003bc
    uint32_t txdp_wedge_pm_p6_reg;           // 0x000003c0
    uint32_t txdp_wedge_pm_p7_reg;           // 0x000003c4
    uint32_t txdp_wedge_pm_p8_reg;           // 0x000003c8
    uint32_t txdp_wedge_pm_p9_reg;           // 0x000003cc
    uint32_t txdp_wedge_pm_p10_reg;          // 0x000003d0
    uint32_t txdp_wedge_pm_p11_reg;          // 0x000003d4
    uint32_t txdp_wedge_pm_p12_reg;          // 0x000003d8
    uint32_t txdp_wedge_pm_p13_reg;          // 0x000003dc
    uint32_t txdp_wedge_pm_p14_reg;          // 0x000003e0
    uint32_t txdp_wedge_pm_p15_reg;          // 0x000003e4
    uint32_t txdp_wedge_pm_p16_reg;          // 0x000003e8
    uint32_t __1004[1];                      // 0x000003ec
    uint32_t aclr_coef4;                     // 0x000003f0
    uint32_t aclr_coef5;                     // 0x000003f4
    uint32_t aclr_coef6;                     // 0x000003f8
    uint32_t aclr_coef7;                     // 0x000003fc
    uint32_t clk_convert_rate_load;          // 0x00000400
    uint32_t clk_dac_ctrl;                   // 0x00000404
    uint32_t txdp_delay_reg;                 // 0x00000408
    uint32_t aclr_coef0;                     // 0x0000040c
    uint32_t aclr_coef1;                     // 0x00000410
    uint32_t aclr_coef2;                     // 0x00000414
    uint32_t aclr_coef3;                     // 0x00000418
    uint32_t txdp_gdeq_coef0_rg_1;           // 0x0000041c
    uint32_t txdp_gdeq_coef0_rg_2;           // 0x00000420
    uint32_t txdp_gdeq_coef1_rg_1;           // 0x00000424
    uint32_t txdp_gdeq_coef1_rg_2;           // 0x00000428
    uint32_t txdp_gdeq_coef2_rg_1;           // 0x0000042c
    uint32_t txdp_gdeq_coef2_rg_2;           // 0x00000430
    uint32_t txdp_gdeq_coef3_rg_1;           // 0x00000434
    uint32_t txdp_gdeq_coef3_rg_2;           // 0x00000438
    uint32_t __1084[12];                     // 0x0000043c
    uint32_t txdp_loft_offset_i_reg;         // 0x0000046c
    uint32_t txdp_loft_offset_reg;           // 0x00000470
    uint32_t txdp_loft_phase_err_reg;        // 0x00000474
    uint32_t txdp_loft_amp_err_reg;          // 0x00000478
    uint32_t txdp_loft_rssi_reg;             // 0x0000047c
    uint32_t txdp_loft_tone_amp_reg;         // 0x00000480
    uint32_t txdp_loft_tone_fre_reg0;        // 0x00000484
    uint32_t txdp_loft_tone_fre_reg1;        // 0x00000488
    uint32_t txdp_loft_misc0_reg;            // 0x0000048c
    uint32_t txdp_loft_gain1_reg;            // 0x00000490
    uint32_t data_format_ctrl;               // 0x00000494
    uint32_t txdp_loft_rssi_reg_real;        // 0x00000498
    uint32_t __1180[1];                      // 0x0000049c
    uint32_t temper_tsx_ct;                  // 0x000004a0
    uint32_t temper_tsx_dout_reg;            // 0x000004a4
    uint32_t tsx_temp_clk_ct;                // 0x000004a8
    uint32_t temper_tsx_lpf_a11_rg;          // 0x000004ac
    uint32_t temper_tsx_lpf_a12_rg;          // 0x000004b0
    uint32_t temper_tsx_lpf_g1_rg;           // 0x000004b4
    uint32_t temper_tsx_lpf_a21_rg;          // 0x000004b8
    uint32_t temper_tsx_lpf_a22_rg;          // 0x000004bc
    uint32_t temper_tsx_lpf_g2_rg;           // 0x000004c0
    uint32_t temper_tsx_dout_real_reg;       // 0x000004c4
    uint32_t __1224[14];                     // 0x000004c8
    uint32_t temper_ct;                      // 0x00000500
    uint32_t temper_dout_reg;                // 0x00000504
    uint32_t osc_temp_clk_ct;                // 0x00000508
    uint32_t __1292[2];                      // 0x0000050c
    uint32_t temper_lpf_a11_rg;              // 0x00000514
    uint32_t temper_lpf_a12_rg;              // 0x00000518
    uint32_t temper_lpf_g1_rg;               // 0x0000051c
    uint32_t temper_lpf_a21_rg;              // 0x00000520
    uint32_t temper_lpf_a22_rg;              // 0x00000524
    uint32_t temper_lpf_g2_rg;               // 0x00000528
    uint32_t __1324[8];                      // 0x0000052c
    uint32_t temper_dout_real_reg;           // 0x0000054c
    uint32_t __1360[1];                      // 0x00000550
    uint32_t dfe_sw_clkgate_en_rg;           // 0x00000554
    uint32_t mon_ct;                         // 0x00000558
    uint32_t dac_offset_re_rg;               // 0x0000055c
    uint32_t dac_offset_im_rg;               // 0x00000560
    uint32_t dac_tx_amp_re_rg;               // 0x00000564
    uint32_t dac_tx_amp_im_rg;               // 0x00000568
    uint32_t __1388[1];                      // 0x0000056c
    uint32_t data_dac_ctrl;                  // 0x00000570
    uint32_t sincos_amp;                     // 0x00000574
    uint32_t sincos_fre_lo;                  // 0x00000578
    uint32_t sincos_fre_hi;                  // 0x0000057c
    uint32_t txdp_bypass_reg;                // 0x00000580
    uint32_t txdp_bypass_mode_reg;           // 0x00000584
    uint32_t __1416[2];                      // 0x00000588
    uint32_t reserved_all_zeros_reg;         // 0x00000590
    uint32_t reserved_all_ones_reg;          // 0x00000594
    uint32_t pwr_rf_acc_len_reg;             // 0x00000598
    uint32_t pwr_rf_acc_misc_reg;            // 0x0000059c
    uint32_t pwr_rf_acc_report_reg;          // 0x000005a0
    uint32_t __1444[3];                      // 0x000005a4
    uint32_t txdp_clk_gate_enable_reg;       // 0x000005b0
    uint32_t rxdp_clk_gate_enable_reg2;      // 0x000005b4
    uint32_t rxdp_clk_gate_enable_reg1;      // 0x000005b8
    uint32_t test_dac_bits_sel_register;     // 0x000005bc
    uint32_t txdp_ampequ_coef0_rg_1;         // 0x000005c0
    uint32_t txdp_ampequ_coef1_rg_1;         // 0x000005c4
    uint32_t txdp_ampequ_coef2_rg_1;         // 0x000005c8
    uint32_t txdp_ampequ_coef3_rg_1;         // 0x000005cc
    uint32_t txdp_ampequ_g;                  // 0x000005d0
    uint32_t txdp_ampequ_g_ext_reg;          // 0x000005d4
    uint32_t fifo_sample_rate_reg1;          // 0x000005d8
    uint32_t __1500[1];                      // 0x000005dc
    uint32_t fifo_status_reg;                // 0x000005e0
    uint32_t __1508[1];                      // 0x000005e4
    uint32_t dfe_dump_reg;                   // 0x000005e8
    uint32_t aclr_coef8;                     // 0x000005ec
    uint32_t aclr_coef9;                     // 0x000005f0
    uint32_t aclr_coef10;                    // 0x000005f4
    uint32_t aclr_coef11;                    // 0x000005f8
    uint32_t aclr_coef12;                    // 0x000005fc
    uint32_t aclr_coef13;                    // 0x00000600
    uint32_t aclr_coef14;                    // 0x00000604
    uint32_t aclr_coef15;                    // 0x00000608
    uint32_t aclr_coef16;                    // 0x0000060c
    uint32_t aclr_coef17;                    // 0x00000610
    uint32_t aclr_coef18;                    // 0x00000614
    uint32_t aclr_coef19;                    // 0x00000618
    uint32_t aclr_coef20;                    // 0x0000061c
    uint32_t aclr_coef21;                    // 0x00000620
    uint32_t aclr_coef22;                    // 0x00000624
    uint32_t aclr_coef23;                    // 0x00000628
    uint32_t pwd_dcc;                        // 0x0000062c
    uint32_t pwd_dc_calib_re;                // 0x00000630
    uint32_t pwd_dc_calib_im;                // 0x00000634
    uint32_t pwd_dc_delta_re;                // 0x00000638
    uint32_t pwd_dc_delta_im;                // 0x0000063c
    uint32_t pwd_dc_cr;                      // 0x00000640
    uint32_t pwd_dcc_valid_o_reg;            // 0x00000644
    uint32_t pwd_dcc_re_o_reg;               // 0x00000648
    uint32_t pwd_dcc_im_o_reg;               // 0x0000064c
    uint32_t pwd_dcc_re_real_reg;            // 0x00000650
    uint32_t pwd_dcc_im_real_reg;            // 0x00000654
} HWP_RF_DFE_T;

#define hwp_rfDfe ((HWP_RF_DFE_T *)REG_ACCESS_ADDRESS(REG_RF_DFE_BASE))

// general_mode
typedef union {
    uint32_t v;
    struct
    {
        uint32_t zf_if_mode : 1;       // [0]
        uint32_t adc_clk_mode : 2;     // [2:1]
        uint32_t __3_3 : 1;            // [3]
        uint32_t rx_mode : 4;          // [7:4]
        uint32_t __11_8 : 4;           // [11:8]
        uint32_t clk_adc_inv_mode : 1; // [12]
        uint32_t clk_dac_inv_mode : 1; // [13]
        uint32_t reset_mode : 1;       // [14]
        uint32_t __31_15 : 17;         // [31:15]
    } b;
} REG_RF_DFE_GENERAL_MODE_T;

// dfe_clock_gate_enable_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_adc_clk_en : 1;     // [0]
        uint32_t txdp_clk_dac_en : 1;     // [1]
        uint32_t rxdp_dfe_clk_en : 1;     // [2]
        uint32_t __3_3 : 1;               // [3]
        uint32_t txdp_nb_dfe_clk_en : 1;  // [4]
        uint32_t __5_5 : 1;               // [5]
        uint32_t clk_122p88m_en : 1;      // [6]
        uint32_t __7_7 : 1;               // [7]
        uint32_t clk_rate_convert_rg : 1; // [8]
        uint32_t sw_resetn : 1;           // [9]
        uint32_t __12_10 : 3;             // [12:10]
        uint32_t txdp_loft_mode : 1;      // [13]
        uint32_t reg_clkgate_en : 1;      // [14]
        uint32_t __31_15 : 17;            // [31:15]
    } b;
} REG_RF_DFE_DFE_CLOCK_GATE_ENABLE_REG_T;

// rxdp_dcc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dcc_rx_calib_sel_rg : 1;   // [0]
        uint32_t dcc_dc_calib_en_rg : 1;    // [1]
        uint32_t dcc_dc_delta_ld_st_rg : 1; // [2]
        uint32_t dcc_bypass_rg : 1;         // [3]
        uint32_t dcc_hold_en_rg : 1;        // [4]
        uint32_t dcc_imgrej_rg : 1;         // [5]
        uint32_t rxdp_dcc_load : 1;         // [6]
        uint32_t __31_7 : 25;               // [31:7]
    } b;
} REG_RF_DFE_RXDP_DCC_T;

// rxdp_dc_calib_re
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_dc_calib_re_rg : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_DC_CALIB_RE_T;

// rxdp_dc_calib_im
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_dc_calib_im_rg : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_DC_CALIB_IM_T;

// rxdp_dc_delta_re
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_dc_delta_re_rg : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_DC_DELTA_RE_T;

// rxdp_dc_delta_im
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_dc_delta_im_rg : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_DC_DELTA_IM_T;

// rxdp_dc_cr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t conv_mode_ct_rg : 2;    // [1:0]
        uint32_t conv_tmr_ct_rg : 4;     // [5:2]
        uint32_t conv_fast_bw_ct_rg : 3; // [8:6]
        uint32_t conv_slow_bw_ct_rg : 3; // [11:9]
        uint32_t __31_12 : 20;           // [31:12]
    } b;
} REG_RF_DFE_RXDP_DC_CR_T;

// rxdp_gain_ct_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_gain_ct : 11;            // [10:0]
        uint32_t __11_11 : 1;                  // [11]
        uint32_t rxdp_gain_ct_load_bypass : 1; // [12]
        uint32_t rxdp_gain_ct_load : 1;        // [13]
        uint32_t __31_14 : 18;                 // [31:14]
    } b;
} REG_RF_DFE_RXDP_GAIN_CT_REG_T;

// rxdp_gdeq_coef0_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_gdeq_coef0_rg_lo : 16; // [15:0]
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_DFE_RXDP_GDEQ_COEF0_RG_1_T;

// rxdp_gdeq_coef0_rg_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_gdeq_coef0_rg_hi : 4; // [3:0]
        uint32_t __31_4 : 28;               // [31:4]
    } b;
} REG_RF_DFE_RXDP_GDEQ_COEF0_RG_2_T;

// rxdp_gdeq_coef1_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_gdeq_coef1_rg_lo : 16; // [15:0]
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_DFE_RXDP_GDEQ_COEF1_RG_1_T;

// rxdp_gdeq_coef1_rg_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_gdeq_coef1_rg_hi : 4; // [3:0]
        uint32_t __31_4 : 28;               // [31:4]
    } b;
} REG_RF_DFE_RXDP_GDEQ_COEF1_RG_2_T;

// rxdp_gdeq_coef2_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_gdeq_coef2_rg_lo : 16; // [15:0]
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_DFE_RXDP_GDEQ_COEF2_RG_1_T;

// rxdp_gdeq_coef2_rg_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_gdeq_coef2_rg_hi : 4; // [3:0]
        uint32_t __31_4 : 28;               // [31:4]
    } b;
} REG_RF_DFE_RXDP_GDEQ_COEF2_RG_2_T;

// rxdp_gdeq_coef3_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_gdeq_coef3_rg_lo : 16; // [15:0]
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_DFE_RXDP_GDEQ_COEF3_RG_1_T;

// rxdp_gdeq_coef3_rg_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_gdeq_coef3_rg_hi : 4; // [3:0]
        uint32_t rxdp_gdeq_bp_lp_sel : 1;   // [4]
        uint32_t __31_5 : 27;               // [31:5]
    } b;
} REG_RF_DFE_RXDP_GDEQ_COEF3_RG_2_T;

// rxdp_adc_wr_buf_fifo
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_adc_wr_en_rg : 1;    // [0]
        uint32_t rxdp_adc_smp_rate_rg : 6; // [6:1]
        uint32_t __31_7 : 25;              // [31:7]
    } b;
} REG_RF_DFE_RXDP_ADC_WR_BUF_FIFO_T;

// rxdp_dcc_valid_o_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_dcc_val_reg : 1; // [0], read only
        uint32_t __31_1 : 31;          // [31:1]
    } b;
} REG_RF_DFE_RXDP_DCC_VALID_O_REG_T;

// rxdp_dcc_re_o_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_dcc_re_o : 16; // [15:0], read only
        uint32_t __31_16 : 16;       // [31:16]
    } b;
} REG_RF_DFE_RXDP_DCC_RE_O_REG_T;

// rxdp_dcc_im_o_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_dcc_im_o : 16; // [15:0], read only
        uint32_t __31_16 : 16;       // [31:16]
    } b;
} REG_RF_DFE_RXDP_DCC_IM_O_REG_T;

// rxdp_notch_ct
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch_dataen1 : 1; // [0]
        uint32_t rxdp_notch_dataen0 : 1; // [1]
        uint32_t __31_2 : 30;            // [31:2]
    } b;
} REG_RF_DFE_RXDP_NOTCH_CT_T;

// rxdp_notch_a0_i_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch_a0_i : 12; // [11:0]
        uint32_t __31_12 : 20;         // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH_A0_I_REG_T;

// rxdp_notch_a0_q_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch_a0_q : 12; // [11:0]
        uint32_t __31_12 : 20;         // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH_A0_Q_REG_T;

// rxdp_notch_k_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch_k0 : 6; // [5:0]
        uint32_t __31_6 : 26;       // [31:6]
    } b;
} REG_RF_DFE_RXDP_NOTCH_K_REG_T;

// rxdp_mirror_remove
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_mrrm_bw_sel : 2; // [1:0]
        uint32_t __31_2 : 30;          // [31:2]
    } b;
} REG_RF_DFE_RXDP_MIRROR_REMOVE_T;

// rxdp_notch2_ct
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_dataen1 : 1; // [0]
        uint32_t rxdp_notch2_dataen0 : 1; // [1]
        uint32_t __31_2 : 30;             // [31:2]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_CT_T;

// rxdp_notch2_a0_i_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_a0_i : 12; // [11:0]
        uint32_t __31_12 : 20;          // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_A0_I_REG_T;

// rxdp_notch2_a0_q_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_a0_q : 12; // [11:0]
        uint32_t __31_12 : 20;          // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_A0_Q_REG_T;

// rxdp_notch2_a1_i_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_a1_i : 12; // [11:0]
        uint32_t __31_12 : 20;          // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_A1_I_REG_T;

// rxdp_notch2_a1_q_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_a1_q : 12; // [11:0]
        uint32_t __31_12 : 20;          // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_A1_Q_REG_T;

// rxdp_notch2_k_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_k1 : 6; // [5:0]
        uint32_t rxdp_notch2_k0 : 6; // [11:6]
        uint32_t __31_12 : 20;       // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_K_REG_T;

// rxdp_aci_filter_coef0_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef0 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF0_REG_T;

// rxdp_aci_filter_coef1_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef1 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF1_REG_T;

// rxdp_aci_filter_coef2_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef2 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF2_REG_T;

// rxdp_aci_filter_coef3_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef3 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF3_REG_T;

// rxdp_aci_filter_coef4_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef4 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF4_REG_T;

// rxdp_aci_filter_coef5_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef5 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF5_REG_T;

// rxdp_aci_filter_coef6_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef6 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF6_REG_T;

// rxdp_aci_filter_coef7_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef7 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF7_REG_T;

// rxdp_aci_filter_coef8_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef8 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF8_REG_T;

// rxdp_aci_filter_coef9_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef9 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF9_REG_T;

// rxdp_aci_filter_coef10_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef10 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF10_REG_T;

// rxdp_aci_filter_coef11_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef11 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF11_REG_T;

// rxdp_aci_filter_coef12_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef12 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF12_REG_T;

// rxdp_aci_filter_coef13_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef13 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF13_REG_T;

// rxdp_aci_filter_coef14_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef14 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF14_REG_T;

// rxdp_aci_filter_coef15_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef15 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF15_REG_T;

// rxdp_aci_filter_coef16_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef16 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF16_REG_T;

// rxdp_aci_filter_coef17_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef17 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF17_REG_T;

// rxdp_aci_filter_coef18_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef18 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF18_REG_T;

// rxdp_aci_filter_coef19_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef19 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF19_REG_T;

// rxdp_aci_filter_coef20_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef20 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF20_REG_T;

// rxdp_aci_filter_coef21_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef21 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF21_REG_T;

// rxdp_aci_filter_coef22_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef22 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF22_REG_T;

// rxdp_aci_filter_coef23_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_aci_fir_coef23 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_ACI_FILTER_COEF23_REG_T;

// rxdp_mixer_freq_in_reg0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_mixer_freq_p0 : 16; // [15:0]
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_RXDP_MIXER_FREQ_IN_REG0_T;

// rxdp_mixer_freq_in_reg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_mixer_freq_p1 : 8; // [7:0]
        uint32_t __31_8 : 24;            // [31:8]
    } b;
} REG_RF_DFE_RXDP_MIXER_FREQ_IN_REG1_T;

// rxdp_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_rssi_ib_ushift : 3; // [2:0]
        uint32_t rxdp_rssi_ob_ushift : 3; // [5:3]
        uint32_t rxdp_rssi_ib_enable : 1; // [6]
        uint32_t rxdp_rssi_ob_enable : 1; // [7]
        uint32_t rxdp_rssi3_ushift : 3;   // [10:8]
        uint32_t rxdp_rssi3_enable : 1;   // [11]
        uint32_t __31_12 : 20;            // [31:12]
    } b;
} REG_RF_DFE_RXDP_RSSI_REG_T;

// rxdp_imbc_wa_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_imbc_wa : 16; // [15:0]
        uint32_t __31_16 : 16;      // [31:16]
    } b;
} REG_RF_DFE_RXDP_IMBC_WA_REG_T;

// rxdp_imbc_wq_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_imbc_wq : 16; // [15:0]
        uint32_t __31_16 : 16;      // [31:16]
    } b;
} REG_RF_DFE_RXDP_IMBC_WQ_REG_T;

// rxdp_imbc_misc_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_imbc_load : 1;          // [0]
        uint32_t rxdp_imbc_calc_rels : 1;     // [1]
        uint32_t rxdp_imbc_hold_dr : 1;       // [2]
        uint32_t rxdp_imbc_bw_slow_ct : 4;    // [6:3]
        uint32_t rxdp_imbc_bw_fast_ct_rg : 4; // [10:7]
        uint32_t __31_11 : 21;                // [31:11]
    } b;
} REG_RF_DFE_RXDP_IMBC_MISC_REG_T;

// rxdp_imbc_wa_out_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_imbc_wa_out : 16; // [15:0], read only
        uint32_t __31_16 : 16;          // [31:16]
    } b;
} REG_RF_DFE_RXDP_IMBC_WA_OUT_REG_T;

// rxdp_imbc_wq_out_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_imbc_wq_out : 16; // [15:0], read only
        uint32_t __31_16 : 16;          // [31:16]
    } b;
} REG_RF_DFE_RXDP_IMBC_WQ_OUT_REG_T;

// rxdp_imbc_out_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_imbc_val_out : 1; // [0], read only
        uint32_t __31_1 : 31;           // [31:1]
    } b;
} REG_RF_DFE_RXDP_IMBC_OUT_REG_T;

// rxdp_rc_rate_ofs_period_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_rc_rate_ofs_period : 10; // [9:0]
        uint32_t __31_10 : 22;                 // [31:10]
    } b;
} REG_RF_DFE_RXDP_RC_RATE_OFS_PERIOD_REG_T;

// rxdp_rc_rate_ofs_hi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_rc_rate_ofs_hi : 8; // [7:0]
        uint32_t __31_8 : 24;             // [31:8]
    } b;
} REG_RF_DFE_RXDP_RC_RATE_OFS_HI_REG_T;

// rxdp_rc_rate_ofs_lo_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_rc_rate_ofs_lo : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_RXDP_RC_RATE_OFS_LO_REG_T;

// start_max_min_ib_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t start_max_min_ib_rssi : 1; // [0]
        uint32_t __31_1 : 31;               // [31:1]
    } b;
} REG_RF_DFE_START_MAX_MIN_IB_RSSI_REG_T;

// count_16lsb_ib_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t count_16lsb_ib_rssi : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_COUNT_16LSB_IB_RSSI_REG_T;

// count_16msb_ib_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t count_16msb_ib_rssi : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_COUNT_16MSB_IB_RSSI_REG_T;

// load_max_min_ib_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t load_max_min_ib_rssi : 1; // [0]
        uint32_t __31_1 : 31;              // [31:1]
    } b;
} REG_RF_DFE_LOAD_MAX_MIN_IB_RSSI_REG_T;

// rssi_min_ib_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_min_reg_ib_rssi : 10;        // [9:0], read only
        uint32_t rssi_max_min_val_reg_ib_rssi : 1; // [10], read only
        uint32_t __31_11 : 21;                     // [31:11]
    } b;
} REG_RF_DFE_RSSI_MIN_IB_RSSI_T;

// rssi_max_ib_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_max_reg_ib_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;              // [31:10]
    } b;
} REG_RF_DFE_RSSI_MAX_IB_RSSI_T;

// int_ib_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t int_clear_ib_rssi : 1; // [0]
        uint32_t int_mask_ib_rssi : 1;  // [1]
        uint32_t rssi_int_ib_rssi : 1;  // [2], read only
        uint32_t __31_3 : 29;           // [31:3]
    } b;
} REG_RF_DFE_INT_IB_RSSI_T;

// load_ib_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t load_ib_rssi : 1; // [0]
        uint32_t __31_1 : 31;      // [31:1]
    } b;
} REG_RF_DFE_LOAD_IB_RSSI_REG_T;

// rssi_val_ib_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_val_reg_ib_rssi : 1; // [0], read only
        uint32_t __31_1 : 31;              // [31:1]
    } b;
} REG_RF_DFE_RSSI_VAL_IB_RSSI_T;

// rssi_ib_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_reg_ib_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_RSSI_IB_RSSI_T;

// start_max_min_ob_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t start_max_min_ob_rssi : 1; // [0]
        uint32_t __31_1 : 31;               // [31:1]
    } b;
} REG_RF_DFE_START_MAX_MIN_OB_RSSI_REG_T;

// count_16lsb_ob_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t count_16lsb_ob_rssi : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_COUNT_16LSB_OB_RSSI_REG_T;

// count_16msb_ob_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t count_16msb_ob_rssi : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_COUNT_16MSB_OB_RSSI_REG_T;

// load_max_min_ob_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t load_max_min_ob_rssi : 1; // [0]
        uint32_t __31_1 : 31;              // [31:1]
    } b;
} REG_RF_DFE_LOAD_MAX_MIN_OB_RSSI_REG_T;

// rssi_max_min_val_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_max_min_val_reg_ob_rssi : 1; // [0], read only
        uint32_t __31_1 : 31;                      // [31:1]
    } b;
} REG_RF_DFE_RSSI_MAX_MIN_VAL_OB_RSSI_T;

// rssi_min_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_min_reg_ob_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;              // [31:10]
    } b;
} REG_RF_DFE_RSSI_MIN_OB_RSSI_T;

// rssi_max_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_max_reg_ob_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;              // [31:10]
    } b;
} REG_RF_DFE_RSSI_MAX_OB_RSSI_T;

// int_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t int_clear_ob_rssi : 1; // [0]
        uint32_t int_mask_ob_rssi : 1;  // [1]
        uint32_t rssi_int_ob_rssi : 1;  // [2], read only
        uint32_t __31_3 : 29;           // [31:3]
    } b;
} REG_RF_DFE_INT_OB_RSSI_T;

// load_ob_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t load_ob_rssi : 1; // [0]
        uint32_t __31_1 : 31;      // [31:1]
    } b;
} REG_RF_DFE_LOAD_OB_RSSI_REG_T;

// rssi_val_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_val_reg_ob_rssi : 1; // [0], read only
        uint32_t __31_1 : 31;              // [31:1]
    } b;
} REG_RF_DFE_RSSI_VAL_OB_RSSI_T;

// rssi_wd_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_reg_wd_ob_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_RF_DFE_RSSI_WD_OB_RSSI_T;

// rssi_up_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_reg_up_ob_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_RF_DFE_RSSI_UP_OB_RSSI_T;

// rssi_dn_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_reg_dn_ob_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_RF_DFE_RSSI_DN_OB_RSSI_T;

// rxdp_rc_stretch_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_rc_stretch : 8; // [7:0]
        uint32_t __31_8 : 24;         // [31:8]
    } b;
} REG_RF_DFE_RXDP_RC_STRETCH_REG_T;

// rxdp_rc_rate_ofs_rest_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_rc_rate_ofs_rest : 10; // [9:0]
        uint32_t __31_10 : 22;               // [31:10]
    } b;
} REG_RF_DFE_RXDP_RC_RATE_OFS_REST_REG_T;

// rxdp_bypass_control_reg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_bypass_cic1 : 1;     // [0]
        uint32_t rxdp_bypass_dcc : 1;      // [1]
        uint32_t __2_2 : 1;                // [2]
        uint32_t rxdp_bypass_rc : 1;       // [3]
        uint32_t rxdp_bypass_mixer : 1;    // [4]
        uint32_t rxdp_bypass_notch1_1 : 1; // [5]
        uint32_t __6_6 : 1;                // [6]
        uint32_t rxdp_bypass_gdeq : 1;     // [7]
        uint32_t __9_8 : 2;                // [9:8]
        uint32_t rxdp_bypass_aci_lpf : 1;  // [10]
        uint32_t rxdp_bypass_dnbh1 : 1;    // [11]
        uint32_t rxdp_bypass_notch2_1 : 1; // [12]
        uint32_t rxdp_bypass_notch2_2 : 1; // [13]
        uint32_t rxdp_bypass_gainbb : 1;   // [14]
        uint32_t __31_15 : 17;             // [31:15]
    } b;
} REG_RF_DFE_RXDP_BYPASS_CONTROL_REG1_T;

// rxdp_bypass_control_reg2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;             // [3:0]
        uint32_t rxdp_bypass_mrrm : 1;  // [4]
        uint32_t rxdp_bypass_imbc : 1;  // [5]
        uint32_t rxdp_bypass_dnhb2 : 1; // [6]
        uint32_t __31_7 : 25;           // [31:7]
    } b;
} REG_RF_DFE_RXDP_BYPASS_CONTROL_REG2_T;

// rxdp_bypass_mode_control_reg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_bypass_mode_cic1 : 1;     // [0]
        uint32_t rxdp_bypass_mode_dcc : 1;      // [1]
        uint32_t __2_2 : 1;                     // [2]
        uint32_t rxdp_bypass_mode_rc : 1;       // [3]
        uint32_t rxdp_bypass_mode_mixer : 1;    // [4]
        uint32_t rxdp_bypass_mode_notch1_1 : 1; // [5]
        uint32_t __6_6 : 1;                     // [6]
        uint32_t rxdp_bypass_mode_gdeq : 1;     // [7]
        uint32_t __9_8 : 2;                     // [9:8]
        uint32_t rxdp_bypass_mode_aci_lpf : 1;  // [10]
        uint32_t rxdp_bypass_mode_dnbh1 : 1;    // [11]
        uint32_t rxdp_bypass_mode_notch2_1 : 1; // [12]
        uint32_t rxdp_bypass_mode_notch2_2 : 1; // [13]
        uint32_t rxdp_bypass_mode_gainbb : 1;   // [14]
        uint32_t __31_15 : 17;                  // [31:15]
    } b;
} REG_RF_DFE_RXDP_BYPASS_MODE_CONTROL_REG1_T;

// rxdp_bypass_mode_control_reg2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;                  // [3:0]
        uint32_t rxdp_bypass_mode_mrrm : 1;  // [4]
        uint32_t rxdp_bypass_mode_imbc : 1;  // [5]
        uint32_t rxdp_bypass_mode_dnhb2 : 1; // [6]
        uint32_t __31_7 : 25;                // [31:7]
    } b;
} REG_RF_DFE_RXDP_BYPASS_MODE_CONTROL_REG2_T;

// rxdp_dcc_re_real_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_dcc_re_real : 16; // [15:0], read only
        uint32_t __31_16 : 16;          // [31:16]
    } b;
} REG_RF_DFE_RXDP_DCC_RE_REAL_REG_T;

// rxdp_dcc_im_real_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_dcc_im_real : 16; // [15:0], read only
        uint32_t __31_16 : 16;          // [31:16]
    } b;
} REG_RF_DFE_RXDP_DCC_IM_REAL_REG_T;

// rssi_real_ib_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_reg_real_ib_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;               // [31:10]
    } b;
} REG_RF_DFE_RSSI_REAL_IB_RSSI_T;

// rssi_wd_real_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_reg_wd_real_ob_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;                  // [31:10]
    } b;
} REG_RF_DFE_RSSI_WD_REAL_OB_RSSI_T;

// rssi_up_real_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_reg_up_real_ob_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;                  // [31:10]
    } b;
} REG_RF_DFE_RSSI_UP_REAL_OB_RSSI_T;

// rssi_dn_real_ob_rssi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_reg_dn_real_ob_rssi : 10; // [9:0], read only
        uint32_t __31_10 : 22;                  // [31:10]
    } b;
} REG_RF_DFE_RSSI_DN_REAL_OB_RSSI_T;

// rxdp_imbc_wa_out_real_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_imbc_wa_out_real : 16; // [15:0], read only
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_DFE_RXDP_IMBC_WA_OUT_REAL_REG_T;

// rxdp_imbc_wq_out_real_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_imbc_wq_out_real : 16; // [15:0], read only
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_DFE_RXDP_IMBC_WQ_OUT_REAL_REG_T;

// start_max_min_rssi3_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t start_max_min_rssi3 : 1; // [0]
        uint32_t __31_1 : 31;             // [31:1]
    } b;
} REG_RF_DFE_START_MAX_MIN_RSSI3_REG_T;

// count_16lsb_rssi3_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t count_16lsb_rssi3 : 16; // [15:0]
        uint32_t __31_16 : 16;           // [31:16]
    } b;
} REG_RF_DFE_COUNT_16LSB_RSSI3_REG_T;

// count_16msb_rssi3_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t count_16msb_rssi3 : 16; // [15:0]
        uint32_t __31_16 : 16;           // [31:16]
    } b;
} REG_RF_DFE_COUNT_16MSB_RSSI3_REG_T;

// load_max_min_rssi3_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t load_max_min_rssi3 : 1; // [0]
        uint32_t __31_1 : 31;            // [31:1]
    } b;
} REG_RF_DFE_LOAD_MAX_MIN_RSSI3_REG_T;

// rssi_min_rssi3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_min_reg_rssi3 : 10;        // [9:0], read only
        uint32_t rssi_max_min_val_reg_rssi3 : 1; // [10], read only
        uint32_t __31_11 : 21;                   // [31:11]
    } b;
} REG_RF_DFE_RSSI_MIN_RSSI3_T;

// rssi_max_rssi3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_max_reg_rssi3 : 10; // [9:0], read only
        uint32_t __31_10 : 22;            // [31:10]
    } b;
} REG_RF_DFE_RSSI_MAX_RSSI3_T;

// int_rssi3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t int_clear_rssi3 : 1; // [0]
        uint32_t int_mask_rssi3 : 1;  // [1]
        uint32_t rssi_int_rssi3 : 1;  // [2], read only
        uint32_t __31_3 : 29;         // [31:3]
    } b;
} REG_RF_DFE_INT_RSSI3_T;

// load_rssi3_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t load_rssi3 : 1; // [0]
        uint32_t __31_1 : 31;    // [31:1]
    } b;
} REG_RF_DFE_LOAD_RSSI3_REG_T;

// rssi_val_rssi3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_val_reg_rssi3 : 1; // [0], read only
        uint32_t __31_1 : 31;            // [31:1]
    } b;
} REG_RF_DFE_RSSI_VAL_RSSI3_T;

// rssi_rssi3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_reg_rssi3 : 10; // [9:0], read only
        uint32_t __31_10 : 22;        // [31:10]
    } b;
} REG_RF_DFE_RSSI_RSSI3_T;

// rssi_real_rssi3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rssi_reg_real_rssi3 : 10; // [9:0], read only
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_RF_DFE_RSSI_REAL_RSSI3_T;

// rxdp_notch_cordic_enable_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch1_cordic_enable : 1;  // [0]
        uint32_t rxdp_notch2_cordic0_enable : 1; // [1]
        uint32_t rxdp_notch2_cordic1_enable : 1; // [2]
        uint32_t rxdp_notch_cordic_gain_sel : 2; // [4:3]
        uint32_t __31_5 : 27;                    // [31:5]
    } b;
} REG_RF_DFE_RXDP_NOTCH_CORDIC_ENABLE_REG_T;

// rxdp_notch1_cordic_amp_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch1_cordic_amp : 14; // [13:0]
        uint32_t __31_14 : 18;                // [31:14]
    } b;
} REG_RF_DFE_RXDP_NOTCH1_CORDIC_AMP_REG_T;

// rxdp_notch1_cordic_zin_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch1_cordic_zin : 14; // [13:0]
        uint32_t __31_14 : 18;                // [31:14]
    } b;
} REG_RF_DFE_RXDP_NOTCH1_CORDIC_ZIN_REG_T;

// rxdp_notch2_cordic0_amp_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_cordic0_amp : 14; // [13:0]
        uint32_t __31_14 : 18;                 // [31:14]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_CORDIC0_AMP_REG_T;

// rxdp_notch2_cordic0_zin_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_cordic0_zin : 14; // [13:0]
        uint32_t __31_14 : 18;                 // [31:14]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_CORDIC0_ZIN_REG_T;

// rxdp_notch2_cordic1_amp_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_cordic1_amp : 14; // [13:0]
        uint32_t __31_14 : 18;                 // [31:14]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_CORDIC1_AMP_REG_T;

// rxdp_notch2_cordic1_zin_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_cordic1_zin : 14; // [13:0]
        uint32_t __31_14 : 18;                 // [31:14]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_CORDIC1_ZIN_REG_T;

// txdp_cfr_th_liner_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_cfr_th_liner : 12; // [11:0]
        uint32_t __31_12 : 20;           // [31:12]
    } b;
} REG_RF_DFE_TXDP_CFR_TH_LINER_REG_T;

// txdp_sine_rate_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_sine_rate : 8; // [7:0]
        uint32_t __31_8 : 24;        // [31:8]
    } b;
} REG_RF_DFE_TXDP_SINE_RATE_REG_T;

// txdp_rc_stretch_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_rc_stretch : 8; // [7:0]
        uint32_t __31_8 : 24;         // [31:8]
    } b;
} REG_RF_DFE_TXDP_RC_STRETCH_REG_T;

// txdp_rc_rate_ofs_rest_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_rc_rate_ofs_rest : 10; // [9:0]
        uint32_t __31_10 : 22;               // [31:10]
    } b;
} REG_RF_DFE_TXDP_RC_RATE_OFS_REST_REG_T;

// txdp_rc_rate_ofs_period_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_rc_rate_ofs_period : 10; // [9:0]
        uint32_t __31_10 : 22;                 // [31:10]
    } b;
} REG_RF_DFE_TXDP_RC_RATE_OFS_PERIOD_REG_T;

// txdp_rc_rate_ofs_hi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_rc_rate_ofs_hi : 8; // [7:0]
        uint32_t __31_8 : 24;             // [31:8]
    } b;
} REG_RF_DFE_TXDP_RC_RATE_OFS_HI_REG_T;

// txdp_rc_rate_ofs_lo_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_rc_rate_ofs_lo : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_TXDP_RC_RATE_OFS_LO_REG_T;

// clk_convert_rate_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_convert_rate_a : 8; // [7:0]
        uint32_t clk_convert_rate_b : 8; // [15:8]
        uint32_t __31_16 : 16;           // [31:16]
    } b;
} REG_RF_DFE_CLK_CONVERT_RATE_REG_T;

// rxdp_notch1_cordic_dout_i_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch1_cordic_dout_i : 12; // [11:0], read only
        uint32_t __31_12 : 20;                   // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH1_CORDIC_DOUT_I_REG_T;

// rxdp_notch1_cordic_dout_q_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch1_cordic_dout_q : 12; // [11:0], read only
        uint32_t __31_12 : 20;                   // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH1_CORDIC_DOUT_Q_REG_T;

// rxdp_notch2_cordic0_dout_i_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_cordic0_dout_i : 12; // [11:0], read only
        uint32_t __31_12 : 20;                    // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_CORDIC0_DOUT_I_REG_T;

// rxdp_notch2_cordic0_dout_q_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_cordic0_dout_q : 12; // [11:0], read only
        uint32_t __31_12 : 20;                    // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_CORDIC0_DOUT_Q_REG_T;

// rxdp_notch2_cordic1_dout_i_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_cordic1_dout_i : 12; // [11:0], read only
        uint32_t __31_12 : 20;                    // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_CORDIC1_DOUT_I_REG_T;

// rxdp_notch2_cordic1_dout_q_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch2_cordic1_dout_q : 12; // [11:0], read only
        uint32_t __31_12 : 20;                    // [31:12]
    } b;
} REG_RF_DFE_RXDP_NOTCH2_CORDIC1_DOUT_Q_REG_T;

// rxdp_notch_gen_val_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_notch1_cordic_dout_val : 1;  // [0], read only
        uint32_t rxdp_notch2_cordic0_dout_val : 1; // [1], read only
        uint32_t rxdp_notch2_cordic1_dout_val : 1; // [2], read only
        uint32_t __31_3 : 29;                      // [31:3]
    } b;
} REG_RF_DFE_RXDP_NOTCH_GEN_VAL_REG_T;

// resetn_notch_gen_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t resetn_notch_gen : 1; // [0]
        uint32_t __31_1 : 31;          // [31:1]
    } b;
} REG_RF_DFE_RESETN_NOTCH_GEN_REG_T;

// dfe_dump_smp_rate_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dfe_dump_smp_rate : 8; // [7:0]
        uint32_t __31_8 : 24;           // [31:8]
    } b;
} REG_RF_DFE_DFE_DUMP_SMP_RATE_REG_T;

// txdp_wedge_gain_ct_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_gain_ct : 11;            // [10:0]
        uint32_t __11_11 : 1;                        // [11]
        uint32_t txdp_wedge_gain_ct_load_bypass : 1; // [12]
        uint32_t txdp_wedge_gain_ct_load : 1;        // [13]
        uint32_t __31_14 : 18;                       // [31:14]
    } b;
} REG_RF_DFE_TXDP_WEDGE_GAIN_CT_REG_T;

// txdp_wedge_am_shrink_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_shrink : 8; // [7:0]
        uint32_t __31_8 : 24;              // [31:8]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_SHRINK_REG_T;

// txdp_wedge_pm_shift_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_shift : 2; // [1:0]
        uint32_t __31_2 : 30;             // [31:2]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_SHIFT_REG_T;

// txdp_wedge_am_p0_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p0 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P0_REG_T;

// txdp_wedge_am_p1_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p1 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P1_REG_T;

// txdp_wedge_am_p2_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p2 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P2_REG_T;

// txdp_wedge_am_p3_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p3 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P3_REG_T;

// txdp_wedge_am_p4_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p4 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P4_REG_T;

// txdp_wedge_am_p5_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p5 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P5_REG_T;

// txdp_wedge_am_p6_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p6 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P6_REG_T;

// txdp_wedge_am_p7_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p7 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P7_REG_T;

// txdp_wedge_am_p8_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p8 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P8_REG_T;

// txdp_wedge_am_p9_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p9 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P9_REG_T;

// txdp_wedge_am_p10_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p10 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P10_REG_T;

// txdp_wedge_am_p11_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p11 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P11_REG_T;

// txdp_wedge_am_p12_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p12 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P12_REG_T;

// txdp_wedge_am_p13_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p13 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P13_REG_T;

// txdp_wedge_am_p14_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p14 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P14_REG_T;

// txdp_wedge_am_p15_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p15 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P15_REG_T;

// txdp_wedge_am_p16_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_am_p16 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_AM_P16_REG_T;

// txdp_wedge_pm_p0_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p0 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P0_REG_T;

// txdp_wedge_pm_p1_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p1 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P1_REG_T;

// txdp_wedge_pm_p2_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p2 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P2_REG_T;

// txdp_wedge_pm_p3_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p3 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P3_REG_T;

// txdp_wedge_pm_p4_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p4 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P4_REG_T;

// txdp_wedge_pm_p5_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p5 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P5_REG_T;

// txdp_wedge_pm_p6_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p6 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P6_REG_T;

// txdp_wedge_pm_p7_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p7 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P7_REG_T;

// txdp_wedge_pm_p8_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p8 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P8_REG_T;

// txdp_wedge_pm_p9_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p9 : 10; // [9:0]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P9_REG_T;

// txdp_wedge_pm_p10_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p10 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P10_REG_T;

// txdp_wedge_pm_p11_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p11 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P11_REG_T;

// txdp_wedge_pm_p12_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p12 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P12_REG_T;

// txdp_wedge_pm_p13_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p13 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P13_REG_T;

// txdp_wedge_pm_p14_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p14 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P14_REG_T;

// txdp_wedge_pm_p15_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p15 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P15_REG_T;

// txdp_wedge_pm_p16_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_wedge_pm_p16 : 10; // [9:0]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TXDP_WEDGE_PM_P16_REG_T;

// aclr_coef4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef04 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF4_T;

// aclr_coef5
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef05 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF5_T;

// aclr_coef6
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef06 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF6_T;

// aclr_coef7
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef07 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF7_T;

// clk_convert_rate_load
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_convert_rate_load : 1; // [0]
        uint32_t __31_1 : 31;               // [31:1]
    } b;
} REG_RF_DFE_CLK_CONVERT_RATE_LOAD_T;

// clk_dac_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_dac_sel : 1;      // [0]
        uint32_t clk_dac_test_en : 1;  // [1]
        uint32_t clk_dac_test_sel : 2; // [3:2]
        uint32_t __31_4 : 28;          // [31:4]
    } b;
} REG_RF_DFE_CLK_DAC_CTRL_T;

// txdp_delay_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_delay : 8; // [7:0]
        uint32_t __31_8 : 24;    // [31:8]
    } b;
} REG_RF_DFE_TXDP_DELAY_REG_T;

// aclr_coef0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef00 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF0_T;

// aclr_coef1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef01 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF1_T;

// aclr_coef2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef02 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF2_T;

// aclr_coef3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef03 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF3_T;

// txdp_gdeq_coef0_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_gdeq_coef0_rg_lo : 16; // [15:0]
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_DFE_TXDP_GDEQ_COEF0_RG_1_T;

// txdp_gdeq_coef0_rg_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_gdeq_coef0_rg_hi : 4; // [3:0]
        uint32_t __31_4 : 28;               // [31:4]
    } b;
} REG_RF_DFE_TXDP_GDEQ_COEF0_RG_2_T;

// txdp_gdeq_coef1_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_gdeq_coef1_rg_lo : 16; // [15:0]
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_DFE_TXDP_GDEQ_COEF1_RG_1_T;

// txdp_gdeq_coef1_rg_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_gdeq_coef1_rg_hi : 4; // [3:0]
        uint32_t __31_4 : 28;               // [31:4]
    } b;
} REG_RF_DFE_TXDP_GDEQ_COEF1_RG_2_T;

// txdp_gdeq_coef2_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_gdeq_coef2_rg_lo : 16; // [15:0]
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_DFE_TXDP_GDEQ_COEF2_RG_1_T;

// txdp_gdeq_coef2_rg_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_gdeq_coef2_rg_hi : 4; // [3:0]
        uint32_t __31_4 : 28;               // [31:4]
    } b;
} REG_RF_DFE_TXDP_GDEQ_COEF2_RG_2_T;

// txdp_gdeq_coef3_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_gdeq_coef3_rg_lo : 16; // [15:0]
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_DFE_TXDP_GDEQ_COEF3_RG_1_T;

// txdp_gdeq_coef3_rg_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_gdeq_coef3_rg_hi : 4; // [3:0]
        uint32_t __31_4 : 28;               // [31:4]
    } b;
} REG_RF_DFE_TXDP_GDEQ_COEF3_RG_2_T;

// txdp_loft_offset_i_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_offset_i : 12; // [11:0]
        uint32_t __31_12 : 20;            // [31:12]
    } b;
} REG_RF_DFE_TXDP_LOFT_OFFSET_I_REG_T;

// txdp_loft_offset_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_offset : 12; // [11:0]
        uint32_t __31_12 : 20;          // [31:12]
    } b;
} REG_RF_DFE_TXDP_LOFT_OFFSET_REG_T;

// txdp_loft_phase_err_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_phase_err : 12; // [11:0]
        uint32_t __31_12 : 20;             // [31:12]
    } b;
} REG_RF_DFE_TXDP_LOFT_PHASE_ERR_REG_T;

// txdp_loft_amp_err_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_amp_err : 12; // [11:0]
        uint32_t __31_12 : 20;           // [31:12]
    } b;
} REG_RF_DFE_TXDP_LOFT_AMP_ERR_REG_T;

// txdp_loft_rssi_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_rssi_err : 16; // [15:0], read only
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_DFE_TXDP_LOFT_RSSI_REG_T;

// txdp_loft_tone_amp_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_tone_amp : 12; // [11:0]
        uint32_t __31_12 : 20;            // [31:12]
    } b;
} REG_RF_DFE_TXDP_LOFT_TONE_AMP_REG_T;

// txdp_loft_tone_fre_reg0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_tone_fre0 : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_DFE_TXDP_LOFT_TONE_FRE_REG0_T;

// txdp_loft_tone_fre_reg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_tone_fre1 : 7; // [6:0]
        uint32_t __31_7 : 25;             // [31:7]
    } b;
} REG_RF_DFE_TXDP_LOFT_TONE_FRE_REG1_T;

// txdp_loft_misc0_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_rssi_load : 1;       // [0]
        uint32_t txdp_loft_rssi_enable : 1;     // [1]
        uint32_t txdp_loft_rssi_period_idx : 1; // [2]
        uint32_t txdp_loft_rssi_ushift : 3;     // [5:3]
        uint32_t txdp_loft_bpf_bypass : 1;      // [6]
        uint32_t txdp_loft_bpf_enable : 1;      // [7]
        uint32_t txdp_loft_flg_loft_calib : 1;  // [8]
        uint32_t txdp_loft_amp_err_dr : 1;      // [9]
        uint32_t txdp_loft_phase_err_dr : 1;    // [10]
        uint32_t txdp_loft_offset_dr : 1;       // [11]
        uint32_t txdp_loft_cancel_bypass : 1;   // [12]
        uint32_t txdp_loft_cali_en : 1;         // [13]
        uint32_t txdp_loft_din_loft_sel : 1;    // [14]
        uint32_t txdp_loft_sincos_en : 1;       // [15]
        uint32_t __31_16 : 16;                  // [31:16]
    } b;
} REG_RF_DFE_TXDP_LOFT_MISC0_REG_T;

// txdp_loft_gain1_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_gain1_ct_sel : 1; // [0]
        uint32_t txdp_loft_gain1_ct_dyn : 6; // [6:1]
        uint32_t txdp_loft_gain1_ct : 6;     // [12:7]
        uint32_t txdp_loft_rssi_val : 1;     // [13], read only
        uint32_t __31_14 : 18;               // [31:14]
    } b;
} REG_RF_DFE_TXDP_LOFT_GAIN1_REG_T;

// data_format_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dac_off_bin_en : 1; // [0]
        uint32_t adc_off_bin_en : 1; // [1]
        uint32_t tx_off_bin_en : 1;  // [2]
        uint32_t rx_off_bin_en : 1;  // [3]
        uint32_t dac_iq_swap : 1;    // [4]
        uint32_t adc_iq_swap : 1;    // [5]
        uint32_t tx_iq_swap : 1;     // [6]
        uint32_t rx_iq_swap : 1;     // [7]
        uint32_t nb_tx_rx_loop : 1;  // [8]
        uint32_t __31_9 : 23;        // [31:9]
    } b;
} REG_RF_DFE_DATA_FORMAT_CTRL_T;

// txdp_loft_rssi_reg_real
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_loft_rssi_err_real : 16; // [15:0], read only
        uint32_t __31_16 : 16;                 // [31:16]
    } b;
} REG_RF_DFE_TXDP_LOFT_RSSI_REG_REAL_T;

// temper_tsx_ct
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_tsx_hold_en : 1;     // [0]
        uint32_t temper_tsx_lpf_bypass : 1;  // [1]
        uint32_t temper_tsx_bw_sel : 2;      // [3:2]
        uint32_t temper_tsx_ushift : 3;      // [6:4]
        uint32_t temper_tsx_lpf3_bypass : 1; // [7]
        uint32_t temper_tsx_pout_load : 1;   // [8]
        uint32_t temper_tsx_pout_val_rg : 1; // [9], read only
        uint32_t __31_10 : 22;               // [31:10]
    } b;
} REG_RF_DFE_TEMPER_TSX_CT_T;

// temper_tsx_dout_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_tsx_dout : 16; // [15:0], read only
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_RF_DFE_TEMPER_TSX_DOUT_REG_T;

// tsx_temp_clk_ct
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;                    // [3:0]
        uint32_t temper_tsx_clk_phase_sel : 1; // [4]
        uint32_t temper_tsx_clk_freq_sel : 2;  // [6:5]
        uint32_t temper_tsx_clk_en : 1;        // [7]
        uint32_t __31_8 : 24;                  // [31:8]
    } b;
} REG_RF_DFE_TSX_TEMP_CLK_CT_T;

// temper_tsx_lpf_a11_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_tsx_lpf_a11 : 14; // [13:0]
        uint32_t __31_14 : 18;            // [31:14]
    } b;
} REG_RF_DFE_TEMPER_TSX_LPF_A11_RG_T;

// temper_tsx_lpf_a12_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_tsx_lpf_a12 : 14; // [13:0]
        uint32_t __31_14 : 18;            // [31:14]
    } b;
} REG_RF_DFE_TEMPER_TSX_LPF_A12_RG_T;

// temper_tsx_lpf_g1_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_tsx_lpf_g1 : 14; // [13:0]
        uint32_t __31_14 : 18;           // [31:14]
    } b;
} REG_RF_DFE_TEMPER_TSX_LPF_G1_RG_T;

// temper_tsx_lpf_a21_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_tsx_lpf_a21 : 14; // [13:0]
        uint32_t __31_14 : 18;            // [31:14]
    } b;
} REG_RF_DFE_TEMPER_TSX_LPF_A21_RG_T;

// temper_tsx_lpf_a22_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_tsx_lpf_a22 : 14; // [13:0]
        uint32_t __31_14 : 18;            // [31:14]
    } b;
} REG_RF_DFE_TEMPER_TSX_LPF_A22_RG_T;

// temper_tsx_lpf_g2_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_tsx_lpf_g2 : 14; // [13:0]
        uint32_t __31_14 : 18;           // [31:14]
    } b;
} REG_RF_DFE_TEMPER_TSX_LPF_G2_RG_T;

// temper_tsx_dout_real_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_tsx_dout_real : 16; // [15:0], read only
        uint32_t __31_16 : 16;              // [31:16]
    } b;
} REG_RF_DFE_TEMPER_TSX_DOUT_REAL_REG_T;

// temper_ct
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_hold_en : 1;     // [0]
        uint32_t temper_lpf_bypass : 1;  // [1]
        uint32_t temper_bw_sel : 2;      // [3:2]
        uint32_t temper_ushift : 3;      // [6:4]
        uint32_t temper_lpf3_bypass : 1; // [7]
        uint32_t temper_pout_load : 1;   // [8]
        uint32_t temper_pout_val_rg : 1; // [9], read only
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_RF_DFE_TEMPER_CT_T;

// temper_dout_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_dout : 16; // [15:0], read only
        uint32_t __31_16 : 16;     // [31:16]
    } b;
} REG_RF_DFE_TEMPER_DOUT_REG_T;

// osc_temp_clk_ct
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;                // [3:0]
        uint32_t temper_clk_phase_sel : 1; // [4]
        uint32_t temper_clk_freq_sel : 2;  // [6:5]
        uint32_t temper_clk_en : 1;        // [7]
        uint32_t __31_8 : 24;              // [31:8]
    } b;
} REG_RF_DFE_OSC_TEMP_CLK_CT_T;

// temper_lpf_a11_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_lpf_a11 : 14; // [13:0]
        uint32_t __31_14 : 18;        // [31:14]
    } b;
} REG_RF_DFE_TEMPER_LPF_A11_RG_T;

// temper_lpf_a12_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_lpf_a12 : 14; // [13:0]
        uint32_t __31_14 : 18;        // [31:14]
    } b;
} REG_RF_DFE_TEMPER_LPF_A12_RG_T;

// temper_lpf_g1_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_lpf_g1 : 14; // [13:0]
        uint32_t __31_14 : 18;       // [31:14]
    } b;
} REG_RF_DFE_TEMPER_LPF_G1_RG_T;

// temper_lpf_a21_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_lpf_a21 : 14; // [13:0]
        uint32_t __31_14 : 18;        // [31:14]
    } b;
} REG_RF_DFE_TEMPER_LPF_A21_RG_T;

// temper_lpf_a22_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_lpf_a22 : 14; // [13:0]
        uint32_t __31_14 : 18;        // [31:14]
    } b;
} REG_RF_DFE_TEMPER_LPF_A22_RG_T;

// temper_lpf_g2_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_lpf_g2 : 14; // [13:0]
        uint32_t __31_14 : 18;       // [31:14]
    } b;
} REG_RF_DFE_TEMPER_LPF_G2_RG_T;

// temper_dout_real_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t temper_dout_real : 16; // [15:0], read only
        uint32_t __31_16 : 16;          // [31:16]
    } b;
} REG_RF_DFE_TEMPER_DOUT_REAL_REG_T;

// dfe_sw_clkgate_en_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dfe_sw_clkgate_en : 1; // [0]
        uint32_t __31_1 : 31;           // [31:1]
    } b;
} REG_RF_DFE_DFE_SW_CLKGATE_EN_RG_T;

// mon_ct
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dfe_monitor_sel : 4;  // [3:0]
        uint32_t dfe_monitor_swap : 1; // [4]
        uint32_t __31_5 : 27;          // [31:5]
    } b;
} REG_RF_DFE_MON_CT_T;

// dac_offset_re_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dac_offset_re : 12; // [11:0]
        uint32_t __31_12 : 20;       // [31:12]
    } b;
} REG_RF_DFE_DAC_OFFSET_RE_RG_T;

// dac_offset_im_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dac_offset_im : 12; // [11:0]
        uint32_t __31_12 : 20;       // [31:12]
    } b;
} REG_RF_DFE_DAC_OFFSET_IM_RG_T;

// dac_tx_amp_re_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dac_tx_amp_re : 12; // [11:0]
        uint32_t __31_12 : 20;       // [31:12]
    } b;
} REG_RF_DFE_DAC_TX_AMP_RE_RG_T;

// dac_tx_amp_im_rg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dac_tx_amp_im : 12; // [11:0]
        uint32_t __31_12 : 20;       // [31:12]
    } b;
} REG_RF_DFE_DAC_TX_AMP_IM_RG_T;

// data_dac_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_test_dac_sel_rg : 5; // [4:0]
        uint32_t txdp_test_dac_en_rg : 1;  // [5]
        uint32_t rxdp_test_dac_sel_rg : 5; // [10:6]
        uint32_t rxdp_test_dac_en_rg : 1;  // [11]
        uint32_t sine_enable_rg : 1;       // [12]
        uint32_t data_dac_sel : 2;         // [14:13]
        uint32_t __31_15 : 17;             // [31:15]
    } b;
} REG_RF_DFE_DATA_DAC_CTRL_T;

// sincos_amp
typedef union {
    uint32_t v;
    struct
    {
        uint32_t sincos_amp_rg : 12; // [11:0]
        uint32_t __31_12 : 20;       // [31:12]
    } b;
} REG_RF_DFE_SINCOS_AMP_T;

// sincos_fre_lo
typedef union {
    uint32_t v;
    struct
    {
        uint32_t sincos_fre_rg_lo : 16; // [15:0]
        uint32_t __31_16 : 16;          // [31:16]
    } b;
} REG_RF_DFE_SINCOS_FRE_LO_T;

// sincos_fre_hi
typedef union {
    uint32_t v;
    struct
    {
        uint32_t sincos_fre_rg_hi : 7;      // [6:0]
        uint32_t txdp_bypass_mode_loft : 1; // [7]
        uint32_t txdp_bypass_loft : 1;      // [8]
        uint32_t __31_9 : 23;               // [31:9]
    } b;
} REG_RF_DFE_SINCOS_FRE_HI_T;

// txdp_bypass_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_bypass_ampequ : 1;       // [0]
        uint32_t txdp_bypass_aclr_lpf : 1;     // [1]
        uint32_t txdp_bypass_uphb1 : 1;        // [2]
        uint32_t txdp_bypass_cfr : 1;          // [3]
        uint32_t __4_4 : 1;                    // [4]
        uint32_t txdp_bypass_gain : 1;         // [5]
        uint32_t txdp_bypass_rc : 1;           // [6]
        uint32_t txdp_bypass_polariq : 1;      // [7]
        uint32_t __8_8 : 1;                    // [8]
        uint32_t txdp_bypass_polariq_ampm : 1; // [9]
        uint32_t __10_10 : 1;                  // [10]
        uint32_t txdp_bypass_gdeq : 1;         // [11]
        uint32_t txdp_bypass_uphb4 : 1;        // [12]
        uint32_t txdp_bypass_uphb5 : 1;        // [13]
        uint32_t __31_14 : 18;                 // [31:14]
    } b;
} REG_RF_DFE_TXDP_BYPASS_REG_T;

// txdp_bypass_mode_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_bypass_mode_ampequ : 1;       // [0]
        uint32_t txdp_bypass_mode_aclr_lpf : 1;     // [1]
        uint32_t txdp_bypass_mode_uphb1 : 1;        // [2]
        uint32_t txdp_bypass_mode_cfr : 1;          // [3]
        uint32_t __4_4 : 1;                         // [4]
        uint32_t txdp_bypass_mode_gain : 1;         // [5]
        uint32_t txdp_bypass_mode_rc : 1;           // [6]
        uint32_t txdp_bypass_mode_polariq : 1;      // [7]
        uint32_t __8_8 : 1;                         // [8]
        uint32_t txdp_bypass_mode_polariq_ampm : 1; // [9]
        uint32_t __10_10 : 1;                       // [10]
        uint32_t txdp_bypass_mode_gdeq : 1;         // [11]
        uint32_t txdp_bypass_mode_uphb4 : 1;        // [12]
        uint32_t txdp_bypass_mode_uphb5 : 1;        // [13]
        uint32_t __31_14 : 18;                      // [31:14]
    } b;
} REG_RF_DFE_TXDP_BYPASS_MODE_REG_T;

// reserved_all_zeros_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rsv_all_zero : 16; // [15:0]
        uint32_t __31_16 : 16;      // [31:16]
    } b;
} REG_RF_DFE_RESERVED_ALL_ZEROS_REG_T;

// reserved_all_ones_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rsv_all_ones : 16; // [15:0]
        uint32_t __31_16 : 16;      // [31:16]
    } b;
} REG_RF_DFE_RESERVED_ALL_ONES_REG_T;

// pwr_rf_acc_len_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwr_rf_acc_len_rg : 16; // [15:0]
        uint32_t __31_16 : 16;           // [31:16]
    } b;
} REG_RF_DFE_PWR_RF_ACC_LEN_REG_T;

// pwr_rf_acc_misc_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwr_rf_polar_rg : 1;    // [0]
        uint32_t pwr_rf_start_rg : 1;    // [1]
        uint32_t pwr_rf_ushift_rg : 3;   // [4:2]
        uint32_t pwr_adc_off_bin_en : 1; // [5]
        uint32_t __31_6 : 26;            // [31:6]
    } b;
} REG_RF_DFE_PWR_RF_ACC_MISC_REG_T;

// pwr_rf_acc_report_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwr_rf_calc_done : 1; // [0], read only
        uint32_t pwr_rf_o : 11;        // [11:1], read only
        uint32_t __31_12 : 20;         // [31:12]
    } b;
} REG_RF_DFE_PWR_RF_ACC_REPORT_REG_T;

// txdp_clk_gate_enable_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_sine_clkgate_en : 1;   // [0]
        uint32_t __1_1 : 1;                  // [1]
        uint32_t txdp_loft_clkgate_en : 1;   // [2]
        uint32_t __3_3 : 1;                  // [3]
        uint32_t txdp_uphb5_clkgate_en : 1;  // [4]
        uint32_t txdp_uphb4_clkgate_en : 1;  // [5]
        uint32_t txdp_gdeq_clkgate_en : 1;   // [6]
        uint32_t txdp_dpd_clkgate_en : 1;    // [7]
        uint32_t txdp_rc_clkgate_en : 1;     // [8]
        uint32_t txdp_gain_clkgate_en : 1;   // [9]
        uint32_t __11_10 : 2;                // [11:10]
        uint32_t txdp_uphb1_clkgate_en : 1;  // [12]
        uint32_t txdp_aclr_clkgate_en : 1;   // [13]
        uint32_t txdp_ampequ_clkgate_en : 1; // [14]
        uint32_t __31_15 : 17;               // [31:15]
    } b;
} REG_RF_DFE_TXDP_CLK_GATE_ENABLE_REG_T;

// rxdp_clk_gate_enable_reg2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_rc_clkgate_en : 1; // [0]
        uint32_t __31_1 : 31;            // [31:1]
    } b;
} REG_RF_DFE_RXDP_CLK_GATE_ENABLE_REG2_T;

// rxdp_clk_gate_enable_reg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxdp_rssi3_clkgate_en : 1;     // [0]
        uint32_t rxdp_notch_gen_clkgate_en : 1; // [1]
        uint32_t __2_2 : 1;                     // [2]
        uint32_t rxdp_ib_clkgate_en : 1;        // [3]
        uint32_t rxdp_dnhb2_clkgate_en : 1;     // [4]
        uint32_t rxdp_gainbb_clkgate_en : 1;    // [5]
        uint32_t rxdp_notch2_clkgate_en : 1;    // [6]
        uint32_t rxdp_aci_clkgate_en : 1;       // [7]
        uint32_t rxdp_dnhb1_clkgate_en : 1;     // [8]
        uint32_t rxdp_mrrm_clkgate_en : 1;      // [9]
        uint32_t rxdp_ob_clkgate_en : 1;        // [10]
        uint32_t __11_11 : 1;                   // [11]
        uint32_t rxdp_gdeq_clkgate_en : 1;      // [12]
        uint32_t rxdp_notch1_clkgate_en : 1;    // [13]
        uint32_t rxdp_mixer_clkgate_en : 1;     // [14]
        uint32_t rxdp_imbc_clkgate_en : 1;      // [15]
        uint32_t __31_16 : 16;                  // [31:16]
    } b;
} REG_RF_DFE_RXDP_CLK_GATE_ENABLE_REG1_T;

// test_dac_bits_sel_register
typedef union {
    uint32_t v;
    struct
    {
        uint32_t test_dac_bits_sel : 3; // [2:0]
        uint32_t __31_3 : 29;           // [31:3]
    } b;
} REG_RF_DFE_TEST_DAC_BITS_SEL_REGISTER_T;

// txdp_ampequ_coef0_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_ampequ_coef0_rg : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_RF_DFE_TXDP_AMPEQU_COEF0_RG_1_T;

// txdp_ampequ_coef1_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_ampequ_coef1_rg : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_RF_DFE_TXDP_AMPEQU_COEF1_RG_1_T;

// txdp_ampequ_coef2_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_ampequ_coef2_rg : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_RF_DFE_TXDP_AMPEQU_COEF2_RG_1_T;

// txdp_ampequ_coef3_rg_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_ampequ_coef3_rg : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_RF_DFE_TXDP_AMPEQU_COEF3_RG_1_T;

// txdp_ampequ_g
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_ampequ_g_rg : 16; // [15:0]
        uint32_t __31_16 : 16;          // [31:16]
    } b;
} REG_RF_DFE_TXDP_AMPEQU_G_T;

// txdp_ampequ_g_ext_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txdp_ampequ_g_ext : 12; // [11:0]
        uint32_t __31_12 : 20;           // [31:12]
    } b;
} REG_RF_DFE_TXDP_AMPEQU_G_EXT_REG_T;

// fifo_sample_rate_reg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fifo_b_smp_rate_rg : 4; // [3:0]
        uint32_t fifo_a_smp_rate_rg : 7; // [10:4]
        uint32_t __31_11 : 21;           // [31:11]
    } b;
} REG_RF_DFE_FIFO_SAMPLE_RATE_REG1_T;

// fifo_status_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fifo_a_empty_status : 1;       // [0], read only
        uint32_t fifo_a_full_status : 1;        // [1], read only
        uint32_t fifo_b_empty_status : 1;       // [2], read only
        uint32_t fifo_b_full_status : 1;        // [3], read only
        uint32_t __7_4 : 4;                     // [7:4]
        uint32_t fifo_adc_empty_status : 1;     // [8], read only
        uint32_t fifo_adc_full_status : 1;      // [9], read only
        uint32_t fifo_rxdp_rc_empty_status : 1; // [10], read only
        uint32_t fifo_rxdp_rc_full_status : 1;  // [11], read only
        uint32_t fifo_txdp_rc_empty_status : 1; // [12], read only
        uint32_t fifo_txdp_rc_full_status : 1;  // [13], read only
        uint32_t fifo_dump_empty_status : 1;    // [14], read only
        uint32_t fifo_dump_full_status : 1;     // [15], read only
        uint32_t __31_16 : 16;                  // [31:16]
    } b;
} REG_RF_DFE_FIFO_STATUS_REG_T;

// dfe_dump_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dfe_dump_sel : 2;     // [1:0]
        uint32_t dfe_dump_resetn : 1;  // [2]
        uint32_t dfe_dump_en : 1;      // [3]
        uint32_t dfe_dump_vld_sel : 2; // [5:4]
        uint32_t __7_6 : 2;            // [7:6]
        uint32_t sel_clk_dump_w : 4;   // [11:8]
        uint32_t __31_12 : 20;         // [31:12]
    } b;
} REG_RF_DFE_DFE_DUMP_REG_T;

// aclr_coef8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef08 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF8_T;

// aclr_coef9
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef09 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF9_T;

// aclr_coef10
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef10 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF10_T;

// aclr_coef11
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef11 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF11_T;

// aclr_coef12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef12 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF12_T;

// aclr_coef13
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef13 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF13_T;

// aclr_coef14
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef14 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF14_T;

// aclr_coef15
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef15 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF15_T;

// aclr_coef16
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef16 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF16_T;

// aclr_coef17
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef17 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF17_T;

// aclr_coef18
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef18 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF18_T;

// aclr_coef19
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef19 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF19_T;

// aclr_coef20
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef20 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF20_T;

// aclr_coef21
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef21 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF21_T;

// aclr_coef22
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef22 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF22_T;

// aclr_coef23
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aclr_coef23 : 10; // [9:0]
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_RF_DFE_ACLR_COEF23_T;

// pwd_dcc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_dcc_rx_calib_sel_rg : 1;   // [0]
        uint32_t pwd_dcc_dc_calib_en_rg : 1;    // [1]
        uint32_t pwd_dcc_dc_delta_ld_st_rg : 1; // [2]
        uint32_t pwd_dcc_bypass_rg : 1;         // [3]
        uint32_t pwd_dcc_hold_en_rg : 1;        // [4]
        uint32_t pwd_dcc_imgrej_rg : 1;         // [5]
        uint32_t pwd_dcc_load : 1;              // [6]
        uint32_t __31_7 : 25;                   // [31:7]
    } b;
} REG_RF_DFE_PWD_DCC_T;

// pwd_dc_calib_re
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_dc_calib_re_rg : 10; // [9:0]
        uint32_t __31_10 : 22;            // [31:10]
    } b;
} REG_RF_DFE_PWD_DC_CALIB_RE_T;

// pwd_dc_calib_im
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_dc_calib_im_rg : 10; // [9:0]
        uint32_t __31_10 : 22;            // [31:10]
    } b;
} REG_RF_DFE_PWD_DC_CALIB_IM_T;

// pwd_dc_delta_re
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_dc_delta_re_rg : 10; // [9:0]
        uint32_t __31_10 : 22;            // [31:10]
    } b;
} REG_RF_DFE_PWD_DC_DELTA_RE_T;

// pwd_dc_delta_im
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_dc_delta_im_rg : 10; // [9:0]
        uint32_t __31_10 : 22;            // [31:10]
    } b;
} REG_RF_DFE_PWD_DC_DELTA_IM_T;

// pwd_dc_cr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_conv_mode_ct_rg : 2;    // [1:0]
        uint32_t pwd_conv_tmr_ct_rg : 4;     // [5:2]
        uint32_t pwd_conv_fast_bw_ct_rg : 3; // [8:6]
        uint32_t pwd_conv_slow_bw_ct_rg : 3; // [11:9]
        uint32_t __31_12 : 20;               // [31:12]
    } b;
} REG_RF_DFE_PWD_DC_CR_T;

// pwd_dcc_valid_o_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_dcc_val_reg : 1; // [0], read only
        uint32_t __31_1 : 31;         // [31:1]
    } b;
} REG_RF_DFE_PWD_DCC_VALID_O_REG_T;

// pwd_dcc_re_o_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_dcc_re_o : 10; // [9:0], read only
        uint32_t __31_10 : 22;      // [31:10]
    } b;
} REG_RF_DFE_PWD_DCC_RE_O_REG_T;

// pwd_dcc_im_o_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_dcc_im_o : 10; // [9:0], read only
        uint32_t __31_10 : 22;      // [31:10]
    } b;
} REG_RF_DFE_PWD_DCC_IM_O_REG_T;

// pwd_dcc_re_real_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_dcc_re_real : 10; // [9:0], read only
        uint32_t __31_10 : 22;         // [31:10]
    } b;
} REG_RF_DFE_PWD_DCC_RE_REAL_REG_T;

// pwd_dcc_im_real_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwd_dcc_im_real : 10; // [9:0], read only
        uint32_t __31_10 : 22;         // [31:10]
    } b;
} REG_RF_DFE_PWD_DCC_IM_REAL_REG_T;

// general_mode
#define RF_DFE_ZF_IF_MODE (1 << 0)
#define RF_DFE_ADC_CLK_MODE(n) (((n)&0x3) << 1)
#define RF_DFE_RX_MODE(n) (((n)&0xf) << 4)
#define RF_DFE_CLK_ADC_INV_MODE (1 << 12)
#define RF_DFE_CLK_DAC_INV_MODE (1 << 13)
#define RF_DFE_RESET_MODE (1 << 14)

// dfe_clock_gate_enable_reg
#define RF_DFE_RXDP_ADC_CLK_EN (1 << 0)
#define RF_DFE_TXDP_CLK_DAC_EN (1 << 1)
#define RF_DFE_RXDP_DFE_CLK_EN (1 << 2)
#define RF_DFE_TXDP_NB_DFE_CLK_EN (1 << 4)
#define RF_DFE_CLK_122P88M_EN (1 << 6)
#define RF_DFE_CLK_RATE_CONVERT_RG (1 << 8)
#define RF_DFE_SW_RESETN (1 << 9)
#define RF_DFE_TXDP_LOFT_MODE (1 << 13)
#define RF_DFE_REG_CLKGATE_EN (1 << 14)

// rxdp_dcc
#define RF_DFE_DCC_RX_CALIB_SEL_RG (1 << 0)
#define RF_DFE_DCC_DC_CALIB_EN_RG (1 << 1)
#define RF_DFE_DCC_DC_DELTA_LD_ST_RG (1 << 2)
#define RF_DFE_DCC_BYPASS_RG (1 << 3)
#define RF_DFE_DCC_HOLD_EN_RG (1 << 4)
#define RF_DFE_DCC_IMGREJ_RG (1 << 5)
#define RF_DFE_RXDP_DCC_LOAD (1 << 6)

// rxdp_dc_calib_re
#define RF_DFE_RXDP_DC_CALIB_RE_RG(n) (((n)&0xffff) << 0)

// rxdp_dc_calib_im
#define RF_DFE_RXDP_DC_CALIB_IM_RG(n) (((n)&0xffff) << 0)

// rxdp_dc_delta_re
#define RF_DFE_RXDP_DC_DELTA_RE_RG(n) (((n)&0xffff) << 0)

// rxdp_dc_delta_im
#define RF_DFE_RXDP_DC_DELTA_IM_RG(n) (((n)&0xffff) << 0)

// rxdp_dc_cr
#define RF_DFE_CONV_MODE_CT_RG(n) (((n)&0x3) << 0)
#define RF_DFE_CONV_TMR_CT_RG(n) (((n)&0xf) << 2)
#define RF_DFE_CONV_FAST_BW_CT_RG(n) (((n)&0x7) << 6)
#define RF_DFE_CONV_SLOW_BW_CT_RG(n) (((n)&0x7) << 9)

// rxdp_gain_ct_reg
#define RF_DFE_RXDP_GAIN_CT(n) (((n)&0x7ff) << 0)
#define RF_DFE_RXDP_GAIN_CT_LOAD_BYPASS (1 << 12)
#define RF_DFE_RXDP_GAIN_CT_LOAD (1 << 13)

// rxdp_gdeq_coef0_rg_1
#define RF_DFE_RXDP_GDEQ_COEF0_RG_LO(n) (((n)&0xffff) << 0)

// rxdp_gdeq_coef0_rg_2
#define RF_DFE_RXDP_GDEQ_COEF0_RG_HI(n) (((n)&0xf) << 0)

// rxdp_gdeq_coef1_rg_1
#define RF_DFE_RXDP_GDEQ_COEF1_RG_LO(n) (((n)&0xffff) << 0)

// rxdp_gdeq_coef1_rg_2
#define RF_DFE_RXDP_GDEQ_COEF1_RG_HI(n) (((n)&0xf) << 0)

// rxdp_gdeq_coef2_rg_1
#define RF_DFE_RXDP_GDEQ_COEF2_RG_LO(n) (((n)&0xffff) << 0)

// rxdp_gdeq_coef2_rg_2
#define RF_DFE_RXDP_GDEQ_COEF2_RG_HI(n) (((n)&0xf) << 0)

// rxdp_gdeq_coef3_rg_1
#define RF_DFE_RXDP_GDEQ_COEF3_RG_LO(n) (((n)&0xffff) << 0)

// rxdp_gdeq_coef3_rg_2
#define RF_DFE_RXDP_GDEQ_COEF3_RG_HI(n) (((n)&0xf) << 0)
#define RF_DFE_RXDP_GDEQ_BP_LP_SEL (1 << 4)

// rxdp_adc_wr_buf_fifo
#define RF_DFE_RXDP_ADC_WR_EN_RG (1 << 0)
#define RF_DFE_RXDP_ADC_SMP_RATE_RG(n) (((n)&0x3f) << 1)

// rxdp_dcc_valid_o_reg
#define RF_DFE_RXDP_DCC_VAL_REG (1 << 0)

// rxdp_dcc_re_o_reg
#define RF_DFE_RXDP_DCC_RE_O(n) (((n)&0xffff) << 0)

// rxdp_dcc_im_o_reg
#define RF_DFE_RXDP_DCC_IM_O(n) (((n)&0xffff) << 0)

// rxdp_notch_ct
#define RF_DFE_RXDP_NOTCH_DATAEN1 (1 << 0)
#define RF_DFE_RXDP_NOTCH_DATAEN0 (1 << 1)

// rxdp_notch_a0_i_reg
#define RF_DFE_RXDP_NOTCH_A0_I(n) (((n)&0xfff) << 0)

// rxdp_notch_a0_q_reg
#define RF_DFE_RXDP_NOTCH_A0_Q(n) (((n)&0xfff) << 0)

// rxdp_notch_k_reg
#define RF_DFE_RXDP_NOTCH_K0(n) (((n)&0x3f) << 0)

// rxdp_mirror_remove
#define RF_DFE_RXDP_MRRM_BW_SEL(n) (((n)&0x3) << 0)

// rxdp_notch2_ct
#define RF_DFE_RXDP_NOTCH2_DATAEN1 (1 << 0)
#define RF_DFE_RXDP_NOTCH2_DATAEN0 (1 << 1)

// rxdp_notch2_a0_i_reg
#define RF_DFE_RXDP_NOTCH2_A0_I(n) (((n)&0xfff) << 0)

// rxdp_notch2_a0_q_reg
#define RF_DFE_RXDP_NOTCH2_A0_Q(n) (((n)&0xfff) << 0)

// rxdp_notch2_a1_i_reg
#define RF_DFE_RXDP_NOTCH2_A1_I(n) (((n)&0xfff) << 0)

// rxdp_notch2_a1_q_reg
#define RF_DFE_RXDP_NOTCH2_A1_Q(n) (((n)&0xfff) << 0)

// rxdp_notch2_k_reg
#define RF_DFE_RXDP_NOTCH2_K1(n) (((n)&0x3f) << 0)
#define RF_DFE_RXDP_NOTCH2_K0(n) (((n)&0x3f) << 6)

// rxdp_aci_filter_coef0_reg
#define RF_DFE_RXDP_ACI_FIR_COEF0(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef1_reg
#define RF_DFE_RXDP_ACI_FIR_COEF1(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef2_reg
#define RF_DFE_RXDP_ACI_FIR_COEF2(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef3_reg
#define RF_DFE_RXDP_ACI_FIR_COEF3(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef4_reg
#define RF_DFE_RXDP_ACI_FIR_COEF4(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef5_reg
#define RF_DFE_RXDP_ACI_FIR_COEF5(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef6_reg
#define RF_DFE_RXDP_ACI_FIR_COEF6(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef7_reg
#define RF_DFE_RXDP_ACI_FIR_COEF7(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef8_reg
#define RF_DFE_RXDP_ACI_FIR_COEF8(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef9_reg
#define RF_DFE_RXDP_ACI_FIR_COEF9(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef10_reg
#define RF_DFE_RXDP_ACI_FIR_COEF10(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef11_reg
#define RF_DFE_RXDP_ACI_FIR_COEF11(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef12_reg
#define RF_DFE_RXDP_ACI_FIR_COEF12(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef13_reg
#define RF_DFE_RXDP_ACI_FIR_COEF13(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef14_reg
#define RF_DFE_RXDP_ACI_FIR_COEF14(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef15_reg
#define RF_DFE_RXDP_ACI_FIR_COEF15(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef16_reg
#define RF_DFE_RXDP_ACI_FIR_COEF16(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef17_reg
#define RF_DFE_RXDP_ACI_FIR_COEF17(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef18_reg
#define RF_DFE_RXDP_ACI_FIR_COEF18(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef19_reg
#define RF_DFE_RXDP_ACI_FIR_COEF19(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef20_reg
#define RF_DFE_RXDP_ACI_FIR_COEF20(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef21_reg
#define RF_DFE_RXDP_ACI_FIR_COEF21(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef22_reg
#define RF_DFE_RXDP_ACI_FIR_COEF22(n) (((n)&0xffff) << 0)

// rxdp_aci_filter_coef23_reg
#define RF_DFE_RXDP_ACI_FIR_COEF23(n) (((n)&0xffff) << 0)

// rxdp_mixer_freq_in_reg0
#define RF_DFE_RXDP_MIXER_FREQ_P0(n) (((n)&0xffff) << 0)

// rxdp_mixer_freq_in_reg1
#define RF_DFE_RXDP_MIXER_FREQ_P1(n) (((n)&0xff) << 0)

// rxdp_rssi_reg
#define RF_DFE_RXDP_RSSI_IB_USHIFT(n) (((n)&0x7) << 0)
#define RF_DFE_RXDP_RSSI_OB_USHIFT(n) (((n)&0x7) << 3)
#define RF_DFE_RXDP_RSSI_IB_ENABLE (1 << 6)
#define RF_DFE_RXDP_RSSI_OB_ENABLE (1 << 7)
#define RF_DFE_RXDP_RSSI3_USHIFT(n) (((n)&0x7) << 8)
#define RF_DFE_RXDP_RSSI3_ENABLE (1 << 11)

// rxdp_imbc_wa_reg
#define RF_DFE_RXDP_IMBC_WA(n) (((n)&0xffff) << 0)

// rxdp_imbc_wq_reg
#define RF_DFE_RXDP_IMBC_WQ(n) (((n)&0xffff) << 0)

// rxdp_imbc_misc_reg
#define RF_DFE_RXDP_IMBC_LOAD (1 << 0)
#define RF_DFE_RXDP_IMBC_CALC_RELS (1 << 1)
#define RF_DFE_RXDP_IMBC_HOLD_DR (1 << 2)
#define RF_DFE_RXDP_IMBC_BW_SLOW_CT(n) (((n)&0xf) << 3)
#define RF_DFE_RXDP_IMBC_BW_FAST_CT_RG(n) (((n)&0xf) << 7)

// rxdp_imbc_wa_out_reg
#define RF_DFE_RXDP_IMBC_WA_OUT(n) (((n)&0xffff) << 0)

// rxdp_imbc_wq_out_reg
#define RF_DFE_RXDP_IMBC_WQ_OUT(n) (((n)&0xffff) << 0)

// rxdp_imbc_out_reg
#define RF_DFE_RXDP_IMBC_VAL_OUT (1 << 0)

// rxdp_rc_rate_ofs_period_reg
#define RF_DFE_RXDP_RC_RATE_OFS_PERIOD(n) (((n)&0x3ff) << 0)

// rxdp_rc_rate_ofs_hi_reg
#define RF_DFE_RXDP_RC_RATE_OFS_HI(n) (((n)&0xff) << 0)

// rxdp_rc_rate_ofs_lo_reg
#define RF_DFE_RXDP_RC_RATE_OFS_LO(n) (((n)&0xffff) << 0)

// start_max_min_ib_rssi_reg
#define RF_DFE_START_MAX_MIN_IB_RSSI (1 << 0)

// count_16lsb_ib_rssi_reg
#define RF_DFE_COUNT_16LSB_IB_RSSI(n) (((n)&0xffff) << 0)

// count_16msb_ib_rssi_reg
#define RF_DFE_COUNT_16MSB_IB_RSSI(n) (((n)&0xffff) << 0)

// load_max_min_ib_rssi_reg
#define RF_DFE_LOAD_MAX_MIN_IB_RSSI (1 << 0)

// rssi_min_ib_rssi
#define RF_DFE_RSSI_MIN_REG_IB_RSSI(n) (((n)&0x3ff) << 0)
#define RF_DFE_RSSI_MAX_MIN_VAL_REG_IB_RSSI (1 << 10)

// rssi_max_ib_rssi
#define RF_DFE_RSSI_MAX_REG_IB_RSSI(n) (((n)&0x3ff) << 0)

// int_ib_rssi
#define RF_DFE_INT_CLEAR_IB_RSSI (1 << 0)
#define RF_DFE_INT_MASK_IB_RSSI (1 << 1)
#define RF_DFE_RSSI_INT_IB_RSSI (1 << 2)

// load_ib_rssi_reg
#define RF_DFE_LOAD_IB_RSSI (1 << 0)

// rssi_val_ib_rssi
#define RF_DFE_RSSI_VAL_REG_IB_RSSI (1 << 0)

// rssi_ib_rssi
#define RF_DFE_RSSI_REG_IB_RSSI(n) (((n)&0x3ff) << 0)

// start_max_min_ob_rssi_reg
#define RF_DFE_START_MAX_MIN_OB_RSSI (1 << 0)

// count_16lsb_ob_rssi_reg
#define RF_DFE_COUNT_16LSB_OB_RSSI(n) (((n)&0xffff) << 0)

// count_16msb_ob_rssi_reg
#define RF_DFE_COUNT_16MSB_OB_RSSI(n) (((n)&0xffff) << 0)

// load_max_min_ob_rssi_reg
#define RF_DFE_LOAD_MAX_MIN_OB_RSSI (1 << 0)

// rssi_max_min_val_ob_rssi
#define RF_DFE_RSSI_MAX_MIN_VAL_REG_OB_RSSI (1 << 0)

// rssi_min_ob_rssi
#define RF_DFE_RSSI_MIN_REG_OB_RSSI(n) (((n)&0x3ff) << 0)

// rssi_max_ob_rssi
#define RF_DFE_RSSI_MAX_REG_OB_RSSI(n) (((n)&0x3ff) << 0)

// int_ob_rssi
#define RF_DFE_INT_CLEAR_OB_RSSI (1 << 0)
#define RF_DFE_INT_MASK_OB_RSSI (1 << 1)
#define RF_DFE_RSSI_INT_OB_RSSI (1 << 2)

// load_ob_rssi_reg
#define RF_DFE_LOAD_OB_RSSI (1 << 0)

// rssi_val_ob_rssi
#define RF_DFE_RSSI_VAL_REG_OB_RSSI (1 << 0)

// rssi_wd_ob_rssi
#define RF_DFE_RSSI_REG_WD_OB_RSSI(n) (((n)&0x3ff) << 0)

// rssi_up_ob_rssi
#define RF_DFE_RSSI_REG_UP_OB_RSSI(n) (((n)&0x3ff) << 0)

// rssi_dn_ob_rssi
#define RF_DFE_RSSI_REG_DN_OB_RSSI(n) (((n)&0x3ff) << 0)

// rxdp_rc_stretch_reg
#define RF_DFE_RXDP_RC_STRETCH(n) (((n)&0xff) << 0)

// rxdp_rc_rate_ofs_rest_reg
#define RF_DFE_RXDP_RC_RATE_OFS_REST(n) (((n)&0x3ff) << 0)

// rxdp_bypass_control_reg1
#define RF_DFE_RXDP_BYPASS_CIC1 (1 << 0)
#define RF_DFE_RXDP_BYPASS_DCC (1 << 1)
#define RF_DFE_RXDP_BYPASS_RC (1 << 3)
#define RF_DFE_RXDP_BYPASS_MIXER (1 << 4)
#define RF_DFE_RXDP_BYPASS_NOTCH1_1 (1 << 5)
#define RF_DFE_RXDP_BYPASS_GDEQ (1 << 7)
#define RF_DFE_RXDP_BYPASS_ACI_LPF (1 << 10)
#define RF_DFE_RXDP_BYPASS_DNBH1 (1 << 11)
#define RF_DFE_RXDP_BYPASS_NOTCH2_1 (1 << 12)
#define RF_DFE_RXDP_BYPASS_NOTCH2_2 (1 << 13)
#define RF_DFE_RXDP_BYPASS_GAINBB (1 << 14)

// rxdp_bypass_control_reg2
#define RF_DFE_RXDP_BYPASS_MRRM (1 << 4)
#define RF_DFE_RXDP_BYPASS_IMBC (1 << 5)
#define RF_DFE_RXDP_BYPASS_DNHB2 (1 << 6)

// rxdp_bypass_mode_control_reg1
#define RF_DFE_RXDP_BYPASS_MODE_CIC1 (1 << 0)
#define RF_DFE_RXDP_BYPASS_MODE_DCC (1 << 1)
#define RF_DFE_RXDP_BYPASS_MODE_RC (1 << 3)
#define RF_DFE_RXDP_BYPASS_MODE_MIXER (1 << 4)
#define RF_DFE_RXDP_BYPASS_MODE_NOTCH1_1 (1 << 5)
#define RF_DFE_RXDP_BYPASS_MODE_GDEQ (1 << 7)
#define RF_DFE_RXDP_BYPASS_MODE_ACI_LPF (1 << 10)
#define RF_DFE_RXDP_BYPASS_MODE_DNBH1 (1 << 11)
#define RF_DFE_RXDP_BYPASS_MODE_NOTCH2_1 (1 << 12)
#define RF_DFE_RXDP_BYPASS_MODE_NOTCH2_2 (1 << 13)
#define RF_DFE_RXDP_BYPASS_MODE_GAINBB (1 << 14)

// rxdp_bypass_mode_control_reg2
#define RF_DFE_RXDP_BYPASS_MODE_MRRM (1 << 4)
#define RF_DFE_RXDP_BYPASS_MODE_IMBC (1 << 5)
#define RF_DFE_RXDP_BYPASS_MODE_DNHB2 (1 << 6)

// rxdp_dcc_re_real_reg
#define RF_DFE_RXDP_DCC_RE_REAL(n) (((n)&0xffff) << 0)

// rxdp_dcc_im_real_reg
#define RF_DFE_RXDP_DCC_IM_REAL(n) (((n)&0xffff) << 0)

// rssi_real_ib_rssi
#define RF_DFE_RSSI_REG_REAL_IB_RSSI(n) (((n)&0x3ff) << 0)

// rssi_wd_real_ob_rssi
#define RF_DFE_RSSI_REG_WD_REAL_OB_RSSI(n) (((n)&0x3ff) << 0)

// rssi_up_real_ob_rssi
#define RF_DFE_RSSI_REG_UP_REAL_OB_RSSI(n) (((n)&0x3ff) << 0)

// rssi_dn_real_ob_rssi
#define RF_DFE_RSSI_REG_DN_REAL_OB_RSSI(n) (((n)&0x3ff) << 0)

// rxdp_imbc_wa_out_real_reg
#define RF_DFE_RXDP_IMBC_WA_OUT_REAL(n) (((n)&0xffff) << 0)

// rxdp_imbc_wq_out_real_reg
#define RF_DFE_RXDP_IMBC_WQ_OUT_REAL(n) (((n)&0xffff) << 0)

// start_max_min_rssi3_reg
#define RF_DFE_START_MAX_MIN_RSSI3 (1 << 0)

// count_16lsb_rssi3_reg
#define RF_DFE_COUNT_16LSB_RSSI3(n) (((n)&0xffff) << 0)

// count_16msb_rssi3_reg
#define RF_DFE_COUNT_16MSB_RSSI3(n) (((n)&0xffff) << 0)

// load_max_min_rssi3_reg
#define RF_DFE_LOAD_MAX_MIN_RSSI3 (1 << 0)

// rssi_min_rssi3
#define RF_DFE_RSSI_MIN_REG_RSSI3(n) (((n)&0x3ff) << 0)
#define RF_DFE_RSSI_MAX_MIN_VAL_REG_RSSI3 (1 << 10)

// rssi_max_rssi3
#define RF_DFE_RSSI_MAX_REG_RSSI3(n) (((n)&0x3ff) << 0)

// int_rssi3
#define RF_DFE_INT_CLEAR_RSSI3 (1 << 0)
#define RF_DFE_INT_MASK_RSSI3 (1 << 1)
#define RF_DFE_RSSI_INT_RSSI3 (1 << 2)

// load_rssi3_reg
#define RF_DFE_LOAD_RSSI3 (1 << 0)

// rssi_val_rssi3
#define RF_DFE_RSSI_VAL_REG_RSSI3 (1 << 0)

// rssi_rssi3
#define RF_DFE_RSSI_REG_RSSI3(n) (((n)&0x3ff) << 0)

// rssi_real_rssi3
#define RF_DFE_RSSI_REG_REAL_RSSI3(n) (((n)&0x3ff) << 0)

// rxdp_notch_cordic_enable_reg
#define RF_DFE_RXDP_NOTCH1_CORDIC_ENABLE (1 << 0)
#define RF_DFE_RXDP_NOTCH2_CORDIC0_ENABLE (1 << 1)
#define RF_DFE_RXDP_NOTCH2_CORDIC1_ENABLE (1 << 2)
#define RF_DFE_RXDP_NOTCH_CORDIC_GAIN_SEL(n) (((n)&0x3) << 3)

// rxdp_notch1_cordic_amp_reg
#define RF_DFE_RXDP_NOTCH1_CORDIC_AMP(n) (((n)&0x3fff) << 0)

// rxdp_notch1_cordic_zin_reg
#define RF_DFE_RXDP_NOTCH1_CORDIC_ZIN(n) (((n)&0x3fff) << 0)

// rxdp_notch2_cordic0_amp_reg
#define RF_DFE_RXDP_NOTCH2_CORDIC0_AMP(n) (((n)&0x3fff) << 0)

// rxdp_notch2_cordic0_zin_reg
#define RF_DFE_RXDP_NOTCH2_CORDIC0_ZIN(n) (((n)&0x3fff) << 0)

// rxdp_notch2_cordic1_amp_reg
#define RF_DFE_RXDP_NOTCH2_CORDIC1_AMP(n) (((n)&0x3fff) << 0)

// rxdp_notch2_cordic1_zin_reg
#define RF_DFE_RXDP_NOTCH2_CORDIC1_ZIN(n) (((n)&0x3fff) << 0)

// txdp_cfr_th_liner_reg
#define RF_DFE_TXDP_CFR_TH_LINER(n) (((n)&0xfff) << 0)

// txdp_sine_rate_reg
#define RF_DFE_TXDP_SINE_RATE(n) (((n)&0xff) << 0)

// txdp_rc_stretch_reg
#define RF_DFE_TXDP_RC_STRETCH(n) (((n)&0xff) << 0)

// txdp_rc_rate_ofs_rest_reg
#define RF_DFE_TXDP_RC_RATE_OFS_REST(n) (((n)&0x3ff) << 0)

// txdp_rc_rate_ofs_period_reg
#define RF_DFE_TXDP_RC_RATE_OFS_PERIOD(n) (((n)&0x3ff) << 0)

// txdp_rc_rate_ofs_hi_reg
#define RF_DFE_TXDP_RC_RATE_OFS_HI(n) (((n)&0xff) << 0)

// txdp_rc_rate_ofs_lo_reg
#define RF_DFE_TXDP_RC_RATE_OFS_LO(n) (((n)&0xffff) << 0)

// clk_convert_rate_reg
#define RF_DFE_CLK_CONVERT_RATE_A(n) (((n)&0xff) << 0)
#define RF_DFE_CLK_CONVERT_RATE_B(n) (((n)&0xff) << 8)

// rxdp_notch1_cordic_dout_i_reg
#define RF_DFE_RXDP_NOTCH1_CORDIC_DOUT_I(n) (((n)&0xfff) << 0)

// rxdp_notch1_cordic_dout_q_reg
#define RF_DFE_RXDP_NOTCH1_CORDIC_DOUT_Q(n) (((n)&0xfff) << 0)

// rxdp_notch2_cordic0_dout_i_reg
#define RF_DFE_RXDP_NOTCH2_CORDIC0_DOUT_I(n) (((n)&0xfff) << 0)

// rxdp_notch2_cordic0_dout_q_reg
#define RF_DFE_RXDP_NOTCH2_CORDIC0_DOUT_Q(n) (((n)&0xfff) << 0)

// rxdp_notch2_cordic1_dout_i_reg
#define RF_DFE_RXDP_NOTCH2_CORDIC1_DOUT_I(n) (((n)&0xfff) << 0)

// rxdp_notch2_cordic1_dout_q_reg
#define RF_DFE_RXDP_NOTCH2_CORDIC1_DOUT_Q(n) (((n)&0xfff) << 0)

// rxdp_notch_gen_val_reg
#define RF_DFE_RXDP_NOTCH1_CORDIC_DOUT_VAL (1 << 0)
#define RF_DFE_RXDP_NOTCH2_CORDIC0_DOUT_VAL (1 << 1)
#define RF_DFE_RXDP_NOTCH2_CORDIC1_DOUT_VAL (1 << 2)

// resetn_notch_gen_reg
#define RF_DFE_RESETN_NOTCH_GEN (1 << 0)

// dfe_dump_smp_rate_reg
#define RF_DFE_DFE_DUMP_SMP_RATE(n) (((n)&0xff) << 0)

// txdp_wedge_gain_ct_reg
#define RF_DFE_TXDP_WEDGE_GAIN_CT(n) (((n)&0x7ff) << 0)
#define RF_DFE_TXDP_WEDGE_GAIN_CT_LOAD_BYPASS (1 << 12)
#define RF_DFE_TXDP_WEDGE_GAIN_CT_LOAD (1 << 13)

// txdp_wedge_am_shrink_reg
#define RF_DFE_TXDP_WEDGE_AM_SHRINK(n) (((n)&0xff) << 0)

// txdp_wedge_pm_shift_reg
#define RF_DFE_TXDP_WEDGE_PM_SHIFT(n) (((n)&0x3) << 0)

// txdp_wedge_am_p0_reg
#define RF_DFE_TXDP_WEDGE_AM_P0(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p1_reg
#define RF_DFE_TXDP_WEDGE_AM_P1(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p2_reg
#define RF_DFE_TXDP_WEDGE_AM_P2(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p3_reg
#define RF_DFE_TXDP_WEDGE_AM_P3(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p4_reg
#define RF_DFE_TXDP_WEDGE_AM_P4(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p5_reg
#define RF_DFE_TXDP_WEDGE_AM_P5(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p6_reg
#define RF_DFE_TXDP_WEDGE_AM_P6(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p7_reg
#define RF_DFE_TXDP_WEDGE_AM_P7(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p8_reg
#define RF_DFE_TXDP_WEDGE_AM_P8(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p9_reg
#define RF_DFE_TXDP_WEDGE_AM_P9(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p10_reg
#define RF_DFE_TXDP_WEDGE_AM_P10(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p11_reg
#define RF_DFE_TXDP_WEDGE_AM_P11(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p12_reg
#define RF_DFE_TXDP_WEDGE_AM_P12(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p13_reg
#define RF_DFE_TXDP_WEDGE_AM_P13(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p14_reg
#define RF_DFE_TXDP_WEDGE_AM_P14(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p15_reg
#define RF_DFE_TXDP_WEDGE_AM_P15(n) (((n)&0x3ff) << 0)

// txdp_wedge_am_p16_reg
#define RF_DFE_TXDP_WEDGE_AM_P16(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p0_reg
#define RF_DFE_TXDP_WEDGE_PM_P0(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p1_reg
#define RF_DFE_TXDP_WEDGE_PM_P1(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p2_reg
#define RF_DFE_TXDP_WEDGE_PM_P2(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p3_reg
#define RF_DFE_TXDP_WEDGE_PM_P3(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p4_reg
#define RF_DFE_TXDP_WEDGE_PM_P4(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p5_reg
#define RF_DFE_TXDP_WEDGE_PM_P5(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p6_reg
#define RF_DFE_TXDP_WEDGE_PM_P6(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p7_reg
#define RF_DFE_TXDP_WEDGE_PM_P7(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p8_reg
#define RF_DFE_TXDP_WEDGE_PM_P8(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p9_reg
#define RF_DFE_TXDP_WEDGE_PM_P9(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p10_reg
#define RF_DFE_TXDP_WEDGE_PM_P10(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p11_reg
#define RF_DFE_TXDP_WEDGE_PM_P11(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p12_reg
#define RF_DFE_TXDP_WEDGE_PM_P12(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p13_reg
#define RF_DFE_TXDP_WEDGE_PM_P13(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p14_reg
#define RF_DFE_TXDP_WEDGE_PM_P14(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p15_reg
#define RF_DFE_TXDP_WEDGE_PM_P15(n) (((n)&0x3ff) << 0)

// txdp_wedge_pm_p16_reg
#define RF_DFE_TXDP_WEDGE_PM_P16(n) (((n)&0x3ff) << 0)

// aclr_coef4
#define RF_DFE_ACLR_COEF04(n) (((n)&0x3ff) << 0)

// aclr_coef5
#define RF_DFE_ACLR_COEF05(n) (((n)&0x3ff) << 0)

// aclr_coef6
#define RF_DFE_ACLR_COEF06(n) (((n)&0x3ff) << 0)

// aclr_coef7
#define RF_DFE_ACLR_COEF07(n) (((n)&0x3ff) << 0)

// clk_convert_rate_load
#define RF_DFE_CLK_CONVERT_RATE_LOAD (1 << 0)

// clk_dac_ctrl
#define RF_DFE_CLK_DAC_SEL (1 << 0)
#define RF_DFE_CLK_DAC_TEST_EN (1 << 1)
#define RF_DFE_CLK_DAC_TEST_SEL(n) (((n)&0x3) << 2)

// txdp_delay_reg
#define RF_DFE_TXDP_DELAY(n) (((n)&0xff) << 0)

// aclr_coef0
#define RF_DFE_ACLR_COEF00(n) (((n)&0x3ff) << 0)

// aclr_coef1
#define RF_DFE_ACLR_COEF01(n) (((n)&0x3ff) << 0)

// aclr_coef2
#define RF_DFE_ACLR_COEF02(n) (((n)&0x3ff) << 0)

// aclr_coef3
#define RF_DFE_ACLR_COEF03(n) (((n)&0x3ff) << 0)

// txdp_gdeq_coef0_rg_1
#define RF_DFE_TXDP_GDEQ_COEF0_RG_LO(n) (((n)&0xffff) << 0)

// txdp_gdeq_coef0_rg_2
#define RF_DFE_TXDP_GDEQ_COEF0_RG_HI(n) (((n)&0xf) << 0)

// txdp_gdeq_coef1_rg_1
#define RF_DFE_TXDP_GDEQ_COEF1_RG_LO(n) (((n)&0xffff) << 0)

// txdp_gdeq_coef1_rg_2
#define RF_DFE_TXDP_GDEQ_COEF1_RG_HI(n) (((n)&0xf) << 0)

// txdp_gdeq_coef2_rg_1
#define RF_DFE_TXDP_GDEQ_COEF2_RG_LO(n) (((n)&0xffff) << 0)

// txdp_gdeq_coef2_rg_2
#define RF_DFE_TXDP_GDEQ_COEF2_RG_HI(n) (((n)&0xf) << 0)

// txdp_gdeq_coef3_rg_1
#define RF_DFE_TXDP_GDEQ_COEF3_RG_LO(n) (((n)&0xffff) << 0)

// txdp_gdeq_coef3_rg_2
#define RF_DFE_TXDP_GDEQ_COEF3_RG_HI(n) (((n)&0xf) << 0)

// txdp_loft_offset_i_reg
#define RF_DFE_TXDP_LOFT_OFFSET_I(n) (((n)&0xfff) << 0)

// txdp_loft_offset_reg
#define RF_DFE_TXDP_LOFT_OFFSET(n) (((n)&0xfff) << 0)

// txdp_loft_phase_err_reg
#define RF_DFE_TXDP_LOFT_PHASE_ERR(n) (((n)&0xfff) << 0)

// txdp_loft_amp_err_reg
#define RF_DFE_TXDP_LOFT_AMP_ERR(n) (((n)&0xfff) << 0)

// txdp_loft_rssi_reg
#define RF_DFE_TXDP_LOFT_RSSI_ERR(n) (((n)&0xffff) << 0)

// txdp_loft_tone_amp_reg
#define RF_DFE_TXDP_LOFT_TONE_AMP(n) (((n)&0xfff) << 0)

// txdp_loft_tone_fre_reg0
#define RF_DFE_TXDP_LOFT_TONE_FRE0(n) (((n)&0xffff) << 0)

// txdp_loft_tone_fre_reg1
#define RF_DFE_TXDP_LOFT_TONE_FRE1(n) (((n)&0x7f) << 0)

// txdp_loft_misc0_reg
#define RF_DFE_TXDP_LOFT_RSSI_LOAD (1 << 0)
#define RF_DFE_TXDP_LOFT_RSSI_ENABLE (1 << 1)
#define RF_DFE_TXDP_LOFT_RSSI_PERIOD_IDX (1 << 2)
#define RF_DFE_TXDP_LOFT_RSSI_USHIFT(n) (((n)&0x7) << 3)
#define RF_DFE_TXDP_LOFT_BPF_BYPASS (1 << 6)
#define RF_DFE_TXDP_LOFT_BPF_ENABLE (1 << 7)
#define RF_DFE_TXDP_LOFT_FLG_LOFT_CALIB (1 << 8)
#define RF_DFE_TXDP_LOFT_AMP_ERR_DR (1 << 9)
#define RF_DFE_TXDP_LOFT_PHASE_ERR_DR (1 << 10)
#define RF_DFE_TXDP_LOFT_OFFSET_DR (1 << 11)
#define RF_DFE_TXDP_LOFT_CANCEL_BYPASS (1 << 12)
#define RF_DFE_TXDP_LOFT_CALI_EN (1 << 13)
#define RF_DFE_TXDP_LOFT_DIN_LOFT_SEL (1 << 14)
#define RF_DFE_TXDP_LOFT_SINCOS_EN (1 << 15)

// txdp_loft_gain1_reg
#define RF_DFE_TXDP_LOFT_GAIN1_CT_SEL (1 << 0)
#define RF_DFE_TXDP_LOFT_GAIN1_CT_DYN(n) (((n)&0x3f) << 1)
#define RF_DFE_TXDP_LOFT_GAIN1_CT(n) (((n)&0x3f) << 7)
#define RF_DFE_TXDP_LOFT_RSSI_VAL (1 << 13)

// data_format_ctrl
#define RF_DFE_DAC_OFF_BIN_EN (1 << 0)
#define RF_DFE_ADC_OFF_BIN_EN (1 << 1)
#define RF_DFE_TX_OFF_BIN_EN (1 << 2)
#define RF_DFE_RX_OFF_BIN_EN (1 << 3)
#define RF_DFE_DAC_IQ_SWAP (1 << 4)
#define RF_DFE_ADC_IQ_SWAP (1 << 5)
#define RF_DFE_TX_IQ_SWAP (1 << 6)
#define RF_DFE_RX_IQ_SWAP (1 << 7)
#define RF_DFE_NB_TX_RX_LOOP (1 << 8)

// txdp_loft_rssi_reg_real
#define RF_DFE_TXDP_LOFT_RSSI_ERR_REAL(n) (((n)&0xffff) << 0)

// temper_tsx_ct
#define RF_DFE_TEMPER_TSX_HOLD_EN (1 << 0)
#define RF_DFE_TEMPER_TSX_LPF_BYPASS (1 << 1)
#define RF_DFE_TEMPER_TSX_BW_SEL(n) (((n)&0x3) << 2)
#define RF_DFE_TEMPER_TSX_USHIFT(n) (((n)&0x7) << 4)
#define RF_DFE_TEMPER_TSX_LPF3_BYPASS (1 << 7)
#define RF_DFE_TEMPER_TSX_POUT_LOAD (1 << 8)
#define RF_DFE_TEMPER_TSX_POUT_VAL_RG (1 << 9)

// temper_tsx_dout_reg
#define RF_DFE_TEMPER_TSX_DOUT(n) (((n)&0xffff) << 0)

// tsx_temp_clk_ct
#define RF_DFE_TEMPER_TSX_CLK_PHASE_SEL (1 << 4)
#define RF_DFE_TEMPER_TSX_CLK_FREQ_SEL(n) (((n)&0x3) << 5)
#define RF_DFE_TEMPER_TSX_CLK_EN (1 << 7)

// temper_tsx_lpf_a11_rg
#define RF_DFE_TEMPER_TSX_LPF_A11(n) (((n)&0x3fff) << 0)

// temper_tsx_lpf_a12_rg
#define RF_DFE_TEMPER_TSX_LPF_A12(n) (((n)&0x3fff) << 0)

// temper_tsx_lpf_g1_rg
#define RF_DFE_TEMPER_TSX_LPF_G1(n) (((n)&0x3fff) << 0)

// temper_tsx_lpf_a21_rg
#define RF_DFE_TEMPER_TSX_LPF_A21(n) (((n)&0x3fff) << 0)

// temper_tsx_lpf_a22_rg
#define RF_DFE_TEMPER_TSX_LPF_A22(n) (((n)&0x3fff) << 0)

// temper_tsx_lpf_g2_rg
#define RF_DFE_TEMPER_TSX_LPF_G2(n) (((n)&0x3fff) << 0)

// temper_tsx_dout_real_reg
#define RF_DFE_TEMPER_TSX_DOUT_REAL(n) (((n)&0xffff) << 0)

// temper_ct
#define RF_DFE_TEMPER_HOLD_EN (1 << 0)
#define RF_DFE_TEMPER_LPF_BYPASS (1 << 1)
#define RF_DFE_TEMPER_BW_SEL(n) (((n)&0x3) << 2)
#define RF_DFE_TEMPER_USHIFT(n) (((n)&0x7) << 4)
#define RF_DFE_TEMPER_LPF3_BYPASS (1 << 7)
#define RF_DFE_TEMPER_POUT_LOAD (1 << 8)
#define RF_DFE_TEMPER_POUT_VAL_RG (1 << 9)

// temper_dout_reg
#define RF_DFE_TEMPER_DOUT(n) (((n)&0xffff) << 0)

// osc_temp_clk_ct
#define RF_DFE_TEMPER_CLK_PHASE_SEL (1 << 4)
#define RF_DFE_TEMPER_CLK_FREQ_SEL(n) (((n)&0x3) << 5)
#define RF_DFE_TEMPER_CLK_EN (1 << 7)

// temper_lpf_a11_rg
#define RF_DFE_TEMPER_LPF_A11(n) (((n)&0x3fff) << 0)

// temper_lpf_a12_rg
#define RF_DFE_TEMPER_LPF_A12(n) (((n)&0x3fff) << 0)

// temper_lpf_g1_rg
#define RF_DFE_TEMPER_LPF_G1(n) (((n)&0x3fff) << 0)

// temper_lpf_a21_rg
#define RF_DFE_TEMPER_LPF_A21(n) (((n)&0x3fff) << 0)

// temper_lpf_a22_rg
#define RF_DFE_TEMPER_LPF_A22(n) (((n)&0x3fff) << 0)

// temper_lpf_g2_rg
#define RF_DFE_TEMPER_LPF_G2(n) (((n)&0x3fff) << 0)

// temper_dout_real_reg
#define RF_DFE_TEMPER_DOUT_REAL(n) (((n)&0xffff) << 0)

// dfe_sw_clkgate_en_rg
#define RF_DFE_DFE_SW_CLKGATE_EN (1 << 0)

// mon_ct
#define RF_DFE_DFE_MONITOR_SEL(n) (((n)&0xf) << 0)
#define RF_DFE_DFE_MONITOR_SWAP (1 << 4)

// dac_offset_re_rg
#define RF_DFE_DAC_OFFSET_RE(n) (((n)&0xfff) << 0)

// dac_offset_im_rg
#define RF_DFE_DAC_OFFSET_IM(n) (((n)&0xfff) << 0)

// dac_tx_amp_re_rg
#define RF_DFE_DAC_TX_AMP_RE(n) (((n)&0xfff) << 0)

// dac_tx_amp_im_rg
#define RF_DFE_DAC_TX_AMP_IM(n) (((n)&0xfff) << 0)

// data_dac_ctrl
#define RF_DFE_TXDP_TEST_DAC_SEL_RG(n) (((n)&0x1f) << 0)
#define RF_DFE_TXDP_TEST_DAC_EN_RG (1 << 5)
#define RF_DFE_RXDP_TEST_DAC_SEL_RG(n) (((n)&0x1f) << 6)
#define RF_DFE_RXDP_TEST_DAC_EN_RG (1 << 11)
#define RF_DFE_SINE_ENABLE_RG (1 << 12)
#define RF_DFE_DATA_DAC_SEL(n) (((n)&0x3) << 13)

// sincos_amp
#define RF_DFE_SINCOS_AMP_RG(n) (((n)&0xfff) << 0)

// sincos_fre_lo
#define RF_DFE_SINCOS_FRE_RG_LO(n) (((n)&0xffff) << 0)

// sincos_fre_hi
#define RF_DFE_SINCOS_FRE_RG_HI(n) (((n)&0x7f) << 0)
#define RF_DFE_TXDP_BYPASS_MODE_LOFT (1 << 7)
#define RF_DFE_TXDP_BYPASS_LOFT (1 << 8)

// txdp_bypass_reg
#define RF_DFE_TXDP_BYPASS_AMPEQU (1 << 0)
#define RF_DFE_TXDP_BYPASS_ACLR_LPF (1 << 1)
#define RF_DFE_TXDP_BYPASS_UPHB1 (1 << 2)
#define RF_DFE_TXDP_BYPASS_CFR (1 << 3)
#define RF_DFE_TXDP_BYPASS_GAIN (1 << 5)
#define RF_DFE_TXDP_BYPASS_RC (1 << 6)
#define RF_DFE_TXDP_BYPASS_POLARIQ (1 << 7)
#define RF_DFE_TXDP_BYPASS_POLARIQ_AMPM (1 << 9)
#define RF_DFE_TXDP_BYPASS_GDEQ (1 << 11)
#define RF_DFE_TXDP_BYPASS_UPHB4 (1 << 12)
#define RF_DFE_TXDP_BYPASS_UPHB5 (1 << 13)

// txdp_bypass_mode_reg
#define RF_DFE_TXDP_BYPASS_MODE_AMPEQU (1 << 0)
#define RF_DFE_TXDP_BYPASS_MODE_ACLR_LPF (1 << 1)
#define RF_DFE_TXDP_BYPASS_MODE_UPHB1 (1 << 2)
#define RF_DFE_TXDP_BYPASS_MODE_CFR (1 << 3)
#define RF_DFE_TXDP_BYPASS_MODE_GAIN (1 << 5)
#define RF_DFE_TXDP_BYPASS_MODE_RC (1 << 6)
#define RF_DFE_TXDP_BYPASS_MODE_POLARIQ (1 << 7)
#define RF_DFE_TXDP_BYPASS_MODE_POLARIQ_AMPM (1 << 9)
#define RF_DFE_TXDP_BYPASS_MODE_GDEQ (1 << 11)
#define RF_DFE_TXDP_BYPASS_MODE_UPHB4 (1 << 12)
#define RF_DFE_TXDP_BYPASS_MODE_UPHB5 (1 << 13)

// reserved_all_zeros_reg
#define RF_DFE_RSV_ALL_ZERO(n) (((n)&0xffff) << 0)

// reserved_all_ones_reg
#define RF_DFE_RSV_ALL_ONES(n) (((n)&0xffff) << 0)

// pwr_rf_acc_len_reg
#define RF_DFE_PWR_RF_ACC_LEN_RG(n) (((n)&0xffff) << 0)

// pwr_rf_acc_misc_reg
#define RF_DFE_PWR_RF_POLAR_RG (1 << 0)
#define RF_DFE_PWR_RF_START_RG (1 << 1)
#define RF_DFE_PWR_RF_USHIFT_RG(n) (((n)&0x7) << 2)
#define RF_DFE_PWR_ADC_OFF_BIN_EN (1 << 5)

// pwr_rf_acc_report_reg
#define RF_DFE_PWR_RF_CALC_DONE (1 << 0)
#define RF_DFE_PWR_RF_O(n) (((n)&0x7ff) << 1)

// txdp_clk_gate_enable_reg
#define RF_DFE_TXDP_SINE_CLKGATE_EN (1 << 0)
#define RF_DFE_TXDP_LOFT_CLKGATE_EN (1 << 2)
#define RF_DFE_TXDP_UPHB5_CLKGATE_EN (1 << 4)
#define RF_DFE_TXDP_UPHB4_CLKGATE_EN (1 << 5)
#define RF_DFE_TXDP_GDEQ_CLKGATE_EN (1 << 6)
#define RF_DFE_TXDP_DPD_CLKGATE_EN (1 << 7)
#define RF_DFE_TXDP_RC_CLKGATE_EN (1 << 8)
#define RF_DFE_TXDP_GAIN_CLKGATE_EN (1 << 9)
#define RF_DFE_TXDP_UPHB1_CLKGATE_EN (1 << 12)
#define RF_DFE_TXDP_ACLR_CLKGATE_EN (1 << 13)
#define RF_DFE_TXDP_AMPEQU_CLKGATE_EN (1 << 14)

// rxdp_clk_gate_enable_reg2
#define RF_DFE_RXDP_RC_CLKGATE_EN (1 << 0)

// rxdp_clk_gate_enable_reg1
#define RF_DFE_RXDP_RSSI3_CLKGATE_EN (1 << 0)
#define RF_DFE_RXDP_NOTCH_GEN_CLKGATE_EN (1 << 1)
#define RF_DFE_RXDP_IB_CLKGATE_EN (1 << 3)
#define RF_DFE_RXDP_DNHB2_CLKGATE_EN (1 << 4)
#define RF_DFE_RXDP_GAINBB_CLKGATE_EN (1 << 5)
#define RF_DFE_RXDP_NOTCH2_CLKGATE_EN (1 << 6)
#define RF_DFE_RXDP_ACI_CLKGATE_EN (1 << 7)
#define RF_DFE_RXDP_DNHB1_CLKGATE_EN (1 << 8)
#define RF_DFE_RXDP_MRRM_CLKGATE_EN (1 << 9)
#define RF_DFE_RXDP_OB_CLKGATE_EN (1 << 10)
#define RF_DFE_RXDP_GDEQ_CLKGATE_EN (1 << 12)
#define RF_DFE_RXDP_NOTCH1_CLKGATE_EN (1 << 13)
#define RF_DFE_RXDP_MIXER_CLKGATE_EN (1 << 14)
#define RF_DFE_RXDP_IMBC_CLKGATE_EN (1 << 15)

// test_dac_bits_sel_register
#define RF_DFE_TEST_DAC_BITS_SEL(n) (((n)&0x7) << 0)

// txdp_ampequ_coef0_rg_1
#define RF_DFE_TXDP_AMPEQU_COEF0_RG(n) (((n)&0xfff) << 0)

// txdp_ampequ_coef1_rg_1
#define RF_DFE_TXDP_AMPEQU_COEF1_RG(n) (((n)&0xfff) << 0)

// txdp_ampequ_coef2_rg_1
#define RF_DFE_TXDP_AMPEQU_COEF2_RG(n) (((n)&0xfff) << 0)

// txdp_ampequ_coef3_rg_1
#define RF_DFE_TXDP_AMPEQU_COEF3_RG(n) (((n)&0xfff) << 0)

// txdp_ampequ_g
#define RF_DFE_TXDP_AMPEQU_G_RG(n) (((n)&0xffff) << 0)

// txdp_ampequ_g_ext_reg
#define RF_DFE_TXDP_AMPEQU_G_EXT(n) (((n)&0xfff) << 0)

// fifo_sample_rate_reg1
#define RF_DFE_FIFO_B_SMP_RATE_RG(n) (((n)&0xf) << 0)
#define RF_DFE_FIFO_A_SMP_RATE_RG(n) (((n)&0x7f) << 4)

// fifo_status_reg
#define RF_DFE_FIFO_A_EMPTY_STATUS (1 << 0)
#define RF_DFE_FIFO_A_FULL_STATUS (1 << 1)
#define RF_DFE_FIFO_B_EMPTY_STATUS (1 << 2)
#define RF_DFE_FIFO_B_FULL_STATUS (1 << 3)
#define RF_DFE_FIFO_ADC_EMPTY_STATUS (1 << 8)
#define RF_DFE_FIFO_ADC_FULL_STATUS (1 << 9)
#define RF_DFE_FIFO_RXDP_RC_EMPTY_STATUS (1 << 10)
#define RF_DFE_FIFO_RXDP_RC_FULL_STATUS (1 << 11)
#define RF_DFE_FIFO_TXDP_RC_EMPTY_STATUS (1 << 12)
#define RF_DFE_FIFO_TXDP_RC_FULL_STATUS (1 << 13)
#define RF_DFE_FIFO_DUMP_EMPTY_STATUS (1 << 14)
#define RF_DFE_FIFO_DUMP_FULL_STATUS (1 << 15)

// dfe_dump_reg
#define RF_DFE_DFE_DUMP_SEL(n) (((n)&0x3) << 0)
#define RF_DFE_DFE_DUMP_RESETN (1 << 2)
#define RF_DFE_DFE_DUMP_EN (1 << 3)
#define RF_DFE_DFE_DUMP_VLD_SEL(n) (((n)&0x3) << 4)
#define RF_DFE_SEL_CLK_DUMP_W(n) (((n)&0xf) << 8)

// aclr_coef8
#define RF_DFE_ACLR_COEF08(n) (((n)&0x3ff) << 0)

// aclr_coef9
#define RF_DFE_ACLR_COEF09(n) (((n)&0x3ff) << 0)

// aclr_coef10
#define RF_DFE_ACLR_COEF10(n) (((n)&0x3ff) << 0)

// aclr_coef11
#define RF_DFE_ACLR_COEF11(n) (((n)&0x3ff) << 0)

// aclr_coef12
#define RF_DFE_ACLR_COEF12(n) (((n)&0x3ff) << 0)

// aclr_coef13
#define RF_DFE_ACLR_COEF13(n) (((n)&0x3ff) << 0)

// aclr_coef14
#define RF_DFE_ACLR_COEF14(n) (((n)&0x3ff) << 0)

// aclr_coef15
#define RF_DFE_ACLR_COEF15(n) (((n)&0x3ff) << 0)

// aclr_coef16
#define RF_DFE_ACLR_COEF16(n) (((n)&0x3ff) << 0)

// aclr_coef17
#define RF_DFE_ACLR_COEF17(n) (((n)&0x3ff) << 0)

// aclr_coef18
#define RF_DFE_ACLR_COEF18(n) (((n)&0x3ff) << 0)

// aclr_coef19
#define RF_DFE_ACLR_COEF19(n) (((n)&0x3ff) << 0)

// aclr_coef20
#define RF_DFE_ACLR_COEF20(n) (((n)&0x3ff) << 0)

// aclr_coef21
#define RF_DFE_ACLR_COEF21(n) (((n)&0x3ff) << 0)

// aclr_coef22
#define RF_DFE_ACLR_COEF22(n) (((n)&0x3ff) << 0)

// aclr_coef23
#define RF_DFE_ACLR_COEF23(n) (((n)&0x3ff) << 0)

// pwd_dcc
#define RF_DFE_PWD_DCC_RX_CALIB_SEL_RG (1 << 0)
#define RF_DFE_PWD_DCC_DC_CALIB_EN_RG (1 << 1)
#define RF_DFE_PWD_DCC_DC_DELTA_LD_ST_RG (1 << 2)
#define RF_DFE_PWD_DCC_BYPASS_RG (1 << 3)
#define RF_DFE_PWD_DCC_HOLD_EN_RG (1 << 4)
#define RF_DFE_PWD_DCC_IMGREJ_RG (1 << 5)
#define RF_DFE_PWD_DCC_LOAD (1 << 6)

// pwd_dc_calib_re
#define RF_DFE_PWD_DC_CALIB_RE_RG(n) (((n)&0x3ff) << 0)

// pwd_dc_calib_im
#define RF_DFE_PWD_DC_CALIB_IM_RG(n) (((n)&0x3ff) << 0)

// pwd_dc_delta_re
#define RF_DFE_PWD_DC_DELTA_RE_RG(n) (((n)&0x3ff) << 0)

// pwd_dc_delta_im
#define RF_DFE_PWD_DC_DELTA_IM_RG(n) (((n)&0x3ff) << 0)

// pwd_dc_cr
#define RF_DFE_PWD_CONV_MODE_CT_RG(n) (((n)&0x3) << 0)
#define RF_DFE_PWD_CONV_TMR_CT_RG(n) (((n)&0xf) << 2)
#define RF_DFE_PWD_CONV_FAST_BW_CT_RG(n) (((n)&0x7) << 6)
#define RF_DFE_PWD_CONV_SLOW_BW_CT_RG(n) (((n)&0x7) << 9)

// pwd_dcc_valid_o_reg
#define RF_DFE_PWD_DCC_VAL_REG (1 << 0)

// pwd_dcc_re_o_reg
#define RF_DFE_PWD_DCC_RE_O(n) (((n)&0x3ff) << 0)

// pwd_dcc_im_o_reg
#define RF_DFE_PWD_DCC_IM_O(n) (((n)&0x3ff) << 0)

// pwd_dcc_re_real_reg
#define RF_DFE_PWD_DCC_RE_REAL(n) (((n)&0x3ff) << 0)

// pwd_dcc_im_real_reg
#define RF_DFE_PWD_DCC_IM_REAL(n) (((n)&0x3ff) << 0)

#endif // _RF_DFE_H_