EC600G/components/hal/include/hwregs/8850/rxcapt.h

/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _RXCAPT_H_
#define _RXCAPT_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_RXCAPT_BASE (0x1a000000)

typedef volatile struct
{
    uint32_t rxcapt_en;       // 0x00000000
    uint32_t capt_cfg;        // 0x00000004
    uint32_t fill_cfg1;       // 0x00000008
    uint32_t fill_cfg2;       // 0x0000000c
    uint32_t dma_req_en;      // 0x00000010
    uint32_t irq_inten;       // 0x00000014
    uint32_t irq_inten_set;   // 0x00000018
    uint32_t irq_inten_clr;   // 0x0000001c
    uint32_t irq_state;       // 0x00000020
    uint32_t capt_end_addr12; // 0x00000024
    uint32_t capt_end_addr34; // 0x00000028
    uint32_t fill_end_addr12; // 0x0000002c
    uint32_t fill_end_addr56; // 0x00000030
    uint32_t norm_ctrl;       // 0x00000034
    uint32_t state_mem12;     // 0x00000038
    uint32_t state_mem34;     // 0x0000003c
    uint32_t state_mem56;     // 0x00000040
    uint32_t state_err12;     // 0x00000044
    uint32_t state_err34;     // 0x00000048
    uint32_t capt_sta;        // 0x0000004c
    uint32_t fill1_sta1;      // 0x00000050
    uint32_t fill1_sta2;      // 0x00000054
    uint32_t fill2_sta1;      // 0x00000058
    uint32_t fill2_sta2;      // 0x0000005c
    uint32_t dma_sta;         // 0x00000060
    uint32_t capt12_len;      // 0x00000064
    uint32_t capt34_len;      // 0x00000068
    uint32_t err_inten;       // 0x0000006c
    uint32_t err_inten_set;   // 0x00000070
    uint32_t err_inten_clr;   // 0x00000074
    uint32_t err_int_sta;     // 0x00000078
    uint32_t __124[16353];    // 0x0000007c
    uint32_t mem12_ping;      // 0x00010000
    uint32_t __65540[2047];   // 0x00010004
    uint32_t mem12_pang;      // 0x00012000
    uint32_t __73732[2047];   // 0x00012004
    uint32_t mem34_ping;      // 0x00014000
    uint32_t __81924[511];    // 0x00014004
    uint32_t mem34_pang;      // 0x00014800
    uint32_t __83972[511];    // 0x00014804
    uint32_t mem56_ping;      // 0x00015000
    uint32_t __86020[1023];   // 0x00015004
    uint32_t mem56_pang;      // 0x00016000
} HWP_RXCAPT_T;

#define hwp_rxcapt ((HWP_RXCAPT_T *)REG_ACCESS_ADDRESS(REG_RXCAPT_BASE))

// rxcapt_en
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rxcapt_en : 1; // [0]
        uint32_t __31_1 : 31;   // [31:1]
    } b;
} REG_RXCAPT_RXCAPT_EN_T;

// capt_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t capt_rx : 1;            // [0]
        uint32_t capt_odtoa : 1;         // [1]
        uint32_t capt_iddet_offline : 1; // [2]
        uint32_t capt_tx : 1;            // [3]
        uint32_t capt_dump : 1;          // [4]
        uint32_t __31_5 : 27;            // [31:5]
    } b;
} REG_RXCAPT_CAPT_CFG_T;

// fill_cfg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fill_div : 3;        // [2:0]
        uint32_t fill_dl_offline : 1; // [3]
        uint32_t fill_len : 28;       // [31:4]
    } b;
} REG_RXCAPT_FILL_CFG1_T;

// fill_cfg2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fill_div : 3;           // [2:0]
        uint32_t fill_iddet_offline : 1; // [3]
        uint32_t fill_len : 28;          // [31:4]
    } b;
} REG_RXCAPT_FILL_CFG2_T;

// dma_req_en
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dma_req0_en : 1; // [0]
        uint32_t dma_req1_en : 1; // [1]
        uint32_t dma_req2_en : 1; // [2]
        uint32_t dma_req3_en : 1; // [3]
        uint32_t dma_req4_en : 1; // [4]
        uint32_t dma_req5_en : 1; // [5]
        uint32_t dma_req6_en : 1; // [6]
        uint32_t dma_req7_en : 1; // [7]
        uint32_t __31_8 : 24;     // [31:8]
    } b;
} REG_RXCAPT_DMA_REQ_EN_T;

// irq_inten
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mem12_ping_irq : 1;   // [0]
        uint32_t mem12_pang_irq : 1;   // [1]
        uint32_t mem12_finish_irq : 1; // [2]
        uint32_t __3_3 : 1;            // [3]
        uint32_t mem34_ping_irq : 1;   // [4]
        uint32_t mem34_pang_irq : 1;   // [5]
        uint32_t mem34_finish_irq : 1; // [6]
        uint32_t __7_7 : 1;            // [7]
        uint32_t mem56_ping_irq : 1;   // [8]
        uint32_t mem56_pang_irq : 1;   // [9]
        uint32_t mem56_finish_irq : 1; // [10]
        uint32_t __11_11 : 1;          // [11]
        uint32_t capt_err12 : 1;       // [12]
        uint32_t capt_err34 : 1;       // [13]
        uint32_t __31_14 : 18;         // [31:14]
    } b;
} REG_RXCAPT_IRQ_INTEN_T;

// irq_inten_set
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mem12_ping_irq : 1;   // [0], write set
        uint32_t mem12_pang_irq : 1;   // [1], write set
        uint32_t mem12_finish_irq : 1; // [2], write set
        uint32_t __3_3 : 1;            // [3]
        uint32_t mem34_ping_irq : 1;   // [4], write set
        uint32_t mem34_pang_irq : 1;   // [5], write set
        uint32_t mem34_finish_irq : 1; // [6], write set
        uint32_t __7_7 : 1;            // [7]
        uint32_t mem56_ping_irq : 1;   // [8], write set
        uint32_t mem56_pang_irq : 1;   // [9], write set
        uint32_t mem56_finish_irq : 1; // [10], write set
        uint32_t __11_11 : 1;          // [11]
        uint32_t capt_err12 : 1;       // [12], write set
        uint32_t capt_err34 : 1;       // [13], write set
        uint32_t __31_14 : 18;         // [31:14]
    } b;
} REG_RXCAPT_IRQ_INTEN_SET_T;

// irq_inten_clr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mem12_ping_irq : 1;   // [0], write clear
        uint32_t mem12_pang_irq : 1;   // [1], write clear
        uint32_t mem12_finish_irq : 1; // [2], write clear
        uint32_t __3_3 : 1;            // [3]
        uint32_t mem34_ping_irq : 1;   // [4], write clear
        uint32_t mem34_pang_irq : 1;   // [5], write clear
        uint32_t mem34_finish_irq : 1; // [6], write clear
        uint32_t __7_7 : 1;            // [7]
        uint32_t mem56_ping_irq : 1;   // [8], write clear
        uint32_t mem56_pang_irq : 1;   // [9], write clear
        uint32_t mem56_finish_irq : 1; // [10], write clear
        uint32_t __11_11 : 1;          // [11]
        uint32_t capt_err12 : 1;       // [12], write clear
        uint32_t capt_err34 : 1;       // [13], write clear
        uint32_t __31_14 : 18;         // [31:14]
    } b;
} REG_RXCAPT_IRQ_INTEN_CLR_T;

// irq_state
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mem12_ping_irq : 1;   // [0], write clear
        uint32_t mem12_pang_irq : 1;   // [1], write clear
        uint32_t mem12_finish_irq : 1; // [2], write clear
        uint32_t __3_3 : 1;            // [3]
        uint32_t mem34_ping_irq : 1;   // [4], write clear
        uint32_t mem34_pang_irq : 1;   // [5], write clear
        uint32_t mem34_finish_irq : 1; // [6], write clear
        uint32_t __7_7 : 1;            // [7]
        uint32_t mem56_ping_irq : 1;   // [8], write clear
        uint32_t mem56_pang_irq : 1;   // [9], write clear
        uint32_t mem56_finish_irq : 1; // [10], write clear
        uint32_t __11_11 : 1;          // [11]
        uint32_t capt_err12_irq : 1;   // [12], write clear
        uint32_t capt_err34_irq : 1;   // [13], write clear
        uint32_t __31_14 : 18;         // [31:14]
    } b;
} REG_RXCAPT_IRQ_STATE_T;

// capt_end_addr12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t end_addr12 : 11; // [10:0]
        uint32_t __31_11 : 21;    // [31:11]
    } b;
} REG_RXCAPT_CAPT_END_ADDR12_T;

// capt_end_addr34
typedef union {
    uint32_t v;
    struct
    {
        uint32_t end_addr34 : 9; // [8:0]
        uint32_t __31_9 : 23;    // [31:9]
    } b;
} REG_RXCAPT_CAPT_END_ADDR34_T;

// fill_end_addr12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t end_addr12 : 11; // [10:0]
        uint32_t __31_11 : 21;    // [31:11]
    } b;
} REG_RXCAPT_FILL_END_ADDR12_T;

// fill_end_addr56
typedef union {
    uint32_t v;
    struct
    {
        uint32_t end_addr56 : 10; // [9:0]
        uint32_t __31_10 : 22;    // [31:10]
    } b;
} REG_RXCAPT_FILL_END_ADDR56_T;

// state_mem12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ping_addr : 11; // [10:0], read only
        uint32_t __11_11 : 1;    // [11]
        uint32_t ping_sta : 3;   // [14:12], read only
        uint32_t __15_15 : 1;    // [15]
        uint32_t pang_addr : 11; // [26:16], read only
        uint32_t __27_27 : 1;    // [27]
        uint32_t pang_sta : 3;   // [30:28], read only
        uint32_t __31_31 : 1;    // [31]
    } b;
} REG_RXCAPT_STATE_MEM12_T;

// state_mem34
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ping_addr : 9; // [8:0], read only
        uint32_t __11_9 : 3;    // [11:9]
        uint32_t ping_sta : 3;  // [14:12], read only
        uint32_t __15_15 : 1;   // [15]
        uint32_t pang_addr : 9; // [24:16], read only
        uint32_t __27_25 : 3;   // [27:25]
        uint32_t pang_sta : 3;  // [30:28], read only
        uint32_t __31_31 : 1;   // [31]
    } b;
} REG_RXCAPT_STATE_MEM34_T;

// state_mem56
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ping_addr : 10; // [9:0], read only
        uint32_t __11_10 : 2;    // [11:10]
        uint32_t ping_sta : 3;   // [14:12], read only
        uint32_t __15_15 : 1;    // [15]
        uint32_t pang_addr : 10; // [25:16], read only
        uint32_t __27_26 : 2;    // [27:26]
        uint32_t pang_sta : 3;   // [30:28], read only
        uint32_t __31_31 : 1;    // [31]
    } b;
} REG_RXCAPT_STATE_MEM56_T;

// state_err12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t err_fn : 24;   // [23:0], read only
        uint32_t which_mem : 1; // [24], read only
        uint32_t __31_25 : 7;   // [31:25]
    } b;
} REG_RXCAPT_STATE_ERR12_T;

// state_err34
typedef union {
    uint32_t v;
    struct
    {
        uint32_t err_fn : 24;   // [23:0], read only
        uint32_t which_mem : 1; // [24], read only
        uint32_t __31_25 : 7;   // [31:25]
    } b;
} REG_RXCAPT_STATE_ERR34_T;

// capt_sta
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rx_sta : 2;    // [1:0], read only
        uint32_t __3_2 : 2;     // [3:2]
        uint32_t dump_sta : 2;  // [5:4], read only
        uint32_t __7_6 : 2;     // [7:6]
        uint32_t tx_sta : 2;    // [9:8], read only
        uint32_t __11_10 : 2;   // [11:10]
        uint32_t iddet_sta : 2; // [13:12], read only
        uint32_t __15_14 : 2;   // [15:14]
        uint32_t otdoa_sta : 2; // [17:16], read only
        uint32_t __31_18 : 14;  // [31:18]
    } b;
} REG_RXCAPT_CAPT_STA_T;

// fill1_sta1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t out_len : 28;         // [27:0], read only
        uint32_t fill_running_sta : 2; // [29:28], read only
        uint32_t __31_30 : 2;          // [31:30]
    } b;
} REG_RXCAPT_FILL1_STA1_T;

// fill1_sta2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t in_len : 28; // [27:0], read only
        uint32_t __31_28 : 4; // [31:28]
    } b;
} REG_RXCAPT_FILL1_STA2_T;

// fill2_sta1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t out_len : 28;         // [27:0], read only
        uint32_t fill_running_sta : 2; // [29:28], read only
        uint32_t __31_30 : 2;          // [31:30]
    } b;
} REG_RXCAPT_FILL2_STA1_T;

// fill2_sta2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t in_len : 28; // [27:0], read only
        uint32_t __31_28 : 4; // [31:28]
    } b;
} REG_RXCAPT_FILL2_STA2_T;

// dma_sta
typedef union {
    uint32_t v;
    struct
    {
        uint32_t req_sta : 8;  // [7:0], read only
        uint32_t ack_sta : 8;  // [15:8], read only
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_RXCAPT_DMA_STA_T;

// capt12_len
typedef union {
    uint32_t v;
    struct
    {
        uint32_t current_len12 : 24; // [23:0], read only
        uint32_t __31_24 : 8;        // [31:24]
    } b;
} REG_RXCAPT_CAPT12_LEN_T;

// capt34_len
typedef union {
    uint32_t v;
    struct
    {
        uint32_t current_len34 : 24; // [23:0], read only
        uint32_t __31_24 : 8;        // [31:24]
    } b;
} REG_RXCAPT_CAPT34_LEN_T;

// err_inten
typedef union {
    uint32_t v;
    struct
    {
        uint32_t err_inten_sr : 4; // [3:0]
        uint32_t __31_4 : 28;      // [31:4]
    } b;
} REG_RXCAPT_ERR_INTEN_T;

// err_inten_set
typedef union {
    uint32_t v;
    struct
    {
        uint32_t err_inten_set_sr : 4; // [3:0], write clear
        uint32_t __31_4 : 28;          // [31:4]
    } b;
} REG_RXCAPT_ERR_INTEN_SET_T;

// err_inten_clr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t err_inten_clr_sr : 4; // [3:0], write clear
        uint32_t __31_4 : 28;          // [31:4]
    } b;
} REG_RXCAPT_ERR_INTEN_CLR_T;

// err_int_sta
typedef union {
    uint32_t v;
    struct
    {
        uint32_t err_int_sta : 4; // [3:0], write clear
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_RXCAPT_ERR_INT_STA_T;

// mem12_ping
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;         // [3:0]
        uint32_t mem12_ping_0 : 12; // [15:4]
        uint32_t __19_16 : 4;       // [19:16]
        uint32_t mem12_ping_1 : 12; // [31:20]
    } b;
} REG_RXCAPT_MEM12_PING_T;

// mem12_pang
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;         // [3:0]
        uint32_t mem12_pang_0 : 12; // [15:4]
        uint32_t __19_16 : 4;       // [19:16]
        uint32_t mem12_pang_1 : 12; // [31:20]
    } b;
} REG_RXCAPT_MEM12_PANG_T;

// mem34_ping
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;         // [3:0]
        uint32_t mem34_ping_0 : 12; // [15:4]
        uint32_t __19_16 : 4;       // [19:16]
        uint32_t mem34_ping_1 : 12; // [31:20]
    } b;
} REG_RXCAPT_MEM34_PING_T;

// mem34_pang
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;         // [3:0]
        uint32_t mem34_pang_0 : 12; // [15:4]
        uint32_t __19_16 : 4;       // [19:16]
        uint32_t mem34_pang_1 : 12; // [31:20]
    } b;
} REG_RXCAPT_MEM34_PANG_T;

// mem56_ping
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;         // [3:0]
        uint32_t mem56_ping_0 : 12; // [15:4]
        uint32_t __19_16 : 4;       // [19:16]
        uint32_t mem56_ping_1 : 12; // [31:20]
    } b;
} REG_RXCAPT_MEM56_PING_T;

// mem56_pang
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;         // [3:0]
        uint32_t mem56_pang_0 : 12; // [15:4]
        uint32_t __19_16 : 4;       // [19:16]
        uint32_t mem56_pang_1 : 12; // [31:20]
    } b;
} REG_RXCAPT_MEM56_PANG_T;

// rxcapt_en
#define RXCAPT_RXCAPT_EN (1 << 0)

// capt_cfg
#define RXCAPT_CAPT_RX (1 << 0)
#define RXCAPT_CAPT_ODTOA (1 << 1)
#define RXCAPT_CAPT_IDDET_OFFLINE (1 << 2)
#define RXCAPT_CAPT_TX (1 << 3)
#define RXCAPT_CAPT_DUMP (1 << 4)

// fill_cfg1
#define RXCAPT_FILL_DIV(n) (((n)&0x7) << 0)
#define RXCAPT_FILL_DL_OFFLINE (1 << 3)
#define RXCAPT_FILL_LEN(n) (((n)&0xfffffff) << 4)

// fill_cfg2
#define RXCAPT_FILL_DIV(n) (((n)&0x7) << 0)
#define RXCAPT_FILL_IDDET_OFFLINE (1 << 3)
#define RXCAPT_FILL_LEN(n) (((n)&0xfffffff) << 4)

// dma_req_en
#define RXCAPT_DMA_REQ0_EN (1 << 0)
#define RXCAPT_DMA_REQ1_EN (1 << 1)
#define RXCAPT_DMA_REQ2_EN (1 << 2)
#define RXCAPT_DMA_REQ3_EN (1 << 3)
#define RXCAPT_DMA_REQ4_EN (1 << 4)
#define RXCAPT_DMA_REQ5_EN (1 << 5)
#define RXCAPT_DMA_REQ6_EN (1 << 6)
#define RXCAPT_DMA_REQ7_EN (1 << 7)

// irq_inten
#define RXCAPT_MEM12_PING_IRQ (1 << 0)
#define RXCAPT_MEM12_PANG_IRQ (1 << 1)
#define RXCAPT_MEM12_FINISH_IRQ (1 << 2)
#define RXCAPT_MEM34_PING_IRQ (1 << 4)
#define RXCAPT_MEM34_PANG_IRQ (1 << 5)
#define RXCAPT_MEM34_FINISH_IRQ (1 << 6)
#define RXCAPT_MEM56_PING_IRQ (1 << 8)
#define RXCAPT_MEM56_PANG_IRQ (1 << 9)
#define RXCAPT_MEM56_FINISH_IRQ (1 << 10)
#define RXCAPT_CAPT_ERR12 (1 << 12)
#define RXCAPT_CAPT_ERR34 (1 << 13)

// irq_inten_set
#define RXCAPT_MEM12_PING_IRQ (1 << 0)
#define RXCAPT_MEM12_PANG_IRQ (1 << 1)
#define RXCAPT_MEM12_FINISH_IRQ (1 << 2)
#define RXCAPT_MEM34_PING_IRQ (1 << 4)
#define RXCAPT_MEM34_PANG_IRQ (1 << 5)
#define RXCAPT_MEM34_FINISH_IRQ (1 << 6)
#define RXCAPT_MEM56_PING_IRQ (1 << 8)
#define RXCAPT_MEM56_PANG_IRQ (1 << 9)
#define RXCAPT_MEM56_FINISH_IRQ (1 << 10)
#define RXCAPT_CAPT_ERR12 (1 << 12)
#define RXCAPT_CAPT_ERR34 (1 << 13)

// irq_inten_clr
#define RXCAPT_MEM12_PING_IRQ (1 << 0)
#define RXCAPT_MEM12_PANG_IRQ (1 << 1)
#define RXCAPT_MEM12_FINISH_IRQ (1 << 2)
#define RXCAPT_MEM34_PING_IRQ (1 << 4)
#define RXCAPT_MEM34_PANG_IRQ (1 << 5)
#define RXCAPT_MEM34_FINISH_IRQ (1 << 6)
#define RXCAPT_MEM56_PING_IRQ (1 << 8)
#define RXCAPT_MEM56_PANG_IRQ (1 << 9)
#define RXCAPT_MEM56_FINISH_IRQ (1 << 10)
#define RXCAPT_CAPT_ERR12 (1 << 12)
#define RXCAPT_CAPT_ERR34 (1 << 13)

// irq_state
#define RXCAPT_MEM12_PING_IRQ (1 << 0)
#define RXCAPT_MEM12_PANG_IRQ (1 << 1)
#define RXCAPT_MEM12_FINISH_IRQ (1 << 2)
#define RXCAPT_MEM34_PING_IRQ (1 << 4)
#define RXCAPT_MEM34_PANG_IRQ (1 << 5)
#define RXCAPT_MEM34_FINISH_IRQ (1 << 6)
#define RXCAPT_MEM56_PING_IRQ (1 << 8)
#define RXCAPT_MEM56_PANG_IRQ (1 << 9)
#define RXCAPT_MEM56_FINISH_IRQ (1 << 10)
#define RXCAPT_CAPT_ERR12_IRQ (1 << 12)
#define RXCAPT_CAPT_ERR34_IRQ (1 << 13)

// capt_end_addr12
#define RXCAPT_END_ADDR12(n) (((n)&0x7ff) << 0)

// capt_end_addr34
#define RXCAPT_END_ADDR34(n) (((n)&0x1ff) << 0)

// fill_end_addr12
#define RXCAPT_END_ADDR12(n) (((n)&0x7ff) << 0)

// fill_end_addr56
#define RXCAPT_END_ADDR56(n) (((n)&0x3ff) << 0)

// state_mem12
#define RXCAPT_STATE_MEM12_PING_ADDR(n) (((n)&0x7ff) << 0)
#define RXCAPT_PING_STA(n) (((n)&0x7) << 12)
#define RXCAPT_STATE_MEM12_PANG_ADDR(n) (((n)&0x7ff) << 16)
#define RXCAPT_PANG_STA(n) (((n)&0x7) << 28)

// state_mem34
#define RXCAPT_STATE_MEM34_PING_ADDR(n) (((n)&0x1ff) << 0)
#define RXCAPT_PING_STA(n) (((n)&0x7) << 12)
#define RXCAPT_STATE_MEM34_PANG_ADDR(n) (((n)&0x1ff) << 16)
#define RXCAPT_PANG_STA(n) (((n)&0x7) << 28)

// state_mem56
#define RXCAPT_STATE_MEM56_PING_ADDR(n) (((n)&0x3ff) << 0)
#define RXCAPT_PING_STA(n) (((n)&0x7) << 12)
#define RXCAPT_STATE_MEM56_PANG_ADDR(n) (((n)&0x3ff) << 16)
#define RXCAPT_PANG_STA(n) (((n)&0x7) << 28)

// state_err12
#define RXCAPT_ERR_FN(n) (((n)&0xffffff) << 0)
#define RXCAPT_WHICH_MEM (1 << 24)

// state_err34
#define RXCAPT_ERR_FN(n) (((n)&0xffffff) << 0)
#define RXCAPT_WHICH_MEM (1 << 24)

// capt_sta
#define RXCAPT_RX_STA(n) (((n)&0x3) << 0)
#define RXCAPT_DUMP_STA(n) (((n)&0x3) << 4)
#define RXCAPT_TX_STA(n) (((n)&0x3) << 8)
#define RXCAPT_IDDET_STA(n) (((n)&0x3) << 12)
#define RXCAPT_OTDOA_STA(n) (((n)&0x3) << 16)

// fill1_sta1
#define RXCAPT_OUT_LEN(n) (((n)&0xfffffff) << 0)
#define RXCAPT_FILL_RUNNING_STA(n) (((n)&0x3) << 28)

// fill1_sta2
#define RXCAPT_IN_LEN(n) (((n)&0xfffffff) << 0)

// fill2_sta1
#define RXCAPT_OUT_LEN(n) (((n)&0xfffffff) << 0)
#define RXCAPT_FILL_RUNNING_STA(n) (((n)&0x3) << 28)

// fill2_sta2
#define RXCAPT_IN_LEN(n) (((n)&0xfffffff) << 0)

// dma_sta
#define RXCAPT_REQ_STA(n) (((n)&0xff) << 0)
#define RXCAPT_ACK_STA(n) (((n)&0xff) << 8)

// capt12_len
#define RXCAPT_CURRENT_LEN12(n) (((n)&0xffffff) << 0)

// capt34_len
#define RXCAPT_CURRENT_LEN34(n) (((n)&0xffffff) << 0)

// err_inten
#define RXCAPT_ERR_INTEN_SR(n) (((n)&0xf) << 0)

// err_inten_set
#define RXCAPT_ERR_INTEN_SET_SR(n) (((n)&0xf) << 0)

// err_inten_clr
#define RXCAPT_ERR_INTEN_CLR_SR(n) (((n)&0xf) << 0)

// err_int_sta
#define RXCAPT_ERR_INT_STA(n) (((n)&0xf) << 0)

// mem12_ping
#define RXCAPT_MEM12_PING_0(n) (((n)&0xfff) << 4)
#define RXCAPT_MEM12_PING_1(n) (((n)&0xfff) << 20)

// mem12_pang
#define RXCAPT_MEM12_PANG_0(n) (((n)&0xfff) << 4)
#define RXCAPT_MEM12_PANG_1(n) (((n)&0xfff) << 20)

// mem34_ping
#define RXCAPT_MEM34_PING_0(n) (((n)&0xfff) << 4)
#define RXCAPT_MEM34_PING_1(n) (((n)&0xfff) << 20)

// mem34_pang
#define RXCAPT_MEM34_PANG_0(n) (((n)&0xfff) << 4)
#define RXCAPT_MEM34_PANG_1(n) (((n)&0xfff) << 20)

// mem56_ping
#define RXCAPT_MEM56_PING_0(n) (((n)&0xfff) << 4)
#define RXCAPT_MEM56_PING_1(n) (((n)&0xfff) << 20)

// mem56_pang
#define RXCAPT_MEM56_PANG_0(n) (((n)&0xfff) << 4)
#define RXCAPT_MEM56_PANG_1(n) (((n)&0xfff) << 20)

#endif // _RXCAPT_H_