EC600G/tools/win32/setting/chips/8910/8910_hard.xml

<?xml version="1.0" ?>
<bigarchive>
  <archive relative="****phantomglobalvars****">
</archive>
  <archive relative="globals.xml" vhdlpkg="chip_cfg_pkg">
    <var name="NB_BITS_ADDR" value="32">
      <comment>AHB Address bus size</comment>
    </var>
    <var name="AP_NB_BITS_ADDR" value="32">
      <comment>AXI Address bus size of DMA_AP</comment>
    </var>
    <var name="AON_NB_BITS_PSEL" value="7">
      <comment>System AON Apb Bus Configuration</comment>
    </var>
    <var name="AON_NB_BITS_PADDR" value="12"/>
    <var name="AON_APB_STEP" value="exp2(AON_NB_BITS_PADDR)"/>
    <var name="AON_APB_ID_IFC_BASE" value="16"/>
    <enum name="Aon_Apb_Id">
      <comment>8910m sys aon apb module id</comment>
      <entry name="AON_APB_ID_SYS_CTRL"/>
      <entry name="AON_APB_ID_LVDS"/>
      <entry name="AON_APB_ID_GSM_LPS"/>
      <entry name="AON_APB_ID_I2C_M2"/>
      <entry name="AON_APB_ID_MAILBOX"/>
      <entry name="AON_APB_ID_TIMER_3"/>
      <entry name="AON_APB_ID_KEYPAD"/>
      <entry name="AON_APB_ID_GPIO_1"/>
      <entry name="AON_APB_ID_PWM"/>
      <entry name="AON_APB_ID_ANALOG_REG"/>
      <entry name="AON_APB_ID_AON_IFC"/>
      <entry name="AON_APB_ID_NB_LPS"/>
      <entry name="AON_APB_ID_IOMUX"/>
      <entry name="AON_APB_ID_SPINLOCK"/>
      <entry name="AON_APB_ID_EFUSE"/>
      <entry name="AON_APB_ID_NORMAL_LAST" value="AON_APB_ID_IFC_BASE-1">
        <comment>Last of AON Normal slave</comment>
      </entry>
      <entry name="AON_APB_ID_DEBUG_UART" value="AON_APB_ID_IFC_BASE"/>
      <entry name="AON_APB_ID_17_RESERVED"/>
      <entry name="AON_APB_ID_VAD"/>
      <bound name="AON_NB_PSEL">
        <comment>Num of System Aon Apb Slaves except Debug Host</comment>
      </bound>
      <entry name="AON_APB_ID_DEBUG_HOST" value="exp2(AON_NB_BITS_PSEL)-1">
        <comment>The debug host is placed at last PSEL127 in the IFC</comment>
      </entry>
    </enum>
    <var name="DEBUG_HOST_SLAVE_ID" value="AON_APB_ID_DEBUG_HOST">
      <comment>Debug host slave id used for ifc channel.</comment>
    </var>
    <var name="AP_NB_BITS_PSEL" value="7">
      <comment>System Apb Bus Configuration</comment>
    </var>
    <var name="AP_NB_BITS_PADDR" value="12"/>
    <var name="AP_APB_STEP" value="exp2(AP_NB_BITS_PADDR)"/>
    <var name="AP_APB_ID_IFC_BASE" value="16"/>
    <enum name="Ap_Apb_Id">
      <comment>8910m sys apb module id</comment>
      <entry name="AP_APB_ID_IRQH"/>
      <entry name="AP_APB_ID_LPDDR_PSRAM_CTRL"/>
      <entry name="AP_APB_ID_PAGESPY"/>
      <entry name="AP_APB_ID_DMC_CTRL"/>
      <entry name="AP_APB_ID_SYSIMEM"/>
      <entry name="AP_APB_ID_LZMA"/>
      <entry name="AP_APB_ID_GOUDA"/>
      <entry name="AP_APB_ID_LCDC"/>
      <entry name="AP_APB_ID_TIMER_1"/>
      <entry name="AP_APB_ID_TIMER_2"/>
      <entry name="AP_APB_ID_I2C_M1"/>
      <entry name="AP_APB_ID_I2C_M3"/>
      <entry name="AP_APB_ID_12_RESERVED"/>
      <entry name="AP_APB_ID_AUD_2AD"/>
      <entry name="AP_APB_ID_TIMER_4"/>
      <entry name="AP_APB_ID_AP_IFC"/>
      <entry name="AP_APB_ID_NORMAL_LAST" value="AP_APB_ID_IFC_BASE-1">
        <comment>Last of Sys APB Normal slave</comment>
      </entry>
      <entry name="AP_APB_ID_SDMMC1" value="AP_APB_ID_IFC_BASE"/>
      <entry name="AP_APB_ID_SDMMC2"/>
      <entry name="AP_APB_ID_SPI_1"/>
      <entry name="AP_APB_ID_SPI_2"/>
      <entry name="AP_APB_ID_SCI_1"/>
      <entry name="AP_APB_ID_SCI_2"/>
      <entry name="AP_APB_ID_ZSP_UART"/>
      <entry name="AP_APB_ID_UART_2"/>
      <entry name="AP_APB_ID_UART_3"/>
      <entry name="AP_APB_ID_CAMERA"/>
      <entry name="AP_APB1_ID_AIF"/>
      <entry name="AP_APB1_ID_AIF2"/>
      <bound name="AP_NB_PSEL">
        <comment>Num of System Apb Slaves</comment>
      </bound>
    </enum>
    <var name="SYS_NB_BITS_HADDR" value="18">
      <comment>System Ahb Bus Configuration</comment>
    </var>
    <var name="SYS_AHB_STEP" value="exp2(SYS_NB_BITS_HADDR)"/>
    <enum name="Sys_Ahb_Id">
      <comment>8910m sys ahb module id</comment>
      <entry name="SYS_AHB_ID_F8" value="1"/>
      <entry name="SYS_AHB_ID_USBC"/>
      <entry name="SYS_AHB_ID_GOUDA"/>
      <entry name="SYS_AHB_ID_AXIDMA"/>
      <entry name="SYS_AHB_ID_GEA3"/>
      <entry name="SYS_AHB_ID_AES"/>
      <bound name="NB_SYS_AHB_SLAVES">
        <comment>Num of System Ahb Slaves</comment>
      </bound>
      <entry name="SYS_AHB_ID_USB11"/>
    </enum>
    <var name="AIF_NB_BITS_PSEL" value="5">
      <comment>Aif Apb Bus Configuration</comment>
    </var>
    <var name="AIF_NB_BITS_PADDR" value="12"/>
    <var name="AIF_APB_STEP" value="exp2(AIF_NB_BITS_PADDR)"/>
    <enum name="Aif_Apb_Id">
      <comment>8910m aif apb module id</comment>
      <entry name="AIF_APB_ID_AIF" value="7"/>
      <bound name="AIF_NB_PSEL">
        <comment>Num of Aif Apb Slaves</comment>
      </bound>
    </enum>
    <var name="AIF_SLAVE_ID" value="AIF_APB_ID_AIF">
      <comment>Aif slave id used for ifc channel.</comment>
    </var>
    <var name="AP_APB1_NB_BITS_PADDR" value="AP_NB_BITS_PADDR"/>
    <var name="AP_APB1_NB_BITS_PSEL" value="AP_NB_BITS_PSEL"/>
    <var name="AUDIO_IFC_APB_STEP" value="exp2(8)"/>
    <var name="AP_NB_DMA_REQ_WIDTH" value="5"/>
    <enum name="Ap_Ifc_Request_IDs">
      <entry name="AP_APB_DMA_ID_SDMMC1_TX" value="(AP_APB_ID_SDMMC1-AP_APB_ID_IFC_BASE)*2+0"/>
      <entry name="AP_APB_DMA_ID_SDMMC1_RX" value="(AP_APB_ID_SDMMC1-AP_APB_ID_IFC_BASE)*2+1"/>
      <entry name="AP_APB_DMA_ID_SDMMC2_TX" value="(AP_APB_ID_SDMMC2-AP_APB_ID_IFC_BASE)*2+0"/>
      <entry name="AP_APB_DMA_ID_SDMMC2_RX" value="(AP_APB_ID_SDMMC2-AP_APB_ID_IFC_BASE)*2+1"/>
      <entry name="AP_APB_DMA_ID_SPI_1_TX" value="(AP_APB_ID_SPI_1-AP_APB_ID_IFC_BASE)*2+0"/>
      <entry name="AP_APB_DMA_ID_SPI_1_RX" value="(AP_APB_ID_SPI_1-AP_APB_ID_IFC_BASE)*2+1"/>
      <entry name="AP_APB_DMA_ID_SPI_2_TX" value="(AP_APB_ID_SPI_2-AP_APB_ID_IFC_BASE)*2+0"/>
      <entry name="AP_APB_DMA_ID_SPI_2_RX" value="(AP_APB_ID_SPI_2-AP_APB_ID_IFC_BASE)*2+1"/>
      <entry name="AP_APB_DMA_ID_SCI_1_TX" value="(AP_APB_ID_SCI_1-AP_APB_ID_IFC_BASE)*2+0"/>
      <entry name="AP_APB_DMA_ID_SCI_1_RX" value="(AP_APB_ID_SCI_1-AP_APB_ID_IFC_BASE)*2+1"/>
      <entry name="AP_APB_DMA_ID_SCI_2_TX" value="(AP_APB_ID_SCI_2-AP_APB_ID_IFC_BASE)*2+0"/>
      <entry name="AP_APB_DMA_ID_SCI_2_RX" value="(AP_APB_ID_SCI_2-AP_APB_ID_IFC_BASE)*2+1"/>
      <entry name="AP_APB_DMA_ID_FREE_TX" value="(AP_APB_ID_CAMERA-AP_APB_ID_IFC_BASE)*2+0"/>
      <entry name="AP_APB_DMA_ID_CAMERA_RX" value="(AP_APB_ID_CAMERA-AP_APB_ID_IFC_BASE)*2+1"/>
      <bound name="AP_NB_DMA_REQ">
        <comment>Num of sys ifc dma req</comment>
      </bound>
    </enum>
    <enum name="Sys_Axi_DMA_Request_IDs">
      <entry name="SYS_AXI_DMA_ID_UART_1_RX"/>
      <entry name="SYS_AXI_DMA_ID_UART_1_TX"/>
      <entry name="SYS_AXI_DMA_ID_UART_2_RX"/>
      <entry name="SYS_AXI_DMA_ID_UART_2_TX"/>
      <entry name="SYS_AXI_DMA_ID_UART_3_RX"/>
      <entry name="SYS_AXI_DMA_ID_UART_3_TX"/>
      <entry name="SYS_AXI_DMA_ID_ZBUSMON"/>
      <entry name="SYS_AXI_DMA_ID_ZSP_UART"/>
    </enum>
    <var name="AON_NB_DMA_REQ_WIDTH" value="5"/>
    <enum name="Aon_Ifc_Request_IDs">
      <entry name="AON_APB_DMA_ID_TX_DEBUG_UART" value="(AON_APB_ID_DEBUG_UART-AON_APB_ID_IFC_BASE)*2+0"/>
      <entry name="AON_APB_DMA_ID_RX_DEBUG_UART" value="(AON_APB_ID_DEBUG_UART-AON_APB_ID_IFC_BASE)*2+1"/>
      <entry name="AON_APB_DMA_ID_RX_VAD" value="(AON_APB_ID_VAD-AON_APB_ID_IFC_BASE)*2+1"/>
      <bound name="AON_NB_DMA_REQ">
        <comment>Num of aon ifc dma req</comment>
      </bound>
    </enum>
    <enum name="Sys_Irq_Id">
      <entry name="SYS_IRQ_ID_PAGE_SPY">
        <comment>System IRQ IDs</comment>
      </entry>
      <entry name="SYS_IRQ_ID_IMEM"/>
      <entry name="SYS_IRQ_ID_TIMER_1"/>
      <entry name="SYS_IRQ_ID_TIMER_1_OS"/>
      <entry name="SYS_IRQ_ID_TIMER_2"/>
      <entry name="SYS_IRQ_ID_TIMER_2_OS"/>
      <entry name="SYS_IRQ_ID_TIMER_4"/>
      <entry name="SYS_IRQ_ID_TIMER_4_OS"/>
      <entry name="SYS_IRQ_ID_I2C_M1"/>
      <entry name="SYS_IRQ_ID_AIF_APB_0"/>
      <entry name="SYS_IRQ_ID_AIF_APB_1"/>
      <entry name="SYS_IRQ_ID_AIF_APB_2"/>
      <entry name="SYS_IRQ_ID_AIF_APB_3"/>
      <entry name="SYS_IRQ_ID_AUD_2AD"/>
      <entry name="SYS_IRQ_ID_SDMMC1"/>
      <entry name="SYS_IRQ_ID_SDMMC2"/>
      <entry name="SYS_IRQ_ID_SPI_1"/>
      <entry name="SYS_IRQ_ID_SPI_2"/>
      <entry name="SYS_IRQ_ID_ZSP_UART"/>
      <entry name="SYS_IRQ_ID_UART_2"/>
      <entry name="SYS_IRQ_ID_UART_3"/>
      <entry name="SYS_IRQ_ID_CAMERA"/>
      <entry name="SYS_IRQ_ID_LZMA"/>
      <entry name="SYS_IRQ_ID_GOUDA"/>
      <entry name="SYS_IRQ_ID_F8"/>
      <entry name="SYS_IRQ_ID_USBC"/>
      <entry name="SYS_IRQ_ID_USB11"/>
      <entry name="SYS_IRQ_ID_AXIDMA"/>
      <entry name="SYS_IRQ_ID_AXIDMA_1_SECURITY"/>
      <entry name="SYS_IRQ_ID_AXIDMA_1_UNSECURITY"/>
      <entry name="SYS_IRQ_ID_PMU_APCPU"/>
      <entry name="SYS_IRQ_ID_31_RESERVED"/>
      <entry name="SYS_IRQ_ID_LCD"/>
      <entry name="SYS_IRQ_ID_SPIFLASH"/>
      <entry name="SYS_IRQ_ID_SPIFLASH1"/>
      <entry name="SYS_IRQ_ID_GPRS_0"/>
      <entry name="SYS_IRQ_ID_GPRS_1"/>
      <entry name="SYS_IRQ_ID_DMC"/>
      <entry name="SYS_IRQ_ID_AES"/>
      <entry name="SYS_IRQ_ID_CTI_APCPU"/>
      <entry name="SYS_IRQ_ID_AP_TZ_SLV"/>
      <entry name="SYS_IRQ_ID_AP_TZ_MEM"/>
      <entry name="SYS_IRQ_ID_I2C_M3"/>
      <entry name="SYS_IRQ_ID_GSM_LPS"/>
      <entry name="SYS_IRQ_ID_I2C_M2"/>
      <entry name="SYS_IRQ_ID_TIMER_3"/>
      <entry name="SYS_IRQ_ID_TIMER_3_OS"/>
      <entry name="SYS_IRQ_ID_KEYPAD"/>
      <entry name="SYS_IRQ_ID_GPIO_1"/>
      <entry name="SYS_IRQ_ID_DEBUG_UART"/>
      <entry name="SYS_IRQ_ID_SCI_1"/>
      <entry name="SYS_IRQ_ID_SCI_2"/>
      <entry name="SYS_IRQ_ID_ADI"/>
      <entry name="SYS_IRQ_ID_UART_1"/>
      <entry name="SYS_IRQ_ID_VAD"/>
      <entry name="SYS_IRQ_ID_VAD_PULSE"/>
      <entry name="SYS_IRQ_ID_AON_TZ"/>
      <entry name="SYS_IRQ_ID_NB_LPS"/>
      <entry name="SYS_IRQ_ID_CP_IDLE_H"/>
      <entry name="SYS_IRQ_ID_CP_IDLE_2_H"/>
      <entry name="SYS_IRQ_ID_MAILBOX_ARM_AP"/>
      <entry name="SYS_IRQ_ID_LTEM1_FRAME"/>
      <entry name="SYS_IRQ_ID_LTEM2_FRAME"/>
      <entry name="SYS_IRQ_ID_RFSPI_CONFLICT"/>
      <entry name="SYS_IRQ_ID_CP_WD_RESET"/>
      <entry name="SYS_IRQ_ID_GSM_FRAME"/>
      <entry name="SYS_IRQ_ID_PWRCTRL_TIMEOUT"/>
      <entry name="SYS_IRQ_ID_NB_FRAME"/>
      <entry name="SYS_IRQ_ID_ZSP_AXIDMA"/>
      <entry name="SYS_IRQ_ID_ZSP_BUSMON"/>
      <entry name="SYS_IRQ_ID_ZSP_WD"/>
      <entry name="SYS_IRQ_ID_71_RESERVED"/>
      <entry name="SYS_IRQ_ID_GGE_FINT"/>
      <entry name="SYS_IRQ_ID_GGE_TCU_0"/>
      <entry name="SYS_IRQ_ID_GGE_TCU_1"/>
      <entry name="SYS_IRQ_ID_NB_FINT"/>
      <entry name="SYS_IRQ_ID_NB_TCU_0"/>
      <entry name="SYS_IRQ_ID_NB_TCU_1"/>
      <entry name="SYS_IRQ_ID_NB_TCU_SYNC"/>
      <entry name="SYS_IRQ_ID_GGE_COMP_INT"/>
      <entry name="SYS_IRQ_ID_GGE_NB_RX_DSP"/>
      <entry name="SYS_IRQ_ID_GGE_NB_RX_MCU"/>
      <entry name="SYS_IRQ_ID_GGE_NB_TX_DSP"/>
      <entry name="SYS_IRQ_ID_GGE_NB_ACC_DSP"/>
      <entry name="SYS_IRQ_ID_84_RESERVED"/>
      <entry name="SYS_IRQ_ID_WCN_WLAN"/>
      <entry name="SYS_IRQ_ID_WCN_SOFT"/>
      <entry name="SYS_IRQ_ID_WCN_WDT_RST"/>
      <entry name="SYS_IRQ_ID_WCN_AWAKE"/>
      <entry name="SYS_IRQ_ID_RF_WDG_RST"/>
      <entry name="SYS_IRQ_ID_LVDS"/>
      <bound name="NB_SYS_IRQ">
        <comment>Num of System IRQS</comment>
      </bound>
    </enum>
    <enum name="CP_Irq_Id">
      <entry name="CP_IRQ_ID_PAGE_SPY">
        <comment>IRQ IDs For CP CPU</comment>
      </entry>
      <entry name="CP_IRQ_ID_TIMER_1"/>
      <entry name="CP_IRQ_ID_TIMER_1_OS"/>
      <entry name="CP_IRQ_ID_UART_2"/>
      <entry name="CP_IRQ_ID_UART_3"/>
      <entry name="CP_IRQ_ID_F8"/>
      <entry name="CP_IRQ_ID_AXIDMA"/>
      <entry name="CP_IRQ_ID_ZSP_UART"/>
      <entry name="CP_IRQ_ID_CTI_CPCPU"/>
      <entry name="CP_IRQ_ID_PMU_CPCPU"/>
      <entry name="CP_IRQ_ID_UART_1"/>
      <entry name="CP_IRQ_ID_LPS_GSM"/>
      <entry name="CP_IRQ_ID_LPS_NB"/>
      <entry name="CP_IRQ_ID_SCI_1"/>
      <entry name="CP_IRQ_ID_SCI_2"/>
      <entry name="CP_IRQ_ID_VAD"/>
      <entry name="CP_IRQ_ID_VAD_PULSE"/>
      <entry name="CP_IRQ_ID_CP_IDLE_H"/>
      <entry name="CP_IRQ_ID_CP_IDLE_2_H"/>
      <entry name="CP_IRQ_ID_MAILBOX_ARM_CP"/>
      <entry name="CP_IRQ_ID_LTEM1_FRAME"/>
      <entry name="CP_IRQ_ID_LTEM2_FRAME"/>
      <entry name="CP_IRQ_ID_RFSPI_CONFLICT"/>
      <entry name="CP_IRQ_ID_GSM_FRAME"/>
      <entry name="CP_IRQ_ID_NB_FRAME"/>
      <entry name="CP_IRQ_ID_PWRCTRL_TIMEOUT"/>
      <entry name="CP_IRQ_ID_LTE_COEFF"/>
      <entry name="CP_IRQ_ID_LTE_CSIRS"/>
      <entry name="CP_IRQ_ID_LTE_DLFFT"/>
      <entry name="CP_IRQ_ID_LTE_DLFFT_ERR"/>
      <entry name="CP_IRQ_ID_LTE_IDDET"/>
      <entry name="CP_IRQ_ID_LTE_LDTC1_CTRL"/>
      <entry name="CP_IRQ_ID_LTE_LDTC1_DATA"/>
      <entry name="CP_IRQ_ID_LTE_LDTC1_VIT"/>
      <entry name="CP_IRQ_ID_LTE_LDTC"/>
      <entry name="CP_IRQ_ID_LTE_MEASPWR"/>
      <entry name="CP_IRQ_ID_LTE_PUSCH"/>
      <entry name="CP_IRQ_ID_LTE_RX_TRACE"/>
      <entry name="CP_IRQ_ID_LTE_TXRX"/>
      <entry name="CP_IRQ_ID_LTE_TX_TRACE"/>
      <entry name="CP_IRQ_ID_LTE_ULDFT"/>
      <entry name="CP_IRQ_ID_LTE_ULDFT_ERR"/>
      <entry name="CP_IRQ_ID_LTE_OTDOA"/>
      <entry name="CP_IRQ_ID_LTE_PBMEAS"/>
      <entry name="CP_IRQ_ID_LTE_RXCAPT"/>
      <entry name="CP_IRQ_ID_LTE_ULPCDCI"/>
      <entry name="CP_IRQ_ID_LTE_CORR"/>
      <entry name="CP_IRQ_ID_ZSP_AXIDMA"/>
      <entry name="CP_IRQ_ID_ZSP_BUSMON"/>
      <entry name="CP_IRQ_ID_ZSP_WD"/>
      <entry name="CP_IRQ_ID_ZSP_AUD_DFT"/>
      <entry name="CP_IRQ_ID_GGE_FINT"/>
      <entry name="CP_IRQ_ID_GGE_TCU_0"/>
      <entry name="CP_IRQ_ID_GGE_TCU_1"/>
      <entry name="CP_IRQ_ID_NB_FINT"/>
      <entry name="CP_IRQ_ID_NB_TCU_0"/>
      <entry name="CP_IRQ_ID_NB_TCU_1"/>
      <entry name="CP_IRQ_ID_GGE_NB_RX_DSP"/>
      <entry name="CP_IRQ_ID_GGE_NB_RX_MCU"/>
      <entry name="CP_IRQ_ID_GGE_NB_TX_DSP"/>
      <entry name="CP_IRQ_ID_GGE_NB_ACC_DSP"/>
      <entry name="CP_IRQ_ID_NB_TCU_SYNC"/>
      <entry name="CP_IRQ_ID_TIMER_3"/>
      <entry name="CP_IRQ_ID_OTHERS"/>
      <bound name="NB_CP_IRQ">
        <comment>Num of IRQS For CP CPU</comment>
      </bound>
    </enum>
    <enum name="CP_Other_Irq_Id">
      <entry name="CP_IRQ_ID_IMEM">
        <comment>Other IRQ IDs For CP CPU</comment>
      </entry>
      <entry name="CP_IRQ_ID_TIMER_2"/>
      <entry name="CP_IRQ_ID_TIMER_2_OS"/>
      <entry name="CP_IRQ_ID_TIMER_4"/>
      <entry name="CP_IRQ_ID_TIMER_4_OS"/>
      <entry name="CP_IRQ_ID_I2C_M1"/>
      <entry name="CP_IRQ_ID_AIF_APB_0"/>
      <entry name="CP_IRQ_ID_AIF_APB_1"/>
      <entry name="CP_IRQ_ID_AIF_APB_2"/>
      <entry name="CP_IRQ_ID_AIF_APB_3"/>
      <entry name="CP_IRQ_ID_AUD_2AD"/>
      <entry name="CP_IRQ_ID_SDMMC1"/>
      <entry name="CP_IRQ_ID_SDMMC2"/>
      <entry name="CP_IRQ_ID_SPI_1"/>
      <entry name="CP_IRQ_ID_SPI_2"/>
      <entry name="CP_IRQ_ID_CAMERA"/>
      <entry name="CP_IRQ_ID_LZMA"/>
      <entry name="CP_IRQ_ID_GOUDA"/>
      <entry name="CP_IRQ_ID_USBC"/>
      <entry name="CP_IRQ_ID_USB11"/>
      <entry name="CP_IRQ_ID_AXIDMA_1_SECURITY"/>
      <entry name="CP_IRQ_ID_AXIDMA_1_UNSECURITY"/>
      <entry name="CP_IRQ_ID_LCD"/>
      <entry name="CP_IRQ_ID_SPIFLASH"/>
      <entry name="CP_IRQ_ID_SPIFLASH1"/>
      <entry name="CP_IRQ_ID_GPRS_0"/>
      <entry name="CP_IRQ_ID_GPRS_1"/>
      <entry name="CP_IRQ_ID_DMC"/>
      <entry name="CP_IRQ_ID_AES"/>
      <entry name="CP_IRQ_ID_AP_TZ_SLV"/>
      <entry name="CP_IRQ_ID_AP_TZ_MEM"/>
      <entry name="CP_IRQ_ID_I2C_M3"/>
      <entry name="CP_IRQ_ID_GGE_COMP_INT"/>
      <entry name="CP_IRQ_ID_I2C_M2"/>
      <entry name="CP_IRQ_ID_TIMER_3_OS"/>
      <entry name="CP_IRQ_ID_KEYPAD"/>
      <entry name="CP_IRQ_ID_GPIO_1"/>
      <entry name="CP_IRQ_ID_DEBUG_UART"/>
      <entry name="CP_IRQ_ID_ADI"/>
      <entry name="CP_IRQ_ID_AON_TZ"/>
      <entry name="CP_IRQ_ID_CP_WD_RESET"/>
      <bound name="NB_CP_OTHER_IRQ">
        <comment>Num of Other IRQS For CP CPU</comment>
      </bound>
    </enum>
    <var name="RF_SPI_SLAVE_ID" value="22">
      <comment>Below is for compatibility to inherited design and for rtl compiling pass</comment>
    </var>
    <var name="SYS_NB_MASTERS" value="9"/>
    <var name="BB_NB_MASTERS" value="6"/>
    <var name="BB_NB_SLAVES" value="NB_SYS_AHB_SLAVES"/>
    <var name="BB_NB_BITS_PSEL" value="AIF_NB_BITS_PSEL"/>
    <var name="BB_NB_BITS_PADDR" value="AIF_NB_BITS_PADDR"/>
    <var name="BB_NB_PSEL" value="AIF_NB_PSEL"/>
    <var name="RF_SLAVE_ID" value="6"/>
    <var name="BB_SYS_BITS_PADDR" value="12"/>
    <var name="BB_SYS_NB_BITS_PSEL" value="4"/>
    <var name="BB_SYS_STEP" value="exp2(BB_SYS_BITS_PADDR)"/>
    <enum name="BB_SYSCTRL_ID">
      <entry name="BB_SYSCTRL_ID_SYSREG"/>
      <entry name="BB_SYSCTRL_ID_CLKRST"/>
      <entry name="BB_SYSCTRL_ID_2_RESERVED"/>
      <entry name="BB_SYSCTRL_ID_MONITOR"/>
      <entry name="BB_SYSCTRL_ID_CP_WD_TIMER"/>
      <entry name="BB_SYSCTRL_ID_IDLE" value="exp2(BB_SYS_NB_BITS_PSEL)"/>
      <entry name="BB_SYSCTRL_ID_UART1" value="exp2(BB_SYS_NB_BITS_PSEL)/2+BB_SYSCTRL_ID_IDLE"/>
      <entry name="BB_SYSCTRL_ID_PWRCTRL" value="exp2(BB_SYS_NB_BITS_PSEL)+BB_SYSCTRL_ID_IDLE"/>
    </enum>
    <var name="CP_ZSP_SYS_PADDR" value="12"/>
    <var name="CP_ZSP_NB_BITS_PSEL" value="12"/>
    <var name="CP_ZSP_SYS_STEP" value="exp2(CP_ZSP_SYS_PADDR)"/>
    <enum name="CP_ZSP_SYS_ID">
      <entry name="CP_ZSP_SYS_ID_ZSP_AXIDMA"/>
      <entry name="CP_ZSP_SYS_ID_ZSP_AUD_DFT" value="exp2(CP_ZSP_NB_BITS_PSEL)"/>
      <entry name="CP_ZSP_SYS_ID_ZSP_WD"/>
      <entry name="CP_ZSP_SYS_ID_ZSP_IRQH"/>
      <entry name="CP_ZSP_SYS_ID_BUSMON"/>
    </enum>
    <var name="CP_LTE_SYS_PADDR" value="20"/>
    <var name="CP_LTE_NB_BITS_PSEL" value="4"/>
    <var name="CP_LTE_SYS_STEP" value="exp2(CP_LTE_SYS_PADDR)"/>
    <enum name="CP_LTE_SYS_ID">
      <entry name="CP_LTE_SYS_ID_TXRX"/>
      <entry name="CP_LTE_SYS_ID_RFAD"/>
      <entry name="CP_LTE_SYS_ID_COEFF"/>
      <entry name="CP_LTE_SYS_ID_LDTC"/>
      <entry name="CP_LTE_SYS_ID_OTDOA"/>
      <entry name="CP_LTE_SYS_ID_MEASPWR" value="5"/>
      <entry name="CP_LTE_SYS_ID_IDDET"/>
      <entry name="CP_LTE_SYS_ID_ULDFT"/>
      <entry name="CP_LTE_SYS_ID_PUSCH"/>
      <entry name="CP_LTE_SYS_ID_ULPCDCI"/>
      <entry name="CP_LTE_SYS_ID_DLFFT"/>
      <entry name="CP_LTE_SYS_ID_CSIRS"/>
      <entry name="CP_LTE_SYS_ID_LDTC1" value="exp2(CP_LTE_NB_BITS_PSEL)"/>
      <entry name="CP_LTE_SYS_ID_RXCAPT" value="2*exp2(CP_LTE_NB_BITS_PSEL)"/>
    </enum>
    <var name="GGE_SYS_NB_BITS_PSEL" value="5">
      <comment>GGE System Apb Bus Configuration</comment>
    </var>
    <var name="GGE_SYS_NB_BITS_PADDR" value="12"/>
    <var name="GGE_SYS_APB_STEP" value="exp2(GGE_SYS_NB_BITS_PADDR)"/>
    <enum name="Gge_Sys_Apb_Id">
      <comment>8910m gge sys apb module id</comment>
      <entry name="GGE_SYS_APB_ID_0_RSV"/>
      <entry name="GGE_SYS_APB_ID_TCU_GSM"/>
      <entry name="GGE_SYS_APB_ID_TCU_NB"/>
      <entry name="GGE_SYS_APB_ID_BB_DMA"/>
      <entry name="GGE_SYS_APB_ID_4_RSV"/>
      <entry name="GGE_SYS_APB_ID_WDT"/>
      <entry name="GGE_SYS_APB_ID_GGE_IFC"/>
      <entry name="GGE_SYS_APB_ID_7_RSV"/>
      <entry name="GGE_SYS_APB_ID_8_RSV"/>
      <entry name="GGE_SYS_APB_ID_9_RSV"/>
      <entry name="GGE_SYS_APB_ID_10_RSV"/>
      <entry name="GGE_SYS_APB_ID_11_RSV"/>
      <entry name="GGE_SYS_APB_ID_12_RSV"/>
      <entry name="GGE_SYS_APB_ID_13_RSV"/>
      <entry name="GGE_SYS_APB_ID_RFSPI_GSM"/>
      <entry name="GGE_SYS_APB_ID_RFSPI_NB"/>
      <bound name="GGE_SYS_APB_NB_PSEL">
        <comment>Num of GGE System Apb Slaves</comment>
      </bound>
    </enum>
    <var name="GGE_SYS_NB_DMA_REQ_WIDTH" value="5"/>
    <enum name="Gge_Ifc_Request_IDs">
      <bound name="GGE_SYS_NB_DMA_REQ">
        <comment>Num of gge ifc dma req</comment>
      </bound>
    </enum>
    <var name="GGE_BB_NB_BITS_PSEL" value="5">
      <comment>GGE System Apb Bus Configuration</comment>
    </var>
    <var name="GGE_BB_NB_BITS_PADDR" value="12"/>
    <var name="GGE_BB_APB_STEP" value="exp2(GGE_BB_NB_BITS_PADDR)"/>
    <enum name="Gge_Bb_Apb_Id">
      <comment>8910m gge bb apb module id</comment>
      <entry name="GGE_BB_APB_ID_XCOR"/>
      <entry name="GGE_BB_APB_ID_CORDIC"/>
      <entry name="GGE_BB_APB_ID_ITLV"/>
      <entry name="GGE_BB_APB_ID_VITAC"/>
      <entry name="GGE_BB_APB_ID_EXCOR"/>
      <entry name="GGE_BB_APB_ID_CHOLK"/>
      <entry name="GGE_BB_APB_ID_CIPHER"/>
      <entry name="GGE_BB_APB_ID_EVITAC"/>
      <entry name="GGE_BB_APB_ID_CP2"/>
      <entry name="GGE_BB_APB_ID_BCPU_DBG"/>
      <entry name="GGE_BB_APB_ID_BCPU_CORE"/>
      <entry name="GGE_BB_APB_ID_ROM"/>
      <entry name="GGE_BB_APB_ID_RF_IF"/>
      <entry name="GGE_BB_APB_ID_IRQ"/>
      <entry name="GGE_BB_APB_ID_SYSCTRL"/>
      <entry name="GGE_BB_APB_ID_A53"/>
      <entry name="GGE_BB_APB_ID_NB_CTRL"/>
      <entry name="GGE_BB_APB_ID_NB_COMMON"/>
      <entry name="GGE_BB_APB_ID_NB_INTC"/>
      <entry name="GGE_BB_APB_ID_NB_CELL_SEARCH"/>
      <entry name="GGE_BB_APB_ID_NB_FFT_RSRP"/>
      <entry name="GGE_BB_APB_ID_NB_VITERBI"/>
      <entry name="GGE_BB_APB_ID_NB_MEAS"/>
      <entry name="GGE_BB_APB_ID_NB_DS_BSEL"/>
      <entry name="GGE_BB_APB_ID_NB_TX_PUSCH_ENC"/>
      <entry name="GGE_BB_APB_ID_NB_TX_CHSC"/>
      <entry name="GGE_BB_APB_ID_NB_TX_FRONTEND"/>
      <bound name="GGE_BB_APB_NB_PSEL">
        <comment>Num of GGE Baseband Apb Slaves</comment>
      </bound>
    </enum>
    <enum name="Gge_Bb_Irq_Id">
      <entry name="GGE_BB_IRQ_ID_TCU0_GSM">
        <comment>GGE IRQ IDs</comment>
      </entry>
      <entry name="GGE_BB_IRQ_ID_TCU1_GSM"/>
      <entry name="GGE_BB_IRQ_ID_FRAME_GSM"/>
      <entry name="GGE_BB_IRQ_ID_TCU0_NB"/>
      <entry name="GGE_BB_IRQ_ID_TCU1_NB"/>
      <entry name="GGE_BB_IRQ_ID_FRAME_NB"/>
      <entry name="GGE_BB_IRQ_ID_RFSPI_CONFLICT"/>
      <entry name="GGE_BB_IRQ_ID_A53"/>
      <bound name="NB_GGE_BB_IRQ_PULSE">
        <comment>Number of GGE Pulse IRQ</comment>
      </bound>
      <entry name="GGE_BB_IRQ_ID_RFIF_DBG_2G"/>
      <entry name="GGE_BB_IRQ_ID_RFIF_DBG_NB"/>
      <entry name="GGE_BB_IRQ_ID_RFIF_RX"/>
      <entry name="GGE_BB_IRQ_ID_RFIF_TX"/>
      <entry name="GGE_BB_IRQ_ID_EVITAC"/>
      <entry name="GGE_BB_IRQ_ID_EXCOR"/>
      <entry name="GGE_BB_IRQ_ID_ITLV"/>
      <entry name="GGE_BB_IRQ_ID_VITAC"/>
      <entry name="GGE_BB_IRQ_ID_XCOR"/>
      <entry name="GGE_BB_IRQ_ID_CHOLK"/>
      <entry name="GGE_BB_IRQ_ID_RF_SPI_GSM"/>
      <entry name="GGE_BB_IRQ_ID_MAILBOX"/>
      <entry name="GGE_BB_IRQ_ID_TCU_SYNC"/>
      <entry name="GGE_BB_IRQ_ID_NB_RX"/>
      <entry name="GGE_BB_IRQ_ID_NB_TX"/>
      <entry name="GGE_BB_IRQ_ID_NB_ACC"/>
      <entry name="GGE_BB_IRQ_ID_AIF0"/>
      <entry name="GGE_BB_IRQ_ID_AIF1"/>
      <entry name="GGE_BB_IRQ_ID_AIF2"/>
      <entry name="GGE_BB_IRQ_ID_AIF3"/>
      <entry name="GGE_BB_IRQ_ID_RF_SPI_NB"/>
      <entry name="GGE_BB_IRQ_ID_BB_DMA"/>
      <bound name="NB_GGE_BB_IRQ">
        <comment>Num of Gge IRQS</comment>
      </bound>
    </enum>
    <var name="NB_GGE_BB_IRQ_LEVEL" value="NB_GGE_BB_IRQ - NB_GGE_BB_IRQ_PULSE">
      <comment>Number of GGE BB Level IRQ</comment>
    </var>
    <var name="BB_SYMBOL_SIZE" value="13"/>
    <var name="VITAC_MULT_SIZE" value="14"/>
    <var name="BB_SRAM_ADDR_WIDTH" value="13"/>
    <var name="RF_NB_BITS_PADDR" value="12">
      <comment>System RF Apb Bus Configuration</comment>
    </var>
    <var name="RF_APB_STEP" value="exp2(RF_NB_BITS_PADDR)"/>
    <enum name="Rf_Apb_Id">
      <comment>8910m rf apb module id</comment>
      <entry name="RF_APB_ID_CTRL_1"/>
      <entry name="RF_APB_ID_CTRL_2"/>
      <entry name="RF_APB_ID_DFE"/>
      <entry name="RF_APB_ID_ET"/>
      <entry name="RF_APB_ID_RTC"/>
      <entry name="RF_APB_ID_SYS_CTRL"/>
      <entry name="RF_APB_ID_TIMER_1"/>
      <entry name="RF_APB_ID_TIMER_2"/>
      <entry name="RF_APB_ID_TIMER_3"/>
      <entry name="RF_APB_ID_UART"/>
      <entry name="RF_APB_ID_WATCHDOG"/>
      <entry name="RF_APB_ID_TSEN_ADC"/>
      <entry name="RF_APB_ID_RFFE"/>
      <bound name="RF_NB_PSEL">
        <comment>Num of RF Apb Slaves</comment>
      </bound>
    </enum>
    <var name="WCN_SYS_NB_BITS_PSEL" value="4">
      <comment>WCN System Apb Bus Configuration</comment>
    </var>
    <var name="WCN_SYS_NB_BITS_PADDR" value="12"/>
    <var name="WCN_SYS_APB_STEP" value="exp2(WCN_SYS_NB_BITS_PADDR)"/>
    <enum name="Wcn_Sys_Apb_Id">
      <comment>8910m wcn sys apb module id</comment>
      <entry name="WCN_SYS_APB_ID_SYS_CTRL"/>
      <entry name="WCN_SYS_APB_ID_DBM"/>
      <entry name="WCN_SYS_APB_ID_SYS_IFC"/>
      <entry name="WCN_SYS_APB_ID_BT_CORE"/>
      <entry name="WCN_SYS_APB_ID_UART"/>
      <entry name="WCN_SYS_APB_ID_RF_IF"/>
      <entry name="WCN_SYS_APB_ID_MODEM"/>
      <entry name="WCN_SYS_APB_ID_WLAN"/>
      <entry name="WCN_SYS_APB_ID_WDT"/>
      <entry name="WCN_SYS_APB_ID_TRAP"/>
      <entry name="WCN_SYS_APB_ID_SYSTICK"/>
      <entry name="WCN_SYS_APB_ID_COMREGS_WCN"/>
      <entry name="WCN_SYS_APB_ID_COMREGS_AP"/>
      <bound name="WCN_SYS_APB_NB_PSEL">
        <comment>Num of WCN System Apb Slaves</comment>
      </bound>
    </enum>
  </archive>
  <archive asm="no" relative="global_macros.xml">
    <cjoker>
#if defined(REG_ADDRESS_FOR_GGE)
#define KSEG0(addr)     ( (addr) | 0x80000000 )
#define KSEG1(addr)     ( (addr) | 0xA0000000 )
#else
#define KSEG0(addr)     (addr)
#define KSEG1(addr)     (addr)
#endif
#define REG_ACCESS_ADDRESS(addr)    KSEG1(addr)
/* Define access cached or uncached */
#define MEM_ACCESS_CACHED(addr)     (assert(0, &quot;NOT SUPPORTED&quot;))
#define MEM_ACCESS_UNCACHED(addr)   (assert(0, &quot;NOT SUPPORTED&quot;))
/* Register access for assembly */
#define BASE_HI(val) (((0xa0000000 | val) &amp; 0xffff8000) + (val &amp; 0x8000))
#define BASE_LO(val) (((val) &amp; 0x7fff) - (val &amp; 0x8000))
/* to extract bitfield from register value */
#define GET_BITFIELD(dword, bitfield) (((dword) &amp; (bitfield ## _MASK)) &gt;&gt; (bitfield ## _SHIFT))
#define EXP2(n) (1&lt;&lt;(n))
#define REG32 volatile unsigned int
#define REG16 volatile unsigned short
#define REG8  volatile unsigned char
#define UINT32 unsigned int
#define UINT16 unsigned short
#define UINT8  unsigned char
#define REG_READ_UINT32( _reg_ )           (*(volatile unsigned int*)(_reg_))
#define REG_WRITE_UINT32( _reg_, _val_)    ((*(volatile unsigned int*)(_reg_)) = (unsigned int)(_val_))
#define REG_READ_U64( _reg_ )          (*(volatile unsigned long*)(_reg_))
#define REG_WRITE_U64( _reg_, _val_)   ((*(volatile unsigned long*)(_reg_)) = (unsigned long)(_val_))
</cjoker>
  </archive>
  <archive relative="gallite_generic_config.xml">
    <var name="FPGA_OPTION" value="0">
      <comment>0= chip option; 1= FPGA option</comment>
    </var>
    <var name="BB_OPTION" value="1">
      <comment>0= no baseband; 1= baseband included</comment>
    </var>
    <var name="USE_TEST_MASTER" value="1">
      <comment>0= Nothing; 1= BIST; 2= TEST MASTER</comment>
    </var>
    <var name="USE_SYS_AHBC_MON" value="1">
      <comment>0= no monitor; 1=monitor included</comment>
    </var>
    <var name="HAVE_DEBUG_HOST_SEL" value="0">
      <comment>0= no debug host sel register as on test chip; 1=debug host sel register included</comment>
    </var>
    <var name="VOC_OPTION" value="1">
      <comment>0= No VOC ; 1= VOC included</comment>
    </var>
    <var name="AIF_OPTION" value="1">
      <comment>0= No aif channels (0,1) ; 1= All 3 channels</comment>
    </var>
    <var name="MMI_OPTION" value="1">
      <comment>0= No MMI ; 1= MMI included : keypad, PWL/PWT, calendar</comment>
    </var>
    <var name="NB_GPIO" value="32">
      <comment>GPIO/GPO OPTIONS: numbers</comment>
    </var>
    <var name="NB_GPIO_INT" value="32"/>
    <var name="NB_GPO" value="8"/>
    <var name="DMA_OPTION" value="1">
      <comment>0= No DMA ; 1= DMA included</comment>
    </var>
    <var name="SYS_PERIPH_OPTION" value="1">
      <comment>0 = no SPI, no GPADC, no UART1; 1 = SPI, GPADC, UART1 included</comment>
    </var>
    <var name="USB_OPTION" value="1">
      <comment>0 = no USB; 1 = USB included</comment>
    </var>
    <var name="AP_IFC_NB_STD_CHANNEL" value="7">
      <comment>Ap Ifc Number of generic channel (range 2 to 7)</comment>
    </var>
    <var name="AON_IFC_NB_STD_CHANNEL" value="2">
      <comment>Aon Ifc Number of generic channel (range 2 to 7)</comment>
    </var>
    <var name="SYS_IFC_NB_STD_CHANNEL" value="2">
      <comment>Gge Ifc Number of generic channel (range 2 to 7)</comment>
    </var>
    <var name="NB_AIF_IFC_CHANNEL" value="4">
      <comment>audio Ifc Number of generic channel (range 0 to 4)</comment>
    </var>
    <var name="UART2_OPTION" value="1">
      <comment>0 = no UART2; 1 = UART2 included</comment>
    </var>
    <var name="SPI1_NB_CS" value="3">
      <comment>number of SPI1 CS</comment>
    </var>
    <var name="SPI1_NB_DI" value="2">
      <comment>number of SPI1 DI</comment>
    </var>
    <var name="SPI1_DATA_SIZE" value="8">
      <comment>size of SPI1 DATA</comment>
    </var>
    <var name="SPI2_OPTION" value="1">
      <comment>0 = no SPI2; 1 = SPI2 included</comment>
    </var>
    <var name="SPI2_NB_CS" value="2">
      <comment>number of SPI2 CS</comment>
    </var>
    <var name="SPI2_NB_DI" value="2">
      <comment>number of SPI DI</comment>
    </var>
    <var name="SPI2_DATA_SIZE" value="8">
      <comment>size of SPI2 DATA</comment>
    </var>
    <var name="SPI3_OPTION" value="1">
      <comment>0 = no SPI3; 1 = SPI3 included</comment>
    </var>
    <var name="SPI3_NB_CS" value="3">
      <comment>number of SPI3 CS</comment>
    </var>
    <var name="SPI3_NB_DI" value="3">
      <comment>number of SPI DI</comment>
    </var>
    <var name="SPI3_DATA_SIZE" value="32">
      <comment>size of SPI3 DATA</comment>
    </var>
    <var name="SDMMC_OPTION" value="1">
      <comment>0 = no SDMMC; 1 = SDMMC controller included</comment>
    </var>
    <var name="CAMERA_OPTION" value="1">
      <comment>0 = no Camera; 1 = Camera controller included</comment>
    </var>
    <var name="GOUDA_OPTION" value="1">
      <comment>0 = no Gouda; 1 = Gouda included</comment>
    </var>
    <var name="MEMBRIDGE_OPTION" value="0">
      <comment>0 = EBC, 1 = AHBM</comment>
    </var>
    <var name="MEMBRIDGE_RAM_NB_BLOCK" value="2">
      <comment>for membridge internal ram: number of 32k blocks</comment>
    </var>
    <var name="EBC_NB_BITS_ADDR" value="25">
      <comment>for EBC option only</comment>
    </var>
    <var name="AHBM_NB_BITS_ADDR" value="26">
      <comment>for AHBM option only: address bus size</comment>
    </var>
    <var name="AHBM_INIT_SB_0" value="0"/>
    <var name="AHBM_INIT_SB_1" value="0"/>
    <var name="AHBM_INIT_SB_2" value="0"/>
    <var name="AHBM_INIT_SB_3" value="0"/>
    <var name="AHBM_INIT_SB_4" value="0"/>
  </archive>
  <archive relative="debug_host.xml">
    <module category="Debug" name="DEBUG_HOST">
      <reg name="cmd" protect="--">
        <bits access="r" name="addr" pos="28:0" rst="-">
          <comment>Address of data to be read or written.</comment>
        </bits>
        <bits access="r" name="size" pos="30:29" rst="-">
          <comment>
            These two bits indicates element data size.
            <br/>
            when &quot;00&quot; = &quot;byte&quot;.
            <br/>
            when &quot;01&quot; = &quot;half word&quot;.
            <br/>
            when &quot;10&quot; = &quot;word&quot;.
          </comment>
        </bits>
        <bits access="r" name="write_h" pos="31" rst="-">
          <comment>
            This bit indicates command is read or write.
            <br/>
        when &quot;0&quot; = &quot;Read&quot;.
            <br/>
        when &quot;1&quot; = &quot;Write&quot;.
          </comment>
        </bits>
      </reg>
      <reg name="data_reg" protect="--">
        <bits access="rw" name="data" pos="31:0" rst="-">
          <comment>Those bits are data to be read or written by IFC.</comment>
        </bits>
      </reg>
      <reg name="event" protect="rw">
        <bits access="rw" name="event0_sema" pos="0" rst="0">
          <comment>
            When read, this bit is used for event semaphore.
            <br/>
            '0' = no new event should be programed.
            <br/>
            '1' = no pending event, new event is authorised.
            <br/>
            If host is not enabled, this bit is always '1'. However in this case,
            any event written will be ignored.
            <br/>
            When Write, this bit is the least significant bit for a 32-bit event.
          </comment>
        </bits>
        <bits access="w" name="event31_1" pos="31:1" rst="-">
          <comment>These bits combined with bit0 consists a 32-bit event number. If a
            new event is written before the previous event has been sent, it will
            be ignored.</comment>
        </bits>
      </reg>
      <reg name="mode" protect="rw">
        <bits access="rw" name="force_on" pos="0" rst="1">
          <comment>When '1', force the debug host on, use clock UART if clock host is not
            detected.</comment>
        </bits>
        <bits access="r" name="clk_host_on" pos="1" rst="0">
          <comment>
            This bit indicates if clock host is detected to be on or not.
            <br/>
            '0' = no clock host.
            <br/>
            '1' = clock host detected.
          </comment>
        </bits>
      </reg>
      <reg name="h2p_status_reg" protect="rw">
        <bits access="r" name="h2p_status" pos="7:0" rst="0">
          <comment>Status which can be written through debug uart interface into a debug host
            internal register and read by APB.</comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="w" name="h2p_status_rst" pos="16" rst="0">
          <comment>write in this bit will reset h2p status register.</comment>
        </bits>
      </reg>
      <reg name="p2h_status_reg" protect="rw">
        <bits access="rw" name="p2h_status" pos="7:0" rst="0">
          <comment>Status which can be written by APB and read through debug uart interface
            as a debug host internal register.</comment>
        </bits>
      </reg>
      <reg name="irq" protect="r">
        <bits access="r" name="xcpu_irq" pos="0" rst="0">
          <comment>
            when write '1', clear the xcpu irq level which is programmed in a debug host
          internal register, this bit is automatic cleared.
            <br/>
             when read, get the xcpu
          irq status.
          </comment>
        </bits>
        <bits access="r" name="bcpu_irq" pos="1" rst="0">
          <comment>
            when write '1', clear the bcpu irq level which is programmed in a debug host
            internal register, this bit is automatic cleared.
            <br/>
             when read, get the bcpu
            irq status.
          </comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="debug_host_internals.xml">
    <include file="globals.xml"/>
    <module category="Debug" name="DEBUG_HOST_INTERNAL_REGISTERS">
      <ireg name="CTRL_SET" protect="rw">
        <comment>General control signals set.</comment>
        <bits access="rs" name="Debug_Reset" pos="0" rst="0">
          <comment>
            Debug host generated reset. Signal to system control. Active high.
            <br/>
            Write '1' to this bit will set it to '1'.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
        <bits access="rs" name="XCPU_Force_Reset" pos="1" rst="0">
          <comment>
            Force XCPU Reset signal. Active high. Hold XCPU in reset state until this bit is cleared.
            <br/>
            Write '1' to this bit will set it to '1'.
            <br/>
            Reseted by signal rst_host_reg.
          </comment>
        </bits>
        <bits access="rs" name="Force_Wakeup" pos="2" rst="0">
          <comment>
            Force wakeup. Active high.
            <br/>
            Write '1' to this bit will set it to '1'.
            <br/>
            Reseted by signal rst_host_reg.
          </comment>
        </bits>
        <bits access="rs" name="Force_BP_XCPU" pos="3" rst="0">
          <comment>
            Force XCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by XCPU.
            <br/>
            Write '1' to this bit will set it to '1'.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
        <bits access="rs" name="Force_BP_BCPU" pos="4" rst="0">
          <comment>
            Force BCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by BCPU.
            <br/>
            Write '1' to this bit will set it to '1'.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
        <bits access="rs" name="IT_XCPU" pos="5" rst="0">
          <comment>
            When write '1, generate a level IRQ to XCPU. Write '0 is ignored. This IRQ can be cleared by written APB register. When Read, Get the IRQ status.
            <br/>
            Write '1' to this bit will set it to '1'.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
        <bits access="rs" name="IT_BCPU" pos="6" rst="0">
          <comment>
            When write '1', generate a level IRQ to BCPU. Write '0' is ignored. This IRQ can be cleared by written APB register. When Read, Get the IRQ status.
            <br/>
            Write '1' to this bit will set it to '1'.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
        <bits access="rs" name="Debug_Port_Lock" pos="7" rst="0">
          <comment>
            Lock Debug port set.
            <br/>
            Write '1' to this bit will set it to '1'.
            <br/>
            Reseted by signal rst_host_reg.
          </comment>
        </bits>
      </ireg>
      <ireg name="CTRL_CLR" protect="rw">
        <comment>General control signals clear.</comment>
        <bits access="rc" name="XCPU_Force_Reset" pos="1" rst="0">
          <comment>
            Force XCPU Reset signal. Active high. Hold XCPU in reset state until this bit is cleared.
            <br/>
            Write '1' to this bit will clear it to '0'.
            <br/>
            Reseted by signal rst_host_reg.
          </comment>
        </bits>
        <bits access="rc" name="Force_Wakeup" pos="2" rst="0">
          <comment>
            Force wakeup. Active high.
            <br/>
            Write '1' to this bit will clear it to '0'.
            <br/>
            Reseted by signal rst_host_reg.
          </comment>
        </bits>
        <bits access="rc" name="Force_BP_XCPU" pos="3" rst="0">
          <comment>
            Force XCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by XCPU.
            <br/>
            Write '1' to this bit will clear it to '0'.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
        <bits access="rc" name="Force_BP_BCPU" pos="4" rst="0">
          <comment>
            Force BCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by BCPU.
            <br/>
            Write '1' to this bit will clear it to '0'.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
        <bits access="rc" name="Debug_Port_Lock" pos="7" rst="0">
          <comment>
            Lock Debug port clear.
            <br/>
            Write '1' to this bit will clear it to '0'.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
      </ireg>
      <ireg name="CLKDIV" protect="rw">
        <comment>Configure Debug UART Clock divider.</comment>
        <bits access="rw" name="CFG_CLK" pos="5:0" rst="2">
          <comment>
            Debug host clock divider. The serial clock is generated by dividing  14,7456MHz Host Clock by (CFG_CLK+2). So By default, the serial clock is 14,7456MHz / (2+2) = 3,6864 MHz which corresponds to the 921,6K Baud-rate.
            <br/>
            Reseted by signal rst_host_reg.
          </comment>
        </bits>
      </ireg>
      <ireg name="CFG" protect="rw">
        <comment>Configure Debug UART.</comment>
        <bits access="rw" name="Disable_Uart_H" pos="0" rst="0">
          <comment>
            When '1', Disable Normal Uart functional group.
            <br/>
            This bit is set to '1' when break.
            <br/>
            Reseted by signal rst_host_reg.
          </comment>
        </bits>
        <bits access="rw" name="Disable_IFC_H" pos="1" rst="0">
          <comment>
            When '1', Ignore IFC write and read access so only debug host internal is accessible.
            <br/>
            This bit is set to '1' when break.
            <br/>
            Reseted by signal rst_host_reg.
          </comment>
        </bits>
        <bits access="rw" name="Debug_Host_Sel" pos="2" rst="0">
          <comment>
            The usage of this bit is deternimed by the specific chip.
            <br/>
            Can be used as Debug_Port_Lock register to protect some register change by the regular software while debug hosr is used to set thoses registers to specific values.
            <br/>
            Reseted by signal rst_host_reg.
          </comment>
        </bits>
        <bits access="rw" name="Force_Prio_H" pos="7" rst="1">
          <comment>
            When '1', force the Debug Uart to have priority on TX.
            <br/>
            Reseted by signal rst_host_reg.
          </comment>
        </bits>
      </ireg>
      <ireg name="CRC_REG" protect="rw">
        <comment>Status of CRC.</comment>
        <bits access="rc" name="CRC" pos="0" rst="0">
          <comment>
            This bit represents that an CRC error has occured in commands received by Debug Host. Once set to '1', it will keep the value until this register is clearred by write '1'.
            <br/>
            '0' = no CRC error.
            <br/>
            '1' = CRC error.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
        <bits access="r" name="FC_Fifo_Ovf" pos="1" rst="0">
          <comment>
            This bit represents if the 16-byte Flow Control FIFO has an overflow error. This status will be kept until a RX break is received.
            <br/>
            '0' = no Flow Control Overflow Error.
            <br/>
            '1' = Flow Control Overflow Error.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
      </ireg>
      <ireg name="H2P_STATUS" protect="rw">
        <comment>Host write, APB readable register.</comment>
        <bits access="rw" name="STATUS" pos="7:0" rst="0">
          <comment>
            These bits can be read by APB and write by host. Corresponds to APB register STATUS. They can also be reseted to zeros by APB command. (see details in debug host APB register mapping)
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
      </ireg>
      <ireg name="P2H_STATUS" protect="rw">
        <comment>APB write, Host readable register.</comment>
        <bits access="rw" name="STATUS" pos="7:0" rst="0">
          <comment>
            These bits can be written by APB and read by host. Corresponds to APB register STATUS.
            <br/>
            Write to Bit 0 can reset the P2H status.
            <br/>
            Reseted by signal sys_rst_others (host).
          </comment>
        </bits>
      </ireg>
      <ireg name="AHB_SYS_HMBURSREQ" protect="r">
        <comment>Debug information of system side AHB bus status.</comment>
        <bits access="r" name="SYS_IFC_HMBURSREQ" pos="0" rst="-">
          <comment>The bit represent Sys Ifc HMBURSREQ.</comment>
        </bits>
        <bits access="r" name="SYS_DMA_HMBURSREQ" pos="1" rst="-">
          <comment>The bit represent Dma HMBURSREQ.</comment>
        </bits>
        <bits access="r" name="SYS_AHB2AHB_HMBURSREQ" pos="2" rst="-">
          <comment>The bit represent Sys Ahb2ahb HMBURSREQ.</comment>
        </bits>
        <bits access="r" name="XCPU_HMBURSREQ" pos="3" rst="-">
          <comment>The bit represent Xcpu HMBURSREQ.</comment>
        </bits>
        <bits access="r" name="USBC_HMBURSREQ" pos="4" rst="-">
          <comment>The bit represent USBC HMBURSREQ.</comment>
        </bits>
        <bits access="r" name="GOUDA_HMBURSREQ" pos="5" rst="-">
          <comment>The bit represent GOUDA HMBURSREQ.</comment>
        </bits>
      </ireg>
      <ireg name="AHB_SYS_HMGRANT" protect="r">
        <bits access="r" name="SYS_IFC_HMGRANT" pos="0" rst="-">
          <comment>The bit represent Sys Ifc HMGRANT.</comment>
        </bits>
        <bits access="r" name="SYS_DMA_HMGRANT" pos="1" rst="-">
          <comment>The bit represent Dma HMGRANT.</comment>
        </bits>
        <bits access="r" name="SYS_AHB2AHB_HMGRANT" pos="2" rst="-">
          <comment>The bit represent Sys Ahb2ahb HMGRANT.</comment>
        </bits>
        <bits access="r" name="XCPU_HMGRANT" pos="3" rst="-">
          <comment>The bit represent Xcpu HMGRANT.</comment>
        </bits>
        <bits access="r" name="USBC_HMGRANT" pos="4" rst="-">
          <comment>The bit represent USBC HMGRANT.</comment>
        </bits>
        <bits access="r" name="GOUDA_HMGRANT" pos="5" rst="-">
          <comment>The bit represent GOUDA HMGRANT.</comment>
        </bits>
      </ireg>
      <ireg name="AHB_SYS_HSEL" protect="r">
        <comment>Debug information of AHB bus status HSEL.</comment>
        <bits access="r" name="SYS_MEM_EXT_HSEL" pos="0" rst="-">
          <comment>The bit represent Sys MEM_EXT HSEL.</comment>
        </bits>
        <bits access="r" name="SYS_MEM_INT_HSEL" pos="1" rst="-">
          <comment>The bit represent Sys MEM_INT HSEL.</comment>
        </bits>
        <bits access="r" name="SYS_IFC_HSEL" pos="2" rst="-">
          <comment>The bit represent Sys Ifc HSEL.</comment>
        </bits>
        <bits access="r" name="SYS_AHB2AHB_HSEL" pos="3" rst="-">
          <comment>The bit represent Sys Ahb2ahb HSEL.</comment>
        </bits>
        <bits access="r" name="SYS_USBC_HSEL" pos="4" rst="-">
          <comment>The bit represent USBC HSEL.</comment>
        </bits>
        <bits access="r" name="SYS_GOUDA_HSEL" pos="5" rst="-">
          <comment>The bit represent GOUDA HSEL.</comment>
        </bits>
        <bits access="r" name="SYS_XCPU_RAM_HSEL" pos="6" rst="-">
          <comment>The bit represent XCPU RAM HSEL.</comment>
        </bits>
      </ireg>
      <ireg name="AHB_SYS_HSREADY" protect="r">
        <bits access="r" name="SYS_IFC_HSREADY" pos="0" rst="-">
          <comment>The bit represent Sys Ifc HSREADY.</comment>
        </bits>
        <bits access="r" name="SYS_MEM_HSREADY" pos="1" rst="-">
          <comment>The bit represent Sys EBC HSREADY.</comment>
        </bits>
        <bits access="r" name="SYS_AHB2AHB_HSREADY" pos="2" rst="-">
          <comment>The bit represent Sys Ahb2ahb HSREADY.</comment>
        </bits>
        <bits access="r" name="SYS_USBC_HSREADY" pos="4" rst="-">
          <comment>The bit represent USBC HSREADY.</comment>
        </bits>
        <bits access="r" name="SYS_GOUDA_HSREADY" pos="5" rst="-">
          <comment>The bit represent GOUDA HSREADY.</comment>
        </bits>
        <bits access="r" name="SYS_XCPU_RAM_HSREADY" pos="6" rst="-">
          <comment>The bit represent XCPU RAM HSREADY.</comment>
        </bits>
        <bits access="r" name="SYS_HREADY" pos="7" rst="-">
          <comment>The bit represent Sys HSREADY which is sent to all sys AHB slaves.</comment>
        </bits>
      </ireg>
      <ireg name="AHB_BB_MASTER" protect="r">
        <comment>Debug information of baseband side AHB bus status.</comment>
        <bits access="r" name="BB_IFC_HMBURSREQ" pos="0" rst="-">
          <comment>The bit represent BB Ifc HMBURSREQ.</comment>
        </bits>
        <bits access="r" name="BB_VOC_HMBURSREQ" pos="1" rst="-">
          <comment>The bit represent Voc HMBURSREQ.</comment>
        </bits>
        <bits access="r" name="BB_AHB2AHB_HMBURSREQ" pos="2" rst="-">
          <comment>The bit represent BB Ahb2ahb HMBURSREQ.</comment>
        </bits>
        <bits access="r" name="BCPU_HMBRSREQ" pos="3" rst="-">
          <comment>The bit represent Bcpu HMBURSREQ.</comment>
        </bits>
        <bits access="r" name="BB_IFC_HMGRANT" pos="4" rst="-">
          <comment>The bit represent BB Ifc HMGRANT.</comment>
        </bits>
        <bits access="r" name="BB_VOC_HMGRANT" pos="5" rst="-">
          <comment>The bit represent Voc HMGRANT.</comment>
        </bits>
        <bits access="r" name="BB_AHB2AHB_HMGRANT" pos="6" rst="-">
          <comment>The bit represent BB Ahb2ahb HMGRANT.</comment>
        </bits>
        <bits access="r" name="BCPU_HMGRANT" pos="7" rst="-">
          <comment>The bit represent Bcpu HMGRANT.</comment>
        </bits>
      </ireg>
      <ireg name="AHB_BB_HSREADY" protect="r">
        <comment>Debug information of AHB bus status HSEL.</comment>
        <bits access="r" name="BB_MEM_HSREADY" pos="0" rst="-">
          <comment>The bit represent BB MEM HSREADY.</comment>
        </bits>
        <bits access="r" name="BB_VOC_HSREADY" pos="1" rst="-">
          <comment>The bit represent BB VoC HSREADY.</comment>
        </bits>
        <bits access="r" name="BB_SRAM_HSREADY" pos="2" rst="-">
          <comment>The bit represent BB Sram HSREADY.</comment>
        </bits>
        <bits access="r" name="BB_IFC_HSREADY" pos="3" rst="-">
          <comment>The bit represent BB Ifc HSREADY.</comment>
        </bits>
        <bits access="r" name="BB_AHB2AHB_HSREADY" pos="4" rst="-">
          <comment>The bit represent BB Ahb2ahb HSREADY.</comment>
        </bits>
        <bits access="r" name="BB_HREADY" pos="7" rst="-">
          <comment>The bit represent BB HREADY which is sent to all BB AHB slaves.</comment>
        </bits>
      </ireg>
      <ireg name="AHB_BB_HSEL" protect="r">
        <comment>Debug information of AHB bus status HSEL.</comment>
        <bits access="r" name="BB_MEM_EXT_HSEL" pos="0" rst="-">
          <comment>The bit represent BB MEM_EXT HSEL.</comment>
        </bits>
        <bits access="r" name="BB_MEM_INT_HSEL" pos="1" rst="-">
          <comment>The bit represent BB MEM_INT HSEL.</comment>
        </bits>
        <bits access="r" name="BB_VOC_HSEL" pos="2" rst="-">
          <comment>The bit represent BB VOC HSEL.</comment>
        </bits>
        <bits access="r" name="BB_SRAM_HSEL" pos="3" rst="-">
          <comment>The bit represent BB Sram HSEL.</comment>
        </bits>
        <bits access="r" name="BB_IFC_HSEL" pos="4" rst="-">
          <comment>The bit represent BB Ifc HSEL.</comment>
        </bits>
        <bits access="r" name="BB_AHB2AHB_HSEL" pos="5" rst="-">
          <comment>The bit represent BB Ahb2ahb HSEL.</comment>
        </bits>
      </ireg>
      <ireg name="AHB_SYS_MASK_SPLIT" protect="r">
        <comment>Represents the split status register of the SYS_AHBC.</comment>
        <bits access="r" name="Sys_Mask_Split" pos="9-1:1" rst="all-">
            </bits>
      </ireg>
      <ireg name="AHB_BB_MASK_SPLIT" protect="r">
        <comment>Represents the split status register of the BB_AHBC.</comment>
        <bits access="r" name="BB_Mask_Split" pos="6:1" rst="all-">
            </bits>
      </ireg>
    </module>
  </archive>
  <archive relative="debug_uart.xml">
    <module category="System" name="DEBUG_UART">
      <var name="DEBUG_UART_RX_FIFO_SIZE" value="16"/>
      <var name="DEBUG_UART_TX_FIFO_SIZE" value="16"/>
      <var name="DEBUG_UART_NB_RX_FIFO_BITS" value="4"/>
      <var name="DEBUG_UART_NB_TX_FIFO_BITS" value="4"/>
      <var name="ESC_DAT" value="92"/>
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="enable" pos="0" rst="0">
          <options>
            <option name="DISABLE" value="0"/>
            <option name="ENABLE" value="1"/>
            <default/>
          </options>
          <comment>
            Allows to turn off the UART:
            <br/>
            0 = Disable
            <br/>
            1 = Enable
          </comment>
        </bits>
        <bits access="rw" name="data bits" pos="1" rst="0">
          <options>
            <option name="7_BITS" value="0"/>
            <option name="8_BITS" value="1"/>
            <default/>
          </options>
          <comment>
            Number of data bits per character (least significant bit
          first):
            <br/>
            0 = 7 bits
            <br/>
            1 = 8 bits
            <br/>
             This bit will be masked to
          '1' if debug host is enabled.
          </comment>
        </bits>
        <bits access="rw" name="tx stop bits" pos="2" rst="0">
          <options>
            <option name="1_BIT" value="0"/>
            <option name="2_BITS" value="1"/>
            <default/>
          </options>
          <comment>
            Stop bits controls the number of stop bits transmitted. Can
      receive with one stop bit (more inaccuracy can be compensated with two
      stop bits when divisor mode is set to 0).
            <br/>
            0 = one stop bit is
      transmitted in the serial data.
            <br/>
            1 = two stop bits are generated and
      transmitted in the serial data out.
            <br/>
             This bit will be masked to
      '0' if debug host is enabled.
          </comment>
        </bits>
        <bits access="rw" name="parity enable" pos="3" rst="0">
          <options>
            <option name="NO" value="0"/>
            <option name="YES" value="1"/>
            <default/>
          </options>
          <comment>
            Parity is enabled when this bit is set.
            <br/>
             This bit will be masked to
      '0' if debug host is enabled.
          </comment>
        </bits>
        <bits access="rw" name="parity select" pos="5:4" rst="0">
          <options>
            <option name="ODD" value="0"/>
            <option name="EVEN" value="1"/>
            <option name="SPACE" value="2"/>
            <option name="MARK" value="3"/>
            <default/>
          </options>
          <comment>
            Controls the parity format when parity is enabled:
            <br/>
            00 =
      an odd number of received 1 bits is checked, or transmitted (the parity
      bit is included).
            <br/>
            01 = an even number of received 1 bits is checked
      or transmitted (the parity bit is included).
            <br/>
            10 = a space is
      generated and received as parity bit.
            <br/>
            11 = a mark is generated and
      received as parity bit.
            <br/>
             These bit will be ignored if debug host is
      enabled.
          </comment>
        </bits>
        <bits access="rw" name="tx break control" pos="6" rst="0">
          <comment>
            Sends a break signal by holding the Uart_Tx line low until
          this bit is cleared.
            <br/>
             This bit will be masked to '0' if debug host
          is enabled.
          </comment>
          <options>
            <option name="OFF" value="0"/>
            <option name="ON" value="1"/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="rx fifo reset" pos="7" rst="0">
    </bits>
        <bits access="rw" name="tx fifo reset" pos="8" rst="0">
    </bits>
        <bits access="rw" name="dma mode" pos="9" rst="0">
          <options>
            <option name="DISABLE" value="0"/>
            <option name="ENABLE" value="1"/>
            <default/>
          </options>
          <comment>Enables the DMA signaling for the Uart_Dma_Tx_Req_H and
      Uart_Dma_Rx_Req_H to the IFC.</comment>
        </bits>
        <bits access="rw" name="swrx flow ctrl" pos="13:12" rst="1">
          <comment>
            When this field is &quot;00&quot; and SWTX_flow_Ctrl is also &quot;00&quot;, hardwre
            flow ctrl is used. Otherwise, software flow control is used:
            <br/>
            00 = no transmit flow control.
            <br/>
            01 = transmit XON1/XOFF1 as flow control bytes
            <br/>
            10 = transmit XON2/XOFF2 as flow control bytes
            <br/>
            11 = transmit XON1 and XON2/XOFF1 and XOFF2 as flow control bytes
            <br/>
          </comment>
          <options>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="swtx flow ctrl" pos="15:14" rst="1">
          <comment>
            When this field is &quot;00&quot; and SWRX_flow_Ctrl is also &quot;00&quot;, hardwre
            flow ctrl is used. Otherwise, software flow control is used:
            <br/>
            00 = no receive flow control
            <br/>
            01 = receive XON1/XOFF1 as flow control bytes
            <br/>
            10 = receive XON2/XOFF2 as flow control bytes
            <br/>
            11 = receive XON1 and XON2/XOFF1 and XOFF2 as flow control bytes
            <br/>
            <br/>
             Note: If single XON/XOFF character is used for flow contol, the received
            XON/XOFF character will not be put into Rx FIFO. This is also the case if XON is
            received when XOFF is expected.
            <br/>
            If double XON/XOFF characters are expected, the XON1/XOFF1 must followed sequently
            by XON2/XOFF2 to be considered as patterns, which will not be put into Rx FIFO.
            Otherwise they will be considered as data. This is also the case if XOFF1 is followed
            by character other than XOFF2.
            <br/>
          </comment>
          <options>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="backslash en" pos="16" rst="1">
          <comment>When soft flow control characters or backslash are encountered in the data file,
            they will be inverted and a backslash will be added before them. for example, if tx data
            is XON(0x11) with BackSlash_En = '1', then uart will send 5Ch(Backslash) + EEh (~XON).</comment>
        </bits>
        <bits access="rw" name="send xon" pos="17" rst="1">
    </bits>
        <bits access="rw" name="tx finish n wait" pos="19" rst="0">
          <comment>When this bit is set the Tx engine terminates to send the
      current byte and then it stops to send data.</comment>
        </bits>
        <bits access="rw" name="divisor mode" pos="20" rst="0">
          <comment>
            Selects the divisor value used to generate the baud rate
      frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA
      is enable, this bit is ignored and the divisor used will be 16.
            <br/>
            0 =
      (BCLK = SCLK / 4)
            <br/>
            1 = (BCLK = SCLK / 16)
            <br/>
             This bit will be
      masked to '0' if debug host is enabled.
          </comment>
        </bits>
        <bits access="rw" name="irda enable" pos="21" rst="0">
          <comment>
            When set, the UART is in IrDA mode and the baud rate divisor
      used is 16 (see UART Operation for details).
            <br/>
             This bit will be
      masked to '0' if debug host is enabled.
          </comment>
        </bits>
        <bits access="rw" name="rx rts" pos="22" rst="0">
          <comment>
            Controls the Uart_RTS output (not directly in auto flow control
      mode).
            <br/>
            0 = the Uart_RTS will be inactive high
            <br/>
            1 = the Uart_RTS
      will be active low
            <br/>
             This bit will be masked to '1' if debug host is
      enabled.
          </comment>
          <options>
            <option name="INACTIVE" value="0"/>
            <option name="ACTIVE" value="1"/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="auto flow control" pos="23" rst="0">
          <options>
            <option name="ENABLE" value="1"/>
            <option name="DISABLE" value="0"/>
            <default/>
          </options>
          <comment>
            Enables the auto flow control.
            <br/>
          In case HW flow control (both swTx_Flow_ctrl=0 and swRx_Flow_Ctrl=0),
          If Auto_Flow_Control is enabled, Uart_RTS is controlled by the Rx RTS bit in
          CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx
          Fifo Level and AFC_Level in Triggers register).
          Tx data flow is stopped If Uart_CTS become inactive high.
            <br/>
          If Auto_Flow_Control is disabled, Uart_RTS is controlled only by the Rx RTS
          bit in CMD_Set register. Uart_CTS will not take effect.
            <br/>
            <br/>
          In case SW flow control(either swTx_Flow_ctrl/=0 or swRx_Flow_Ctrl/=0),
          If Auto_Flow_Control is enabled, XON/XOFF will be controlled by the Rx RTS bit
          in CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx
          Fifo Level and AFC_Level in Triggers register).
            <br/>
          If Auto_Flow_Control is disabled, XON/XOFF will be controlled only by Rx RTS bit
          in CMD_Set register. Tx data flow will be stoped when XOFF is received either
          this bit is enable or disabled.
            <br/>
            <br/>
             This bit will be masked to '1' if debug host is enabled.
          </comment>
        </bits>
        <bits access="rw" name="loop back mode" pos="24" rst="0">
          <comment>When set, data on the Uart_Tx line is held high, while the
      serial output is looped back to the serial input line, internally. In
      this mode all the interrupts are fully functional. This feature is used
      for diagnostic purposes. Also, in loop back mode, the modem control
      input Uart_CTS is disconnected and the modem control output Uart_RTS are
      looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is
      inverted (see IrDA SIR Mode Support).</comment>
        </bits>
        <bits access="rw" name="rx lock err" pos="25" rst="0">
          <comment>
            Allow to stop the data receiving when an error is detected
      (framing, parity or break). The data in the fifo are kept.
            <br/>
             This bit
      will be masked to '0' if debug host is enabled.
          </comment>
          <options>
            <option name="DISABLE" value="0"/>
            <option name="ENABLE" value="1"/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="hst txd oen" pos="26" rst="0">
          <comment>HST TXD output enable. '0' enable.</comment>
          <options>
            <option name="DISABLE" value="1"/>
            <option name="ENABLE" value="0"/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="rx break length" pos="31:28" rst="0xF">
          <comment>
            Length of a break, in number of bits.
            <br/>
             This bit will be masked
      to &quot;1011&quot; if debug host is enabled.
          </comment>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="rx fifo level" pos="4:0" rst="0">
          <options>
            <mask/>
            <shift/>
          </options>
          <comment>Those bits indicate the number of data available in the Rx
      Fifo. Those data can be read.</comment>
        </bits>
        <bits access="r" name="tx fifo level" pos="12:8" rst="0">
          <options>
            <mask/>
            <shift/>
          </options>
          <comment>Those bits indicate the number of data available in the Tx
      Fifo. Those data will be sent.</comment>
        </bits>
        <bits access="r" name="tx active" pos="13" rst="0">
          <comment>This bit indicates that the UART is sending data. If no data is
      in the fifo, the UART is currently sending the last one through the
      serial interface.</comment>
        </bits>
        <bits access="r" name="rx active" pos="14" rst="0">
          <comment>This bit indicates that the UART is receiving a byte.</comment>
        </bits>
        <bits access="r" name="rx overflow err" pos="16" rst="0">
          <comment>This bit indicates that the receiver received a new character
      when the fifo was already full. The new character is discarded. This bit
      is cleared when the UART_STATUS register is written with any value.</comment>
        </bits>
        <bits access="r" name="tx overflow err" pos="17" rst="0">
          <comment>This bit indicates that the user tried to write a character when fifo was
          already full. The written data will not be kept. This bit is cleared when
          the UART_STATUS register is written with any value.</comment>
        </bits>
        <bits access="r" name="rx parity err" pos="18" rst="0">
          <comment>This bit is set if the parity is enabled and a parity error
      occurred in the received data. This bit is cleared when the UART_STATUS
      register is written with any value.</comment>
        </bits>
        <bits access="r" name="rx framing err" pos="19" rst="0">
          <comment>This bit is set whenever there is a framing error occured. A
      framing error occurs when the receiver does not detect a valid STOP bit
      in the received data. This bit is cleared when the UART_STATUS register
      is written with any value.</comment>
        </bits>
        <bits access="r" name="rx break int" pos="20" rst="0">
          <comment>This bit is set whenever the serial input is held in a logic 0
      state for longer than the length of x bits, where x is the value
      programmed Rx Break Length. A null word will be written in the Rx Fifo.
      This bit is cleared when the UART_STATUS register is written with any
      value.</comment>
        </bits>
        <bits access="r" name="tx dcts" pos="24" rst="0">
          <comment>
            In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0),
            This bit is set when the Uart_CTS line changed since the last
            time this register has been written.
            <br/>
            In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0),
            This bit is set when received XON/XOFF status changed since the last time
            this register has been writtern.
            <br/>
            This bit is cleared when the UART_STATUS register is written with any value.
          </comment>
        </bits>
        <bits access="r" name="tx cts" pos="25" rst="0">
          <comment>
            In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0),
            current value of the Uart_CTS line.
            <br/>
             '1' = Tx not allowed.
            <br/>
             '0' = Tx allowed.
            <br/>
            In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0),
            current state of software flow control.
            <br/>
             '1' = when XOFF received.
            <br/>
             '0' = when XON received.
          </comment>
        </bits>
        <bits access="r" name="tx fifo rsted l" pos="28" rst="0">
          <comment>This bit is set when Tx Fifo Reset command is received by CTRL
      register and is cleared when Tx fifo reset process has finished.</comment>
        </bits>
        <bits access="r" name="rx fifo rsted l" pos="29" rst="0">
          <comment>This bit is set when Rx Fifo Reset command is received by CTRL
      register and is cleared when Rx fifo reset process has finished.</comment>
        </bits>
        <bits access="r" name="enable n finished" pos="30" rst="0">
          <comment>This bit is set when bit enable is changed from '0' to '1' or
      from '1' to '0', it is cleared when the enable process has finished.</comment>
        </bits>
        <bits access="r" name="clk enabled" pos="31" rst="0">
          <comment>This bit is set when Uart Clk has been enabled and received by
      UART after Need Uart Clock becomes active. It serves to avoid enabling
      Rx RTS too early.</comment>
        </bits>
      </reg>
      <reg name="rxtx_buffer" protect="--">
        <bits access="r" name="rx data" pos="7:0" rst="no">
          <comment>The UART_RECEIVE_BUFFER register is a read-only register that
      contains the data byte received on the serial input port. This register
      accesses the head of the receive FIFO. If the receive FIFO is full and
      this register is not read before the next data character arrives, then
      the data already in the FIFO will be preserved but any incoming data
      will be lost. An overflow error will also occur.</comment>
        </bits>
        <bits access="w" name="tx data" pos="7:0" rst="no">
          <comment>The UART_TRANSMIT_HOLDING register is a write-only register
      that contains data to be transmitted on the serial output port. 16
      characters of data may be written to the UART_TRANSMIT_HOLDING register
      before the FIFO is full. Any attempt to write data when the FIFO is full
      results in the write data being lost.</comment>
        </bits>
      </reg>
      <reg name="irq_mask" protect="rw">
        <bits access="rw" name="tx modem status" pos="0" rst="0">
          <comment>Clear to send signal change or XON/XOFF detected.</comment>
        </bits>
        <bits access="rw" name="rx data available" pos="1" rst="0">
          <comment>Rx Fifo at or upper threshold level (current level &gt;= Rx
      Fifo trigger level).</comment>
        </bits>
        <bits access="rw" name="tx data needed" pos="2" rst="0">
          <comment>Tx Fifo at or below threshold level (current level &lt;= Tx
      Fifo trigger level).</comment>
        </bits>
        <bits access="rw" name="rx timeout" pos="3" rst="0">
          <comment>No characters in or out of the Rx Fifo during the last 4
      character times and there is at least 1 character in it during this
      time.</comment>
        </bits>
        <bits access="rw" name="rx line err" pos="4" rst="0">
          <comment>Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break
      Interrupt.</comment>
        </bits>
        <bits access="rw" name="tx dma done" pos="5" rst="0">
          <comment>Pulse detected on Uart_Dma_Tx_Done_H signal.</comment>
        </bits>
        <bits access="rw" name="rx dma done" pos="6" rst="0">
          <comment>Pulse detected on Uart_Dma_Rx_Done_H signal.</comment>
        </bits>
        <bits access="rw" name="rx dma timeout" pos="7" rst="0">
          <comment>In DMA mode, there is at least 1 character that has been read
            in or out the Rx Fifo. Then before received Rx DMA Done, No characters
            in or out of the Rx Fifo during the last 4 character times.</comment>
        </bits>
        <bits access="rw" name="xoff_detected" pos="8" rst="0">
    </bits>
      </reg>
      <reg name="irq_cause" protect="rw">
        <bits access="r" name="tx modem status" pos="0" rst="0">
          <comment>Clear to send signal detected. Reset control: This bit is
      cleared when the UART_STATUS register is written with any value.</comment>
        </bits>
        <bits access="r" name="rx data available" pos="1" rst="0">
          <comment>Rx Fifo at or upper threshold level (current level &gt;= Rx
      Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER
      until the Fifo drops below the trigger level.</comment>
        </bits>
        <bits access="r" name="tx data needed" pos="2" rst="0">
          <comment>Tx Fifo at or below threshold level (current level &lt;= Tx
      Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING
      register above threshold level.</comment>
        </bits>
        <bits access="r" name="rx timeout" pos="3" rst="0">
          <comment>No characters in or out of the Rx Fifo during the last 4
      character times and there is at least 1 character in it during this
      time. Reset control: Reading from the UART_RECEIVE_BUFFER register.</comment>
        </bits>
        <bits access="r" name="rx line err" pos="4" rst="0">
          <comment>Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break
      Interrupt. Reset control: This bit is cleared when the UART_STATUS
      register is written with any value.</comment>
        </bits>
        <bits access="rw" name="tx dma done" pos="5" rst="0">
          <comment>This interrupt is generated when a pulse is detected on the
      Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register.</comment>
        </bits>
        <bits access="rw" name="rx dma done" pos="6" rst="0">
          <comment>This interrupt is generated when a pulse is detected on the
      Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register.</comment>
        </bits>
        <bits access="rw" name="rx dma timeout" pos="7" rst="0">
          <comment>In DMA mode, there is at least 1 character that has been read
            in or out the Rx Fifo. Then before received Rx DMA Done, No characters
            in or out of the Rx Fifo during the last 4 character times.</comment>
        </bits>
        <bits access="r" name="xoff detected" pos="8" rst="0">
    </bits>
        <bits access="r" name="tx modem status u" pos="16" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="rx data available u" pos="17" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="tx data needed u" pos="18" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="rx timeout u" pos="19" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="rx line err u" pos="20" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="tx dma done u" pos="21" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="rx dma done u" pos="22" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="rx dma timeout u" pos="23" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="xoff detected u" pos="24" rst="0">
    </bits>
      </reg>
      <reg name="triggers" protect="rw">
        <bits access="rw" name="rx trigger" pos="3:0" rst="0">
          <comment>
            Defines the threshold level at which the Data Available
      Interrupt will be generated.
            <br/>
            The Data Available interrupt is
      generated when quantity of data in Rx Fifo &gt; Rx Trigger.
          </comment>
        </bits>
        <bits access="rw" name="tx trigger" pos="7:4" rst="0">
          <comment>
            Defines the threshold level at which the Data Needed
      Interrupt will be generated.
            <br/>
            The Data Needed Interrupt is generated
      when quantity of data in Tx Fifo &lt;= Tx Trigger.
          </comment>
        </bits>
        <bits access="rw" name="afc level" pos="11:8" rst="0">
          <comment>
            Controls the Rx Fifo level at which the Uart_RTS Auto Flow
      Control will be set inactive high (see UART Operation for more details
      on AFC).
            <br/>
            The Uart_RTS Auto Flow Control will be set inactive high
      when quantity of data in Rx Fifo &gt; AFC Level.
          </comment>
        </bits>
      </reg>
      <reg name="xchar" protect="rw">
        <bits access="rw" name="xon1" pos="7:0" rst="17">
          <comment>XON1 character value. Reset Value is CTRL-Q 0x11.</comment>
        </bits>
        <bits access="rw" name="xoff1" pos="15:8" rst="19">
          <comment>XOFF1 character value. Reset Value is CTRL-S 0x13</comment>
        </bits>
        <bits access="rw" name="xon2" pos="23:16" rst="0">
          <comment>XON2 character value.</comment>
        </bits>
        <bits access="rw" name="xoff2" pos="31:24" rst="0">
          <comment>XOFF2 character value.</comment>
        </bits>
        <comment>These characters must respect following constraints: They must be different if used in software control, if BackSlash_En='1', they cannot be '\' and they cannot be complementary to each other, for example neither XON1 = ~XOFF1 nor XON1 = ~'\' is permitted.</comment>
      </reg>
    </module>
  </archive>
  <archive relative="arm_axidma.xml">
    <module category="System" name="ARM_AXIDMA">
      <reg name="axidma_conf" protect="rw">
        <bits access="rw" name="gen_reg_secuirty_en" pos="6" rst="1">
          <comment>general used register security visit enable
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="resp_err_stop_en" pos="5" rst="0">
          <comment>response error stop function enable
0:enable
1:disable</comment>
        </bits>
        <bits access="rw" name="outstand" pos="4:3" rst="2">
          <comment>the number of outstanding that can be send out
0: 2
1: 3
2: 4</comment>
        </bits>
        <bits access="rw" name="priority" pos="2" rst="0">
          <comment>multe-channel transport priority mode control
0: there is no priority in the channels, using polling to DMA data
1: smaller channel number has high-priority.high-priority move data before low-priority channels</comment>
        </bits>
        <bits access="rw" name="stop_ie" pos="1" rst="0">
          <comment>interrupt control bit
0: no interruption occurs when all logical channels finish
1: interruption occurs when all logical channels finish</comment>
        </bits>
        <bits access="rw" name="stop" pos="0" rst="0">
          <comment>the control bit of logical channel transport finish
0: don't stop all the channel,or automatically clear after setting
1: stop all channel.the current transmission is stopped.the start bits of all channels are cleared</comment>
        </bits>
      </reg>
      <reg name="axidma_delay" protect="rw">
        <bits access="rw" name="delay" pos="15:0" rst="0">
          <comment>in the non-priority mode, the time interval between two COUNTP transmission. Take the system clock as the criterion to avoid AXIDMA long-term use of the bus.</comment>
        </bits>
      </reg>
      <reg name="axidma_status" protect="r">
        <bits access="r" name="stop_status" pos="4" rst="0">
          <comment>stop status
0: not finish
1: finish</comment>
        </bits>
        <bits access="r" name="ch_num" pos="3:0" rst="15">
          <comment>the channel number of the final transmission
0000: channel 0 just finished the transmission
0001: channel 1 just finished the transmission
0010: channel 2 just finished the transmission
......
1011: channel 11 just finished the transmission
others: nonentity</comment>
        </bits>
      </reg>
      <reg name="axidma_irq_stat" protect="r">
        <bits access="r" name="rst_fin_irq" pos="12" rst="0">
          <comment>logic channel stop interrupt status</comment>
        </bits>
        <bits access="r" name="ch11_irq" pos="11" rst="0">
          <comment>channel 11 interrupts state
0: the channel 11 has not been interrupted, or the interrupt bit has been cleared
1: channel 11 is interrupted</comment>
        </bits>
        <bits access="r" name="ch10_irq" pos="10" rst="0">
          <comment>channel 10 interrupts state
0: the channel 10 has not been interrupted, or the interrupt bit has been cleared
1: channel 10 is interrupted</comment>
        </bits>
        <bits access="r" name="ch9_irq" pos="9" rst="0">
          <comment>channel 9 interrupts state
0: the channel 9 has not been interrupted, or the interrupt bit has been cleared
1: channel 9 is interrupted</comment>
        </bits>
        <bits access="r" name="ch8_irq" pos="8" rst="0">
          <comment>channel 8 interrupts state
0: the channel 8 has not been interrupted, or the interrupt bit has been cleared
1: channel 8 is interrupted</comment>
        </bits>
        <bits access="r" name="ch7_irq" pos="7" rst="0">
          <comment>channel 7 interrupts state
0: the channel 7 has not been interrupted, or the interrupt bit has been cleared
1: channel 7 is interrupted</comment>
        </bits>
        <bits access="r" name="ch6_irq" pos="6" rst="0">
          <comment>channel 6 interrupts state
0: the channel 6 has not been interrupted, or the interrupt bit has been cleared
1: channel 6 is interrupted</comment>
        </bits>
        <bits access="r" name="ch5_irq" pos="5" rst="0">
          <comment>channel 5 interrupts state
0: the channel 5 has not been interrupted, or the interrupt bit has been cleared
1: channel 5 is interrupted</comment>
        </bits>
        <bits access="r" name="ch4_irq" pos="4" rst="0">
          <comment>channel 4 interrupts state
0: the channel 4 has not been interrupted, or the interrupt bit has been cleared
1: channel 4 is interrupted</comment>
        </bits>
        <bits access="r" name="ch3_irq" pos="3" rst="0">
          <comment>channel 3 interrupts state
0: the channel 3 has not been interrupted, or the interrupt bit has been cleared
1: channel 3 is interrupted</comment>
        </bits>
        <bits access="r" name="ch2_irq" pos="2" rst="0">
          <comment>channel 2 interrupts state
0: the channel 2 has not been interrupted, or the interrupt bit has been cleared
1: channel 2 is interrupted</comment>
        </bits>
        <bits access="r" name="ch1_irq" pos="1" rst="0">
          <comment>channel 1 interrupts state
0: the channel 1 has not been interrupted, or the interrupt bit has been cleared
1: channel 1 is interrupted</comment>
        </bits>
        <bits access="r" name="ch0_irq" pos="0" rst="0">
          <comment>channel 0 interrupts state
0: the channel 0 has not been interrupted, or the interrupt bit has been cleared
1: channel 0 is interrupted</comment>
        </bits>
      </reg>
      <reg name="axidma_arm_req_stat" protect="r">
        <bits access="r" name="irq23" pos="23" rst="0">
          <comment>state of IRQ 23 generate requests of moving data
0: IRQ 23 does not generate requests of moving data
1: IRQ 23 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq22" pos="22" rst="0">
          <comment>state of IRQ 22 generate requests of moving data
0: IRQ 22 does not generate requests of moving data
1: IRQ 22 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq21" pos="21" rst="0">
          <comment>state of IRQ 21 generate requests of moving data
0: IRQ 21 does not generate requests of moving data
1: IRQ 21 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq20" pos="20" rst="0">
          <comment>state of IRQ 20 generate requests of moving data
0: IRQ 20 does not generate requests of moving data
1: IRQ 20 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq19" pos="19" rst="0">
          <comment>state of IRQ 19 generate requests of moving data
0: IRQ 19 does not generate requests of moving data
1: IRQ 19 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq18" pos="18" rst="0">
          <comment>state of IRQ 18 generate requests of moving data
0: IRQ 18 does not generate requests of moving data
1: IRQ 18 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq17" pos="17" rst="0">
          <comment>state of IRQ 17 generate requests of moving data
0: IRQ 17 does not generate requests of moving data
1: IRQ 17 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq16" pos="16" rst="0">
          <comment>state of IRQ 16 generate requests of moving data
0: IRQ 16 does not generate requests of moving data
1: IRQ 16 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq15" pos="15" rst="0">
          <comment>state of IRQ 15 generate requests of moving data
0: IRQ 15 does not generate requests of moving data
1: IRQ 15 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq14" pos="14" rst="0">
          <comment>state of IRQ 14 generate requests of moving data
0: IRQ 14 does not generate requests of moving data
1: IRQ 14 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq13" pos="13" rst="0">
          <comment>state of IRQ 13 generate requests of moving data
0: IRQ 13 does not generate requests of moving data
1: IRQ 13 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq12" pos="12" rst="0">
          <comment>state of IRQ 12 generate requests of moving data
0: IRQ 12 does not generate requests of moving data
1: IRQ 12 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq11" pos="11" rst="0">
          <comment>state of IRQ 11 generate requests of moving data
0: IRQ 11 does not generate requests of moving data
1: IRQ 11 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq10" pos="10" rst="0">
          <comment>state of IRQ 10 generate requests of moving data
0: IRQ 10 does not generate requests of moving data
1: IRQ 10 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq9" pos="9" rst="0">
          <comment>state of IRQ 9 generate requests of moving data
0: IRQ 9 does not generate requests of moving data
1: IRQ 7 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq8" pos="8" rst="0">
          <comment>state of IRQ 8 generate requests of moving data
0: IRQ 8 does not generate requests of moving data
1: IRQ 8 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq7" pos="7" rst="0">
          <comment>state of IRQ 7 generate requests of moving data
0: IRQ 7 does not generate requests of moving data
1: IRQ 7 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq6" pos="6" rst="0">
          <comment>state of IRQ 6 generate requests of moving data
0: IRQ 6 does not generate requests of moving data
1: IRQ 6 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq5" pos="5" rst="0">
          <comment>state of IRQ 5 generate requests of moving data
0: IRQ 5 does not generate requests of moving data
1: IRQ 5 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq4" pos="4" rst="0">
          <comment>state of IRQ 4 generate requests of moving data
0: IRQ 4 does not generate requests of moving data
1: IRQ 4 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq3" pos="3" rst="0">
          <comment>state of IRQ 3 generate requests of moving data
0: IRQ 3 does not generate requests of moving data
1: IRQ 3 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq2" pos="2" rst="0">
          <comment>state of IRQ 2 generate requests of moving data
0: IRQ 2 does not generate requests of moving data
1: IRQ 2 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq1" pos="1" rst="0">
          <comment>state of IRQ 1 generate requests of moving data
0: IRQ 1 does not generate requests of moving data
1: IRQ 1 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq0" pos="0" rst="0">
          <comment>state of IRQ 0 generate requests of moving data
0: IRQ 0 does not generate requests of moving data
1: IRQ 0 generate requests of moving data</comment>
        </bits>
      </reg>
      <reg name="axidma_arm_ack_stat" protect="r">
        <bits access="r" name="ack23" pos="23" rst="0">
          <comment>state of ACK 23 generate requests of moving data
0: ACK 23 does not generate requests of moving data
1: ACK 23 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack22" pos="22" rst="0">
          <comment>state of ACK 22 generate requests of moving data
0: ACK 22 does not generate requests of moving data
1: ACK 22 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack21" pos="21" rst="0">
          <comment>state of ACK 21 generate requests of moving data
0: ACK 21 does not generate requests of moving data
1: ACK 21 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack20" pos="20" rst="0">
          <comment>state of ACK 20 generate requests of moving data
0: ACK 20 does not generate requests of moving data
1: ACK 20 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack19" pos="19" rst="0">
          <comment>state of ACK 19 generate requests of moving data
0: ACK 19 does not generate requests of moving data
1: ACK 19 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack18" pos="18" rst="0">
          <comment>state of ACK 18 generate requests of moving data
0: ACK 18 does not generate requests of moving data
1: ACK 18 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack17" pos="17" rst="0">
          <comment>state of ACK 17 generate requests of moving data
0: ACK 17 does not generate requests of moving data
1: ACK 17 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack16" pos="16" rst="0">
          <comment>state of ACK 16 generate requests of moving data
0: ACK 16 does not generate requests of moving data
1: ACK 16 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack15" pos="15" rst="0">
          <comment>state of ACK 15 generate requests of moving data
0: ACK 15 does not generate requests of moving data
1: ACK 15 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack14" pos="14" rst="0">
          <comment>state of ACK 14 generate requests of moving data
0: ACK 14 does not generate requests of moving data
1: ACK 14 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack13" pos="13" rst="0">
          <comment>state of ACK 13 generate requests of moving data
0: ACK 13 does not generate requests of moving data
1: ACK 13 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack12" pos="12" rst="0">
          <comment>state of ACK 12 generate requests of moving data
0: ACK 12 does not generate requests of moving data
1: ACK 12 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack11" pos="11" rst="0">
          <comment>state of ACK 11 generate requests of moving data
0: ACK 11 does not generate requests of moving data
1: ACK 11 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack10" pos="10" rst="0">
          <comment>state of ACK 10 generate requests of moving data
0: ACK 10 does not generate requests of moving data
1: ACK 10 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack9" pos="9" rst="0">
          <comment>state of ACK 9 generate requests of moving data
0: ACK 9 does not generate requests of moving data
1: ACK 7 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack8" pos="8" rst="0">
          <comment>state of ACK 8 generate requests of moving data
0: ACK 8 does not generate requests of moving data
1: ACK 8 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack7" pos="7" rst="0">
          <comment>state of ACK 7 generate requests of moving data
0: ACK 7 does not generate requests of moving data
1: ACK 7 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack6" pos="6" rst="0">
          <comment>state of ACK 6 generate requests of moving data
0: ACK 6 does not generate requests of moving data
1: ACK 6 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack5" pos="5" rst="0">
          <comment>state of ACK 5 generate requests of moving data
0: ACK 5 does not generate requests of moving data
1: ACK 5 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack4" pos="4" rst="0">
          <comment>state of ACK 4 generate requests of moving data
0: ACK 4 does not generate requests of moving data
1: ACK 4 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack3" pos="3" rst="0">
          <comment>state of ACK 3 generate requests of moving data
0: ACK 3 does not generate requests of moving data
1: ACK 3 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack2" pos="2" rst="0">
          <comment>state of ACK 2 generate requests of moving data
0: ACK 2 does not generate requests of moving data
1: ACK 2 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack1" pos="1" rst="0">
          <comment>state of ACK 1 generate requests of moving data
0: ACK 1 does not generate requests of moving data
1: ACK 1 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack0" pos="0" rst="0">
          <comment>state of ACK 0 generate requests of moving data
0: ACK 0 does not generate requests of moving data
1: ACK 0 generate requests of moving data</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="axidma_ch_irq_distr" protect="rw">
        <bits access="rw" name="ch11_irq_en0" pos="11" rst="0">
          <comment>channel 11 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch10_irq_en0" pos="10" rst="0">
          <comment>channel 10 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch9_irq_en0" pos="9" rst="0">
          <comment>channel 9 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch8_irq_en0" pos="8" rst="0">
          <comment>channel 8 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch7_irq_en0" pos="7" rst="0">
          <comment>channel 7 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch6_irq_en0" pos="6" rst="0">
          <comment>channel 6 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch5_irq_en0" pos="5" rst="0">
          <comment>channel 5 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch4_irq_en0" pos="4" rst="0">
          <comment>channel 4 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch3_irq_en0" pos="3" rst="0">
          <comment>channel 3 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch2_irq_en0" pos="2" rst="0">
          <comment>channel 2 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch1_irq_en0" pos="1" rst="0">
          <comment>channel 1 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch0_irq_en0" pos="0" rst="0">
          <comment>channel 0 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
      </reg>
      <hole size="224"/>
      <reg name="axidma_c0_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="0">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="0">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c1_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="1">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="1">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c2_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="2">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="2">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c3_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="3">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="3">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c4_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="4">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="4">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c5_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="5">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="5">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c6_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="6">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="6">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c7_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="7">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="7">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c8_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="8">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="8">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c9_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="9">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="9">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c10_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="10">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="10">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c11_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0:disable
1:enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0:security
1:unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="11">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
......
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="11">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
......
01111: IRQ15 trigger transmission
......
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0:unset
1:set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
......
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="aes.xml">
    <var name="CIOS_RAM_SIZE" value="256*4"/>
    <module category="System" name="AES">
      <reg32 name="dma_ctrl" protect="rw">
        <bits access="rw" name="fix_src" pos="0" rst="0x00">
          <comment>1 - fix src address
            0 - increament src address</comment>
        </bits>
        <bits access="rw" name="fix_dst" pos="1" rst="0x00">
          <comment>1 - fix dst address
            0 - increament dst address</comment>
        </bits>
        <bits access="rw" name="hsizem" pos="4:2" rst="0x00">
          <comment>0 - 1 byte
            1 - 2 byte
            2 - 4 byte</comment>
        </bits>
        <bits access="rw" name="cycle2_3" pos="5" rst="0x00">
          <comment>write cycles</comment>
        </bits>
        <bits access="rw" name="crc_ce_ctrl" pos="30:28" rst="0x00">
          <comment>0 - normal dma mode
            1 - dma aes encode mode
            5 - dma aes decode mode
            2 - dma crc mode</comment>
        </bits>
      </reg32>
      <reg32 name="dma_src" protect="rw">
        <bits access="rw" name="src_addr" pos="31:0" rst="0x00">
          <comment>source dma address</comment>
        </bits>
      </reg32>
      <reg32 name="dma_dst" protect="rw">
        <bits access="rw" name="dst_addr" pos="31:0" rst="0x00">
          <comment>destination dma address</comment>
        </bits>
      </reg32>
      <reg32 name="dma_len" protect="rw">
        <bits access="rw" name="length" pos="17:0" rst="0x3ffff">
          <comment>number of hsizem</comment>
        </bits>
      </reg32>
      <reg32 name="crc_gen" protect="rw">
        <bits access="rw" name="crc_poly" pos="31:0" rst="0x04c11db7">
          <comment>crc generator, MSB aligned</comment>
        </bits>
      </reg32>
      <reg32 name="dma_func_ctrl" protect="rw">
        <bits access="rw" name="crc_gen_len" pos="1:0" rst="0x3">
          <comment>--no-use 0 - crc8 1 - crc16 3 - crc32</comment>
        </bits>
        <bits access="rw" name="crc_ctrl" pos="19:16" rst="0x00">
          <comment>bit0 - input byte reverse
            bit1 - input bit reverse
            bit2 - output byte reverse
            bit3 - output bit reverse</comment>
        </bits>
        <bits access="rw" name="aes_eng_cgen" pos="24" rst="0x00">
          <comment>aes engine clk on</comment>
        </bits>
        <bits access="rw" name="aes_keygen_cgen" pos="25" rst="0x00">
          <comment>aes key generator clk on</comment>
        </bits>
        <bits access="rw" name="crc_cgen" pos="28" rst="0x00">
          <comment>crc engine clk on</comment>
        </bits>
        <bits access="rw" name="trng_cgen" pos="30" rst="0x00">
          <comment>trng engine clk on</comment>
        </bits>
      </reg32>
      <reg32 name="aes_key0" protect="rw">
        <bits access="rw" name="key0" pos="31:0" rst="0x00">
          <comment>aes key bit 31:0</comment>
        </bits>
      </reg32>
      <reg32 name="aes_key1" protect="rw">
        <bits access="rw" name="key1" pos="31:0" rst="0x00">
          <comment>aes key bit 63:32</comment>
        </bits>
      </reg32>
      <reg32 name="aes_key2" protect="rw">
        <bits access="rw" name="key2" pos="31:0" rst="0x00">
          <comment>aes key bit 95:64</comment>
        </bits>
      </reg32>
      <reg32 name="aes_key3" protect="rw">
        <bits access="rw" name="key3" pos="31:0" rst="0x00">
          <comment>aes key bit 127:96</comment>
        </bits>
      </reg32>
      <reg32 name="aes_iv0" protect="rw">
        <bits access="rw" name="iv0" pos="31:0" rst="0x00">
          <comment>aes iv bit 31:0</comment>
        </bits>
      </reg32>
      <reg32 name="aes_iv1" protect="rw">
        <bits access="rw" name="iv1" pos="31:0" rst="0x00">
          <comment>aes iv bit 63:32</comment>
        </bits>
      </reg32>
      <reg32 name="aes_iv2" protect="rw">
        <bits access="rw" name="iv2" pos="31:0" rst="0x00">
          <comment>aes iv bit 95:64</comment>
        </bits>
      </reg32>
      <reg32 name="aes_iv3" protect="rw">
        <bits access="rw" name="iv3" pos="31:0" rst="0x00">
          <comment>aes iv bit 127:96</comment>
        </bits>
      </reg32>
      <reg32 name="aes_mode" protect="rw">
        <bits access="rw" name="mode" pos="0" rst="0x00">
          <comment>1 - CBC mode
            0 - ECB mode</comment>
        </bits>
        <bits access="rw" name="key_start" pos="1" rst="0x00">
          <comment>1 - start aes key calc
            0 - after start calc, need written to 0</comment>
        </bits>
        <bits access="rw" name="key_start_mode" pos="2" rst="0x00">
          <comment>1 - aes key calc started by every 32bit key change
            0 - aes key calc started by mode[1] :default</comment>
        </bits>
      </reg32>
      <reg32 name="cios_ctrl" protect="rw">
        <bits access="rw" name="cios_ram_en" pos="0" rst="0x00">
          <comment>Not used. The mac rd/wr fifo mem used by cios</comment>
        </bits>
        <bits access="rw" name="cios_mode" pos="3:1" rst="0x00">
          <comment>0: 3'b000 - 1k 28bit mode
            4: 3'b100 - 2k 28bit mode
            1: 3'b001 - 1k 31bit mode
            5: 3'b101 - 2k 31bit mode
            2: 3'b010 - 1k 32bit mode
            6: 3'b110 - 2k 32bit mode</comment>
        </bits>
        <bits access="rw" name="cios_force_ram" pos="4" rst="0x00">
          <comment>1 - cios ram can be accessed only by ahb bus
            0 - when cios ram input data completely writed by bus, then accessed by cios engine
                when engine accessed completely, then accessed by bus</comment>
        </bits>
        <bits access="rw" name="cios_clk_en" pos="5" rst="0x0">
          <comment>cios clk on</comment>
        </bits>
        <bits access="rw" name="cios_start_mode" pos="6" rst="0x0">
          <comment>0 - cios start by cios_ctrl[7]
            1 - cios auto start when mod_N load done.</comment>
        </bits>
        <bits access="rw" name="cios_start_compute" pos="7" rst="0x0">
          <comment>1 - write 1'b1 to start cios compute.
            0 - after start compute, need written to 0</comment>
        </bits>
      </reg32>
      <reg32 name="cios_reg0" protect="rw">
        <bits access="rw" name="cios_reg0" pos="31:0" rst="0x00">
          <comment>cios reg</comment>
        </bits>
      </reg32>
      <reg32 name="crc_init_val" protect="rw">
        <bits access="rw" name="crc_init" pos="31:0" rst="0x00000000">
          <comment>crc initial value, MSB aligned</comment>
        </bits>
      </reg32>
      <reg32 name="crc_out_xorval" protect="rw">
        <bits access="rw" name="crc_xorval" pos="31:0" rst="0x00">
          <comment>crc output value xored value, LSB aligned</comment>
        </bits>
      </reg32>
      <reg32 name="crc_out_val" protect="rw">
        <bits access="RO" name="crc_out" pos="31:0" rst="0x00">
          <comment>crc output value, LSB aligned</comment>
        </bits>
      </reg32>
      <reg32 name="crc_size_val" protect="rw">
        <bits access="rw" name="crc_size" pos="2:0" rst="0x2">
          <comment>crc size:
            3'd0 - 8bit crc
            3'd1 - 16bit crc
            3'd2 - 32bit crc</comment>
        </bits>
      </reg32>
      <reg32 name="ififo_thr" protect="rw">
        <bits access="rw" name="ififo_rd_low_thr" pos="6:0" rst="0x4">
          <comment>low threshold to trigger ififo read from ahb</comment>
        </bits>
        <bits access="rw" name="ififo_rd_hight_thr" pos="14:8" rst="0x37">
          <comment>high threshold to switch ififo read to ofifo write</comment>
        </bits>
      </reg32>
      <reg32 name="ofifo_thr" protect="rw">
        <bits access="rw" name="ofifo_wr_low_thr" pos="6:0" rst="0x4">
          <comment>low threshold to switch ofifo write to ififo read</comment>
        </bits>
        <bits access="rw" name="ofifo_wr_hight_thr" pos="14:8" rst="0x37">
          <comment>high threshold to trigger ofifo write to ahb</comment>
        </bits>
      </reg32>
      <hole size="9*32"/>
      <reg32 name="dma_int_out" protect="rw">
        <bits access="RO" name="int_out" pos="5:0" rst="0x00">
          <comment>interrupt output, write 1 for clear
            bit0 - ahb dma done
            bit1 - prng alert
            bit2 - trng on fly test failed
            bit3 - trng start test failed
            bit4 - trng data ready
            bit5 - cios done</comment>
        </bits>
      </reg32>
      <reg32 name="dma_int_mask" protect="rw">
        <bits access="rw" name="int_mask" pos="5:0" rst="0x00">
          <comment>interrupt mask, 1 for disable interrapt
            bit0 - ahb dma done
            bit1 - prng alert
            bit2 - trng on fly test failed
            bit3 - trng start test failed
            bit4 - trng data ready
            bit5 - cios done</comment>
        </bits>
      </reg32>
      <hole size="30*32"/>
      <reg32 name="trng_ctrl" protect="rw">
        <bits access="rw" name="trng_ctrl" pos="6:0" rst="0x0c">
          <comment>bit0 - trng enable
            bit1 - trng mode, 1 for continualy mode, 0 for once
            bit2 - trng start test enable
            bit3 - trng on fly test enable
            bit4 - trng source open
            bit5 - trng test enable
            bit6 - trng data mask enable</comment>
        </bits>
        <bits access="rw" name="trng_mask" pos="23:16" rst="0x00">
          <comment>trng source mask</comment>
        </bits>
      </reg32>
      <reg32 name="prng_ctrl" protect="rw">
        <bits access="rw" name="prng_ctrl" pos="3:0" rst="0x00">
          <comment>bit0 - prng enable
            bit1 - prng seed load
            bit2 - prng seed mode
            bit3 - prng timer enable</comment>
        </bits>
      </reg32>
      <reg32 name="prng_seed" protect="rw">
        <bits access="rw" name="prng_seed" pos="31:0" rst="0x00">
          <comment>prng seed</comment>
        </bits>
      </reg32>
      <reg32 name="prng_timer_init" protect="rw">
        <bits access="rw" name="prng_init" pos="31:1" rst="0x00">
          <comment>prng timer initial value * 2</comment>
        </bits>
        <bits access="rw" name="prng_clk_sel" pos="0" rst="0x00">
          <comment>0 - use 40m/32=1.25MHz clk to sample input data
            1 - use dma clk to sample input data</comment>
        </bits>
      </reg32>
      <reg32 name="prng_timer" protect="rw">
        <bits access="RO" name="prng_timer" pos="31:0" rst="0x00">
          <comment>prng timer value</comment>
        </bits>
      </reg32>
      <reg32 name="trng_data0" protect="rw">
        <bits access="RO" name="trng_data0" pos="31:0" rst="0x00">
          <comment>trng data0</comment>
        </bits>
      </reg32>
      <reg32 name="trng_data0_mask" protect="rw">
        <bits access="RO" name="trng_data0_mask" pos="31:0" rst="0x00">
          <comment>trng data0 mask</comment>
        </bits>
      </reg32>
      <reg32 name="trng_data1" protect="rw">
        <bits access="RO" name="trng_data1" pos="31:0" rst="0x00">
          <comment>trng data1</comment>
        </bits>
      </reg32>
      <reg32 name="trng_data1_mask" protect="rw">
        <bits access="RO" name="trng_data1_mask" pos="31:0" rst="0x00">
          <comment>trng data1 mask</comment>
        </bits>
      </reg32>
      <reg32 name="prng_data" protect="rw">
        <bits access="RO" name="prng_data" pos="31:0" rst="0x00">
          <comment>prng data</comment>
        </bits>
      </reg32>
      <reg32 name="trng_hc" protect="rw">
        <bits access="RO" name="trng_c_value" pos="15:0" rst="0x00">
          <comment>trng c value</comment>
        </bits>
        <bits access="RO" name="trng_h_value" pos="31:16" rst="0x01e0">
          <comment>trng h value</comment>
        </bits>
      </reg32>
      <hole size="181*32"/>
      <reg32 name="sha_command" protect="rw">
        <bits access="rw" name="sha_start" pos="0" rst="0x00">
          <comment>When written to a one, the calculation starts. The complete and complete error bits
          are cleared when this bit is written with a one.</comment>
        </bits>
        <bits access="RO" name="sha_complete" pos="1" rst="0x00">
          <comment>Set to a one when the operation has completed.</comment>
        </bits>
        <bits access="rw" name="sha_message_end" pos="2" rst="0x00">
          <comment>When set, the block of data described by MESSAGE_ADDR and MESSAGE_LENGTH includes the end byte of the message.</comment>
        </bits>
        <bits access="rw" name="sha_message_start" pos="3" rst="0x00">
          <comment>When set, the block of data described by MESSAGE_ADDR and MESSAGE_LENGTH includes the starting byte of the message</comment>
        </bits>
        <bits access="rw" name="sha_algorithm" pos="7:4" rst="0x00">
          <comment>0x0       - SHA256 processing
          0x1       - SHA1 processing
          0x2 ~ 0xF - SHA1 processing</comment>
        </bits>
        <bits access="rw" name="sha_int_on_completion" pos="8" rst="0x00">
          <comment>If set, and interrupt will be generated upon completion of message processing.</comment>
        </bits>
        <bits access="rw" name="sha_msg_endian_mode" pos="9" rst="0x00">
          <comment>Swaps intra-word byte order of message words. If set byte addressing is Big Endian.</comment>
        </bits>
        <bits access="rw" name="sha_hash_endian_mode" pos="10" rst="0x00">
          <comment>Swaps intra-word byte order of hash values. If set byte addressing is Big Endian.</comment>
        </bits>
        <bits access="RO" name="sha_rev_16_11" pos="16:11" rst="0x00">
          <comment>Reserved.</comment>
        </bits>
        <bits access="RO" name="sha_illegal_len" pos="17" rst="0x00">
          <comment>The Command register was written with start=1 when the Message Length register held an illegal value.
          No calculation was executed.</comment>
        </bits>
        <bits access="RO" name="sha_rev_31_18" pos="31:18" rst="0x00">
          <comment>Reserved.</comment>
        </bits>
      </reg32>
      <reg32 name="sha_message_addr" protect="rw">
        <bits access="rw" name="sha_message_addr" pos="31:0" rst="0x00">
          <comment>Starting Byte address of the message block in memory.</comment>
        </bits>
      </reg32>
      <reg32 name="sha_message_len" protect="rw">
        <bits access="rw" name="sha_message_len" pos="18:0" rst="0x00">
          <comment>Byte Length of Message. Maximum of 256K - Message Address[1:0].</comment>
        </bits>
      </reg32>
      <reg32 name="sha_rd_counter" protect="rw">
        <bits access="RO" name="sha_rd_counter" pos="15:0" rst="0x00">
          <comment>HW state. Used for debug only. Umac Interface rd_counter.</comment>
        </bits>
      </reg32>
      <reg32 name="sha_wr_counter" protect="rw">
        <bits access="RO" name="sha_wr_counter" pos="15:0" rst="0x00">
          <comment>HW state. Used for debug only. Umac Interface wr_counter.</comment>
        </bits>
      </reg32>
      <reg32 name="sha_umac_state_c" protect="rw">
        <bits access="RO" name="sha_umac_state_c" pos="1:0" rst="0x00">
          <comment>HW state. Used for debug only. Umac Interface umac_state_c.</comment>
        </bits>
      </reg32>
      <reg32 name="sha_state_c" protect="rw">
        <bits access="RO" name="sha_state_c" pos="2:0" rst="0x00">
          <comment>HW state. Used for debug only. Umac Interface sha_state_c.</comment>
        </bits>
      </reg32>
      <hole size="6*32"/>
      <reg32 name="sha_int_clr" protect="rw">
        <bits access="rw" name="sha_int_clr" pos="0" rst="0x00">
          <comment>Write 1 to the bit to clear the Interrupt</comment>
        </bits>
      </reg32>
      <reg32 name="sha_int_en" protect="rw">
        <bits access="rw" name="sha_int_en" pos="0" rst="0x00">
          <comment>Write 1 to the bit to enable SHA Interrupt</comment>
        </bits>
      </reg32>
      <reg32 name="sha_int_status" protect="rw">
        <bits access="RO" name="sha_int_status" pos="0" rst="0x00">
          <comment>SAM Interrupt status</comment>
        </bits>
      </reg32>
      <reg32 name="sha_restart" protect="rw">
        <bits access="rw" name="sha_restart" pos="0" rst="0x1">
          <comment>Write 1 to restart SHA module</comment>
        </bits>
      </reg32>
      <hole size="47*32"/>
      <reg32 name="hash_value_0" protect="rw">
        <bits access="rw" name="hash_value_0" pos="31:0" rst="0x00">
          <comment>SHA Hash Values. The resulting message digest is the concatenation of H0.</comment>
        </bits>
      </reg32>
      <reg32 name="hash_value_1" protect="rw">
        <bits access="rw" name="hash_value_1" pos="31:0" rst="0x00">
          <comment>SHA Hash Values. The resulting message digest is the concatenation of H1.</comment>
        </bits>
      </reg32>
      <reg32 name="hash_value_2" protect="rw">
        <bits access="rw" name="hash_value_2" pos="31:0" rst="0x00">
          <comment>SHA Hash Values. The resulting message digest is the concatenation of H2.</comment>
        </bits>
      </reg32>
      <reg32 name="hash_value_3" protect="rw">
        <bits access="rw" name="hash_value_3" pos="31:0" rst="0x00">
          <comment>SHA Hash Values. The resulting message digest is the concatenation of H3.</comment>
        </bits>
      </reg32>
      <reg32 name="hash_value_4" protect="rw">
        <bits access="rw" name="hash_value_4" pos="31:0" rst="0x00">
          <comment>SHA Hash Values. The resulting message digest is the concatenation of H4.</comment>
        </bits>
      </reg32>
      <reg32 name="hash_value_5" protect="rw">
        <bits access="rw" name="hash_value_5" pos="31:0" rst="0x00">
          <comment>SHA Hash Values. The resulting message digest is the concatenation of H5.</comment>
        </bits>
      </reg32>
      <reg32 name="hash_value_6" protect="rw">
        <bits access="rw" name="hash_value_6" pos="31:0" rst="0x00">
          <comment>SHA Hash Values. The resulting message digest is the concatenation of H6.</comment>
        </bits>
      </reg32>
      <reg32 name="hash_value_7" protect="rw">
        <bits access="rw" name="hash_value_7" pos="31:0" rst="0x00">
          <comment>SHA Hash Values. The resulting message digest is the concatenation of H7.</comment>
        </bits>
      </reg32>
      <hole size="8*32"/>
      <reg32 name="sha_byte_count" protect="rw">
        <bits access="rw" name="sha_byte_count" pos="28:0" rst="0x00">
          <comment>Number of Message bytes processed. Maximum of 0x1FFF_FFFF.
          Read for status or to save context.
          Written to restore context.</comment>
        </bits>
      </reg32>
      <hole size="175*32"/>
      <memory name="cios_local_ram" size="CIOS_RAM_SIZE">
        <comment>
          CIOS RAM Space
          <br/>
           Used for CIOS Only.
        </comment>
      </memory>
    </module>
  </archive>
  <archive relative="lzma.xml">
    <module category="System" name="LZMA">
      <reg name="lzma_cmd_reg" protect="rw">
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>Writing 1 starts block decode</comment>
        </bits>
      </reg>
      <reg name="lzma_status_reg" protect="rw">
        <bits access="rw" name="axi_err" pos="2" rst="0">
          <comment>AXI bus error flag. Reading 1 indicates AXI bus operation fails and Lzma should be reset.</comment>
        </bits>
        <bits access="rw" name="dec_err" pos="1" rst="0">
          <comment>Decode error flag. Reading 1 indicates block decode error and Lzma should be reset.</comment>
        </bits>
        <bits access="rw" name="dec_done" pos="0" rst="0">
          <comment>Decode done flag. Reading 1 indicates block decode done, writing 1 clears.</comment>
        </bits>
      </reg>
      <reg name="lzma_irq_mask" protect="rw">
        <bits access="rw" name="axi_errirqmask" pos="2" rst="0">
          <comment>Writing 1 indicates a interrupt will be generated when lzma_status_reg[2]=1</comment>
        </bits>
        <bits access="rw" name="dec_errirqmask" pos="1" rst="0">
          <comment>Writing 1 indicates a interrupt will be generated when lzma_status_reg[1]=1</comment>
        </bits>
        <bits access="rw" name="dec_doneirqmask" pos="0" rst="0">
          <comment>Writing 1 indicates a interrupt will be generated when lzma_status_reg[0]=1</comment>
        </bits>
      </reg>
      <reg name="reserve0" protect="r">
      </reg>
      <reg name="lzma_config_reg1" protect="rw">
        <bits access="rw" name="reg_dict_size" pos="29:17" rst="0">
          <comment>Lzma dictionary size in byte</comment>
        </bits>
        <bits access="rw" name="reg_block_size" pos="16:0" rst="0">
          <comment>lzma block size in byte</comment>
        </bits>
      </reg>
      <reg name="lzma_config_reg2" protect="rw">
        <bits access="rw" name="reg_stream_len" pos="16:0" rst="0">
          <comment>lzma zip stream lenght in byte</comment>
        </bits>
      </reg>
      <reg name="lzma_config_reg3" protect="rw">
        <bits access="rw" name="reg_refbyte_en" pos="2" rst="0">
          <comment>1: refbyte enable; 0: refbyte disable</comment>
        </bits>
        <bits access="rw" name="reg_cabac_movebits" pos="1" rst="0">
          <comment>1: cabac_movebits=5; 0: cabac_movebits=4</comment>
        </bits>
        <bits access="rw" name="reg_cabac_totalbits" pos="0" rst="0">
          <comment>1: cabac_totalbits=11; 0: cabac_totalbits=10</comment>
        </bits>
      </reg>
      <reg name="lzma_status_reg2" protect="r">
        <bits access="r" name="stream_byte_pos" pos="16:0" rst="0">
          <comment>current decoding byte position in zip stream</comment>
        </bits>
      </reg>
      <reg name="lzma_status_reg3" protect="r">
        <bits access="r" name="dict_byte_pos" pos="16:0" rst="0">
          <comment>current recovering byte position in dictionary</comment>
        </bits>
      </reg>
      <reg name="lzma_error_type" protect="r">
        <bits access="r" name="inbuf_underflow" pos="6" rst="0">
          <comment>Equals to 1 when block decode finishes with zip stream reading byte position less than (reg_stream_len-2)</comment>
        </bits>
        <bits access="r" name="outbuf_overflow" pos="5" rst="0">
          <comment>Equals to 1 when block decode finishes with block buffer writing byte position exceeds the block size</comment>
        </bits>
        <bits access="r" name="symbol_len_err" pos="4" rst="0">
          <comment>Equals to 1 when a symbol is decoded as match type with length more than 273</comment>
        </bits>
        <bits access="r" name="symbol_reps_err0" pos="3" rst="0">
          <comment>Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary size</comment>
        </bits>
        <bits access="r" name="symbol_reps_err1" pos="2" rst="0">
          <comment>Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary recovery byte postion</comment>
        </bits>
        <bits access="r" name="symbol_type_err" pos="1" rst="0">
          <comment>Equals to 1 when first symbol in a block is decoded as match type</comment>
        </bits>
        <bits access="r" name="inbuf_overflow" pos="0" rst="0">
          <comment>Equals to 1 when zip stream reading byte position exceeds the stream length</comment>
        </bits>
      </reg>
      <reg name="reserve1" protect="r">
      </reg>
      <reg name="reserve2" protect="r">
      </reg>
      <reg name="lzma_input_crc" protect="r">
        <bits access="r" name="input_crc" pos="31:0" rst="0">
          <comment>Crc of lzma rdma read bytes</comment>
        </bits>
      </reg>
      <reg name="lzma_output_crc" protect="r">
        <bits access="r" name="output_crc" pos="31:0" rst="0">
          <comment>Crc of lzma wdma write bytes</comment>
        </bits>
      </reg>
      <reg name="reserve3" protect="r">
      </reg>
      <reg name="reserve4" protect="r">
      </reg>
      <reg name="lzma_dma_raddr_reg" protect="rw">
        <bits access="rw" name="dma_raddr_reg" pos="31:0" rst="0">
          <comment>Base address of lzma rdma</comment>
        </bits>
      </reg>
      <reg name="lzma_dma_waddr_reg" protect="rw">
        <bits access="rw" name="dma_waddr_reg" pos="31:0" rst="0">
          <comment>Base address of lzma wdma</comment>
        </bits>
      </reg>
      <reg name="lzma_inbuf_rwmargin_reg" protect="rw">
        <bits access="rw" name="inbuf_rwmargin_reg" pos="5:0" rst="10">
          <comment>Set the margin between input_buf wrptr and rdptr for pending the decode process</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="f8.xml">
    <module category="System" name="F8">
      <reg name="f8_conf" protect="rw">
        <bits access="rw" name="f8_ar_sel" pos="3:2" rst="0">
          <comment>F8
00
01AES
10snow3G
11zuc</comment>
        </bits>
        <bits access="rw" name="f8_irq_en" pos="1" rst="0">
          <comment>F8
0F8 /group
1F8 /group</comment>
        </bits>
        <bits access="rw" name="f8_start" pos="0" rst="0">
          <comment>F8
0F8
1F8</comment>
        </bits>
      </reg>
      <reg name="f8_group_addr" protect="rw">
        <bits access="rw" name="group_addr" pos="31:0" rst="0">
          <comment>group</comment>
        </bits>
      </reg>
      <reg name="f8_group_cnt" protect="rw">
        <bits access="rw" name="group_addr" pos="31:0" rst="0">
          <comment>group</comment>
        </bits>
      </reg>
      <reg name="f8_status" protect="rw">
        <bits access="rc" name="f9_stat" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          0F9
1F9</comment>
        </bits>
        <bits access="rc" name="f8_stat" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          0F8/
1F8/</comment>
        </bits>
      </reg>
      <reg name="f9_conf" protect="rw">
        <bits access="rw" name="f9_ar_sel" pos="3:2" rst="0">
          <comment>F9
00AES
01AES
10snow3G
11zuc</comment>
        </bits>
        <bits access="rw" name="f9_irq_en" pos="1" rst="0">
          <comment>F9
0F9 /group
1F9 /group</comment>
        </bits>
        <bits access="rw" name="f9_start" pos="0" rst="0">
          <comment>F9
0F9
1F9</comment>
        </bits>
      </reg>
      <reg name="f9_group_addr" protect="rw">
        <bits access="rw" name="f9_addr" pos="31:0" rst="0">
          <comment>F9 group</comment>
        </bits>
      </reg>
      <reg name="f9_result" protect="r">
        <bits access="r" name="f9_mac" pos="31:0" rst="0">
          <comment>F9</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="fpi3_gprs.xml">
    <module category="System" name="FPI3_GPRS">
      <reg name="gprs_clc" protect="rw">
        <bits access="rw" name="fsoe" pos="5" rst="0">
          <comment>FSOE</comment>
        </bits>
        <bits access="w" name="sbwe" pos="4" rst="0">
          <comment>SBWE</comment>
        </bits>
        <bits access="rw" name="edis" pos="3" rst="0">
          <comment>EDIS</comment>
        </bits>
        <bits access="rw" name="spen" pos="2" rst="0">
          <comment>SPEN</comment>
        </bits>
        <bits access="r" name="diss" pos="1" rst="1">
          <comment>DISS</comment>
        </bits>
        <bits access="rw" name="disr" pos="0" rst="1">
          <comment>DISR</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="gprs_id" protect="r">
        <bits access="r" name="mod_number" pos="31:16" rst="61443">
          <comment>MOD_NUMBER = F003H</comment>
        </bits>
        <bits access="r" name="rev_number" pos="7:0" rst="32">
          <comment>REV_NUMBER = 20H</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="gprs_data" protect="rw">
        <bits access="rw" name="data" pos="31:0" rst="0">
          <comment>Data Register (Bus address of buffer-32 GPRS_DATA registers are building the on-chip FIFO-buffer)</comment>
        </bits>
      </reg>
      <reg name="gprs_stat" protect="rw">
        <bits access="r" name="ofl_stat" pos="31" rst="0">
          <comment>Overflow Status
Set to 1 by the GPRS unit when an overflow of the buffer occurs.
Can be reset by writing '0' to bit UFL.</comment>
        </bits>
        <bits access="r" name="ufl_stat" pos="23" rst="0">
          <comment>Underflow Status
Set to 1 by the GPRS unit when an underflow of the buffer occurs.
Can be reset by writing '0' to bit UFL.</comment>
        </bits>
        <bits access="w" name="ofl" pos="15" rst="0">
          <comment>Overflow
By writing '0' to this bit, bit OFL_STAT will be reset. The current
overflow status can be read via bit OFL_STAT.</comment>
        </bits>
        <bits access="r" name="wr" pos="13:8" rst="32">
          <comment>Write
Describes the number of on-chip buffer blocks which are free to be written by the microcontroller.
Note: If the XOR-combination is disabled by setting bit XOR_DIS in CTRL and ciphering is switched on by setting bit CIPH_CTRL in CTRL this bitfield is set to 0x00.</comment>
        </bits>
        <bits access="w" name="ufl" pos="7" rst="0">
          <comment>Underflow
By writing '0' to this bit, bit UFL_STAT will be reset. The current underflow status can be read via bit UFL_STAT.</comment>
        </bits>
        <bits access="r" name="rd" pos="5:0" rst="0">
          <comment>Read
Describes the number of on-chip buffer blocks which have already been processed by the GPRS unit. These blocks can be read by the microcontroller.</comment>
        </bits>
      </reg>
      <reg name="gprs_mac" protect="r">
        <bits access="r" name="mac_i" pos="31:0" rst="0">
          <comment>MAC-I Bits [31:0]</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="gprs_bccc" protect="w">
        <bits access="w" name="ciph_bcctrl" pos="19" rst="0">
          <comment>CIPH_CTRL Value for the Actual Block in Byte Count Mode
0 Ciphering switched off
1 Ciphering switched on
This bit is only valid for BC_EN = &quot;1&quot; (Byte count enabled)!</comment>
        </bits>
        <bits access="w" name="crc_bcctrl" pos="18" rst="0">
          <comment>CRC_CTRL Value for Actual Block in Byte Count Mode
0 CRC calculation switched off, necessery for unprotected data stream
1 CRC calculation switched on
This bit is only valid for BC_EN = &quot;1&quot; (Byte count enabled)!</comment>
        </bits>
        <bits access="w" name="cnt_val" pos="10:0" rst="0">
          <comment>Byte Counter Value
Number of Bytes for the actual block.
Only valid if BC_EN = &quot;1&quot;!</comment>
        </bits>
      </reg>
      <reg name="gprs_poly" protect="rw">
        <bits access="rw" name="polynomial" pos="31:0" rst="0">
          <comment>Polynomial Bits [31:0]</comment>
        </bits>
      </reg>
      <reg name="gprs_fcs" protect="rw">
        <bits access="rw" name="fcs" pos="31:0" rst="0">
          <comment>FCS Bits [31:0]</comment>
        </bits>
      </reg>
      <reg name="gprs_fresh" protect="rw">
        <bits access="rw" name="fresh" pos="31:0" rst="0">
          <comment>FRESH Bits [31:0]</comment>
        </bits>
      </reg>
      <reg name="gprs_kc0" protect="rw">
        <bits access="rw" name="kc0" pos="31:0" rst="0">
          <comment>KC0 Bits [31:0]
GEA1/2: Cipher key.
GEA3/f8: Input CK to the core function KGCORE (see
Section 4.3.9).
f9: Integrity key IK.</comment>
        </bits>
      </reg>
      <reg name="gprs_kc1" protect="rw">
        <bits access="rw" name="kc1" pos="31:0" rst="0">
          <comment>KC1 Bits [31:0]
GEA1/2: Cipher key.
GEA3/UMTS: Input CK to the core function KGCORE (see Section 4.3.9).
f9: Integrity key IK.</comment>
        </bits>
      </reg>
      <reg name="gprs_kc2" protect="rw">
        <bits access="rw" name="kc2" pos="31:0" rst="0">
          <comment>KC2 Bits [31:0]
GEA1/2: Cipher key.
GEA3/UMTS: Input CK to the core function KGCORE (see Section 4.3.9).
f9: Integrity key IK.</comment>
        </bits>
      </reg>
      <reg name="gprs_kc3" protect="rw">
        <bits access="rw" name="kc3" pos="31:0" rst="0">
          <comment>KC3 Bits [31:0]
GEA1/2: Cipher key.
GEA3/UMTS: Input CK to the core function KGCORE (see Section 4.3.9).
f9: Integrity key IK.</comment>
        </bits>
      </reg>
      <reg name="gprs_input" protect="rw">
        <bits access="rw" name="input" pos="31:0" rst="0">
          <comment>Input Key Bits [31:0]
GEA1/2: Input key for initialization.
GEA3/f8: Input CC[31:0] to the core function KGCORE (see Section 4.3.9).
f9: Frame dependent input Count-I[31:0].</comment>
        </bits>
      </reg>
      <reg name="gprs_gea3" protect="rw">
        <bits access="rw" name="cb" pos="31:27" rst="0">
          <comment>CB
Input CB[4:0] to the core function KGCORE (see Section 4.3.9).</comment>
        </bits>
        <bits access="rw" name="cd" pos="26" rst="0">
          <comment>CD
Input CD[0] to the core function KGCORE (see Section 4.3.9).
Note: For f8 and f9 calculation, this bit refers to the input
DIRECTION.</comment>
        </bits>
        <bits access="rw" name="ca" pos="23:16" rst="0">
          <comment>Input CA[7:0]
To the core function KGCORE (see Section 4.3.9).</comment>
        </bits>
        <bits access="rw" name="ce" pos="15:0" rst="0">
          <comment>Input CE[15:0]
To the core function KGCORE (see Section 4.3.9).</comment>
        </bits>
      </reg>
      <reg name="gprs_length" protect="rw">
        <bits access="rw" name="length" pos="31:0" rst="0">
          <comment>Length Bits [31:0]
Total number of bits of the input/output bit stream.</comment>
        </bits>
      </reg>
      <reg name="gprs_ctrl" protect="rw">
        <bits access="r" name="f9cal_stat" pos="30" rst="0">
          <comment>F9CAL Status
This bit is set by writing to bit F9CAL and reset by the GPRS block when the f9 calculation has finished.
After this bit is reset by the GPRS block, the MAC can be read by the CPU.
0 F9 calculation finished.
1 F9 calculation ongoing.</comment>
        </bits>
        <bits access="rw" name="offset" pos="28:24" rst="0">
          <comment>Offset
Indicates the size of the header part to be discarded for UMTS f8</comment>
        </bits>
        <bits access="r" name="int_stat" pos="22" rst="0">
          <comment>Initilisation Status
This bit is only valid for MIN_INT=&quot;1&quot;!
This bit is set by writing to bit INT_EN and reset by the GPRS block.
0 GPRS_INT0 generation not enabled.
1 GPRS_INT0 generation enabled.</comment>
        </bits>
        <bits access="rw" name="xor_dis" pos="21" rst="0">
          <comment>XOR Disable
By setting this bit, the XOR combination of input data and keystream will be omitted. This bit is valid only for f8 ciphering.
0 XOR combination enabled.
If CIPH_CTRL = '0' the GPRS unit can be used DMA copy with bit-shifting. Data register DATA is used for writing the input bit stream.
1 XOR combination disabled.
If CIPH_CTRL = '1' no input bit stream has to be written to the data register DATA. The produced keystream can be read from register DATA.
Note: This bit in combination with CIPH_CTRL has effect on the DMA BUFIN request generation (see Table 18 and Table 19)</comment>
        </bits>
        <bits access="rw" name="gea3_umts" pos="20" rst="0">
          <comment>GEA3 UMTS Mode
0 GEA3 or UMTS mode not enabled (default). GEA1 or GEA2 mode will be used according to the settings in bit MODE.
1 GEA3 or UMTS mode enabled. GEA3/UMTS f8 or UMTS f9 will be used according to the settings in bit MODE.
Note: For GEA3 or UTMS f8 mode additionally bit MODE has to be set to '0' . For UMTS f9 mode bit MODE has to be set to '1' (see Table 21).</comment>
        </bits>
        <bits access="r" name="init_stat" pos="16" rst="0">
          <comment>Initilisation Status
This bit is set by writing to bit INIT and reset by the GPRS block. After this bit is reset by the GPRS block, processing of GPRS_DATA is automatically started. During initialisation GPRS_DATA processing is blocked.
0 Initialisation finished.
1 Initialisation ongoing.</comment>
        </bits>
        <bits access="w" name="f9cal" pos="14" rst="0">
          <comment>F9 Calculation Bit
The f9 calculation bit can be set to &quot;1&quot; by the MCU before data for a new f9 calculation is written to the GPRS unit. The status of the f9 calculation can be read via bit F9CAL_STAT.
0 No effect.
1 Start the indicator for f9 operation.</comment>
        </bits>
        <bits access="w" name="fifo_flush" pos="13" rst="0">
          <comment>FIFO Flush
0 No operation (default)
1 Data FIFO DATA is flushed. (This bit need not be reset by software.)</comment>
        </bits>
        <bits access="rw" name="burstsize" pos="12:10" rst="0">
          <comment>Burse Size
000 Burst Size 1 (default)
001 Burst Size 4
010 Burst Size 8
011 Burst Size 16
100 Burst Size 32</comment>
        </bits>
        <bits access="rw" name="bc_en" pos="9" rst="0">
          <comment>Byte Count Enable
0 Byte count feature disabled (default)
1 Byte count feature enabled</comment>
        </bits>
        <bits access="rw" name="bufin_en" pos="8" rst="0">
          <comment>Buffer In Enable
0 GPRS_BUFIN/GPRS_INT1 not generated (default)
1 GPRS_BUFIN/GPRS_INT1 generation if:
WR in STAT &gt;= BURSTSIZE if XOR_DIS = '0' or
The bit counter in UMTS f8 mode has reached the value programmed in register LENGTH if XOR_DIS = '1' and CIPH_CTRL = '1'.For details on programming this bit please check Table 18 and Table 19.</comment>
        </bits>
        <bits access="rw" name="bufout_en" pos="7" rst="0">
          <comment>Buffer Out Enable
This bit is only valid for MIN_INT=&quot;1&quot;!
0 GPRS_BUFOUT not generated (default)
1 GPRS_BUFOUT generation if:
RD in STAT &gt;= BURSTSIZE or  BCCC is worked out (only for BC_EN=&quot;1&quot;) For details on programming this bit please check Table 18.</comment>
        </bits>
        <bits access="rw" name="int_en" pos="6" rst="0">
          <comment>Interrupt Enable
This bit is only valid for MIN_INT=&quot;1&quot;!
The status of this bit can be read via bit INT_STAT.
0 GPRS_INT0 not generated (default)
1 GPRS_INT0 generation if: WR+RD in STAT = 32 (all data in DATA are processed) For details on programming this bit please check Table 18.
Note: This bit must not be set for DMA transfers!</comment>
        </bits>
        <bits access="rw" name="min_int" pos="5" rst="0">
          <comment>Minimized Interrupt
0 Minimized interrupt generation frequency disabled (default)
1 Minimized interrupt generation frequency enabled
For details on programming this bit please check Table 18.</comment>
        </bits>
        <bits access="rw" name="mode" pos="4" rst="0">
          <comment>Mode
0 GEA1 ciphering mode if bit GEA3_UMTS is '0' (default)
1 GEA2 ciphering mode if bit GEA3_UMTS is '0'
Note: This bit performs different if bit GEA3_UMTS is set! In GEA3/UMTS f8 mode this bit must be '0', in UMTS f9 mode '1' (see Table 21).</comment>
        </bits>
        <bits access="rw" name="ciph_ctrl" pos="3" rst="0">
          <comment>Cipher Control
This bit is only valid for BC_EN = &quot;0&quot; (Byte count disabled)!
0 Ciphering switched off
1 Ciphering switched on
Notes:
1. This bit has to be set in all cipher modes (GPRS, UMTS) if the corresponding algorithm (GEA1/2/3, f8) shall be performed!
2. This bit in combination with XOR_DIS has effect on the DMA BUFIN request generation (see Table 18 and Table 19)</comment>
        </bits>
        <bits access="rw" name="crc_ctrl" pos="2" rst="0">
          <comment>CRC Control
This bit is only valid for BC_EN = &quot;0&quot; (Byte count disabled)!
0 CRC calculation switched off, necessary for unprotected data stream
1 CRC calculation switched on
Note: As the CRC was originally implemented for GPRS mode, it is not recommended to use CRC in UMTS  mode!</comment>
        </bits>
        <bits access="rw" name="init_direction" pos="1">
          <comment>Initialisation Bit
The initialisation bit is set to &quot;1&quot; by the MCU.
The status of this bit can be read via bit INIT_STAT
0 No operation
1 Start of initialization Direction
Selects the encoding resp. decoding procedure for GEA1 and GEA2
0 Uplink channel
1 Downlink channel
Note: In the UMTS f8 case this bit also indicates how the bitfield OFFSET operates on the ciphering process.</comment>
        </bits>
      </reg>
      <hole size="1344"/>
      <reg name="gprs_src1" protect="rw">
        <bits access="w" name="setr" pos="15" rst="0">
          <comment>Request Flag Set Bit
0 No action
1 Set request flag SRR (no action if CLRR = 1)
Written value is not stored. Read returns 0.</comment>
        </bits>
        <bits access="w" name="clrr" pos="14" rst="0">
          <comment>Request Flag Clear Bit
0 No action
1 Clear request flag SRR (no action if SETR = 1)
Written value is not stored. Read returns 0.</comment>
        </bits>
        <bits access="r" name="srr" pos="13" rst="0">
          <comment>Service Request Flag
0 No service request pending
1 A service request is pending</comment>
        </bits>
        <bits access="rw" name="sre" pos="12" rst="0">
          <comment>Service Request Enable Control
0 Service request is disabled
1 Service request is enabled</comment>
        </bits>
        <bits access="rw" name="tos" pos="10" rst="0">
          <comment>Type-of-Service Control
0 Request CPU service (Service Provider 0)
1 Request DMA service (Service Provider 1)
Not all SRN can request DMA service. See column DMA Support in Table Interrupt
Source List</comment>
        </bits>
      </reg>
      <reg name="gprs_src0" protect="rw">
        <bits access="w" name="setr" pos="15" rst="0">
          <comment>Request Flag Set Bit
0 No action
1 Set request flag SRR (no action if CLRR = 1)
Written value is not stored. Read returns 0.</comment>
        </bits>
        <bits access="w" name="clrr" pos="14" rst="0">
          <comment>Request Flag Clear Bit
0 No action
1 Clear request flag SRR (no action if SETR = 1)
Written value is not stored. Read returns 0.</comment>
        </bits>
        <bits access="r" name="srr" pos="13" rst="0">
          <comment>Service Request Flag
0 No service request pending
1 A service request is pending</comment>
        </bits>
        <bits access="rw" name="sre" pos="12" rst="0">
          <comment>Service Request Enable Control
0 Service request is disabled
1 Service request is enabled</comment>
        </bits>
        <bits access="rw" name="tos" pos="10" rst="0">
          <comment>Type-of-Service Control
0 Request CPU service (Service Provider 0)
1 Request DMA service (Service Provider 1)
Not all SRN can request DMA service. See column DMA Support in Table Interrupt
Source List</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="gouda.xml">
    <include file="globals.xml"/>
    <module category="System" name="GOUDA">
      <var name="GD_MAX_OUT_WIDTH" value="640"/>
      <comment>Maximum output width in pixels</comment>
      <var name="GD_NB_BITS_LCDPOS" value="11"/>
      <comment>Number of bits coding position in virtual screen</comment>
      <var name="GD_FP_FRAC_SIZE" value="8"/>
      <comment>Number of bits of fractional part of internal fixed point values</comment>
      <var name="GD_FIXEDPOINT_SIZE" value="3+GD_FP_FRAC_SIZE"/>
      <comment>Number of bits of internal fixed point values</comment>
      <var name="GD_NB_BITS_STRIDE" value="13"/>
      <comment>Number of bits for stride storage</comment>
      <var name="GD_MAX_SLCD_READ_LEN" value="4"/>
      <var name="GD_MAX_SLCD_CLK_DIVIDER" value="255"/>
      <reg name="gd_command" protect="rw">
        <bits access="rw" name="start" pos="0" rst="0x0">
          <comment>Starts the image transfer. Autoreset</comment>
        </bits>
      </reg>
      <reg name="gd_status" protect="r">
        <bits access="r" name="ia_busy" pos="0" rst="0x0">
          <comment>High while image accelerator is busy</comment>
        </bits>
        <bits access="r" name="lcd_busy" pos="4" rst="0x0">
          <comment>High while LCD controller is busy</comment>
        </bits>
      </reg>
      <reg name="gd_eof_irq" protect="rc">
        <bits access="rc" name="eof_cause" pos="0" rst="0x0">
          <comment>
            High when End Of Frame IRQ has been generated.
            <br/>
            To clear it, write 1 in this bit or in eof_status.
          </comment>
        </bits>
        <bits access="rc" name="eof_status" pos="16" rst="0x0">
          <comment>
            Unmasked version of eof_cause.
            <br/>
            To clear it, write 1 in this bit or in eof_status.
          </comment>
        </bits>
      </reg>
      <reg name="gd_eof_irq_mask" protect="rw">
        <bits access="rw" name="eof_mask" pos="0" rst="0x0">
          <comment>
            EOF interrupt generation mask:
            <br/>
            0: EOF IRQ disabled
            <br/>
            1: EOF IRQ enabled
          </comment>
        </bits>
      </reg>
      <reg name="gd_roi_tl_ppos" protect="rw">
        <bits access="rw" name="x0" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
          <comment>LCD Region Of Interest Top-Left pixel x-axis</comment>
        </bits>
        <bits access="rw" name="y0" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
          <comment>LCD Region Of Interest Top-Left pixel y-axis</comment>
        </bits>
      </reg>
      <reg name="gd_roi_br_ppos" protect="rw">
        <bits access="rw" name="x1" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
          <comment>LCD Region Of Interest Bottom-Right pixel x-axis</comment>
        </bits>
        <bits access="rw" name="y1" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
          <comment>LCD Region Of Interest Bottom-Right pixel y-axis</comment>
        </bits>
      </reg>
      <reg name="gd_roi_bg_color" protect="rw">
        <bits access="rw" name="b" pos="4:0" rst="0x0">
          <comment>Blue component of the ROI background color</comment>
        </bits>
        <bits access="rw" name="g" pos="10:5" rst="0x0">
          <comment>Green component of the ROI background color</comment>
        </bits>
        <bits access="rw" name="r" pos="15:11" rst="0x0">
          <comment>Red component of the ROI background color</comment>
        </bits>
      </reg>
      <reg name="gd_vl_input_fmt" protect="rw">
        <bits access="rw" name="format" pos="1:0" rst="0x0">
          <comment>
            Input image format
            <br/>
            00b: RGB565 pixel packed
            <br/>
            01b: YUV4:2:2 pixel packed (UYVY)
            <br/>
            10b: YUV4:2:2 pixel packed (YUYV)
            <br/>
            11b: YUV4:2:0 planar (IYUV)
          </comment>
        </bits>
        <bits access="rw" name="stride" pos="GD_NB_BITS_STRIDE+1:2" rst="0x0">
          <comment>
            Image stride in bytes (of Y component for planar formats).
            <br/>
            This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size).
          </comment>
        </bits>
        <bits access="rw" name="active" pos="31" rst="0x0">
          <comment>
            Defines Layer's activity:
            <br/>
            0: Layer disabled
            <br/>
            1: Layer active
          </comment>
        </bits>
      </reg>
      <reg name="gd_vl_tl_ppos" protect="rw">
        <bits access="rw" name="x0" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
          <comment>Video Layer (layer 0) Top-Left pixel x-axis position</comment>
        </bits>
        <bits access="rw" name="y0" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
          <comment>Video Layer (layer 0) Top-Left pixel y-axis position</comment>
        </bits>
      </reg>
      <reg name="gd_vl_br_ppos" protect="rw">
        <bits access="rw" name="x1" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
          <comment>Video Layer (layer 0) Bottom-Right pixel x-axis position</comment>
        </bits>
        <bits access="rw" name="y1" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
          <comment>Video Layer (layer 0) Bottom-Right pixel y-axis position</comment>
        </bits>
      </reg>
      <reg name="gd_vl_extents" protect="rw">
        <bits access="rw" name="max_line" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
          <comment>Number of lines of source image (idem gd_vl_br_ppos.y1 when
                 vertical scaling factor is one).</comment>
        </bits>
        <bits access="rw" name="max_col" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
          <comment>Number of columns of source image (idem gd_vl_br_ppos.x1 when
                 vertical scaling factor is one).</comment>
        </bits>
      </reg>
      <reg name="gd_vl_blend_opt" protect="rw">
        <bits access="rw" name="chroma key b" pos="4:0" rst="0x0">
          <comment>Blue component of the Chroma Key</comment>
          <options>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="chroma key g" pos="10:5" rst="0x0">
          <comment>Green component of the Chroma Key</comment>
          <options>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="chroma key r" pos="15:11" rst="0x0">
          <comment>Red component of the Chroma Key</comment>
          <options>
            <mask/>
          </options>
        </bits>
        <bitgroup name="chroma key color">
          <entry ref="chroma key b"/>
          <entry ref="chroma key g"/>
          <entry ref="chroma key r"/>
        </bitgroup>
        <bits access="rw" name="chroma key enable" pos="16" rst="0x0">
          <comment>Enables the Chroma Keying</comment>
          <options>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="chroma key mask" pos="19:17" rst="0x0">
          <comment>
            Allows a range of color for the Chroma Keying:
            <br/>
            000b: exact color match
            <br/>
            001b: disregard 1 LSBit of each color component for matching
            <br/>
            011b: disregard 2 LSBit of each color component for matching
            <br/>
            111b: disregard 3 LSBit of each color component for matching
          </comment>
          <options>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="alpha" pos="27:20" rst="0x0">
          <comment>Layer Alpha blending coefficient</comment>
          <options>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="rotation" pos="29:28" rst="0x0">
          <comment>
            Layer rotation selection
            <br/>
            00b: No rotation
            <br/>
            01b: 90  degrees rotation (clockwise)
            <br/>
            10b: reserved
            <br/>
            11b: reserved
          </comment>
          <options>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="depth" pos="31:30" rst="0x0">
          <comment>
            Layer depth
            <br/>
            00b: Video layer behind all Overlay layers
            <br/>
            01b: Video layer between Overlay layers 1 and 0
            <br/>
            10b: Video layer between Overlay layers 2 and 1
            <br/>
            11b: Video layer on top of all Overlay layers
          </comment>
          <options>
            <mask/>
          </options>
        </bits>
      </reg>
      <reg name="gd_vl_y_src" protect="rw">
        <bits access="rw" name="addr" pos="NB_BITS_ADDR-1:2" rst="0x0">
          <comment>Dword-aligned address of the Y component (or RGB) of the source image</comment>
        </bits>
      </reg>
      <reg name="gd_vl_u_src" protect="rw">
        <bits access="rw" name="addr" pos="NB_BITS_ADDR-1:2" rst="0x0">
          <comment>Dword-aligned address of the U component of the source image</comment>
        </bits>
      </reg>
      <reg name="gd_vl_v_src" protect="rw">
        <bits access="rw" name="addr" pos="NB_BITS_ADDR-1:2" rst="0x0">
          <comment>Dword-aligned address of the V component of the source image</comment>
        </bits>
      </reg>
      <reg name="gd_vl_resc_ratio" protect="rw">
        <bits access="rw" name="xpitch" pos="GD_FIXEDPOINT_SIZE-1:0" rst="0x0">
          <comment>Video layer rescaling ratio upon x-axis. This is a 2.8 fixed point number representing the input/output width ratio.</comment>
        </bits>
        <bits access="rw" name="ypitch" pos="GD_FIXEDPOINT_SIZE+15:16" rst="0x0">
          <comment>Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio.</comment>
        </bits>
        <bits access="w" name="pre_fetch_en" pos="29" rst="0x0">
          <comment>Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio.</comment>
        </bits>
        <bits access="rw" name="iy_dctenable" pos="30" rst="0x0">
          <comment>Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio.</comment>
        </bits>
        <bits access="rw" name="ypitch_scale_enable" pos="31" rst="0x0">
          <comment>Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio.</comment>
        </bits>
      </reg>
      <struct count="3" name="overlay_layer">
        <comment>The Overlay layers have a fixed depth relative to their index. Overlay layer 0 is the first to be drawn (thus the deepest), overlay layer 2 is the last to be drawn.</comment>
        <reg name="gd_ol_input_fmt" protect="rw">
          <bits access="rw" name="format" pos="1:0" rst="0x0">
            <comment>
              Input image format
              <br/>
              0: RGB565 pixel packed
              <br/>
              1: ARGB8888 pixel packed
              <br/>
              others: reserved
            </comment>
          </bits>
          <bits access="rw" name="stride" pos="GD_NB_BITS_STRIDE+1:2" rst="0x0">
            <comment>
              Image stride in 16-bits word.
              <br/>
              This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size).
            </comment>
          </bits>
          <bits access="rw" name="prefetch" pos="18" rst="0x1">
            <comment>
              Image stride in 16-bits word.
              <br/>
              This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size).
            </comment>
          </bits>
          <bits access="rw" name="active" pos="31" rst="0x0">
            <comment>
              Defines Layer's activity:
              <br/>
              0: Layer disabled
              <br/>
              1: Layer active
            </comment>
          </bits>
        </reg>
        <reg name="gd_ol_tl_ppos" protect="rw">
          <bits access="rw" name="x0" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
            <comment>Overlay Layer (layer X+1) Top-Left pixel x-axis position</comment>
          </bits>
          <bits access="rw" name="y0" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
            <comment>Overlay Layer (layer X+1) Top-Left pixel y-axis position</comment>
          </bits>
        </reg>
        <reg name="gd_ol_br_ppos" protect="rw">
          <bits access="rw" name="x1" pos="GD_NB_BITS_LCDPOS-1:0" rst="0x0">
            <comment>Overlay Layer (layer X+1) Bottom-Right pixel x-axis position</comment>
          </bits>
          <bits access="rw" name="y1" pos="GD_NB_BITS_LCDPOS+15:16" rst="0x0">
            <comment>Overlay Layer (layer X+1) Bottom-Right pixel y-axis position</comment>
          </bits>
        </reg>
        <reg name="gd_ol_blend_opt" protect="rw">
          <bits access="rw" name="chroma key b" pos="4:0" rst="0x0">
            <comment>Blue component of the Chroma Key</comment>
          </bits>
          <bits access="rw" name="chroma key g" pos="10:5" rst="0x0">
            <comment>Green component of the Chroma Key</comment>
          </bits>
          <bits access="rw" name="chroma key r" pos="15:11" rst="0x0">
            <comment>Red component of the Chroma Key</comment>
          </bits>
          <bitgroup name="chroma key color">
            <entry ref="chroma key b"/>
            <entry ref="chroma key g"/>
            <entry ref="chroma key r"/>
          </bitgroup>
          <bits access="rw" name="chroma key enable" pos="16" rst="0x0">
            <comment>Enables the Chroma Keying</comment>
          </bits>
          <bits access="rw" name="chroma key mask" pos="19:17" rst="0x0">
            <comment>
              Allows a range of color for the Chroma Keying:
              <br/>
              000b: exact color match
              <br/>
              001b: disregard 1 LSBit of each color component for matching
              <br/>
              011b: disregard 2 LSBit of each color component for matching
              <br/>
              111b: disregard 3 LSBit of each color component for matching
            </comment>
          </bits>
          <bits access="rw" name="alpha" pos="27:20" rst="0x0">
            <comment>Layer Alpha blending coefficient</comment>
          </bits>
        </reg>
        <reg name="gd_ol_rgb_src" protect="rw">
          <bits access="rw" name="addr" pos="NB_BITS_ADDR-1:2" rst="0x0">
            <comment>Dword-aligned address of the source image</comment>
          </bits>
        </reg>
      </struct>
      <reg name="gd_lcd_ctrl" protect="rw">
        <bits access="rw" name="destination" pos="1:0" rst="0x0">
          <comment>Destination Selection</comment>
          <options>
            <option name="LCD CS 0" value="0"/>
            <option name="LCD CS 1" value="1"/>
            <option name="Memory LCD type" value="2"/>
            <option name="Memory RAM" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="output format" pos="6:4" rst="0x0">
          <comment>
            Output format
            <br/>
            000b:  8-bit - RGB3:3:2 - 1cycle/1pixel - RRRGGGBB
            <br/>
            001b:  8-bit - RGB4:4:4 - 3cycle/2pixel - RRRRGGGG/BBBBRRRR/GGGGBBBB
            <br/>
            010b:  8-bit - RGB5:6:5 - 2cycle/1pixel - RRRRRGGG/GGGBBBBB
            <br/>
            011b:  reserved
            <br/>
            100b: 16-bit - RGB3:3:2 - 1cycle/2pixel - RRRGGGBBRRRGGGBB
            <br/>
            101b: 16-bit - RGB4:4:4 - 1cycle/1pixel - XXXXRRRRGGGGBBBB
            <br/>
            110b: 16-bit - RGB5:6:5 - 1cycle/1pixel - RRRRRGGGGGGBBBBB
            <br/>
            111b: 32-bit - RGB5:6:5 - 1cycle/2pixel - RRRRRGGGGGGBBBBB/RRRRRGGGGGGBBBBB
            <br/>
            <br/>
             The MSB select also the AHB access size (8-bit or 16-bit) when Memory destination is selected.
            <br/>
             Must set to RGB565 when RAM type destination selected
          </comment>
          <options>
            <option name="8-bit;RGB332" value="0"/>
            <option name="8-bit;RGB444" value="1"/>
            <option name="8-bit;RGB565" value="2"/>
            <option name="16-bit;RGB332" value="4"/>
            <option name="16-bit;RGB444" value="5"/>
            <option name="16-bit;RGB565" value="6"/>
          </options>
        </bits>
        <bits access="rw" name="high byte" pos="7" rst="0x0">
    </bits>
        <bits access="rw" name="cs0 polarity" pos="8" rst="0x0">
          <comment>
            Change Polarity of CS0 signal
            <br/>
             0: no change
            <br/>
             1: Inverted
          </comment>
        </bits>
        <bits access="rw" name="cs1 polarity" pos="9" rst="0x0">
          <comment>
            Change Polarity of CS1 signal
            <br/>
             0: no change
            <br/>
             1: Inverted
          </comment>
        </bits>
        <bits access="rw" name="rs polarity" pos="10" rst="0x0">
          <comment>
            Change Polarity of RS signal
            <br/>
             0: no change
            <br/>
             1: Inverted
          </comment>
        </bits>
        <bits access="rw" name="wr polarity" pos="11" rst="0x0">
          <comment>
            Change Polarity of WR signal
            <br/>
             0: no change
            <br/>
             1: Inverted
          </comment>
        </bits>
        <bits access="rw" name="rd polarity" pos="12" rst="0x0">
          <comment>
            Change Polarity of RD signal
            <br/>
             0: no change
            <br/>
             1: Inverted
          </comment>
        </bits>
        <bits access="rw" name="nb command" pos="21:16" rst="0x0">
          <comment>Number of command to be send to the LCD command (up to 31)</comment>
        </bits>
        <bits access="w" name="start command" pos="24" rst="0x0">
          <comment>Start command transfer only. Autoreset</comment>
        </bits>
        <bits access="rw" name="lcd resetb" pos="25" rst="0x1">
          <comment>LCD reset signal. Low active</comment>
        </bits>
      </reg>
      <reg name="gd_lcd_timing" protect="rw">
        <comment>All value are in cycle number of system clock</comment>
        <bits access="rw" name="tas" pos="2:0" rst="0x0">
          <comment>Address setup time (RS to WR, RS to RD)</comment>
        </bits>
        <bits access="rw" name="tah" pos="6:4" rst="0x0">
          <comment>Adress hold time</comment>
        </bits>
        <bits access="rw" name="pwl" pos="13:8" rst="0x0">
          <comment>Pulse Width Low level, between 2 and 63.</comment>
        </bits>
        <bits access="rw" name="pwh" pos="21:16" rst="0x0">
          <comment>Pulse Width High level, between 2 and 63 (must be &gt; (TAH+TAS) ).</comment>
        </bits>
      </reg>
      <reg name="gd_lcd_mem_address" protect="rw">
        <bits access="rw" name="addr_dst" pos="NB_BITS_ADDR-1:2" rst="all0">
          <comment>
            Address destination pointer when memory destination is selected.
            <br/>
            The addr_dst[1] which correspond to the M_A[0] on the memory interface is used to select between command/data.
          </comment>
        </bits>
      </reg>
      <reg name="gd_lcd_stride_offset" protect="rw">
        <bits access="rw" name="stride_offset" pos="9:0" rst="all0">
          <comment>
            Address offset (in Bytes) skipped at the end of each line when memory destination is selected.
            <br/>
            This 2D feature allows for in-memory image compositing.
          </comment>
        </bits>
      </reg>
      <reg name="gd_lcd_single_access" protect="rw">
        <bits access="rw" name="lcd_data" pos="15:0" rst="all0">
          <comment>data to write or data readen (the readen data is ready when the lcd is not busy)</comment>
        </bits>
        <bits access="rw" name="type" pos="16" rst="0x0">
          <comment>
            Acesss type selection
            <br/>
            0: Command
            <br/>
            1: Data
          </comment>
        </bits>
        <bits access="w" name="start_write" pos="17" rst="0x0">
          <comment>Start a single write access. Autoreset</comment>
        </bits>
        <bits access="w" name="start_read" pos="18" rst="0x0">
          <comment>Start a single read access (only when LCD output selected). Autoreset.</comment>
        </bits>
      </reg>
      <reg name="gd_spilcd_config" protect="rw">
        <bits access="rw" name="spi_lcd_select" pos="0" rst="0"> </bits>
        <bits access="rw" name="spi_device_id" pos="6:1" rst="all0">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="spi_clk_divider" pos="14:7" rst="0a">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="spi_dummy_cycle" pos="17:15" rst="all0">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="spi_line" pos="19:18" rst="all0">
          <comment>0:4 line mode
                   1:3 line mode
                   2:command mode
                   3:3 line 2 lane mode tx</comment>
          <options>
            <mask/>
            <option name="4" value="0"/>
            <option name="3" value="1"/>
            <option name="4_Start_Byte" value="2"/>
            <option name="3_Two_Lane" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="spi_rx_byte" pos="22:20" rst="all0">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="spi_rw" pos="23" rst="0">
          <options>
            <option name="Write" value="0"/>
            <option name="Read" value="1"/>
          </options>
        </bits>
      </reg>
      <reg name="gd_spilcd_rd" protect="r">
        <bits access="r" name="spi_lcd_rd" pos="31:0" rst="all0">
          <comment/>
        </bits>
      </reg>
      <reg name="gd_vl_fix_ratio" protect="rw">
        <bits access="rw" name="reg_vl_only_sel" pos="19" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="mirror" pos="18" rst="0x0">
          <comment>Mirror enable.</comment>
        </bits>
        <bits access="rw" name="l_yfixen" pos="17" rst="0x0">
          <comment>.</comment>
        </bits>
        <bits access="rw" name="l_xfixen" pos="16" rst="0x0">
          <comment>.</comment>
        </bits>
        <bits access="rw" name="l_yratio" pos="15:8" rst="0x0">
          <comment>.</comment>
        </bits>
        <bits access="rw" name="l_xratio" pos="7:0" rst="0x0">
          <comment>.</comment>
        </bits>
      </reg>
      <hole size="(80-38-1)*32"/>
      <reg name="tecon" protect="rw">
        <bits access="rw" name="te_count2" pos="27:16" rst="0x0">
          <comment>Count value to detect vsync pulse</comment>
        </bits>
        <bits access="rw" name="te_mode" pos="2" rst="0x0">
          <comment>0:vsync te only 1:vsync and hsync te</comment>
        </bits>
        <bits access="rw" name="te_edge_sel" pos="1" rst="0x0">
          <comment>Pol select</comment>
        </bits>
        <bits access="rw" name="te_en" pos="0" rst="0x0">
          <comment>Te enable.</comment>
        </bits>
      </reg>
      <reg name="tecon2" protect="rw">
        <bits access="rw" name="te_count1" pos="28:0" rst="0x0">
          <comment>Te counter value</comment>
        </bits>
      </reg>
      <hole size="(256-81-1)*32"/>
    </module>
    <module category="System" name="GOUDA_SRAM">
      <var name="GD_NB_WORKBUF_WORDS" value="5856"/>
      <var name="GD_NB_LCD_CMD_WORDS" value="64"/>
      <var name="GD_SRAM_SIZE" value="(GD_NB_WORKBUF_WORDS+GD_NB_LCD_CMD_WORDS)*2"/>
      <var name="GD_SRAM_ADDR_WIDTH" value="13"/>
      <memory name="sram_array" size="GD_SRAM_SIZE">
        <comment>Gouda internal Sram space</comment>
      </memory>
    </module>
  </archive>
  <archive relative="lcdc.xml">
    <include file="globals.xml"/>
    <module category="System" name="LCDC">
      <reg name="gd_command" protect="wo">
        <bits access="wo" name="start" pos="0" rst="0x0">
          <comment>Starts the image transfer. Autoreset</comment>
        </bits>
      </reg>
      <reg name="gd_status" protect="r">
        <bits access="r" name="ia_busy" pos="0" rst="0x0">
          <comment>High while image accelerator is busy</comment>
        </bits>
        <bits access="r" name="lcd_busy" pos="4" rst="0x0">
          <comment>High while LCD controller is busy</comment>
        </bits>
      </reg>
      <reg name="gd_eof_irq" protect="rc">
        <bits access="rc" name="eof_cause" pos="0" rst="0x0">
          <comment>
            High when End Of Frame IRQ has been generated.
            <br/>
            To clear it, write 1 in this bit or in eof_status.
          </comment>
        </bits>
        <bits access="rw" name="vsync_rise" pos="2" rst="0x0">
          <comment>Vsync rise interrupt.</comment>
        </bits>
        <bits access="rw" name="vsync_fall" pos="3" rst="0x0">
          <comment>Vsync fall interrupt</comment>
        </bits>
        <bits access="rw" name="dpi_overflow" pos="4" rst="0x0">
          <comment>Dpi overflow interrupt</comment>
        </bits>
        <bits access="rw" name="dpi_frameover" pos="5" rst="0x0">
          <comment>Frame over interrupt.</comment>
        </bits>
        <bits access="rw" name="mipi_int" pos="6" rst="0x0">
          <comment>interrupt.</comment>
        </bits>
        <bits access="rc" name="eof_status" pos="16" rst="0x0">
          <comment>
            Unmasked version of eof_cause.
            <br/>
            To clear it, write 1 in this bit or in eof_status.
          </comment>
        </bits>
      </reg>
      <reg name="gd_eof_irq_mask" protect="rw">
        <bits access="rw" name="eof_mask" pos="0" rst="0x0">
          <comment>
            EOF interrupt generation mask:
            <br/>
            0: EOF IRQ disabled
            <br/>
            1: EOF IRQ enabled
          </comment>
        </bits>
        <bits access="rw" name="vsync_rise_mask" pos="1" rst="0x0">
          <comment>Vsync rise interrupt.</comment>
        </bits>
        <bits access="rw" name="vsync_fall_mask" pos="2" rst="0x0">
          <comment>Vsync fall interrupt.</comment>
        </bits>
        <bits access="rw" name="dpi_overflow_mask" pos="3" rst="0x0">
          <comment>Dpi overflow interrupt.</comment>
        </bits>
        <bits access="rw" name="dpi_frameover_mask" pos="4" rst="0x0">
          <comment>Frame over interrupt.</comment>
        </bits>
        <bits access="rw" name="mipi_int_mask" pos="5" rst="0x0">
          <comment>Mipi interrupt</comment>
        </bits>
      </reg>
      <reg name="gd_lcd_ctrl" protect="rw">
        <bits access="rw" name="destination" pos="1:0" rst="0x0">
          <comment>Destination Selection</comment>
          <options>
            <option name="LCD CS 0" value="0"/>
            <option name="LCD CS 1" value="1"/>
            <option name="Memory RAM" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="output format" pos="6:4" rst="0x0">
          <comment>
            Output format, when Destination is Memory
            <br/>
            110b: 16-bit - RGB5:6:5
            <br/>
            111b: 32-bit - ARGB8:8:8:8
          </comment>
          <options>
            <option name="16-bit;RGB565" value="6"/>
            <option name="32-bit;ARGB8888" value="7"/>
          </options>
        </bits>
        <bits access="rw" name="high byte" pos="7" rst="0x0">
          <comment>exchange high byte and low byte, when output data bus width is 16 bit</comment>
        </bits>
        <bits access="rw" name="cs0 polarity" pos="8" rst="0x0">
          <comment>
            Change Polarity of CS0 signal
            <br/>
             0: no change
            <br/>
             1: Inverted
          </comment>
        </bits>
        <bits access="rw" name="cs1 polarity" pos="9" rst="0x0">
          <comment>
            Change Polarity of CS1 signal
            <br/>
             0: no change
            <br/>
             1: Inverted
          </comment>
        </bits>
        <bits access="rw" name="rs polarity" pos="10" rst="0x0">
          <comment>
            Change Polarity of RS signal
            <br/>
             0: no change
            <br/>
             1: Inverted
          </comment>
        </bits>
        <bits access="rw" name="wr polarity" pos="11" rst="0x0">
          <comment>
            Change Polarity of WR signal
            <br/>
             0: no change
            <br/>
             1: Inverted
          </comment>
        </bits>
        <bits access="rw" name="rd polarity" pos="12" rst="0x0">
          <comment>
            Change Polarity of RD signal
            <br/>
             0: no change
            <br/>
             1: Inverted
          </comment>
        </bits>
        <bits access="rw" name="gamma_en" pos="13" rst="0x0">
          <comment>gamma enable</comment>
        </bits>
        <bits access="rw" name="bus_sel" pos="26:25" rst="0x0">
          <comment>
            output data bus width select,when use mcu port
            <br/>
             0: 16bit rgb565
            <br/>
             1: 18bit rgb666
            <br/>
             2: 24bit rgb888
          </comment>
        </bits>
      </reg>
      <reg name="gd_lcd_timing" protect="rw">
        <comment>All value are in cycle number of system clock</comment>
        <bits access="rw" name="tas" pos="2:0" rst="0x0">
          <comment>Address setup time (RS to WR, RS to RD)</comment>
        </bits>
        <bits access="rw" name="tah" pos="6:4" rst="0x0">
          <comment>Adress hold time</comment>
        </bits>
        <bits access="rw" name="pwl" pos="13:8" rst="0x0">
          <comment>Pulse Width Low level, between 2 and 63.</comment>
        </bits>
        <bits access="rw" name="pwh" pos="21:16" rst="0x0">
          <comment>Pulse Width High level, between 2 and 63 (must be &gt; (TAH+TAS) ).</comment>
        </bits>
      </reg>
      <reg name="gd_lcd_mem_address" protect="rw">
        <bits access="rw" name="addr_dst" pos="NB_BITS_ADDR-1:2" rst="all0">
          <comment>
            Address destination pointer when memory destination is selected.
            <br/>
            The addr_dst[1] which correspond to the M_A[0] on the memory interface is used to select between command/data.
          </comment>
        </bits>
      </reg>
      <reg name="gd_lcd_stride_offset" protect="rw">
        <bits access="rw" name="stride_offset" pos="10:0" rst="all0">
          <comment>
            Address offset (in Bytes) skipped at the end of each line when memory destination is selected.
            <br/>
            This 2D feature allows for in-memory image compositing.
          </comment>
        </bits>
      </reg>
      <reg name="gd_lcd_single_access" protect="rw">
        <bits access="rw" name="lcd_data" pos="15:0" rst="all0">
          <comment>data to write or data readen (the readen data is ready when the lcd is not busy)</comment>
        </bits>
        <bits access="rw" name="type" pos="16" rst="0x0">
          <comment>
            Acesss type selection
            <br/>
            0: Command
            <br/>
            1: Data
          </comment>
        </bits>
        <bits access="w" name="start_write" pos="17" rst="0x0">
          <comment>Start a single write access. Autoreset</comment>
        </bits>
        <bits access="w" name="start_read" pos="18" rst="0x0">
          <comment>Start a single read access (only when LCD output selected). Autoreset.</comment>
        </bits>
      </reg>
      <reg name="gd_spilcd_config" protect="rw">
        <bits access="rw" name="spi_lcd_select" pos="0" rst="0"> </bits>
        <bits access="rw" name="spi_device_id" pos="6:1" rst="all0">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="spi_clk_divider" pos="14:7" rst="0a">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="spi_dummy_cycle" pos="17:15" rst="all0">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="spi_line" pos="19:18" rst="all0">
          <comment>0:4 line mode
                     1:3 line mode
                     2:command mode
                     3:3 line 2 lane mode tx</comment>
          <options>
            <mask/>
            <option name="4" value="0"/>
            <option name="3" value="1"/>
            <option name="4_Start_Byte" value="2"/>
            <option name="3_Two_Lane" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="spi_rx_byte" pos="22:20" rst="all0">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="spi_rw" pos="23" rst="0">
          <options>
            <option name="Write" value="0"/>
            <option name="Read" value="1"/>
          </options>
        </bits>
      </reg>
      <hole size="1*32"/>
      <reg name="dct_shiftr_uv_reg1" protect="rw">
        <bits access="rw" name="vsync_toggle_hsync_cnt" pos="10:0" rst="0x143">
          <comment>For vsync to hsync setup.</comment>
        </bits>
        <bits access="rw" name="reg_rgb_wait" pos="30" rst="0x0">
          <comment>whether wait for data, when data is not ready for transfer</comment>
        </bits>
      </reg>
      <reg name="dpi_config" protect="rw">
        <bits access="rw" name="reg_pend_req" pos="25:21" rst="0x0">
          <comment>control outstanding number</comment>
        </bits>
        <bits access="rw" name="mipi_cmd_sel" pos="20" rst="0x0">
          <comment>
            if this bit is enable and dsi is enable. lcdc will stop at the end of a frame.
            <br/>
            this is used to send mipi cmd
          </comment>
        </bits>
        <bits access="rw" name="reg_empty_ctrl" pos="15:14" rst="0x0">
          <comment>
            control actions to take, when fifo underflow arise
            <br/>
            bit0:control when fifo is underflow, output zero or data in the fifo.
            <br/>
                 0:output data in the fifo
            <br/>
                 1:output zero
            <br/>
            bit1:whether clear fifo at the end of a frame, when fifo is underflow.
            <br/>
                 0:not clear
            <br/>
                 1:clear
          </comment>
        </bits>
        <bits access="rw" name="r_rgb_format" pos="13:12" rst="0x0">
          <comment>0:24bit 1:16bit. 2:18bit</comment>
        </bits>
        <bits access="rw" name="r_dsi_enable" pos="9" rst="0x0">
          <comment>Mipi enable.</comment>
        </bits>
        <bits access="rw" name="r_outoff_data" pos="8" rst="0x0">
          <comment>Rgb panel disable output data.</comment>
        </bits>
        <bits access="rw" name="r_outoff_clk" pos="7" rst="0x0">
          <comment>Rgb panel disable output clock.</comment>
        </bits>
        <bits access="rw" name="r_outoff_all" pos="6" rst="0x0">
          <comment>Rgb panel disable output all.</comment>
        </bits>
        <bits access="rw" name="r_pix_fmt" pos="5:4" rst="0x0">
          <comment>00:rgb565  01:rgb888   10:xrgb8888   11:rgbx8888.</comment>
        </bits>
        <bits access="rw" name="r_rgb_order" pos="3" rst="0x0">
          <comment>0:RGB 1:BGR.</comment>
        </bits>
        <bits access="rw" name="r_frame2_enable" pos="2" rst="0x0">
          <comment>Frame2 use.</comment>
        </bits>
        <bits access="rw" name="r_frame1_enable" pos="1" rst="0x0">
          <comment>Frame1 use.</comment>
        </bits>
        <bits access="rw" name="r_rgb_enable" pos="0" rst="0x0">
          <comment>Rgb panel enable.</comment>
        </bits>
      </reg>
      <reg name="dpi_fram0_addr" protect="rw">
    </reg>
      <reg name="dpi_fram0_con" protect="rw">
        <bits access="rw" name="r_frame0_line_step" pos="28:16" rst="0x0">
          <comment>Frame0 line step,in byte.</comment>
        </bits>
        <bits access="rw" name="r_frame0_valid" pos="0" rst="0x0">
          <comment>Frame 0 valid.</comment>
        </bits>
      </reg>
      <reg name="dpi_fram1_addr" protect="rw">
    </reg>
      <reg name="dpi_fram1_con" protect="rw">
        <bits access="rw" name="r_frame1_line_step" pos="28:16" rst="0x0">
          <comment>Frame1 line step,in byte.</comment>
        </bits>
        <bits access="rw" name="r_frame1_valid" pos="0" rst="0x0">
          <comment>Frame 1 valid.</comment>
        </bits>
      </reg>
      <reg name="dpi_fram2_addr" protect="rw">
    </reg>
      <reg name="dpi_fram2_con" protect="rw">
        <bits access="rw" name="r_frame2_line_step" pos="28:16" rst="0x0">
          <comment>Frame2 line step,in byte.</comment>
        </bits>
        <bits access="rw" name="r_frame2_valid" pos="0" rst="0x0">
          <comment>Frame 2 valid.</comment>
        </bits>
      </reg>
      <reg name="dpi_size" protect="rw">
        <bits access="rw" name="r_v_size" pos="26:16" rst="0x10">
          <comment>Vertical pix num.</comment>
        </bits>
        <bits access="rw" name="r_h_size" pos="10:0" rst="0x10">
          <comment>Horizontal pix num.</comment>
        </bits>
      </reg>
      <reg name="dpi_fifo_ctrl" protect="rw">
        <bits access="rw" name="r_data_fifo_lowthres" pos="25:16" rst="0x10">
          <comment>Data fifo threshold when req axi.</comment>
        </bits>
        <bits access="rw" name="r_fifo_rst_auto" pos="1" rst="0x0">
          <comment>Dpi fifo auto reset enable when occur overflow .</comment>
        </bits>
        <bits access="rw" name="r_fifo_rst" pos="0" rst="0x0">
          <comment>Dpi fifo reset.</comment>
        </bits>
      </reg>
      <reg name="dpi_throt" protect="rw">
        <bits access="rw" name="r_throttle_period" pos="25:16" rst="0x0">
          <comment>Throttle period. delay time between read requests</comment>
        </bits>
        <bits access="rw" name="r_throttle_en" pos="0" rst="0x0">
          <comment>Dpi dma throttle enable.</comment>
        </bits>
      </reg>
      <reg name="dpi_pol" protect="rw">
        <bits access="rw" name="r_reg_clk_adj" pos="16:13" rst="0x0">
          <comment>adjust dot clock phase. unit is fast dpi clock</comment>
        </bits>
        <bits access="rw" name="r_de_pol" pos="11" rst="0x0">
          <comment>Data enable pol.</comment>
        </bits>
        <bits access="rw" name="r_vsync_pol" pos="10" rst="0x0">
          <comment>Vsync pol.</comment>
        </bits>
        <bits access="rw" name="r_hsync_pol" pos="9" rst="0x0">
          <comment>Hsync pol.</comment>
        </bits>
        <bits access="rw" name="r_dot_clk_pol" pos="8" rst="0x0">
          <comment>Dot clock pol.</comment>
        </bits>
        <bits access="rw" name="r_dot_clk_div" pos="7:0" rst="0x0">
          <comment>dot clock div.</comment>
        </bits>
      </reg>
      <reg name="dpi_time0" protect="rw">
        <bits access="rw" name="r_front_porch_start_vsync_timer" pos="26:16" rst="0xf2">
          <comment>vsync back porch + vsync display period.</comment>
        </bits>
        <bits access="rw" name="r_back_porch_end_vsync_timer" pos="10:0" rst="0x2">
          <comment>vsync back porch num.</comment>
        </bits>
      </reg>
      <reg name="dpi_time1" protect="rw">
        <bits access="rw" name="r_vsync_include_hsync_th_low" pos="26:16" rst="0x1">
          <comment>vsync low pulse width.</comment>
        </bits>
        <bits access="rw" name="r_vsync_include_hsync_th_high" pos="10:0" rst="0xf3">
          <comment>vsync period - 1.</comment>
        </bits>
      </reg>
      <reg name="dpi_time2" protect="rw">
        <bits access="rw" name="r_hsync_include_dotclk_th_low" pos="26:16" rst="0x1">
          <comment>hsync low pulse width.</comment>
        </bits>
        <bits access="rw" name="r_hsync_include_dotclk_th_high" pos="10:0" rst="0x143">
          <comment>hsync period -1.</comment>
        </bits>
      </reg>
      <reg name="dpi_time3" protect="rw">
        <bits access="rw" name="r_rgb_data_enable_end_timer" pos="26:16" rst="0x142">
          <comment>data enable end.</comment>
        </bits>
        <bits access="rw" name="r_rgb_data_enable_start_timer" pos="10:0" rst="0x2">
          <comment>data enable start.</comment>
        </bits>
      </reg>
      <reg name="dpi_status" protect="ro">
        <bits access="ro" name="current_frame" pos="5:4" rst="0x0">
          <comment/>
        </bits>
        <bits access="ro" name="frame_runing" pos="3" rst="0x0">
          <comment/>
        </bits>
        <bits access="ro" name="frame2_over" pos="2" rst="0x0">
          <comment/>
        </bits>
        <bits access="ro" name="frame1_over" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="ro" name="frame0_over" pos="0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dither_ctrl" protect="rw">
        <bits access="rw" name="r_dither_en" pos="0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="dither_mode_r" pos="1" rst="0x0">
          <comment>0:8bits to 6bits 1:8bits to 5bits</comment>
        </bits>
        <bits access="rw" name="dither_mode_g" pos="2" rst="0x0">
          <comment>0:8bits to 6bits 1:8bits to 5bits</comment>
        </bits>
        <bits access="rw" name="dither_mode_b" pos="3" rst="0x0">
          <comment>0:8bits to 6bits 1:8bits to 5bits</comment>
        </bits>
        <bits access="rw" name="dither_ctrl_r" pos="5:4" rst="0x0">
          <comment>
            0: bypass mode
            <br/>
            1: 2x2 mode
            <br/>
            2: 4x4 mode
            <br/>
            3: lfsr mode
          </comment>
        </bits>
        <bits access="rw" name="dither_ctrl_g" pos="7:6" rst="0x0">
          <comment>
            0: bypass mode
            <br/>
            1: 2x2 mode
            <br/>
            2: 4x4 mode
            <br/>
            3: lfsr mode
          </comment>
        </bits>
        <bits access="rw" name="dither_ctrl_b" pos="9:8" rst="0x0">
          <comment>
            0: bypass mode
            <br/>
            1: 2x2 mode
            <br/>
            2: 4x4 mode
            <br/>
            3: lfsr mode
          </comment>
        </bits>
      </reg>
      <reg name="dither_matrix0_0" protect="rw">
        <bits access="rw" name="dither_matrix0_0" pos="31:0" rst="0x4056273">
        </bits>
      </reg>
      <reg name="dither_matrix0_1" protect="rw">
        <bits access="rw" name="dither_matrix0_1" pos="31:0" rst="0x15148362">
        </bits>
      </reg>
      <reg name="dither_matrix1" protect="rw">
        <bits access="rw" name="dither_matrix1" pos="7:0" rst="0x2d">
          <comment/>
        </bits>
        <bits access="rw" name="reg_lfsr_initialdata" pos="19:8" rst="0x0">
          <comment>linear feedback shift register initial data</comment>
        </bits>
      </reg>
      <reg name="tecon" protect="rw">
        <bits access="rw" name="te_count2" pos="27:16" rst="0x0">
          <comment>Count value to detect vsync pulse</comment>
        </bits>
        <bits access="rw" name="te_mode" pos="2" rst="0x0">
          <comment>0:vsync te only 1:vsync and hsync te</comment>
        </bits>
        <bits access="rw" name="te_edge_sel" pos="1" rst="0x0">
          <comment>Pol select</comment>
        </bits>
        <bits access="rw" name="te_en" pos="0" rst="0x0">
          <comment>Te enable.</comment>
        </bits>
      </reg>
      <reg name="tecon2" protect="rw">
        <bits access="rw" name="te_count1" pos="28:0" rst="0x0">
          <comment>count hsync after vsync have been detected.</comment>
        </bits>
      </reg>
      <hole size="2*32"/>
      <reg name="dct_shiftr_y_reg0" protect="rw">
        <bits access="rw" name="counter_en" pos="31" rst="0x0">
          <comment>Use to delay between rgb data over and fetch the next frame data.</comment>
        </bits>
        <bits access="rw" name="delay_counter" pos="23:0" rst="0x0">
          <comment>.count by hclk</comment>
        </bits>
      </reg>
      <reg name="gamma_r_coef" protect="w">
        <bits access="w" name="gamma_r_a" pos="7:0" rst="0x0">
          <comment>address</comment>
        </bits>
        <bits access="w" name="gamma_r_d" pos="15:8" rst="0x0">
          <comment>data will be write to address</comment>
        </bits>
      </reg>
      <reg name="gamma_g_coef" protect="w">
        <bits access="w" name="gamma_g_a" pos="7:0" rst="0x0">
          <comment>address</comment>
        </bits>
        <bits access="w" name="gamma_g_d" pos="15:8" rst="0x0">
          <comment>data will be write to address</comment>
        </bits>
      </reg>
      <reg name="gamma_b_coef" protect="w">
        <bits access="w" name="gamma_b_a" pos="7:0" rst="0x0">
          <comment>address</comment>
        </bits>
        <bits access="w" name="gamma_b_d" pos="15:8" rst="0x0">
          <comment>data will be write to address</comment>
        </bits>
      </reg>
      <hole size="216*32"/>
      <reg name="dsi_power_up" protect="rw">
        <bits access="rw" name="dsipll_pu" pos="1" rst="0x0">
          <comment>Dsi pll power up</comment>
        </bits>
        <bits access="rw" name="pu_dsi" pos="0" rst="0x0">
          <comment>Power up dsi</comment>
        </bits>
      </reg>
      <reg name="dsi_enable" protect="rw">
        <bits access="rw" name="dsi_enable_reg" pos="0" rst="0x0">
          <comment>Enable digital dsi</comment>
        </bits>
        <bits access="rw" name="dsi_lprx_lpcd_enable" pos="1" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_lane_config" protect="rw">
        <bits access="rw" name="video_packet_hd_dr" pos="2" rst="0x0">
          <comment>1'b1: use the config register value 1'b0: use the compute value of controller</comment>
        </bits>
        <bits access="rw" name="dsi_config_reg" pos="1:0" rst="0x0">
          <comment>2'b00: x1 2'b01: x2 2'b10: x4 2'b11: hz</comment>
        </bits>
      </reg>
      <reg name="dsi_pixel_num" protect="rw">
        <bits access="rw" name="pixel_num_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_pixel_type" protect="rw">
        <bits access="rw" name="rgb_quad_en_reg" pos="3" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="pixel_type_reg" pos="2:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_tx_mode" protect="rw">
        <bits access="rw" name="dsi_tx_mode_reg" pos="1:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_vcid_bllp" protect="rw">
        <bits access="rw" name="bllp_enable_per_l_reg" pos="2" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="vci_reg" pos="1:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_line_byte_num" protect="rw">
        <bits access="rw" name="v2c_switch_start" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="frame_idle_en" pos="0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_hsa_num" protect="rw">
        <bits access="rw" name="hsa_num_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_hbp_num" protect="rw">
        <bits access="rw" name="hbp_num_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_hfp_num" protect="rw">
        <bits access="rw" name="hfp_num_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_hact_num" protect="rw">
        <bits access="rw" name="rgb_num_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_vsa_line_num" protect="rw">
        <bits access="rw" name="vsa_line_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_vbp_line_num" protect="rw">
        <bits access="rw" name="vbp_line_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_vfp_line_num" protect="rw">
        <bits access="rw" name="vfp_line_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_vact_line_num" protect="rw">
        <bits access="rw" name="vat_line_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_num" protect="rw">
        <bits access="rw" name="dsi_cmd_num_reg" pos="4:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cq_ctrl" protect="rw">
        <bits access="rw" name="dsi_cmd_merge_en_reg" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="dsi_cmd_start" pos="0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_int_clear" protect="wo">
        <bits access="wo" name="sleepout_done" pos="10" rst="0">
          <comment>write '1' to clear sleep out done interrupt</comment>
        </bits>
        <bits access="wo" name="frame_done" pos="9" rst="0">
          <comment>write '1' to clear frame done interrupt</comment>
        </bits>
        <bits access="wo" name="rx_te_ready" pos="8" rst="0">
          <comment>write '1' to clear rx te(tearing effect) interrupt</comment>
        </bits>
        <bits access="wo" name="fifo_half" pos="7" rst="0">
          <comment>write '1' to clear rx fifo half full interrupt</comment>
        </bits>
        <bits access="wo" name="fifo_ovfl" pos="6" rst="0">
          <comment>write '1' to clear rx fifo overflow interrupt</comment>
        </bits>
        <bits access="wo" name="cmd_q_end" pos="5" rst="0">
          <comment>write '1' to clear command queue tx end interrupt</comment>
        </bits>
        <bits access="wo" name="rx_data_end" pos="4" rst="0">
          <comment>write '1' to clear rx data end interrupt</comment>
        </bits>
        <bits access="wo" name="rx_crc_err" pos="3" rst="0">
          <comment>write '1' to clear rx crc error interrupt</comment>
        </bits>
        <bits access="wo" name="rx_ecc_err" pos="2" rst="0">
          <comment>write '1' to clear rx ecc error interrupt</comment>
        </bits>
        <bits access="wo" name="rx_bta_timeout" pos="1" rst="0">
          <comment>write '1' to clear rx bta timeout interrupt</comment>
        </bits>
        <bits access="wo" name="cd_err" pos="0" rst="0">
          <comment>write '1' to clear contention detect interrupt</comment>
        </bits>
      </reg>
      <reg name="dsi_int_mask" protect="rw">
        <bits access="rw" name="sleepout_done" pos="10" rst="0">
          <comment>sleep out done en</comment>
        </bits>
        <bits access="rw" name="frame_done" pos="9" rst="0">
          <comment>frame done en</comment>
        </bits>
        <bits access="rw" name="rx_te_ready" pos="8" rst="0">
          <comment>rx te(tearing effect) en</comment>
        </bits>
        <bits access="rw" name="fifo_half" pos="7" rst="0">
          <comment>rx fifo half full en</comment>
        </bits>
        <bits access="rw" name="fifo_ovfl" pos="6" rst="0">
          <comment>rx fifo overflow en</comment>
        </bits>
        <bits access="rw" name="cmd_q_end" pos="5" rst="0">
          <comment>command queue tx end en</comment>
        </bits>
        <bits access="rw" name="rx_data_end" pos="4" rst="0">
          <comment>rx data end en</comment>
        </bits>
        <bits access="rw" name="rx_crc_err" pos="3" rst="0">
          <comment>rx crc error en</comment>
        </bits>
        <bits access="rw" name="rx_ecc_err" pos="2" rst="0">
          <comment>rx ecc error en</comment>
        </bits>
        <bits access="rw" name="rx_bta_timeout" pos="1" rst="0">
          <comment>rx bta timeout en</comment>
        </bits>
        <bits access="rw" name="cd_err" pos="0" rst="0">
          <comment>contention detect error en</comment>
        </bits>
      </reg>
      <reg name="dsi_fifo_set" protect="rw">
        <bits access="rw" name="rx_ph_clr_reg" pos="3" rst="0x0">
          <comment>clear the packet header stored in registers from lcd. auto-clear</comment>
        </bits>
        <bits access="rw" name="lpk_mem_rst_reg" pos="2" rst="0x0">
          <comment>Reset the read pointer of queue which store the long packet payload</comment>
        </bits>
        <bits access="rw" name="fifo_set_reg " pos="1" rst="0x0">
          <comment>Reset the write index of fifo which store the data read from lcd</comment>
        </bits>
        <bits access="rw" name="fifo_read_set_reg " pos="0" rst="0x0">
          <comment>Reset the read index of fifo which store the data read from lcd</comment>
        </bits>
      </reg>
      <reg name="dsi_irq_status" protect="ro">
        <bits access="ro" name="fifo_empty" pos="11" rst="1">
          <comment>rx fifo empty flag</comment>
        </bits>
        <bits access="ro" name="sleepout_done" pos="10" rst="0">
          <comment>sleep out done flag</comment>
        </bits>
        <bits access="ro" name="frame_done" pos="9" rst="0">
          <comment>frame done flag</comment>
        </bits>
        <bits access="ro" name="rx_te_ready" pos="8" rst="0">
          <comment>rx te(tearing effect) flag</comment>
        </bits>
        <bits access="ro" name="fifo_half" pos="7" rst="0">
          <comment>rx fifo half full flag</comment>
        </bits>
        <bits access="ro" name="fifo_ovfl" pos="6" rst="0">
          <comment>rx fifo overflow flag</comment>
        </bits>
        <bits access="ro" name="cmd_q_end" pos="5" rst="0">
          <comment>command queue tx end flag</comment>
        </bits>
        <bits access="ro" name="rx_data_end" pos="4" rst="0">
          <comment>rx data end flag</comment>
        </bits>
        <bits access="ro" name="rx_crc_err" pos="3" rst="0">
          <comment>rx crc error flag</comment>
        </bits>
        <bits access="ro" name="rx_ecc_err" pos="2" rst="0">
          <comment>rx ecc error flag</comment>
        </bits>
        <bits access="ro" name="rx_bta_timeout" pos="1" rst="0">
          <comment>rx bta timeout flag</comment>
        </bits>
        <bits access="ro" name="cd_err" pos="0" rst="0">
          <comment>contention detect error flag</comment>
        </bits>
      </reg>
      <reg name="dsi_irq_cause" protect="ro">
        <bits access="ro" name="sleepout_done" pos="10" rst="0">
          <comment>sleep out done cause</comment>
        </bits>
        <bits access="ro" name="frame_done" pos="9" rst="0">
          <comment>frame done cause</comment>
        </bits>
        <bits access="ro" name="rx_te_ready" pos="8" rst="0">
          <comment>rx te(tearing effect) cause</comment>
        </bits>
        <bits access="ro" name="fifo_half" pos="7" rst="0">
          <comment>rx fifo half full cause</comment>
        </bits>
        <bits access="ro" name="fifo_ovfl" pos="6" rst="0">
          <comment>rx fifo overflow cause</comment>
        </bits>
        <bits access="ro" name="cmd_q_end" pos="5" rst="0">
          <comment>command queue tx end cause</comment>
        </bits>
        <bits access="ro" name="rx_data_end" pos="4" rst="0">
          <comment>rx data end cause</comment>
        </bits>
        <bits access="ro" name="rx_crc_err" pos="3" rst="0">
          <comment>rx crc error cause</comment>
        </bits>
        <bits access="ro" name="rx_ecc_err" pos="2" rst="0">
          <comment>rx ecc error cause</comment>
        </bits>
        <bits access="ro" name="rx_bta_timeout" pos="1" rst="0">
          <comment>rx bta timeout cause</comment>
        </bits>
        <bits access="ro" name="cd_err" pos="0" rst="0">
          <comment>contention detect error cause</comment>
        </bits>
      </reg>
      <reg name="dsi_rx_payload" protect="ro">
        <bits access="ro" name="rx_payload_03" pos="31:0" rst="0x0">
          <comment>
            receive payload byte0~3 of long packet from lcd
            <br/>
             [31:24]: byte3
            <br/>
             [23:16]: byte2
            <br/>
             [15:8]:  byte1
            <br/>
             [7:0]:   byte0
          </comment>
        </bits>
      </reg>
      <reg name="dsi_esc_pause_num" protect="rw">
        <bits access="rw" name="esc_pause_num_reg" pos="3:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_lptx_ratio" protect="rw">
        <bits access="rw" name="phy_lp_tx_rate_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_dsi_sel" protect="rw">
        <bits access="rw" name="mipi_dsi_sel_reg" pos="5:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_bllp_num" protect="rw">
        <bits access="rw" name="blp_num_reg" pos="5:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_hsa_hd_num" protect="rw">
        <bits access="rw" name="hsa_hd_num_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_hbp_hd_num" protect="rw">
        <bits access="rw" name="hbp_hd_num_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_hfp_hd_num" protect="rw">
        <bits access="rw" name="hfp_hd_num_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_hact_hd_num" protect="rw">
        <bits access="rw" name="rgb_hd_num_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_clk_state_ad_num" protect="rw">
        <bits access="rw" name="clk_state_ad_num_reg" pos="15:0" rst="0x10">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_clk_zero" protect="rw">
        <bits access="rw" name="clk_hd_zero_num_reg" pos="15:0" rst="0x9">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_rx_fifo_cnt" protect="r">
        <bits access="r" name="rx_fifo_cnt" pos="8:0" rst="0x0">
          <comment>
            receive payload of long packet from lcd stored in the FIFO.
            <br/>
             The value indicates the word count of FIFO.
          </comment>
        </bits>
      </reg>
      <hole size="29*32"/>
      <reg name="dsi_hs_mode_ctrl" protect="rw">
        <bits access="rw" name="hs_clk_always_reg" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="hs_mode_reg" pos="0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_swap_control" protect="rw">
        <bits access="rw" name="sync_word_swap_reg" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="data_swap_reg" pos="0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_lp00" protect="rw">
        <bits access="rw" name="t_lp_00_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_lp01" protect="rw">
        <bits access="rw" name="t_lp_01_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_lp10" protect="rw">
        <bits access="rw" name="t_lp_10_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_lp11" protect="rw">
        <bits access="rw" name="t_lp_11_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_hs_zero" protect="rw">
        <bits access="rw" name="t_zero_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_hs_sync" protect="rw">
        <bits access="rw" name="t_sync_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_hs_trail" protect="rw">
        <bits access="rw" name="t_eot_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_clk_lp00" protect="rw">
        <bits access="rw" name="clk_lp_00_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_clk_lp01" protect="rw">
        <bits access="rw" name="clk_lp_01_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_ulps_wakeup" protect="rw">
        <bits access="rw" name="t_ulps_wakeup" pos="19:0" rst="0x1ffff">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_clk_eot" protect="rw">
        <bits access="rw" name="clk_eot_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_bta_lpx" protect="rw">
        <bits access="rw" name="t_bta_lpx_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_bta_go" protect="rw">
        <bits access="rw" name="t_bta_cd_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_bta_00" protect="rw">
        <bits access="rw" name="t_bta_00_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_bta_timeout" protect="rw">
        <bits access="rw" name="t_bta_timeout_reg" pos="15:0" rst="0xffff">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_phy_ctrl" protect="rw">
        <bits access="rw" name="hz_bit_dr" pos="14:10" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="hz_bit_reg" pos="9:5" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="vreg_bit" pos="4:3" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="phase_selg" pos="2:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_ulps_ana_ctrl" protect="rw">
        <bits access="rw" name="cd_bit" pos="7:6" rst="0x2">
          <comment/>
        </bits>
        <bits access="rw" name="rx_bit" pos="5:4" rst="0x2">
          <comment/>
        </bits>
        <bits access="rw" name="trig_en" pos="2" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="wakeup_en" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="ulps_enable" pos="0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_bta_sure" protect="rw">
        <bits access="rw" name="t_rx_bta_cd_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_t_clk_post" protect="rw">
        <bits access="rw" name="clk_post_reg" pos="15:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cd_err_num" protect="rw">
        <bits access="rw" name="cd_err_num" pos="3:0" rst="0x8">
          <comment>The value is to count the time that lprx0 and lpcd0 are not equal.</comment>
        </bits>
      </reg>
      <hole size="2*32"/>
      <reg name="dsi_phy_reg" protect="rw">
        <bits access="rw" name="clk_band" pos="3:0" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="phase_sel" pos="6:4" rst="0x4">
          <comment/>
        </bits>
        <bits access="rw" name="rx_bit" pos="9:8" rst="0x2">
          <comment/>
        </bits>
        <bits access="rw" name="cd_bit" pos="11:10" rst="0x2">
          <comment/>
        </bits>
        <bits access="rw" name="clk_enable" pos="12" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="ck2lane_edge_sel" pos="13" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="ck2dig_edge_sel" pos="14" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="clk_dly_sel" pos="19:16" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="drv_sel" pos="21:20" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="lp_ldo_bit" pos="23:22" rst="0x2">
          <comment/>
        </bits>
        <bits access="rw" name="hs_ldo_bit" pos="25:24" rst="0x2">
          <comment/>
        </bits>
        <bits access="rw" name="clk_pu_hsldo" pos="26" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="d1_pu_hsldo" pos="27" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="d0_pu_hsldo" pos="28" rst="0x1">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_pll_reg" protect="rw">
        <bits access="rw" name="pll_cpr2_bit" pos="2:0" rst="0x4">
          <comment/>
        </bits>
        <bits access="rw" name="pll_cpc2_ibit" pos="6:4" rst="0x4">
          <comment/>
        </bits>
        <bits access="rw" name="pll_cpbias_ibit" pos="10:8" rst="0x4">
          <comment/>
        </bits>
        <bits access="rw" name="reg_res_bit" pos="13:12" rst="0x2">
          <comment/>
        </bits>
        <bits access="rw" name="pll_vreg_bit" pos="19:16" rst="0x8">
          <comment/>
        </bits>
        <bits access="rw" name="vco_low_test" pos="20" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="vco_high_test" pos="21" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="pll_test_en" pos="22" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="pll_refmulti2_en" pos="23" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="sdm_clk_test_en" pos="24" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="pcon_mode" pos="25" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <hole size="2*32"/>
      <reg name="dsi_misc_ctrl" protect="rw">
        <bits access="rw" name="tx_lp_cmd_dr" pos="12" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="tx_lp_cmd_reg" pos="11:4" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="tx_lp_swap_reg" pos="3" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="rx_lp_lp11_reg" pos="2" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="frz_disable_reg" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="eot_tx_disable_reg" pos="0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <hole size="3*32"/>
      <reg name="dsi_cmd_1_0_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_0_reg" pos="31:0" rst="0x0">
          <comment>
            config the transmission at cmd mode
            <br/>
             [31:24]: data byte 1 of command
            <br/>
             [23:16]: data byte 0 of command
            <br/>
             [15:8]:  data ID of command
            <br/>
             [6:5]:   cmd_type
            <br/>
             	   	     2'b00,01: short packet
            <br/>
             	    	 2'b10,11: long  packet
            <br/>
             [3:2]:   2'b00,2'b01: cmd_ddr_enable
            <br/>
                                   enable to get long packet payload from ddr
            <br/>
              	    2'b10: cmd_buf_enable
            <br/>
                             enable to write frame buffer at cmd mode, only for high speed.
            <br/>
              	    2'b11: cmd_reg_enable
            <br/>
                             enable to get long packet payload from register
            <br/>
             bit1:    cmd_hs_enable
            <br/>
              	   	enable high-speed transmission
            <br/>
             bit0:    cmd_bta_enable
            <br/>
              		enable bta
          </comment>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_1_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_1_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_2_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_2_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_3_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_3_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_4_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_4_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_5_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_5_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_6_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_6_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_7_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_7_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_8_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_8_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_9_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_9_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_a_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_a_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_b_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_b_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_c_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_c_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_d_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_d_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_e_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_e_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_1_f_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_1_f_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_0_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_0_reg" pos="31:0" rst="0x0">
          <comment>
            config the transmission at cmd mode
            <br/>
             [31:24]: data byte 1 of command
            <br/>
             [23:16]: data byte 0 of command
            <br/>
             [15:8]:  data ID of command
            <br/>
             [6:5]:   cmd_type
            <br/>
             	   	 2'b00,01: short packet
            <br/>
             	    	 2'b10,11: long  packet
            <br/>
             [3:2]:   2'b00,2'b01: cmd_ddr_enable
            <br/>
                                   enable to get long packet payload from ddr
            <br/>
              	    2'b10: cmd_buf_enable
            <br/>
                             enable to write frame buffer at cmd mode, only for high speed.
            <br/>
              	    2'b11: cmd_reg_enable
            <br/>
                             enable to get long packet payload from register
            <br/>
             bit1:    cmd_hs_enable
            <br/>
              	   	enable high-speed transmission
            <br/>
             bit0:    cmd_bta_enable
            <br/>
              		enable bta
          </comment>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_1_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_1_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_2_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_2_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_3_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_3_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_4_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_4_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_5_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_5_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_6_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_6_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_7_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_7_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_8_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_8_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_9_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_9_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_a_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_a_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_b_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_b_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_c_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_c_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_d_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_d_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_e_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_e_reg" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_cmd_2_f_reg" protect="rw">
        <bits access="rw" name="dsi_cmd_2_f_reg" pos="31:0" rst="0x0">
          <comment>
            config the transmission at cmd mode
            <br/>
             [31:24]: data byte 1 of command
            <br/>
             [23:16]: data byte 0 of command
            <br/>
             [15:8]:  data ID of command
            <br/>
             [6:5]:   cmd_type
            <br/>
             	   	 2'b00,01: short packet
            <br/>
             	    	 2'b10,11: long  packet
            <br/>
             [3:2]:   2'b00,2'b01: cmd_ddr_enable
            <br/>
                                   enable to get long packet payload from ddr
            <br/>
              	    2'b10: cmd_buf_enable
            <br/>
                             enable to write frame buffer at cmd mode, only for high speed.
            <br/>
              	    2'b11: cmd_reg_enable
            <br/>
                             enable to get long packet payload from register
            <br/>
             bit1:    cmd_hs_enable
            <br/>
              	   	enable high-speed transmission
            <br/>
             bit0:    cmd_bta_enable
            <br/>
              		enable bta
          </comment>
        </bits>
      </reg>
      <reg name="dsi_read_reg0" protect="r">
        <bits access="r" name="read_lcd0" pos="31:0" rst="0x0">
          <comment>
            read from lcd corresponding cmd queue index
            <br/>
             [7:0]:DI
            <br/>
             [15:8]:  SP data0 or LP WC LS BYTE
            <br/>
             [23:16]: SP data1 or LP WC MS BYTE
            <br/>
             [24]: ack  response
            <br/>
             [25]: te   response
            <br/>
             [26]: lpdt response
            <br/>
             [27]: ECC error flag
            <br/>
             [28]: LP CRC error flag
            <br/>
             [29]: Acknowledge and Error Report flag
          </comment>
        </bits>
      </reg>
      <reg name="dsi_read_reg1" protect="r">
        <bits access="r" name="read_lcd1" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg2" protect="r">
        <bits access="r" name="read_lcd2" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg3" protect="r">
        <bits access="r" name="read_lcd3" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg4" protect="r">
        <bits access="r" name="read_lcd4" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg5" protect="r">
        <bits access="r" name="read_lcd5" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg6" protect="r">
        <bits access="r" name="read_lcd6" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg7" protect="r">
        <bits access="r" name="read_lcd7" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg8" protect="r">
        <bits access="r" name="read_lcd8" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg9" protect="r">
        <bits access="r" name="read_lcd9" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg10" protect="r">
        <bits access="r" name="read_lcd10" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg11" protect="r">
        <bits access="r" name="read_lcd11" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg12" protect="r">
        <bits access="r" name="read_lcd12" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg13" protect="r">
        <bits access="r" name="read_lcd13" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg14" protect="r">
        <bits access="r" name="read_lcd14" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg15" protect="r">
        <bits access="r" name="read_lcd15" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg16" protect="r">
        <bits access="r" name="read_lcd16" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg17" protect="r">
        <bits access="r" name="read_lcd17" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg18" protect="r">
        <bits access="r" name="read_lcd18" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg19" protect="r">
        <bits access="r" name="read_lcd19" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg20" protect="r">
        <bits access="r" name="read_lcd20" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg21" protect="r">
        <bits access="r" name="read_lcd21" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg22" protect="r">
        <bits access="r" name="read_lcd22" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg23" protect="r">
        <bits access="r" name="read_lcd23" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg24" protect="r">
        <bits access="r" name="read_lcd24" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg25" protect="r">
        <bits access="r" name="read_lcd25" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg26" protect="r">
        <bits access="r" name="read_lcd26" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg27" protect="r">
        <bits access="r" name="read_lcd27" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg28" protect="r">
        <bits access="r" name="read_lcd28" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg29" protect="r">
        <bits access="r" name="read_lcd29" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg30" protect="r">
        <bits access="r" name="read_lcd30" pos="31:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dsi_read_reg31" protect="r">
        <bits access="r" name="read_lcd31" pos="31:0" rst="0x0">
          <comment>
            read from lcd corresponding cmd queue index
            <br/>
             [7:0]:DI
            <br/>
             [15:8]:  SP data0 or LP WC LS BYTE
            <br/>
             [23:16]: SP data1 or LP WC MS BYTE
            <br/>
             [24]: ack  response
            <br/>
             [25]: te   response
            <br/>
             [26]: lpdt response
            <br/>
             [27]: ECC error flag
            <br/>
             [28]: LP CRC error flag
            <br/>
             [29]: Acknowledge and Error Report flag
          </comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="spi_flash.xml">
    <module category="System" name="SPI_FLASH">
      <reg name="spi_cmd_addr" protect="rw">
        <bits access="rw" name="spi_tx_cmd" pos="7:0" rst="all0">
          <comment>spi flash command to send.</comment>
        </bits>
        <bits access="rw" name="spi_address" pos="31:8" rst="all0">
          <comment>spi flash address to send.</comment>
        </bits>
      </reg>
      <reg name="spi_block_size" protect="rw">
        <bits access="rw" name="spi_modebit" pos="7:0" rst="all0">
          <comment>spi flash modebit,set 0xA0 to enable continuous read.</comment>
        </bits>
        <bits access="rw" name="spi_rw_blk_size" pos="21:8" rst="0x1">
          <comment>spi flash spi read/write block size.</comment>
        </bits>
        <bits access="rw" name="continuous_enable" pos="24" rst="0x0">
        </bits>
      </reg>
      <reg name="spi_data_fifo" protect="rw">
        <bits access="w" name="spi_tx_data" pos="7:0" rst="no">
          <comment>spi flash data to send.</comment>
        </bits>
        <bits access="w" name="spi_send_type" pos="8" rst="no">
          <comment>spi send byte, 1: quad send 0: spi send.</comment>
        </bits>
      </reg>
      <reg name="spi_status" protect="r">
        <bits access="r" name="spi_flash_busy" pos="0" rst="0x0">
          <comment>spi flash busy.</comment>
        </bits>
        <bits access="r" name="tx_fifo_empty" pos="1" rst="0x1">
          <comment>tx fifo empty.</comment>
        </bits>
        <bits access="r" name="tx_fifo_full" pos="2" rst="0x0">
          <comment>tx fifo full.</comment>
        </bits>
        <bits access="r" name="rx_fifo_empty" pos="3" rst="0x1">
          <comment>rx fifo empty.</comment>
        </bits>
        <bits access="r" name="rx_fifo_count" pos="8:4" rst="all0">
          <comment>rx fifo data count.</comment>
        </bits>
        <bits access="r" name="read_stat_busy" pos="9" rst="0x0">
          <comment>read busy.</comment>
        </bits>
        <bits access="r" name="nand_int" pos="10" rst="0x0">
          <comment>nand int .</comment>
        </bits>
        <bits access="r" name="spiflash_int" pos="11" rst="0x0">
          <comment>spiflash_int = nand_int and nand_int_mask .</comment>
        </bits>
      </reg>
      <reg name="spi_read_back" protect="r">
        <bits access="r" name="rx_status" pos="31:0" rst="0x0">
          <comment>flash rx status.</comment>
        </bits>
      </reg>
      <reg name="spi_config" protect="rw">
        <bits access="rw" name="quad_mode" pos="0" rst="0x0">
          <comment>spi flash read mode from AHB.</comment>
          <options>
            <option name="spi read" value="0"/>
            <option name="quad read" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="spi_wprotect_pin" pos="1" rst="0x0">
          <comment>spi flash wprotect pin.</comment>
        </bits>
        <bits access="rw" name="spi_hold_pin" pos="2" rst="0x0">
          <comment>spi flash hold pin.</comment>
        </bits>
        <bits access="rw" name="sample_delay" pos="6:4" rst="0x2">
          <comment>spi flash read sample delay cycles.</comment>
        </bits>
        <bits access="rw" name="clk_divider" pos="15:8" rst="0x8">
          <comment>spi flash clock divider.</comment>
        </bits>
        <bits access="rw" name="cmd_quad" pos="16" rst="0x0">
          <comment>spi flash send command using quad lines.</comment>
        </bits>
        <bits access="rw" name="tx_rx_size" pos="18:17" rst="0x0">
        </bits>
      </reg>
      <reg name="spi_fifo_control" protect="w">
        <bits access="w" name="rx_fifo_clr" pos="0" rst="0x0">
          <comment>rx fifo_clr,self clear.</comment>
        </bits>
        <bits access="w" name="tx_fifo_clr" pos="1" rst="0x0">
          <comment>tx fifo_clr,self clear.</comment>
        </bits>
      </reg>
      <reg name="spi_cs_size" protect="rw">
        <bits access="rw" name="spi_cs_num" pos="0" rst="0x0">
          <comment>spi flash cs num.</comment>
          <options>
            <option name="1 spiflash" value="0"/>
            <option name="2 spiflash" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="spi size" pos="2:1" rst="all0">
          <comment>single chip spi flash size.</comment>
          <options>
            <option name="32m" value="0"/>
            <option name="64m" value="1"/>
            <option name="16m" value="2"/>
            <option name="8m" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="spi_128m" pos="3" rst="0x0">
          <comment>spi flash is 128m flash.</comment>
          <options>
            <option name="other spiflash" value="0"/>
            <option name="128m  spiflash" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="ahb_read_disable" pos="4" rst="0x0">
          <comment>disable read from ahb.</comment>
          <options>
            <option name="enable ahb read" value="0"/>
            <option name="disable ahb read" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="sel_flash_1" pos="5" rst="0x0">
          <comment>sel flash 1, addr[24].</comment>
          <options>
            <option name="sel flash 0" value="0"/>
            <option name="sel flash 1" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="sel1_flash_1" pos="6" rst="0x0">
          <comment>addr[25].</comment>
        </bits>
        <bits access="rw" name="diff_128m_diff_cmd_en" pos="7" rst="0x0">
          <comment>diff 128m diff cmd en.</comment>
        </bits>
        <bits access="rw" name="spi_256m" pos="8" rst="0x0">
          <comment>spi_256m.</comment>
        </bits>
        <bits access="rw" name="spi_512m" pos="9" rst="0x0">
          <comment>spi_512m.</comment>
        </bits>
        <bits access="rw" name="spi_cs1_sel2" pos="10" rst="0x0">
          <comment>spi_cs1_sel2.</comment>
        </bits>
        <bits access="rw" name="spi_1g" pos="11" rst="0x0">
          <comment>spi_1g .</comment>
        </bits>
        <bits access="rw" name="spi_2g" pos="12" rst="0x0">
          <comment>spi_2g.</comment>
        </bits>
        <bits access="rw" name="spi_4g" pos="13" rst="0x0">
          <comment>spi_4g.</comment>
        </bits>
        <bits access="rw" name="spi_cs1_sel3" pos="14" rst="0x0">
          <comment>spi_cs1_sel3.</comment>
        </bits>
        <bits access="rw" name="spi_cs1_sel4" pos="15" rst="0x0">
          <comment>spi_cs1_sel4.</comment>
        </bits>
        <bits access="rw" name="spi_cs1_sel5" pos="16" rst="0x0">
          <comment>spi_cs1_sel5.</comment>
        </bits>
      </reg>
      <reg name="spi_read_cmd" protect="rw">
        <bits access="rw" name="qread_cmd" pos="7:0" rst="0xeb">
          <comment>quad read command.</comment>
        </bits>
        <bits access="rw" name="fread_cmd" pos="15:8" rst="0x0b">
          <comment>fast read command.</comment>
        </bits>
        <bits access="rw" name="read_cmd" pos="23:16" rst="0x03">
          <comment>fast read command.</comment>
        </bits>
        <bits access="w" name="protect_byte" pos="31:24" rst="all0">
          <comment>protect_byte, must be 0x55 when program this register.</comment>
        </bits>
      </reg>
      <reg name="spi_nand_config" protect="rw">
        <bits access="rw" name="nand_sel" pos="0" rst="all0">
		</bits>
        <bits access="rw" name="nand_addr" pos="2:1" rst="all0">
        </bits>
        <bits access="rw" name="reuse_nand_ram" pos="3" rst="all0">
        </bits>
        <bits access="rw" name="reuse_read" pos="4" rst="all0">
        </bits>
        <bits access="rw" name="write_page_hit" pos="5" rst="all0">
        </bits>
        <bits access="rw" name="nand_data_trans" pos="6" rst="all0">
        </bits>
        <bits access="rw" name="page_size_sel" pos="7" rst="all0">
		</bits>
        <bits access="rw" name="page_read_cmd" pos="15:8" rst="0x13">
        </bits>
        <bits access="rw" name="get_sts_cmd" pos="23:16" rst="0x0f">
        </bits>
        <bits access="rw" name="ram_read_cmd" pos="31:24" rst="0x03">
        </bits>
      </reg>
      <reg name="spi_nand_config2" protect="rw">
        <bits access="rw" name="get_sts_addr" pos="7:0" rst="0xc0">
        </bits>
        <bits access="rw" name="sts_qip" pos="23:16" rst="0x01">
        </bits>
      </reg>
      <reg name="spi_256_512_flash_config" protect="rw">
        <bits access="rw" name="four_byte_addr" pos="0" rst="all0">
		</bits>
        <bits access="rw" name="dummy_cycle_en" pos="1" rst="all0">
		</bits>
        <bits access="rw" name="dummy_cycle" pos="11:8" rst="0x08">
        </bits>
        <bits access="rw" name="wrap_en" pos="12" rst="all0">
        </bits>
        <bits access="rw" name="wrap_code" pos="19:16" rst="all0">
        </bits>
      </reg>
      <reg name="spi_128_flash_config" protect="rw">
        <bits access="rw" name="first_128m_cmd" pos="7:0" rst="0x8c">
		</bits>
        <bits access="rw" name="second_128m_cmd" pos="15:8" rst="0x8d">
        </bits>
        <bits access="rw" name="third_128m_cmd" pos="23:16" rst="0x0">
        </bits>
        <bits access="rw" name="fourth_128m_cmd" pos="31:24" rst="0x0">
        </bits>
      </reg>
      <reg name="spi_cs4_sel" protect="rw">
        <bits access="rw" name="spi_cs4_sel" pos="2:0" rst="0x0">
		</bits>
      </reg>
      <reg name="page0_addr" protect="rw">
        <bits access="rw" name="page0_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page0_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page1_addr" protect="rw">
        <bits access="rw" name="page1_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page1_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page2_addr" protect="rw">
        <bits access="rw" name="page2_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page2_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page3_addr" protect="rw">
        <bits access="rw" name="page3_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page3_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page4_addr" protect="rw">
        <bits access="rw" name="page4_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page4_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page5_addr" protect="rw">
        <bits access="rw" name="page5_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page5_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page6_addr" protect="rw">
        <bits access="rw" name="page6_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page6_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page7_addr" protect="rw">
        <bits access="rw" name="page7_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page7_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page8_addr" protect="rw">
        <bits access="rw" name="page8_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page8_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page9_addr" protect="rw">
        <bits access="rw" name="page9_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page9_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page10_addr" protect="rw">
        <bits access="rw" name="page10_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page10_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page11_addr" protect="rw">
        <bits access="rw" name="page11_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page11_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page12_addr" protect="rw">
        <bits access="rw" name="page12_addr" pos="23:0" rst="0x0">
        </bits>
        <bits access="rw" name="page12_valid" pos="31" rst="0x0">
		</bits>
      </reg>
      <reg name="page13_addr" protect="rw">
        <bits access="rw" name="page13_addr" pos="23:0" rst="0x0">
         </bits>
        <bits access="rw" name="page13_valid" pos="31" rst="0x0">
	 	</bits>
      </reg>
      <reg name="page14_addr" protect="rw">
        <bits access="rw" name="page14_addr" pos="23:0" rst="0x0">
         </bits>
        <bits access="rw" name="page14_valid" pos="31" rst="0x0">
	 	</bits>
      </reg>
      <reg name="page15_addr" protect="rw">
        <bits access="rw" name="page15_addr" pos="23:0" rst="0x0">
         </bits>
        <bits access="rw" name="page15_valid" pos="31" rst="0x0">
	 	</bits>
      </reg>
      <reg name="spi_page_config" protect="rw">
        <bits access="rw" name="multi_page_enable/multi_page_start" pos="0" rst="0x0">
         </bits>
        <bits access="rw" name="page_num" pos="12:8" rst="0x0">
	 	</bits>
      </reg>
      <reg name="spi_cmd_reconfig" protect="rw">
        <bits access="rw" name="program_exe_cmd" pos="7:0" rst="0x0">
         </bits>
        <bits access="rw" name="program_load_cmd" pos="15:8" rst="0x0">
         </bits>
        <bits access="rw" name="write_enable_cmd" pos="23:16" rst="0x0">
         </bits>
      </reg>
      <reg name="page0_col_addr" protect="rw">
        <bits access="rw" name="page0_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page1_col_addr" protect="rw">
        <bits access="rw" name="page1_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page2_col_addr" protect="rw">
        <bits access="rw" name="page2_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page3_col_addr" protect="rw">
        <bits access="rw" name="page3_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page4_col_addr" protect="rw">
        <bits access="rw" name="page4_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page5_col_addr" protect="rw">
        <bits access="rw" name="page5_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page6_col_addr" protect="rw">
        <bits access="rw" name="page6_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page7_col_addr" protect="rw">
        <bits access="rw" name="page7_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page8_col_addr" protect="rw">
        <bits access="rw" name="page8_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page9_col_addr" protect="rw">
        <bits access="rw" name="page9_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page10_col_addr" protect="rw">
        <bits access="rw" name="page10_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page11_col_addr" protect="rw">
        <bits access="rw" name="page11_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page12_col_addr" protect="rw">
        <bits access="rw" name="page12_col_addr" pos="15:0" rst="0x0">
        </bits>
      </reg>
      <reg name="page13_col_addr" protect="rw">
        <bits access="rw" name="page13_col_addr" pos="15:0" rst="0x0">
         </bits>
      </reg>
      <reg name="page14_col_addr" protect="rw">
        <bits access="rw" name="page14_col_addr" pos="15:0" rst="0x0">
         </bits>
      </reg>
      <reg name="page15_col_addr" protect="rw">
        <bits access="rw" name="page15_col_addr" pos="15:0" rst="0x0">
         </bits>
      </reg>
      <reg name="nand_int_mask" protect="rw">
        <bits access="rw" name="nand_int_mask" pos="0" rst="0x0">
		</bits>
      </reg>
    </module>
  </archive>
  <archive relative="gic400_reg.xml">
    <module category="System" name="GIC400">
      <hole size="32768"/>
      <reg name="gicd_ctrl" protect="rw">
        <bits access="rw" name="enablegrp1" pos="1" rst="0">
          <comment>Global enable for forwarding pending Group 1 interrupts from the Distributor to the CPU interfaces:
          0    Group 1 interrupts not forward.
          1    Group 1 interrupts forwarded, subject to the priority rules.</comment>
        </bits>
        <bits access="rw" name="enablegrp0" pos="0" rst="0">
          <comment>Global enable for forwarding pending Group 0 interrupts from the Distributor to the CPU interfaces:
          0    Group 0 interrupts not forwarded.
          1    Group 0 interrupts forwarded, subject to the priority rules.</comment>
        </bits>
      </reg>
      <reg name="gicd_typer" protect="r">
        <bits access="r" name="lspi" pos="15:11" rst="31">
          <comment>If the GIC implements the Security Extensions, the value of this field is the maximum number of
          implemented lockable SPIs, from 0 (0b00000) to 31 (0b11111), see Configuration lockdown on
          page 4-82. If this field is 0b00000 then the GIC does not implement configuration lockdown.
          If the GIC does not implement the Security Extensions, this field is reserved.</comment>
        </bits>
        <bits access="r" name="securityextn" pos="10" rst="1">
          <comment>Indicates whether the GIC implements the Security Extensions.
          0 Security Extensions not implemented.
          1 Security Extensions implemented.</comment>
        </bits>
        <bits access="r" name="cpunumber" pos="7:5" rst="1">
          <comment>Indicates the number of implemented CPU interfaces. The number of implemented CPU interfaces is
          one more than the value of this field, for example if this field is 0b011, there are four CPU interfaces.
          If the GIC implements the Virtualization Extensions, this is also the number of virtual CPU interfaces.</comment>
        </bits>
        <bits access="r" name="itlinesnumber" pos="4:0" rst="3">
          <comment>Indicates the maximum number of interrupts that the GIC supports. If ITLinesNumber=N, the
          maximum number of interrupts is 32(N+1). The interrupt ID range is from 0 to (number of IDs C 1).
          For example:
          0b00011 Up to 128 interrupt lines, interrupt IDs 0-127.
          The maximum number of interrupts is 1020 (0b11111). See the text in this section for more information.
          Regardless of the range of interrupt IDs defined by this field, interrupt IDs 1020-1023 are reserved for
          special purposes.</comment>
        </bits>
      </reg>
      <reg name="gicd_iddr" protect="r">
        <bits access="r" name="productid" pos="31:24" rst="2">
          <comment>Product ID</comment>
        </bits>
        <bits access="r" name="variant" pos="19:16" rst="0">
          <comment>An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish product variants,
          or major revisions of a product.</comment>
        </bits>
        <bits access="r" name="revision" pos="15:12" rst="1">
          <comment>An IMPLEMENTATION DEFINED revision number. Typically, this field is used to distinguish minor revisions
          of a product.</comment>
        </bits>
        <bits access="r" name="implementer" pos="11:0" rst="1083">
          <comment>Contains the JEP106 code of the company that implemented the GIC Distributor:
          Bits [11:8] The JEP106 continuation code of the implementer. For an ARM implementation, this field
          is 0x4.
          Bits [7] Always 0.
          Bits [6:0] The JEP106 identity code of the implementer. For an ARM implementation, bits[7:0] are
          0x3B.</comment>
        </bits>
      </reg>
      <hole size="928"/>
      <reg count="4" name="gicd_igrouprn" protect="rw">
        <bits access="rw" name="group_status_bits" pos="31:0" rst="0">
          <comment>The GICD_IGROUPR registers provide a status bit for each interrupt supported by the GIC.
          Each bit controls whether the corresponding interrupt is in Group 0 or Group 1.
          Accessible by Secure accesses Only.
          For each bit:
          0 The corresponding interrupt is Group 0.
          1 The corresponding interrupt is Group 1.For interrupt ID m, when DIV and MOD are the integer division and
          modulo operations:
          a. the corresponding GICD_IGROUPRn number, n, is given by n = m DIV 32
          b. the offset of the required GICD_IGROUPR is (0x080 + (4*n))
          c. the bit number of the required group status bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <hole size="896"/>
      <reg name="gicd_isenabler0" protect="rw">
        <bits access="rw" name="set_enable_bits" pos="31:0" rst="65535">
          <comment>The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC.
          For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to
          the CPU interfaces:
          Reads  0 Forwarding of the corresponding interrupt is disabled.
                 1 Forwarding of the corresponding interrupt is enabled.
          Writes 0 Has no effect.
                 1 Enables the forwarding of the corresponding interrupt.
          After a write of 1 to a bit, a subsequent read of the bit returns the value 1.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32
          b.the offset of the required GICD_ISENABLER is (0x100 + (4*n))
          c.the bit number of the required Set-enable bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <reg name="gicd_isenabler1" protect="rw">
        <bits access="rw" name="set_enable_bits" pos="31:0" rst="0">
          <comment>The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC.
          For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to
          the CPU interfaces:
          Reads  0 Forwarding of the corresponding interrupt is disabled.
                 1 Forwarding of the corresponding interrupt is enabled.
          Writes 0 Has no effect.
                 1 Enables the forwarding of the corresponding interrupt.
          After a write of 1 to a bit, a subsequent read of the bit returns the value 1.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32
          b.the offset of the required GICD_ISENABLER is (0x100 + (4*n))
          c.the bit number of the required Set-enable bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <reg name="gicd_isenabler2" protect="rw">
        <bits access="rw" name="set_enable_bits" pos="31:0" rst="0">
          <comment>The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC.
          For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to
          the CPU interfaces:
          Reads  0 Forwarding of the corresponding interrupt is disabled.
                 1 Forwarding of the corresponding interrupt is enabled.
          Writes 0 Has no effect.
                 1 Enables the forwarding of the corresponding interrupt.
          After a write of 1 to a bit, a subsequent read of the bit returns the value 1.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32
          b.the offset of the required GICD_ISENABLER is (0x100 + (4*n))
          c.the bit number of the required Set-enable bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <reg name="gicd_isenabler3" protect="rw">
        <bits access="rw" name="set_enable_bits" pos="31:0" rst="0">
          <comment>The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC.
          For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to
          the CPU interfaces:
          Reads  0 Forwarding of the corresponding interrupt is disabled.
                 1 Forwarding of the corresponding interrupt is enabled.
          Writes 0 Has no effect.
                 1 Enables the forwarding of the corresponding interrupt.
          After a write of 1 to a bit, a subsequent read of the bit returns the value 1.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32
          b.the offset of the required GICD_ISENABLER is (0x100 + (4*n))
          c.the bit number of the required Set-enable bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <hole size="896"/>
      <reg name="gicd_icenabler0" protect="rw">
        <bits access="rw" name="clear_enable_bits" pos="31:0" rst="65535">
          <comment>The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the
          GIC.
          For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to
          the CPU interfaces:
          Reads  0 Forwarding of the corresponding interrupt is disabled.
                 1 Forwarding of the corresponding interrupt is enabled.
          Writes 0 Has no effect.
                 1 Disables the forwarding of the corresponding interrupt.
          After a write of 1 to a bit, a subsequent read of the bit returns the value 0.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32
          b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n))
          c.the bit number of the required Clear-enable bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <reg name="gicd_icenabler1" protect="rw">
        <bits access="rw" name="clear_enable_bits" pos="31:0" rst="0">
          <comment>The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the
          GIC.
          For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to
          the CPU interfaces:
          Reads  0 Forwarding of the corresponding interrupt is disabled.
                 1 Forwarding of the corresponding interrupt is enabled.
          Writes 0 Has no effect.
                 1 Disables the forwarding of the corresponding interrupt.
          After a write of 1 to a bit, a subsequent read of the bit returns the value 0.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32
          b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n))
          c.the bit number of the required Clear-enable bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <reg name="gicd_icenabler2" protect="rw">
        <bits access="rw" name="clear_enable_bits" pos="31:0" rst="0">
          <comment>The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the
          GIC.
          For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to
          the CPU interfaces:
          Reads  0 Forwarding of the corresponding interrupt is disabled.
                 1 Forwarding of the corresponding interrupt is enabled.
          Writes 0 Has no effect.
                 1 Disables the forwarding of the corresponding interrupt.
          After a write of 1 to a bit, a subsequent read of the bit returns the value 0.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32
          b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n))
          c.the bit number of the required Clear-enable bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <reg name="gicd_icenabler3" protect="rw">
        <bits access="rw" name="clear_enable_bits" pos="31:0" rst="0">
          <comment>The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the
          GIC.
          For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to
          the CPU interfaces:
          Reads  0 Forwarding of the corresponding interrupt is disabled.
                 1 Forwarding of the corresponding interrupt is enabled.
          Writes 0 Has no effect.
                 1 Disables the forwarding of the corresponding interrupt.
          After a write of 1 to a bit, a subsequent read of the bit returns the value 0.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32
          b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n))
          c.the bit number of the required Clear-enable bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <hole size="896"/>
      <reg count="4" name="gicd_ispendrn" protect="rw">
        <bits access="rw" name="set_pending_bits" pos="31:0" rst="0">
          <comment>The GICD_ISPENDRs provide a Set-pending bit for each interrupt supported by the GIC.
          For each bit:
          Reads 0  The corresponding interrupt is not pending on any processor.
                1  a. For PPIs and SGIs, the corresponding interrupt is pendinga on this
                      processor.
                   b. For SPIs, the corresponding interrupt is pendinga on at least one
                      processor.
          Writes For SPIs and PPIs:
                0  Has no effect.
                1  The effect depends on whether the interrupt is edge-triggered or
                   level-sensitive:
                   Edge-triggered
                         Changes the status of the corresponding interrupt to:
                         a.pending if it was previously inactive
                         b.active and pending if it was previously active.
                         Has no effect if the interrupt is already pending.
                   Level sensitive
                         If the corresponding interrupt is not pendinga, changes the status
                         of the corresponding interrupt to:
                         a. pending if it was previously inactive
                         b. active and pending if it was previously active.
                         If the interrupt is already pending:
                         a. because of a write to the GICD_ISPENDR, the write has
                           no effect.
                         b. because the corresponding interrupt signal is asserted, the
                           write has no effect on the status of the interrupt, but the
                           interrupt remains pendinga if the interrupt signal is
                           deasserted.
                For SGIs, the write is ignored. SGIs have their own Set-Pending registers.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ISPENDR number, n, is given by n = m DIV 32
          b. the offset of the required GICD_ISPENDR is (0x200 + (4*n))
          c. the bit number of the required Set-pending bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <hole size="896"/>
      <reg count="4" name="gicd_icpendrn" protect="rw">
        <bits access="rw" name="clear_pending_bits" pos="31:0" rst="0">
          <comment>The GICD_ICPENDRs provide a Clear-pending bit for each interrupt supported by the GIC.
          For each bit:
          Reads 0   The corresponding interrupt is not pending on any processor.
                1   a. For SGIs and PPIs, the corresponding interrupt is pendinga on this
                       processor.
                    b. For SPIs, the corresponding interrupt is pendinga on at least one
                       processor.
          Writes For SPIs and PPIs:
                0   Has no effect.
                1   The effect depends on whether the interrupt is edge-triggered or level-sensitive:
                    Edge-triggered
                          Changes the status of the corresponding interrupt to:
                          a. inactive if it was previously pending
                          b. active if it was previously active and pending.
                          Has no effect if the interrupt is not pending.
                    Level-sensitive
                          If the corresponding interrupt is pendinga only because of a write to
                          GICD_ISPENDRn, the write changes the status of the interrupt to:
                          a. inactive if it was previously pending
                          b. active if it was previously active and pending.
                          Otherwise the interrupt remains pending if the interrupt signal
                          remains asserted.
                For SGIs, the write is ignored. SGIs have their own Clear-Pending registers.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ICPENDR number, n, is given by n = m DIV 32
          b. the offset of the required GICD_ICPENDR is (0x280 + (4*n))
          c. the bit number of the required Set-pending bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <hole size="896"/>
      <reg count="4" name="gicd_isactivern" protect="rw">
        <bits access="rw" name="set_active_bits" pos="31:0" rst="0">
          <comment>The GICD_ISACTIVERs provide a Set-active bit for each interrupt that the GIC supports.
          For each bit:
          Reads  0  The corresponding interrupt is not active.
                 1  The corresponding interrupt is active.
          Writes 0  Has no effect.
                 1  Activates the corresponding interrupt, if it is not already active. If the interrupt
                    is already active, the write has no effect.
                    After a write of 1 to this bit, a subsequent read of the bit returns the value 1.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ISACTIVERn number, n, is given by n = m DIV 32
          b. the offset of the required GICD_ISACTIVERn is (0x300 + (4*n))
          c. the bit number of the required Set-active bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <hole size="896"/>
      <reg count="4" name="gicd_icactivern" protect="rw">
        <bits access="rw" name="clear_active_bits" pos="31:0" rst="0">
          <comment>The GICD_ICACTIVERs provide a Clear-active bit for each interrupt that the GIC
          supports.
          For each bit:
          Reads  0  The corresponding interrupt is not activea.
                 1  The corresponding interrupt is activea.
          Writes 0  Has no effect.
                 1  Deactivates the corresponding interrupt, if the interrupt is active. If the
                    interrupt is already deactivated, the write has no effect.
                    After a write of 1 to this bit, a subsequent read of the bit returns the value 0.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ICACTIVERn number, n, is given by n = m DIV 32
          b. the offset of the required GICD_ICACTIVERn is (0x380 + (4*n))
          c. the bit number of the required Clear-active bit in this register is m MOD 32.</comment>
        </bits>
      </reg>
      <hole size="896"/>
      <reg count="32" name="gicd_ipriorityrn" protect="rw">
        <bits access="rw" name="priority" pos="31:0" rst="0">
          <comment>The GICD_IPRIORITYRs provide an 8-bit priority field for each interrupt supported by the
          GIC.
          Each priority field holds a priority value, from an IMPLEMENTATION DEFINED range. The lower the
          value, the greater the priority of the corresponding interrupt.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_IPRIORITYRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_IPRIORITYRn is (0x400 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <hole size="7168"/>
      <reg name="gicd_itargetsr0" protect="r">
        <bits access="r" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr1" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr2" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr3" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr4" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr5" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr6" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr7" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr8" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr9" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr10" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr11" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr12" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr13" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr14" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr15" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr16" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr17" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr18" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr19" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr20" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr21" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr22" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr23" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr24" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr25" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr26" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr27" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr28" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr29" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr30" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <reg name="gicd_itargetsr31" protect="rw">
        <bits access="rw" name="cpu_targets" pos="31:0" rst="0">
          <comment>The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported
          by the GIC.This field stores the list of target processors for the interrupt. That is, it holds
          the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and
          has sufficient priority.
          GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns
          a value that corresponds only to the processor reading the register.
          Processors in the system number from 0, and each bit in a CPU targets field refers to the
          corresponding processor. For example, a value of 0x3 means that the Pending
          interrupt is sent to processors 0 and 1.
          For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns
          the number of the processor performing the read.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4
          b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n))
          c. the byte offset of the required Priority field in this register is m MOD 4, where:
             (1) byte offset 0 refers to register bits [7:0]
             (2) byte offset 1 refers to register bits [15:8]
             (3) byte offset 2 refers to register bits [23:16]
             (4) byte offset 3 refers to register bits [31:24].</comment>
        </bits>
      </reg>
      <hole size="7168"/>
      <reg name="gicd_icfgr0" protect="rw">
        <bits access="rw" name="int_config" pos="31:0" rst="2863311530">
          <comment>The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC.
          For Int_config[1], the most significant bit, bit [2F+1], the encoding is:
          0 Corresponding interrupt is level-sensitive.
          1 Corresponding interrupt is edge-triggered.
          Int_config[0], the least significant bit, bit [2F], reserved
          For SGIs:
          Int_config[1] Not programmable, RAO/WI.
          For PPIs:
          Int_config[1] Not programmable, RAZ/WI.
          For SPIs:
          Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value
          to indicate whether the corresponding interrupt is level-sensitive or edge-triggered.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16
          b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n))
          c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits
          [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30].</comment>
        </bits>
      </reg>
      <reg name="gicd_icfgr1" protect="rw">
        <bits access="rw" name="int_config" pos="31:0" rst="1431568384">
          <comment>The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC.
          For Int_config[1], the most significant bit, bit [2F+1], the encoding is:
          0 Corresponding interrupt is level-sensitive.
          1 Corresponding interrupt is edge-triggered.
          Int_config[0], the least significant bit, bit [2F], reserved
          For SGIs:
          Int_config[1] Not programmable, RAO/WI.
          For PPIs:
          Int_config[1] Not programmable, RAZ/WI.
          For SPIs:
          Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value
          to indicate whether the corresponding interrupt is level-sensitive or edge-triggered.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16
          b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n))
          c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits
          [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30].</comment>
        </bits>
      </reg>
      <reg name="gicd_icfgr2" protect="rw">
        <bits access="rw" name="int_config" pos="31:0" rst="1431655765">
          <comment>The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC.
          For Int_config[1], the most significant bit, bit [2F+1], the encoding is:
          0 Corresponding interrupt is level-sensitive.
          1 Corresponding interrupt is edge-triggered.
          Int_config[0], the least significant bit, bit [2F], reserved
          For SGIs:
          Int_config[1] Not programmable, RAO/WI.
          For PPIs:
          Int_config[1] Not programmable, RAZ/WI.
          For SPIs:
          Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value
          to indicate whether the corresponding interrupt is level-sensitive or edge-triggered.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16
          b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n))
          c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits
          [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30].</comment>
        </bits>
      </reg>
      <reg name="gicd_icfgr3" protect="rw">
        <bits access="rw" name="int_config" pos="31:0" rst="1431655765">
          <comment>The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC.
          For Int_config[1], the most significant bit, bit [2F+1], the encoding is:
          0 Corresponding interrupt is level-sensitive.
          1 Corresponding interrupt is edge-triggered.
          Int_config[0], the least significant bit, bit [2F], reserved
          For SGIs:
          Int_config[1] Not programmable, RAO/WI.
          For PPIs:
          Int_config[1] Not programmable, RAZ/WI.
          For SPIs:
          Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value
          to indicate whether the corresponding interrupt is level-sensitive or edge-triggered.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16
          b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n))
          c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits
          [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30].</comment>
        </bits>
      </reg>
      <reg name="gicd_icfgr4" protect="rw">
        <bits access="rw" name="int_config" pos="31:0" rst="1431655765">
          <comment>The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC.
          For Int_config[1], the most significant bit, bit [2F+1], the encoding is:
          0 Corresponding interrupt is level-sensitive.
          1 Corresponding interrupt is edge-triggered.
          Int_config[0], the least significant bit, bit [2F], reserved
          For SGIs:
          Int_config[1] Not programmable, RAO/WI.
          For PPIs:
          Int_config[1] Not programmable, RAZ/WI.
          For SPIs:
          Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value
          to indicate whether the corresponding interrupt is level-sensitive or edge-triggered.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16
          b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n))
          c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits
          [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30].</comment>
        </bits>
      </reg>
      <reg name="gicd_icfgr5" protect="rw">
        <bits access="rw" name="int_config" pos="31:0" rst="1431655765">
          <comment>The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC.
          For Int_config[1], the most significant bit, bit [2F+1], the encoding is:
          0 Corresponding interrupt is level-sensitive.
          1 Corresponding interrupt is edge-triggered.
          Int_config[0], the least significant bit, bit [2F], reserved
          For SGIs:
          Int_config[1] Not programmable, RAO/WI.
          For PPIs:
          Int_config[1] Not programmable, RAZ/WI.
          For SPIs:
          Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value
          to indicate whether the corresponding interrupt is level-sensitive or edge-triggered.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16
          b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n))
          c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits
          [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30].</comment>
        </bits>
      </reg>
      <reg name="gicd_icfgr6" protect="rw">
        <bits access="rw" name="int_config" pos="31:0" rst="1431655765">
          <comment>The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC.
          For Int_config[1], the most significant bit, bit [2F+1], the encoding is:
          0 Corresponding interrupt is level-sensitive.
          1 Corresponding interrupt is edge-triggered.
          Int_config[0], the least significant bit, bit [2F], reserved
          For SGIs:
          Int_config[1] Not programmable, RAO/WI.
          For PPIs:
          Int_config[1] Not programmable, RAZ/WI.
          For SPIs:
          Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value
          to indicate whether the corresponding interrupt is level-sensitive or edge-triggered.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16
          b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n))
          c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits
          [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30].</comment>
        </bits>
      </reg>
      <reg name="gicd_icfgr7" protect="rw">
        <bits access="rw" name="int_config" pos="31:0" rst="1431655765">
          <comment>The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC.
          For Int_config[1], the most significant bit, bit [2F+1], the encoding is:
          0 Corresponding interrupt is level-sensitive.
          1 Corresponding interrupt is edge-triggered.
          Int_config[0], the least significant bit, bit [2F], reserved
          For SGIs:
          Int_config[1] Not programmable, RAO/WI.
          For PPIs:
          Int_config[1] Not programmable, RAZ/WI.
          For SPIs:
          Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value
          to indicate whether the corresponding interrupt is level-sensitive or edge-triggered.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16
          b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n))
          c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits
          [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30].</comment>
        </bits>
      </reg>
      <hole size="1792"/>
      <reg name="gicd_ppisr" protect="r">
        <bits access="r" name="ppi_status" pos="15:9" rst="0">
          <comment>Asserted when the PPI inputs to the Distributor are active.
          ID 31 nLEGACYIRQ signal
          ID 30 Non-secure physical timer event
          ID 29 Secure physical timer event
          ID 28 nLEGACYFIQ signal
          ID 27 Virtual timer event
          ID 26 Hypervisor timer event
          ID 25 Virtual maintenance interrupt.</comment>
        </bits>
      </reg>
      <reg count="3" name="gicd_spisrn" protect="r">
        <bits access="r" name="spis_status" pos="31:0" rst="0">
          <comment>Returns the status of the IRQS inputs on the Distributor. For each bit:
          0 IRQS is LOW
          1 IRQS is HIGH.</comment>
        </bits>
      </reg>
      <hole size="1920"/>
      <reg count="8" name="gicd_nsacrn" protect="rw">
        <bits access="rw" name="ns_access" pos="31:0" rst="0">
          <comment>The GICD_NSACRs enable Secure software to permit Non-secure software on a particular
          processor to create and manage Group 0 interrupts. They provide an access control for each
          implemented interrupt.
          If the corresponding interrupt does not support configurable Non-secure access, the field is
          RAZ/WI. Otherwise, the field is RW and configures the level of Non-secure access permitted
          when the interrupt is in Group 0. If the interrupt is in Group 1, this field is ignored. The possible
          values of the field are:
          0b00 No Non-secure access is permitted to fields associated with the corresponding
               interrupt.
          0b01 Non-secure write access is permitted to fields associated with the corresponding
               interrupt in the GICD_ISPENDRn registers. A Non-secure write access to
               GICD_SGIR is permitted to generate a Group 0 SGI for the corresponding
               interrupt.
          0b10 Adds Non-secure write access permission to fields associated with the
               corresponding interrupt in the GICD_ICPENDRn registers. Also adds
               Non-secure read access permission to fields associated with the corresponding
               interrupt in the GICD_ISACTIVERn and GICD_ICACTIVERn registers.
          0b11 Adds Non-secure read and write access permission to fields associated with the
               corresponding interrupt in the GICD_ITARGETSRn registers.
          The GICD_NSACRn registers do not support PPI accesses, meaning that GICD_NSACR0 bits [31:16] are
          RAZ/WI.
          For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
          a. the corresponding GICD_NSACR number, n, is given by n = m DIV 16
          b. the offset of the required GICD_NSACRn is (0xE00 + (4*n)).</comment>
        </bits>
      </reg>
      <hole size="1792"/>
      <reg name="gicd_sgir" protect="rw">
        <bits access="w" name="targetlistfilter" pos="25:24" rst="0">
          <comment>Determines how the distributor must process the requested SGI:
          0b00 Forward the interrupt to the CPU interfaces specified in the CPUTargetList fielda.
          0b01 Forward the interrupt to all CPU interfaces except that of the processor that requested the
               interrupt.
          0b10 Forward the interrupt only to the CPU interface of the processor that requested the
               interrupt.
          0b11 Reserved.</comment>
        </bits>
        <bits access="w" name="cputargetlist" pos="23:16" rst="0">
          <comment>When TargetList Filter = 0b00, defines the CPU interfaces to which the Distributor must forward the
          interrupt.
          Each bit of CPUTargetList[7:0] refers to the corresponding CPU interface, for example
          CPUTargetList[0] corresponds to CPU interface 0. Setting a bit to 1 indicates that the interrupt must be
          forwarded to the corresponding interface.
          If this field is 0x00 when TargetListFilter is 0b00, the Distributor does not forward the interrupt to any
          CPU interface.</comment>
        </bits>
        <bits access="w" name="nsatt" pos="15" rst="0">
          <comment>Implemented only if the GIC includes the Security Extensions.
          Specifies the required security value of the SGI:
          0   Forward the SGI specified in the SGIINTID field to a specified CPU interface only if the
              SGI is configured as Group 0 on that interface.
          1   Forward the SGI specified in the SGIINTID field to a specified CPU interfaces only if
              the SGI is configured as Group 1 on that interface.
          This field is writable only by a Secure access. Any Non-secure write to the GICD_SGIR generates an
          SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit[15] of the write.</comment>
        </bits>
        <bits access="w" name="sgiintid" pos="3:0" rst="0">
          <comment>The Interrupt ID of the SGI to forward to the specified CPU interfaces. The value of this field is the
          Interrupt ID, in the range 0-15, for example a value of 0b0011 specifies Interrupt ID 3.</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg count="4" name="gicd_cpendsgirn" protect="rw">
        <bits access="rw" name="sgi_clear_pending" pos="31:0" rst="0">
          <comment>The GICD_CPENDSGIRs provide a clear-pending bit for each supported SGI and source
          processor combination.
          For each bit:
          Reads  0 SGI x from the corresponding processor is not pending.
                 1 SGI x from the corresponding processor is pending.
          Writes 0 Has no effect.
                 1 Removes the pending state of SGI x for the corresponding processor.
          For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and
          modulo operations:
          a. the corresponding GICD_CPENDSGIR register number, n, is given by n = x DIV 4
          b. the offset of the required GICD_CPENDSGIR is (0xF10 + (4*n));
          c. the SGI Clear-pending field offset, y, is given by y = x MOD 4
          d. the required bit in the SGI x Clear-pending field is bit C.</comment>
        </bits>
      </reg>
      <reg count="4" name="gicd_spendsgirn" protect="rw">
        <bits access="rw" name="sgi_set_pending" pos="31:0" rst="0">
          <comment>The GICD_SPENDSGIRn registers provide a set-pending bit for each supported SGI and
          source processor combination.
          For each bit:
          Reads  0 SGI x for the corresponding processor is not pendinga.
                 1 SGI x for the corresponding processor is pendinga.
          Writes 0 Has no effect.
                 1 Adds the pending state of SGI x for the corresponding processor,
                   if it is not already pending. If SGI x is already pending for the
                   corresponding processor then the write has no effect.
          For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and
          modulo operations:
          a. the corresponding GICD_SPENDSGIR register number, n, is given by n = x DIV 4
          b. the offset of the required GICD_SPENDSGIR is (0xF20 + (4*n))
          c. the SGI Set-pending field offset, y, is given by y = x MOD 4
          d. the required bit in the SGI x Set-pending field is bit C.</comment>
        </bits>
      </reg>
      <hole size="1664"/>
      <reg name="gicc_ctrl" protect="rw">
        <bits access="rw" name="eoimodens" pos="10" rst="0">
          <comment>Alias of EOImodeNS from the Non-secure copy of this register.</comment>
        </bits>
        <bits access="rw" name="eoimodes" pos="9" rst="0">
          <comment>Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers. In a GIC implementation
          that includes the Security Extensions, this control applies only to Secure accesses, and the EOImodeNS
          bit controls the behavior of Non-secure accesses to these registers:
          0   GICC_EOIR has both priority drop and deactivate interrupt functionality. Accesses to
              the GICC_DIR are UNPREDICTABLE.
          1   GICC_EOIR has priority drop functionality only. GICC_DIR has deactivate interrupt
              functionality.</comment>
        </bits>
        <bits access="rw" name="irqbypdisgrp1" pos="8" rst="0">
          <comment>Alias of IRQBypDisGrp1 from the Non-secure copy of this register.</comment>
        </bits>
        <bits access="rw" name="fiqbypdisgrp1" pos="7" rst="0">
          <comment>Alias of FIQBypDisGrp1 from the Non-secure copy of this register.</comment>
        </bits>
        <bits access="rw" name="irqbypdisgrp0" pos="6" rst="0">
          <comment>When the signaling of IRQs by the CPU interface is disabled, this bit partly controls whether the bypass
          IRQ signal is signaled to the processor:
          0 Bypass IRQ signal is signaled to the processor
          1 Bypass IRQ signal is not signaled to the processor.</comment>
        </bits>
        <bits access="rw" name="fiqbypdisgrp0" pos="5" rst="0">
          <comment>When the signaling of FIQs by the CPU interface is disabled, this bit partly controls whether the bypass
          FIQ signal is signaled to the processor:
          0 Bypass FIQ signal is signaled to the processor
          1 Bypass FIQ signal is not signaled to the processor.</comment>
        </bits>
        <bits access="rw" name="cbpr" pos="4" rst="0">
          <comment>Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts.
          0 To determine any preemption, use:
          ? the GICC_BPR for Group 0 interrupts
          ? the GICC_ABPR for Group 1 interrupts.
          1 To determine any preemption use the GICC_BPR for both Group 0 and Group 1
          interrupts.</comment>
        </bits>
        <bits access="rw" name="fiqen" pos="3" rst="0">
          <comment>Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or
          the IRQ signal.
          0 Signal Group 0 interrupts using the IRQ signal.
          1 Signal Group 0 interrupts using the FIQ signal.
          The GIC always signals Group 1 interrupts using the IRQ signal.</comment>
        </bits>
        <bits access="rw" name="ackctl" pos="2" rst="0">
          <comment>When the highest priority pending interrupt is a Group 1 interrupt, determines both:
          ? whether a read of GICC_IAR acknowledges the interrupt, or returns a spurious interrupt ID
          ? whether a read of GICC_HPPIR returns the ID of the highest priority pending interrupt, or
          returns a spurious interrupt ID.
          0 If the highest priority pending interrupt is a Group 1 interrupt, a read of the GICC_IAR
          or the GICC_HPPIR returns an Interrupt ID of 1022. A read of the GICC_IAR does
          not acknowledge the interrupt, and has no effect on the pending status of the interrupt.
          1 If the highest priority pending interrupt is a Group 1 interrupt, a read of the GICC_IAR
          or the GICC_HPPIR returns the Interrupt ID of the Group 1 interrupt. A read of
          GICC_IAR acknowledges and Activates the interrupt.</comment>
        </bits>
        <bits access="rw" name="enablegrp1" pos="1" rst="0">
          <comment>Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor:
          0 Disable signaling of Group 1 interrupts.
          1 Enable signaling of Group 1 interrupts.</comment>
        </bits>
        <bits access="rw" name="enablegrp0" pos="0" rst="0">
          <comment>Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor:
          0 Disable signaling of Group 0 interrupts.
          1 Enable signaling of Group 0 interrupts.</comment>
        </bits>
      </reg>
      <reg name="gicc_pmr" protect="rw">
        <bits access="rw" name="priority" pos="7:0" rst="0">
          <comment>The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
          value indicated by this field, the interface signals the interrupt to the processor.
          If the GIC supports fewer than 256 priority levels then some bits are RAZ/WI, as follows:
          128 supported levels Bit [0] = 0.
          64 supported levels Bit [1:0] = 0b00.
          32 supported levels Bit [2:0] = 0b000.
          16 supported levels Bit [3:0] = 0b0000.</comment>
        </bits>
      </reg>
      <reg name="gicc_bpr" protect="rw">
        <bits access="rw" name="binary_point" pos="2:0" rst="2">
          <comment>The value of this field controls how the 8-bit interrupt priority field is split into a group
          priority field, used to determine interrupt preemption, and a subpriority field.
          The minimum value of the Binary Point Register depends on which
          security-banked copy is considered:
          0x2 Secure copy
          0x3 Non-secure copy</comment>
        </bits>
      </reg>
      <reg name="gicc_iar" protect="r">
        <bits access="r" name="cpuid" pos="12:10" rst="0">
          <comment>For SGIs in a multiprocessor implementation, this field identifies the processor that
          requested the interrupt. It returns the number of the CPU interface that made the
          request, for example a value of 3 means the request was generated by a write to the
          GICD_SGIR on CPU interface 3.
          For all other interrupts this field is RAZ.</comment>
        </bits>
        <bits access="r" name="interrupt_id" pos="9:0" rst="1023">
          <comment>The interrupt ID.</comment>
        </bits>
      </reg>
      <reg name="gicc_eoir" protect="rw">
        <bits access="w" name="cpuid" pos="12:10" rst="0">
          <comment>On a multiprocessor implementation, if the write refers to an SGI, this
          the CPUID value from the corresponding GICC_IAR access.
          In all other cases this field SBZ.</comment>
        </bits>
        <bits access="w" name="eoiintid" pos="9:0" rst="0">
          <comment>The Interrupt ID value from the corresponding GICC_IAR access.</comment>
        </bits>
      </reg>
      <reg name="gicc_rpr" protect="r">
        <bits access="r" name="priority" pos="7:0" rst="255">
          <comment>The current running priority on the CPU interface.</comment>
        </bits>
      </reg>
      <reg name="gicc_hppir" protect="r">
        <bits access="r" name="cpuid" pos="12:10" rst="0">
          <comment>On a multiprocessor implementation, if the PENDINTID field returns the ID of an
          SGI, this field contains the CPUID value for that interrupt. This identifies the
          processor that generated the interrupt.
          In all other cases this field is RAZ.</comment>
        </bits>
        <bits access="r" name="pendintid" pos="9:0" rst="1023">
          <comment>The interrupt ID of the highest priority pending interrupt. See Table 4-42 on
          page 4-144 for more information about the result of Non-secure reads of the
          GICC_HPPIR when the GIC implements the Security Extensions.</comment>
        </bits>
      </reg>
      <reg name="gicc_abpr" protect="rw">
        <bits access="rw" name="binary_point" pos="2:0" rst="3">
          <comment>A Binary Point Register for handling Group 1 interrupts.</comment>
        </bits>
      </reg>
      <reg name="gicc_aiar" protect="r">
        <bits access="r" name="cpuid" pos="12:10" rst="0">
          <comment>CPUID For SGIs in a multiprocessor implementation, this field identifies the processor that
          requested the interrupt. It returns the number of the CPU interface that made the request,
          for example a value of 3 means the request was generated by a write to the GICD_SGIR
          on CPU interface 3.
          For all other interrupts this field is RAZ.</comment>
        </bits>
        <bits access="r" name="interrupt_id" pos="9:0" rst="1023">
          <comment>Interrupt ID The interrupt ID.</comment>
        </bits>
      </reg>
      <reg name="gicc_aeoir" protect="rw">
        <bits access="w" name="cpuid" pos="12:10" rst="0">
          <comment>On a multiprocessor implementation, when processing an SGI, this field must contain
          the CPUID value from the corresponding GICC_AIAR, or Non-secure GICC_IAR,
          access.
          In all other cases this field SBZ.</comment>
        </bits>
        <bits access="w" name="interrupt_id" pos="9:0" rst="0">
          <comment>The Interrupt ID value from the corresponding GICC_AIAR, or Non-secure GICC_IAR,
          access.</comment>
        </bits>
      </reg>
      <reg name="gicc_ahppir" protect="r">
        <bits access="r" name="cpuid" pos="12:10" rst="0">
          <comment>On a multiprocessor implementation, if the PENDINTID field returns the ID of an
          SGI, this field contains the CPUID value for that interrupt. This identifies the
          processor that generated the interrupt.
          In all other cases this field is RAZ.</comment>
        </bits>
        <bits access="r" name="pendintid" pos="9:0" rst="1023">
          <comment>The interrupt ID of the highest priority pending interrupt, if that interrupt is a Group 1
          interrupt. Otherwise, the spurious interrupt ID, 1023.</comment>
        </bits>
      </reg>
      <hole size="1312"/>
      <reg name="gicc_aprn" protect="rw">
        <bits access="rw" name="active_priority" pos="31:0" rst="0">
          <comment>Active Priorities Registers</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="gicc_nsaprn" protect="rw">
        <bits access="rw" name="ns_active_priority" pos="31:0" rst="0">
          <comment>NonSecure Active Priorities Registers</comment>
        </bits>
      </reg>
      <hole size="192"/>
      <reg name="gicc_iidr" protect="r">
        <bits access="r" name="productid" pos="31:24" rst="2">
          <comment>An IMPLEMENTATION DEFINED product identifier.</comment>
        </bits>
        <bits access="r" name="architecture_version" pos="19:16" rst="2">
          <comment>The value of this field depends on the GIC architecture version, as follows:
          ? 0x1 for GICv1
          ? 0x2 for GICv2.</comment>
        </bits>
        <bits access="r" name="revision" pos="15:12" rst="1">
          <comment>An IMPLEMENTATION DEFINED revision number for the CPU interface.</comment>
        </bits>
        <bits access="r" name="implementer" pos="11:0" rst="1083">
          <comment>Contains the JEP106 code of the company that implemented the GIC CPU
          interface:
          Bits [11:8] The JEP106 continuation code of the implementer.
          Bit  [7]    Always 0.
          Bits [6:0] The JEP106 identity code of the implementer.</comment>
        </bits>
      </reg>
      <hole size="30720"/>
      <reg name="gicc_dir" protect="rw">
        <bits access="w" name="cpuid" pos="12:10" rst="0">
          <comment>For an SGI in a multiprocessor implementation, this field
          identifies the processor that requested the interrupt.
          For all other interrupts this field is RAZ.</comment>
        </bits>
        <bits access="w" name="interrupt_id" pos="9:0" rst="0">
          <comment>The interrupt ID</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="gpio.xml">
    <include file="gallite_generic_config.xml"/>
    <var name="IDX_GPIO_DCON" value="0"/>
    <var name="IDX_GPO_CHG" value="0"/>
    <module category="Periph" name="GPIO">
      <reg name="gpio_oen_val" protect="rw">
        <bits access="rw" display="hex" name="oen_val" pos="NB_GPIO-1:0" rst="0xffffffff">
          <options>
            <option name="INPUT" value="1"/>
            <option name="OUTPUT" value="0"/>
            <default/>
          </options>
          <comment>
            Set the direction of the GPIO n.
            <br/>
            0 = output
            <br/>
            1 =
      input
          </comment>
        </bits>
      </reg>
      <reg name="gpio_oen_set_out" protect="rw">
        <bits access="rc" name="oen_set_out" pos="NB_GPIO-1:0" rst="0xffffffff">
          <comment>'Write '1' sets the corresponding GPIO pin as output.</comment>
        </bits>
      </reg>
      <reg name="gpio_oen_set_in" protect="rw">
        <bits access="rs" display="hex" name="oen_set_in" pos="NB_GPIO-1:0" rst="0xffffffff">
          <comment>'Write '1' sets the corresponding GPIO pin as input.</comment>
        </bits>
      </reg>
      <reg name="gpio_val_reg" protect="rw">
        <bits access="rw" display="hex" name="gpio_val" pos="NB_GPIO-1:0" rst="0x00000000">
          <comment>When write, update the output value. When read, get the input
      value.</comment>
        </bits>
      </reg>
      <reg name="gpio_set_reg" protect="rw">
        <bits access="rs" name="gpio_set" pos="NB_GPIO-1:0" rst="0xffffffff">
          <comment>Write '1' will set GPIO output value. When read, get the GPIO
      output value.</comment>
        </bits>
      </reg>
      <reg name="gpio_clr_reg" protect="rw">
        <bits access="rc" name="gpio_clr" pos="NB_GPIO-1:0" rst="0xffffffff">
          <comment>'Write '1' clears corresponding GPIO output value. When read, get the GPIO
      output value.</comment>
        </bits>
      </reg>
      <reg name="gpint_ctrl_r_set_reg" protect="rw">
        <bits access="rs" name="gpint_ctrl_r_set" pos="NB_GPIO-1:0" rst="0">
          <comment>'Write '1' will set GPIO interrupt mask for rising edge and
      level high. When read, get the GPIO interrupt mask for rising edge and
      level high.</comment>
        </bits>
      </reg>
      <reg name="gpint_ctrl_r_clr_reg" protect="rw">
        <bits access="rc" name="gpint_ctrl_r_clr" pos="NB_GPIO-1:0" rst="0">
          <comment>'Write '1' will clear GPIO interrupt mask for rising edge and
      level high.</comment>
        </bits>
      </reg>
      <reg name="int_clr" protect="w">
        <bits access="c" name="gpint_clr" pos="NB_GPIO_INT-1:0" rst="0">
          <comment>'Write '1' will clear GPIO interrupt.</comment>
        </bits>
      </reg>
      <reg name="int_status" protect="r">
        <bits access="r" name="gpint_status" pos="NB_GPIO_INT-1:0" rst="0">
          <comment>Each bit represents if there is a GPIO interrupt
      pending.</comment>
          <options>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <reg name="chg_ctrl" protect="rw">
        <bits access="rw" display="hex" name="out_time" pos="3:0" rst="0xf">
          <comment>
            time for which GPIO0 is set to output mode, after a start read
            DCON command is issued.
            <br/>
            The output time = (OUT_TIME+1)*30.5us.
          </comment>
        </bits>
        <bits access="rw" display="hex" name="wait_time" pos="9:4" rst="0x3f">
          <comment>
            time for which GPIO0 should wait before reading DC_ON, after
            a start read DCON command is issued.
            <br/>
            The wait time = (WAIT_TIME+1)*30.5us.
            <br/>
            NOTE: wait_time must be strictly greater than out_time;
          </comment>
        </bits>
        <bits access="rw" display="hex" name="int_mode" pos="17:16" rst="0x3">
          <comment>
            interruption mode of GPIO0 in mode DC_ON detection.
            <br/>
          </comment>
          <options>
            <option name="L2H" value="0">
              <comment>&quot;00&quot; = send IRQ if last read DCON is '0' and now is '1'.</comment>
            </option>
            <option name="H2L" value="1">
              <comment>&quot;01&quot; = send IRQ if last read DCON is '1' and now is '0'.</comment>
            </option>
            <option name="RR" value="3">
              <comment>&quot;11&quot; = send IRQ every time read is ready.</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="chg_cmd" protect="w">
        <bits access="s" name="dcon_mode_set" pos="0" rst="0">
          <comment>Write '1' to set GPIO0 to charger DCON detect mode.</comment>
        </bits>
        <bits access="s" name="chg_mode_set" pos="4" rst="0">
          <comment>Write '1' to set GPO0 to charger watchdog mode.</comment>
        </bits>
        <bits access="c" name="dcon_mode_clr" pos="8" rst="0">
          <comment>Write '1' to clear charger DCON detect mode of GPIO0.</comment>
        </bits>
        <bits access="c" name="chg_mode_clr" pos="12" rst="0">
          <comment>Write '1' to clear the charger watchdog mode of GPO0.</comment>
        </bits>
        <bits access="s" name="chg_down" pos="24" rst="0">
          <comment>Write '1' to generate a pulse of '0' on GPO0 for 16 CLK_OSC cycles.</comment>
        </bits>
      </reg>
      <reg name="gpo_set_reg" protect="rw">
        <bits access="rs" display="hex" name="gpo_set" pos="NB_GPO-1:0" rst="0xaa">
          <comment>'Write '1' will set GPO output value. When read, get the GPO
      output value.</comment>
        </bits>
      </reg>
      <reg name="gpo_clr_reg" protect="rw">
        <bits access="rc" display="hex" name="gpo_clr" pos="NB_GPO-1:0" rst="0xaa">
          <comment>'Write '1' will clear GPO output value. When read, get the GPO
      output value.</comment>
        </bits>
      </reg>
      <reg name="gpint_ctrl_f_set_reg" protect="rw">
        <bits access="rs" name="gpint_ctrl_f_set" pos="NB_GPIO-1:0" rst="0">
          <comment>'Write '1' will set GPIO interrupt mask for rising edge and
      level high. When read, get the GPIO interrupt mask for rising edge and
      level high.</comment>
        </bits>
      </reg>
      <reg name="gpint_ctrl_f_clr_reg" protect="rw">
        <bits access="rc" name="gpint_ctrl_f_clr" pos="NB_GPIO-1:0" rst="0">
          <comment>'Write '1' will clear GPIO interrupt mask for rising edge and
      level high.</comment>
        </bits>
      </reg>
      <reg name="dbn_en_set_reg" protect="rw">
        <bits access="rs" name="dbn_en_set" pos="NB_GPIO-1:0" rst="0xffffffff">
          <comment>'Write '1' will enable debounce mechanism.</comment>
        </bits>
      </reg>
      <reg name="dbn_en_clr_reg" protect="rw">
        <bits access="rc" name="dbn_en_clr" pos="NB_GPIO-1:0" rst="0xffffffff">
          <comment>'Write '1' will disable debounce mechanism.</comment>
        </bits>
      </reg>
      <reg name="gpint_mode_set_reg" protect="rw">
        <bits access="rs" name="gpint_mode_set" pos="NB_GPIO-1:0" rst="0">
          <comment>Write '1' will set interruption mode to level.</comment>
        </bits>
      </reg>
      <reg name="gpint_mode_clr_reg" protect="rw">
        <bits access="rc" name="gpint_mode_clr" pos="NB_GPIO-1:0" rst="0">
          <comment>Write '1' will set interruption mode to edge
      triggered.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="i2c_master.xml">
    <module category="Periph" name="I2C_MASTER">
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="en" pos="0" rst="0">
          <comment>I2C master enable, high active.</comment>
        </bits>
        <bits access="rw" name="irq_mask" pos="8" rst="0">
          <comment>I2C master interrupt enable, high active.</comment>
        </bits>
        <bits access="rw" name="clock_prescale" pos="31:16" rst="0xFFFF">
          <comment>
            This register is used to prescale the SCL clock line. Due to the structure of I2C interface, this module uses a 5*SCL clock frequency. Clock_Prescale must be programmed to this 5*SCL clock frequency (minus 1). Change the value of Clock_Prescale only when bit EN is cleared.
            <br/>
            <br/>
             Example:
            <br/>
             PCLK_MOD is 52 MHz, desired SCL is 100 KHz.
            <br/>
             Prescale = 52MHz / (5 * 100KHz) -1 = 103.
          </comment>
          <options>
            <mask/>
          </options>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="irq_cause" pos="0" rst="0">
          <comment>IRQ Cause bit. This bit is set when one byte transfer has been completed or arbitration is lost, this bit is generated by bit IRQ_Status AND bit IRQ_MASK.</comment>
        </bits>
        <bits access="r" name="irq_status" pos="4" rst="0">
          <comment>IRQ status bit.</comment>
        </bits>
        <bits access="r" name="tip" pos="8" rst="0">
          <comment>TIP, Transfer in progress.
				'1' when transferring data. '0' when transfer complete.</comment>
        </bits>
        <bits access="r" name="al" pos="12" rst="0">
          <comment>AL,Arbitration lost.
				This bit is set when the I2C master lost arbitration.</comment>
        </bits>
        <bits access="r" name="busy" pos="16" rst="0">
          <comment>Busy,I2C bus busy.
				'1' after START signal detected.
				'0' after STOP signal detected.</comment>
        </bits>
        <bits access="r" name="rxack" pos="20" rst="0">
          <comment>RxACK, Received acknowledge from slave.
				'1'= &quot;No ACK&quot; received.
				'0'= ACK received.</comment>
        </bits>
      </reg>
      <reg name="txrx_buffer" protect="rw">
        <bits access="w" name="tx_data" pos="7:0" rst="-">
          <comment>
            Byte to transmit via I2C.
            <br/>
             for Bit 0, In case of a data transfer this bit represents the data's LSB. In case of a slave address transfer this bit represents the RW bit.
            <br/>
             '1' = reading from slave.
            <br/>
             '0' = writing to slave.
          </comment>
        </bits>
        <bits access="r" name="rx_data" pos="7:0" rst="-">
          <comment>Last byte received via I2C.</comment>
        </bits>
      </reg>
      <reg name="cmd" protect="w">
        <bits access="w" name="ack" pos="0" rst="0">
          <comment>ACK,when master works as a receiver,sent ACK(ACK='0') or NACK(ACK='1').</comment>
        </bits>
        <bits access="w" name="rd" pos="4" rst="0">
          <comment>RD,read from slave, this bit is auto cleared.</comment>
        </bits>
        <bits access="w" name="sto" pos="8" rst="0">
          <comment>STO,generate stop condition, this bit is auto cleared.</comment>
        </bits>
        <bits access="w" name="rw" pos="12" rst="0">
          <comment>WR,write to slave, this bit is auto cleared.</comment>
        </bits>
        <bits access="w" name="sta" pos="16" rst="0">
          <comment>STA,generate (repeated) start condition, this bit is auto cleared.</comment>
        </bits>
      </reg>
      <reg name="irq_clr" protect="rw">
        <bits access="c" name="irq_clr" pos="0" rst="0">
          <comment>When write '1', clears a pending I2C interrupt.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="pagespy_dmc.xml">
    <module category="Debug" name="PAGESPY_DMC">
      <var name="PAGESPY_DMC_NB_PAGE" value="8"/>
      <var name="PAGESPY_DMC_AXI_ID_WIDTH" value="9"/>
      <struct count="PAGESPY_DMC_NB_PAGE" name="page">
        <reg name="mon_ctrl" protect="rw">
          <bits access="rw" name="mon_ctrl_sr" pos="0" rst="0">
            <comment>Write  0: disable pagespy; 1: enable pagespy
                   Read   0: pagespy idle;    1: pagespy active</comment>
          </bits>
        </reg>
        <reg name="mon_conf" protect="rw">
          <bits access="rw" cut="1" cutprefix="mon_sysifsel" name="mon_sysifsel" pos="1:0" rst="all0">
            <comment>Spy interface select,
                 'b00: interface 0, 'b01: interface 1,
                 'b10: interface 2, 'b11: interface 3.</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="mon_time_en" name="mon_time_en" pos="2" rst="0">
            <comment>Enable of One configured time monitor mode.
                 When timer reaches the time threshold,
                 this bit clear to 0 automatically.</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="mon_long_en" name="mon_long_en" pos="3" rst="0">
            <comment>Enable of long time continuously monitor mode.</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="mon_num_en" name="mon_num_en" pos="4" rst="0">
            <comment>Enable of a configured access threshold mode.
                 When accesses reaches the threshold,
                 this bit clear to 0 automatically.</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="mon_hit_en" name="mon_hit_en" pos="5" rst="0">
            <comment>Enable of address hit mode.
                 Once one access hit the configured address range,
                 this bit clear to 0 automatically.</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="mon_hit_detectw" name="mon_hit_detectw" pos="6" rst="0">
            <comment>enable monitoring write address hit.</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="mon_hit_detectr" name="mon_hit_detectr" pos="7" rst="0">
            <comment>enable monitoring read address hit.</comment>
          </bits>
          <bitgroup name="mon_hit_mode">
            <entry ref="mon_hit_detectw"/>
            <entry ref="mon_hit_detectr"/>
          </bitgroup>
        </reg>
        <reg name="mon_start_addr" protect="rw">
          <bits access="rw" name="mon_start_addr" pos="27:0" rst="all0">
            <comment>high 28bit of start address of monitor.</comment>
          </bits>
        </reg>
        <reg name="mon_end_addr" protect="rw">
          <bits access="rw" name="mon_end_addr" pos="27:0" rst="all0">
            <comment>high 28bit of end address of monitor.</comment>
          </bits>
        </reg>
        <reg name="mon_int_en" protect="rw">
          <bits access="rw" name="timer_int_en" pos="0" rst="0">
            <comment>enable timer reach threshold interrupt.</comment>
          </bits>
          <bits access="rw" name="num_int_en" pos="1" rst="0">
            <comment>enable access reach threshold interrupt</comment>
          </bits>
          <bits access="rw" name="hit_int_en" pos="2" rst="0">
            <comment>enable access hit interrupt</comment>
          </bits>
        </reg>
        <reg name="mon_int_status" protect="rw">
          <bits access="rw" cut="1" cutprefix="time_int_status" name="time_int_status" pos="0" rst="0">
            <comment>In one configured time monitor mode,
                   when timer reach the time threshold, this interrupt source trigger.
                   Write 1: clear interrupt; 0: ignored
                   Read  1: the one has source triggerd; 0: not source triggerd</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="long_int_status" name="long_int_status" pos="1" rst="0">
            <comment>In long time continuously monitor mode,
                   when timer reach the time threshold, this interrupt source trigger.
                   Write 1: clear interrupt; 0: ignored
                   Read  1: the one has source triggerd; 0: not source triggerd</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="write_num_int_status" name="write_num_int_status" pos="2" rst="0">
            <comment>In the configured access threshold monitor mode,
                   when write access num reaches the threshold, this interrupt source trigger.
                   Write 1: clear interrupt; 0: ignored
                   Read  1: the one has source triggerd; 0: not source triggerd</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="read_num_int_status" name="read_num_int_status" pos="3" rst="0">
            <comment>In the configured access threshold monitor mode,
                   when read access num reaches the threshold, this interrupt source trigger.
                   Write 1: clear interrupt; 0: ignored
                   Read  1: the one has source triggerd; 0: not source triggerd</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="write_hit_int_status" name="write_hit_int_status" pos="4" rst="0">
            <comment>In the address hit monitor mode,
                   when one write access hit the address range, this interrupt source trigger.
                   Write 1: clear interrupt; 0: ignored
                   Read  1: the one has source triggerd; 0: not source triggerd</comment>
          </bits>
          <bits access="rw" cut="1" cutprefix="read_hit_int_status" name="read_hit_int_status" pos="5" rst="0">
            <comment>In the address hit monitor mode,
                   when one read access hit the address range, this interrupt source trigger.
                   Write 1: clear interrupt; 0: ignored
                   Read  1: the one has source triggerd; 0: not source triggerd</comment>
          </bits>
        </reg>
        <reg name="mon_int_cause" protect="r">
          <bits access="r" cut="1" cutprefix="time_int_cause" name="time_int_cause" pos="0" rst="0">
      </bits>
          <bits access="r" cut="1" cutprefix="long_int_cause" name="long_int_cause" pos="1" rst="0">
      </bits>
          <bits access="r" cut="1" cutprefix="write_num_int_cause" name="write_num_int_cause" pos="2" rst="0">
      </bits>
          <bits access="r" cut="1" cutprefix="read_num_int_cause" name="read_num_int_cause" pos="3" rst="0">
      </bits>
          <bits access="r" cut="1" cutprefix="write_hit_int_cause" name="write_hit_int_cause" pos="4" rst="0">
      </bits>
          <bits access="r" cut="1" cutprefix="read_hit_int_cause" name="read_hit_int_cause" pos="5" rst="0">
      </bits>
        </reg>
        <reg name="mon_timer_th" protect="rw">
          <bits access="rw" name="mon_timer_threshold" pos="31:0" rst="all1">
      </bits>
        </reg>
        <reg name="write_bytes_sr" protect="r">
          <bits access="r" name="write_bytes_sr" pos="31:0" rst="all0">
            <comment>Write bytes when a monitor finishes in one configured time monitor mode
                   or long time continuously monitor mode.</comment>
          </bits>
        </reg>
        <reg name="read_bytes_sr" protect="r">
          <bits access="r" name="read_bytes_sr" pos="31:0" rst="all0">
            <comment>Read bytes when a monitor finishes in one configured time monitor mode or
                   long time continuously monitor mode.</comment>
          </bits>
        </reg>
        <reg name="timer_count" protect="r">
          <bits access="r" name="timer_count" pos="31:0" rst="all0">
            <comment>Current timer count value</comment>
          </bits>
        </reg>
        <reg name="mon_num_th" protect="rw">
          <bits access="rw" name="mon_num_threshold" pos="31:0" rst="all1">
            <comment/>
          </bits>
        </reg>
        <reg name="hit_info" protect="r">
          <bits access="r" cut="1" cutprefix="hit_aburst" name="hit_aburst" pos="1:0" rst="all0">
            <comment/>
          </bits>
          <bits access="r" cut="1" cutprefix="hit_asize" name="hit_asize" pos="4:2" rst="all0">
            <comment/>
          </bits>
          <bits access="r" cut="1" cutprefix="hit_alen" name="hit_alen" pos="8:5" rst="all0">
            <comment/>
          </bits>
          <bits access="r" cut="1" cutprefix="hit_aid" name="hit_aid" pos="PAGESPY_DMC_AXI_ID_WIDTH+8:9" rst="all0">
            <comment/>
          </bits>
        </reg>
        <reg name="hit_addr" protect="r">
          <bits access="r" name="hit_addr" pos="31:0" rst="all0">
            <comment/>
          </bits>
        </reg>
        <hole size="32"/>
        <reg name="int_vec" protect="r">
          <bits access="r" name="int_vec" pos="15:0" rst="all0">
            <comment>interrupt vector for all 16 pagespy channels</comment>
          </bits>
        </reg>
      </struct>
    </module>
  </archive>
  <archive relative="vad.xml">
    <module category="System" name="VAD">
      <reg name="vad_system" protect="rw">
        <bits access="r" name="second_enable" pos="21" rst="0">
          <comment>Enable signal from1 Stage to 2 Stage:
1: 2 Stage work;
0: 2 Stage not work, HOLD state;</comment>
        </bits>
        <bits access="r" name="rstn_inner" pos="20" rst="0">
          <comment>Inner Enable signal from 2 Stage
Control followed module : vad_2stg_probvad_2stg_para_update_feature_minvad_2stg_para_updatemean_adjust.
Not Control module vadflag_smooth.
1: Controlled modules work
0: Controlled modules not work</comment>
        </bits>
        <bits access="rw" name="dma_en" pos="19" rst="0">
          <comment>1:vad_dma_req_h is valid
0:vad_dma_req_h is invalid</comment>
        </bits>
        <bits access="r" name="vad_int_mask" pos="18:16" rst="0">
          <comment>[18]:masked vadflag interrupt
[17]:masked wr_full interrupt
[16]:masked rd_empty interrupt</comment>
        </bits>
        <bits access="r" name="vad_int_raw" pos="14:12" rst="0">
          <comment>[14]:raw vadflag interrupt
[13]:raw wr_full interrupt
[12]:raw rd_empty interrupt</comment>
        </bits>
        <bits access="rw" name="force_2stg_work_en" pos="11" rst="0">
          <comment>Force 2 Stage continue work
1: Force 2 Stage continue work
0: 2Stage normal work (depend vadflag..)</comment>
        </bits>
        <bits access="rw" name="vad_int_clr" pos="10:8" rst="0">
          <comment>Interrupt clear
[10]:clear  vadflag interrupt
[9]:clear   wr_full interrupt
[8]:clear  rd_empty interrupt</comment>
        </bits>
        <bits access="rw" name="frame_ind_mask" pos="7" rst="0">
          <comment>Enable frame vad_int_pulse(width is 500ns)</comment>
        </bits>
        <bits access="rw" name="vad_int_en" pos="6:4" rst="0">
          <comment>[18]:mask vadflag interrupt
[17]:mask wr_full interrupt
[16]:mask rd_empty interrupt</comment>
        </bits>
        <bits access="rw" name="sel_16k" pos="3" rst="0">
          <comment>1:write into mem data rate is 16K (hpf_out)
0:write into mem data rate is 8K(hbf_out)</comment>
        </bits>
        <bits access="rw" name="fix_prob_para" pos="2" rst="0">
          <comment>1:Probability four channel coeff(speech_means,noise_means,speech_std,noise_std)
0:Probability four channel coeff from para_update 4 channel output</comment>
        </bits>
        <bits access="rw" name="para_update_openloop" pos="1" rst="0">
          <comment>1:speech_means_adj[i] and noise_means_adj[i] of para_update input  is fixed at 100
0:speech_means_adj[i] and noise_means_adj[i] of para_update input  is from means_adjust</comment>
        </bits>
        <bits access="rw" name="fix_feature_min" pos="0" rst="0">
          <comment>1:feature_min of noise_mean is fixed at 512
0:feature_min of noise_mean is normal output</comment>
        </bits>
      </reg>
      <reg name="vad_04" protect="rw">
        <bits access="rw" name="hpf_bypass" pos="16" rst="0">
          <comment>1:bypass HPF, note: the output is input reduces hpf_dc_cal
0:normal HPF output</comment>
        </bits>
        <bits access="rw" name="hpf_dc_cal" pos="15:0" rst="0">
          <comment>The DC of hpf</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="vad_0c" protect="rw">
        <bits access="rw" name="hpf_coef_a1" pos="29:16" rst="0">
          <comment>The coeff of hpf</comment>
        </bits>
        <bits access="rw" name="hpf_coef_a2" pos="13:0" rst="0">
          <comment>The coeff of hpf</comment>
        </bits>
      </reg>
      <reg name="vad_10" protect="rw">
        <bits access="rw" name="lpf_bypass" pos="24" rst="0">
          <comment>1:bypass LPF
0:normal LPF output.</comment>
        </bits>
        <bits access="rw" name="lpf_coef_a1" pos="23:12" rst="0">
          <comment>The coeff of lpf</comment>
        </bits>
        <bits access="rw" name="lpf_coef_a2" pos="11:0" rst="0">
          <comment>The coeff of lpf</comment>
        </bits>
      </reg>
      <reg name="vad_14" protect="rw">
        <bits access="rw" name="lpf_coef_g" pos="31:21" rst="0">
          <comment>The gain of lpf</comment>
        </bits>
        <bits access="rw" name="rela_thd" pos="20:16" rst="0">
          <comment>relative threshold</comment>
        </bits>
        <bits access="rw" name="mean_noise_ini" pos="15:0" rst="0">
          <comment>The initial of mean_noise.
ABS thd = mean_noise * rela_thd. The cmp_trigger signal depending the comparation between ABS thd and lpf_out's absolute value</comment>
        </bits>
      </reg>
      <reg name="vad_18" protect="rw">
        <bits access="rw" name="refresh_timer" pos="31:16" rst="0">
          <comment>mean_noise changed in every refresh timer
The refresh_timer is more than average_timer</comment>
        </bits>
        <bits access="rw" name="average_timer_sel" pos="9:8" rst="0">
          <comment>00:begin average_timer = 16'd127 ;cut_bit = 4'd7; end
01:begin average_timer = 16'd255 ;cut_bit = 4'd8; end
10:begin average_timer = 16'd511 ;cut_bit = 4'd9; end
11:begin average_timer = 16'd1023;cut_bit = 4'd10;end</comment>
        </bits>
        <bits access="rw" name="individualtest" pos="6:0" rst="0">
          <comment>unsigned threshold value
When LLR[k]*4 &gt; individualtest, vadflag is 1,otherwise 0</comment>
        </bits>
      </reg>
      <reg name="vad_1c" protect="rw">
        <bits access="rw" name="totaltest" pos="19:8" rst="0">
          <comment>unsigned threshold value
When sum of all LLR[k] &gt; totaltest, vadflag is 1,otherwise 0
There is a OR relationship with individualtest</comment>
        </bits>
        <bits access="rw" name="overhead1" pos="7:4" rst="0">
          <comment>valdflag smooth module
Count the number of successive detected speech frames,no longer count more than 6.After that , when detect no speech frames, smooth the overhead2 frames into speech frames. If less 6, smooth the overhead1 frames into speech frames</comment>
        </bits>
        <bits access="rw" name="overhead2" pos="3:0" rst="0">
          <comment>ditto</comment>
        </bits>
      </reg>
      <reg name="vad_20" protect="r">
      </reg>
      <reg name="vad_24" protect="rw">
        <bits access="rw" name="wr_clr" pos="9" rst="0">
          <comment>SFIFO's write address is reset to all 0, high active</comment>
        </bits>
        <bits access="rw" name="rd_clr" pos="8" rst="0">
          <comment>SFIFO's read address is reset to all 0, high active</comment>
        </bits>
        <bits access="rw" name="test_ctrl_s" pos="7:4" rst="0">
          <comment>0:test_port_s &lt;= {1'b0,speech_stds_0 ,1'b0,speech_means_adj_0 }    ;</comment>
        </bits>
        <bits access="rw" name="test_ctrl_n" pos="3:0" rst="0">
          <comment>0: test_port_n &lt;= {1'b0,noise_stds_0 ,1'b0,noise_means_adj_0 }    ;</comment>
        </bits>
      </reg>
      <reg name="vad_28" protect="r">
        <bits access="r" name="test_port_s" pos="31:0" rst="0">
          <comment>{1'b0,speech_stds ,1'b0,speech_means_adj }    ;</comment>
        </bits>
      </reg>
      <reg name="vad_2c" protect="r">
        <bits access="r" name="test_port_n" pos="31:0" rst="0">
          <comment>{1'b0,noise_stds ,1'b0,noise_means_adj }</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="sci.xml">
    <module category="Periph" name="SCI">
      <reg name="sci_config" protect="rw">
        <bits access="rw" name="enable" pos="0" rst="0">
          <comment>Enables the SIM Card IF module</comment>
        </bits>
        <bits access="rw" name="parity" pos="1" rst="0">
          <comment>Selects the parity generation/detection</comment>
          <options>
            <option name="Even_parity" value="0"/>
            <option name="Odd_parity" value="1"/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="perf" pos="2" rst="0">
          <comment>
            Parity Error Receive Feed-through
            <br/>
            0 = Don't store bytes with detected parity errors
            <br/>
            1 = Feed-through bytes with detected parity errors
          </comment>
        </bits>
        <bits access="rw" name="filter_disable" pos="3" rst="0">
          <comment>
            Enable or disable NULL (0x60) character filtering when SIM card sends NULL to reset WWT timer.
            <br/>
            0 = Enable NULL character filtering, NULL characters are not reported if not data.
            <br/>
            1 = Disable NULL character filtering.  NULL characters (0x60) are transferred to the SCI data buffer.
          </comment>
        </bits>
        <bits access="rw" name="clockstop" pos="4" rst="1">
          <comment>
            Manual SCI Clock Stop control.  Manually starts and stops the SCI clock.  This bit must be set to '1' when Autostop mode is enabled.
            <br/>
            0 = Enable the SCI clock
            <br/>
            1 = Disable SCI clock
          </comment>
        </bits>
        <bits access="rw" name="autostop_en_h" pos="5" rst="0">
          <comment>
            Enables automatic clock shutdown when command is complete.  Enabling this will generate the necessary startup and shutdown delays required by the SIM protocol.
            <br/>
            0 = Auto clock control not enabled.  SCI clock controlled by SCI_Clockstop bit
            <br/>
            1 = Auto clock control enabled.
          </comment>
        </bits>
        <bits access="rw" name="msbh_lsbl" pos="6" rst="1">
          <comment>
            Sets the transmission and reception bit order:
            <br/>
            0 = LSB is sent/recieved first (Direct convention)
            <br/>
            1 = MSB is sent/received first (Inverse convention)
          </comment>
        </bits>
        <bits access="rw" name="lli" pos="7" rst="1">
          <comment>
            Logic Level Invert:
            <br/>
            0 = Logic level 0 data is sent/received as '0' or 'A' which is the same as the start bit.  (Direct convention)
            <br/>
            1 = Logic level 0 data is sent/received as '1' or 'Z' which is the opposite of the start bit.  (Inverse convention)
          </comment>
        </bits>
        <bits access="rw" name="pegen_len" pos="8" rst="0">
          <comment>
            Parity Error signal length.  This configuration bit can be used to extend the duration of the parity error signal generation from 1 ETU to 1.5 ETU
            <br/>
            0 = Parity Error signal duration is 1 ETU starting at 10.5 ETU
            <br/>
            1 = Parity Error signal duration is 1.5 ETU starting at 10.5 ETU
          </comment>
        </bits>
        <bits access="rw" name="parity_en" pos="9" rst="0">
          <comment>
            Enable or disable parity error checking on the receive data
            <br/>
            0 = Disable parity error checking
            <br/>
            1 = Enable parity error checking
          </comment>
        </bits>
        <bits access="rw" name="stop_level" pos="10" rst="1">
          <comment>
            Logical value of the clock signal when SCI clock is stopped (either due to automatic shutdown or manual shutdown)
            <br/>
            0 = Stop clock at low level
            <br/>
            1 = Stop clock at high level
          </comment>
        </bits>
        <bits access="rw" name="arg_h" pos="16" rst="0">
          <comment>Automatic Reset Generator.  Write a '1' to this bit to initiate an automatic reset procedure on the SIM.  Write '0' to switch back to SCI_Reset control (bit 20).  An ARG interrupt will be generated if the ARG process succeeded or failed.  The ARG status bit (ARG_Det) must be read to determine if a reset response from the card was detected.  This bit needs to be cleared between ARG attempts.</comment>
        </bits>
        <bits access="rw" name="afd_en_h" pos="17" rst="0">
          <comment>
            Automatic format detection.  This bit is generally set in conjunction with the ARG_H bit to enable automatic detection of the data convention.
            <br/>
            1 = Enable TS detection and automatic convention settings programming
            <br/>
            0 = disable automatic settings and use the register bits (MSBH_LSBL and LLI) to control the convention
          </comment>
        </bits>
        <bits access="rw" name="tx_resend_en_h" pos="18" rst="1">
          <comment>
            1 = Enable automatic resend of characters when Tx parity error is detected
            <br/>
            0 = Disable automatic resend
          </comment>
        </bits>
        <bits access="rw" name="reset" pos="20" rst="0">
          <comment>
            Direct connection to the SIM card reset pin.  This is overridden when ARG_H is enabled
            <br/>
            0 = SCI_Reset low voltage
            <br/>
            1 = SCI Reset high voltage
          </comment>
        </bits>
        <bits access="rw" name="dly_sel" pos="21" rst="0">
          <comment>
            This selects between two delay times for the automatic clock stop startup and shutdown:
            <br/>
            0 = short delay
            <br/>
            Startup/Shutdown : 744 SCI clocks / 1860 SCI clocks
            <br/>
            1 = long delay
            <br/>
            Startup/Shutdown : (2 x 744) SCI clocks / (2 x 1860) SCI clocks
          </comment>
        </bits>
        <bits access="rw" name="in_avg_en" pos="22" rst="1">
          <comment>
            Input data average enable.
            <br/>
            0 = Disable
            <br/>
            1 = Enable
          </comment>
        </bits>
        <bits access="rw" name="par_chk_offset" pos="29:24" rst="0xe">
          <comment>Allows fine control of the parity check position during the parity error time period.</comment>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="rxdata_rdy" pos="0" rst="0">
          <comment>
            Returns the status of the Rx FIFO:
            <br/>
            0 = Rx FIFO empty
            <br/>
            1 = There is at least 1 character in the Rx FIFO
          </comment>
        </bits>
        <bits access="r" name="tx_fifo_rdy" pos="1" rst="1">
          <comment>
            Returns the status of the Tx FIFO:
            <br/>
            0 = Tx FIFO is full
            <br/>
            1 = There is at least 1 free spot in the Tx FIFO
          </comment>
        </bits>
        <bits access="r" name="format_det" pos="2" rst="0">
          <comment>
            Returns the status of the automatic format detection after reset:
            <br/>
            0 = TS character has not been detected in the ATR
            <br/>
            1 = TS character has been detected and SCI module is using the automatic convention settings
            <br/>
            <br/>
            This bit is cleared when the AFD_En bit is cleared
          </comment>
        </bits>
        <bits access="r" name="arg_det" pos="3" rst="0">
          <comment>
            Returns the status of the automatic reset procedure:
            <br/>
            0 = ARG detection has failed
            <br/>
            1 = ARG detection has detected that the SIM has responded to the reset
            <br/>
            <br/>
            This bit is used in conjunction with the ARG interrupt.  The ARG interrupt will be generated at the successful or unsuccessful termination of the ARG process.  This bit can be used to determine the success or failure.
          </comment>
        </bits>
        <bits access="r" name="reset_det" pos="4" rst="0">
          <comment>This is the status of the Reset pin when automatic reset generation is enabled.  This bit can be used to discover whether the SIM card that has successfully responded to an ARG procedure has an active high or active low reset. (Det means 'Detection')</comment>
        </bits>
        <bits access="r" name="clk_rdy_h" pos="5" rst="0">
          <comment>
            Status of the control signal to the clock control module.  This bit respects the startup and shutdown phases, so during these times, the clock may actually be on, but it is not considered to be 'ready'
            <br/>
            0 = SCI clock may be on or off but is not ready for use
            <br/>
            1 = SCI clock is on and ready for use
          </comment>
        </bits>
        <bits access="r" name="clk_off" pos="6" rst="1">
          <comment>
            Status bit of the Sci clock.
            <br/>
            0 = Sci clock is ON
            <br/>
            1 = Sci clock is OFF
          </comment>
        </bits>
        <bits access="r" name="rx_err" pos="8" rst="0">
          <comment>A receive parity error was detected. Reading this register clears the bit.</comment>
        </bits>
        <bits access="r" name="tx_err" pos="9" rst="0">
          <comment>A transmit parity error was detected. Reading this register clears the bit.</comment>
        </bits>
        <bits access="r" name="rxoverflow" pos="10" rst="0">
          <comment>The internal receive FIFO has reached an overflow condition. Reading this register clears the bit.</comment>
        </bits>
        <bits access="r" name="txoverflow" pos="11" rst="0">
          <comment>The internal transmit FIFO has reached an overflow condition. Reading this register clears the bit.</comment>
        </bits>
        <bits access="r" name="autostop_state" pos="31:30" rst="0">
          <comment>Returns the state of the clock management state machine when AutoStop mode is enabled.  This value is '00' when manual mode is selected.</comment>
          <options>
            <option name="Startup_phase" value="0">
              <comment>Clock is on, but not ready to be used.</comment>
            </option>
            <option name="Auto_on" value="1">
              <comment>Clock is on and ready to be used</comment>
            </option>
            <option name="Shutdown_phase" value="2">
              <comment>Clock is still on, but should not be used.</comment>
            </option>
            <option name="Clock_off" value="3">
              <comment>Clock is off.</comment>
            </option>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <reg name="data" protect="--">
        <bits access="w" name="data_in" pos="7:0" rst="FF">
          <comment>Writing to this register will send the data to the SIM card. If automatic clock shutdown is enabled, the appropriate delay will be applied before the data is actually sent.</comment>
        </bits>
        <bits access="r" name="data_out" pos="7:0" rst="FF">
          <comment>Reading this register will read from the receive data FIFO.</comment>
        </bits>
      </reg>
      <reg name="clkdiv_reg" protect="rw">
        <bits access="rw" name="clkdiv" pos="8:0" rst="0x174">
          <comment>Clock divider for generating the baud clock from the SCI clock.  This value must match the value used by the SIM card whose default value is 0x174.</comment>
        </bits>
        <bits access="rw" name="baud_x8_en" pos="9" rst="0">
          <comment>
            Speed mode enable.
            <br/>
            0 = Low speed mode
            <br/>
            1 = High speed mode(372/32, 372/64, 512/64)
          </comment>
        </bits>
        <bits access="rw" name="rx_clk_cnt_limit" pos="14:10" rst="0x10">
          <comment>Rx_clk_cnt wrap value.</comment>
        </bits>
        <bits access="rw" name="clk_tst" pos="15" rst="0">
          </bits>
        <bits access="rw" name="clkdiv_16" pos="23:16" rst="0x16">
          <comment>Secondary clock divider for generating 16x baud clock.</comment>
        </bits>
        <bits access="rw" name="maindiv" pos="29:24" rst="0x4">
          <comment>
            Main clock divider to generate the SCI clock.  This value should be calculated as follows:
            <br/>
            MainDiv = Clk_Sys/(2xSCI_Clk) - 1
            <br/>
            where SCI_Clk is in the range of 3-5 MHz as specified in the SIM specification.
          </comment>
          <options>
            <mask/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="clk_out_inv" pos="30" rst="0">
          <comment>
            Inverts the polarity of the SCI clock to the SIM card only.
            <br/>
            0 = No inversion
            <br/>
            1 = Invert external SCI clock
          </comment>
        </bits>
        <bits access="rw" name="clk_inv" pos="31" rst="0">
          <comment>
            Inverts the polarity of the SCI clock to the SIM card and internal.
            <br/>
            0 = No inversion
            <br/>
            1 = Invert external SCI clock
          </comment>
        </bits>
      </reg>
      <reg name="rxcnt_reg" protect="rw">
        <bits access="rw" name="rxcnt" pos="9:0" rst="0">
          <comment>
            This value should be programmed with the number of expected characters to receive.  It will be decremented each time a character is
            <strong>actually</strong>
             received and should be 0 when the transfer is complete.  If a character is sent after the RxCnt reaches zero, the extra character flag will be set but this value will stay at zero.
          </comment>
        </bits>
        <bits access="rw" name="clk_persist" pos="31" rst="0">
          <comment>
            When in automatic clock shutdown mode, this bit can prevent the clock from entering shutdown mode when the transfer is complete.  This should be used for multi-transfer commands where the clock must not be shut down until the command is complete.  This bit must be programmed for each transfer.
            <br/>
            1 = Keep clock on
            <br/>
            0 = Allow clock shutdown when transfer is complete
          </comment>
        </bits>
      </reg>
      <reg name="times" protect="rw">
        <bits access="rw" name="chguard" pos="7:0" rst="1">
          <comment>This is the extra guard time that can be added to the 2 ETU minimum (and default) guard time between successive transmitted characters.  This should be programmed depending on the SIM's ATR.  The total ETU guard time will be ChGuard + 1.</comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="turnaroundguard" pos="11:8" rst="0x6">
          <comment>
            Turnaround guard time configuration.  This value can be used to adjust the delay between the leading edge of a received character and the leading edge of the next transmitted character.  The minimum time specified in the SIM recommendation is 16 ETU.  The number of ETUs can be calculated using the following formula:
            <br/>
            Total Turnaround Time (in ETUs) = 11 + TurnaroundGuard
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="wi" pos="23:16" rst="0x0A">
          <comment>
            Work Waiting Time factor.  A timeout will be generated when the WWT is exceeded.  The WWT is calculated by:
            <br/>
                   WWT = 960 x WI x (F/Fi)
            <br/>
            where Fi is the main SCI clock frequency (3-5 MHz) and F is 372 before an enhanced PPS and 512 after an enhanced PPS.
            <br/>
            The SCI_WI value must be calculated as follows:
            <br/>
                   SCI_WI = WI * D
            <br/>
            Thus, by default (WI = 10) this value needs to be set to 10 before an EPPS, but needs to be scaled to WI*D=80 after the EPPS procedure.
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="tx_pert" pos="31:24" rst="0xFF">
          <comment>Number of times to try resending character when the SIM indicates a parity error.</comment>
        </bits>
      </reg>
      <reg name="ch_filt_reg" protect="rw">
        <bits access="rw" name="ch_filt" pos="7:0" rst="0x60">
          <comment>
            Value of the character to be filtered.  0x60 is the NULL character in the SIM protocol.  If character filtering is enabled, the
            <strong>first</strong>
             0x60 character that is received by the SIM during a transfer will
            <strong>not</strong>
             be recorded.  The purpose of this character is to enable the SIM to reset the WWT counter when the SIM is not ready to send the data.  This filter has no effect on characters within the datastream.
          </comment>
        </bits>
      </reg>
      <reg name="dbg" protect="w">
        <bits access="w" name="fifo_rx_clr" pos="0" rst="0">
          <comment>Clear RX FIFO.</comment>
        </bits>
        <bits access="w" name="fifo_tx_clr" pos="1" rst="0">
          <comment>Clear TX FIFO.</comment>
        </bits>
        <comment>clear RX/TX FIFO</comment>
      </reg>
      <reg name="int_cause" protect="r">
        <bits access="r" name="rx_done" pos="0" rst="0">
          <comment>Number of expected Rx characters, as programmed in the RxCnt register, has been received.</comment>
        </bits>
        <bits access="r" name="rx_half" pos="1" rst="0">
          <comment>Receiver FIFO is half full.</comment>
        </bits>
        <bits access="r" name="wwt_timeout" pos="2" rst="0">
          <comment>No Tx character has been sent NOR any Rx character detected within the WWT timeout.</comment>
        </bits>
        <bits access="r" name="extra_rx" pos="3" rst="0">
          <comment>An extra character has been received after the number of characters in RxCnt has been received.</comment>
        </bits>
        <bits access="r" name="resend_ovfl" pos="4" rst="0">
          <comment>The automatic re-transmit of parity error characters has exceeded the threshold specified in the Tx_PERT field.</comment>
        </bits>
        <bits access="r" name="arg_end" pos="5" rst="0">
          <comment>End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not.</comment>
        </bits>
        <bits access="r" name="sci_dma_tx_done" pos="6" rst="0">
          <comment>DMA tx done.</comment>
        </bits>
        <bits access="r" name="sci_dma_rx_done" pos="7" rst="0">
          <comment>DMA rx done.</comment>
        </bits>
        <comment>
          This register is a
          <b>READ ONLY</b>
           register that returns the logical
          <b>and</b>
           of the SCI_INT_STATUS register and the SCI_INT_MASK. If any of these bits is '1', the SCI module will generate an interrupt.  Bits 21:16 return the
          <u>status</u>
           of the interrupt which is the interrupt state before the mask is applied.  These bits should only be used for debugging.
        </comment>
      </reg>
      <reg name="int_clr" protect="rw">
        <bits access="c" name="rx_done" pos="0" rst="0">
          <comment>Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received.</comment>
        </bits>
        <bits access="c" name="rx_half" pos="1" rst="0">
          <comment>Receiver FIFO is half full.</comment>
        </bits>
        <bits access="c" name="wwt_timeout" pos="2" rst="0">
          <comment>No Tx character has been sent NOR any Rx character detected within the WWT timeout.</comment>
        </bits>
        <bits access="c" name="extra_rx" pos="3" rst="0">
          <comment>An extra character has been received after the number of characters in SCI_RxCnt has been received.</comment>
        </bits>
        <bits access="c" name="resend_ovfl" pos="4" rst="0">
          <comment>The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field.</comment>
        </bits>
        <bits access="c" name="arg_end" pos="5" rst="0">
          <comment>End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not.</comment>
        </bits>
        <bits access="c" name="sci_dma_tx_done" pos="6">
          <comment>DMA tx done.</comment>
        </bits>
        <bits access="c" name="sci_dma_rx_done" pos="7">
          <comment>DMA rx done.</comment>
        </bits>
        <comment>This is a WRITE ONLY register that is used to clear an SCI interrupt. Write a '1' to the interrupt that is to be cleared. Writing '0' has no effect.</comment>
      </reg>
      <reg name="int_mask" protect="rw">
        <bits access="rw" name="rx_done" pos="0" rst="0">
          <comment>Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received.</comment>
        </bits>
        <bits access="rw" name="rx_half" pos="1" rst="0">
          <comment>Receiver FIFO is half full.</comment>
        </bits>
        <bits access="rw" name="wwt_timeout" pos="2" rst="0">
          <comment>No Tx character has been sent NOR any Rx character detected within the WWT timeout.</comment>
        </bits>
        <bits access="rw" name="extra_rx" pos="3" rst="0">
          <comment>An extra character has been received after the number of characters in SCI_RxCnt has been received.</comment>
        </bits>
        <bits access="rw" name="resend_ovfl" pos="4" rst="0">
          <comment>The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field.</comment>
        </bits>
        <bits access="rw" name="arg_end" pos="5" rst="0">
          <comment>End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not.</comment>
        </bits>
        <bits access="rw" name="sci_dma_tx_done" pos="6" rst="0">
          <comment>DMA tx done.</comment>
        </bits>
        <bits access="rw" name="sci_dma_rx_done" pos="7" rst="0">
          <comment>DMA rx done.</comment>
        </bits>
        <comment>This register is READ/WRITE register that enables the desired interrupt. A '1' in a bit position indicates that the corresponding interrupt is enabled and if the interrupt occurs, the SCI will generate a hardware interrupt.</comment>
      </reg>
      <reg name="pa_clk_stop_en" protect="rw">
    </reg>
      <reg name="pa_status" protect="rw">
    </reg>
    </module>
  </archive>
  <archive relative="lps.xml">
    <module category="System" name="LPS">
      <var name="LP_FRAC_NB_BITS" value="16"/>
      <var name="LP_COUNT_INT_NB_BITS" value="19"/>
      <var name="LP_COUNT_NB_BITS" value="LP_COUNT_INT_NB_BITS + LP_FRAC_NB_BITS"/>
      <var name="LP_RATE_INT_NB_BITS" value="12"/>
      <var name="LP_RATE_NB_BITS" value="LP_RATE_INT_NB_BITS + LP_FRAC_NB_BITS"/>
      <var name="SYS_COUNT_NB_BITS" value="29"/>
      <var name="FRAME_COUNT_NB_BITS" value="32"/>
      <var name="PU_COUNT_NB_BITS" value="12"/>
      <reg name="lps_sf_ctrl" protect="rw">
        <bits access="rw" name="lps_sf_enable" pos="0" rst="0">
          <comment>
            Lps Skip Frame Enable.
            <br/>
            When enabled the frame interrupt are masked until the programmed number of frames are elapsed.
            <br/>
            This is done by masking the frame interrupt line from the regular TCU counter, and counting the frames. Also when activating the LowPower SkipFrame the frame counter is tranfered to the low power counter that will update it based on the 32kHz Clock.
          </comment>
        </bits>
        <bits access="rw" name="lps_sf_lowpower" pos="5:4" rst="0">
          <comment>Controls the Lps Low Power Counters (counters at 32kHz) usage.</comment>
          <options>
            <option name="Stop" value="0">
              <comment>Disable the Low Power Counters.</comment>
            </option>
            <option name="SkipFrame" value="1">
              <comment>The Low Power Counters are started in Skip Frame Mode. In this mode the Low Power Counter are used to maintain the Time base, The Skip Frame Must be enabled as this is the Low Power extention of the Skip Frame feature.</comment>
            </option>
            <option name="Calib" value="3">
              <comment>Start the calibration. The Low Power Counters are used to Calibrate the 32kHz clock against the System Clock, The Calibration is required to compensate from temperature variation. Note that the Skip Frame can also be enabled during calibration (but not with low power).</comment>
            </option>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="lps_sf_wakeup0" pos="8" rst="0">
          <comment>Enable fake Fint used with wakeupNumber=0.</comment>
          <options>
            <option name="Disabled" value="0"/>
            <option name="Enabled" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="lps_sf_wakeup0_cfg" pos="9" rst="0">
          <comment>
            Enable fake Fint when sys_sf_frame_count&gt;=cfg_sf_frame.
            <br/>
            Default sys_sf_frame_count&gt;cfg_sf_frame.
          </comment>
          <options>
            <option name="0" value="0"/>
            <option name="1" value="1"/>
          </options>
        </bits>
      </reg>
      <reg name="lps_sf_status" protect="rw">
        <bits access="r" name="lps_sf_ready" pos="0" rst="1">
          <comment>
            Lps Skip Frame Ready, status of the state machines to keep valid state between system clock and 32Khz clock.
            <br/>
            Must read as '1' before entering Low Power Skip Frame or Calibration mode.
          </comment>
        </bits>
        <bits access="r" name="lps_sf_slowrunning" pos="4" rst="0">
          <comment>
            '1' when Lps Skip Frame Low Power Counters are Running.
            <br/>
            When entering Low Power Skip Frame, the counters are not immediately started, they wait for the nextFrame interrupt. Reading this status allow to know if the counters are running, and the System Clock can be safely disabled.
          </comment>
        </bits>
        <bits access="r" name="lps_sf_calibrationdone" pos="8" rst="0">
          <comment>'1' when the Lps Skip Frame Calibration is Done.</comment>
        </bits>
        <bits access="r" name="lps_sf_pu_reached" pos="12" rst="0">
          <comment>'1' when the Lps Skip Frame Power-up sequence frame is reached.</comment>
        </bits>
        <bits access="r" name="lps_sf_tcu_restart" pos="16" rst="0">
          <comment>'1' when tcu counter is restarted.</comment>
        </bits>
      </reg>
      <reg name="lps_sf_frames" protect="rw">
        <bits access="rw" name="lps_sf_frame" pos="FRAME_COUNT_NB_BITS-1:0" rst="0">
          <comment>
            Number of frames to Skip.
            <br/>
            If the power up sequence is enabled, frames are skipped until both this number is reached and the powerup sequence has finished.
            <br/>
            Note: The power up sequence must be
            <b>Done</b>
             before the the frame LPS_SF_Frame ends.
          </comment>
        </bits>
      </reg>
      <reg name="lps_sf_pu_frames" protect="rw">
        <bits access="rw" name="lps_sf_pu_frame" pos="FRAME_COUNT_NB_BITS-1:0" rst="0">
          <comment>Number of frames before activating the Power-up sequence.</comment>
        </bits>
      </reg>
      <reg name="lps_sf_restart_time" protect="rw">
        <bits access="rw" name="lps_sf_restart_time" pos="LP_COUNT_INT_NB_BITS-1:0" rst="0">
          <comment>
            For LowPower SkipFrame mode: Value to restart TCU (and frame interrupt generation) on the system clock counter after a low power phase.
            <br/>
            For Calibration mode: number of 32k cycles for the calibration.
          </comment>
        </bits>
      </reg>
      <reg name="lps_sf_frame_period" protect="rw">
        <bits access="rw" name="lps_sf_frame_period" pos="LP_COUNT_INT_NB_BITS-1:0" rst="0">
          <comment>Value of the frame period in system clock count.</comment>
        </bits>
      </reg>
      <reg name="lps_sf_rate" protect="rw">
        <comment>The rate is the number of System Clocks per 32kHz Clocks.</comment>
        <bits access="rw" name="lps_sf_rate_int" pos="LP_RATE_NB_BITS-1:LP_FRAC_NB_BITS" rst="0">
          <comment>Integer part of the rate.</comment>
        </bits>
        <bits access="rw" name="lps_sf_rate_frac" pos="LP_FRAC_NB_BITS-1:0" rst="0">
          <comment>Fractional part of the rate.</comment>
        </bits>
      </reg>
      <reg name="lps_sf_elapsed_frames" protect="rw">
        <bits access="r" name="lps_sf_elapsed_frames" pos="FRAME_COUNT_NB_BITS-1:0" rst="0">
          <comment>
            Current number of elapsed frames.
            <br/>
            Valid when Skip Frame is Enabled.
          </comment>
        </bits>
      </reg>
      <reg name="lps_sf_sys_count" protect="rw">
        <bits access="r" name="lps_sf_sys_count" pos="SYS_COUNT_NB_BITS-1:0" rst="0">
          <comment>
            Value of the system clock counter at the end of calibration (when CalibrationDone is '1' in LPS_SF_Status register).
            <br/>
            The hardware behind it is reused during other operation, reading that register at any other time will return an undefined value.
          </comment>
        </bits>
      </reg>
      <reg name="lps_irq" protect="rw">
        <bits access="rc" name="lps_irq_calibration_done_cause" pos="0" rst="0">
          <comment>
            1 when the IRQ was triggered because the calibration is done.
            <br/>
            Write 1 in cause or status bit to clear.
          </comment>
        </bits>
        <bits access="rc" name="lps_irq_slow_running_cause" pos="1" rst="0">
          <comment>
            1 when the IRQ was triggered because the Slow Counter started.
            <br/>
            Write 1 in cause or status bit to clear.
          </comment>
        </bits>
        <bits access="rc" name="lps_irq_pu_reached_cause" pos="2" rst="0">
          <comment>
            1 when the IRQ was triggered because the Power-Up frame was reached.
            <br/>
            Write 1 in cause or status bit to clear.
          </comment>
        </bits>
        <bits access="rc" name="lps_irq_tcu_restart_cause" pos="3" rst="0">
          <comment>
            1 when the IRQ was triggered because the tcu counter was restarted.
            <br/>
            Write 1 in cause or status bit to clear.
          </comment>
        </bits>
        <bitgroup name="lps_pu_irq_cause">
          <entry ref="lps_irq_calibration_done_cause"/>
          <entry ref="lps_irq_slow_running_cause"/>
          <entry ref="lps_irq_pu_reached_cause"/>
          <entry ref="lps_irq_tcu_restart_cause"/>
        </bitgroup>
        <bits access="rc" name="lps_irq_calibration_done_status" pos="16" rst="0">
          <comment>
            1 when the calibration is done.
            <br/>
            Write 1 in cause or status bit to clear.
          </comment>
        </bits>
        <bits access="rc" name="lps_irq_slow_running_status" pos="17" rst="0">
          <comment>
            1 when the Slow Counter started.
            <br/>
            Write 1 in cause or status bit to clear.
          </comment>
        </bits>
        <bits access="rc" name="lps_irq_pu_reached_status" pos="18" rst="0">
          <comment>
            1 when the Power-Up frame was reached.
            <br/>
            Write 1 in cause or status bit to clear.
          </comment>
        </bits>
        <bits access="rc" name="lps_irq_tcu_restart_status" pos="19" rst="0">
          <comment>
            1 when the tcu counter was restarted.
            <br/>
            Write 1 in cause or status bit to clear.
          </comment>
        </bits>
        <bitgroup name="lps_pu_irq_status">
          <entry ref="lps_irq_calibration_done_status"/>
          <entry ref="lps_irq_slow_running_status"/>
          <entry ref="lps_irq_pu_reached_status"/>
          <entry ref="lps_irq_tcu_restart_status"/>
        </bitgroup>
      </reg>
      <reg name="lps_irq_mask" protect="rw">
        <bits access="rw" name="lps_irq_calibration_done_mask" pos="0" rst="0">
          <comment>when 1 the LPS_IRQ_Calibration_Done is enabled.</comment>
        </bits>
        <bits access="rw" name="lps_irq_slow_running_mask" pos="1" rst="0">
          <comment>when 1 the LPS_IRQ_Slow_Running is enabled.</comment>
        </bits>
        <bits access="rw" name="lps_irq_pu_reached_mask" pos="2" rst="0">
          <comment>when 1 the LPS_IRQ_PU_Reached is enabled.</comment>
        </bits>
        <bits access="rw" name="lps_irq_tcu_restart_mask" pos="3" rst="0">
          <comment>when 1 the LPS_IRQ_TCU_Restart is enabled.</comment>
        </bits>
        <bitgroup name="lps_irq_mask">
          <entry ref="lps_irq_calibration_done_mask"/>
          <entry ref="lps_irq_slow_running_mask"/>
          <entry ref="lps_irq_pu_reached_mask"/>
          <entry ref="lps_irq_tcu_restart_mask"/>
        </bitgroup>
      </reg>
    </module>
  </archive>
  <archive relative="spi.xml">
    <var name="SPI_TX_FIFO_SIZE" value="16"/>
    <var name="SPI_RX_FIFO_SIZE" value="16"/>
    <module category="Periph" name="SPI">
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="enable" pos="0" rst="0">
          <comment>Enable the module and activate the chip select selected by CS_sel field.</comment>
        </bits>
        <bits access="rw" name="cs_sel" pos="2:1" rst="0">
          <comment>Selects the active CS.</comment>
          <options>
            <option name="CS0" value="0"/>
            <option name="CS1" value="1"/>
            <option name="CS2" value="2"/>
            <option name="CS3" value="3"/>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="input_mode" pos="4" rst="1">
          <comment>
            When set to 1 the inputs are activated, else only the output is driven and no data are stored in the receive FIFO.
            <br/>
            Notes: The Input_mode bit status is also readable onto the bit rxtx_buffer[31].
          </comment>
        </bits>
        <bits access="rw" name="clock_polarity" pos="5" rst="1">
          <comment>
            The spi clock polarity
            <br/>
            when '0' the clock disabled level is low, and the first edge is a rising edge.
            <br/>
            When '1' the clock disabled level is high, and the first edge is a falling edge.
          </comment>
        </bits>
        <bits access="rw" name="clock_delay" pos="7:6" rst="3">
          <comment>Transfer start to first edge delay value from 0 to 2 is the number of spi clock half period between the CS activation and the first clock edge.</comment>
        </bits>
        <bits access="rw" name="do_delay" pos="9:8" rst="3">
          <comment>Transfer start to first data out delay value from 0 to 2 is the number of spi clock half period between the CS activation and the first data out</comment>
        </bits>
        <bits access="rw" name="di_delay" pos="11:10" rst="3">
          <comment>
            Transfer start to first data in sample delay value from 0 to 3 is the number of spi clock half period between the CS activation and the first data in sampled.
            <br/>
            NOTE: DI_Delay must be less or equal to DO_Delay + CS_Delay + 2.
            <br/>
            In other words DI_Delay can be 3 only if DO_Delay and CS_Delay are not both equal to 0.
          </comment>
        </bits>
        <bits access="rw" name="cs_delay" pos="13:12" rst="3">
          <comment>Transfer end to chip select deactivation delay value from 0 to 3 is the number of spi clock half period between the end of transfer and CS deactivation</comment>
        </bits>
        <bits access="rw" name="cs_pulse" pos="15:14" rst="3">
          <comment>Chip select deactivation to reactivation minimum delay value from 0 to 3 is the number of spi clock half period between the CS deactivation and a new CS activation (CS will activate only if more data are available in the transmit FIFO)</comment>
        </bits>
        <bits access="rw" name="frame_size" pos="20:16" rst="31">
          <comment>
            Frame Size
            <br/>
            The frame size is the binary value of this register + 1 valid value are 3 to 31 (frame size 4 to 32bits)
          </comment>
        </bits>
        <bits access="rw" name="oe_delay" pos="28:24" rst="31">
          <comment>
            OE delay
            <br/>
            When 0: regular mode, SPI_DO pin as output only.
            <br/>
            Value from 1 to 31 is the number of data out to transfert before the SPI_DO pin switch to input.
          </comment>
        </bits>
        <bits access="rw" name="ctrl_data_mux_sel" pos="29" rst="0">
          <comment>
            Selects the active CS and Input_reg either from the ctrl or rxtx_buffer register.
            <br/>
            If SPI FIFO 8b or 32b, when set to &quot;0&quot;: CS from CS_sel and INPUT from Input_mode in the register ctrl.
            <br/>
            Only if SPI FIFO 32b, when set to &quot;1&quot;: CS and INPUT from SPI DATA.(Do not work for FIFO8b)
          </comment>
          <options>
            <option name="Ctrl_reg_sel" value="0"/>
            <option name="Data_reg_sel" value="1"/>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="input_sel" pos="31:30" rst="0">
          <comment>
            Selects the input line to be used as SPI data in.(Not used for SPI3)
            <br/>
            when &quot;00&quot; the SPI_DI_0 is used.
            <br/>
            When &quot;01&quot; the SPI_DI_1 is used.
            <br/>
            When &quot;10&quot; the SPI_DI_2 is used.
            <br/>
            When &quot;11&quot; reserved.
          </comment>
        </bits>
      </reg>
      <reg name="status" protect="rw">
        <bits access="r" name="active_status" pos="0" rst="0">
          <comment>'1' when a transfer is in progress.</comment>
        </bits>
        <bits access="rw" name="cause_rx_ovf_irq" pos="3" rst="0">
          <comment>
            The receive FIFO overflow irq cause.
            <br/>
            Writing a '1' clear the receive overflow status and cause.
          </comment>
        </bits>
        <bits access="r" name="cause_tx_th_irq" pos="4" rst="0">
          <comment>The transmit FIFO threshold irq cause.</comment>
        </bits>
        <bits access="rw" name="cause_tx_dma_irq" pos="5" rst="0">
          <comment>
            The transmit Dma Done irq cause.
            <br/>
            Writing a '1' clear the transmit Dma Done status and cause.
          </comment>
        </bits>
        <bits access="r" name="cause_rx_th_irq" pos="6" rst="0">
          <comment>The receive FIFO threshold irq cause.</comment>
        </bits>
        <bits access="rw" name="cause_rx_dma_irq" pos="7" rst="0">
          <comment>
            The receive Dma Done irq cause.
            <br/>
            Writing a '1' clear the receive Dma Done status and cause.
          </comment>
        </bits>
        <bitgroup name="irq_cause">
          <entry ref="cause_rx_ovf_irq"/>
          <entry ref="cause_tx_th_irq"/>
          <entry ref="cause_tx_dma_irq"/>
          <entry ref="cause_rx_th_irq"/>
          <entry ref="cause_rx_dma_irq"/>
        </bitgroup>
        <bits access="rw" name="tx_ovf" pos="9" rst="0">
          <comment>
            The transmit FIFO overflow status.
            <br/>
            Writing a '1' clear the transmit overflow status and cause.
          </comment>
        </bits>
        <bits access="rw" name="rx_udf" pos="10" rst="0">
          <comment>
            The receive FIFO underflow status.
            <br/>
            Writing a '1' clear the receive underflow status and cause.
          </comment>
        </bits>
        <bits access="rw" name="rx_ovf" pos="11" rst="0">
          <comment>
            The receive FIFO overflow status.
            <br/>
            Writing a '1' clear the receive overflow status and cause.
          </comment>
        </bits>
        <bits access="r" name="tx_th" pos="12" rst="1">
          <comment>The transmit FIFO threshold status.</comment>
        </bits>
        <bits access="rw" name="tx_dma_done" pos="13" rst="0">
          <comment>
            The transmit Dma Done status.
            <br/>
            Writing a '1' clear the transmit Dma Done status and cause.
          </comment>
        </bits>
        <bits access="r" name="rx_th" pos="14" rst="0">
          <comment>The receive FIFO threshold status.</comment>
        </bits>
        <bits access="rw" name="rx_dma_done" pos="15" rst="0">
          <comment>
            The receive Dma Done status.
            <br/>
            Writing a '1' clear the receive Dma Done status and cause.
          </comment>
        </bits>
        <bits access="r" name="tx_space" pos="20:16" rst="16">
          <comment>
            Transmit FIFO Space
            <br/>
            Number of empty spot in the FIFO
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="rx_level" pos="28:24" rst="0">
          <comment>
            Receive FIFO level
            <br/>
            Number of DATA in the FIFO
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="w" name="fifo_flush" pos="30" rst="0">
          <comment>Writing '1' flush both FIFO, don't do it when SPI is active (transfer in progress)</comment>
        </bits>
      </reg>
      <reg name="rxtx_buffer" protect="--">
        <comment>
          Spi1 fifo size (rxtx_buffer): 8bits.
          <br/>
                 Spi2 fifo size (rxtx_buffer): 8bits.
          <br/>
                 Spi3 fifo size (rxtx_buffer): 32bits.
          <br/>
        </comment>
        <bits access="rw" name="data_in_out" pos="28:0" rst="0">
          <comment>Write to the transmit FIFO
	    Read in the receive FIFO.</comment>
        </bits>
        <bits access="rw" name="cs" pos="30:29" rst="0">
          <comment>Chip Select on which write the data written in the
                Fifo.
		Data in bit [30:29]
		Data out bit [30:29]</comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="read_ena" pos="31" rst="1">
          <comment>Set this bit to one when the data received while sending
                this peculiar data are expected to be kept in the FIFO,
                otherwise no data is recorded in the FIFO.
		Data in bit [31]
		Data out bit [31]</comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="cfg" protect="rw">
        <bits access="rw" cut="1" cutprefix="CS_Polarity" name="cs_polarity" pos="2:0" rst="0x3">
          <comment>Chip select polarity</comment>
          <options>
            <option name="active high" value="0">
              <comment>chip select is active high</comment>
            </option>
            <option name="active low" value="1">
              <comment>chip select is active low</comment>
            </option>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="clock_divider" pos="25:16" rst="0x3ff">
          <comment>
            Clock Divider
            <br/>
            The state machine clock is generated by dividing the system clock by the value of this register + 1.
            <br/>
            So the output clock is divided by (register + 1)*2
          </comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="clock_limiter" pos="28" rst="1">
          <comment>
            When enabled the clock input to the divider is not the system clock, but a limited version of it: It cannot be above 52MHz, so the output clock will never be above 26MHz.
            <br/>
             for system clock of 104Mhz the clock input to the divider is 52Mhz, for system clock of 78Mhz the clock input to the divider is 39Mhz, for lower system clock value, the input to the divider is the system clock.
          </comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pattern" protect="rw">
        <bits access="rw" name="pattern" pos="7:0" rst="0">
          <comment>MMC Pattern value for RX pattern match mode.</comment>
        </bits>
        <bits access="rw" name="pattern_mode" pos="8" rst="0">
          <comment>Enable the pattern mode.</comment>
          <options>
            <option name="disabled" value="0">
              <comment>Spi Behaviour.</comment>
            </option>
            <option name="enabled" value="1">
              <comment>Pattern matching.</comment>
            </option>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="pattern_selector" pos="9" rst="0">
          <comment>Select the RX pattern matching mode when the pattern_mode is enabled( set 1). Used for SD/MMC SPI mode.</comment>
          <options>
            <option name="UNTIL" value="0">
              <comment>No datas are written into the RX FIFO UNTIL the received data is equal to the pattern.</comment>
            </option>
            <option name="WHILE" value="1">
              <comment>No datas are written into the RX FIFO WHILE the received data is equal to the pattern.</comment>
            </option>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
      </reg>
      <reg name="stream" protect="rw">
        <bits access="rw" name="tx_stream_bit" pos="0" rst="0">
          <comment>When TX stream mode is enabled, once the TX fifo is empty, all new bits send have the value of this bit.</comment>
          <options>
            <option name="zero" value="0"/>
            <option name="one" value="1"/>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="tx_stream_mode" pos="8" rst="0">
          <comment>
            Enable the TX stream mode. Used for SD/MMC SPI mode.
            <br/>
            When enabled, this mode provide infinite bit stream for sending, after fifo is empty the extra bits generated all have the same value. The value is in tx_stream_bit.
          </comment>
          <options>
            <option name="disabled" value="0"/>
            <option name="enabled" value="1"/>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="tx_stream_stop_with_rx_dma_done" pos="16" rst="0">
          <comment>Allow to automatically clear the tx_stream_mode when Rx_Dma_Done is set.</comment>
          <options>
            <option name="disabled" value="0"/>
            <option name="enabled" value="1"/>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
      </reg>
      <reg name="pin_control" protect="rw">
        <bits access="rw" name="clk_ctrl" pos="1:0" rst="0">
          <options>
            <option name="Spi Ctrl" value="0">
              <comment>The Spi_Clk pin is set OUTPUT(Basic SPI Behaviour).</comment>
            </option>
            <option name="Input Ctrl" value="1">
              <comment>The Spi_Clk pin is set INPUT (High Impedance).</comment>
            </option>
            <option name="Force 0 Ctrl" value="2">
              <comment>The Spi_Clk pin is set OUTPUT and forced to 0.</comment>
            </option>
            <option name="Force 1 Ctrl" value="3">
              <comment>The Spi_Clk pin is set OUTPUT and forced to 1.</comment>
            </option>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="do_ctrl" pos="3:2" rst="0">
          <options>
            <option name="Spi Ctrl" value="0">
              <comment>The Spi_DO pin is set OUTPUT(Basic SPI Behaviour).</comment>
            </option>
            <option name="Input Ctrl" value="1">
              <comment>The Spi_DO pin is set INPUT (High Impedance).</comment>
            </option>
            <option name="Force 0 Ctrl" value="2">
              <comment>The Spi_DO pin is set OUTPUT and forced to 0.</comment>
            </option>
            <option name="Force 1 Ctrl" value="3">
              <comment>The Spi_DO pin is set OUTPUT and forced to 1.</comment>
            </option>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="cs0_ctrl" pos="5:4" rst="0">
          <options>
            <option name="Spi Ctrl" value="0">
              <comment>The Spi_CSO pin is set OUTPUT(Basic SPI Behaviour).</comment>
            </option>
            <option name="Input Ctrl" value="1">
              <comment>The Spi_CSO pin is set INPUT (High Impedance).</comment>
            </option>
            <option name="Force 0 Ctrl" value="2">
              <comment>The Spi_CSO pin is set OUTPUT and forced to 0.</comment>
            </option>
            <option name="Force 1 Ctrl" value="3">
              <comment>The Spi_CSO pin is set OUTPUT and forced to 1.</comment>
            </option>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="cs1_ctrl" pos="7:6" rst="0">
          <options>
            <option name="Spi Ctrl" value="0">
              <comment>The Spi_CS1 pin is set OUTPUT(Basic SPI Behaviour).</comment>
            </option>
            <option name="Input Ctrl" value="1">
              <comment>The Spi_CS1 pin is set INPUT (High Impedance).</comment>
            </option>
            <option name="Force 0 Ctrl" value="2">
              <comment>The Spi_CS1 pin is set OUTPUT and forced to 0.</comment>
            </option>
            <option name="Force 1 Ctrl" value="3">
              <comment>The Spi_CS1 pin is set OUTPUT and forced to 1.</comment>
            </option>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="cs2_ctrl" pos="9:8" rst="0">
          <options>
            <option name="Spi Ctrl" value="0">
              <comment>The Spi_CS2 pin is set OUTPUT(Basic SPI Behaviour).</comment>
            </option>
            <option name="Input Ctrl" value="1">
              <comment>The Spi_CS2 pin is set INPUT (High Impedance).</comment>
            </option>
            <option name="Force 0 Ctrl" value="2">
              <comment>The Spi_CS2 pin is set OUTPUT and forced to 0.</comment>
            </option>
            <option name="Force 1 Ctrl" value="3">
              <comment>The Spi_CS2 pin is set OUTPUT and forced to 1.</comment>
            </option>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <reg name="irq" protect="rw">
        <bits access="rw" name="mask_rx_ovf_irq" pos="0" rst="0">
          <comment>Mask the receive FIFO overflow irq</comment>
        </bits>
        <bits access="rw" name="mask_tx_th_irq" pos="1" rst="0">
          <comment>Mask the transmit FIFO threshold irq</comment>
        </bits>
        <bits access="rw" name="mask_tx_dma_irq" pos="2" rst="0">
          <comment>Mask the transmit Dma Done irq</comment>
        </bits>
        <bits access="rw" name="mask_rx_th_irq" pos="3" rst="0">
          <comment>Mask the receive FIFO threshold irq</comment>
        </bits>
        <bits access="rw" name="mask_rx_dma_irq" pos="4" rst="0">
          <comment>Mask the receive DMA Done irq</comment>
        </bits>
        <bitgroup name="irq_mask">
          <entry ref="mask_rx_ovf_irq"/>
          <entry ref="mask_tx_th_irq"/>
          <entry ref="mask_tx_dma_irq"/>
          <entry ref="mask_rx_th_irq"/>
          <entry ref="mask_rx_dma_irq"/>
        </bitgroup>
        <bits access="rw" name="tx_threshold" pos="6:5" rst="3">
          <comment>Transmit FIFO threshold this threshold is used to generate the irq.</comment>
          <options>
            <option name="1 Empty Slot" value="0"/>
            <option name="4 Empty Slots" value="1"/>
            <option name="8 Empty Slots" value="2"/>
            <option name="12 Empty Slots" value="3"/>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="rx_threshold" pos="8:7" rst="3">
          <comment>Receive FIFO threshold this threshold is used to generate the irq.</comment>
          <options>
            <option name="1 Valid Data" value="0"/>
            <option name="4 Valid Data" value="1"/>
            <option name="8 Valid Data" value="2"/>
            <option name="12 Valid Data" value="3"/>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="sys_ctrl.xml">
    <include file="globals.xml"/>
    <module category="System" name="SYS_CTRL">
      <enum name="Cpu_Id">
        <entry name="A5CPU">
          <comment>CPU IDs</comment>
        </entry>
      </enum>
      <enum name="Sys_Axi_Clks">
        <entry name="SYS_AXI_CLK_ID_IMEM">
          <comment>Sys Axi Clks IDs</comment>
        </entry>
        <entry name="SYS_AXI_CLK_ID_LZMA"/>
        <bound name="NB_SYS_AXI_CLK_REV">
          <comment>reserved base number</comment>
        </bound>
        <entry name="SYS_AXI_CLK_ID_REV0"/>
        <entry name="SYS_AXI_CLK_ID_REV1"/>
        <entry name="SYS_AXI_CLK_ID_REV2"/>
        <entry name="SYS_AXI_CLK_ID_SDMMC1"/>
        <bound name="NB_SYS_AXI_CLK_AEN">
          <comment>auto clock enable number</comment>
        </bound>
        <entry name="SYS_AXI_CLK_ID_ALWAYS"/>
        <bound name="NB_SYS_AXI_CLK_EN"/>
        <bound name="NB_SYS_AXI_CLK"/>
      </enum>
      <enum name="Sys_Ahb_Clks">
        <entry name="SYS_AHB_CLK_ID_GOUDA">
          <comment>Sys Ahb Clks IDs</comment>
        </entry>
        <entry name="SYS_AHB_CLK_ID_GGE"/>
        <entry name="SYS_AHB_CLK_ID_GEA3"/>
        <bound name="NB_SYS_AHB_CLK_REV">
          <comment>reserved base number</comment>
        </bound>
        <entry name="SYS_AHB_CLK_ID_LZMA"/>
        <entry name="SYS_AHB_CLK_ID_F8"/>
        <entry name="SYS_AHB_CLK_ID_AXIDMA"/>
        <bound name="NB_SYS_AHB_CLK_AEN">
          <comment>auto clock enable number</comment>
        </bound>
        <entry name="SYS_AHB_CLK_ID_USBC"/>
        <entry name="SYS_AHB_CLK_ID_LCD"/>
        <entry name="SYS_AHB_CLK_ID_AES"/>
        <entry name="SYS_AHB_CLK_ID_USB11"/>
        <entry name="SYS_AHB_CLK_ID_ALWAYS"/>
        <bound name="NB_SYS_AHB_CLK_EN"/>
        <bound name="NB_SYS_AHB_CLK"/>
      </enum>
      <enum name="Ap_Apb_Clks">
        <entry name="AP_APB_CLK_ID_CONF">
          <comment>Sys Apb Clks IDs</comment>
        </entry>
        <entry name="AP_APB_CLK_ID_MOD_CAMERA"/>
        <entry name="AP_APB_CLK_ID_I2C1"/>
        <entry name="AP_APB_CLK_ID_I2C3"/>
        <entry name="AP_APB_CLK_ID_IFC"/>
        <entry name="AP_APB_CLK_ID_IFC_CH0"/>
        <entry name="AP_APB_CLK_ID_IFC_CH1"/>
        <entry name="AP_APB_CLK_ID_IFC_CH2"/>
        <entry name="AP_APB_CLK_ID_IFC_CH3"/>
        <entry name="AP_APB_CLK_ID_IFC_CH4"/>
        <entry name="AP_APB_CLK_ID_IFC_CH5"/>
        <entry name="AP_APB_CLK_ID_IFC_CH6"/>
        <entry name="AP_APB_CLK_ID_IFC_CHDBG"/>
        <entry name="AP_APB_CLK_ID_GOUDA"/>
        <entry name="AP_APB_CLK_ID_SDMMC2"/>
        <entry name="AP_APB_CLK_ID_SPI1"/>
        <entry name="AP_APB_CLK_ID_SPI2"/>
        <entry name="AP_APB_CLK_ID_SCID1"/>
        <entry name="AP_APB_CLK_ID_SCID2"/>
        <entry name="AP_APB_CLK_ID_SCI1"/>
        <entry name="AP_APB_CLK_ID_SCI2"/>
        <entry name="AP_APB_CLK_ID_CAMERA"/>
        <entry name="AP_APB_CLK_ID_PAGESPY"/>
        <bound name="NB_AP_APB_CLK_AEN">
          <comment>auto clock enable number</comment>
        </bound>
        <entry name="AP_APB_CLK_ID_LZMA"/>
        <entry name="AP_APB_CLK_ID_REV2"/>
        <entry name="AP_APB_CLK_ID_TIMER1"/>
        <entry name="AP_APB_CLK_ID_TIMER2"/>
        <entry name="AP_APB_CLK_ID_TIMER4"/>
        <entry name="AP_APB_CLK_ID_LCD"/>
        <entry name="AP_APB_CLK_ID_CQIRQ"/>
        <entry name="AP_APB_CLK_ID_ALWAYS"/>
        <bound name="NB_AP_APB_CLK_EN"/>
        <bound name="NB_AP_APB_CLK"/>
      </enum>
      <enum name="Aif_Apb_Clks">
        <entry name="AIF_APB_CLK_ID_CONF">
          <comment>Aif Apb Clks IDs</comment>
        </entry>
        <entry name="AIF1_APB_CLK_ID_AIF"/>
        <entry name="AIF2_APB_CLK_ID_AIF"/>
        <entry name="AIF_APB_CLK_ID_IFC"/>
        <entry name="AIF_APB_CLK_ID_IFC_CH0"/>
        <entry name="AIF_APB_CLK_ID_IFC_CH1"/>
        <entry name="AIF_APB_CLK_ID_IFC_CH2"/>
        <entry name="AIF_APB_CLK_ID_IFC_CH3"/>
        <bound name="NB_AIF_APB_CLK_REV">
          <comment>reserved base number</comment>
        </bound>
        <entry name="AIF_APB_CLK_ID_REV0"/>
        <entry name="AIF_APB_CLK_ID_REV1"/>
        <entry name="AIF_APB_CLK_ID_REV2"/>
        <entry name="AIF_APB_CLK_ID_AUD_2AD"/>
        <bound name="NB_AIF_APB_CLK_AEN">
          <comment>auto clock enable number</comment>
        </bound>
        <entry name="AIF_APB_CLK_ID_ALWAYS"/>
        <bound name="NB_AIF_APB_CLK_EN"/>
        <bound name="NB_AIF_APB_CLK"/>
      </enum>
      <enum name="Aon_Ahb_Clks">
        <entry name="AON_AHB_CLK_ID_BB_SYSCTRL">
          <comment>Aon Ahb Clks IDs</comment>
        </entry>
        <bound name="NB_AON_AHB_CLK_REV">
          <comment>reserved base number</comment>
        </bound>
        <entry name="AON_AHB_CLK_ID_BB_REV0"/>
        <entry name="AON_AHB_CLK_ID_BB_REV1"/>
        <entry name="AON_AHB_CLK_ID_BB_REV2"/>
        <entry name="AON_AHB_CLK_ID_CSSYS"/>
        <bound name="NB_AON_AHB_CLK_AEN">
          <comment>auto clock enable number</comment>
        </bound>
        <entry name="AON_AHB_CLK_ID_ALWAYS"/>
        <bound name="NB_AON_AHB_CLK_EN"/>
        <bound name="NB_AON_AHB_CLK"/>
      </enum>
      <enum name="Aon_Apb_Clks">
        <entry name="AON_APB_CLK_ID_CONF">
          <comment>Aon Apb Clks IDs</comment>
        </entry>
        <entry name="AON_APB_CLK_ID_DBG_HOST"/>
        <entry name="AON_APB_CLK_ID_DBG_UART"/>
        <entry name="AON_APB_CLK_ID_IFC"/>
        <entry name="AON_APB_CLK_ID_IFC_CH0"/>
        <entry name="AON_APB_CLK_ID_IFC_CH1"/>
        <entry name="AON_APB_CLK_ID_IFC_CH2"/>
        <entry name="AON_APB_CLK_ID_IFC_CH3"/>
        <entry name="AON_APB_CLK_ID_IFC_CHDBG"/>
        <entry name="AON_APB_CLK_ID_REV0"/>
        <entry name="AON_APB_CLK_ID_REV1"/>
        <entry name="AON_APB_CLK_ID_PWM"/>
        <entry name="AON_APB_CLK_ID_I2C2"/>
        <entry name="AON_APB_CLK_ID_ANA_REG"/>
        <entry name="AON_APB_CLK_ID_SPINLOCK"/>
        <entry name="AON_APB_CLK_ID_LPS_GSM"/>
        <entry name="AON_APB_CLK_ID_LPS_NB"/>
        <entry name="AON_APB_CLK_ID_EFUSE"/>
        <entry name="AON_APB_CLK_ID_REV2"/>
        <entry name="AON_APB_CLK_ID_VAD"/>
        <bound name="NB_AON_APB_CLK_AEN">
          <comment>auto clock enable number</comment>
        </bound>
        <entry name="AON_APB_CLK_ID_REV3"/>
        <entry name="AON_APB_CLK_ID_REV4"/>
        <entry name="AON_APB_CLK_ID_GPIO"/>
        <entry name="AON_APB_CLK_ID_TIMER3"/>
        <entry name="AON_APB_CLK_ID_KEYPAD"/>
        <entry name="AON_APB_CLK_ID_AHB2APB_ADI"/>
        <entry name="AON_APB_CLK_ID_ADI"/>
        <entry name="AON_APB_CLK_ID_LVDS"/>
        <entry name="AON_APB_CLK_ID_ALWAYS"/>
        <bound name="NB_AON_APB_CLK_EN"/>
        <bound name="NB_AON_APB_CLK"/>
      </enum>
      <enum name="Rf_Ahb_Clks">
        <entry name="RF_AHB_CLK_ID_REV0"/>
        <bound name="NB_RF_AHB_CLK_AEN">
          <comment>auto clock enable number</comment>
        </bound>
        <entry name="RF_AHB_CLK_ID_ALWAYS"/>
        <bound name="NB_RF_AHB_CLK_EN"/>
        <bound name="NB_RF_AHB_CLK"/>
      </enum>
      <enum name="Rf_Apb_Clks">
        <entry name="RF_APB_CLK_ID_REV0"/>
        <bound name="NB_RF_APB_CLK_AEN">
          <comment>auto clock enable number</comment>
        </bound>
        <entry name="RF_APB_CLK_ID_ALWAYS"/>
        <bound name="NB_RF_APB_CLK_EN"/>
        <bound name="NB_RF_APB_CLK"/>
      </enum>
      <enum name="Others_Clks">
        <entry name="OC_ID_HOST_UART">
          <comment>Other Clks IDs</comment>
        </entry>
        <entry name="OC_ID_BCK1"/>
        <entry name="OC_ID_BCK2"/>
        <entry name="OC_ID_UART1"/>
        <entry name="OC_ID_UART2"/>
        <entry name="OC_ID_UART3"/>
        <entry name="OC_ID_AP_A5"/>
        <entry name="OC_ID_CP_A5"/>
        <bound name="NB_CLK_OTHER_AEN"/>
        <entry name="OC_ID_GPIO"/>
        <entry name="OC_ID_USBPHY"/>
        <entry name="OC_ID_PIX"/>
        <entry name="OC_ID_CLK_OUT"/>
        <entry name="OC_ID_ISP"/>
        <bound name="OC_ID_SYS_SPIFLASH_BASE">
          <comment>System Spiflash Domain Clock ID Base</comment>
        </bound>
        <entry name="OC_ID_SYS_SPIFLASH"/>
        <entry name="OC_ID_SYS_SPIFLASH_ALWAYS"/>
        <entry name="OC_ID_SYS_SPIFLASH1"/>
        <entry name="OC_ID_SYS_SPIFLASH1_ALWAYS"/>
        <entry name="OC_ID_SPIFLASH"/>
        <entry name="OC_ID_SPIFLASH1"/>
        <entry name="OC_ID_SPICAM"/>
        <entry name="OC_ID_CAM"/>
        <bound name="OC_ID_PSRAM_BASE">
          <comment>Psram Ctrl Domain Clock ID Base</comment>
        </bound>
        <entry name="OC_ID_PSRAM_CONF"/>
        <entry name="OC_ID_PSRAM_DMC"/>
        <entry name="OC_ID_PSRAM_PAGESPY"/>
        <entry name="OC_ID_PSRAM_ALWAYS"/>
        <bound name="NB_CLK_OTHER_EN"/>
        <bound name="NB_CLK_OTHER"/>
      </enum>
      <enum name="Others_Clks_1">
        <entry name="OC_ID_GGE_CLK32K">
          <comment>Other Clks 1 IDs</comment>
        </entry>
        <entry name="OC_ID_GGE_26M"/>
        <entry name="OC_ID_NB_61P44M"/>
        <entry name="OC_ID_BT_FM_CLK32K"/>
        <entry name="OC_ID_BT_FM_26M"/>
        <entry name="OC_ID_PMIC_CLK32K"/>
        <entry name="OC_ID_PMIC_26M"/>
        <entry name="OC_ID_CP_CLK32K"/>
        <entry name="OC_ID_CP_26M"/>
        <entry name="OC_ID_ZSP_UART"/>
        <entry name="OC_ID_CP_BBLTE"/>
        <entry name="OC_ID_494M_LTE"/>
        <entry name="OC_ID_REV0"/>
        <entry name="OC_ID_REV1"/>
        <entry name="OC_ID_REV2"/>
        <entry name="OC_ID_REV3"/>
        <bound name="NB_CLK_OTHER_1_AEN"/>
        <entry name="OC_ID_SDM_26M"/>
        <entry name="OC_ID_LPS_GSM"/>
        <entry name="OC_ID_LPS_NB"/>
        <entry name="OC_ID_EFUSE_26M"/>
        <entry name="OC_ID_USB_ADP_32K"/>
        <entry name="OC_ID_USB_UTMI_48M"/>
        <entry name="OC_ID_AP_26M"/>
        <entry name="OC_ID_AP_32K"/>
        <entry name="OC_ID_MIPIDSI"/>
        <entry name="OC_ID_AHB_BTFM"/>
        <entry name="OC_ID_VAD"/>
        <entry name="OC_ID_USB11_48M"/>
        <entry name="OC_ID_TRNG_CLKEN"/>
        <entry name="OC_ID_CORESIGHT"/>
        <entry name="OC_ID_ADI"/>
        <bound name="NB_CLK_OTHER_1_EN"/>
        <bound name="NB_CLK_OTHER_1"/>
      </enum>
      <enum name="Psram_Clks">
        <entry name="PSRAM_CLK_ID_CONF" value="(OC_ID_PSRAM_CONF-OC_ID_PSRAM_BASE)">
          <comment>Psram Clks IDs</comment>
        </entry>
        <entry name="PSRAM_CLK_ID_DMC" value="(OC_ID_PSRAM_DMC-OC_ID_PSRAM_BASE)"/>
        <entry name="PSRAM_CLK_ID_PAGESPY" value="(OC_ID_PSRAM_PAGESPY-OC_ID_PSRAM_BASE)"/>
        <entry name="PSRAM_CLK_ID_ALWAYS" value="(OC_ID_PSRAM_ALWAYS-OC_ID_PSRAM_BASE)"/>
        <bound name="NB_CLK_PSRAM"/>
      </enum>
      <enum name="Sys_Spiflash_Clks">
        <entry name="SPIFLASH_CLK_ID_SPIFLASH" value="(OC_ID_SYS_SPIFLASH-OC_ID_SYS_SPIFLASH_BASE)">
          <comment>Sys Spiflash Clks IDs</comment>
        </entry>
        <entry name="SPIFLASH_CLK_ID_ALWAYS" value="(OC_ID_SYS_SPIFLASH_ALWAYS-OC_ID_SYS_SPIFLASH_BASE)"/>
        <entry name="SPIFLASH_CLK_ID_SPIFLASH1" value="(OC_ID_SYS_SPIFLASH1-OC_ID_SYS_SPIFLASH_BASE)">
          <comment>Sys Spiflash1 Clks IDs</comment>
        </entry>
        <entry name="SPIFLASH1_CLK_ID_ALWAYS" value="(OC_ID_SYS_SPIFLASH1_ALWAYS-OC_ID_SYS_SPIFLASH_BASE)"/>
      </enum>
      <enum name="Sys_Axi_Rst">
        <entry name="SYS_AXI_RST_ID_SYS">
          <comment>Sys Axi Rst IDs</comment>
        </entry>
        <entry name="SYS_AXI_RST_ID_IMEM"/>
        <entry name="SYS_AXI_RST_ID_LZMA"/>
        <entry name="SYS_AXI_RST_ID_REV0"/>
        <entry name="SYS_AXI_RST_ID_REV1"/>
        <entry name="SYS_AXI_RST_ID_REV2"/>
        <entry name="SYS_AXI_RST_ID_REV3"/>
        <bound name="NB_SYS_AXI_RST"/>
      </enum>
      <enum name="Sys_Ahb_Rst">
        <entry name="SYS_AHB_RST_ID_SYS">
          <comment>Sys Ahb Rst IDs</comment>
        </entry>
        <entry name="SYS_AHB_RST_ID_GOUDA"/>
        <entry name="SYS_AHB_RST_ID_GGE"/>
        <entry name="SYS_AHB_RST_ID_GEA3"/>
        <entry name="SYS_AHB_RST_ID_USBC"/>
        <entry name="SYS_AHB_RST_ID_BTFM"/>
        <entry name="SYS_AHB_RST_ID_GIC400"/>
        <entry name="SYS_AHB_RST_ID_F8"/>
        <entry name="SYS_AHB_RST_ID_AXIDMA"/>
        <entry name="SYS_AHB_RST_ID_LZMA"/>
        <entry name="SYS_AHB_RST_ID_LCD"/>
        <entry name="SYS_AHB_RST_ID_AES"/>
        <entry name="SYS_AHB_RST_ID_USB11"/>
        <bound name="NB_SYS_AHB_RST"/>
      </enum>
      <enum name="Ap_Apb_Rst">
        <entry name="AP_APB_RST_ID_SYS">
          <comment>Sys Apb Rst IDs</comment>
        </entry>
        <entry name="AP_APB_RST_ID_CAMERA"/>
        <entry name="AP_APB_RST_ID_I2C1"/>
        <entry name="AP_APB_RST_ID_I2C3"/>
        <entry name="AP_APB_RST_ID_IFC"/>
        <entry name="AP_APB_RST_ID_IMEM"/>
        <entry name="AP_APB_RST_ID_SDMMC1"/>
        <entry name="AP_APB_RST_ID_SDMMC2"/>
        <entry name="AP_APB_RST_ID_SPI1"/>
        <entry name="AP_APB_RST_ID_SPI2"/>
        <entry name="AP_APB_RST_ID_UART2"/>
        <entry name="AP_APB_RST_ID_UART3"/>
        <entry name="AP_APB_RST_ID_ZSP_UART"/>
        <entry name="AP_APB_RST_ID_REV0"/>
        <entry name="AP_APB_RST_ID_REV1"/>
        <entry name="AP_APB_RST_ID_SCI1"/>
        <entry name="AP_APB_RST_ID_SCI2"/>
        <entry name="AP_APB_RST_ID_PAGESPY"/>
        <entry name="AP_APB_RST_ID_LZMA"/>
        <entry name="AP_APB_RST_ID_PSRAM"/>
        <entry name="AP_APB_RST_ID_TIMER1"/>
        <entry name="AP_APB_RST_ID_TIMER2"/>
        <entry name="AP_APB_RST_ID_TIMER4"/>
        <entry name="AP_APB_RST_ID_GOUDA"/>
        <entry name="AP_APB_RST_ID_CQIRQ"/>
        <bound name="NB_AP_APB_RST"/>
      </enum>
      <enum name="Aif_Apb_Rst">
        <entry name="AIF1_APB_RST_ID_SYS">
          <comment>Aif Apb Rst IDs</comment>
        </entry>
        <entry name="AIF2_APB_RST_ID_SYS"/>
        <entry name="AIF1_APB_RST_ID_AIF"/>
        <entry name="AIF2_APB_RST_ID_AIF"/>
        <entry name="AIF_APB_RST_ID_IFC"/>
        <entry name="AIF_APB_RST_ID_AUD_2AD"/>
        <bound name="NB_AIF_APB_RST"/>
      </enum>
      <enum name="Aon_Ahb_Rst">
        <entry name="AON_AHB_RST_ID_SYS">
          <comment>Aon Ahb Rst IDs</comment>
        </entry>
        <entry name="AON_AHB_RST_ID_REV0"/>
        <entry name="AON_AHB_RST_ID_REV1"/>
        <entry name="AON_AHB_RST_ID_REV2"/>
        <entry name="AON_AHB_RST_ID_CSSYS"/>
        <bound name="NB_AON_AHB_RST"/>
      </enum>
      <enum name="Aon_Apb_Rst">
        <entry name="AON_APB_RST_ID_SYS">
          <comment>Aon Apb Rst IDs</comment>
        </entry>
        <entry name="AON_APB_RST_ID_CALENDAR"/>
        <entry name="AON_APB_RST_ID_GPIO"/>
        <entry name="AON_APB_RST_ID_IFC"/>
        <entry name="AON_APB_RST_ID_KEYPAD"/>
        <entry name="AON_APB_RST_ID_PWM"/>
        <entry name="AON_APB_RST_ID_REV0"/>
        <entry name="AON_APB_RST_ID_REV1"/>
        <entry name="AON_APB_RST_ID_TIMER3"/>
        <entry name="AON_APB_RST_ID_I2C2"/>
        <entry name="AON_APB_RST_ID_ANA_REG"/>
        <entry name="AON_APB_RST_ID_SPINLOCK"/>
        <entry name="AON_APB_RST_ID_LPS_GSM"/>
        <entry name="AON_APB_RST_ID_LPS_NB"/>
        <entry name="AON_APB_RST_ID_EFUSE"/>
        <entry name="AON_APB_RST_ID_AHB2APB_ADI"/>
        <entry name="AON_APB_RST_ID_ADI"/>
        <entry name="AON_APB_RST_ID_LVDS"/>
        <entry name="AON_APB_RST_ID_UART1"/>
        <entry name="AON_APB_RST_ID_VAD"/>
        <bound name="NB_AON_APB_RST"/>
      </enum>
      <enum name="Rf_Ahb_Rst">
        <entry name="RF_AHB_RST_ID_SYS">
          <comment>Rf Ahb Rst IDs</comment>
        </entry>
        <entry name="RF_AHB_RST_ID_RF_REV0"/>
        <bound name="NB_RF_AHB_RST"/>
      </enum>
      <enum name="Rf_Apb_Rst">
        <entry name="RF_APB_RST_ID_SYS">
          <comment>Rf Apb Rst IDs</comment>
        </entry>
        <entry name="RF_APB_RST_ID_REV0"/>
        <bound name="NB_RF_APB_RST"/>
      </enum>
      <enum name="Apcpu_Rst">
        <entry name="APCPU_RST_ID_SYS">
          <comment>APCPU Rst IDs</comment>
        </entry>
        <entry name="APCPU_RST_ID_CORE"/>
        <entry name="APCPU_RST_ID_DBG"/>
        <entry name="APCPU_RST_ID_GIC400"/>
        <bound name="NB_APCPU_RST"/>
        <entry name="Global_Soft_Rst"/>
      </enum>
      <enum name="Cpcpu_Rst">
        <entry name="CPCPU_RST_ID_SYS">
          <comment>CPCPU Rst IDs</comment>
        </entry>
        <entry name="CPCPU_RST_ID_CORE"/>
        <entry name="CPCPU_RST_ID_DBG"/>
        <bound name="NB_CPCPU_RST"/>
      </enum>
      <enum name="Bblte_Rst">
        <entry name="BBLTE_RST_ID_SYS">
          <comment>BBlte Rst IDs</comment>
        </entry>
        <entry name="BBLTE_RST_ID_REV0"/>
        <bound name="NB_BBLTE_RST"/>
      </enum>
      <enum name="Others_Rst">
        <entry name="RSTO_ID_BCK1">
          <comment>Other Rsts IDs</comment>
        </entry>
        <entry name="RSTO_ID_BCK2"/>
        <entry name="RSTO_ID_DBG_HOST"/>
        <entry name="RSTO_ID_GPIO"/>
        <entry name="RSTO_ID_UART1"/>
        <entry name="RSTO_ID_UART2"/>
        <entry name="RSTO_ID_UART3"/>
        <entry name="RSTO_ID_USBC"/>
        <entry name="RSTO_ID_WDTIMER0"/>
        <entry name="RSTO_ID_WDTIMER1"/>
        <entry name="RSTO_ID_WDTIMER2"/>
        <entry name="RSTO_ID_SPIFLASH"/>
        <entry name="RSTO_ID_SPIFLASH_SYS"/>
        <entry name="RSTO_ID_SPIFLASH1"/>
        <entry name="RSTO_ID_SPIFLASH1_SYS"/>
        <entry name="RSTO_ID_PSRAM_DMC"/>
        <entry name="RSTO_ID_PSRAM_SYS"/>
        <entry name="RSTO_ID_PSRAM_PAGESPY"/>
        <entry name="RSTO_ID_VAD"/>
        <entry name="RSTO_ID_PIX"/>
        <entry name="RSTO_ID_SDM_26M"/>
        <entry name="RSTO_ID_WDTIMER4"/>
        <entry name="RSTO_ID_LPS_GSM"/>
        <entry name="RSTO_ID_LPS_NB"/>
        <entry name="RSTO_ID_EFUSE"/>
        <entry name="RSTO_ID_USB_ADP_32K"/>
        <entry name="RSTO_ID_MIPIDSI"/>
        <entry name="RSTO_ID_MIPIDSI_PHY"/>
        <entry name="RSTO_ID_AUD_2AD"/>
        <entry name="RSTO_ID_USB11_48M"/>
        <entry name="RSTO_ID_ZSP_UART"/>
        <entry name="RSTO_ID_CORESIGHT"/>
        <bound name="NB_RSTO"/>
      </enum>
      <var name="SYS_CTRL_PROTECT_LOCK" value="0xa50000">
        <comment>For REG_DBG protect lock/unlock value</comment>
      </var>
      <var name="SYS_CTRL_PROTECT_UNLOCK" value="0xa50001"/>
      <reg name="reg_dbg" protect="rw">
        <comment>
          <strong>This register is used to Lock and Unlock the protected registers.</strong>
        </comment>
        <bits access="rw" name="scratch" pos="15:0" rst="0x8989">
          <comment>
            <br/>
            [7:0]  Write 0x89 to the register to release automatically for related clock gate enable in sysctrl datapath
            <br/>
            [15:8] Write 0x89 to the register to release automatically for related soft reset in sysctrl datapath
          </comment>
        </bits>
        <bits access="r" name="write unlock status" pos="30" rst="0">
          <comment>
            Is set to 1 when a write attempt has been done on a protected register
            <br/>
            Can be reset by writing 0xa50000 or 0xa50001 to the debug register (With the LSB at 1 to unlock the protected registers, with the LSB at 0 to lock them)
          </comment>
        </bits>
        <bits access="r" name="write unlock" pos="31" rst="1">
          <comment>
            When this bit is set to 1, the protected registers are accessible
            <br/>
            When this bit is set to 0, the protected registers can not be written
            <br/>
            Write 0xa50000 to the debug register to set this bit to 0
            <br/>
            Write 0xa50001 to the debug register to set this bit to 1
          </comment>
        </bits>
      </reg>
      <reg name="sys_axi_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Sys_Axi_Rst" cutprefix="Set" cutstart="0" name="set_sys_axi_rst" pos="NB_SYS_AXI_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="sys_axi_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Sys_Axi_Rst" cutprefix="Clr" cutstart="0" name="clr_sys_axi_rst" pos="NB_SYS_AXI_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="sys_ahb_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Sys_Ahb_Rst" cutprefix="Set" cutstart="0" name="set_sys_ahb_rst" pos="NB_SYS_AHB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="sys_ahb_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Sys_Ahb_Rst" cutprefix="Clr" cutstart="0" name="clr_sys_ahb_rst" pos="NB_SYS_AHB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="ap_apb_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Ap_Apb_Rst" cutprefix="Set" cutstart="0" name="set_ap_apb_rst" pos="NB_AP_APB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="ap_apb_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Ap_Apb_Rst" cutprefix="Clr" cutstart="0" name="clr_ap_apb_rst" pos="NB_AP_APB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="aif_apb_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Aif_Apb_Rst" cutprefix="Set" cutstart="0" name="set_aif_apb_rst" pos="NB_AIF_APB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="aif_apb_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Aif_Apb_Rst" cutprefix="Clr" cutstart="0" name="clr_aif_apb_rst" pos="NB_AIF_APB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="aon_ahb_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Aon_Ahb_Rst" cutprefix="Set" cutstart="0" name="set_aon_ahb_rst" pos="NB_AON_AHB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="aon_ahb_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Aon_Ahb_Rst" cutprefix="Clr" cutstart="0" name="clr_aon_ahb_rst" pos="NB_AON_AHB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="aon_apb_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Aon_Apb_Rst" cutprefix="Set" cutstart="0" name="set_aon_apb_rst" pos="NB_AON_APB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="aon_apb_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Aon_Apb_Rst" cutprefix="Clr" cutstart="0" name="clr_aon_apb_rst" pos="NB_AON_APB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="rf_ahb_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Rf_Ahb_Rst" cutprefix="Set" cutstart="0" name="set_rf_ahb_rst" pos="NB_RF_AHB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="rf_ahb_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Rf_Ahb_Rst" cutprefix="Clr" cutstart="0" name="clr_rf_ahb_rst" pos="NB_RF_AHB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="rf_apb_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Rf_Apb_Rst" cutprefix="Set" cutstart="0" name="set_rf_apb_rst" pos="NB_RF_APB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="rf_apb_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Rf_Apb_Rst" cutprefix="Clr" cutstart="0" name="clr_rf_apb_rst" pos="NB_RF_APB_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="apcpu_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Apcpu_Rst" cutprefix="Set" cutstart="0" name="set_apcpu_rst" pos="NB_APCPU_RST:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="apcpu_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Apcpu_Rst" cutprefix="Clr" cutstart="0" name="clr_apcpu_rst" pos="NB_APCPU_RST:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="cpcpu_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Cpcpu_Rst" cutprefix="Set" cutstart="0" name="set_cpcpu_rst" pos="NB_CPCPU_RST:0" rst="0">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="cpcpu_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Cpcpu_Rst" cutprefix="Clr" cutstart="0" name="clr_cpcpu_rst" pos="NB_CPCPU_RST:0" rst="0">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="bblte_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Bblte_Rst" cutprefix="Set" cutstart="0" name="set_bblte_rst" pos="NB_BBLTE_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="bblte_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Bblte_Rst" cutprefix="Clr" cutstart="0" name="clr_bblte_rst" pos="NB_BBLTE_RST-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="others_rst_set" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rs" cut="1" cutenum="Others_Rst" cutprefix="Set" cutstart="0" name="set_others_rst" pos="NB_RSTO-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="others_rst_clr" protect="rw">
        <bits access="rc" cut="1" cutenum="Others_Rst" cutprefix="Clr" cutstart="0" name="clr_others_rst" pos="NB_RSTO-1:0" rst="1">
          <comment>
            Writing a 1 to any of the reset bit will take the corresponding module out of reset state
            <br/>
            Reading this register returns the reset state of all the corresponding modules
            <br/>
            0 : in reset
            <br/>
            1 : out of reset
          </comment>
        </bits>
      </reg>
      <reg name="clk_sys_axi_mode" protect="rw">
        <bits access="rw" cut="1" cutenum="Sys_Axi_Clks" cutprefix="Mode" cutstart="0" name="mode_clk_sys_axi" pos="NB_SYS_AXI_CLK_AEN-1:0" rst="1">
          <options>
            <option name="Automatic" value="0">
              <comment>automatic clock gating enabled</comment>
            </option>
            <option name="Manual" value="1">
              <comment>manual clock gating only</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="clk_sys_axi_enable" protect="rw">
        <bits access="rs" cut="1" cutenum="Sys_Axi_Clks" cutprefix="Enable" cutstart="0" name="enable_clk_sys_axi" pos="NB_SYS_AXI_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will enable the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_sys_axi_disable" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rc" cut="1" cutenum="Sys_Axi_Clks" cutprefix="Disable" cutstart="0" name="disable_clk_sys_axi" pos="NB_SYS_AXI_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will disable  the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_sys_ahb_mode" protect="rw">
        <bits access="rw" cut="1" cutenum="Sys_Ahb_Clks" cutprefix="Mode" cutstart="0" name="mode_clk_sys_ahb" pos="NB_SYS_AHB_CLK_AEN-1:0" rst="1">
          <options>
            <option name="Automatic" value="0">
              <comment>automatic clock gating enabled</comment>
            </option>
            <option name="Manual" value="1">
              <comment>manual clock gating only</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="clk_sys_ahb_enable" protect="rw">
        <bits access="rs" cut="1" cutenum="Sys_Ahb_Clks" cutprefix="Enable" cutstart="0" name="enable_clk_sys_ahb" pos="NB_SYS_AHB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will enable the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_sys_ahb_disable" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rc" cut="1" cutenum="Sys_Ahb_Clks" cutprefix="Disable" cutstart="0" name="disable_clk_sys_ahb" pos="NB_SYS_AHB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will disable  the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_ap_apb_mode" protect="rw">
        <bits access="rw" cut="1" cutenum="Ap_Apb_Clks" cutprefix="Mode" cutstart="0" name="mode_clk_ap_apb" pos="NB_AP_APB_CLK_AEN-1:0" rst="1">
          <options>
            <option name="Automatic" value="0">
              <comment>automatic clock gating enabled</comment>
            </option>
            <option name="Manual" value="1">
              <comment>manual clock gating only</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="clk_ap_apb_enable" protect="rw">
        <bits access="rs" cut="1" cutenum="Ap_Apb_Clks" cutprefix="Enable" cutstart="0" name="enable_clk_ap_apb" pos="NB_AP_APB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will enable the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_ap_apb_disable" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rc" cut="1" cutenum="Ap_Apb_Clks" cutprefix="Disable" cutstart="0" name="disable_clk_ap_apb" pos="NB_AP_APB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will disable  the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_aif_apb_mode" protect="rw">
        <bits access="rw" cut="1" cutenum="Aif_Apb_Clks" cutprefix="Mode" cutstart="0" name="mode_clk_aif_apb" pos="NB_AIF_APB_CLK_AEN-1:0" rst="1">
          <options>
            <option name="Automatic" value="0">
              <comment>automatic clock gating enabled</comment>
            </option>
            <option name="Manual" value="1">
              <comment>manual clock gating only</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="clk_aif_apb_enable" protect="rw">
        <bits access="rs" cut="1" cutenum="Aif_Apb_Clks" cutprefix="Enable" cutstart="0" name="enable_clk_aif_apb" pos="NB_AIF_APB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will enable the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_aif_apb_disable" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rc" cut="1" cutenum="Aif_Apb_Clks" cutprefix="Disable" cutstart="0" name="disable_clk_aif_apb" pos="NB_AIF_APB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will disable  the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_aon_ahb_mode" protect="rw">
        <bits access="rw" cut="1" cutenum="Aon_Ahb_Clks" cutprefix="Mode" cutstart="0" name="mode_clk_aon_ahb" pos="NB_AON_AHB_CLK_AEN-1:0" rst="1">
          <options>
            <option name="Automatic" value="0">
              <comment>automatic clock gating enabled</comment>
            </option>
            <option name="Manual" value="1">
              <comment>manual clock gating only</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="clk_aon_ahb_enable" protect="rw">
        <bits access="rs" cut="1" cutenum="Aon_Ahb_Clks" cutprefix="Enable" cutstart="0" name="enable_clk_aon_ahb" pos="NB_AON_AHB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will enable the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_aon_ahb_disable" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rc" cut="1" cutenum="Aon_Ahb_Clks" cutprefix="Disable" cutstart="0" name="disable_clk_aon_ahb" pos="NB_AON_AHB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will disable  the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_aon_apb_mode" protect="rw">
        <bits access="rw" cut="1" cutenum="Aon_Apb_Clks" cutprefix="Mode" cutstart="0" name="mode_clk_aon_apb" pos="NB_AON_APB_CLK_AEN-1:0" rst="1">
          <options>
            <option name="Automatic" value="0">
              <comment>automatic clock gating enabled</comment>
            </option>
            <option name="Manual" value="1">
              <comment>manual clock gating only</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="clk_aon_apb_enable" protect="rw">
        <bits access="rs" cut="1" cutenum="Aon_Apb_Clks" cutprefix="Enable" cutstart="0" name="enable_clk_aon_apb" pos="NB_AON_APB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will enable the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_aon_apb_disable" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rc" cut="1" cutenum="Aon_Apb_Clks" cutprefix="Disable" cutstart="0" name="disable_clk_aon_apb" pos="NB_AON_APB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will disable  the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_rf_ahb_mode" protect="rw">
        <bits access="rw" cut="1" cutenum="Rf_Ahb_Clks" cutprefix="Mode" cutstart="0" name="mode_clk_rf_ahb" pos="NB_RF_AHB_CLK_AEN-1:0" rst="1">
          <options>
            <option name="Automatic" value="0">
              <comment>automatic clock gating enabled</comment>
            </option>
            <option name="Manual" value="1">
              <comment>manual clock gating only</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="clk_rf_ahb_enable" protect="rw">
        <bits access="rs" cut="1" cutenum="Rf_Ahb_Clks" cutprefix="Enable" cutstart="0" name="enable_clk_rf_ahb" pos="NB_RF_AHB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will enable the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_rf_ahb_disable" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rc" cut="1" cutenum="Rf_Ahb_Clks" cutprefix="Disable" cutstart="0" name="disable_clk_rf_ahb" pos="NB_RF_AHB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will disable  the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_rf_apb_mode" protect="rw">
        <bits access="rw" cut="1" cutenum="Rf_Apb_Clks" cutprefix="Mode" cutstart="0" name="mode_clk_rf_apb" pos="NB_RF_APB_CLK_AEN-1:0" rst="1">
          <options>
            <option name="Automatic" value="0">
              <comment>automatic clock gating enabled</comment>
            </option>
            <option name="Manual" value="1">
              <comment>manual clock gating only</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="clk_rf_apb_enable" protect="rw">
        <bits access="rs" cut="1" cutenum="Rf_Apb_Clks" cutprefix="Enable" cutstart="0" name="enable_clk_rf_apb" pos="NB_RF_APB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will enable the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_rf_apb_disable" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rc" cut="1" cutenum="Rf_Apb_Clks" cutprefix="Disable" cutstart="0" name="disable_clk_rf_apb" pos="NB_RF_APB_CLK_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will disable  the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_others_mode" protect="rw">
        <bits access="rw" cut="1" cutenum="Others_Clks" cutprefix="Mode" cutstart="0" name="mode_clk_others" pos="NB_CLK_OTHER_AEN-1:0" rst="1">
          <options>
            <option name="Automatic" value="0">
              <comment>automatic clock gating enabled</comment>
            </option>
            <option name="Manual" value="1">
              <comment>manual clock gating only</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="clk_others_enable" protect="rw">
        <bits access="rs" cut="1" cutenum="Others_Clks" cutprefix="Enable" cutstart="0" name="enable_clk_others" pos="NB_CLK_OTHER_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will enable the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_others_disable" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rc" cut="1" cutenum="Others_Clks" cutprefix="Disable" cutstart="0" name="disable_clk_others" pos="NB_CLK_OTHER_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will disable  the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_others_1_mode" protect="rw">
        <bits access="rw" cut="1" cutenum="Others_Clks_1" cutprefix="Mode" cutstart="0" name="mode_clk_others_1" pos="NB_CLK_OTHER_1_AEN-1:0" rst="1">
          <options>
            <option name="Automatic" value="0">
              <comment>automatic clock gating enabled</comment>
            </option>
            <option name="Manual" value="1">
              <comment>manual clock gating only</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="clk_others_1_enable" protect="rw">
        <bits access="rs" cut="1" cutenum="Others_Clks_1" cutprefix="Enable" cutstart="0" name="enable_clk_others_1" pos="NB_CLK_OTHER_1_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will enable the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="clk_others_1_disable" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rc" cut="1" cutenum="Others_Clks_1" cutprefix="Disable" cutstart="0" name="disable_clk_others_1" pos="NB_CLK_OTHER_1_EN-1:0" rst="1">
          <comment>
            Each bit controls the manual enable  for one clock
            <br/>
            Writing a 1 to bit x of this register will disable  the corresponding clocks
            <br/>
            Writing a 0 to bit x has no effect on clock x
            <br/>
            Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled)
          </comment>
        </bits>
      </reg>
      <reg name="pll_ctrl" protect="rw">
        <comment>Register protected by Write_Unlocked_H.</comment>
        <bits access="rw" name="pll_enable" pos="0" rst="0">
          <comment>Mode of the Pll. This register is set to enable by the LPS_start_ExtPll_pulse_H.</comment>
          <options>
            <option name="Power_Down" value="0"/>
            <option name="Enable" value="1"/>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="pll_lock_reset" pos="4" rst="1">
          <comment>Used to reset the PLL Lock Detector.</comment>
          <options>
            <option name="Reset" value="0"/>
            <option name="No_Reset" value="1"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="pll_bypass_lock" pos="8" rst="0">
          <options>
            <option name="Pass" value="0">
              <comment>In this mode the output of the PLL is its input clock divided by the proper dividers</comment>
            </option>
            <option name="Bypass" value="1">
              <comment>In this mode the output of the PLL is its input clock</comment>
            </option>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="pll_clk_fast_enable" pos="12" rst="1">
          <comment>Enables the Fast Clock from the ExtPll (Clock Gate Reg Resync).</comment>
          <options>
            <option name="Enable" value="1"/>
            <option name="Disable" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="sel_clock" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rw" name="slow_sel_rf" pos="0" rst="1">
          <comment>PreSelects between RF clock(26mhz) and Oscillator clock(32k) for Clock Slow</comment>
          <options>
            <option name="Oscillator" value="1"/>
            <option name="RF" value="0"/>
          </options>
        </bits>
        <bits access="rw" name="sys_sel_fast" pos="1" rst="1">
          <comment>Selects between the Slow clock and the Fast Clock (APll clock) and Selects between the Slow clock and the APcpu Clock</comment>
          <options>
            <option name="Slow" value="1"/>
            <option name="Fast" value="0"/>
          </options>
        </bits>
        <bits access="rw" name="osc_32k_26m_div32k_sel" pos="2" rst="1">
          <comment>
            When 0, select 26m div32k.
            <br/>
            When 1, select osc 32k.
          </comment>
        </bits>
        <bits access="rw" name="pll_disable_lps" pos="3" rst="1">
          <comment>Disable PLL when LPS power up.</comment>
          <options>
            <option name="Disable" value="1"/>
            <option name="Enable" value="0"/>
          </options>
        </bits>
        <bits access="r" name="rf_detected" pos="4" rst="0">
          <options>
            <option name="Ok" value="1">
              <comment>When 1, the clock from the XCver is detected.</comment>
            </option>
            <option name="No" value="0">
              <comment>When 0, the clock from the XCver is not detected.</comment>
            </option>
          </options>
        </bits>
        <bits access="rw" name="rf_detect_bypass" pos="5" rst="0">
          <comment>
            If RF_Detect_Bypass = 0, RF clock is selected when she is detected.
            <br/>
            If RF_Detect_Bypass = 1, RF clock is selected even she is not detected.
          </comment>
        </bits>
        <bits access="rw" name="rf_detect_reset" pos="6" rst="0">
          <comment>
            When 1, The RF clock detection counter is force reseted.
            <br/>
            When 0, The RF clock detection counter is enabled.
          </comment>
        </bits>
        <bits access="r" name="rf_selected_l" pos="7" rst="1">
          <comment>0 when RF clock is effectively selected for Slow Clock. RF clock selection is not done until the clock has been detected.</comment>
        </bits>
        <bits access="r" name="pll_locked" pos="8" rst="0">
          <options>
            <option name="Locked" value="1">
              <comment/>
            </option>
            <option name="Not_Locked" value="0">
              <comment/>
            </option>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="r" name="fast_selected_l" pos="9" rst="1">
          <comment>0 when Fast clock is effectively selected. Fast clock selection is not done until the PLL has locked.</comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="soft_sel_spiflash" pos="10" rst="1">
          <comment>
            When 1, clk_spiflash is clk_slow.
            <br/>
            When 0, switch from clk_slow to clk_spiflash
          </comment>
        </bits>
        <bits access="rw" name="soft_sel_mem_bridge" pos="11" rst="1">
          <comment>
            When 1, clk_mem_bridge is clk_slow.
            <br/>
            When 0, switch from clk_slow to clk_pll_mem_bridge
          </comment>
        </bits>
        <bits access="rw" name="bblte_clk_pll_sel" pos="12" rst="0">
          <comment>
            When 1, clk_bblte is inverted.
            <br/>
            When 0, clk_bblte is itself, pole select
          </comment>
        </bits>
        <bits access="rw" name="camera_clk_pll_sel" pos="13" rst="1">
          <comment>
            When 1, clk_pix is clk_slow.
            <br/>
            When 0, switch from clk_slow to clk_pll_pix_div_out
          </comment>
        </bits>
        <bits access="r" name="usb_pll_locked_h" pos="14" rst="0">
          <comment>
            When 1, usb clock pll locked.
            <br/>
            When 0, usb clock pll not locked.
          </comment>
        </bits>
        <bits access="rw" name="bb26m_sel" pos="15" rst="0">
          <comment>
            When 1, select i_osc_26m.
            <br/>
            When 0, select i_bb_26m(default).
          </comment>
        </bits>
        <bits access="rw" name="soft_sel_spiflash1" pos="16" rst="1">
          <comment>
            When 1, clk_spiflash is clk_slow.
            <br/>
            When 0, switch from clk_slow to clk_spiflash
          </comment>
        </bits>
        <bits access="r" name="apll_locked_h" pos="17" rst="0">
          <comment>
            <br/>
            When 1, apll locked
            <br/>
            When 0, apll not locked
          </comment>
        </bits>
        <bits access="r" name="mempll_locked_h" pos="18" rst="0">
          <comment>
            <br/>
            When 1, mempll locked
            <br/>
            When 0, mempll not locked
          </comment>
        </bits>
        <bits access="r" name="audiopll_locked_h" pos="19" rst="0">
          <comment>
            <br/>
            When 1, audiopll locked
            <br/>
            When 0, audiopll not locked
          </comment>
        </bits>
        <bits access="r" name="bbpll2_locked_h" pos="20" rst="0">
          <comment>
            <br/>
            When 1, bbpll2 locked
            <br/>
            When 0, bbpll2 not locked
          </comment>
        </bits>
        <bits access="r" name="bbpll1_locked_h" pos="21" rst="0">
          <comment>
            <br/>
            When 1, bbpll1 locked
            <br/>
            When 0, bbpll1 not locked
          </comment>
        </bits>
        <bits access="r" name="usbpll_locked_h" pos="22" rst="0">
          <comment>
            <br/>
            When 1, usbpll locked
            <br/>
            When 0, usbpll not locked
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="cfg_clk_out" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rw" name="clkout_divider" pos="4:0" rst="all0">
          <comment>The generated clock frequency is equal to the 156MHz divided by this value + 2. The 156MHz clock comes from a PLL.</comment>
        </bits>
        <bits access="rw" name="clkout_dbg_sel" pos="5" rst="0">
          </bits>
        <bits access="rw" name="clkout_enable" pos="6" rst="0">
          </bits>
        <bits access="rw" name="clkout_update" pos="7" rst="0">
          </bits>
      </reg>
      <hole size="32"/>
      <reg name="cfg_clk_audiobck1_div" protect="rw">
        <bits access="rw" name="audiobck1_divider" pos="10:0" rst="all1">
          <comment>The generated clock frequency is equal to the pll_host_div4 divided by this value + 2. The clock comes from a PLL.</comment>
        </bits>
        <bits access="rw" name="audiobck1_update" pos="11" rst="0">
        </bits>
      </reg>
      <reg name="cfg_clk_audiobck2_div" protect="rw">
        <bits access="rw" name="audiobck2_divider" pos="10:0" rst="all1">
          <comment>The generated clock frequency is equal to the pll_host_div4 divided by this value + 2. The clock comes from a PLL.</comment>
        </bits>
        <bits access="rw" name="audiobck2_update" pos="11" rst="0">
        </bits>
      </reg>
      <reg count="4" name="cfg_clk_uart" protect="rw">
        <bits access="rw" name="uart_divider" pos="23:0" rst="0x001801">
          <comment>
            The generated clock frequency is equal to the selected source frequency divided by this value.
            <br/>
            The generated clock must be 4 or 16 times the expected baud rate depending on the Uart settings (see Uart section for details).
            <br/>
            [9:0]     numerator   'b0000000001
            <br/>
            [23:10]   denominator 'b000000000000110
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="uart_divider_update" pos="24" rst="0">
        </bits>
        <bits access="rw" name="uart_sel_pll" pos="25" rst="0">
        </bits>
      </reg>
      <reg name="cfg_clk_pwm" protect="rw">
        <bits access="rw" name="pwm_divider" pos="7:0" rst="all1">
          <comment>The Pwm reference clock frequency is the system clock divided by this register value + 1.</comment>
        </bits>
      </reg>
      <reg name="cfg_clk_dbg_div" protect="rw">
        <bits access="rw" name="clk_dbg_divider" pos="10:0" rst="all1">
          <comment>The generated clock frequency is equal to the 156MHz divided by this value + 2. The 156MHz clock comes from a PLL.</comment>
        </bits>
      </reg>
      <reg name="cfg_clk_camera_out" protect="rw">
        <bits access="rw" name="clk_camera_out_en" pos="0" rst="0">
          <comment>Clk camera out enable.</comment>
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="clk_camera_div_src_sel" pos="1" rst="0">
          <comment>Selects from which clock the Clk camera is generated.</comment>
          <options>
            <option name="26 MHz" value="0"/>
            <option name="156 MHz" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="clk_camera_out_div" pos="12:2" rst="all1">
        </bits>
        <bits access="rw" name="clk_camera_div_update" pos="13" rst="0">
        </bits>
        <bits access="rw" name="clk_spi_cam_en" pos="14" rst="0">
          <comment>Clk spi camera out enable.</comment>
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="clk_spi_cam_pol" pos="15" rst="0">
        </bits>
        <bits access="rw" name="clk_spi_cam_sel" pos="16" rst="0">
        </bits>
        <bits access="rw" name="clk_spi_cam_div" pos="27:17" rst="all1">
        </bits>
        <bits access="rw" name="clk_spi_cam_div_update" pos="28" rst="0">
        </bits>
      </reg>
      <reg name="reset_cause" protect="rw">
        <bits access="rw" name="watchdog_reset_1" pos="0" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>A watchdog reset has happened</comment>
            </option>
            <option name="No" value="0">
              <comment>No watchdog reset happened since the last HW reset or power on.</comment>
            </option>
          </options>
          <comment>Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0.</comment>
        </bits>
        <bits access="rw" name="watchdog_reset_2" pos="1" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>A watchdog reset has happened</comment>
            </option>
            <option name="No" value="0">
              <comment>No watchdog reset happened since the last HW reset or power on.</comment>
            </option>
          </options>
          <comment>Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0.</comment>
        </bits>
        <bits access="rw" name="watchdog_reset_3" pos="2" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>A watchdog reset has happened</comment>
            </option>
            <option name="No" value="0">
              <comment>No watchdog reset happened since the last HW reset or power on.</comment>
            </option>
          </options>
          <comment>Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0.</comment>
        </bits>
        <bits access="rw" name="watchdog_reset_4" pos="3" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>A watchdog reset has happened</comment>
            </option>
            <option name="No" value="0">
              <comment>No watchdog reset happened since the last HW reset or power on.</comment>
            </option>
          </options>
          <comment>Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0.</comment>
        </bits>
        <bits access="rw" name="watchdog_reset_rf" pos="4" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>A watchdog reset has happened</comment>
            </option>
            <option name="No" value="0">
              <comment>No watchdog reset happened since the last HW reset or power on.</comment>
            </option>
          </options>
          <comment>Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0.</comment>
        </bits>
        <bits access="rw" name="watchdog_reset_gge" pos="5" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>A watchdog reset has happened</comment>
            </option>
            <option name="No" value="0">
              <comment>No watchdog reset happened since the last HW reset or power on.</comment>
            </option>
          </options>
          <comment>Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0.</comment>
        </bits>
        <bits access="rw" name="watchdog_reset_zsp" pos="6" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>A watchdog reset has happened</comment>
            </option>
            <option name="No" value="0">
              <comment>No watchdog reset happened since the last HW reset or power on.</comment>
            </option>
          </options>
          <comment>Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0.</comment>
        </bits>
        <bits access="r" name="globalsoft_reset" pos="7" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>A reset was initiated from Global soft reset register</comment>
            </option>
            <option name="No" value="0">
              <comment>The reset was not from the soft reset register.</comment>
            </option>
          </options>
        </bits>
        <bits access="r" name="hostdebug_reset" pos="8" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>A reset was initiated from the Host interface</comment>
            </option>
            <option name="No" value="0">
              <comment>The reset was not from the debug interface.</comment>
            </option>
          </options>
        </bits>
        <bits access="rw" name="watchdog_reset_cp" pos="9" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>A watchdog cp reset has happened</comment>
            </option>
            <option name="No" value="0">
              <comment>No watchdog reset happened since the last HW reset or power on.</comment>
            </option>
          </options>
          <comment>Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0.</comment>
        </bits>
        <bits access="r" name="alarmcause" pos="12" rst="no">
          <options>
            <option name="Happened" value="1">
              <comment>An Alarm occur from the calendar</comment>
            </option>
            <option name="No" value="0">
              <comment>No Alarm occur.</comment>
            </option>
          </options>
        </bits>
        <bits access="rw" name="boot_mode" pos="21:16" rst="0x20">
          <comment>
            This contains the state of boot mode pins latched during Reset.
            <br/>
             bit 16: Force download.
            <br/>
             bit 17: Mass production.
            <br/>
             bit 18: Secure boot 1-&gt; secure boot, 0-&gt; nonsecure boot.
            <br/>
             bit 19: Unused.
            <br/>
             bit 20: Unused.
            <br/>
             bit 21: Unused.
            <br/>
             see BootSequence for details.
            <br/>
             This register is not reseted by a software or host reset.
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="sw_boot_mode" pos="27:22" rst="no">
          <comment>
            Software boot mode (Reseted at zero by external reset pin)
            <br/>
             This register is not reseted by a software or host reset.
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="fonctional_test_mode" pos="31" rst="no">
          <comment>When 1 the chip has booted in fonctional test mode (for chip production tests).</comment>
        </bits>
      </reg>
      <reg name="wakeup" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rw" name="force_wakeup" pos="0" rst="0">
          <comment>When 1, the wake up is set. When 0, the wake up is clear .</comment>
        </bits>
      </reg>
      <reg name="ignore_charger" protect="rw">
        <comment>This register is protected.</comment>
        <bits access="rw" name="ignore_charger" pos="0" rst="0">
          <comment>When 1, the CHG_MASK line to PMU is set. When 0, it is cleared.</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="cfg_pll_spiflash_div" protect="rw">
        <bits access="rw" name="cfg_pll_spiflash_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_spiflash_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_spiflash1_div" protect="rw">
        <bits access="rw" name="cfg_pll_spiflash1_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_spiflash1_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_mem_bridge_div" protect="rw">
        <bits access="rw" name="cfg_mem_bridge_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_mem_bridge_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_dbg_clk_source_sel" protect="rw">
        <bits access="rw" name="cfg_dbg_clk_source_sel" pos="5:0" rst="0x0">
        </bits>
      </reg>
      <reg name="cfg_clk_494m_lte_div" protect="rw">
        <bits access="rw" name="cfg_clk_494m_lte_apll_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_clk_494m_lte_apll_div_update" pos="4" rst="0">
        </bits>
        <bits access="rw" name="cfg_clksw_494m_lte_usbphy_sel" pos="5" rst="0">
        </bits>
        <bits access="rw" name="cfg_clksw_494m_clk_sel" pos="6" rst="0">
        </bits>
        <bits access="rw" name="cfg_clk_96m_26m_sel" pos="7" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_clk_96m_div" pos="30:8" rst="0x001401">
          <comment>
            The generated clock frequency is equal to the selected source frequency divided by this value .
            <br/>
            The generated clock must be 4 or 16 times the expected baud rate depending on the Uart settings (see Uart section for details).
            <br/>
            [17:8]     numerator   'b0000000001
            <br/>
            [30:18]   denominator 'b0000000000101
          </comment>
        </bits>
        <bits access="rw" name="cfg_clk_96m_div_update" pos="31" rst="0x0">
        </bits>
      </reg>
      <reg name="cfg_pll_isp_div" protect="rw">
        <bits access="rw" name="cfg_pll_isp_div" pos="11:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_isp_div_update" pos="12" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_pix_div" protect="rw">
        <bits access="rw" name="cfg_pll_pix_div" pos="6:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_pix_div_update" pos="7" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_sys_axi_div" protect="rw">
        <bits access="rw" name="cfg_pll_sys_axi_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_sys_axi_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_sys_ahb_apb_div" protect="rw">
        <bits access="rw" name="cfg_pll_ap_apb_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_ap_apb_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_sys_ahb_btfm_div" protect="rw">
        <bits access="rw" name="cfg_pll_ahb_btfm_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_ahb_btfm_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_csi_div" protect="rw">
        <bits access="rw" name="cfg_pll_csi_div" pos="6:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_csi_div_update" pos="7" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_sys_spiflash_div" protect="rw">
        <bits access="rw" name="cfg_pll_sys_spiflash_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_sys_spiflash_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_cp_div" protect="rw">
        <bits access="rw" name="cfg_pll_cp_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_cp_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_ap_cpu_div" protect="rw">
        <bits access="rw" name="cfg_pll_ap_cpu_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_ap_cpu_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_ap_cpu_aclken_div" protect="rw">
        <bits access="rw" name="cfg_ap_cpu_aclken_div" pos="2:0" rst="0x7">
        </bits>
        <bits access="rw" name="cfg_ap_cpu_aclken_div_update" pos="3" rst="0">
        </bits>
      </reg>
      <reg name="cfg_ap_cpu_dbgen_div" protect="rw">
        <bits access="rw" name="cfg_ap_cpu_dbgen_div" pos="2:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_ap_cpu_dbgen_div_update" pos="3" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_cp_cpu_div" protect="rw">
        <bits access="rw" name="cfg_pll_cp_cpu_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_pll_cp_cpu_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_cp_cpu_aclken_div" protect="rw">
        <bits access="rw" name="cfg_cp_cpu_aclken_div" pos="2:0" rst="0x7">
        </bits>
        <bits access="rw" name="cfg_cp_cpu_aclken_div_update" pos="3" rst="0">
        </bits>
      </reg>
      <reg name="cfg_cp_cpu_dbgen_div" protect="rw">
        <bits access="rw" name="cfg_cp_cpu_dbgen_div" pos="2:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_cp_cpu_dbgen_div_update" pos="3" rst="0">
        </bits>
      </reg>
      <reg name="cfg_trng_clken_div" protect="rw">
        <bits access="rw" name="cfg_trng_clken_div" pos="4:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_trng_clken_div_update" pos="5" rst="0">
        </bits>
      </reg>
      <reg name="cfg_coresight_div" protect="rw">
        <bits access="rw" name="cfg_coresight_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_coresight_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_usb11_48m_div" protect="rw">
        <bits access="rw" name="cfg_usb11_48m_div" pos="4:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_usb11_48m_div_update" pos="5" rst="0">
        </bits>
      </reg>
      <reg name="cfg_pll_usb" protect="rw">
        <bits access="rw" name="cfg_pll_usb_reset" pos="0" rst="0">
        </bits>
        <bits access="rw" name="cfg_pll_usb_rev" pos="1" rst="0">
        </bits>
      </reg>
      <reg name="cfg_vad_div" protect="rw">
        <bits access="rw" name="cfg_vad_div" pos="3:0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_vad_div_update" pos="4" rst="0">
        </bits>
      </reg>
      <reg name="cfg_hmprot" protect="rw">
        <comment>This register is ahb master protect cfg.</comment>
        <bits access="rw" name="hprot_bbdma" pos="3:0" rst="0x3">
        </bits>
        <bits access="rw" name="hprot_aif_ifc" pos="7:4" rst="0x3">
        </bits>
        <bits access="rw" name="hprot_gouda" pos="11:8" rst="0x3">
        </bits>
        <bits access="rw" name="hprot_ap_ifc" pos="15:12" rst="0x3">
        </bits>
        <bits access="rw" name="hprot_usb" pos="19:16" rst="0x3">
        </bits>
        <bits access="rw" name="hprot_sys_aon_ifc" pos="23:20" rst="0x3">
        </bits>
        <bits access="rw" name="hsprot_psram_ctrl" pos="27:24" rst="0x3">
        </bits>
      </reg>
      <reg name="cfg_mem_cq" protect="rw">
        <comment>This register is cq memory cfg.</comment>
        <bits access="rw" name="mem_ema_cq" pos="31:0" rst="0x08421084">
        </bits>
      </reg>
      <reg name="cfg_arm_sys_cfg_mem" protect="rw">
        <comment>This register is a5_top_wrap/axidma/cp_a5_top/f8/gea3_wrap/lzma/sys_imem mem cfg.</comment>
        <bits access="rw" name="arm_sys_cfg_mem" pos="31:0" rst="0x00020202">
        </bits>
      </reg>
      <reg name="cfg_audio_cfg_mem" protect="rw">
        <comment>This register is audio mem cfg.</comment>
        <bits access="rw" name="audio_cfg_mem" pos="31:0" rst="0x00020202">
        </bits>
      </reg>
      <reg name="cfg_lcd_cfg_mem" protect="rw">
        <comment>This register is lcd/gouda mem cfg.</comment>
        <bits access="rw" name="lcd_cfg_mem" pos="31:0" rst="0x00020202">
        </bits>
      </reg>
      <reg name="cfg_cam_cfg_mem" protect="rw">
        <comment>This register is camera mem cfg.</comment>
        <bits access="rw" name="cam_cfg_mem" pos="31:0" rst="0x00020202">
        </bits>
      </reg>
      <reg name="cfg_peri_cfg_mem" protect="rw">
        <comment>This register is peri(sdmmc/uart/usbc etc.) mem cfg.</comment>
        <bits access="rw" name="peri_cfg_mem" pos="31:0" rst="0x00020202">
        </bits>
      </reg>
      <reg name="cfg_aon_sys_cfg_mem" protect="rw">
        <comment>This register is aon sys mem cfg.</comment>
        <bits access="rw" name="aon_sys_cfg_mem" pos="31:0" rst="0x00020202">
        </bits>
      </reg>
      <reg name="cfg_rf_sys_cfg_mem" protect="rw">
        <comment>This register is rf sys mem cfg.</comment>
        <bits access="rw" name="rf_sys_cfg_mem" pos="31:0" rst="0x00020202">
        </bits>
      </reg>
      <reg name="cfg_coresight_cfg_mem" protect="rw">
        <comment>This register is coresight mem cfg.</comment>
        <bits access="rw" name="coresight_cfg_mem" pos="31:0" rst="0x00020202">
        </bits>
      </reg>
      <reg name="cfg_vad_cfg_mem" protect="rw">
        <comment>This register is vad mem cfg.</comment>
        <bits access="rw" name="vad_cfg_mem" pos="31:0" rst="0x00020202">
        </bits>
      </reg>
      <reg name="cfg_aif_cfg" protect="rw">
        <comment>This register is for audio i2s mux ,aif load_position etc. config.</comment>
        <bits access="rw" name="aif1_load_pos" pos="5:0" rst="0x0">
        </bits>
        <bits access="rw" name="aif2_load_pos" pos="11:6" rst="0x0">
        </bits>
        <bits access="rw" name="aif1_sel" pos="14:12" rst="0x7">
          <comment>
            <br/>
            000 = aif1 out mux to aif1
            <br/>
            001 = aif2 out mux to aif1
            <br/>
            010 = i2s1 out mux to aif1
            <br/>
            011 = i2s2 out mux to aif1
            <br/>
            100 = i2s3 out mux to aif1
            <br/>
            101 = zero out mux to aif1
          </comment>
        </bits>
        <bits access="rw" name="aif2_sel" pos="17:15" rst="0x7">
          <comment>
            <br/>
            000 = aif1 out mux to aif2
            <br/>
            001 = aif2 out mux to aif2
            <br/>
            010 = i2s1 out mux to aif2
            <br/>
            011 = i2s2 out mux to aif2
            <br/>
            100 = i2s3 out mux to aif2
            <br/>
            101 = zero out mux to aif2
          </comment>
        </bits>
        <bits access="rw" name="i2s1_sel" pos="20:18" rst="0x7">
          <comment>
            <br/>
            000 = aif1 out mux to i2s1
            <br/>
            001 = aif2 out mux to i2s1
            <br/>
            010 = i2s1 out mux to i2s1
            <br/>
            011 = i2s2 out mux to i2s1
            <br/>
            100 = i2s3 out mux to i2s1
            <br/>
            101 = zero out mux to i2s1
          </comment>
        </bits>
        <bits access="rw" name="i2s2_sel" pos="23:21" rst="0x7">
          <comment>
            <br/>
            000 = aif1 out mux to i2s2
            <br/>
            001 = aif2 out mux to i2s2
            <br/>
            010 = i2s1 out mux to i2s2
            <br/>
            011 = i2s2 out mux to i2s2
            <br/>
            100 = i2s3 out mux to i2s2
            <br/>
            101 = zero out mux to i2s2
          </comment>
        </bits>
        <bits access="rw" name="i2s3_sel" pos="26:24" rst="0x7">
          <comment>
            <br/>
            000 = aif1 out mux to i2s3
            <br/>
            001 = aif2 out mux to i2s3
            <br/>
            010 = i2s1 out mux to i2s3
            <br/>
            011 = i2s2 out mux to i2s3
            <br/>
            100 = i2s3 out mux to i2s3
            <br/>
            101 = zero out mux to i2s3
          </comment>
        </bits>
        <bits access="rw" name="i2s1_bck_lrck_oen" pos="27" rst="0x0">
          <comment>
            <br/>
            0 = i2s1 bck,lrck output enable
            <br/>
            1 = i2s1 bck,lrck output disable
          </comment>
        </bits>
        <bits access="rw" name="i2s2_bck_lrck_oen" pos="28" rst="0x0">
          <comment>
            <br/>
            0 = i2s2 bck,lrck output enable
            <br/>
            1 = i2s2 bck,lrck output disable
          </comment>
        </bits>
        <bits access="rw" name="i2s3_bck_lrck_oen" pos="29" rst="0x0">
          <comment>
            <br/>
            0 = i2s3 bck,lrck output enable
            <br/>
            1 = i2s3 bck,lrck output disable
          </comment>
        </bits>
      </reg>
      <reg name="cfg_misc_cfg" protect="rw">
        <comment>This register is limit_en_spi,,clk_freq cfg.</comment>
        <bits access="rw" name="limit_en_spi1" pos="0" rst="0x0">
        </bits>
        <bits access="rw" name="limit_en_spi2" pos="1" rst="0x0">
        </bits>
        <bits access="rw" name="limit_en_spi3" pos="2" rst="0x0">
        </bits>
        <bits access="rw" name="cfgsdisable_gic400" pos="3" rst="0x0">
        </bits>
        <bits access="rw" name="aif1_i2s_bck_sel" pos="6:4" rst="0x0">
        </bits>
        <bits access="rw" name="aif2_i2s_bck_sel" pos="10:8" rst="0x1">
        </bits>
        <bits access="rw" name="wcn_uart_out_sel" pos="11" rst="0x0">
          <comment>
            <br/>
            0 = wcn uart and ap uart(with wcn communication) connect
            <br/>
            1 = wcn uart output by iomux
          </comment>
        </bits>
        <bits access="rw" name="ap_uart_out_sel" pos="12" rst="0x0">
          <comment>
            <br/>
            0 = ap uart(with wcn communication) and wcn uart connect
            <br/>
            1 = ap uart(with wcn communication) output by iomux
          </comment>
        </bits>
        <bits access="rw" name="cfg_mode_lp" pos="13" rst="0x1">
        </bits>
        <bits access="rw" name="cfg_force_lp" pos="14" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_number_lp" pos="30:15" rst="0x8">
        </bits>
        <bits access="r" name="bcpu_stall_ack" pos="31" rst="0x0">
        </bits>
      </reg>
      <reg name="cfg_misc1_cfg" protect="rw">
        <comment>This register is misc cfg.</comment>
        <bits access="rw" name="debug_mon_sel" pos="4:0" rst="0x0">
        </bits>
        <bits access="rw" name="iomux_clk_force_on" pos="5" rst="0x0">
        </bits>
        <bits access="rw" name="ap_rst_ctrl" pos="6" rst="0x1">
          <comment>
            <br/>
            0 = disable pwr_ctrl for ap reset
            <br/>
            1 = enable pwr_ctrl for ap reset
          </comment>
        </bits>
        <bits access="rw" name="gge_rst_ctrl" pos="7" rst="0x1">
          <comment>
            <br/>
            0 = disable pwr_ctrl for gge reset
            <br/>
            1 = enable pwr_ctrl for gge reset
          </comment>
        </bits>
        <bits access="rw" name="btfm_rst_ctrl" pos="8" rst="0x1">
          <comment>
            <br/>
            0 = disable pwr_ctrl for btfm reset
            <br/>
            1 = enable pwr_ctrl for btfm reset
          </comment>
        </bits>
        <bits access="rw" name="ap_clk_ctrl" pos="9" rst="0x1">
          <comment>
            <br/>
            0 = disable pwr_ctrl for ap clock
            <br/>
            1 = enable pwr_ctrl for ap clock
          </comment>
        </bits>
        <bits access="rw" name="gge_clk_ctrl" pos="10" rst="0x1">
          <comment>
            <br/>
            0 = disable pwr_ctrl for gge clock
            <br/>
            1 = enable pwr_ctrl for gge clock
          </comment>
        </bits>
        <bits access="rw" name="btfm_clk_ctrl" pos="11" rst="0x1">
          <comment>
            <br/>
            0 = disable pwr_ctrl for btfm clock
            <br/>
            1 = enable pwr_ctrl for btfm clock
          </comment>
        </bits>
        <bits access="rw" name="bbpll1_enable" pos="12" rst="0x0">
          <comment>
            <br/>
            0 = disable bbpll1 output
            <br/>
            1 = enable bbpll1 output
          </comment>
        </bits>
        <bits access="rw" name="bbpll2_enable" pos="13" rst="0x0">
          <comment>
            <br/>
            0 = disable bbpll2 output
            <br/>
            1 = enable bbpll2 output
          </comment>
        </bits>
        <bits access="rw" name="mempll_enable" pos="14" rst="0x0">
          <comment>
            <br/>
            0 = disable mempll output
            <br/>
            1 = enable mempll output
          </comment>
        </bits>
        <bits access="rw" name="usbpll_enable" pos="15" rst="0x0">
          <comment>
            <br/>
            0 = disable usbpll output
            <br/>
            1 = enable usbpll output
          </comment>
        </bits>
        <bits access="rw" name="audiopll_enable" pos="16" rst="0x0">
          <comment>
            <br/>
            0 = disable audiopll output
            <br/>
            1 = enable audiopll output
          </comment>
        </bits>
        <bits access="rw" name="apll_zsp_clk_sel" pos="17" rst="0x0">
          <comment>
            <br/>
            0 = select clk_494m clock
            <br/>
            1 = select from apll clock
          </comment>
        </bits>
        <bits access="rw" name="apll_bbpll2_clk_sel" pos="18" rst="0x0">
          <comment>
            <br/>
            0 = select i_apll_in clock
            <br/>
            1 = select clk_494m clock
          </comment>
        </bits>
        <bits access="rw" name="reg_gic400_aruser_sel" pos="19" rst="0x0">
          <comment>gic400 axi aruser sel</comment>
        </bits>
        <bits access="rw" name="reg_gic400_aruser_dbg" pos="20" rst="0x0">
          <comment>gic400 axi aruser dbg</comment>
        </bits>
        <bits access="rw" name="reg_gic400_awuser_sel" pos="21" rst="0x0">
          <comment>gic400 axi awuser sel</comment>
        </bits>
        <bits access="rw" name="reg_gic400_awuser_dbg" pos="22" rst="0x0">
          <comment>gic400 axi awuser dbg</comment>
        </bits>
        <bits access="rw" name="lvds_wcn_rfdig_sel" pos="23" rst="0x0">
          <comment>
            <br/>
            0 = select rfdig lvds
            <br/>
            1 = select wcn lvds
          </comment>
        </bits>
        <bits access="rw" name="lvds_rfdig_rf_bb_sel" pos="24" rst="0x0">
          <comment>
            <br/>
            0 = select rfdig from rf lvds
            <br/>
            1 = select rfdig from bb lvds
          </comment>
        </bits>
        <bits access="rw" name="wcn_osc_en_ctrl" pos="25" rst="0x1">
          <comment>
            <br/>
            0 = disable wcn_hclk and wcn_clk_26m wcn_osc_en control
            <br/>
            1 = enable wcn_hclk and wcn_clk_26m wcn_osc_en control
          </comment>
        </bits>
        <bits access="rw" name="vad_clk_force_on" pos="26" rst="0x0">
          <comment>
            <br/>
            0 = force clock on disable
            <br/>
            1 = force clock on enable
          </comment>
        </bits>
        <bits access="rw" name="vad_clk_pn_sel" pos="27" rst="0x0">
          <comment>
            <br/>
            0 = select vad clock(default)
            <br/>
            1 = select vad inv clock
          </comment>
        </bits>
        <bits access="rw" name="aud_sclk_o_pn_sel" pos="28" rst="0x0">
          <comment>
            <br/>
            0 = select aud_sclk(default)
            <br/>
            1 = select aud_sclk inv clock
          </comment>
        </bits>
        <bits access="rw" name="aon_lp_rst_ctrl" pos="29" rst="0x1">
          <comment>
            <br/>
            0 = disable pwr_ctrl for aon_lp reset
            <br/>
            1 = enable pwr_ctrl for aon_lp reset
          </comment>
        </bits>
        <bits access="rw" name="aon_lp_clk_ctrl" pos="30" rst="0x1">
          <comment>
            <br/>
            0 = disable pwr_ctrl for aon_lp clock
            <br/>
            1 = enable pwr_ctrl for aon_lp clock
          </comment>
        </bits>
        <bits access="rw" name="dump_path" pos="31" rst="0x0">
          <comment>
            <br/>
            0 = disable aon rf async bridge dump data to fifo
            <br/>
            1 = enable  aon rf async bridge dump data to fifo for bus access efficiency
          </comment>
        </bits>
      </reg>
      <reg name="cfg_force_lp_mode_lp" protect="rw">
        <comment>This register set lp related config.</comment>
        <bits access="rw" name="cfg_force_lp_a5" pos="0" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_force_lp_ahb" pos="1" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_force_lp_connect" pos="2" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_force_lp_cp_a5" pos="3" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_force_lp_psram" pos="4" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_force_lp_spiflash" pos="5" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_force_lp_spiflash1" pos="6" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_mode_lp_a5" pos="7" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_mode_lp_ahb" pos="8" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_mode_lp_connect" pos="9" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_mode_lp_cp_a5" pos="10" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_mode_lp_psram" pos="11" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_mode_lp_spiflash" pos="12" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_mode_lp_spiflash1" pos="13" rst="0x0">
        </bits>
        <bits access="rw" name="cfg_mode_lp_ahb_merge" pos="14" rst="0x0">
        </bits>
        <bits access="rw" name="force_lp_ahb_merge" pos="15" rst="0x0">
        </bits>
      </reg>
      <hole size="128"/>
      <reg name="cfg_reserve" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="wd_rst_mode" pos="0" rst="0x1">
        </bits>
        <bits access="rw" name="sys_bb_side" pos="1" rst="0x1">
        </bits>
        <bits access="rw" name="cam_out0_sel" pos="2" rst="0x0">
        </bits>
        <bits access="rw" name="vpu_clk_en" pos="3" rst="0x1">
        </bits>
        <bits access="rw" name="wd_1_rst_en" pos="4" rst="0x1">
        </bits>
        <bits access="rw" name="wd_2_rst_en" pos="5" rst="0x1">
        </bits>
        <bits access="rw" name="wd_3_rst_en" pos="6" rst="0x1">
        </bits>
        <bits access="rw" name="wd_4_rst_en" pos="7" rst="0x1">
        </bits>
        <bits access="rw" name="wd_rf_rst_en" pos="8" rst="0x1">
        </bits>
        <bits access="rw" name="wd_gge_rst_en" pos="9" rst="0x1">
        </bits>
        <bits access="rw" name="wd_zsp_rst_en" pos="10" rst="0x1">
        </bits>
        <bits access="rw" name="wd_cp_rst_en" pos="11" rst="0x1">
        </bits>
        <bits access="rw" name="dmc_phy_rst_en" pos="12" rst="0x1">
        </bits>
        <bits access="rw" name="hmprot_wcn_peri" pos="16:13" rst="0x3">
          <comment>For WCN Ahb Bus peri prot.</comment>
        </bits>
        <bits access="rw" name="hmprot_wcn_mem" pos="20:17" rst="0x3">
          <comment>For WCN Ahb Bus mem prot.</comment>
        </bits>
        <bits access="rw" name="hmprot_aes" pos="24:21" rst="0x3">
          <comment>aes ahb bus prot.</comment>
        </bits>
        <bits access="rw" name="reserve" pos="31:25" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve1" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve1" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve2" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve2" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve3" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve3" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve4" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve4" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve5" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve5" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve6" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve6" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve7" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve7" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve8" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve8" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve9" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve9" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve10" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve10" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve11" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve11" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve12" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve12" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve13" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve13" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve14" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve14" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve15" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve15" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve16" protect="rw">
        <comment>This register is reserved.</comment>
        <bits access="rw" name="reserve16" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve1_in" protect="r">
        <comment>This register is reserved.</comment>
        <bits access="r" name="reserve1_in" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve2_in" protect="r">
        <comment>This register is reserved.</comment>
        <bits access="r" name="reserve2_in" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve3_in" protect="r">
        <comment>This register is reserved.</comment>
        <bits access="r" name="reserve3_in" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve4_in" protect="r">
        <comment>This register is reserved.</comment>
        <bits access="r" name="reserve4_in" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve5_in" protect="r">
        <comment>This register is reserved.</comment>
        <bits access="r" name="reserve5_in" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve6_in" protect="r">
        <comment>This register is reserved.</comment>
        <bits access="r" name="reserve6_in" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_reserve7_in" protect="r">
        <comment>This register is reserved.</comment>
        <bits access="r" name="reserve7_in" pos="31:0" rst="0x0">
          <comment>This register is reserved.</comment>
        </bits>
      </reg>
      <reg name="cfg_chip_prod_id" protect="r">
        <comment>This register is for CHIP_ID(METAL_ID[11:0],BOND_ID[15:12]),PROD[31:16]</comment>
        <bits access="r" name="metal_id" pos="11:0" rst="-">
          <comment>
            <br/>
            [11:0] metal ID
          </comment>
        </bits>
        <bits access="r" name="bond_id" pos="15:12" rst="-">
          <comment>
            <br/>
            [15:12] bond ID, bit15: spi_flash_sel 0-&gt;1.8v pad sequence 1-&gt;3.3v pad sequence; bit14: boot
          </comment>
        </bits>
        <bits access="r" name="prod_id" pos="31:16" rst="-">
          <comment>
            <br/>
            [31:16] production ID
          </comment>
        </bits>
      </reg>
      <reg name="cfg_qos_wcn_a5_gge" protect="rw">
        <comment>This register is for BUS QOS config.</comment>
        <bits access="rw" name="wcn_mem_arqos" pos="4:0" rst="0x0">
          <comment>
            <br/>
            [3:0] for wcn_mem_arqos
            <br/>
            [4]   for wcn_mem_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="wcn_mem_awqos" pos="9:5" rst="0x0">
          <comment>
            <br/>
            [8:5] for wcn_mem_awqos
            <br/>
            [9]   for wcn_mem_awqos sync
          </comment>
        </bits>
        <bits access="rw" name="gge_arqos" pos="14:10" rst="0x0">
          <comment>
            <br/>
            [13:10] for gge_arqos
            <br/>
            [14]    for gge_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="gge_awqos" pos="19:15" rst="0x0">
          <comment>
            <br/>
            [18:15] for gge_awqos
            <br/>
            [19]    for gge_awqos sync
          </comment>
        </bits>
        <bits access="rw" name="a5_arqos" pos="24:20" rst="0x0">
          <comment>
            <br/>
            [23:20] for a5_arqos
            <br/>
            [24]    for a5_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="a5_awqos" pos="29:25" rst="0x0">
          <comment>
            <br/>
            [28:25] for a5_awqos
            <br/>
            [29]    for a5_awqos sync
          </comment>
        </bits>
      </reg>
      <reg name="cfg_qos_axidma_cpa5_f8" protect="rw">
        <comment>This register is for BUS QOS config.</comment>
        <bits access="rw" name="axidma_arqos" pos="4:0" rst="0x0">
          <comment>
            <br/>
            [3:0] for axidma_arqos
            <br/>
            [4]   for axidma_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="axidma_awqos" pos="9:5" rst="0x0">
          <comment>
            <br/>
            [8:5] for axidma_awqos
            <br/>
            [9]   for axidma_awqos sync
          </comment>
        </bits>
        <bits access="rw" name="cp_a5_arqos" pos="14:10" rst="0x0">
          <comment>
            <br/>
            [13:10] for cp_a5_arqos
            <br/>
            [14]    for cp_a5_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="cp_a5_awqos" pos="19:15" rst="0x0">
          <comment>
            <br/>
            [18:15] for cp_a5_awqos
            <br/>
            [19]    for cp_a5_awqos sync
          </comment>
        </bits>
        <bits access="rw" name="f8_arqos" pos="24:20" rst="0x0">
          <comment>
            <br/>
            [23:20] for f8_arqos
            <br/>
            [24]    for f8_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="f8_awqos" pos="29:25" rst="0x0">
          <comment>
            <br/>
            [28:25] for f8_awqos
            <br/>
            [29]    for f8_awqos sync
          </comment>
        </bits>
      </reg>
      <reg name="cfg_qos_lcdc_lzma_gouda" protect="rw">
        <comment>This register is for BUS QOS config.</comment>
        <bits access="rw" name="lcdc_arqos" pos="4:0" rst="0x0">
          <comment>
            <br/>
            [3:0] for lcdc_arqos
            <br/>
            [4]   for lcdc_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="lcdc_awqos" pos="9:5" rst="0x0">
          <comment>
            <br/>
            [8:5] for lcdc_awqos
            <br/>
            [9]   for lcdc_awqos sync
          </comment>
        </bits>
        <bits access="rw" name="lzma_arqos" pos="14:10" rst="0x0">
          <comment>
            <br/>
            [13:10] for lzma_arqos
            <br/>
            [14]    for lzma_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="lzma_awqos" pos="19:15" rst="0x0">
          <comment>
            <br/>
            [18:15] for lzma_awqos
            <br/>
            [19]    for lzma_awqos sync
          </comment>
        </bits>
        <bits access="rw" name="gouda_arqos" pos="24:20" rst="0x0">
          <comment>
            <br/>
            [23:20] for gouda_arqos
            <br/>
            [24]    for gouda_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="gouda_awqos" pos="29:25" rst="0x0">
          <comment>
            <br/>
            [28:25] for gouda_awqos
            <br/>
            [29]    for gouda_awqos sync
          </comment>
        </bits>
      </reg>
      <reg name="cfg_qos_lte_usb" protect="rw">
        <comment>This register is for BUS QOS config.</comment>
        <bits access="rw" name="lte_arqos" pos="4:0" rst="0x0">
          <comment>
            <br/>
            [3:0] for lte_arqos
            <br/>
            [4]   for lte_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="lte_awqos" pos="9:5" rst="0x0">
          <comment>
            <br/>
            [8:5] for lte_awqos
            <br/>
            [9]   for lte_awqos sync
          </comment>
        </bits>
        <bits access="rw" name="usb_arqos" pos="14:10" rst="0x0">
          <comment>
            <br/>
            [13:10] for usb_arqos
            <br/>
            [14]    for usb_arqos sync
          </comment>
        </bits>
        <bits access="rw" name="usb_awqos" pos="19:15" rst="0x0">
          <comment>
            <br/>
            [18:15] for usb_awqos
            <br/>
            [19]    for usb_awqos sync
          </comment>
        </bits>
      </reg>
      <reg name="cfg_qos_merge_mem" protect="rw">
        <comment>This register is for merge mem awqos/arqos QOS config.</comment>
        <bits access="rw" name="merge_mem_awqos" pos="4:0" rst="0x0">
          <comment>
            <br/>
            [3:0] for merge_mem_awqos
            <br/>
            [4]   for merge_mem_awqos sync
          </comment>
        </bits>
        <bits access="rw" name="merge_mem_arqos" pos="9:5" rst="0x0">
          <comment>
            <br/>
            [8:5] for merge_mem_arqos
            <br/>
            [9]   for merge_mem_arqos sync
          </comment>
        </bits>
      </reg>
      <reg name="cfg_bcpu_dbg_bkp" protect="rw">
        <comment>This register is for bcpu break point debug.</comment>
        <bits access="rw" name="bcpu_bkpt_addr" pos="27:0" rst="0x0">
          <comment>
            <br/>
            [27:0] for bcpu break point address.
          </comment>
        </bits>
        <bits access="rw" name="bcpu_bkpt_mode" pos="29:28" rst="0x3">
          <comment>
            <br/>
            [29:28] for bcpu break point mode.
          </comment>
        </bits>
        <bits access="rw" name="bcpu_bkpt_en" pos="30" rst="0x0">
          <comment>
            <br/>
            [30] for bcpu break point enable.
          </comment>
        </bits>
        <bits access="rw" name="bcpu_stalled_w1c" pos="31" rst="0x0">
          <comment>
            <br/>
            [31] for bcpu stalled write 1 clear.
          </comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="iomux.xml">
    <module category="System" name="IOMUX">
      <reg name="pad_spi_flash_clk_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_flash_clk_oen_frc" pos="28" rst="0">
          <comment>spi_flash_clk force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_clk_out_frc" pos="24" rst="0">
          <comment>spi_flash_clk force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_clk_out_reg" pos="20" rst="0">
          <comment>spi_flash_clk pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_clk_oen_reg" pos="17" rst="0">
          <comment>spi_flash_clk force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_clk_pull_frc" pos="16" rst="0">
          <comment>spi_flash_clk force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_clk_pull_up" pos="9" rst="0">
          <comment>spi_flash_clk PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_clk_pull_dn" pos="8" rst="0">
          <comment>spi_flash_clk PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_clk_sel" pos="3:0" rst="0">
          <comment>spi_flash_clk select</comment>
          <options>
            <option name="fun_spi_flash_clk_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_flash_cs_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_flash_cs_oen_frc" pos="28" rst="0">
          <comment>spi_flash_cs force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_cs_out_frc" pos="24" rst="0">
          <comment>spi_flash_cs force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_cs_out_reg" pos="20" rst="0">
          <comment>spi_flash_cs pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_cs_oen_reg" pos="17" rst="0">
          <comment>spi_flash_cs force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_cs_pull_frc" pos="16" rst="0">
          <comment>spi_flash_cs force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_cs_pull_up" pos="9" rst="0">
          <comment>spi_flash_cs PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_cs_pull_dn" pos="8" rst="0">
          <comment>spi_flash_cs PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_cs_sel" pos="3:0" rst="0">
          <comment>spi_flash_cs select</comment>
          <options>
            <option name="fun_spi_flash_cs_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_flash_sel_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_flash_sel_oen_frc" pos="28" rst="0">
          <comment>spi_flash_sel force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sel_out_frc" pos="24" rst="0">
          <comment>spi_flash_sel force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sel_out_reg" pos="20" rst="0">
          <comment>spi_flash_sel pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sel_oen_reg" pos="17" rst="0">
          <comment>spi_flash_sel force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sel_pull_frc" pos="16" rst="0">
          <comment>spi_flash_sel force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sel_pull_up" pos="9" rst="0">
          <comment>spi_flash_sel PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sel_pull_dn" pos="8" rst="0">
          <comment>spi_flash_sel PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sel_sel" pos="3:0" rst="0">
          <comment>spi_flash_sel select</comment>
          <options>
            <option name="fun_spi_flash_sel_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_flash_sio_0_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_flash_sio_0_oen_frc" pos="28" rst="0">
          <comment>spi_flash_sio_0 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_out_frc" pos="24" rst="0">
          <comment>spi_flash_sio_0 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_out_reg" pos="20" rst="0">
          <comment>spi_flash_sio_0 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_oen_reg" pos="17" rst="0">
          <comment>spi_flash_sio_0 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_pull_frc" pos="16" rst="0">
          <comment>spi_flash_sio_0 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_pull_up" pos="9" rst="0">
          <comment>spi_flash_sio_0 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_pull_dn" pos="8" rst="0">
          <comment>spi_flash_sio_0 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_sel" pos="3:0" rst="0">
          <comment>spi_flash_sio_0 select</comment>
          <options>
            <option name="fun_spi_flash_sio_0_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_flash_sio_1_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_flash_sio_1_oen_frc" pos="28" rst="0">
          <comment>spi_flash_sio_1 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_out_frc" pos="24" rst="0">
          <comment>spi_flash_sio_1 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_out_reg" pos="20" rst="0">
          <comment>spi_flash_sio_1 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_oen_reg" pos="17" rst="0">
          <comment>spi_flash_sio_1 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_pull_frc" pos="16" rst="0">
          <comment>spi_flash_sio_1 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_pull_up" pos="9" rst="0">
          <comment>spi_flash_sio_1 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_pull_dn" pos="8" rst="0">
          <comment>spi_flash_sio_1 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_sel" pos="3:0" rst="0">
          <comment>spi_flash_sio_1 select</comment>
          <options>
            <option name="fun_spi_flash_sio_1_sel" value="0"/>
            <option name="fun_gpio_29_sel" value="1"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_flash_sio_2_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_flash_sio_2_oen_frc" pos="28" rst="0">
          <comment>spi_flash_sio_2 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_out_frc" pos="24" rst="0">
          <comment>spi_flash_sio_2 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_out_reg" pos="20" rst="0">
          <comment>spi_flash_sio_2 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_oen_reg" pos="17" rst="0">
          <comment>spi_flash_sio_2 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_pull_frc" pos="16" rst="0">
          <comment>spi_flash_sio_2 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_pull_up" pos="9" rst="0">
          <comment>spi_flash_sio_2 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_pull_dn" pos="8" rst="0">
          <comment>spi_flash_sio_2 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_sel" pos="3:0" rst="0">
          <comment>spi_flash_sio_2 select</comment>
          <options>
            <option name="fun_spi_flash_sio_2_sel" value="0"/>
            <option name="fun_gpio_30_sel" value="1"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_flash_sio_3_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_flash_sio_3_oen_frc" pos="28" rst="0">
          <comment>spi_flash_sio_3 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_out_frc" pos="24" rst="0">
          <comment>spi_flash_sio_3 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_out_reg" pos="20" rst="0">
          <comment>spi_flash_sio_3 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_oen_reg" pos="17" rst="0">
          <comment>spi_flash_sio_3 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_pull_frc" pos="16" rst="0">
          <comment>spi_flash_sio_3 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_pull_up" pos="9" rst="0">
          <comment>spi_flash_sio_3 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_pull_dn" pos="8" rst="0">
          <comment>spi_flash_sio_3 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_sel" pos="3:0" rst="0">
          <comment>spi_flash_sio_3 select</comment>
          <options>
            <option name="fun_spi_flash_sio_3_sel" value="0"/>
            <option name="fun_gpio_31_sel" value="1"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sdmmc1_clk_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sdmmc1_clk_oen_frc" pos="28" rst="0">
          <comment>sdmmc1_clk force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_clk_out_frc" pos="24" rst="0">
          <comment>sdmmc1_clk force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_clk_out_reg" pos="20" rst="0">
          <comment>sdmmc1_clk pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_clk_oen_reg" pos="17" rst="0">
          <comment>sdmmc1_clk force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_clk_pull_frc" pos="16" rst="0">
          <comment>sdmmc1_clk force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_clk_pull_up" pos="9" rst="0">
          <comment>sdmmc1_clk PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_clk_pull_dn" pos="8" rst="0">
          <comment>sdmmc1_clk PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_clk_sel" pos="3:0" rst="0">
          <comment>sdmmc1_clk select</comment>
          <options>
            <option name="fun_sdmmc1_clk_sel" value="0"/>
            <option name="fun_camera_ref_clk_sel" value="2"/>
            <option name="fun_spi_2_cs_0_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sdmmc1_cmd_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sdmmc1_cmd_oen_frc" pos="28" rst="0">
          <comment>sdmmc1_cmd force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_out_frc" pos="24" rst="0">
          <comment>sdmmc1_cmd force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_out_reg" pos="20" rst="0">
          <comment>sdmmc1_cmd pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_oen_reg" pos="17" rst="0">
          <comment>sdmmc1_cmd force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_pull_frc" pos="16" rst="0">
          <comment>sdmmc1_cmd force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_pull_up" pos="9" rst="0">
          <comment>sdmmc1_cmd PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_pull_dn" pos="8" rst="0">
          <comment>sdmmc1_cmd PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_sel" pos="3:0" rst="0">
          <comment>sdmmc1_cmd select</comment>
          <options>
            <option name="fun_sdmmc1_cmd_sel" value="0"/>
            <option name="fun_gpio_24_sel" value="1"/>
            <option name="fun_camera_rst_l_sel" value="2"/>
            <option name="fun_i2c_m3_scl_sel" value="3"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sdmmc1_data_0_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sdmmc1_data_0_oen_frc" pos="28" rst="0">
          <comment>sdmmc1_data_0 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_0_out_frc" pos="24" rst="0">
          <comment>sdmmc1_data_0 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_0_out_reg" pos="20" rst="0">
          <comment>sdmmc1_data_0 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_0_oen_reg" pos="17" rst="0">
          <comment>sdmmc1_data_0 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_0_pull_frc" pos="16" rst="0">
          <comment>sdmmc1_data_0 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_0_pull_up" pos="9" rst="0">
          <comment>sdmmc1_data_0 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_0_pull_dn" pos="8" rst="0">
          <comment>sdmmc1_data_0 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_0_sel" pos="3:0" rst="0">
          <comment>sdmmc1_data_0 select</comment>
          <options>
            <option name="fun_sdmmc1_data_0_sel" value="0"/>
            <option name="fun_gpio_25_sel" value="1"/>
            <option name="fun_camera_pwdn_sel" value="2"/>
            <option name="fun_i2c_m3_sda_sel" value="3"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sdmmc1_data_1_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sdmmc1_data_1_oen_frc" pos="28" rst="0">
          <comment>sdmmc1_data_1 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_out_frc" pos="24" rst="0">
          <comment>sdmmc1_data_1 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_out_reg" pos="20" rst="0">
          <comment>sdmmc1_data_1 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_oen_reg" pos="17" rst="0">
          <comment>sdmmc1_data_1 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_pull_frc" pos="16" rst="0">
          <comment>sdmmc1_data_1 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_pull_up" pos="9" rst="0">
          <comment>sdmmc1_data_1 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_pull_dn" pos="8" rst="0">
          <comment>sdmmc1_data_1 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_sel" pos="3:0" rst="0">
          <comment>sdmmc1_data_1 select</comment>
          <options>
            <option name="fun_sdmmc1_data_1_sel" value="0"/>
            <option name="fun_gpio_26_sel" value="1"/>
            <option name="fun_uart_2_txd_sel" value="5"/>
            <option name="fun_uart_3_rts_sel" value="6"/>
            <option name="fun_spi_2_clk_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sdmmc1_data_2_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sdmmc1_data_2_oen_frc" pos="28" rst="0">
          <comment>sdmmc1_data_2 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_out_frc" pos="24" rst="0">
          <comment>sdmmc1_data_2 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_out_reg" pos="20" rst="0">
          <comment>sdmmc1_data_2 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_oen_reg" pos="17" rst="0">
          <comment>sdmmc1_data_2 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_pull_frc" pos="16" rst="0">
          <comment>sdmmc1_data_2 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_pull_up" pos="9" rst="0">
          <comment>sdmmc1_data_2 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_pull_dn" pos="8" rst="0">
          <comment>sdmmc1_data_2 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_sel" pos="3:0" rst="0">
          <comment>sdmmc1_data_2 select</comment>
          <options>
            <option name="fun_sdmmc1_data_2_sel" value="0"/>
            <option name="fun_gpio_27_sel" value="1"/>
            <option name="fun_spi_camera_ssn_sel" value="4"/>
            <option name="fun_spi_2_dio_0_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sdmmc1_data_3_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sdmmc1_data_3_oen_frc" pos="28" rst="0">
          <comment>sdmmc1_data_3 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_out_frc" pos="24" rst="0">
          <comment>sdmmc1_data_3 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_out_reg" pos="20" rst="0">
          <comment>sdmmc1_data_3 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_oen_reg" pos="17" rst="0">
          <comment>sdmmc1_data_3 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_pull_frc" pos="16" rst="0">
          <comment>sdmmc1_data_3 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_pull_up" pos="9" rst="0">
          <comment>sdmmc1_data_3 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_pull_dn" pos="8" rst="0">
          <comment>sdmmc1_data_3 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_sel" pos="3:0" rst="0">
          <comment>sdmmc1_data_3 select</comment>
          <options>
            <option name="fun_sdmmc1_data_3_sel" value="0"/>
            <option name="fun_gpio_28_sel" value="1"/>
            <option name="fun_spi_camera_sck_sel" value="2"/>
            <option name="fun_uart_2_rts_sel" value="5"/>
            <option name="fun_uart_3_txd_sel" value="6"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_aud_da_sync_cfg_reg" protect="rw">
        <bits access="rw" name="pad_aud_da_sync_oen_frc" pos="28" rst="0">
          <comment>aud_da_sync force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_sync_out_frc" pos="24" rst="0">
          <comment>aud_da_sync force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_sync_out_reg" pos="20" rst="0">
          <comment>aud_da_sync pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_sync_oen_reg" pos="17" rst="0">
          <comment>aud_da_sync force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_sync_pull_frc" pos="16" rst="0">
          <comment>aud_da_sync force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_sync_pull_up" pos="9" rst="0">
          <comment>aud_da_sync PUll up</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_sync_pull_dn" pos="8" rst="0">
          <comment>aud_da_sync PUll down</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_sync_sel" pos="3:0" rst="0">
          <comment>aud_da_sync select</comment>
          <options>
            <option name="fun_aud_da_sync_sel" value="0"/>
            <option name="fun_i2s1_bck_sel" value="1"/>
            <option name="fun_gpio_27_sel" value="2"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_aud_da_d1_cfg_reg" protect="rw">
        <bits access="rw" name="pad_aud_da_d1_oen_frc" pos="28" rst="0">
          <comment>aud_da_d1 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d1_out_frc" pos="24" rst="0">
          <comment>aud_da_d1 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d1_out_reg" pos="20" rst="0">
          <comment>aud_da_d1 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d1_oen_reg" pos="17" rst="0">
          <comment>aud_da_d1 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d1_pull_frc" pos="16" rst="0">
          <comment>aud_da_d1 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d1_pull_up" pos="9" rst="0">
          <comment>aud_da_d1 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d1_pull_dn" pos="8" rst="0">
          <comment>aud_da_d1 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d1_sel" pos="3:0" rst="0">
          <comment>aud_da_d1 select</comment>
          <options>
            <option name="fun_aud_da_d1_sel" value="0"/>
            <option name="fun_i2s1_lrck_sel" value="1"/>
            <option name="fun_gpio_28_sel" value="2"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_aud_da_d0_cfg_reg" protect="rw">
        <bits access="rw" name="pad_aud_da_d0_oen_frc" pos="28" rst="0">
          <comment>aud_da_d0 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d0_out_frc" pos="24" rst="0">
          <comment>aud_da_d0 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d0_out_reg" pos="20" rst="0">
          <comment>aud_da_d0 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d0_oen_reg" pos="17" rst="0">
          <comment>aud_da_d0 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d0_pull_frc" pos="16" rst="0">
          <comment>aud_da_d0 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d0_pull_up" pos="9" rst="0">
          <comment>aud_da_d0 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d0_pull_dn" pos="8" rst="0">
          <comment>aud_da_d0 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_aud_da_d0_sel" pos="3:0" rst="0">
          <comment>aud_da_d0 select</comment>
          <options>
            <option name="fun_aud_da_d0_sel" value="0"/>
            <option name="fun_gpio_29_sel" value="2"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_aud_ad_sync_cfg_reg" protect="rw">
        <bits access="rw" name="pad_aud_ad_sync_oen_frc" pos="28" rst="0">
          <comment>aud_ad_sync force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_sync_out_frc" pos="24" rst="0">
          <comment>aud_ad_sync force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_sync_out_reg" pos="20" rst="0">
          <comment>aud_ad_sync pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_sync_oen_reg" pos="17" rst="0">
          <comment>aud_ad_sync force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_sync_pull_frc" pos="16" rst="0">
          <comment>aud_ad_sync force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_sync_pull_up" pos="9" rst="0">
          <comment>aud_ad_sync PUll up</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_sync_pull_dn" pos="8" rst="0">
          <comment>aud_ad_sync PUll down</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_sync_sel" pos="3:0" rst="0">
          <comment>aud_ad_sync select</comment>
          <options>
            <option name="fun_aud_ad_sync_sel" value="0"/>
            <option name="fun_i2s1_sdat_o_sel" value="1"/>
            <option name="fun_gpio_30_sel" value="2"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_aud_ad_d0_cfg_reg" protect="rw">
        <bits access="rw" name="pad_aud_ad_d0_oen_frc" pos="28" rst="0">
          <comment>aud_ad_d0 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_d0_out_frc" pos="24" rst="0">
          <comment>aud_ad_d0 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_d0_out_reg" pos="20" rst="0">
          <comment>aud_ad_d0 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_d0_oen_reg" pos="17" rst="0">
          <comment>aud_ad_d0 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_d0_pull_frc" pos="16" rst="0">
          <comment>aud_ad_d0 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_d0_pull_up" pos="9" rst="0">
          <comment>aud_ad_d0 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_d0_pull_dn" pos="8" rst="0">
          <comment>aud_ad_d0 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_aud_ad_d0_sel" pos="3:0" rst="0">
          <comment>aud_ad_d0 select</comment>
          <options>
            <option name="fun_aud_ad_d0_sel" value="0"/>
            <option name="fun_gpio_31_sel" value="2"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_aud_sclk_cfg_reg" protect="rw">
        <bits access="rw" name="pad_aud_sclk_oen_frc" pos="28" rst="0">
          <comment>aud_sclk force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_aud_sclk_out_frc" pos="24" rst="0">
          <comment>aud_sclk force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_aud_sclk_out_reg" pos="20" rst="0">
          <comment>aud_sclk pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_sclk_oen_reg" pos="17" rst="0">
          <comment>aud_sclk force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_aud_sclk_pull_frc" pos="16" rst="0">
          <comment>aud_sclk force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_aud_sclk_pull_up" pos="9" rst="0">
          <comment>aud_sclk PUll up</comment>
        </bits>
        <bits access="rw" name="pad_aud_sclk_pull_dn" pos="8" rst="0">
          <comment>aud_sclk PUll down</comment>
        </bits>
        <bits access="rw" name="pad_aud_sclk_sel" pos="3:0" rst="0">
          <comment>aud_sclk select</comment>
          <options>
            <option name="fun_aud_sclk_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_adi_sda_cfg_reg" protect="rw">
        <bits access="rw" name="pad_adi_sda_oen_frc" pos="28" rst="0">
          <comment>adi_sda force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_adi_sda_out_frc" pos="24" rst="0">
          <comment>adi_sda force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_adi_sda_out_reg" pos="20" rst="0">
          <comment>adi_sda pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_adi_sda_oen_reg" pos="17" rst="0">
          <comment>adi_sda force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_adi_sda_pull_frc" pos="16" rst="0">
          <comment>adi_sda force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_adi_sda_pull_up" pos="9" rst="0">
          <comment>adi_sda PUll up</comment>
        </bits>
        <bits access="rw" name="pad_adi_sda_pull_dn" pos="8" rst="0">
          <comment>adi_sda PUll down</comment>
        </bits>
        <bits access="rw" name="pad_adi_sda_sel" pos="3:0" rst="0">
          <comment>adi_sda select</comment>
          <options>
            <option name="fun_adi_sda_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_adi_sync_cfg_reg" protect="rw">
        <bits access="rw" name="pad_adi_sync_oen_frc" pos="28" rst="0">
          <comment>adi_sync force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_adi_sync_out_frc" pos="24" rst="0">
          <comment>adi_sync force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_adi_sync_out_reg" pos="20" rst="0">
          <comment>adi_sync pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_adi_sync_oen_reg" pos="17" rst="0">
          <comment>adi_sync force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_adi_sync_pull_frc" pos="16" rst="0">
          <comment>adi_sync force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_adi_sync_pull_up" pos="9" rst="0">
          <comment>adi_sync PUll up</comment>
        </bits>
        <bits access="rw" name="pad_adi_sync_pull_dn" pos="8" rst="0">
          <comment>adi_sync PUll down</comment>
        </bits>
        <bits access="rw" name="pad_adi_sync_sel" pos="3:0" rst="0">
          <comment>adi_sync select</comment>
          <options>
            <option name="fun_adi_sync_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_adi_scl_cfg_reg" protect="rw">
        <bits access="rw" name="pad_adi_scl_oen_frc" pos="28" rst="0">
          <comment>adi_scl force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_adi_scl_out_frc" pos="24" rst="0">
          <comment>adi_scl force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_adi_scl_out_reg" pos="20" rst="0">
          <comment>adi_scl pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_adi_scl_oen_reg" pos="17" rst="0">
          <comment>adi_scl force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_adi_scl_pull_frc" pos="16" rst="0">
          <comment>adi_scl force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_adi_scl_pull_up" pos="9" rst="0">
          <comment>adi_scl PUll up</comment>
        </bits>
        <bits access="rw" name="pad_adi_scl_pull_dn" pos="8" rst="0">
          <comment>adi_scl PUll down</comment>
        </bits>
        <bits access="rw" name="pad_adi_scl_sel" pos="3:0" rst="0">
          <comment>adi_scl select</comment>
          <options>
            <option name="fun_adi_scl_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_lcd_sio_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_lcd_sio_oen_frc" pos="28" rst="0">
          <comment>spi_lcd_sio force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sio_out_frc" pos="24" rst="0">
          <comment>spi_lcd_sio force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sio_out_reg" pos="20" rst="0">
          <comment>spi_lcd_sio pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sio_oen_reg" pos="17" rst="0">
          <comment>spi_lcd_sio force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sio_pull_frc" pos="16" rst="0">
          <comment>spi_lcd_sio force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sio_pull_up" pos="9" rst="0">
          <comment>spi_lcd_sio PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sio_pull_dn" pos="8" rst="0">
          <comment>spi_lcd_sio PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sio_sel" pos="3:0" rst="0">
          <comment>spi_lcd_sio select</comment>
          <options>
            <option name="fun_spi_lcd_sio_sel" value="0"/>
            <option name="fun_gpio_0_sel" value="1"/>
            <option name="fun_spi_flash1_clk_sel" value="2"/>
            <option name="fun_debug_bus_5_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_lcd_sdc_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_lcd_sdc_oen_frc" pos="28" rst="0">
          <comment>spi_lcd_sdc force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sdc_out_frc" pos="24" rst="0">
          <comment>spi_lcd_sdc force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sdc_out_reg" pos="20" rst="0">
          <comment>spi_lcd_sdc pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sdc_oen_reg" pos="17" rst="0">
          <comment>spi_lcd_sdc force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sdc_pull_frc" pos="16" rst="0">
          <comment>spi_lcd_sdc force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sdc_pull_up" pos="9" rst="0">
          <comment>spi_lcd_sdc PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sdc_pull_dn" pos="8" rst="0">
          <comment>spi_lcd_sdc PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_sdc_sel" pos="3:0" rst="0">
          <comment>spi_lcd_sdc select</comment>
          <options>
            <option name="fun_spi_lcd_sdc_sel" value="0"/>
            <option name="fun_gpio_1_sel" value="1"/>
            <option name="fun_spi_flash1_cs_sel" value="2"/>
            <option name="fun_i2c_m3_sda_sel" value="3"/>
            <option name="fun_debug_bus_6_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_lcd_clk_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_lcd_clk_oen_frc" pos="28" rst="0">
          <comment>spi_lcd_clk force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_clk_out_frc" pos="24" rst="0">
          <comment>spi_lcd_clk force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_clk_out_reg" pos="20" rst="0">
          <comment>spi_lcd_clk pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_clk_oen_reg" pos="17" rst="0">
          <comment>spi_lcd_clk force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_clk_pull_frc" pos="16" rst="0">
          <comment>spi_lcd_clk force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_clk_pull_up" pos="9" rst="0">
          <comment>spi_lcd_clk PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_clk_pull_dn" pos="8" rst="0">
          <comment>spi_lcd_clk PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_clk_sel" pos="3:0" rst="0">
          <comment>spi_lcd_clk select</comment>
          <options>
            <option name="fun_spi_lcd_clk_sel" value="0"/>
            <option name="fun_gpio_2_sel" value="1"/>
            <option name="fun_spi_flash1_sio_0_sel" value="2"/>
            <option name="fun_debug_bus_7_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_lcd_cs_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_lcd_cs_oen_frc" pos="28" rst="0">
          <comment>spi_lcd_cs force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_cs_out_frc" pos="24" rst="0">
          <comment>spi_lcd_cs force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_cs_out_reg" pos="20" rst="0">
          <comment>spi_lcd_cs pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_cs_oen_reg" pos="17" rst="0">
          <comment>spi_lcd_cs force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_cs_pull_frc" pos="16" rst="0">
          <comment>spi_lcd_cs force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_cs_pull_up" pos="9" rst="0">
          <comment>spi_lcd_cs PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_cs_pull_dn" pos="8" rst="0">
          <comment>spi_lcd_cs PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_cs_sel" pos="3:0" rst="0">
          <comment>spi_lcd_cs select</comment>
          <options>
            <option name="fun_spi_lcd_cs_sel" value="0"/>
            <option name="fun_gpio_3_sel" value="1"/>
            <option name="fun_spi_flash1_sio_1_sel" value="2"/>
            <option name="fun_debug_bus_8_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_lcd_select_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_lcd_select_oen_frc" pos="28" rst="0">
          <comment>spi_lcd_select force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_select_out_frc" pos="24" rst="0">
          <comment>spi_lcd_select force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_select_out_reg" pos="20" rst="0">
          <comment>spi_lcd_select pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_select_oen_reg" pos="17" rst="0">
          <comment>spi_lcd_select force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_select_pull_frc" pos="16" rst="0">
          <comment>spi_lcd_select force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_select_pull_up" pos="9" rst="0">
          <comment>spi_lcd_select PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_select_pull_dn" pos="8" rst="0">
          <comment>spi_lcd_select PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_lcd_select_sel" pos="3:0" rst="0">
          <comment>spi_lcd_select select</comment>
          <options>
            <option name="fun_spi_lcd_select_sel" value="0"/>
            <option name="fun_gpio_4_sel" value="1"/>
            <option name="fun_spi_flash1_sio_2_sel" value="2"/>
            <option name="fun_debug_bus_9_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_lcd_fmark_cfg_reg" protect="rw">
        <bits access="rw" name="pad_lcd_fmark_oen_frc" pos="28" rst="0">
          <comment>lcd_fmark force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_lcd_fmark_out_frc" pos="24" rst="0">
          <comment>lcd_fmark force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_lcd_fmark_out_reg" pos="20" rst="0">
          <comment>lcd_fmark pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_lcd_fmark_oen_reg" pos="17" rst="0">
          <comment>lcd_fmark force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_lcd_fmark_pull_frc" pos="16" rst="0">
          <comment>lcd_fmark force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_lcd_fmark_pull_up" pos="9" rst="0">
          <comment>lcd_fmark PUll up</comment>
        </bits>
        <bits access="rw" name="pad_lcd_fmark_pull_dn" pos="8" rst="0">
          <comment>lcd_fmark PUll down</comment>
        </bits>
        <bits access="rw" name="pad_lcd_fmark_sel" pos="3:0" rst="0">
          <comment>lcd_fmark select</comment>
          <options>
            <option name="fun_lcd_fmark_sel" value="0"/>
            <option name="fun_gpio_5_sel" value="1"/>
            <option name="fun_spi_flash1_sio_3_sel" value="2"/>
            <option name="fun_uart_2_txd_sel" value="4"/>
            <option name="fun_debug_bus_10_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_lcd_rstb_cfg_reg" protect="rw">
        <bits access="rw" name="pad_lcd_rstb_oen_frc" pos="28" rst="0">
          <comment>lcd_rstb force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_lcd_rstb_out_frc" pos="24" rst="0">
          <comment>lcd_rstb force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_lcd_rstb_out_reg" pos="20" rst="0">
          <comment>lcd_rstb pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_lcd_rstb_oen_reg" pos="17" rst="0">
          <comment>lcd_rstb force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_lcd_rstb_pull_frc" pos="16" rst="0">
          <comment>lcd_rstb force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_lcd_rstb_pull_up" pos="9" rst="0">
          <comment>lcd_rstb PUll up</comment>
        </bits>
        <bits access="rw" name="pad_lcd_rstb_pull_dn" pos="8" rst="0">
          <comment>lcd_rstb PUll down</comment>
        </bits>
        <bits access="rw" name="pad_lcd_rstb_sel" pos="3:0" rst="0">
          <comment>lcd_rstb select</comment>
          <options>
            <option name="fun_lcd_rstb_sel" value="0"/>
            <option name="fun_gpio_6_sel" value="1"/>
            <option name="fun_i2c_m3_scl_sel" value="3"/>
            <option name="fun_debug_bus_11_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_i2c_m1_scl_cfg_reg" protect="rw">
        <bits access="rw" name="pad_i2c_m1_scl_oen_frc" pos="28" rst="0">
          <comment>i2c_m1_scl force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_scl_out_frc" pos="24" rst="0">
          <comment>i2c_m1_scl force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_scl_out_reg" pos="20" rst="0">
          <comment>i2c_m1_scl pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_scl_oen_reg" pos="17" rst="0">
          <comment>i2c_m1_scl force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_scl_pull_frc" pos="16" rst="0">
          <comment>i2c_m1_scl force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_scl_pull_up" pos="9" rst="0">
          <comment>i2c_m1_scl PUll up</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_scl_pull_dn" pos="8" rst="0">
          <comment>i2c_m1_scl PUll down</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_scl_sel" pos="3:0" rst="0">
          <comment>i2c_m1_scl select</comment>
          <options>
            <option name="fun_i2c_m1_scl_sel" value="0"/>
            <option name="fun_gpio_16_sel" value="4"/>
            <option name="fun_debug_bus_0_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_i2c_m1_sda_cfg_reg" protect="rw">
        <bits access="rw" name="pad_i2c_m1_sda_oen_frc" pos="28" rst="0">
          <comment>i2c_m1_sda force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_sda_out_frc" pos="24" rst="0">
          <comment>i2c_m1_sda force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_sda_out_reg" pos="20" rst="0">
          <comment>i2c_m1_sda pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_sda_oen_reg" pos="17" rst="0">
          <comment>i2c_m1_sda force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_sda_pull_frc" pos="16" rst="0">
          <comment>i2c_m1_sda force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_sda_pull_up" pos="9" rst="0">
          <comment>i2c_m1_sda PUll up</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_sda_pull_dn" pos="8" rst="0">
          <comment>i2c_m1_sda PUll down</comment>
        </bits>
        <bits access="rw" name="pad_i2c_m1_sda_sel" pos="3:0" rst="0">
          <comment>i2c_m1_sda select</comment>
          <options>
            <option name="fun_i2c_m1_sda_sel" value="0"/>
            <option name="fun_gpio_17_sel" value="4"/>
            <option name="fun_debug_bus_1_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_camera_rst_l_cfg_reg" protect="rw">
        <bits access="rw" name="pad_camera_rst_l_oen_frc" pos="28" rst="0">
          <comment>camera_rst_l force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_camera_rst_l_out_frc" pos="24" rst="0">
          <comment>camera_rst_l force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_camera_rst_l_out_reg" pos="20" rst="0">
          <comment>camera_rst_l pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_camera_rst_l_oen_reg" pos="17" rst="0">
          <comment>camera_rst_l force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_camera_rst_l_pull_frc" pos="16" rst="0">
          <comment>camera_rst_l force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_camera_rst_l_pull_up" pos="9" rst="0">
          <comment>camera_rst_l PUll up</comment>
        </bits>
        <bits access="rw" name="pad_camera_rst_l_pull_dn" pos="8" rst="0">
          <comment>camera_rst_l PUll down</comment>
        </bits>
        <bits access="rw" name="pad_camera_rst_l_sel" pos="3:0" rst="0">
          <comment>camera_rst_l select</comment>
          <options>
            <option name="fun_camera_rst_l_sel" value="0"/>
            <option name="fun_i2c_m1_scl_sel" value="1"/>
            <option name="fun_gpio_18_sel" value="4"/>
            <option name="fun_debug_bus_2_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_camera_pwdn_cfg_reg" protect="rw">
        <bits access="rw" name="pad_camera_pwdn_oen_frc" pos="28" rst="0">
          <comment>camera_pwdn force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_camera_pwdn_out_frc" pos="24" rst="0">
          <comment>camera_pwdn force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_camera_pwdn_out_reg" pos="20" rst="0">
          <comment>camera_pwdn pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_camera_pwdn_oen_reg" pos="17" rst="0">
          <comment>camera_pwdn force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_camera_pwdn_pull_frc" pos="16" rst="0">
          <comment>camera_pwdn force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_camera_pwdn_pull_up" pos="9" rst="0">
          <comment>camera_pwdn PUll up</comment>
        </bits>
        <bits access="rw" name="pad_camera_pwdn_pull_dn" pos="8" rst="0">
          <comment>camera_pwdn PUll down</comment>
        </bits>
        <bits access="rw" name="pad_camera_pwdn_sel" pos="3:0" rst="0">
          <comment>camera_pwdn select</comment>
          <options>
            <option name="fun_camera_pwdn_sel" value="0"/>
            <option name="fun_i2c_m1_sda_sel" value="1"/>
            <option name="fun_gpio_19_sel" value="4"/>
            <option name="fun_debug_bus_3_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_camera_ref_clk_cfg_reg" protect="rw">
        <bits access="rw" name="pad_camera_ref_clk_oen_frc" pos="28" rst="0">
          <comment>camera_ref_clk force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_camera_ref_clk_out_frc" pos="24" rst="0">
          <comment>camera_ref_clk force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_camera_ref_clk_out_reg" pos="20" rst="0">
          <comment>camera_ref_clk pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_camera_ref_clk_oen_reg" pos="17" rst="0">
          <comment>camera_ref_clk force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_camera_ref_clk_pull_frc" pos="16" rst="0">
          <comment>camera_ref_clk force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_camera_ref_clk_pull_up" pos="9" rst="0">
          <comment>camera_ref_clk PUll up</comment>
        </bits>
        <bits access="rw" name="pad_camera_ref_clk_pull_dn" pos="8" rst="0">
          <comment>camera_ref_clk PUll down</comment>
        </bits>
        <bits access="rw" name="pad_camera_ref_clk_sel" pos="3:0" rst="0">
          <comment>camera_ref_clk select</comment>
          <options>
            <option name="fun_camera_ref_clk_sel" value="0"/>
            <option name="fun_gpio_20_sel" value="4"/>
            <option name="fun_debug_bus_4_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_camera_si_0_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_camera_si_0_oen_frc" pos="28" rst="0">
          <comment>spi_camera_si_0 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_0_out_frc" pos="24" rst="0">
          <comment>spi_camera_si_0 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_0_out_reg" pos="20" rst="0">
          <comment>spi_camera_si_0 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_0_oen_reg" pos="17" rst="0">
          <comment>spi_camera_si_0 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_0_pull_frc" pos="16" rst="0">
          <comment>spi_camera_si_0 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_0_pull_up" pos="9" rst="0">
          <comment>spi_camera_si_0 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_0_pull_dn" pos="8" rst="0">
          <comment>spi_camera_si_0 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_0_sel" pos="3:0" rst="0">
          <comment>spi_camera_si_0 select</comment>
          <options>
            <option name="fun_spi_lvds_do_sel" value="3"/>
            <option name="fun_gpio_21_sel" value="4"/>
            <option name="fun_debug_bus_5_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_camera_si_1_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_camera_si_1_oen_frc" pos="28" rst="0">
          <comment>spi_camera_si_1 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_1_out_frc" pos="24" rst="0">
          <comment>spi_camera_si_1 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_1_out_reg" pos="20" rst="0">
          <comment>spi_camera_si_1 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_1_oen_reg" pos="17" rst="0">
          <comment>spi_camera_si_1 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_1_pull_frc" pos="16" rst="0">
          <comment>spi_camera_si_1 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_1_pull_up" pos="9" rst="0">
          <comment>spi_camera_si_1 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_1_pull_dn" pos="8" rst="0">
          <comment>spi_camera_si_1 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_si_1_sel" pos="3:0" rst="0">
          <comment>spi_camera_si_1 select</comment>
          <options>
            <option name="fun_spi_camera_ssn_sel" value="2"/>
            <option name="fun_gpio_22_sel" value="4"/>
            <option name="fun_debug_bus_6_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_spi_camera_sck_cfg_reg" protect="rw">
        <bits access="rw" name="pad_spi_camera_sck_oen_frc" pos="28" rst="0">
          <comment>spi_camera_sck force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_sck_out_frc" pos="24" rst="0">
          <comment>spi_camera_sck force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_sck_out_reg" pos="20" rst="0">
          <comment>spi_camera_sck pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_sck_oen_reg" pos="17" rst="0">
          <comment>spi_camera_sck force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_sck_pull_frc" pos="16" rst="0">
          <comment>spi_camera_sck force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_sck_pull_up" pos="9" rst="0">
          <comment>spi_camera_sck PUll up</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_sck_pull_dn" pos="8" rst="0">
          <comment>spi_camera_sck PUll down</comment>
        </bits>
        <bits access="rw" name="pad_spi_camera_sck_sel" pos="3:0" rst="0">
          <comment>spi_camera_sck select</comment>
          <options>
            <option name="fun_spi_camera_sck_sel" value="0"/>
            <option name="fun_gpio_23_sel" value="4"/>
            <option name="fun_debug_bus_7_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_13_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_13_oen_frc" pos="28" rst="0">
          <comment>gpio_13 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_13_out_frc" pos="24" rst="0">
          <comment>gpio_13 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_13_out_reg" pos="20" rst="0">
          <comment>gpio_13 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_13_oen_reg" pos="17" rst="0">
          <comment>gpio_13 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_13_pull_frc" pos="16" rst="0">
          <comment>gpio_13 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_13_pull_up" pos="9" rst="0">
          <comment>gpio_13 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_13_pull_dn" pos="8" rst="0">
          <comment>gpio_13 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_13_sel" pos="3:0" rst="0">
          <comment>gpio_13 select</comment>
          <options>
            <option name="fun_gpio_13_sel" value="0"/>
            <option name="fun_pwm_lpg_out_sel" value="1"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_0_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_0_oen_frc" pos="28" rst="0">
          <comment>gpio_0 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_0_out_frc" pos="24" rst="0">
          <comment>gpio_0 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_0_out_reg" pos="20" rst="0">
          <comment>gpio_0 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_0_oen_reg" pos="17" rst="0">
          <comment>gpio_0 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_0_pull_frc" pos="16" rst="0">
          <comment>gpio_0 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_0_pull_up" pos="9" rst="0">
          <comment>gpio_0 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_0_pull_dn" pos="8" rst="0">
          <comment>gpio_0 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_0_sel" pos="3:0" rst="0">
          <comment>gpio_0 select</comment>
          <options>
            <option name="fun_gpio_0_sel" value="0"/>
            <option name="fun_spi_flash1_clk_sel" value="1"/>
            <option name="fun_spi_2_clk_sel" value="2"/>
            <option name="fun_i2s2_bck_sel" value="3"/>
            <option name="fun_debug_clk_sel" value="7"/>
            <option name="fun_wcn_ext_m_bb_senb_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_1_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_1_oen_frc" pos="28" rst="0">
          <comment>gpio_1 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_1_out_frc" pos="24" rst="0">
          <comment>gpio_1 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_1_out_reg" pos="20" rst="0">
          <comment>gpio_1 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_1_oen_reg" pos="17" rst="0">
          <comment>gpio_1 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_1_pull_frc" pos="16" rst="0">
          <comment>gpio_1 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_1_pull_up" pos="9" rst="0">
          <comment>gpio_1 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_1_pull_dn" pos="8" rst="0">
          <comment>gpio_1 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_1_sel" pos="3:0" rst="0">
          <comment>gpio_1 select</comment>
          <options>
            <option name="fun_gpio_1_sel" value="0"/>
            <option name="fun_spi_flash1_cs_sel" value="1"/>
            <option name="fun_spi_2_cs_0_sel" value="2"/>
            <option name="fun_i2s2_lrck_sel" value="3"/>
            <option name="fun_uart_txd_rf_sel" value="5"/>
            <option name="fun_debug_bus_0_sel" value="7"/>
            <option name="fun_wcn_ext_m_bb_sclk_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_2_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_2_oen_frc" pos="28" rst="0">
          <comment>gpio_2 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_2_out_frc" pos="24" rst="0">
          <comment>gpio_2 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_2_out_reg" pos="20" rst="0">
          <comment>gpio_2 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_2_oen_reg" pos="17" rst="0">
          <comment>gpio_2 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_2_pull_frc" pos="16" rst="0">
          <comment>gpio_2 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_2_pull_up" pos="9" rst="0">
          <comment>gpio_2 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_2_pull_dn" pos="8" rst="0">
          <comment>gpio_2 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_2_sel" pos="3:0" rst="0">
          <comment>gpio_2 select</comment>
          <options>
            <option name="fun_gpio_2_sel" value="0"/>
            <option name="fun_spi_flash1_sio_0_sel" value="1"/>
            <option name="fun_spi_2_dio_0_sel" value="2"/>
            <option name="fun_wcn_hst_txd_sel" value="5"/>
            <option name="fun_debug_bus_1_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_3_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_3_oen_frc" pos="28" rst="0">
          <comment>gpio_3 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_3_out_frc" pos="24" rst="0">
          <comment>gpio_3 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_3_out_reg" pos="20" rst="0">
          <comment>gpio_3 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_3_oen_reg" pos="17" rst="0">
          <comment>gpio_3 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_3_pull_frc" pos="16" rst="0">
          <comment>gpio_3 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_3_pull_up" pos="9" rst="0">
          <comment>gpio_3 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_3_pull_dn" pos="8" rst="0">
          <comment>gpio_3 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_3_sel" pos="3:0" rst="0">
          <comment>gpio_3 select</comment>
          <options>
            <option name="fun_gpio_3_sel" value="0"/>
            <option name="fun_spi_flash1_sio_1_sel" value="1"/>
            <option name="fun_i2s2_sdat_o_sel" value="3"/>
            <option name="fun_debug_bus_2_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_4_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_4_oen_frc" pos="28" rst="0">
          <comment>gpio_4 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_4_out_frc" pos="24" rst="0">
          <comment>gpio_4 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_4_out_reg" pos="20" rst="0">
          <comment>gpio_4 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_4_oen_reg" pos="17" rst="0">
          <comment>gpio_4 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_4_pull_frc" pos="16" rst="0">
          <comment>gpio_4 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_4_pull_up" pos="9" rst="0">
          <comment>gpio_4 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_4_pull_dn" pos="8" rst="0">
          <comment>gpio_4 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_4_sel" pos="3:0" rst="0">
          <comment>gpio_4 select</comment>
          <options>
            <option name="fun_gpio_4_sel" value="0"/>
            <option name="fun_spi_flash1_sio_2_sel" value="1"/>
            <option name="fun_spi_2_cs_1_sel" value="2"/>
            <option name="fun_pwl_out_0_sel" value="3"/>
            <option name="fun_wcn_jtag_tdo_sel" value="4"/>
            <option name="fun_i2c_m3_scl_sel" value="6"/>
            <option name="fun_debug_bus_3_sel" value="7"/>
            <option name="fun_wcn_ext_m_bb_sdo_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_5_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_5_oen_frc" pos="28" rst="0">
          <comment>gpio_5 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_5_out_frc" pos="24" rst="0">
          <comment>gpio_5 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_5_out_reg" pos="20" rst="0">
          <comment>gpio_5 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_5_oen_reg" pos="17" rst="0">
          <comment>gpio_5 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_5_pull_frc" pos="16" rst="0">
          <comment>gpio_5 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_5_pull_up" pos="9" rst="0">
          <comment>gpio_5 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_5_pull_dn" pos="8" rst="0">
          <comment>gpio_5 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_5_sel" pos="3:0" rst="0">
          <comment>gpio_5 select</comment>
          <options>
            <option name="fun_gpio_5_sel" value="0"/>
            <option name="fun_spi_flash1_sio_3_sel" value="1"/>
            <option name="fun_pwt_out_sel" value="2"/>
            <option name="fun_wcn_uart_rts_sel" value="4"/>
            <option name="fun_wcn_uart_txd_sel" value="5"/>
            <option name="fun_i2c_m3_sda_sel" value="6"/>
            <option name="fun_debug_bus_4_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_7_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_7_oen_frc" pos="28" rst="0">
          <comment>gpio_7 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_7_out_frc" pos="24" rst="0">
          <comment>gpio_7 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_7_out_reg" pos="20" rst="0">
          <comment>gpio_7 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_7_oen_reg" pos="17" rst="0">
          <comment>gpio_7 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_7_pull_frc" pos="16" rst="0">
          <comment>gpio_7 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_7_pull_up" pos="9" rst="0">
          <comment>gpio_7 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_7_pull_dn" pos="8" rst="0">
          <comment>gpio_7 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_7_sel" pos="3:0" rst="0">
          <comment>gpio_7 select</comment>
          <options>
            <option name="fun_gpio_7_sel" value="0"/>
            <option name="fun_sdmmc2_clk_sel" value="1"/>
            <option name="fun_spi_1_clk_sel" value="2"/>
            <option name="fun_pwl_out_1_sel" value="3"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_ap_jtag_tck_cfg_reg" protect="rw">
        <bits access="rw" name="pad_ap_jtag_tck_oen_frc" pos="28" rst="0">
          <comment>ap_jtag_tck force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tck_out_frc" pos="24" rst="0">
          <comment>ap_jtag_tck force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tck_out_reg" pos="20" rst="0">
          <comment>ap_jtag_tck pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tck_oen_reg" pos="17" rst="0">
          <comment>ap_jtag_tck force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tck_pull_frc" pos="16" rst="0">
          <comment>ap_jtag_tck force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tck_pull_up" pos="9" rst="0">
          <comment>ap_jtag_tck PUll up</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tck_pull_dn" pos="8" rst="0">
          <comment>ap_jtag_tck PUll down</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tck_sel" pos="3:0" rst="0">
          <comment>ap_jtag_tck select</comment>
          <options>
            <option name="fun_sdmmc2_cmd_sel" value="1"/>
            <option name="fun_spi_1_cs_0_sel" value="2"/>
            <option name="fun_gpio_8_sel" value="5"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_ap_jtag_trst_cfg_reg" protect="rw">
        <bits access="rw" name="pad_ap_jtag_trst_oen_frc" pos="28" rst="0">
          <comment>ap_jtag_trst force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_trst_out_frc" pos="24" rst="0">
          <comment>ap_jtag_trst force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_trst_out_reg" pos="20" rst="0">
          <comment>ap_jtag_trst pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_trst_oen_reg" pos="17" rst="0">
          <comment>ap_jtag_trst force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_trst_pull_frc" pos="16" rst="0">
          <comment>ap_jtag_trst force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_trst_pull_up" pos="9" rst="0">
          <comment>ap_jtag_trst PUll up</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_trst_pull_dn" pos="8" rst="0">
          <comment>ap_jtag_trst PUll down</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_trst_sel" pos="3:0" rst="0">
          <comment>ap_jtag_trst select</comment>
          <options>
            <option name="fun_sdmmc2_data_0_sel" value="1"/>
            <option name="fun_spi_1_dio_0_sel" value="2"/>
            <option name="fun_gpio_9_sel" value="5"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_ap_jtag_tms_cfg_reg" protect="rw">
        <bits access="rw" name="pad_ap_jtag_tms_oen_frc" pos="28" rst="0">
          <comment>ap_jtag_tms force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tms_out_frc" pos="24" rst="0">
          <comment>ap_jtag_tms force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tms_out_reg" pos="20" rst="0">
          <comment>ap_jtag_tms pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tms_oen_reg" pos="17" rst="0">
          <comment>ap_jtag_tms force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tms_pull_frc" pos="16" rst="0">
          <comment>ap_jtag_tms force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tms_pull_up" pos="9" rst="0">
          <comment>ap_jtag_tms PUll up</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tms_pull_dn" pos="8" rst="0">
          <comment>ap_jtag_tms PUll down</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tms_sel" pos="3:0" rst="0">
          <comment>ap_jtag_tms select</comment>
          <options>
            <option name="fun_ap_jtag_tms_sel" value="0"/>
            <option name="fun_sdmmc2_data_1_sel" value="1"/>
            <option name="fun_gpio_10_sel" value="5"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_ap_jtag_tdi_cfg_reg" protect="rw">
        <bits access="rw" name="pad_ap_jtag_tdi_oen_frc" pos="28" rst="0">
          <comment>ap_jtag_tdi force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_out_frc" pos="24" rst="0">
          <comment>ap_jtag_tdi force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_out_reg" pos="20" rst="0">
          <comment>ap_jtag_tdi pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_oen_reg" pos="17" rst="0">
          <comment>ap_jtag_tdi force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_pull_frc" pos="16" rst="0">
          <comment>ap_jtag_tdi force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_pull_up" pos="9" rst="0">
          <comment>ap_jtag_tdi PUll up</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_pull_dn" pos="8" rst="0">
          <comment>ap_jtag_tdi PUll down</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_sel" pos="3:0" rst="0">
          <comment>ap_jtag_tdi select</comment>
          <options>
            <option name="fun_sdmmc2_data_2_sel" value="1"/>
            <option name="fun_spi_1_cs_1_sel" value="2"/>
            <option name="fun_gpio_11_sel" value="5"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_ap_jtag_tdo_cfg_reg" protect="rw">
        <bits access="rw" name="pad_ap_jtag_tdo_oen_frc" pos="28" rst="0">
          <comment>ap_jtag_tdo force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_out_frc" pos="24" rst="0">
          <comment>ap_jtag_tdo force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_out_reg" pos="20" rst="0">
          <comment>ap_jtag_tdo pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_oen_reg" pos="17" rst="0">
          <comment>ap_jtag_tdo force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_pull_frc" pos="16" rst="0">
          <comment>ap_jtag_tdo force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_pull_up" pos="9" rst="0">
          <comment>ap_jtag_tdo PUll up</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_pull_dn" pos="8" rst="0">
          <comment>ap_jtag_tdo PUll down</comment>
        </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_sel" pos="3:0" rst="0">
          <comment>ap_jtag_tdo select</comment>
          <options>
            <option name="fun_ap_jtag_tdo_sel" value="0"/>
            <option name="fun_sdmmc2_data_3_sel" value="1"/>
            <option name="fun_zsp_jtag_tdo_sel" value="3"/>
            <option name="fun_rfdig_jtag_tdo_sel" value="4"/>
            <option name="fun_gpio_12_sel" value="5"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_14_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_14_oen_frc" pos="28" rst="0">
          <comment>gpio_14 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_14_out_frc" pos="24" rst="0">
          <comment>gpio_14 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_14_out_reg" pos="20" rst="0">
          <comment>gpio_14 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_14_oen_reg" pos="17" rst="0">
          <comment>gpio_14 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_14_pull_frc" pos="16" rst="0">
          <comment>gpio_14 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_14_pull_up" pos="9" rst="0">
          <comment>gpio_14 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_14_pull_dn" pos="8" rst="0">
          <comment>gpio_14 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_14_sel" pos="3:0" rst="0">
          <comment>gpio_14 select</comment>
          <options>
            <option name="fun_gpio_14_sel" value="0"/>
            <option name="fun_i2c_m2_scl_sel" value="1"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_15_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_15_oen_frc" pos="28" rst="0">
          <comment>gpio_15 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_15_out_frc" pos="24" rst="0">
          <comment>gpio_15 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_15_out_reg" pos="20" rst="0">
          <comment>gpio_15 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_15_oen_reg" pos="17" rst="0">
          <comment>gpio_15 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_15_pull_frc" pos="16" rst="0">
          <comment>gpio_15 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_15_pull_up" pos="9" rst="0">
          <comment>gpio_15 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_15_pull_dn" pos="8" rst="0">
          <comment>gpio_15 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_15_sel" pos="3:0" rst="0">
          <comment>gpio_15 select</comment>
          <options>
            <option name="fun_gpio_15_sel" value="0"/>
            <option name="fun_i2c_m2_sda_sel" value="1"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_18_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_18_oen_frc" pos="28" rst="0">
          <comment>gpio_18 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_18_out_frc" pos="24" rst="0">
          <comment>gpio_18 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_18_out_reg" pos="20" rst="0">
          <comment>gpio_18 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_18_oen_reg" pos="17" rst="0">
          <comment>gpio_18 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_18_pull_frc" pos="16" rst="0">
          <comment>gpio_18 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_18_pull_up" pos="9" rst="0">
          <comment>gpio_18 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_18_pull_dn" pos="8" rst="0">
          <comment>gpio_18 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_18_sel" pos="3:0" rst="0">
          <comment>gpio_18 select</comment>
          <options>
            <option name="fun_gpio_18_sel" value="0"/>
            <option name="fun_zsp_uart_txd_sel" value="3"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_19_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_19_oen_frc" pos="28" rst="0">
          <comment>gpio_19 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_19_out_frc" pos="24" rst="0">
          <comment>gpio_19 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_19_out_reg" pos="20" rst="0">
          <comment>gpio_19 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_19_oen_reg" pos="17" rst="0">
          <comment>gpio_19 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_19_pull_frc" pos="16" rst="0">
          <comment>gpio_19 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_19_pull_up" pos="9" rst="0">
          <comment>gpio_19 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_19_pull_dn" pos="8" rst="0">
          <comment>gpio_19 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_19_sel" pos="3:0" rst="0">
          <comment>gpio_19 select</comment>
          <options>
            <option name="fun_gpio_19_sel" value="0"/>
            <option name="fun_uart_1_rts_sel" value="1"/>
            <option name="fun_uart_3_txd_sel" value="3"/>
            <option name="fun_wcn_uart_txd_sel" value="4"/>
            <option name="fun_wcn_uart_rts_sel" value="5"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_20_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_20_oen_frc" pos="28" rst="0">
          <comment>gpio_20 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_20_out_frc" pos="24" rst="0">
          <comment>gpio_20 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_20_out_reg" pos="20" rst="0">
          <comment>gpio_20 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_20_oen_reg" pos="17" rst="0">
          <comment>gpio_20 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_20_pull_frc" pos="16" rst="0">
          <comment>gpio_20 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_20_pull_up" pos="9" rst="0">
          <comment>gpio_20 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_20_pull_dn" pos="8" rst="0">
          <comment>gpio_20 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_20_sel" pos="3:0" rst="0">
          <comment>gpio_20 select</comment>
          <options>
            <option name="fun_gpio_20_sel" value="0"/>
            <option name="fun_zsp_uart_rts_sel" value="5"/>
            <option name="fun_debug_bus_12_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_21_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_21_oen_frc" pos="28" rst="0">
          <comment>gpio_21 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_21_out_frc" pos="24" rst="0">
          <comment>gpio_21 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_21_out_reg" pos="20" rst="0">
          <comment>gpio_21 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_21_oen_reg" pos="17" rst="0">
          <comment>gpio_21 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_21_pull_frc" pos="16" rst="0">
          <comment>gpio_21 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_21_pull_up" pos="9" rst="0">
          <comment>gpio_21 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_21_pull_dn" pos="8" rst="0">
          <comment>gpio_21 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_21_sel" pos="3:0" rst="0">
          <comment>gpio_21 select</comment>
          <options>
            <option name="fun_gpio_21_sel" value="0"/>
            <option name="fun_uart_2_txd_sel" value="1"/>
            <option name="fun_uart_3_txd_sel" value="2"/>
            <option name="fun_zsp_uart_txd_sel" value="3"/>
            <option name="fun_uart_3_rts_sel" value="4"/>
            <option name="fun_debug_bus_13_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_22_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_22_oen_frc" pos="28" rst="0">
          <comment>gpio_22 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_22_out_frc" pos="24" rst="0">
          <comment>gpio_22 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_22_out_reg" pos="20" rst="0">
          <comment>gpio_22 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_22_oen_reg" pos="17" rst="0">
          <comment>gpio_22 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_22_pull_frc" pos="16" rst="0">
          <comment>gpio_22 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_22_pull_up" pos="9" rst="0">
          <comment>gpio_22 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_22_pull_dn" pos="8" rst="0">
          <comment>gpio_22 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_22_sel" pos="3:0" rst="0">
          <comment>gpio_22 select</comment>
          <options>
            <option name="fun_gpio_22_sel" value="0"/>
            <option name="fun_zsp_uart_txd_sel" value="5"/>
            <option name="fun_debug_bus_14_sel" value="7"/>
            <option name="fun_i2c_m3_scl_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_23_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_23_oen_frc" pos="28" rst="0">
          <comment>gpio_23 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_23_out_frc" pos="24" rst="0">
          <comment>gpio_23 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_23_out_reg" pos="20" rst="0">
          <comment>gpio_23 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_23_oen_reg" pos="17" rst="0">
          <comment>gpio_23 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_23_pull_frc" pos="16" rst="0">
          <comment>gpio_23 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_23_pull_up" pos="9" rst="0">
          <comment>gpio_23 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_23_pull_dn" pos="8" rst="0">
          <comment>gpio_23 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_23_sel" pos="3:0" rst="0">
          <comment>gpio_23 select</comment>
          <options>
            <option name="fun_gpio_23_sel" value="0"/>
            <option name="fun_uart_2_rts_sel" value="1"/>
            <option name="fun_uart_3_rts_sel" value="2"/>
            <option name="fun_zsp_uart_rts_sel" value="3"/>
            <option name="fun_uart_3_txd_sel" value="4"/>
            <option name="fun_debug_bus_15_sel" value="7"/>
            <option name="fun_i2c_m3_sda_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_8_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_8_oen_frc" pos="28" rst="0">
          <comment>gpio_8 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_8_out_frc" pos="24" rst="0">
          <comment>gpio_8 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_8_out_reg" pos="20" rst="0">
          <comment>gpio_8 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_8_oen_reg" pos="17" rst="0">
          <comment>gpio_8 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_8_pull_frc" pos="16" rst="0">
          <comment>gpio_8 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_8_pull_up" pos="9" rst="0">
          <comment>gpio_8 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_8_pull_dn" pos="8" rst="0">
          <comment>gpio_8 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_8_sel" pos="3:0" rst="0">
          <comment>gpio_8 select</comment>
          <options>
            <option name="fun_gpio_8_sel" value="0"/>
            <option name="fun_spi_1_cs_1_sel" value="1"/>
            <option name="fun_rfdig_gpio_8_sel" value="2"/>
            <option name="fun_lte_gpo_6_sel" value="3"/>
            <option name="fun_gpo_0_sel" value="6"/>
            <option name="fun_digrf_strobe_s_o_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_9_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_9_oen_frc" pos="28" rst="0">
          <comment>gpio_9 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_9_out_frc" pos="24" rst="0">
          <comment>gpio_9 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_9_out_reg" pos="20" rst="0">
          <comment>gpio_9 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_9_oen_reg" pos="17" rst="0">
          <comment>gpio_9 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_9_pull_frc" pos="16" rst="0">
          <comment>gpio_9 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_9_pull_up" pos="9" rst="0">
          <comment>gpio_9 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_9_pull_dn" pos="8" rst="0">
          <comment>gpio_9 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_9_sel" pos="3:0" rst="0">
          <comment>gpio_9 select</comment>
          <options>
            <option name="fun_gpio_9_sel" value="0"/>
            <option name="fun_spi_1_clk_sel" value="1"/>
            <option name="fun_rfdig_gpio_9_sel" value="2"/>
            <option name="fun_lte_gpo_9_sel" value="3"/>
            <option name="fun_lte_spi_sdo_sel" value="4"/>
            <option name="fun_gpo_1_sel" value="6"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_10_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_10_oen_frc" pos="28" rst="0">
          <comment>gpio_10 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_10_out_frc" pos="24" rst="0">
          <comment>gpio_10 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_10_out_reg" pos="20" rst="0">
          <comment>gpio_10 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_10_oen_reg" pos="17" rst="0">
          <comment>gpio_10 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_10_pull_frc" pos="16" rst="0">
          <comment>gpio_10 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_10_pull_up" pos="9" rst="0">
          <comment>gpio_10 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_10_pull_dn" pos="8" rst="0">
          <comment>gpio_10 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_10_sel" pos="3:0" rst="0">
          <comment>gpio_10 select</comment>
          <options>
            <option name="fun_gpio_10_sel" value="0"/>
            <option name="fun_spi_1_cs_0_sel" value="1"/>
            <option name="fun_lte_spi_cs_sel" value="2"/>
            <option name="fun_gpo_2_sel" value="6"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_11_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_11_oen_frc" pos="28" rst="0">
          <comment>gpio_11 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_11_out_frc" pos="24" rst="0">
          <comment>gpio_11 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_11_out_reg" pos="20" rst="0">
          <comment>gpio_11 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_11_oen_reg" pos="17" rst="0">
          <comment>gpio_11 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_11_pull_frc" pos="16" rst="0">
          <comment>gpio_11 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_11_pull_up" pos="9" rst="0">
          <comment>gpio_11 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_11_pull_dn" pos="8" rst="0">
          <comment>gpio_11 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_11_sel" pos="3:0" rst="0">
          <comment>gpio_11 select</comment>
          <options>
            <option name="fun_gpio_11_sel" value="0"/>
            <option name="fun_spi_1_dio_0_sel" value="1"/>
            <option name="fun_lte_spi_sclk_sel" value="2"/>
            <option name="fun_gpo_3_sel" value="6"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_gpio_12_cfg_reg" protect="rw">
        <bits access="rw" name="pad_gpio_12_oen_frc" pos="28" rst="0">
          <comment>gpio_12 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_12_out_frc" pos="24" rst="0">
          <comment>gpio_12 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_12_out_reg" pos="20" rst="0">
          <comment>gpio_12 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_12_oen_reg" pos="17" rst="0">
          <comment>gpio_12 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_gpio_12_pull_frc" pos="16" rst="0">
          <comment>gpio_12 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_gpio_12_pull_up" pos="9" rst="0">
          <comment>gpio_12 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_gpio_12_pull_dn" pos="8" rst="0">
          <comment>gpio_12 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_gpio_12_sel" pos="3:0" rst="0">
          <comment>gpio_12 select</comment>
          <options>
            <option name="fun_gpio_12_sel" value="0"/>
            <option name="fun_lte_spi_sdio_sel" value="2"/>
            <option name="fun_gpo_4_sel" value="6"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyin_0_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyin_0_oen_frc" pos="28" rst="0">
          <comment>keyin_0 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_0_out_frc" pos="24" rst="0">
          <comment>keyin_0 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_0_out_reg" pos="20" rst="0">
          <comment>keyin_0 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_0_oen_reg" pos="17" rst="0">
          <comment>keyin_0 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_0_pull_frc" pos="16" rst="0">
          <comment>keyin_0 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyin_0_pull_up" pos="9" rst="0">
          <comment>keyin_0 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyin_0_pull_dn" pos="8" rst="0">
          <comment>keyin_0 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyin_0_sel" pos="3:0" rst="0">
          <comment>keyin_0 select</comment>
          <options>
            <option name="fun_keyin_0_sel" value="0"/>
            <option name="fun_debug_bus_8_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyin_1_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyin_1_oen_frc" pos="28" rst="0">
          <comment>keyin_1 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_1_out_frc" pos="24" rst="0">
          <comment>keyin_1 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_1_out_reg" pos="20" rst="0">
          <comment>keyin_1 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_1_oen_reg" pos="17" rst="0">
          <comment>keyin_1 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_1_pull_frc" pos="16" rst="0">
          <comment>keyin_1 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyin_1_pull_up" pos="9" rst="0">
          <comment>keyin_1 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyin_1_pull_dn" pos="8" rst="0">
          <comment>keyin_1 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyin_1_sel" pos="3:0" rst="0">
          <comment>keyin_1 select</comment>
          <options>
            <option name="fun_keyin_1_sel" value="0"/>
            <option name="fun_debug_bus_9_sel" value="7"/>
            <option name="fun_wcn_rf_agc_index_out_0_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyin_2_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyin_2_oen_frc" pos="28" rst="0">
          <comment>keyin_2 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_2_out_frc" pos="24" rst="0">
          <comment>keyin_2 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_2_out_reg" pos="20" rst="0">
          <comment>keyin_2 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_2_oen_reg" pos="17" rst="0">
          <comment>keyin_2 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_2_pull_frc" pos="16" rst="0">
          <comment>keyin_2 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyin_2_pull_up" pos="9" rst="0">
          <comment>keyin_2 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyin_2_pull_dn" pos="8" rst="0">
          <comment>keyin_2 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyin_2_sel" pos="3:0" rst="0">
          <comment>keyin_2 select</comment>
          <options>
            <option name="fun_keyin_2_sel" value="0"/>
            <option name="fun_debug_bus_10_sel" value="7"/>
            <option name="fun_wcn_rf_agc_index_out_1_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyin_3_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyin_3_oen_frc" pos="28" rst="0">
          <comment>keyin_3 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_3_out_frc" pos="24" rst="0">
          <comment>keyin_3 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_3_out_reg" pos="20" rst="0">
          <comment>keyin_3 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_3_oen_reg" pos="17" rst="0">
          <comment>keyin_3 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_3_pull_frc" pos="16" rst="0">
          <comment>keyin_3 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyin_3_pull_up" pos="9" rst="0">
          <comment>keyin_3 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyin_3_pull_dn" pos="8" rst="0">
          <comment>keyin_3 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyin_3_sel" pos="3:0" rst="0">
          <comment>keyin_3 select</comment>
          <options>
            <option name="fun_keyin_3_sel" value="0"/>
            <option name="fun_debug_bus_11_sel" value="7"/>
            <option name="fun_wcn_rf_agc_index_out_2_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyin_4_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyin_4_oen_frc" pos="28" rst="0">
          <comment>keyin_4 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_4_out_frc" pos="24" rst="0">
          <comment>keyin_4 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_4_out_reg" pos="20" rst="0">
          <comment>keyin_4 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_4_oen_reg" pos="17" rst="0">
          <comment>keyin_4 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_4_pull_frc" pos="16" rst="0">
          <comment>keyin_4 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyin_4_pull_up" pos="9" rst="0">
          <comment>keyin_4 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyin_4_pull_dn" pos="8" rst="0">
          <comment>keyin_4 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyin_4_sel" pos="3:0" rst="0">
          <comment>keyin_4 select</comment>
          <options>
            <option name="fun_keyin_4_sel" value="0"/>
            <option name="fun_debug_bus_12_sel" value="7"/>
            <option name="fun_wcn_rf_agc_index_out_3_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyin_5_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyin_5_oen_frc" pos="28" rst="0">
          <comment>keyin_5 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_5_out_frc" pos="24" rst="0">
          <comment>keyin_5 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_5_out_reg" pos="20" rst="0">
          <comment>keyin_5 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_5_oen_reg" pos="17" rst="0">
          <comment>keyin_5 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyin_5_pull_frc" pos="16" rst="0">
          <comment>keyin_5 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyin_5_pull_up" pos="9" rst="0">
          <comment>keyin_5 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyin_5_pull_dn" pos="8" rst="0">
          <comment>keyin_5 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyin_5_sel" pos="3:0" rst="0">
          <comment>keyin_5 select</comment>
          <options>
            <option name="fun_keyin_5_sel" value="0"/>
            <option name="fun_uart_2_txd_sel" value="3"/>
            <option name="fun_uart_3_rts_sel" value="4"/>
            <option name="fun_debug_bus_13_sel" value="7"/>
            <option name="fun_wcn_rf_rxon_out_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyout_0_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyout_0_oen_frc" pos="28" rst="0">
          <comment>keyout_0 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_0_out_frc" pos="24" rst="0">
          <comment>keyout_0 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_0_out_reg" pos="20" rst="0">
          <comment>keyout_0 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_0_oen_reg" pos="17" rst="0">
          <comment>keyout_0 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_0_pull_frc" pos="16" rst="0">
          <comment>keyout_0 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyout_0_pull_up" pos="9" rst="0">
          <comment>keyout_0 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyout_0_pull_dn" pos="8" rst="0">
          <comment>keyout_0 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyout_0_sel" pos="3:0" rst="0">
          <comment>keyout_0 select</comment>
          <options>
            <option name="fun_keyout_0_sel" value="0"/>
            <option name="fun_debug_bus_14_sel" value="7"/>
            <option name="fun_wcn_rf_txon_out_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyout_1_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyout_1_oen_frc" pos="28" rst="0">
          <comment>keyout_1 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_1_out_frc" pos="24" rst="0">
          <comment>keyout_1 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_1_out_reg" pos="20" rst="0">
          <comment>keyout_1 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_1_oen_reg" pos="17" rst="0">
          <comment>keyout_1 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_1_pull_frc" pos="16" rst="0">
          <comment>keyout_1 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyout_1_pull_up" pos="9" rst="0">
          <comment>keyout_1 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyout_1_pull_dn" pos="8" rst="0">
          <comment>keyout_1 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyout_1_sel" pos="3:0" rst="0">
          <comment>keyout_1 select</comment>
          <options>
            <option name="fun_keyout_1_sel" value="0"/>
            <option name="fun_debug_bus_15_sel" value="7"/>
            <option name="fun_wcn_rf_apc_out_0_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyout_2_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyout_2_oen_frc" pos="28" rst="0">
          <comment>keyout_2 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_2_out_frc" pos="24" rst="0">
          <comment>keyout_2 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_2_out_reg" pos="20" rst="0">
          <comment>keyout_2 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_2_oen_reg" pos="17" rst="0">
          <comment>keyout_2 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_2_pull_frc" pos="16" rst="0">
          <comment>keyout_2 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyout_2_pull_up" pos="9" rst="0">
          <comment>keyout_2 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyout_2_pull_dn" pos="8" rst="0">
          <comment>keyout_2 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyout_2_sel" pos="3:0" rst="0">
          <comment>keyout_2 select</comment>
          <options>
            <option name="fun_keyout_2_sel" value="0"/>
            <option name="fun_debug_clk_sel" value="7"/>
            <option name="fun_wcn_rf_apc_out_1_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyout_3_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyout_3_oen_frc" pos="28" rst="0">
          <comment>keyout_3 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_3_out_frc" pos="24" rst="0">
          <comment>keyout_3 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_3_out_reg" pos="20" rst="0">
          <comment>keyout_3 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_3_oen_reg" pos="17" rst="0">
          <comment>keyout_3 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_3_pull_frc" pos="16" rst="0">
          <comment>keyout_3 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyout_3_pull_up" pos="9" rst="0">
          <comment>keyout_3 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyout_3_pull_dn" pos="8" rst="0">
          <comment>keyout_3 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyout_3_sel" pos="3:0" rst="0">
          <comment>keyout_3 select</comment>
          <options>
            <option name="fun_keyout_3_sel" value="0"/>
            <option name="fun_wcn_rf_apc_out_2_sel" value="8"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyout_4_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyout_4_oen_frc" pos="28" rst="0">
          <comment>keyout_4 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_4_out_frc" pos="24" rst="0">
          <comment>keyout_4 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_4_out_reg" pos="20" rst="0">
          <comment>keyout_4 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_4_oen_reg" pos="17" rst="0">
          <comment>keyout_4 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_4_pull_frc" pos="16" rst="0">
          <comment>keyout_4 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyout_4_pull_up" pos="9" rst="0">
          <comment>keyout_4 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyout_4_pull_dn" pos="8" rst="0">
          <comment>keyout_4 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyout_4_sel" pos="3:0" rst="0">
          <comment>keyout_4 select</comment>
          <options>
            <option name="fun_keyout_4_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_keyout_5_cfg_reg" protect="rw">
        <bits access="rw" name="pad_keyout_5_oen_frc" pos="28" rst="0">
          <comment>keyout_5 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_5_out_frc" pos="24" rst="0">
          <comment>keyout_5 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_5_out_reg" pos="20" rst="0">
          <comment>keyout_5 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_5_oen_reg" pos="17" rst="0">
          <comment>keyout_5 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_keyout_5_pull_frc" pos="16" rst="0">
          <comment>keyout_5 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_keyout_5_pull_up" pos="9" rst="0">
          <comment>keyout_5 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_keyout_5_pull_dn" pos="8" rst="0">
          <comment>keyout_5 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_keyout_5_sel" pos="3:0" rst="0">
          <comment>keyout_5 select</comment>
          <options>
            <option name="fun_keyout_5_sel" value="0"/>
            <option name="fun_uart_2_rts_sel" value="3"/>
            <option name="fun_uart_3_txd_sel" value="4"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_debug_host_rx_cfg_reg" protect="rw">
        <bits access="rw" name="pad_debug_host_rx_oen_frc" pos="28" rst="0">
          <comment>debug_host_rx force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_rx_out_frc" pos="24" rst="0">
          <comment>debug_host_rx force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_rx_out_reg" pos="20" rst="0">
          <comment>debug_host_rx pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_rx_oen_reg" pos="17" rst="0">
          <comment>debug_host_rx force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_rx_pull_frc" pos="16" rst="0">
          <comment>debug_host_rx force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_rx_pull_up" pos="9" rst="0">
          <comment>debug_host_rx PUll up</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_rx_pull_dn" pos="8" rst="0">
          <comment>debug_host_rx PUll down</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_rx_sel" pos="3:0" rst="0">
          <comment>debug_host_rx select</comment>
          <options>
            <option name="fun_gpio_16_sel" value="1"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_debug_host_tx_cfg_reg" protect="rw">
        <bits access="rw" name="pad_debug_host_tx_oen_frc" pos="28" rst="0">
          <comment>debug_host_tx force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_tx_out_frc" pos="24" rst="0">
          <comment>debug_host_tx force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_tx_out_reg" pos="20" rst="0">
          <comment>debug_host_tx pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_tx_oen_reg" pos="17" rst="0">
          <comment>debug_host_tx force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_tx_pull_frc" pos="16" rst="0">
          <comment>debug_host_tx force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_tx_pull_up" pos="9" rst="0">
          <comment>debug_host_tx PUll up</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_tx_pull_dn" pos="8" rst="0">
          <comment>debug_host_tx PUll down</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_tx_sel" pos="3:0" rst="0">
          <comment>debug_host_tx select</comment>
          <options>
            <option name="fun_debug_host_tx_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_debug_host_clk_cfg_reg" protect="rw">
        <bits access="rw" name="pad_debug_host_clk_oen_frc" pos="28" rst="0">
          <comment>debug_host_clk force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_clk_out_frc" pos="24" rst="0">
          <comment>debug_host_clk force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_clk_out_reg" pos="20" rst="0">
          <comment>debug_host_clk pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_clk_oen_reg" pos="17" rst="0">
          <comment>debug_host_clk force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_clk_pull_frc" pos="16" rst="0">
          <comment>debug_host_clk force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_clk_pull_up" pos="9" rst="0">
          <comment>debug_host_clk PUll up</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_clk_pull_dn" pos="8" rst="0">
          <comment>debug_host_clk PUll down</comment>
        </bits>
        <bits access="rw" name="pad_debug_host_clk_sel" pos="3:0" rst="0">
          <comment>debug_host_clk select</comment>
          <options>
            <option name="fun_debug_host_clk_sel" value="0"/>
            <option name="fun_gpio_17_sel" value="1"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sim_1_clk_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sim_1_clk_oen_frc" pos="28" rst="0">
          <comment>sim_1_clk force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_clk_out_frc" pos="24" rst="0">
          <comment>sim_1_clk force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_clk_out_reg" pos="20" rst="0">
          <comment>sim_1_clk pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_clk_oen_reg" pos="17" rst="0">
          <comment>sim_1_clk force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_clk_pull_frc" pos="16" rst="0">
          <comment>sim_1_clk force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_clk_pull_up" pos="9" rst="0">
          <comment>sim_1_clk PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_clk_pull_dn" pos="8" rst="0">
          <comment>sim_1_clk PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_clk_sel" pos="3:0" rst="0">
          <comment>sim_1_clk select</comment>
          <options>
            <option name="fun_sim_1_clk_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sim_1_dio_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sim_1_dio_oen_frc" pos="28" rst="0">
          <comment>sim_1_dio force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_dio_out_frc" pos="24" rst="0">
          <comment>sim_1_dio force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_dio_out_reg" pos="20" rst="0">
          <comment>sim_1_dio pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_dio_oen_reg" pos="17" rst="0">
          <comment>sim_1_dio force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_dio_pull_frc" pos="16" rst="0">
          <comment>sim_1_dio force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_dio_pull_up" pos="9" rst="0">
          <comment>sim_1_dio PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_dio_pull_dn" pos="8" rst="0">
          <comment>sim_1_dio PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_dio_sel" pos="3:0" rst="0">
          <comment>sim_1_dio select</comment>
          <options>
            <option name="fun_sim_1_dio_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sim_1_rst_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sim_1_rst_oen_frc" pos="28" rst="0">
          <comment>sim_1_rst force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_rst_out_frc" pos="24" rst="0">
          <comment>sim_1_rst force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_rst_out_reg" pos="20" rst="0">
          <comment>sim_1_rst pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_rst_oen_reg" pos="17" rst="0">
          <comment>sim_1_rst force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_rst_pull_frc" pos="16" rst="0">
          <comment>sim_1_rst force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_rst_pull_up" pos="9" rst="0">
          <comment>sim_1_rst PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_rst_pull_dn" pos="8" rst="0">
          <comment>sim_1_rst PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sim_1_rst_sel" pos="3:0" rst="0">
          <comment>sim_1_rst select</comment>
          <options>
            <option name="fun_sim_1_rst_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sim_2_clk_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sim_2_clk_oen_frc" pos="28" rst="0">
          <comment>sim_2_clk force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_clk_out_frc" pos="24" rst="0">
          <comment>sim_2_clk force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_clk_out_reg" pos="20" rst="0">
          <comment>sim_2_clk pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_clk_oen_reg" pos="17" rst="0">
          <comment>sim_2_clk force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_clk_pull_frc" pos="16" rst="0">
          <comment>sim_2_clk force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_clk_pull_up" pos="9" rst="0">
          <comment>sim_2_clk PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_clk_pull_dn" pos="8" rst="0">
          <comment>sim_2_clk PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_clk_sel" pos="3:0" rst="0">
          <comment>sim_2_clk select</comment>
          <options>
            <option name="fun_sim_2_clk_sel" value="0"/>
            <option name="fun_gpo_5_sel" value="1"/>
            <option name="fun_gpio_29_sel" value="2"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sim_2_dio_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sim_2_dio_oen_frc" pos="28" rst="0">
          <comment>sim_2_dio force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_dio_out_frc" pos="24" rst="0">
          <comment>sim_2_dio force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_dio_out_reg" pos="20" rst="0">
          <comment>sim_2_dio pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_dio_oen_reg" pos="17" rst="0">
          <comment>sim_2_dio force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_dio_pull_frc" pos="16" rst="0">
          <comment>sim_2_dio force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_dio_pull_up" pos="9" rst="0">
          <comment>sim_2_dio PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_dio_pull_dn" pos="8" rst="0">
          <comment>sim_2_dio PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_dio_sel" pos="3:0" rst="0">
          <comment>sim_2_dio select</comment>
          <options>
            <option name="fun_sim_2_dio_sel" value="0"/>
            <option name="fun_gpo_6_sel" value="1"/>
            <option name="fun_gpio_30_sel" value="2"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_sim_2_rst_cfg_reg" protect="rw">
        <bits access="rw" name="pad_sim_2_rst_oen_frc" pos="28" rst="0">
          <comment>sim_2_rst force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_rst_out_frc" pos="24" rst="0">
          <comment>sim_2_rst force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_rst_out_reg" pos="20" rst="0">
          <comment>sim_2_rst pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_rst_oen_reg" pos="17" rst="0">
          <comment>sim_2_rst force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_rst_pull_frc" pos="16" rst="0">
          <comment>sim_2_rst force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_rst_pull_up" pos="9" rst="0">
          <comment>sim_2_rst PUll up</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_rst_pull_dn" pos="8" rst="0">
          <comment>sim_2_rst PUll down</comment>
        </bits>
        <bits access="rw" name="pad_sim_2_rst_sel" pos="3:0" rst="0">
          <comment>sim_2_rst select</comment>
          <options>
            <option name="fun_sim_2_rst_sel" value="0"/>
            <option name="fun_gpo_7_sel" value="1"/>
            <option name="fun_gpio_31_sel" value="2"/>
            <option name="fun_uart_1_rts_sel" value="3"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_rfdig_gpio_0_cfg_reg" protect="rw">
        <bits access="rw" name="pad_rfdig_gpio_0_oen_frc" pos="28" rst="0">
          <comment>rfdig_gpio_0 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_out_frc" pos="24" rst="0">
          <comment>rfdig_gpio_0 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_out_reg" pos="20" rst="0">
          <comment>rfdig_gpio_0 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_oen_reg" pos="17" rst="0">
          <comment>rfdig_gpio_0 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_pull_frc" pos="16" rst="0">
          <comment>rfdig_gpio_0 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_pull_up" pos="9" rst="0">
          <comment>rfdig_gpio_0 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_pull_dn" pos="8" rst="0">
          <comment>rfdig_gpio_0 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_sel" pos="3:0" rst="0">
          <comment>rfdig_gpio_0 select</comment>
          <options>
            <option name="fun_rfdig_gpio_0_sel" value="0"/>
            <option name="fun_rffe_sclk_sel" value="1"/>
            <option name="fun_lte_gpo_0_sel" value="2"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_rfdig_gpio_1_cfg_reg" protect="rw">
        <bits access="rw" name="pad_rfdig_gpio_1_oen_frc" pos="28" rst="0">
          <comment>rfdig_gpio_1 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_out_frc" pos="24" rst="0">
          <comment>rfdig_gpio_1 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_out_reg" pos="20" rst="0">
          <comment>rfdig_gpio_1 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_oen_reg" pos="17" rst="0">
          <comment>rfdig_gpio_1 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_pull_frc" pos="16" rst="0">
          <comment>rfdig_gpio_1 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_pull_up" pos="9" rst="0">
          <comment>rfdig_gpio_1 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_pull_dn" pos="8" rst="0">
          <comment>rfdig_gpio_1 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_sel" pos="3:0" rst="0">
          <comment>rfdig_gpio_1 select</comment>
          <options>
            <option name="fun_rfdig_gpio_1_sel" value="0"/>
            <option name="fun_rffe_sdata_sel" value="1"/>
            <option name="fun_lte_gpo_1_sel" value="2"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_rfdig_gpio_2_cfg_reg" protect="rw">
        <bits access="rw" name="pad_rfdig_gpio_2_oen_frc" pos="28" rst="0">
          <comment>rfdig_gpio_2 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_out_frc" pos="24" rst="0">
          <comment>rfdig_gpio_2 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_out_reg" pos="20" rst="0">
          <comment>rfdig_gpio_2 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_oen_reg" pos="17" rst="0">
          <comment>rfdig_gpio_2 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_pull_frc" pos="16" rst="0">
          <comment>rfdig_gpio_2 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_pull_up" pos="9" rst="0">
          <comment>rfdig_gpio_2 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_pull_dn" pos="8" rst="0">
          <comment>rfdig_gpio_2 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_sel" pos="3:0" rst="0">
          <comment>rfdig_gpio_2 select</comment>
          <options>
            <option name="fun_rfdig_gpio_2_sel" value="0"/>
            <option name="fun_lte_gpo_2_sel" value="2"/>
            <option name="fun_dfe_rx_enable_s_o_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_rfdig_gpio_3_cfg_reg" protect="rw">
        <bits access="rw" name="pad_rfdig_gpio_3_oen_frc" pos="28" rst="0">
          <comment>rfdig_gpio_3 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_out_frc" pos="24" rst="0">
          <comment>rfdig_gpio_3 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_out_reg" pos="20" rst="0">
          <comment>rfdig_gpio_3 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_oen_reg" pos="17" rst="0">
          <comment>rfdig_gpio_3 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_pull_frc" pos="16" rst="0">
          <comment>rfdig_gpio_3 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_pull_up" pos="9" rst="0">
          <comment>rfdig_gpio_3 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_pull_dn" pos="8" rst="0">
          <comment>rfdig_gpio_3 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_sel" pos="3:0" rst="0">
          <comment>rfdig_gpio_3 select</comment>
          <options>
            <option name="fun_rfdig_gpio_3_sel" value="0"/>
            <option name="fun_lte_gpo_3_sel" value="2"/>
            <option name="fun_digrf_cp_26m_m_o_sel" value="5"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_rfdig_gpio_4_cfg_reg" protect="rw">
        <bits access="rw" name="pad_rfdig_gpio_4_oen_frc" pos="28" rst="0">
          <comment>rfdig_gpio_4 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_out_frc" pos="24" rst="0">
          <comment>rfdig_gpio_4 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_out_reg" pos="20" rst="0">
          <comment>rfdig_gpio_4 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_oen_reg" pos="17" rst="0">
          <comment>rfdig_gpio_4 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_pull_frc" pos="16" rst="0">
          <comment>rfdig_gpio_4 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_pull_up" pos="9" rst="0">
          <comment>rfdig_gpio_4 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_pull_dn" pos="8" rst="0">
          <comment>rfdig_gpio_4 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_sel" pos="3:0" rst="0">
          <comment>rfdig_gpio_4 select</comment>
          <options>
            <option name="fun_rfdig_gpio_4_sel" value="0"/>
            <option name="fun_lte_gpo_4_sel" value="2"/>
            <option name="fun_digrf_tx_en_s_o_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_rfdig_gpio_5_cfg_reg" protect="rw">
        <bits access="rw" name="pad_rfdig_gpio_5_oen_frc" pos="28" rst="0">
          <comment>rfdig_gpio_5 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_5_out_frc" pos="24" rst="0">
          <comment>rfdig_gpio_5 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_5_out_reg" pos="20" rst="0">
          <comment>rfdig_gpio_5 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_5_oen_reg" pos="17" rst="0">
          <comment>rfdig_gpio_5 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_5_pull_frc" pos="16" rst="0">
          <comment>rfdig_gpio_5 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_5_pull_up" pos="9" rst="0">
          <comment>rfdig_gpio_5 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_5_pull_dn" pos="8" rst="0">
          <comment>rfdig_gpio_5 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_5_sel" pos="3:0" rst="0">
          <comment>rfdig_gpio_5 select</comment>
          <options>
            <option name="fun_rfdig_gpio_5_sel" value="0"/>
            <option name="fun_lte_gpo_5_sel" value="2"/>
            <option name="fun_digrf_tx_data_s_o_sel" value="7"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_rfdig_gpio_6_cfg_reg" protect="rw">
        <bits access="rw" name="pad_rfdig_gpio_6_oen_frc" pos="28" rst="0">
          <comment>rfdig_gpio_6 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_out_frc" pos="24" rst="0">
          <comment>rfdig_gpio_6 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_out_reg" pos="20" rst="0">
          <comment>rfdig_gpio_6 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_oen_reg" pos="17" rst="0">
          <comment>rfdig_gpio_6 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_pull_frc" pos="16" rst="0">
          <comment>rfdig_gpio_6 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_pull_up" pos="9" rst="0">
          <comment>rfdig_gpio_6 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_pull_dn" pos="8" rst="0">
          <comment>rfdig_gpio_6 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_sel" pos="3:0" rst="0">
          <comment>rfdig_gpio_6 select</comment>
          <options>
            <option name="fun_rfdig_gpio_6_sel" value="0"/>
            <option name="fun_lte_gpo_7_sel" value="2"/>
            <option name="fun_digrf_rx_en_m_o_sel" value="5"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_rfdig_gpio_7_cfg_reg" protect="rw">
        <bits access="rw" name="pad_rfdig_gpio_7_oen_frc" pos="28" rst="0">
          <comment>rfdig_gpio_7 force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_out_frc" pos="24" rst="0">
          <comment>rfdig_gpio_7 force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_out_reg" pos="20" rst="0">
          <comment>rfdig_gpio_7 pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_oen_reg" pos="17" rst="0">
          <comment>rfdig_gpio_7 force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_pull_frc" pos="16" rst="0">
          <comment>rfdig_gpio_7 force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_pull_up" pos="9" rst="0">
          <comment>rfdig_gpio_7 PUll up</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_pull_dn" pos="8" rst="0">
          <comment>rfdig_gpio_7 PUll down</comment>
        </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_sel" pos="3:0" rst="0">
          <comment>rfdig_gpio_7 select</comment>
          <options>
            <option name="fun_rfdig_gpio_7_sel" value="0"/>
            <option name="fun_lte_gpo_8_sel" value="2"/>
            <option name="fun_digrf_rx_data_m_o_sel" value="5"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_secure_boot_mode_cfg_reg" protect="rw">
        <bits access="rw" name="pad_secure_boot_mode_oen_frc" pos="28" rst="0">
          <comment>secure_boot_mode force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_secure_boot_mode_out_frc" pos="24" rst="0">
          <comment>secure_boot_mode force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_secure_boot_mode_out_reg" pos="20" rst="0">
          <comment>secure_boot_mode pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_secure_boot_mode_oen_reg" pos="17" rst="0">
          <comment>secure_boot_mode force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_secure_boot_mode_pull_frc" pos="16" rst="0">
          <comment>secure_boot_mode force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_secure_boot_mode_pull_up" pos="9" rst="0">
          <comment>secure_boot_mode PUll up</comment>
        </bits>
        <bits access="rw" name="pad_secure_boot_mode_pull_dn" pos="8" rst="0">
          <comment>secure_boot_mode PUll down</comment>
        </bits>
        <bits access="rw" name="pad_secure_boot_mode_sel" pos="3:0" rst="0">
          <comment>secure_boot_mode select</comment>
          <options>
            <option name="fun_secure_boot_mode_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="pad_nand_flash_sel_cfg_reg" protect="rw">
        <bits access="rw" name="pad_nand_flash_sel_oen_frc" pos="28" rst="0">
          <comment>nand_flash_sel force enable for outoen.</comment>
        </bits>
        <bits access="rw" name="pad_nand_flash_sel_out_frc" pos="24" rst="0">
          <comment>nand_flash_sel force output value for output.</comment>
        </bits>
        <bits access="rw" name="pad_nand_flash_sel_out_reg" pos="20" rst="0">
          <comment>nand_flash_sel pin output value.</comment>
        </bits>
        <bits access="rw" name="pad_nand_flash_sel_oen_reg" pos="17" rst="0">
          <comment>nand_flash_sel force outoen value.</comment>
        </bits>
        <bits access="rw" name="pad_nand_flash_sel_pull_frc" pos="16" rst="0">
          <comment>nand_flash_sel force enable for pu/pd</comment>
        </bits>
        <bits access="rw" name="pad_nand_flash_sel_pull_up" pos="9" rst="0">
          <comment>nand_flash_sel PUll up</comment>
        </bits>
        <bits access="rw" name="pad_nand_flash_sel_pull_dn" pos="8" rst="0">
          <comment>nand_flash_sel PUll down</comment>
        </bits>
        <bits access="rw" name="pad_nand_flash_sel_sel" pos="3:0" rst="0">
          <comment>nand_flash_sel select</comment>
          <options>
            <option name="fun_nand_flash_sel_sel" value="0"/>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="spinlock.xml">
    <module category="System" name="SPINLOCK">
      <reg name="chk_id" protect="rw">
        <bits access="rw" name="chk_id_chk_id" pos="31:0" rst="0">
          <comment>configure whether to check the write id and read id is the same when release the token</comment>
        </bits>
      </reg>
      <reg name="recctrl" protect="rw">
        <bits access="rw" name="rec_ctrl" pos="0" rst="0">
          <comment>Record Select Control
0: Record ID
1: Record User bits
the configuration of this register, can be ignored in APB bus matrix</comment>
        </bits>
      </reg>
      <reg name="ttlsts" protect="r">
        <bits access="r" name="lock" pos="31:0" rst="0">
          <comment>total status register, 32 lock status, indicate if each lock is taken
Read LOCK[i]=0x0, lock i is in the Not Taken status
Read LOCK[i]=1, lock i is in the taken status</comment>
        </bits>
      </reg>
      <reg name="swflag0" protect="rw">
        <bits access="rw" name="swflag0_swflag0" pos="31:0" rst="0">
          <comment>spinlock software flag register0
this register is used to record message by software</comment>
        </bits>
      </reg>
      <reg name="swflag1" protect="rw">
        <bits access="rw" name="swflag1_swflag1" pos="31:0" rst="0">
          <comment>spinlock software flag register1
this register is used to record message by software</comment>
        </bits>
      </reg>
      <reg name="swflag2" protect="rw">
        <bits access="rw" name="swflag2_swflag2" pos="31:0" rst="0">
          <comment>spinlock software flag register2
this register is used to record message by software</comment>
        </bits>
      </reg>
      <reg name="swflag3" protect="rw">
        <bits access="rw" name="swflag3_swflag3" pos="31:0" rst="0">
          <comment>spinlock software flag register3
this register is used to record message by software</comment>
        </bits>
      </reg>
      <hole size="800"/>
      <reg name="mstid0" protect="r">
        <bits access="r" name="mstid0_mstid0" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid1" protect="r">
        <bits access="r" name="mstid1_mstid1" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid2" protect="r">
        <bits access="r" name="mstid2_mstid2" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid3" protect="r">
        <bits access="r" name="mstid3_mstid3" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid4" protect="r">
        <bits access="r" name="mstid4_mstid4" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid5" protect="r">
        <bits access="r" name="mstid5_mstid5" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid6" protect="r">
        <bits access="r" name="mstid6_mstid6" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid7" protect="r">
        <bits access="r" name="mstid7_mstid7" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid8" protect="r">
        <bits access="r" name="mstid8_mstid8" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid9" protect="r">
        <bits access="r" name="mstid9_mstid9" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid10" protect="r">
        <bits access="r" name="mstid10_mstid10" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid11" protect="r">
        <bits access="r" name="mstid11_mstid11" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid12" protect="r">
        <bits access="r" name="mstid12_mstid12" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid13" protect="r">
        <bits access="r" name="mstid13_mstid13" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid14" protect="r">
        <bits access="r" name="mstid14_mstid14" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid15" protect="r">
        <bits access="r" name="mstid15_mstid15" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid16" protect="r">
        <bits access="r" name="mstid16_mstid16" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid17" protect="r">
        <bits access="r" name="mstid17_mstid17" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid18" protect="r">
        <bits access="r" name="mstid18_mstid18" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid19" protect="r">
        <bits access="r" name="mstid19_mstid19" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid20" protect="r">
        <bits access="r" name="mstid20_mstid20" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid21" protect="r">
        <bits access="r" name="mstid21_mstid21" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid22" protect="r">
        <bits access="r" name="mstid22_mstid22" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid23" protect="r">
        <bits access="r" name="mstid23_mstid23" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid24" protect="r">
        <bits access="r" name="mstid24_mstid24" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid25" protect="r">
        <bits access="r" name="mstid25_mstid25" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid26" protect="r">
        <bits access="r" name="mstid26_mstid26" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid27" protect="r">
        <bits access="r" name="mstid27_mstid27" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid28" protect="r">
        <bits access="r" name="mstid28_mstid28" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid29" protect="r">
        <bits access="r" name="mstid29_mstid29" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid30" protect="r">
        <bits access="r" name="mstid30_mstid30" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <reg name="mstid31" protect="r">
        <bits access="r" name="mstid31_mstid31" pos="31:0" rst="0">
          <comment>the master id is stored in this register. The value of this reg in APB bus is 0x0</comment>
        </bits>
      </reg>
      <hole size="14336"/>
      <reg name="locksts0" protect="">
        <bits access="r" name="locksts0_locksts0" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts1" protect="">
        <bits access="r" name="locksts1_locksts1" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts2" protect="">
        <bits access="r" name="locksts2_locksts2" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts3" protect="">
        <bits access="r" name="locksts3_locksts3" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts4" protect="">
        <bits access="r" name="locksts4_locksts4" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts5" protect="">
        <bits access="r" name="locksts5_locksts5" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts6" protect="">
        <bits access="r" name="locksts6_locksts6" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts7" protect="">
        <bits access="r" name="locksts7_locksts7" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts8" protect="">
        <bits access="r" name="locksts8_locksts8" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts9" protect="">
        <bits access="r" name="locksts9_locksts9" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts10" protect="">
        <bits access="r" name="locksts10_locksts10" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts11" protect="">
        <bits access="r" name="locksts11_locksts11" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts12" protect="">
        <bits access="r" name="locksts12_locksts12" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts13" protect="">
        <bits access="r" name="locksts13_locksts13" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts14" protect="">
        <bits access="r" name="locksts14_locksts14" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts15" protect="">
        <bits access="r" name="locksts15_locksts15" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts16" protect="">
        <bits access="r" name="locksts16_locksts16" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts17" protect="">
        <bits access="r" name="locksts17_locksts17" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts18" protect="">
        <bits access="r" name="locksts18_locksts18" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts19" protect="">
        <bits access="r" name="locksts19_locksts19" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts20" protect="">
        <bits access="r" name="locksts20_locksts20" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts21" protect="">
        <bits access="r" name="locksts21_locksts21" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts22" protect="">
        <bits access="r" name="locksts22_locksts22" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts23" protect="">
        <bits access="r" name="locksts23_locksts23" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts24" protect="">
        <bits access="r" name="locksts24_locksts24" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts25" protect="">
        <bits access="r" name="locksts25_locksts25" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts26" protect="">
        <bits access="r" name="locksts26_locksts26" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts27" protect="">
        <bits access="r" name="locksts27_locksts27" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts28" protect="">
        <bits access="r" name="locksts28_locksts28" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts29" protect="">
        <bits access="r" name="locksts29_locksts29" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts30" protect="">
        <bits access="r" name="locksts30_locksts30" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <reg name="locksts31" protect="">
        <bits access="r" name="locksts31_locksts31" pos="0" rst="0">
          <comment>read 0x0, request and get the lock
read 0x1, reqeust but does not get the lock
write unlock token (0x55aa10c5), to unlock the lock
write any other, no effect</comment>
        </bits>
      </reg>
      <hole size="15328"/>
      <reg name="verid" protect="r">
        <bits access="r" name="verid_verid" pos="31:0" rst="257">
          <comment>hw version id</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="efuse_ctrl.xml">
    <module category="Periph" name="EFUSE_CTRL">
      <hole size="64"/>
      <reg name="efuse_all0_index" protect="rw">
        <bits access="rw" name="efuse_all0_start_index" pos="31:16" rst="0">
          <comment>All 0 check start index</comment>
        </bits>
        <bits access="rw" name="efuse_all0_end_index" pos="15:0" rst="31">
          <comment>All 0 check end index</comment>
        </bits>
      </reg>
      <reg name="efuse_mode_ctrl" protect="rw">
        <bits access="rw" name="efuse_all0_check_start" pos="0" rst="0">
          <comment>write 1 to this bit will trigger all0 check to efuse, this bit is self-clear
,read this bit will always get 0.(use PREADY)</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="efuse_ip_ver_reg" protect="r">
        <bits access="r" name="efuse_type" pos="17:16" rst="0">
          <comment>Efuse type: 00 TSMC</comment>
        </bits>
        <bits access="r" name="efuse_ip_ver" pos="15:0" rst="256">
          <comment>IP version, now is r1p0</comment>
        </bits>
      </reg>
      <reg name="efuse_cfg0" protect="rw">
        <bits access="rw" name="clk_efs_div" pos="31:24" rst="0">
          <comment>Clk_efs divider, if this value is n, the frequency of controller will be divided by (n+1) from clk_efs.
In most case, this field not need to change.</comment>
        </bits>
        <bits access="rw" name="efuse_strobe_low_width" pos="23:16" rst="28">
          <comment>This counter is used to control STROBE signal low level width in PGM mode, for TSMC efuse memory, no extra requirement for this signal, For 26Mhz efuse controller clock, by default, this width will be: 38.4*28=1075ns &gt; 1us.
If you want to speed up program speed, can configure the register to a smaller value.</comment>
        </bits>
        <bits access="rw" name="tpgm_time_cnt" pos="8:0" rst="320">
          <comment>Program strobe high time. If set n, the Tpgm time will last for (n+1) clk_efuse cycle, only when PGM_EN=1 can write this field.</comment>
        </bits>
      </reg>
      <hole size="288"/>
      <reg name="efuse_sec_en" protect="rw">
        <bits access="rw" name="sec_lock_bit_wr_en" pos="4" rst="0">
          <comment>If set the bit, lock bits will be written after PGM process.</comment>
        </bits>
        <bits access="rw" name="sec_margin_rd_enable" pos="3" rst="0">
          <comment>efuse margin read mode enable</comment>
        </bits>
        <bits access="rw" name="double_bit_en_sec" pos="2" rst="0">
          <comment>efuse double bit enable</comment>
        </bits>
        <bits access="rw" name="sec_auto_check_enable" pos="1" rst="0">
          <comment>program read back auto-check enable</comment>
        </bits>
        <bits access="rw" name="sec_vdd_en" pos="0" rst="0">
          <comment>efuse vdd enable</comment>
        </bits>
      </reg>
      <reg name="efuse_sec_err_flag" protect="r">
        <bits access="r" name="sec_all0_check_flag" pos="13" rst="0">
          <comment>the bit indicates all 0 check fail.</comment>
        </bits>
        <bits access="r" name="sec_enk_err_flag" pos="12" rst="0">
          <comment>the bit enk1 and enk2 is not switch correctly.</comment>
        </bits>
        <bits access="r" name="sec_magnum_wr_flag" pos="11" rst="0">
          <comment>the bit indicates write process without setting magic number.</comment>
        </bits>
        <bits access="r" name="sec_block0_rd_flag" pos="10" rst="0">
          <comment>the bit indicates arbiter read block0 which may indicates unexpected access.</comment>
        </bits>
        <bits access="r" name="sec_vdd_on_rd_flag" pos="9" rst="0">
          <comment>the bit indicates read process without setting vdd_on to 1.</comment>
        </bits>
        <bits access="r" name="sec_pg_en_wr_flag" pos="8" rst="0">
          <comment>the bit indicates write process without setting pg_en to 1.</comment>
        </bits>
        <bits access="r" name="sec_word1_prot_flag" pos="5" rst="0">
          <comment>The bit indicates shadow block is protected and can not be programmed if double_bit_en is set.
If SW send a PGM command to memory block[i], and the controller found this memory block is protected(which means the highest bit is 1), this bit will set to 1.</comment>
        </bits>
        <bits access="r" name="sec_word0_prot_flag" pos="4" rst="0">
          <comment>The bit indicates block auto check failed after programming. If PGM_AUTO_CHK_EN is set, and controller compared the value read after PGM from the same block, and found the two value not match, this bit will set as an error flag. But if this block is protected, the PGM command in-fact not really send, so this bit will not set.</comment>
        </bits>
        <bits access="r" name="shadow_block_auto_check_failed" pos="1" rst="0">
          <comment>The bit indicates shadow block  auto check failed after programming if double_bit_en is set.
If PGM_AUTO_CHK_EN is set, and controller compared the value read after PGM from the same block, and found the two value not match, this bit will set as an error flag. But if this block is protected, the PGM command in-fact not really send, so this bit will not set.</comment>
        </bits>
        <bits access="r" name="block_auto_check_failed" pos="0" rst="0">
          <comment>The bit indicates block auto check failed after programming. If PGM_AUTO_CHK_EN is set, and controller compared the value read after PGM from the same block, and found the two value not match, this bit will set as an error flag. But if this block is protected, the PGM command in-fact not really send, so this bit will not set.</comment>
        </bits>
      </reg>
      <reg name="efuse_sec_flag_clr" protect="rw">
        <bits access="rw" name="sec_all0_check_clr" pos="13" rst="0">
          <comment>write 1 will clear SEC_ALL0_CHECK_FLAG</comment>
        </bits>
        <bits access="rw" name="sec_enk_err_clr" pos="12" rst="0">
          <comment>write 1 will clear SEC_ENK_ERR_FLAG</comment>
        </bits>
        <bits access="rw" name="sec_magnum_wr_clr" pos="11" rst="0">
          <comment>write 1 will clear SEC_MAGNUM_WR_FLAG</comment>
        </bits>
        <bits access="rw" name="sec_block0_rd_clr" pos="10" rst="0">
          <comment>write 1 will clear SEC_BLOCK0_RD_FLAG</comment>
        </bits>
        <bits access="rw" name="sec_vdd_on_rd_clr" pos="9" rst="0">
          <comment>write 1 will clear SEC_VDD_ON_RD_FLAG</comment>
        </bits>
        <bits access="rw" name="sec_pg_en_wr_clr" pos="8" rst="0">
          <comment>write 1 will clear SEC_PG_EN_WR_FLAG</comment>
        </bits>
        <bits access="rw" name="sec_word1_prot_clr" pos="5" rst="0">
          <comment>write 1 will clear SEC_WORD1_PROT_FLAG. Write 0 will do nothing.</comment>
        </bits>
        <bits access="rw" name="sec_word0_prot_clr" pos="4" rst="0">
          <comment>write 1 will clear SEC_WORD0_PROT_FLAG. Write 0 will do nothing.</comment>
        </bits>
        <bits access="rw" name="sec_word1_err_clr" pos="1" rst="0">
          <comment>write 1 will clear SEC_WORD1_ERR_FLAG. Write 0 will do nothing.</comment>
        </bits>
        <bits access="rw" name="sec_word0_err_clr" pos="0" rst="0">
          <comment>write 1 will clear SEC_WORD0_ERR_FLAG. Write 0 will do nothing.</comment>
        </bits>
      </reg>
      <reg name="efuse_sec_magic_number" protect="rw">
        <bits access="rw" name="sec_efuse_magic_number" pos="15:0" rst="0">
          <comment>Magic number, only when this field is 0x8910, the efuse programming command can be handle.
Set the magic number right will lock the power switch and PGM enable.
So if SW want to program efuse memory, except open clocks and power, 2 other conditions must be met :
(1) SEC_EFUSE_MAGIC_NUMBER =0x8910
(2) PG_EN=1;
(3) Switch the power right;</comment>
        </bits>
      </reg>
      <reg name="efuse_fw_cfg" protect="rw">
        <bits access="rw" name="access_prot" pos="1" rst="0">
          <comment>0: SEC access; 1: NON SEC address enable switch</comment>
        </bits>
        <bits access="rw" name="conf_prot" pos="0" rst="0">
          <comment>SEC/NON-SEC address configure.
1: indicates SEC can access EFUSE_CFG0;
0: indicates NON-SEC can access EFUSE_CFG0;</comment>
        </bits>
      </reg>
      <reg name="efuse_pw_swt" protect="rw">
        <bits access="rw" name="ns_s_pg_en" pos="2" rst="0">
          <comment>set this bit will open static power supply for efuse memory, before any operation towards to efuse memory this bit have to set to 1. once this bit is cleared, the efuse will go to power down mose.</comment>
        </bits>
        <bits access="rw" name="efs_enk2_on" pos="1" rst="1">
          <comment>VDDQ power switch K2, to safely control this power switch.</comment>
        </bits>
        <bits access="rw" name="efs_enk1_on" pos="0" rst="0">
          <comment>VDDQ power switch K2, to safely control this power switch.</comment>
        </bits>
      </reg>
      <reg name="ap_ca5_dbgen_reg" protect="rw">
        <bits access="rw" name="ap_ca5_dbgen" pos="0" rst="0">
          <comment>AP cortex-a5 dbgen, write once register,Invasive debug enable:
0 = not enabled
1 = enabled.</comment>
        </bits>
      </reg>
      <reg name="ap_ca5_niden_reg" protect="rw">
        <bits access="rw" name="ap_ca5_niden" pos="0" rst="0">
          <comment>AP cortex-a5 niden, write once register,Noninvasive debug enable:
0 = not enabled
1 = enabled.</comment>
        </bits>
      </reg>
      <reg name="ap_ca5_spien_reg" protect="rw">
        <bits access="rw" name="ap_ca5_spien" pos="0" rst="0">
          <comment>AP cortex-a5 spien, write once register,Secure privileged invasive debug enable:
0 = not enabled
1 = enabled.</comment>
        </bits>
      </reg>
      <reg name="ap_ca5_spnien_reg" protect="rw">
        <bits access="rw" name="ap_ca5_spnien" pos="0" rst="0">
          <comment>AP cortex-a5 spnien, write once register,Secure privileged noninvasive debug enable:
0 = not enabled
1 = enabled.</comment>
        </bits>
      </reg>
      <reg name="ap_ca5_dap_deviceen_reg" protect="rw">
        <bits access="rw" name="ap_ca5_dap_deviceen" pos="0" rst="0">
          <comment>AP cortex-a5 dap deviceen, write once register,device enable</comment>
        </bits>
      </reg>
      <reg name="riscv_jtag_disable_reg" protect="rw">
        <bits access="rw" name="riscv_jtag_disable" pos="0" rst="1">
          <comment>RISCV JTAG disable, write once register</comment>
        </bits>
      </reg>
      <reg name="zsp_jtag_disable_reg" protect="rw">
        <bits access="rw" name="zsp_jtag_disable" pos="0" rst="1">
          <comment>ZSP JTAG disable, write once register</comment>
        </bits>
      </reg>
      <reg name="debug_host_rx_disable_reg" protect="rw">
        <bits access="rw" name="debug_host_rx_disable" pos="0" rst="1">
          <comment>debug host rx disable, write once register</comment>
        </bits>
      </reg>
      <reg name="uart_1_rx_disable_reg" protect="rw">
        <bits access="rw" name="uart_1_rx_disable" pos="0" rst="1">
          <comment>uart1 rx disable, write once register</comment>
        </bits>
      </reg>
      <reg name="uart_2_rx_disable_reg" protect="rw">
        <bits access="rw" name="uart_2_rx_disable" pos="0" rst="1">
          <comment>uart2 rx disable, write once register</comment>
        </bits>
      </reg>
      <reg name="uart_3_rx_disable_reg" protect="rw">
        <bits access="rw" name="uart_3_rx_disable" pos="0" rst="1">
          <comment>uart3 rx disable, write once register</comment>
        </bits>
      </reg>
      <reg name="uart_cp_rx_disable_reg" protect="rw">
        <bits access="rw" name="uart_cp_rx_disable" pos="0" rst="1">
          <comment>uart cp rx disable, write once register</comment>
        </bits>
      </reg>
      <reg name="mbist_disable_reg" protect="rw">
        <bits access="rw" name="mbist_disable" pos="0" rst="1">
          <comment>mbist disable, write once register</comment>
        </bits>
      </reg>
      <reg name="scan_disable_reg" protect="rw">
        <bits access="rw" name="scan_disable" pos="0" rst="1">
          <comment>scan disable, write once register</comment>
        </bits>
      </reg>
      <reg name="efuse_bist_en_reg" protect="rw">
        <bits access="rw" name="efuse_bist_en" pos="0" rst="0">
          <comment>efuse bist enable, write once register</comment>
        </bits>
      </reg>
      <reg name="cp_ca5_dbgen_reg" protect="rw">
        <bits access="rw" name="cp_ca5_dbgen" pos="0" rst="0">
          <comment>CP cortex-a5 dbgen, write once register,Invasive debug enable:
0 = not enabled
1 = enabled.</comment>
        </bits>
      </reg>
      <reg name="cp_ca5_niden_reg" protect="rw">
        <bits access="rw" name="cp_ca5_niden" pos="0" rst="0">
          <comment>CP cortex-a5 niden, write once register,Noninvasive debug enable:
0 = not enabled
1 = enabled.</comment>
        </bits>
      </reg>
      <reg name="cp_ca5_spien_reg" protect="rw">
        <bits access="rw" name="cp_ca5_spien" pos="0" rst="0">
          <comment>CP cortex-a5 spien, write once register,Secure privileged invasive debug enable:
0 = not enabled
1 = enabled.</comment>
        </bits>
      </reg>
      <reg name="cp_ca5_spnien_reg" protect="rw">
        <bits access="rw" name="cp_ca5_spnien" pos="0" rst="0">
          <comment>CP cortex-a5 spnien, write once register,Secure privileged noninvasive debug enable:
0 = not enabled
1 = enabled.</comment>
        </bits>
      </reg>
      <reg name="cp_ca5_dcp_deviceen_reg" protect="rw">
        <bits access="rw" name="cp_ca5_dcp_deviceen" pos="0" rst="0">
          <comment>CP cortex-a5 dcp deviceen, write once register,device enable</comment>
        </bits>
      </reg>
      <reg name="efuse_block0_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block0_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block0 read/write, write once register:
0 = not enable read/write efuse block0
1 = enable read/write efuse block0</comment>
        </bits>
      </reg>
      <reg name="efuse_block1_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block1_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block1 read/write, write once register:
0 = not enable read/write efuse block1
1 = enable read/write efuse block1</comment>
        </bits>
      </reg>
      <reg name="efuse_block2_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block2_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block2 read/write, write once register:
0 = not enable read/write efuse block2
1 = enable read/write efuse block2</comment>
        </bits>
      </reg>
      <reg name="efuse_block3_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block3_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block3 read/write, write once register:
0 = not enable read/write efuse block3
1 = enable read/write efuse block3</comment>
        </bits>
      </reg>
      <reg name="efuse_block4_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block4_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block4 read/write, write once register:
0 = not enable read/write efuse block4
1 = enable read/write efuse block4</comment>
        </bits>
      </reg>
      <reg name="efuse_block5_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block5_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block5 read/write, write once register:
0 = not enable read/write efuse block5
1 = enable read/write efuse block5</comment>
        </bits>
      </reg>
      <reg name="efuse_block6_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block6_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block6 read/write, write once register:
0 = not enable read/write efuse block6
1 = enable read/write efuse block6</comment>
        </bits>
      </reg>
      <reg name="efuse_block7_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block7_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block7 read/write, write once register:
0 = not enable read/write efuse block7
1 = enable read/write efuse block7</comment>
        </bits>
      </reg>
      <reg name="efuse_block8_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block8_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block8 read/write, write once register:
0 = not enable read/write efuse block8
1 = enable read/write efuse block8</comment>
        </bits>
      </reg>
      <reg name="efuse_block9_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block9_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block9 read/write, write once register:
0 = not enable read/write efuse block9
1 = enable read/write efuse block9</comment>
        </bits>
      </reg>
      <reg name="efuse_block10_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block10_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block10 read/write, write once register:
0 = not enable read/write efuse block10
1 = enable read/write efuse block10</comment>
        </bits>
      </reg>
      <reg name="efuse_block11_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block11_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block11 read/write, write once register:
0 = not enable read/write efuse block11
1 = enable read/write efuse block11</comment>
        </bits>
      </reg>
      <reg name="efuse_block12_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block12_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block12 read/write, write once register:
0 = not enable read/write efuse block12
1 = enable read/write efuse block12</comment>
        </bits>
      </reg>
      <reg name="efuse_block13_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block13_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block13 read/write, write once register:
0 = not enable read/write efuse block13
1 = enable read/write efuse block13</comment>
        </bits>
      </reg>
      <reg name="efuse_block14_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block14_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block14 read/write, write once register:
0 = not enable read/write efuse block14
1 = enable read/write efuse block14</comment>
        </bits>
      </reg>
      <reg name="efuse_block15_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block15_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block15 read/write, write once register:
0 = not enable read/write efuse block15
1 = enable read/write efuse block15</comment>
        </bits>
      </reg>
      <reg name="efuse_block16_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block16_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block16 read/write, write once register:
0 = not enable read/write efuse block16
1 = enable read/write efuse block16</comment>
        </bits>
      </reg>
      <reg name="efuse_block17_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block17_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block17 read/write, write once register:
0 = not enable read/write efuse block17
1 = enable read/write efuse block17</comment>
        </bits>
      </reg>
      <reg name="efuse_block18_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block18_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block18 read/write, write once register:
0 = not enable read/write efuse block18
1 = enable read/write efuse block18</comment>
        </bits>
      </reg>
      <reg name="efuse_block19_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block19_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block19 read/write, write once register:
0 = not enable read/write efuse block19
1 = enable read/write efuse block19</comment>
        </bits>
      </reg>
      <reg name="efuse_block20_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block20_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block20 read/write, write once register:
0 = not enable read/write efuse block20
1 = enable read/write efuse block20</comment>
        </bits>
      </reg>
      <reg name="efuse_block21_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block21_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block21 read/write, write once register:
0 = not enable read/write efuse block21
1 = enable read/write efuse block21</comment>
        </bits>
      </reg>
      <reg name="efuse_block22_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block22_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block22 read/write, write once register:
0 = not enable read/write efuse block22
1 = enable read/write efuse block22</comment>
        </bits>
      </reg>
      <reg name="efuse_block23_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block23_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block23 read/write, write once register:
0 = not enable read/write efuse block23
1 = enable read/write efuse block23</comment>
        </bits>
      </reg>
      <reg name="efuse_block24_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block24_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block24 read/write, write once register:
0 = not enable read/write efuse block24
1 = enable read/write efuse block24</comment>
        </bits>
      </reg>
      <reg name="efuse_block25_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block25_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block25 read/write, write once register:
0 = not enable read/write efuse block25
1 = enable read/write efuse block25</comment>
        </bits>
      </reg>
      <reg name="efuse_block26_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block26_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block26 read/write, write once register:
0 = not enable read/write efuse block26
1 = enable read/write efuse block26</comment>
        </bits>
      </reg>
      <reg name="efuse_block27_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block27_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block27 read/write, write once register:
0 = not enable read/write efuse block27
1 = enable read/write efuse block27</comment>
        </bits>
      </reg>
      <reg name="efuse_block28_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block28_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block28 read/write, write once register:
0 = not enable read/write efuse block28
1 = enable read/write efuse block28</comment>
        </bits>
      </reg>
      <reg name="efuse_block29_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block29_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block29 read/write, write once register:
0 = not enable read/write efuse block29
1 = enable read/write efuse block29</comment>
        </bits>
      </reg>
      <reg name="efuse_block30_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block30_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block30 read/write, write once register:
0 = not enable read/write efuse block30
1 = enable read/write efuse block30</comment>
        </bits>
      </reg>
      <reg name="efuse_block31_rw_ctrl_reg" protect="rw">
        <bits access="rw" name="efuse_block31_rw_ctrl" pos="0" rst="1">
          <comment>control efuse block31 read/write, write once register:
0 = not enable read/write efuse block31
1 = enable read/write efuse block31</comment>
        </bits>
      </reg>
      <reg name="por_read_done_reg" protect="r">
        <bits access="r" name="por_read_done" pos="0" rst="0">
          <comment>read config bits done status from efuse macro after por, then this bit is set to 1.</comment>
        </bits>
      </reg>
      <reg name="efuse_cfg_reg" protect="r">
        <bits access="r" name="ap_ca5_dbgen_status" pos="19" rst="0">
          <comment>ap_ca5_dbgen status</comment>
        </bits>
        <bits access="r" name="ap_ca5_niden_status" pos="18" rst="0">
          <comment>ap_ca5_niden status</comment>
        </bits>
        <bits access="r" name="ap_ca5_spiden_status" pos="17" rst="0">
          <comment>ap_ca5_spiden status</comment>
        </bits>
        <bits access="r" name="ap_ca5_spniden_status" pos="16" rst="0">
          <comment>ap_ca5_spniden status</comment>
        </bits>
        <bits access="r" name="ap_ca5_dap_deviceen_status" pos="15" rst="0">
          <comment>ap_ca5_dap_deviceen status</comment>
        </bits>
        <bits access="r" name="riscv_jtag_disable_status" pos="14" rst="1">
          <comment>riscv_jtag_disable status</comment>
        </bits>
        <bits access="r" name="zsp_jtag_disable_status" pos="13" rst="1">
          <comment>zsp_jtag_disable status</comment>
        </bits>
        <bits access="r" name="debug_host_rx_disable_status" pos="12" rst="1">
          <comment>debug_host_rx_disable status</comment>
        </bits>
        <bits access="r" name="uart_1_rx_disable_status" pos="11" rst="1">
          <comment>uart_1_rx_disable status</comment>
        </bits>
        <bits access="r" name="uart_2_rx_disable_status" pos="10" rst="1">
          <comment>uart_2_rx_disable status</comment>
        </bits>
        <bits access="r" name="uart_3_rx_disable_status" pos="9" rst="1">
          <comment>uart_3_rx_disable status</comment>
        </bits>
        <bits access="r" name="uart_cp_rx_disable_status" pos="8" rst="1">
          <comment>uart_cp_rx_disable status</comment>
        </bits>
        <bits access="r" name="mbist_disable_status" pos="7" rst="1">
          <comment>mbist_disable status</comment>
        </bits>
        <bits access="r" name="scan_disable_status" pos="6" rst="1">
          <comment>scan_disable status</comment>
        </bits>
        <bits access="r" name="efuse_bist_en_status" pos="5" rst="0">
          <comment>efuse_bist_en status</comment>
        </bits>
        <bits access="r" name="cp_ca5_dbgen_status" pos="4" rst="0">
          <comment>cp_ca5_dbgen status</comment>
        </bits>
        <bits access="r" name="cp_ca5_niden_status" pos="3" rst="0">
          <comment>cp_ca5_niden status</comment>
        </bits>
        <bits access="r" name="cp_ca5_spiden_status" pos="2" rst="0">
          <comment>cp_ca5_spiden status</comment>
        </bits>
        <bits access="r" name="cp_ca5_spniden_status" pos="1" rst="0">
          <comment>cp_ca5_spniden status</comment>
        </bits>
        <bits access="r" name="cp_ca5_dap_deviceen_status" pos="0" rst="0">
          <comment>cp_ca5_dap_deviceen status</comment>
        </bits>
      </reg>
      <reg name="efuse_block_en_reg" protect="r">
        <bits access="r" name="efuse_block_en" pos="31:0" rst="4294967295">
          <comment>every block(31~0) read/write enable status</comment>
        </bits>
      </reg>
      <reg name="por_read_data0_reg" protect="r">
        <bits access="r" name="por_read_data0" pos="31:0" rst="0">
          <comment>read block22_23 config bit</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="wcn_jtag_disable_reg" protect="rw">
        <bits access="rw" name="wcn_jtag_disable" pos="0" rst="1">
          <comment>wcn_jtag_disable, write once register</comment>
        </bits>
      </reg>
      <reg name="wcn_uart_disable_reg" protect="rw">
        <bits access="rw" name="wcn_uart_disable" pos="0" rst="1">
          <comment>wcn_uart_disable, write once register</comment>
        </bits>
      </reg>
      <reg name="rf_uart_disable_reg" protect="rw">
        <bits access="rw" name="rf_uart_disable" pos="0" rst="1">
          <comment>rf_uart_disable, write once register</comment>
        </bits>
      </reg>
      <hole size="13728"/>
      <reg name="efuse_mem" protect="--">
        <bits access="rw" name="efuse_data" pos="31:0" rst="0">
          <comment>the registers are the mapping address to efuse macro. Write the 12'hxxx address means burn the data into block (12'hxxx&lt;&lt;2) of efuse. Read the 12'hxxx address will get the block (12'hxxx&lt;&lt;2) data of efuse.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="ap_ifc.xml">
    <include file="globals.xml"/>
    <include file="gallite_generic_config.xml"/>
    <var name="AP_IFC_ADDR_ALIGN" value="0"/>
    <var name="AP_IFC_TC_LEN" value="23"/>
    <var name="AP_IFC_STD_CHAN_NB" value="AP_IFC_NB_STD_CHANNEL"/>
    <var name="AP_IFC_RFSPI_CHAN" value="0"/>
    <module category="System" name="AP_IFC">
      <reg name="get_ch" protect="">
        <bits access="r" name="ch_to_use" pos="3:0" rst="0">
          <comment>
            This field indicates which standard channel to use.
            <br/>
             Before using a channel, the CPU read this register to know which channel must be used.
      After reading this registers, the channel is to be regarded as
      busy.
            <br/>
             After reading this register, if the CPU doesn't want to use
      the specified channel, the CPU must write a disable in the control
      register of the channel to release the channel.
            <br/>
            0000 = use Channel0
            <br/>
            0001 = use Channel1
            <br/>
            0010 = use Channel2
            <br/>
             ...
            <br/>
            0111 = use Channel7
            <br/>
            1111 = all channels are busy
          </comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="dma_status" protect="r">
        <bits access="r" name="ch_enable" pos="AP_IFC_STD_CHAN_NB+AP_IFC_RFSPI_CHAN-1:0" rst="0">
          <comment>
            This register indicates which channel is enabled. It is a copy
      of the enable bit of the control register of each channel. One bit per
      channel, for example:
            <br/>
            0000_0000 = All channels disabled
            <br/>
            0000_0001 = Ch0 enabled
            <br/>
            0000_0010 = Ch1 enabled
            <br/>
            0000_0100 = Ch2 enabled
            <br/>
            0000_0101 = Ch0 and Ch2 enabled
            <br/>
            0000_0111 = Ch0, Ch1 and Ch2 enabled
            <br/>
            1111_1111 = all channels enabled
          </comment>
        </bits>
        <bits access="r" name="ch_busy" pos="AP_IFC_STD_CHAN_NB-1+16:16" rst="0">
          <comment>This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel</comment>
        </bits>
      </reg>
      <reg name="debug_status" protect="r">
        <bits access="r" name="dbg_status" pos="0" rst="1">
          <comment>
            Debug Channel Status .
            <br/>
            0= The debug channel is running
      (not idle)
            <br/>
            1= The debug channel is in idle mode
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <struct count="AP_IFC_STD_CHAN_NB" name="std_ch">
        <reg name="control" protect="rw">
          <bits access="w" name="enable" pos="0" rst="no">
            <comment>
              Channel Enable, write one in this bit enable the channel.
              <br/>
              When the channel is enabled, for a peripheral to memory transfer
        the DMA wait request from peripheral to start transfer.
            </comment>
          </bits>
          <bits access="w" name="disable" pos="1" rst="no">
            <comment>
              Channel Disable, write one in this bit disable the channel.
              <br/>
              When writing one in this bit, the current AHB transfer and
        current APB transfer (if one in progress) is completed and the channel
        is then disabled.
            </comment>
          </bits>
          <bits access="rw" name="rd_hw_exch" pos="2" rst="0">
            <comment>
              Read FIFO data exchange high 8-bit and low 8-bit.
              <br/>
              0: Exchange;    [31:0] = {b2,b3,b0,b1}
              <br/>
              1: No exchange; [31:0] = {b3,b2,b1,b0}
            </comment>
          </bits>
          <bits access="rw" name="wr_hw_exch" pos="3" rst="0">
            <comment>
              Write FIFO data exchange high 8-bit and low 8-bit.
              <br/>
              0: Exchange;    [31:0] = {b3,b2,b1,b0}
              <br/>
              1: No exchange; [31:0] = {b2,b3,b0,b1}
            </comment>
          </bits>
          <bits access="rw" name="autodisable" pos="4" rst="1">
            <comment>
              Set Auto-disable mode
              <br/>
               0 = when TC reach zero the
        channel is not automatically released.
              <br/>
               1 = At the end of the
        transfer when TC reach zero the channel is automatically disabled. the
        current channel is released.
            </comment>
          </bits>
          <bits access="rw" name="size" pos="5" rst="0">
            <comment>
              Peripheral Size
              <br/>
               0= 8-bit peripheral
              <br/>
               1= 32-bit peripheral
            </comment>
          </bits>
          <bits access="rw" display="hex" name="req_src" pos="12:8" rst="0x7">
            <options linkenum="Ap_Ifc_Request_IDs">
              <shift/>
              <mask/>
              <default/>
            </options>
            <comment>Select DMA Request source</comment>
          </bits>
          <bits access="rw" name="flush" pos="16" rst="0">
            <comment>
              When one, flush the internal FIFO channel.
              <br/>
              This bit must be used only in case of Rx transfer. Until this bit is 1, the APB
              request is masked. The flush doesn't release the channel.
              <br/>
               Before writting back this bit to zero the internal fifo must empty.
            </comment>
          </bits>
        </reg>
        <reg name="status" protect="r">
          <bits access="r" name="enable" pos="0" rst="0">
            <comment>Enable bit, when '1' the channel is running</comment>
          </bits>
          <bits access="r" name="fifo_empty" pos="4" rst="1">
            <comment>The internal channel fifo is empty</comment>
          </bits>
        </reg>
        <reg name="start_addr" protect="rw">
          <bits access="rw" display="hex" name="start_addr" pos="NB_BITS_ADDR-1:AP_IFC_ADDR_ALIGN" rst="0xFFFFFFF">
            <comment>
              AHB Address. This field represent the start address of the
        transfer.
              <br/>
              For a 32-bit peripheral, this address must be aligned 32-bit.
            </comment>
          </bits>
        </reg>
        <reg name="tc" protect="rw">
          <bits access="rw" display="hex" name="tc" pos="AP_IFC_TC_LEN-1:0" rst="0xFFFFFF">
            <comment>
              Transfer Count, this field indicated the transfer size in bytes to perform.
              <br/>
              During a transfer a write in this register add the new value to the current TC.
              <br/>
              A read of this register return the current current transfer count.
            </comment>
          </bits>
        </reg>
      </struct>
      <reg name="ch_rfspi_control" protect="rw">
        <bits access="s" name="enable" pos="0" rst="no">
          <comment>
            Channel Enable, write one in this bit enable the channel.
            <br/>
            This channel works only in fifo mode.
          </comment>
        </bits>
        <bits access="c" name="disable" pos="1" rst="no">
          <comment>Channel Disable, write one in this bit to disable the channel.</comment>
        </bits>
      </reg>
      <reg name="ch_rfspi_status" protect="r">
        <bits access="r" name="enable" pos="0" rst="0">
          <comment>Enable bit, when '1' the channel is running</comment>
        </bits>
        <bits access="r" name="fifo_empty" pos="4" rst="1">
          <comment>The internal channel fifo is empty</comment>
        </bits>
        <bits access="r" name="fifo_level" pos="12:8" rst="0">
          <comment>Internal fifo level</comment>
        </bits>
      </reg>
      <reg name="ch_rfspi_start_addr" protect="rw">
        <bits access="rw" display="hex" name="start_ahb_addr" pos="NB_BITS_ADDR-1:AP_IFC_ADDR_ALIGN" rst="0xFFFFFFF">
          <comment>
            AHB Start Address.
            <br/>
            This field represent the start address of the fifo.
                 The start address must 32-bit aligned.
          </comment>
        </bits>
      </reg>
      <reg name="ch_rfspi_end_addr" protect="rw">
        <bits access="rw" display="hex" name="end_ahb_addr" pos="NB_BITS_ADDR-1:AP_IFC_ADDR_ALIGN" rst="0xFFFFFFF">
          <comment>
            AHB End Address.
            <br/>
            This field represent the last address of the fifo (it is the first address not used in the fifo).
            <br/>
            The end address must 32-bit aligned.
          </comment>
        </bits>
      </reg>
      <reg name="ch_rfspi_tc" protect="rw">
        <bits access="rw" display="hex" name="tc" pos="13:0" rst="0x0">
          <comment>
            Transfer Count, transfer size in bytes.
            <br/>
            This bit
        indicated the transfer size in bytes to perform. Up to 16kbytes per
        transfer.
            <br/>
            During a transfer a write in this register add the new
        value to the current TC. A read of this register return the current
        current transfer count.
          </comment>
        </bits>
      </reg>
      <hole size="32*(64 - 4 - 4*(AP_IFC_STD_CHAN_NB) -5)"/>
    </module>
    <module category="System" name="AUDIO_IFC">
      <var name="AP_APB1_IFC_AHB_MAXSPACE" value="20"/>
      <var name="AP_APB1_IFC_ADDR_ALIGN" value="2"/>
      <struct count="NB_AIF_IFC_CHANNEL" name="ch">
        <comment>
          The Channel 0 conveys data from the AIF to the memory.
          <br/>
        The Channel 1 conveys data from the memory to the AIF.
          <br/>
          These Channels only exist with Voice Option.
        </comment>
        <reg name="control" protect="rw">
          <bits access="w" name="enable" pos="0" rst="no">
            <comment>
              Channel Enable, write one in this bit enable the channel.
              <br/>
              When the channel is enabled, for a peripheral to memory transfer
        the DMA wait request from peripheral to start transfer.
            </comment>
          </bits>
          <bits access="w" name="disable" pos="1" rst="no">
            <comment>
              Channel Disable, write one in this bit disable the channel.
              <br/>
              When writing one in this bit, the current AHB transfer and
        current APB transfer (if one in progress) is completed and the channel
        is then disabled.
            </comment>
          </bits>
          <bits access="rw" name="auto_disable" pos="4" rst="0">
            <comment>Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt.</comment>
          </bits>
        </reg>
        <reg name="status" protect="r">
          <bits access="r" name="enable" pos="0" rst="0">
            <comment>When 1 the channel is enabled</comment>
          </bits>
          <bits access="r" name="fifo_empty" pos="4" rst="1">
            <comment>When 1 the fifo is empty</comment>
          </bits>
          <bits access="r" name="cause_ief" pos="8" rst="0">
            <comment>Cause interrupt End of FIFO.</comment>
          </bits>
          <bits access="r" name="cause_ihf" pos="9" rst="0">
            <comment>Cause interrupt Half of FIFO.</comment>
          </bits>
          <bits access="r" name="cause_i4f" pos="10" rst="0">
            <comment>Cause interrupt Quarter of FIFO.</comment>
          </bits>
          <bits access="r" name="cause_i3_4f" pos="11" rst="0">
            <comment>Cause interrupt Three Quarter of FIFO.</comment>
          </bits>
          <bits access="r" name="cause_ahb_error" pos="12" rst="0">
            <comment>Cause interrupt ahb error.</comment>
          </bits>
          <bits access="r" name="ief" pos="16" rst="0">
            <comment>End of FIFO interrupt status bit.</comment>
          </bits>
          <bits access="r" name="ihf" pos="17" rst="0">
            <comment>Half of FIFO interrupt status bit.</comment>
          </bits>
          <bits access="r" name="i4f" pos="18" rst="0">
            <comment>Quarter of FIFO interrupt status bit.</comment>
          </bits>
          <bits access="r" name="i3_4f" pos="19" rst="0">
            <comment>Three Quarter of FIFO interrupt status bit.</comment>
          </bits>
          <bits access="r" name="ahb error" pos="20" rst="0">
            <comment>ahb error interrupt status bit.</comment>
          </bits>
          <bits access="r" name="ch_idle" pos="21" rst="0">
            <comment>channel busy status bit.</comment>
          </bits>
        </reg>
        <reg name="start_addr" protect="rw">
          <bits access="rw" display="hex" name="start_addr" pos="AP_NB_BITS_ADDR-1:AP_APB1_IFC_ADDR_ALIGN" rst="0xFFFFFFFF">
            <comment>AHB Start Address. This field represent the start address of the FIFO located in RAM.</comment>
          </bits>
        </reg>
        <reg name="fifo_size" protect="rw">
          <bits access="rw" display="hex" name="fifo_size" pos="19:4" rst="all1">
            <comment>
              Fifo size in bytes, max 1MBytes.
              <br/>
              The size of the fifo must be a multiple of 16 (The four LSB are always zero).
            </comment>
          </bits>
        </reg>
        <hole size="32"/>
        <reg name="int_mask" protect="rw">
          <bits access="rw" name="end_fifo" pos="8" rst="0">
            <comment>END FIFO Mask interrupt. When one this interrupt is enabled.</comment>
          </bits>
          <bits access="rw" name="half_fifo" pos="9" rst="0">
            <comment>HALF FIFO Mask interrupt. When one this interrupt is enabled.</comment>
          </bits>
          <bits access="rw" name="quarter_fifo" pos="10" rst="0">
            <comment>QUARTER FIFO Mask interrupt. When one this interrupt is
        enabled.</comment>
          </bits>
          <bits access="rw" name="three_quarter_fifo" pos="11" rst="0">
            <comment>THREE QUARTER FIFO Mask interrupt. When one this interrupt is
        enabled.</comment>
          </bits>
          <bits access="rw" name="ahb_error" pos="12" rst="0">
            <comment>ahb_error Mask interrupt. When one this interrupt is
        enabled.</comment>
          </bits>
        </reg>
        <reg name="int_clear" protect="rw">
          <bits access="c" name="end_fifo" pos="8" rst="0">
            <comment>Write one to clear end of fifo interrupt.</comment>
          </bits>
          <bits access="c" name="half_fifo" pos="9" rst="0">
            <comment>Write one to clear half of fifo interrupt.</comment>
          </bits>
          <bits access="c" name="quarter_fifo" pos="10" rst="0">
            <comment>Write one to clear Quarter fifo interrupt.</comment>
          </bits>
          <bits access="c" name="three_quarter_fifo" pos="11" rst="0">
            <comment>Write one to clear Three Quarter fifo interrupt.</comment>
          </bits>
          <bits access="c" name="ahb_error" pos="12" rst="0">
            <comment>Write one to clear ahb_error interrupt.</comment>
          </bits>
        </reg>
        <reg name="cur_ahb_addr" protect="r">
          <bits access="r" display="hex" name="cur_ahb_addr" pos="AP_NB_BITS_ADDR-1:0" rst="0">
            <comment>Current AHB address value. The nine MSB bit is constant and
        equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register.</comment>
          </bits>
        </reg>
      </struct>
    </module>
  </archive>
  <archive relative="aon_ifc.xml">
    <include file="globals.xml"/>
    <include file="gallite_generic_config.xml"/>
    <var name="AON_IFC_ADDR_ALIGN" value="0"/>
    <var name="AON_IFC_TC_LEN" value="23"/>
    <var name="AON_IFC_STD_CHAN_NB" value="AON_IFC_NB_STD_CHANNEL"/>
    <var name="AON_IFC_RFSPI_CHAN" value="0"/>
    <module category="System" name="AON_IFC">
      <reg name="get_ch" protect="">
        <bits access="r" name="ch_to_use" pos="3:0" rst="0">
          <comment>
            This field indicates which standard channel to use.
            <br/>
             Before using a channel, the CPU read this register to know which channel must be used.
      After reading this registers, the channel is to be regarded as
      busy.
            <br/>
             After reading this register, if the CPU doesn't want to use
      the specified channel, the CPU must write a disable in the control
      register of the channel to release the channel.
            <br/>
            0000 = use Channel0
            <br/>
            0001 = use Channel1
            <br/>
            0010 = use Channel2
            <br/>
             ...
            <br/>
            0111 = use Channel7
            <br/>
            1111 = all channels are busy
          </comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="dma_status" protect="r">
        <bits access="r" name="ch_enable" pos="AON_IFC_STD_CHAN_NB+AON_IFC_RFSPI_CHAN-1:0" rst="0">
          <comment>
            This register indicates which channel is enabled. It is a copy
      of the enable bit of the control register of each channel. One bit per
      channel, for example:
            <br/>
            0000_0000 = All channels disabled
            <br/>
            0000_0001 = Ch0 enabled
            <br/>
            0000_0010 = Ch1 enabled
            <br/>
            0000_0100 = Ch2 enabled
            <br/>
            0000_0101 = Ch0 and Ch2 enabled
            <br/>
            0000_0111 = Ch0, Ch1 and Ch2 enabled
            <br/>
            1111_1111 = all channels enabled
          </comment>
        </bits>
        <bits access="r" name="ch_busy" pos="AON_IFC_STD_CHAN_NB-1+16:16" rst="0">
          <comment>This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel</comment>
        </bits>
      </reg>
      <reg name="debug_status" protect="r">
        <bits access="r" name="dbg_status" pos="0" rst="1">
          <comment>
            Debug Channel Status .
            <br/>
            0= The debug channel is running
      (not idle)
            <br/>
            1= The debug channel is in idle mode
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <struct count="AON_IFC_STD_CHAN_NB" name="std_ch">
        <reg name="control" protect="rw">
          <bits access="w" name="enable" pos="0" rst="no">
            <comment>
              Channel Enable, write one in this bit enable the channel.
              <br/>
              When the channel is enabled, for a peripheral to memory transfer
        the DMA wait request from peripheral to start transfer.
            </comment>
          </bits>
          <bits access="w" name="disable" pos="1" rst="no">
            <comment>
              Channel Disable, write one in this bit disable the channel.
              <br/>
              When writing one in this bit, the current AHB transfer and
        current APB transfer (if one in progress) is completed and the channel
        is then disabled.
            </comment>
          </bits>
          <bits access="rw" name="rd_hw_exch" pos="2" rst="0">
            <comment>
              Read FIFO data exchange high 8-bit and low 8-bit.
              <br/>
              0: Exchange;    [31:0] = {b2,b3,b0,b1}
              <br/>
              1: No exchange; [31:0] = {b3,b2,b1,b0}
            </comment>
          </bits>
          <bits access="rw" name="wr_hw_exch" pos="3" rst="0">
            <comment>
              Write FIFO data exchange high 8-bit and low 8-bit.
              <br/>
              0: Exchange;    [31:0] = {b3,b2,b1,b0}
              <br/>
              1: No exchange; [31:0] = {b2,b3,b0,b1}
            </comment>
          </bits>
          <bits access="rw" name="autodisable" pos="4" rst="1">
            <comment>
              Set Auto-disable mode
              <br/>
               0 = when TC reach zero the
        channel is not automatically released.
              <br/>
               1 = At the end of the
        transfer when TC reach zero the channel is automatically disabled. the
        current channel is released.
            </comment>
          </bits>
          <bits access="rw" name="size" pos="5" rst="0">
            <comment>
              Peripheral Size
              <br/>
               0= 8-bit peripheral
              <br/>
               1= 32-bit peripheral
            </comment>
          </bits>
          <bits access="rw" display="hex" name="req_src" pos="12:8" rst="0x1f">
            <options linkenum="Aon_Ifc_Request_IDs">
              <shift/>
              <mask/>
              <default/>
            </options>
            <comment>Select DMA Request source</comment>
          </bits>
          <bits access="rw" name="flush" pos="16" rst="0">
            <comment>
              When one, flush the internal FIFO channel.
              <br/>
              This bit must be used only in case of Rx transfer. Until this bit is 1, the APB
              request is masked. The flush doesn't release the channel.
              <br/>
               Before writting back this bit to zero the internal fifo must empty.
            </comment>
          </bits>
        </reg>
        <reg name="status" protect="r">
          <bits access="r" name="enable" pos="0" rst="0">
            <comment>Enable bit, when '1' the channel is running</comment>
          </bits>
          <bits access="r" name="fifo_empty" pos="4" rst="1">
            <comment>The internal channel fifo is empty</comment>
          </bits>
        </reg>
        <reg name="start_addr" protect="rw">
          <bits access="rw" display="hex" name="start_addr" pos="NB_BITS_ADDR-1:AON_IFC_ADDR_ALIGN" rst="0xFFFFFFF">
            <comment>
              AHB Address. This field represent the start address of the
        transfer.
              <br/>
              For a 32-bit peripheral, this address must be aligned 32-bit.
            </comment>
          </bits>
        </reg>
        <reg name="tc" protect="rw">
          <bits access="rw" display="hex" name="tc" pos="AON_IFC_TC_LEN-1:0" rst="0xFFFFFF">
            <comment>
              Transfer Count, this field indicated the transfer size in bytes to perform.
              <br/>
              During a transfer a write in this register add the new value to the current TC.
              <br/>
              A read of this register return the current current transfer count.
            </comment>
          </bits>
        </reg>
      </struct>
      <reg name="ch_rfspi_control" protect="rw">
        <bits access="s" name="enable" pos="0" rst="no">
          <comment>
            Channel Enable, write one in this bit enable the channel.
            <br/>
            This channel works only in fifo mode.
          </comment>
        </bits>
        <bits access="c" name="disable" pos="1" rst="no">
          <comment>Channel Disable, write one in this bit to disable the channel.</comment>
        </bits>
      </reg>
      <reg name="ch_rfspi_status" protect="r">
        <bits access="r" name="enable" pos="0" rst="0">
          <comment>Enable bit, when '1' the channel is running</comment>
        </bits>
        <bits access="r" name="fifo_empty" pos="4" rst="1">
          <comment>The internal channel fifo is empty</comment>
        </bits>
        <bits access="r" name="fifo_level" pos="12:8" rst="0">
          <comment>Internal fifo level</comment>
        </bits>
      </reg>
      <reg name="ch_rfspi_start_addr" protect="rw">
        <bits access="rw" display="hex" name="start_ahb_addr" pos="NB_BITS_ADDR-1:AON_IFC_ADDR_ALIGN" rst="0xFFFFFFF">
          <comment>
            AHB Start Address.
            <br/>
            This field represent the start address of the fifo.
                 The start address must 32-bit aligned.
          </comment>
        </bits>
      </reg>
      <reg name="ch_rfspi_end_addr" protect="rw">
        <bits access="rw" display="hex" name="end_ahb_addr" pos="NB_BITS_ADDR-1:AON_IFC_ADDR_ALIGN" rst="0xFFFFFFF">
          <comment>
            AHB End Address.
            <br/>
            This field represent the last address of the fifo (it is the first address not used in the fifo).
            <br/>
            The end address must 32-bit aligned.
          </comment>
        </bits>
      </reg>
      <reg name="ch_rfspi_tc" protect="rw">
        <bits access="rw" display="hex" name="tc" pos="13:0" rst="0x0">
          <comment>
            Transfer Count, transfer size in bytes.
            <br/>
            This bit
        indicated the transfer size in bytes to perform. Up to 16kbytes per
        transfer.
            <br/>
            During a transfer a write in this register add the new
        value to the current TC. A read of this register return the current
        current transfer count.
          </comment>
        </bits>
      </reg>
      <hole size="32*(64 - 4 - 4*(AON_IFC_STD_CHAN_NB) -5)"/>
    </module>
  </archive>
  <archive relative="timer.xml">
    <module category="System" name="TIMER">
      <var name="NB_INTERVAL" value="1"/>
      <var name="INT_TIMER_NB_BITS" value="24"/>
      <var name="WD_TIMER_NB_BITS" value="24"/>
      <var name="HW_TIMER_NB_BITS" value="32"/>
      <var name="TIM_MAXVAL" value="0xffffff"/>
      <reg name="ostimer_ctrl" protect="rw">
        <bits access="rw" name="loadval" pos="23:0" rst="0">
          <comment>Value loaded to OS timer.</comment>
        </bits>
        <bits access="rw" name="enable" pos="24" rst="0">
          <comment>
            Write '1' to this bit will enable OS timer.
            <br/>
            When read, the value is what we have written to this bit, it changes immediately  after been written.
          </comment>
        </bits>
        <bits access="r" name="enabled" pos="25" rst="0">
          <comment>
            Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock.
            <br/>
            <br/>
            '1' indicates OS timer enabled.
            <br/>
            '0' indicates OS timer not enabled.
          </comment>
        </bits>
        <bits access="r" name="cleared" pos="26" rst="0">
          <comment>
            Read this bit will get the information if OS timer interruption clear operation is finished or not.
            <br/>
            <br/>
            '1' indicates OS timer interruption clear operation is on going.
            <br/>
            '0' indicates no OS timer interruption clear operation is on going.
          </comment>
        </bits>
        <bits access="rw" name="repeat" pos="28" rst="0">
          <comment>
            Write '1' to this bit will set OS timer to repeat mode.
            <br/>
            When read, get the information if OS timer is in repeat mode.
            <br/>
            <br/>
            '1' indicates OS timer in repeat mode.
            <br/>
            '0' indicates OS timer not in repeat mode.
          </comment>
        </bits>
        <bits access="rw" name="wrap" pos="29" rst="0">
          <comment>
            Write '1' to this bit will set OS timer to wrap mode.
            <br/>
            When read, get the information if OS timer is in wrap mode.
            <br/>
            <br/>
            '1' indicates OS timer in wrap mode.
            <br/>
            '0' indicates OS timer not in wrap mode.
          </comment>
        </bits>
        <bits access="rw" name="load" pos="30" rst="0">
          <comment>Write '1' to this bit will load the initial value to OS timer.</comment>
        </bits>
      </reg>
      <reg name="ostimer_curval" protect="rw">
        <bits access="r" name="curval" pos="31:0" rst="-">
          <comment>Current value of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped.</comment>
        </bits>
      </reg>
      <reg name="wdtimer_ctrl" protect="rw">
        <bits access="s" name="start" pos="0" rst="0">
          <comment>Write '1' to this bit will enable watchdog timer and Load it with WDTimer_LoadVal.</comment>
        </bits>
        <bits access="c" name="stop" pos="4" rst="0">
          <comment>Write '1' to this bit will stop watchdog timer.</comment>
        </bits>
        <bits access="w" name="reload" pos="16" rst="0">
          <comment>
            Write '1' to this bit will load WDTimer_LoadVal value to watchdog timer.
            <br/>
            Use this bit to implement the watchog keep alive.
          </comment>
        </bits>
        <bits access="r" name="wdenabled" pos="8" rst="0">
          <comment>
            Read this bit will get the information if watchdog timer is really enabled or not. This bit will change only after the next front of 32 KHz system clock.
            <br/>
            <br/>
            '1' indicates watchdog timer is enabled, if current watchdog timer value reaches 0, the system will be reseted.
            <br/>
            '0' indicates watchdog timer is not enabled.
          </comment>
        </bits>
      </reg>
      <reg name="wdtimer_loadval" protect="rw">
        <bits access="rw" name="wdloadval" pos="WD_TIMER_NB_BITS-1:0" rst="-">
          <comment>
            Load value of watchdog timer. Number of 32kHz Clock before Reset.
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="hwtimer_ctrl" protect="rw">
        <bits access="rw" name="interval_en" pos="8" rst="0">
          <comment>
            This bit enables interval IRQ mode.
            <br/>
            <br/>
            '0': hw delay timer does not generate interval IRQ.
            <br/>
            '1': hw delay timer generate an IRQ each interval.
          </comment>
        </bits>
        <bits access="rw" name="interval" pos="1:0" rst="00">
          <comment>
            interval of generating an HwTimer IRQ.
            <br/>
            <br/>
            &quot;00&quot;: interval of 1/8 second.
            <br/>
            &quot;01&quot;: interval of 1/4 second.
            <br/>
            &quot;10&quot;: interval of 1/2 second.
            <br/>
            &quot;11&quot;: interval of 1 second.
          </comment>
        </bits>
      </reg>
      <reg name="hwtimer_curval" protect="rw">
        <bits access="r" name="curval" pos="31:0" rst="0">
          <comment>Current value of the hardware delay timer. The value is incremented every 61 us. This timer is running all the time and wrap at value 0xFFFFFFFF.</comment>
        </bits>
      </reg>
      <reg name="timer_irq_mask_set" protect="rw">
        <bits access="rs" name="ostimer_mask" pos="0" rst="0">
          <comment>Set mask for OS timer IRQ.</comment>
        </bits>
        <bits access="rs" name="hwtimer_wrap_mask" pos="1" rst="0">
          <comment>Set mask for hardwre delay timer wrap IRQ.</comment>
        </bits>
        <bits access="rs" name="hwtimer_itv_mask" pos="2" rst="0">
          <comment>Set mask for hardwre delay timer interval IRQ.</comment>
        </bits>
      </reg>
      <reg name="timer_irq_mask_clr" protect="rw">
        <bits access="rc" name="ostimer_mask" pos="0" rst="0">
          <comment>Clear mask for OS timer IRQ.</comment>
        </bits>
        <bits access="rc" name="hwtimer_wrap_mask" pos="1" rst="0">
          <comment>Clear mask for hardwre delay timer wrap IRQ.</comment>
        </bits>
        <bits access="rc" name="hwtimer_itv_mask" pos="2" rst="0">
          <comment>Clear mask for hardwre delay timer interval IRQ.</comment>
        </bits>
      </reg>
      <reg name="timer_irq_clr" protect="rw">
        <bits access="c" name="ostimer_clr" pos="0" rst="0">
          <comment>Clear OS timer IRQ.</comment>
        </bits>
        <bits access="c" name="hwtimer_wrap_clr" pos="1" rst="0">
          <comment>Clear hardware delay timer wrap IRQ.</comment>
        </bits>
        <bits access="c" name="hwtimer_itv_clr" pos="2" rst="0">
          <comment>Clear hardware delay timer interval IRQ.</comment>
        </bits>
      </reg>
      <reg name="timer_irq_cause" protect="rw">
        <bits access="r" name="ostimer_cause" pos="0" rst="0">
          <comment>OS timer IRQ cause.</comment>
        </bits>
        <bits access="r" name="hwtimer_wrap_cause" pos="1" rst="0">
          <comment>hardware delay timer wrap IRQ cause.</comment>
        </bits>
        <bits access="r" name="hwtimer_itv_cause" pos="2" rst="0">
          <comment>hardware delay timer interval IRQ cause.</comment>
        </bits>
        <bits access="r" name="ostimer_status" pos="16" rst="0">
          <comment>OS timer IRQ status.</comment>
        </bits>
        <bits access="r" name="hwtimer_wrap_status" pos="17" rst="0">
          <comment>hardware delay timer wrap IRQ status.</comment>
        </bits>
        <bits access="r" name="hwtimer_itv_status" pos="18" rst="0">
          <comment>hardware delay timer interval IRQ status.</comment>
        </bits>
        <bitgroup name="other_tims_irq">
          <entry ref="hwtimer_wrap_cause"/>
          <entry ref="hwtimer_itv_cause"/>
        </bitgroup>
      </reg>
    </module>
  </archive>
  <archive relative="timer_ap.xml">
    <module category="System" name="TIMER_AP">
      <reg name="ostimer_loadval_l" protect="rw">
        <bits access="rw" name="loadval_l" pos="31:0" rst="0">
          <comment>Value low 32bits loaded to OS timer.</comment>
        </bits>
      </reg>
      <reg name="ostimer_ctrl" protect="rw">
        <bits access="rw" name="loadval_h" pos="23:0" rst="0">
          <comment>Value high 24bits loaded to OS timer.</comment>
        </bits>
        <bits access="rw" name="enable" pos="24" rst="0">
          <comment>
            Write '1' to this bit will enable OS timer.
            <br/>
            When read, the value is what we have written to this bit, it changes immediately  after been written.
          </comment>
        </bits>
        <bits access="r" name="enabled" pos="25" rst="0">
          <comment>
            Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock.
            <br/>
            <br/>
            '1' indicates OS timer enabled.
            <br/>
            '0' indicates OS timer not enabled.
          </comment>
        </bits>
        <bits access="r" name="cleared" pos="26" rst="0">
          <comment>
            Read this bit will get the information if OS timer interruption clear operation is finished or not.
            <br/>
            <br/>
            '1' indicates OS timer interruption clear operation is on going.
            <br/>
            '0' indicates no OS timer interruption clear operation is on going.
          </comment>
        </bits>
        <bits access="rw" name="repeat" pos="28" rst="0">
          <comment>
            Write '1' to this bit will set OS timer to repeat mode.
            <br/>
            When read, get the information if OS timer is in repeat mode.
            <br/>
            <br/>
            '1' indicates OS timer in repeat mode.
            <br/>
            '0' indicates OS timer not in repeat mode.
          </comment>
        </bits>
        <bits access="rw" name="wrap" pos="29" rst="0">
          <comment>
            Write '1' to this bit will set OS timer to wrap mode.
            <br/>
            When read, get the information if OS timer is in wrap mode.
            <br/>
            <br/>
            '1' indicates OS timer in wrap mode.
            <br/>
            '0' indicates OS timer not in wrap mode.
          </comment>
        </bits>
        <bits access="rw" name="load" pos="30" rst="0">
          <comment>Write '1' to this bit will load the initial value to OS timer.</comment>
        </bits>
      </reg>
      <reg name="ostimer_curval_l" protect="rw">
        <bits access="r" name="curval_l" pos="31:0" rst="-">
          <comment>Current value low 32bits of OS timer.</comment>
        </bits>
      </reg>
      <reg name="ostimer_curval_h" protect="rw">
        <bits access="r" name="curval_h" pos="31:0" rst="-">
          <comment>Current value high bits of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped.</comment>
        </bits>
      </reg>
      <reg name="ostimer_lockval_l" protect="rw">
        <bits access="r" name="lockval_l" pos="31:0" rst="0">
          <comment>Current locked value low 32bits of OS timer.</comment>
        </bits>
      </reg>
      <reg name="ostimer_lockval_h" protect="rw">
        <bits access="r" name="lockval_h" pos="31:0" rst="0">
          <comment>Current locked value high bits of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped.</comment>
        </bits>
      </reg>
      <reg name="hwtimer_ctrl" protect="rw">
        <bits access="rw" name="interval_en" pos="8" rst="0">
          <comment>
            This bit enables interval IRQ mode.
            <br/>
            <br/>
            '0': hw delay timer does not generate interval IRQ.
            <br/>
            '1': hw delay timer generate an IRQ each interval.
          </comment>
        </bits>
        <bits access="rw" name="interval" pos="1:0" rst="00">
          <comment>
            interval of generating an HwTimer IRQ.
            <br/>
            <br/>
            &quot;00&quot;: interval of 1/8 second.
            <br/>
            &quot;01&quot;: interval of 1/4 second.
            <br/>
            &quot;10&quot;: interval of 1/2 second.
            <br/>
            &quot;11&quot;: interval of 1 second.
          </comment>
        </bits>
      </reg>
      <reg name="hwtimer_curval_l" protect="rw">
        <bits access="r" name="curval_l" pos="31:0" rst="0">
          <comment>Current low 32bits value of the hardware delay timer.</comment>
        </bits>
      </reg>
      <reg name="hwtimer_curval_h" protect="rw">
        <bits access="r" name="curval_h" pos="31:0" rst="0">
          <comment>Current high 32bits value of the hardware delay timer.</comment>
        </bits>
      </reg>
      <reg name="hwtimer_lockval_l" protect="rw">
        <bits access="r" name="lockval_l" pos="31:0" rst="0">
          <comment>Current locked low 32bits value of the hardware delay timer.</comment>
        </bits>
      </reg>
      <reg name="hwtimer_lockval_h" protect="rw">
        <bits access="r" name="lockval_h" pos="31:0" rst="0">
          <comment>Current locked high 32bits value of the hardware delay timer.</comment>
        </bits>
      </reg>
      <reg name="timer_irq_mask_set" protect="rw">
        <bits access="rs" name="ostimer_mask" pos="0" rst="0">
          <comment>Set mask for OS timer IRQ.</comment>
        </bits>
        <bits access="rs" name="hwtimer_wrap_mask" pos="1" rst="0">
          <comment>Set mask for hardwre delay timer wrap IRQ.</comment>
        </bits>
        <bits access="rs" name="hwtimer_itv_mask" pos="2" rst="0">
          <comment>Set mask for hardwre delay timer interval IRQ.</comment>
        </bits>
      </reg>
      <reg name="timer_irq_mask_clr" protect="rw">
        <bits access="rc" name="ostimer_mask" pos="0" rst="0">
          <comment>Clear mask for OS timer IRQ.</comment>
        </bits>
        <bits access="rc" name="hwtimer_wrap_mask" pos="1" rst="0">
          <comment>Clear mask for hardwre delay timer wrap IRQ.</comment>
        </bits>
        <bits access="rc" name="hwtimer_itv_mask" pos="2" rst="0">
          <comment>Clear mask for hardwre delay timer interval IRQ.</comment>
        </bits>
      </reg>
      <reg name="timer_irq_clr" protect="rw">
        <bits access="c" name="ostimer_clr" pos="0" rst="0">
          <comment>Clear OS timer IRQ.</comment>
        </bits>
        <bits access="c" name="hwtimer_wrap_clr" pos="1" rst="0">
          <comment>Clear hardware delay timer wrap IRQ.</comment>
        </bits>
        <bits access="c" name="hwtimer_itv_clr" pos="2" rst="0">
          <comment>Clear hardware delay timer interval IRQ.</comment>
        </bits>
      </reg>
      <reg name="timer_irq_cause" protect="rw">
        <bits access="r" name="ostimer_cause" pos="0" rst="0">
          <comment>OS timer IRQ cause.</comment>
        </bits>
        <bits access="r" name="hwtimer_wrap_cause" pos="1" rst="0">
          <comment>hardware delay timer wrap IRQ cause.</comment>
        </bits>
        <bits access="r" name="hwtimer_itv_cause" pos="2" rst="0">
          <comment>hardware delay timer interval IRQ cause.</comment>
        </bits>
        <bits access="r" name="ostimer_status" pos="16" rst="0">
          <comment>OS timer IRQ status.</comment>
        </bits>
        <bits access="r" name="hwtimer_wrap_status" pos="17" rst="0">
          <comment>hardware delay timer wrap IRQ status.</comment>
        </bits>
        <bits access="r" name="hwtimer_itv_status" pos="18" rst="0">
          <comment>hardware delay timer interval IRQ status.</comment>
        </bits>
        <bitgroup name="other_tims_irq">
          <entry ref="hwtimer_wrap_cause"/>
          <entry ref="hwtimer_itv_cause"/>
        </bitgroup>
      </reg>
    </module>
  </archive>
  <archive relative="arm_uart.xml">
    <module category="Periph" name="ARM_UART">
      <reg name="uart_tx" protect="rw">
        <bits access="rw" name="tx_data" pos="7:0" rst="0">
          <comment>transmit data register</comment>
        </bits>
      </reg>
      <reg name="uart_rx" protect="r">
        <bits access="r" name="rx_data" pos="7:0" rst="0">
          <comment>receive data register</comment>
        </bits>
      </reg>
      <reg name="uart_baud" protect="rw">
        <bits access="rw" name="baud_const" pos="19:16" rst="3">
          <comment>baud rate divider constant N: (N&gt;=4)
0011:  N=4
...
0111:  N=8
...
1111:  N=16</comment>
        </bits>
        <bits access="rw" name="baud_div" pos="15:0" rst="6">
          <comment>baud rate divider coeffcient,baud rate formula is:
BAUD RATE = Fclk/(Nx(BAUD_DIV+1))
default baud rate is 921.6K, N=4, Ffun=26MHz.</comment>
        </bits>
      </reg>
      <reg name="uart_conf" protect="rw">
        <bits access="rw" name="st_parity" pos="26" rst="0">
          <comment>Stick parity enble
1:  enable
0:  disable</comment>
        </bits>
        <bits access="rw" name="at_lock_ie" pos="25" rst="0">
          <comment>Automatic baud detection complete interrupt enable
1:  enable
0:  disable</comment>
        </bits>
        <bits access="rw" name="swfc_en" pos="24" rst="0">
          <comment>software flow control bit
1:  enable
0:  disable</comment>
        </bits>
        <bits access="rw" name="swfc_xon_ie" pos="23" rst="0">
          <comment>1: enable software flow XON interrupt
0: disable software flow XON interrupt</comment>
        </bits>
        <bits access="rw" name="swfc_xoff_ie" pos="22" rst="0">
          <comment>1: enable software flow XOFF interrupt
0: disable software flow XOFF interrupt</comment>
        </bits>
        <bits access="rw" name="at_enable" pos="21" rst="0">
          <comment>1:  enable automatically detect baud rate
0:  disable automatically detect baud rate</comment>
        </bits>
        <bits access="rw" name="at_div_mode" pos="20" rst="0">
          <comment>1:  autobaud BAUD_CONST=4'b1111
0:  autobaud BAUD_CONST=4'b0011</comment>
        </bits>
        <bits access="rw" name="at_verify_2byte" pos="19" rst="0">
          <comment>1:  the automatic baud rate detects 2 bytes
0:  the automatic baud rate detects 1 byte</comment>
        </bits>
        <bits access="rw" name="at_parity_sel" pos="17:16" rst="0">
          <comment>2'b00:  automatic baud rate detection using odd check
2'b01:  automatic baud rate detection using even check</comment>
        </bits>
        <bits access="rw" name="at_parity_en" pos="15" rst="0">
          <comment>1:  automatic baud rate detection has test bit
0:  automatic baud rate detection has no test bit</comment>
        </bits>
        <bits access="rw" name="rxrst" pos="14" rst="0">
          <comment>RX FIFO reset control
1:  RX FIFO reset
0:  RX FIFO not reset; or set 1'b1, auto clear to 1'b0</comment>
        </bits>
        <bits access="rw" name="txrst" pos="13" rst="0">
          <comment>TX FIFO reset control
1:  TX FIFO reset
0:  TX FIFO not reset;or set to 1'b1,auto clear to 1'b0</comment>
        </bits>
        <bits access="rw" name="trail" pos="12" rst="0">
          <comment>TRAIL byte manipulation:
  1:  DMA dispose the TRAIL byte of RXFIFO
  0:  ARM dispose the TRALL byte of RXFIFO</comment>
        </bits>
        <bits access="rw" name="frm_stp" pos="11" rst="0">
          <comment>frames stop control
1:  enable
0:  disable</comment>
        </bits>
        <bits access="rw" name="hdlc" pos="10" rst="0">
          <comment>HDLC escape bytes enable control
1:  enable add escape bytes(transit data),and remove escape byte(receive data)
0:  disable</comment>
        </bits>
        <bits access="rw" name="tout_hwfc" pos="9" rst="0">
          <comment>after RX timeout, enable hardware flow control (on condition that HWFC is enable)
1:  after RX timeout,enable hardware flow control. Do not accept data until the timeout bit has been cleared, so that disable the hardware flow control
0:  after RX timeout, disable hardware flow control</comment>
        </bits>
        <bits access="rw" name="rx_trig_hwfc" pos="8" rst="0">
          <comment>RX trigger RTS enable control (on condition that HWFC is enable)
1:  enable RX TRIG trigger RTS flow signal
0:  disable RX TRIG trigger RTS flow signal</comment>
        </bits>
        <bits access="rw" name="hwfc" pos="7" rst="0">
          <comment>hardware flow control bit
1:  enable
0:  disable</comment>
        </bits>
        <bits access="rw" name="tout_ie" pos="6" rst="0">
          <comment>RX timeout interrupt control bit
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="tx_ie" pos="5" rst="0">
          <comment>TX data interrupt control bit
1: enable TX interrupt
0: disable TX interrupt</comment>
        </bits>
        <bits access="rw" name="rx_ie" pos="4" rst="0">
          <comment>RX data interrupt control bit
1: enable RX interrupt
0: disable RX interrupt</comment>
        </bits>
        <bits access="rw" name="st_check" pos="3" rst="0">
          <comment>stop bit detection control bit
1: enable stop bit detection
0: disable stop bit detection</comment>
        </bits>
        <bits access="rw" name="stop_bit" pos="2" rst="1">
          <comment>stop bit control bit
1: 2bit stop bit
0: 1bit stop bit</comment>
        </bits>
        <bits access="rw" name="parity" pos="1" rst="0">
          <comment>check bit
1: odd check
0: even check</comment>
        </bits>
        <bits access="rw" name="check" pos="0" rst="0">
          <comment>check bit enable or not
1: enable
0: disable</comment>
        </bits>
      </reg>
      <reg name="uart_rxtrig" protect="rw">
        <bits access="rw" name="rx_trig" pos="7:0" rst="1">
          <comment>RX FIFO trigger settings
00000000: don't trigger
00000001: 1 byte trigger
00000010: 2 bytes trigger
00000011: 3 bytes trigger
00000100: 4 bytes trigger
......
01111111: 127bytes trigger
10000000: 128bytes trigger</comment>
        </bits>
      </reg>
      <reg name="uart_txtrig" protect="rw">
        <bits access="rw" name="tx_trig" pos="7:0" rst="0">
          <comment>TX FIFO trigger setting
00000000: 0 byte trigger
00000001: 1 byte trigger
00000010: 2 bytes trigger
00000011: 3 bytes trigger
00000100: 4 bytes trigger
......
01111110: 126bytes trigger
01111111: 127bytes trigger
10000000: don't trigger</comment>
        </bits>
      </reg>
      <reg name="uart_delay" protect="rw">
        <bits access="rw" name="two_tx_delay" pos="11:8" rst="0">
          <comment>configure the time interval between sending data twice
0000:  interval 0 baud rate clock
0001:  interval 1 baud rate clock
1111:  interval 15 baud rate clock</comment>
        </bits>
        <bits access="rw" name="toutcnt" pos="7:0" rst="43">
          <comment>configure the threshold value of the UART timeout interrupt counter
00000000:  configure the initial value of 0 baud rate clock
00000001:  configure the initial value of 1 baud rate clock
00000010:  configure the initial value of  2 baud rate clock
......
11111111:  configure the initial value of 255 baud rate clock</comment>
        </bits>
      </reg>
      <reg name="uart_status" protect="rw">
        <bits access="rc" name="xon_status" pos="10" rst="0">
          <comment>bit type is changed from rw1c to rc.
          XON interrupt status bit
1: XON interrupt
0: not XON interrupt</comment>
        </bits>
        <bits access="rc" name="xoff_status" pos="9" rst="0">
          <comment>bit type is changed from rw1c to rc.
          XOFF interrupt status bit
1: XOFF interrupt
0: not XOFF interrupt</comment>
        </bits>
        <bits access="r" name="swfc_status" pos="8" rst="0">
          <comment>SWFC status
1: prohbit home terminal to send
0: allow home terminal to send</comment>
        </bits>
        <bits access="rc" name="rts" pos="7" rst="0">
          <comment>bit type is changed from rw1c to rc.
          request to send status bit
1: prohibit far-end to send
0: request far-end to send</comment>
        </bits>
        <bits access="rc" name="cts" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          clear the sending status bit
1: prohibit home terminal to send
0: allow home terminal to send</comment>
        </bits>
        <bits access="rc" name="st_error" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          the received data stop bit state
1: stop bit error
0: stop bit right</comment>
        </bits>
        <bits access="rc" name="p_error" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          RX data parity status
1: parity error
0:  parity right</comment>
        </bits>
        <bits access="rc" name="frame_int" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          RX data frame stop bit interrupt status bit
1: received frame stop bit &quot;7E&quot;
0: not received frame stop bit &quot;7E&quot;</comment>
        </bits>
        <bits access="rc" name="timeout_int" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          RX data timeout interrupt status bit
1: timeout
0: not timeout</comment>
        </bits>
        <bits access="rc" name="rx_int" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          RX data interrupt status bit
1: RX_FIFO_CNTRX_TRIG
0: RX_FIFO_CNT&lt;RX_TRIG</comment>
        </bits>
        <bits access="rc" name="tx_int" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          TX data interrupt status bit
1: TX_FIFO_CNT TX_TRIG
0: TX_FIFO_CNT &gt;TX_TRIG</comment>
        </bits>
      </reg>
      <reg name="uart_rxfifo_stat" protect="r">
        <bits access="r" name="rx_fifo_cnt" pos="7:0" rst="0">
          <comment>RX FIFO data number
00000000: RX FIFO has 0 data
00000001: RX FIFO has 1 data
......
01111111: RX FIFO has 127 data
10000000: RX FIFO has 128 data</comment>
        </bits>
      </reg>
      <reg name="uart_txfifo_stat" protect="r">
        <bits access="r" name="tx_fifo_cnt" pos="7:0" rst="0">
          <comment>TX FIFO data number
00000000: TX FIFO has 0 data
00000001: TX FIFO has 1 data
......
01111111: TX FIFO has 127 data
10000000: TX FIFO has 128 data</comment>
        </bits>
      </reg>
      <reg name="uart_rxfifo_hdlc" protect="r">
        <bits access="r" name="hdlc_rxfifo_cnt" pos="7:0" rst="0">
          <comment>enable HDLC, the number of RX FIFO data when received at the end of frames(include the end of frames)
00000000: RX FIFO has 0 data
00000001: RX FIFO has 1 data
......
01111111: RX FIFO has 127 data
10000000: RX FIFO has 128 data
Note: UART_RXFIFO_HDLC only read.Uart automatically updates the register value, after receiving the end of frames &quot;7e&quot;.</comment>
        </bits>
      </reg>
      <reg name="uart_at_status" protect="r">
        <bits access="r" name="character_status" pos="18" rst="0">
          <comment>After automatic detection, the detective byte is &quot;AT&quot; or &quot;at&quot;
1: &quot;AT&quot;
0: &quot;at&quot;</comment>
        </bits>
        <bits access="r" name="auto_baud_locked" pos="17" rst="0">
          <comment>1: Automatic detection complete,lock baud rate
0: automatic detection is not completed</comment>
        </bits>
        <bits access="r" name="character_miscompare" pos="16" rst="0">
          <comment>1: automatic detection failed, no matching bytes detected
0: automatic detection of matching bytes</comment>
        </bits>
        <bits access="r" name="at_baud_div" pos="15:0" rst="0">
          <comment>automatic detection of BAUD_DIV values</comment>
        </bits>
      </reg>
      <reg name="uart_swfc_cc" protect="rw">
        <bits access="rw" name="xon_cc" pos="15:8" rst="17">
          <comment>XON characteristic parameter</comment>
        </bits>
        <bits access="rw" name="xoff_cc" pos="7:0" rst="19">
          <comment>XOFF characteristic parameter</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="keypad.xml">
    <module category="Periph" name="KEYPAD">
      <var name="KEY_NB" value="36">
        <comment>Number of key in the keypad</comment>
      </var>
      <var name="LOW_KEY_NB" value="30">
        <comment>Number of key in the low data register</comment>
      </var>
      <var name="HIGH_KEY_NB" value="6">
        <comment>Number of key in the high data register</comment>
      </var>
      <reg name="kp_data_l" protect="r">
        <bits access="r" name="kp_data_l" pos="31:0" rst="0">
          <comment>
            For keys in column Idx_KeyOut(from 0 to 3) and in line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_L(Idx_KeyOut*8+Idx_KeyIn) :
            <br/>
            0 = Released
            <br/>
            1 = Pressed
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <reg name="kp_data_h" protect="r">
        <bits access="r" name="kp_data_h" pos="31:0" rst="0">
          <comment>
            For keys in column Idx_KeyOut(from 4 to 7) and line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_H(Idx_KeyIn*8-32+Idx_KeyIn):
            <br/>
            0 = Released
            <br/>
            1 = Pressed
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <reg name="kp_status" protect="r">
        <bits access="r" name="keyin_status" pos="7:0" rst="0x08">
          <comment>
            For keys in lines status
            <br/>
            0 = Released
            <br/>
            1 = Pressed
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="kp_on" pos="31" rst="0">
          <comment>
            Indicate Key ON pressing status :
            <br/>
            0 = Release
            <br/>
            1 = Pressed
          </comment>
          <options>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <reg name="kp_ctrl" protect="rw">
        <bits access="rw" name="kp_en" pos="0" rst="0">
          <comment>
            This bit enables key detection. If this bit is '0', the key detection function
            is disabled. Key ON is an exception, it can be still detected and generate key interrupt
            even if KP_En = '0', however in this case, the debouncing time configuration in key
            control register is ignored and the key ON state is considerred to be stable if it keeps
            same in consecutive 2 cycles of 16KHz clock.
            <br/>
            <br/>
            0 = keypad disable
            <br/>
            1 = keypad enable
          </comment>
        </bits>
        <bits access="rw" name="kp_dbn_time" pos="9:2" rst="0">
          <comment>De-bounce time = (KP_DBN_TIME + 1) * SCAN_TIME, SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_DBN_TIME = 7, KP_OUT_MASK = &quot;111111&quot;, then De-bounce time = (7+1)*0.3125*6=15 ms. The maximum debounce time is 480 ms.</comment>
        </bits>
        <bits access="rw" name="kp_itv_time" pos="15:10" rst="0">
          <comment>Configure interval of generating an IRQ if one key or several keys are pressed long time. Interval of IRQ generation = (KP_ITV_Time + 1) * (KP_DBN_TIME + 1) * SCAN_TIME. SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_ITV_TIME = 7, KP_DBN_TIME = 7, KP_OUT_MASK = &quot;111111&quot;, then De-bounce time = (7+1)*(7+1)*0.3125*6=120 ms.</comment>
        </bits>
        <bits access="rw" name="kp_in_mask" pos="23:16" rst="0xff">
          <comment>
            each bit masks one input lines.
            <br/>
            '1' = enabled
            <br/>
             '0' = disabled
            <br/>
            The Key In pins 0 to 5 are muxed with the boot mode pins, latched during Reset.
            <br/>
             Key_In 0: BOOT_MODE_NO_AUTO_PU.
            <br/>
             Key_In 1: BOOT_MODE_FORCE_MONITOR.
            <br/>
             Key_In 2: BOOT_MODE_UART_MONITOR_ENABLE.
            <br/>
             Key_In 3: BOOT_MODE_USB_MONITOR_DISABLE.
            <br/>
             Key_In 4: reserved
          </comment>
        </bits>
        <bits access="rw" name="kp_out_mask" pos="31:24" rst="0xff">
          <comment>
            each bit masks one output lines.
            <br/>
            '1' = enabled
            <br/>
             '0' = disabled
          </comment>
        </bits>
      </reg>
      <reg name="kp_irq_mask" protect="rw">
        <bits access="rw" name="kp_evt0_irq_mask" pos="0" rst="0">
          <comment>
            This bit mask keypad irq generated by event0 (key press or key release event, not including all keys release event which is event1).
            <br/>
            0 = keypad event irq disable
            <br/>
            1 = keypad event irq enable
          </comment>
        </bits>
        <bits access="rw" name="kp_evt1_irq_mask" pos="1" rst="0">
          <comment>
            This bit mask keypad irq generated by event1 (all keys release event).
            <br/>
            0 = keypad event irq disable
            <br/>
            1 = keypad event irq enable
          </comment>
        </bits>
        <bits access="rw" name="kp_itv_irq_mask" pos="2" rst="0">
          <comment>
            This bit mask keypad irq generated by key pressed long time (generated each interval configured in KP_ITV_Time.
            <br/>
            0 = keypad interval irq disable
            <br/>
            1 = keypad interval irq enable
          </comment>
        </bits>
      </reg>
      <reg name="kp_irq_cause" protect="r">
        <bits access="r" name="kp_evt0_irq_cause" pos="0" rst="0">
          <comment>keypad event0(key press or key release event, not including all keys release which is event1) IRQ cause.</comment>
        </bits>
        <bits access="r" name="kp_evt1_irq_cause" pos="1" rst="0">
          <comment>keypad event1(all keys release event) IRQ cause.</comment>
        </bits>
        <bits access="r" name="kp_itv_irq_cause" pos="2" rst="0">
          <comment>keypad interval irq cause.</comment>
        </bits>
        <bits access="r" name="kp_evt0_irq_status" pos="16" rst="0">
          <comment>keypad event0(key press or key release event, not including all keys release which is event1) irq status.</comment>
        </bits>
        <bits access="r" name="kp_evt1_irq_status" pos="17" rst="0">
          <comment>keypad event1(all keys release event) irq status.</comment>
        </bits>
        <bits access="r" name="kp_itv_irq_status" pos="18" rst="0">
          <comment>keypad interval irq status.</comment>
        </bits>
      </reg>
      <reg name="kp_irq_clr" protect="rw">
        <bits access="c" name="kp_irq_clr" pos="0" rst="0">
          <comment>Write '1' to this bit clears key IRQ.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="pwm.xml">
    <module category="Periph" name="PWM">
      <reg name="pwt_config" protect="rw">
        <bits access="rw" name="pwt_enable" pos="0" rst="0">
          <comment>
            Enables the Pulse Width Tone output
            <br/>
            1 = Enable PWT output
            <br/>
            0 = Disable PWT output
          </comment>
        </bits>
        <bits access="r" name="pwt_start" pos="1" rst="0">
          <comment>The working status of PWT.</comment>
        </bits>
        <bits access="rw" name="pwt_duty" pos="13:4" rst="all1">
          <comment>
            The PWT_Duty value can be used to set the approximate volume of the tone.
            <br/>
             The PWT_Duty value must be less than or equal to half the PWT_Period value and must be at least a value of 8, otherwise no tone will be generated.
          </comment>
        </bits>
        <bits access="rw" name="pwt_period" pos="26:16" rst="all1">
          <comment>
            PWT_Period is the divider value to produce a tone of a given frequency.
            <br/>
             To calculate the PWT_Period value, Use the following formula:
            <br/>
              PWT_Period = FBASE/FNOTE
            <br/>
             where FBASE is the frequency of the PWM module clock (it is based on the system frequency, 26, 39, 52, 78 or 104 MHz divided by 5).  FNOTE is the frequency of the desired tone.
          </comment>
        </bits>
      </reg>
      <reg name="lpg_config" protect="rw">
        <bits access="rw" name="lpg_reset_l" pos="0" rst="0">
          <comment>Setting this bit to '0' will reset the Light Pulse Generator internal counters.</comment>
        </bits>
        <bits access="rw" name="lpg_test" pos="1" rst="0">
          <comment>Setting this bit to '0' will reset the Light Pulse Generator internal counters.</comment>
        </bits>
        <bits access="rw" name="lpg_ontime" pos="7:4" rst="0xf">
          <comment>Configures the duty cycle for the Light Pulse Generator by setting the ontime for the LPG output. The actual on-time is calculated as: Tick Period * LPG_OnTime * 256 where the Tick Period is nominally 1/16kHz.</comment>
          <options>
            <option name="undefined" value="0"/>
            <option name="15_6mS" value="1"/>
            <option name="31_2mS" value="2"/>
            <option name="46_8mS" value="3"/>
            <option name="62mS" value="4"/>
            <option name="78mS" value="5"/>
            <option name="94mS" value="6"/>
            <option name="110mS" value="7"/>
            <option name="125mS" value="8"/>
            <option name="140mS" value="9"/>
            <option name="156mS" value="10"/>
            <option name="172mS" value="11"/>
            <option name="188mS" value="12"/>
            <option name="200mS" value="13"/>
            <option name="218mS" value="14"/>
            <option name="234mS" value="15"/>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="lpg_period" pos="18:16" rst="0">
          <comment>
            Configures the main period of the light pulse generator. The period is calculated based on the following configurations:
            <br/>
            with the Tick Period ~ 1/16kHz
            <br/>
          </comment>
          <options>
            <option name="0_125s" value="0">
              <comment>Tick Period * 2048</comment>
            </option>
            <option name="0_25s" value="1">
              <comment>Tick Period * 4096</comment>
            </option>
            <option name="0_5s" value="2">
              <comment>Tick Period * 8192</comment>
            </option>
            <option name="0_75s" value="3">
              <comment>Tick Period * 12288</comment>
            </option>
            <option name="1s" value="4">
              <comment>Tick Period * 16384</comment>
            </option>
            <option name="1_25s" value="5">
              <comment>Tick Period * 20480</comment>
            </option>
            <option name="1_5s" value="6">
              <comment>Tick Period * 24576</comment>
            </option>
            <option name="1_75s" value="7">
              <comment>Tick Period * 28672</comment>
            </option>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <reg name="pwl0_config" protect="rw">
        <bits access="rw" name="pwl_min" pos="7:0" rst="all1">
          <comment>Sets the lower boundary for PWL pulse.  When pulse mode is not used, this is the threshold value for the PWL0.  Reading this value will return the current value used for the threshold.</comment>
        </bits>
        <bits access="rw" name="pwl_max" pos="15:8" rst="all1">
          <comment>Sets the upper boundary for PWL pulse.  When pulse mode is not used, this value is ignored.  Reading this value will return the LFSR value used for generating the PWL outputs.</comment>
        </bits>
        <bits access="rs" name="pwl0_en_h" pos="16" rst="0">
          <comment>When this bit is written with '1', the PWL 0 is enabled and the output is a PRBS whose average on-time is proportional to PWL_Min.  This bit is cleared when either of the Force bits are written.  Reading this bit will return the current state of the PWL0 enable.</comment>
        </bits>
        <bits access="rc" name="pwl0_force_l" pos="17" rst="0">
          <comment>Writing a '1' to this bit will force the PWL0 to output a low value.  If the PWL0 was previously enabled, this will clear the bit.</comment>
        </bits>
        <bits access="r" name="pwl0_force_h" pos="18" rst="no">
          <comment>Writing a '1' to this bit will force the PWL0 to output a high value.  If the PWL0 was previously enabled, this will clear the bit.</comment>
        </bits>
        <bits access="rw" name="pwl_pulse_en" pos="19" rst="0">
          <comment>This will enable the PWL pulse mode.  The threshold will dynamically sweep between PWL_Min and PWL_Max at a rate depending on PWL_Pulse_Per.</comment>
        </bits>
        <bits access="rs" name="pwl0_set_oe" pos="20" rst="0">
          <comment>Writing '1' to this bit will set the output enable.  Reading this bit will return the current status.</comment>
        </bits>
        <bits access="c" name="pwl0_clr_oe" pos="21" rst="no">
          <comment>Writing '1' to this bit will clear the output enable.</comment>
        </bits>
        <bits access="rs" name="pwl_set_mux" pos="22" rst="0">
          <comment>Writing a '1' to this bit will swap the PWL0 and PWL1 outputs.  Reading this bit will return the current status.</comment>
        </bits>
        <bits access="c" name="pwl_clr_mux" pos="23" rst="no">
          <comment>Writing a '1' to this bit will unswap the PWL0/PWL1 outputs.</comment>
        </bits>
        <bits access="w" name="pwl_pulse_per" pos="31:24" rst="all1">
          <comment>This value will adjust the pulse period when pulsing is enabled.</comment>
        </bits>
      </reg>
      <reg name="pwl1_config" protect="rw">
        <bits access="rw" name="pwl1_threshold" pos="7:0" rst="all1">
          <comment>Average duty cycle for the Pulse Width Light 1 output. The average duty cycle is calculated as PWL1_Threshold/256.</comment>
        </bits>
        <bits access="r" name="lfsr_reg" pos="15:8" rst="0xa1">
          <comment>LFSR value for PWL.</comment>
        </bits>
        <bits access="rs" name="pwl1_en_h" pos="16" rst="0">
          <comment>When this bit is written with '1', the PWL 1 is enabled and the output is a PRBS whose average on-time is proportional to PWL1_Threshold.  This bit is cleared when either of the Force bits are written.  Reading this bit will return the current state of the PWL1 enable.</comment>
        </bits>
        <bits access="rc" name="pwl1_force_l" pos="17" rst="0">
          <comment>Writing a '1' to this bit will force the PWL1 to output a low value.  If the PWL1 was previously enabled, this will clear the bit.</comment>
        </bits>
        <bits access="r" name="pwl1_force_h" pos="18" rst="no">
          <comment>Writing a '1' to this bit will force the PWL1 to output a high value.  If the PWL1 was previously enabled, this will clear the bit.</comment>
        </bits>
        <bits access="rs" name="pwl1_set_oe" pos="20" rst="0">
          <comment>Writing '1' to this bit will set the output enable.  Reading this bit will return the current status.</comment>
        </bits>
        <bits access="c" name="pwl1_clr_oe" pos="21" rst="no">
          <comment>Writing '1' to this bit will clear the output enable.</comment>
        </bits>
      </reg>
      <reg name="tsc_data" protect="r">
        <bits access="r" name="tsc_x_value_bit" pos="9:0" rst="0">
          <comment>TSC X Value.</comment>
        </bits>
        <bits access="r" name="tsc_x_value_valid" pos="10" rst="0">
          <comment>TSC X Value valid.</comment>
        </bits>
        <bits access="r" name="tsc_y_value_bit" pos="20:11" rst="0">
          <comment>TSC Y Value.</comment>
        </bits>
        <bits access="r" name="tsc_y_value_valid" pos="21" rst="0">
          <comment>TSC Y Value valid.</comment>
        </bits>
      </reg>
      <reg name="gpadc_data" protect="r">
        <bits access="r" name="gpadc_value_bit" pos="9:0" rst="0">
          <comment>GPADC Value.</comment>
        </bits>
        <bits access="r" name="gpadc_value_valid" pos="10" rst="0">
          <comment>GPADC Value valid.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="calendar.xml">
    <module category="System" name="CALENDAR">
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="interval" pos="1:0" rst="0">
          <options>
            <default/>
            <option name="DISABLE" value="0"/>
            <option name="PER SEC" value="1"/>
            <option name="PER MIN" value="2"/>
            <option name="PER HOUR" value="3"/>
          </options>
          <comment>These 2 bits configure the interval of generating an IRQ status.</comment>
        </bits>
      </reg>
      <reg name="cmd" protect="rw">
        <bits access="rs" name="calendar_load" pos="0" rst="0">
          <comment>
            When write, command to program calendar with a new value (sec, min, hour, day, month, year, day of week) previously written in registers Calendar_LoadVal_H and Calendar_LoadVal_L. This bit is auto cleared.
            <br/>
            '1' = load calendar timer.
            <br/>
            <br/>
            When read, Calendar timer load status.
            <br/>
            '1' = Calendar load has not finished.
            <br/>
            '0' = Calendar load has finished.
          </comment>
        </bits>
        <bits access="rs" name="alarm_load" pos="4" rst="0">
          <comment>
            When write, command to program alarm with a new value (sec, min, hour, day, month, year, day of week) prviously written in registers AlarmVal_H and AlarmVal_L. This bit is auto cleared.
            <br/>
            '1' = load alarm.
            <br/>
            <br/>
            When read, alarm load status.
            <br/>
            '1' = alarm load has not finished.
            <br/>
            '0' = alarm load has finished.
          </comment>
        </bits>
        <bits access="rs" name="alarm_enable_set" pos="5" rst="0">
          <comment>
            command to enable alarm. When alarm is triggered, it will generate a wakup.
            <br/>
            '1' = enable alarm.
            <br/>
            <br/>
            When read, alarm enable status.
            <br/>
            '1' = alarm enable operation is on going, not finished.
            <br/>
            '0' = alarm is enabled.
          </comment>
        </bits>
        <bits access="rc" name="alarm_enable_clr" pos="6" rst="0">
          <comment>
            command to disable alarm.
            <br/>
            '1' = disable alarm.
            <br/>
            <br/>
            When read, alarm enable status.
            <br/>
            '1' = alarm disable operation is on going, not finished.
            <br/>
            '0' = alarm is disabled.
          </comment>
        </bits>
        <bits access="rc" name="alarm_clr" pos="8" rst="0">
          <comment>
            writing '1', clear Alarm triggered signal (connect to wakeup) and alarm triggered IRQ.
            <br/>
            <br/>
            When read, get alarm clear status.
            <br/>
            '1' = alarm clear operation is on going, not finished.
            <br/>
            '0' = alarm is cleared.
          </comment>
        </bits>
        <bits access="c" name="itv_irq_clr" pos="9" rst="0">
          <comment>writing '1', clear interval IRQ.</comment>
        </bits>
        <bits access="rs" name="itv_irq_mask_set" pos="16" rst="0">
          <comment>
            When write '1', Set interval Irq Mask.
            <br/>
            When read, get interval Irq mask.
          </comment>
        </bits>
        <bits access="rc" name="itv_irq_mask_clr" pos="17" rst="0">
          <comment>
            When write '1', Clear interval Irq Mask.
            <br/>
            When read, get inteval Irq mask.
          </comment>
        </bits>
        <bits access="rs" name="calendar_not_valid" pos="31" rst="1">
          <comment>
            When write '1', mark calendar value to be not valid.
            <br/>
            <br/>
            When read, Indicate if the Calendar value is valid or not.
            <br/>
            The calendar value is not valid in case of mismatch between the calendar counter and the APB register,
                    which is the case of wakeup the phone after shut down. This mismatch disappear after one RTC cycle or
                    after re-porgramming a new calendar value.
            <br/>
            '1' = not valid.
          </comment>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="itv_irq_cause" pos="0" rst="0">
          <comment>Interval Irq Cause.</comment>
        </bits>
        <bits access="r" name="alarm_irq_cause" pos="1" rst="0">
          <comment>Alarm Irq Cause.</comment>
        </bits>
        <bits access="r" name="force_wakeup" pos="8" rst="0">
          <comment>
            Force Wakeup status. After set &quot;Force_Wakeup&quot; to '1' in sys_ctrl, the real
                 force_wakeup is not set immediatly, this bit indicates when the force wakeup is
                 really set. This bits also indicates if the interface between Calendar domain and
                 Core domain is enabled.
            <br/>
            '1': force wakeup set.
          </comment>
        </bits>
        <bits access="r" name="chg_mask" pos="12" rst="0">
          <comment>
            Charger Mask status. After set &quot;Chg_Mask&quot; to '1' in sys_ctrl, the real
                 Chg_Mask line is not set immediatly, this bit indicates when the Chg_Mask line is
                 really set.
            <br/>
            '1': Chg_Mask line set.
          </comment>
        </bits>
        <bits access="r" name="itv_irq_status" pos="16" rst="0">
          <comment>Interval Irq Status.</comment>
        </bits>
        <bits access="r" name="alarm_enable" pos="20" rst="0">
          <comment>
            Alarm Enable Status.
            <br/>
             Note: When calendar is not programmed, Alarm can be enabled or not.
            <br/>
             It is suggested to clear Alarm Enable when program RTC.
          </comment>
        </bits>
        <bits access="r" name="calendar_not_prog" pos="31" rst="0">
          <comment>
            '1' = Calendar has not been programmed.
            <br/>
            This bit keep value '0' after the calendar is programmed once.
          </comment>
        </bits>
      </reg>
      <reg name="calendar_loadval_l" protect="rw">
        <bits access="rw" name="sec" pos="5:0" rst="-">
          <comment>Second value loaded to calendar, ranged from 0 to 59.</comment>
        </bits>
        <bits access="rw" name="min" pos="13:8" rst="-">
          <comment>Minute value loaded to calendar, ranged from 0 to 59.</comment>
        </bits>
        <bits access="rw" name="hour" pos="20:16" rst="-">
          <comment>Hour value loaded to calendar, ranged from 0 to 23.</comment>
        </bits>
      </reg>
      <reg name="calendar_loadval_h" protect="rw">
        <bits access="rw" name="day" pos="4:0" rst="-">
          <comment>Day value loaded to calendar, ranged from 1 to 31.</comment>
        </bits>
        <bits access="rw" name="mon" pos="11:8" rst="-">
          <comment>Month value loaded to calendar, ranged from 1 to 12.</comment>
        </bits>
        <bits access="rw" name="year" pos="22:16" rst="-">
          <comment>
            Year value loaded to calendar, ranged from 0 to 127.
            <br/>
            Represent year 2000 to 2127.
          </comment>
        </bits>
        <bits access="rw" name="weekday" pos="26:24" rst="-">
          <comment>
            Day of the week value loaded to calendar, ranged from 1 to 7.
            <br/>
            Represent Monday, Tuesday etc.
          </comment>
        </bits>
      </reg>
      <reg name="calendar_curval_l" protect="r">
        <bits access="r" name="sec" pos="5:0" rst="-">
          <comment>Current Second value of calendar, ranged from 0 to 59.</comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="r" name="min" pos="13:8" rst="-">
          <comment>Current Minute value of calendar, ranged from 0 to 59.</comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="r" name="hour" pos="20:16" rst="-">
          <comment>Current Hour value of calendar, ranged from 0 to 23.</comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="calendar_curval_h" protect="r">
        <bits access="r" name="day" pos="4:0" rst="-">
          <comment>
            Current Day value of calendar, ranged from 1 to 31.
            <br/>
            Maximum number of days in each month are stored in the module,
                and leap year is supported, so February can have 28 or 29 days.
          </comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="r" name="mon" pos="11:8" rst="-">
          <comment>Current Month value of calendar, ranged from 1 to 12.</comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="r" name="year" pos="22:16" rst="-">
          <comment>
            Current Year value of calendar, ranged from 0 to 127.
            <br/>
            Represent year 2000 to 2127.
          </comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="r" name="weekday" pos="26:24" rst="-">
          <comment>
            Current Day of the week value of calendar, ranged from 1 to 7.
            <br/>
            Represent Monday, Tuesday etc.
          </comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="alarmval_l" protect="rw">
        <bits access="rw" name="sec" pos="5:0" rst="-">
          <comment>Second value loaded to alarm, ranged from 0 to 59.</comment>
        </bits>
        <bits access="rw" name="min" pos="13:8" rst="-">
          <comment>Minute value loaded to alarm, ranged from 0 to 59.</comment>
        </bits>
        <bits access="rw" name="hour" pos="20:16" rst="-">
          <comment>Hour value loaded to alarm, ranged from 0 to 23.</comment>
        </bits>
      </reg>
      <reg name="alarmval_h" protect="rw">
        <bits access="rw" name="day" pos="4:0" rst="-">
          <comment>Day value loaded to alarm, ranged from 1 to 31.</comment>
        </bits>
        <bits access="rw" name="mon" pos="11:8" rst="-">
          <comment>Month value loaded to alarm, ranged from 1 to 12.</comment>
        </bits>
        <bits access="rw" name="year" pos="22:16" rst="-">
          <comment>
            Year value loaded to alarm, ranged from 0 to 127.
            <br/>
            Represent year 2000 to 2127.
          </comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="aif.xml">
    <module category="System" name="AIF">
      <enum name="AIF_Sampling_Rate">
        <entry name="AIF_8k"/>
        <entry name="AIF_11k025"/>
        <entry name="AIF_12k"/>
        <entry name="AIF_16k"/>
        <entry name="AIF_22k05"/>
        <entry name="AIF_24k"/>
        <entry name="AIF_32k"/>
        <entry name="AIF_44k1"/>
        <entry name="AIF_48k"/>
      </enum>
      <var name="AIF_RX_FIFO_SIZE" value="8"/>
      <var name="AIF_TX_FIFO_SIZE" value="8"/>
      <reg name="data" protect="w">
        <bits access="rw" name="data0" pos="15:0" rst="-">
          <comment>This reg contains data to be read or written by IFC.
            In mono mode, data0 is before data1.
            In stereo mode, data0 is in left channel.</comment>
        </bits>
        <bits access="rw" name="data1" pos="31:16" rst="-">
          <comment>This reg contains data to be read or written by IFC.
            In mono mode, data1 is after data0.
            In stereo mode, data1 is in right channel.</comment>
        </bits>
      </reg>
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="enable" pos="0" rst="0">
          <options>
            <default/>
            <option name="ENABLE" value="1"/>
            <option name="DISABLE" value="0"/>
          </options>
          <comment>
            Audio Interface Enable.
            <br/>
             0: if AIF_Tone[0] is also 0, AIF is disabled.
            <br/>
             1 = AIF Enabled. If AIF_Tone[0] is also '1', Tx fifo continue to fetch and distribute data
                   from IFC when tone is enable. However, these data are not used.
          </comment>
        </bits>
        <bits access="rw" name="tx off" pos="4" rst="0">
          <options>
            <default/>
            <option name="Tx On" value="0"/>
            <option name="Tx Off" value="1"/>
          </options>
          <comment>
            Disable AIF Tx functions. Important: if you want to do record only, you must set this bit otherwise AIF state machine will not start.
            <br/>
             0 = Both Tx Rx enabled.
            <br/>
             1 = Rx enabled only, Tx disabled.
          </comment>
        </bits>
        <bits access="rs" name="parallel out set" pos="8" rst="0">
          <options>
            <default/>
            <option name="SERL" value="0"/>
            <option name="PARA" value="1"/>
          </options>
          <comment>
            Selects parallel audio interface connected to analog front-end.
            <br/>
             0 = serial output.
            <br/>
             1 = parallel output.
          </comment>
        </bits>
        <bits access="rc" name="parallel out clr" pos="9" rst="0">
          <options>
            <default/>
            <option name="SERL" value="0"/>
            <option name="PARA" value="1"/>
          </options>
          <comment>
            Selects parallel audio interface connected to analog front-end.
            <br/>
             0 = serial output.
            <br/>
             1 = parallel output.
          </comment>
        </bits>
        <bits access="rs" name="parallel in set" pos="10" rst="0">
          <options>
            <default/>
            <option name="SERL" value="0"/>
            <option name="PARA" value="1"/>
          </options>
          <comment>
            Selects parallel audio interface connected to analog front-end.
            <br/>
             0 = serial input.
            <br/>
             1 = parallel input.
          </comment>
        </bits>
        <bits access="rc" name="parallel in clr" pos="11" rst="0">
          <options>
            <default/>
            <option name="SERL" value="0"/>
            <option name="PARA" value="1"/>
          </options>
          <comment>
            Selects parallel audio interface connected to analog front-end.
            <br/>
             0 = serial input.
            <br/>
             1 = parallel input.
          </comment>
        </bits>
        <bits access="rw" name="tx stb mode" pos="12" rst="0">
          <comment>
            In parallel mode, select AIF Tx Strobe mode. Reserved in serial mode.
            <br/>
             0 = Tx STB edge is in middle of data.
            <br/>
             1 = Tx STB edge is aligned to data edge.
          </comment>
        </bits>
        <bits access="rc" name="out underflow" pos="16" rst="0">
          <comment>
            This bit indicates if the AIF had needed some data while the Out Fifo was empty.
            In case of data famine, the last available data will be sent again.
            <br/>
             Write one to clear the out_underflow status bit. This bit is auto clear.
          </comment>
        </bits>
        <bits access="rc" name="in overflow" pos="17" rst="0">
          <comment>
            This bit indicates if the AIF had received some data while the Input Fifo was full.
            If the Fifo In is full, the newly received data will be lost.
            <br/>
             Write one to clear the in_overflow status bit. This bit is auto clear.
          </comment>
        </bits>
        <bits access="rw" name="loop back" pos="31" rst="0">
          <options>
            <default/>
            <option name="NORMAL" value="0"/>
            <option name="LOOPBACK" value="1"/>
          </options>
          <comment>Sets the loop back mode. The feature is for debug only and can not work in DAI mode.</comment>
        </bits>
      </reg>
      <reg name="serial_ctrl" protect="rw">
        <bits access="rw" name="serial mode" pos="1:0" rst="00">
          <options>
            <default/>
            <option name="I2S_PCM" value="0"/>
            <option name="VOICE" value="1"/>
            <option name="DAI" value="2"/>
          </options>
          <comment>
            Configure serial AIF mode. &quot;11&quot; is reserved.
            <br/>
            <br/>
             When mode is set DAI, the bit Master Mode should be set to '1',
            bit Endian_L set to '0'. Data should be sent out on falling edge, which
            requires either Bclk_Pol = '0' and Half_Cycle_DLY = '1' or Bclk_Pol = '1'
            and Half_Cycle_DLY = '0'. Bits Tx_DLY and BCKOut_Gate must be configured
            to '0' and '1'.
            <br/>
             The DAI mode must NOT be modified after AIF is enabled.
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="i2s in sel" pos="3:2" rst="0">
          <options>
            <default/>
            <option name="I2S IN 0" value="0"/>
            <option name="I2S IN 1" value="1"/>
            <option name="I2S IN 2" value="2"/>
          </options>
          <comment>Select AIF I2S input.</comment>
        </bits>
        <bits access="rw" name="master mode" pos="4" rst="1">
          <options>
            <default/>
            <option name="SLAVE" value="0"/>
            <option name="MASTER" value="1"/>
          </options>
          <comment>configure AIF works in master mode (LRCLK and BCK timing signals are generated internally)
            or slave mode (LRCLK and BCK timing signals are generated externally).</comment>
        </bits>
        <bits access="rw" name="lsb" pos="5" rst="0">
          <options>
            <default/>
            <option name="MSB" value="0"/>
            <option name="LSB" value="1"/>
          </options>
          <comment>When high, the output data format is with the least significant bit first.</comment>
        </bits>
        <bits access="rw" name="lrck pol" pos="6" rst="0">
          <options>
            <default/>
            <option name="LEFT_H_RIGHT_L" value="0"/>
            <option name="LEFT_L_RIGHT_H" value="1"/>
          </options>
          <comment>
            configure LRCK polarity.
            <br/>
             0 = high level on LRCK means left channel, low level on LRCK means right channel.
            <br/>
             1 = high level on LRCK means right channel, low level on LRCK means left channel.
            <br/>
            <br/>
             Note: this bit should be set to '0' (LEFT_H_RIGHT_L) in voice mode.
          </comment>
        </bits>
        <bits access="rw" name="lr justified" pos="7" rst="0">
          <options>
        </options>
          <comment>.</comment>
        </bits>
        <bits access="rw" name="rx_dly" pos="9:8" rst="0">
          <options>
            <default/>
            <option name="ALIGN" value="0"/>
            <option name="DLY_1" value="1"/>
            <option name="DLY_2" value="2"/>
            <option name="DLY_3" value="3"/>
          </options>
          <comment>
            Indicates the delay between serial data in MSB and LRCK edge.
            <br/>
             &quot;00&quot; = Digital audio in MSB is aligned with LRCLK edge.
            <br/>
             &quot;01&quot; = Digital audio in MSB is 1 cycle delayed to LRCLK edge.
            <br/>
             &quot;10&quot; = Digital audio in MSB is 2 cycle delayed to LRCLK edge.
            <br/>
             &quot;11&quot; = Digital audio in MSB is 3 cycle delayed to LRCLK edge.
          </comment>
        </bits>
        <bits access="rw" name="tx_dly" pos="10" rst="0">
          <options>
            <default/>
            <option name="ALIGN" value="0"/>
            <option name="DLY_1" value="1"/>
          </options>
          <comment>
            configure the delay between serial data out MSB and LRCK edge.
            <br/>
             &quot;0&quot; = Digital audio out MSB is aligned with LRCLK edge.
            <br/>
             &quot;1&quot; = Digital audio out MSB is 1 cycle delayed to LRCLK edge.
          </comment>
        </bits>
        <bits access="rw" name="tx_dly_s" pos="11" rst="0">
          <options>
            <default/>
            <option name="NO DLY" value="0"/>
            <option name="DLY" value="1"/>
          </options>
          <comment>
            ONLY for slave mode: configure 1 cycle supplementary Tx delay.
            <br/>
             &quot;0&quot; = No supplementary Tx delay.
            <br/>
             &quot;1&quot; = One Cycle supplementary Tx delay.
          </comment>
        </bits>
        <bits access="rw" name="tx_mode" pos="13:12" rst="0">
          <options>
            <default/>
            <option name="STEREO_STEREO" value="0"/>
            <option name="MONO_STEREO_CHAN_L" value="1"/>
            <option name="MONO_STEREO_DUPLI" value="2"/>
            <option name="STEREO_TO_MONO" value="3"/>
          </options>
          <comment>
            Configure mono or stereo format for Audio data out.
                  This field is used both in serial mode or in parallel EXT mode.
            <br/>
             &quot;00&quot; = stereo input from IFC, stereo output to pin.
            <br/>
             &quot;01&quot; = mono input from IFC, stereo output in left channel to pin.
                          This value is reserved in parallel EXT mode.
            <br/>
             &quot;10&quot; = mono input from IFC, stereo output duplicate in both channels to pin.
            <br/>
             &quot;11&quot; = stereo input from IFC, mono output to left and right channel. This mode is only used for parallel stereo interface.
            <br/>
            <br/>
             if AIF works in DAI or Voice mode, always select &quot;00&quot; mode STEREO_STEREO.
          </comment>
        </bits>
        <bits access="rw" name="rx mode" pos="14" rst="0">
          <options>
            <default/>
            <option name="STEREO_STEREO" value="0"/>
            <option name="STEREO_MONO_FROM_L" value="1"/>
          </options>
          <comment>
            Configure mono or stereo format for Audio data in.
            <br/>
             0 = stereo input from pin, stereo output to IFC.
            <br/>
             1 = stereo input from pin, mono input to IFC selected from left channel.
            <br/>
            <br/>
             Users can change LRCK polarity to choose mono input from right channel.
          </comment>
        </bits>
        <bits access="rw" name="bck lrck" pos="20:16" rst="0">
          <options>
            <default/>
            <option name="BCK LRCK 16" value="0"/>
            <option name="BCK LRCK 17" value="1"/>
            <option name="BCK LRCK 18" value="2"/>
            <option name="BCK LRCK 19" value="3"/>
            <option name="BCK LRCK 20" value="4"/>
            <option name="BCK LRCK 21" value="5"/>
            <option name="BCK LRCK 22" value="6"/>
            <option name="BCK LRCK 23" value="7"/>
            <option name="BCK LRCK 24" value="8"/>
            <option name="BCK LRCK 25" value="9"/>
            <option name="BCK LRCK 26" value="10"/>
            <option name="BCK LRCK 27" value="11"/>
            <option name="BCK LRCK 28" value="12"/>
            <option name="BCK LRCK 29" value="13"/>
            <option name="BCK LRCK 30" value="14"/>
            <option name="BCK LRCK 31" value="15"/>
            <option name="BCK LRCK 32" value="16"/>
            <option name="BCK LRCK 33" value="17"/>
            <option name="BCK LRCK 34" value="18"/>
            <option name="BCK LRCK 35" value="19"/>
            <option name="BCK LRCK 36" value="20"/>
            <option name="BCK LRCK 37" value="21"/>
            <option name="BCK LRCK 38" value="22"/>
            <option name="BCK LRCK 39" value="23"/>
            <option name="BCK LRCK 40" value="24"/>
            <option name="BCK LRCK 41" value="25"/>
            <option name="BCK LRCK 42" value="26"/>
            <option name="BCK LRCK 43" value="27"/>
            <option name="BCK LRCK 44" value="28"/>
            <option name="BCK LRCK 45" value="29"/>
            <option name="BCK LRCK 46" value="30"/>
            <option name="BCK LRCK 47" value="31"/>
          </options>
          <comment>
            configure the ratio of BCK and LRCK cycle from 16 to 31.
            <br/>
             Voice_Mode: &quot;XXXX&quot;: each sample takes 16 + &quot;XXXX&quot; BCLK cycle.
            <br/>
             Audio_Mode: &quot;XXXX&quot;: each sample takes 2*(16 + &quot;XXXX) BCLK cycle. 2 times than Voice Mode because in audio mode each sample occupies two channels.
          </comment>
        </bits>
        <bits access="rw" name="bck pol" pos="24" rst="0">
          <options>
            <default/>
            <option name="NORMAL" value="0"/>
            <option name="INVERT" value="1"/>
          </options>
          <comment>if Master Mode, invert BCLK out. if slave Mode, invert BCLK in.</comment>
        </bits>
        <bits access="rw" name="output half cycle dly" pos="25" rst="0">
          <options>
            <default/>
            <option name="NO DLY" value="0"/>
            <option name="DLY" value="1"/>
          </options>
          <comment>delayed Audio output data or LRCK by half cycle.</comment>
        </bits>
        <bits access="rw" name="input half cycle dly" pos="26" rst="0">
          <options>
            <default/>
            <option name="NO DLY" value="0"/>
            <option name="DLY" value="1"/>
          </options>
          <comment>delayed Audio input data by half cycle.</comment>
        </bits>
        <bits access="rw" name="bckout gate" pos="28" rst="0">
          <options>
            <default/>
            <option name="NO GATE" value="0"/>
            <option name="GATED" value="1"/>
          </options>
          <comment>Sets the BckOut gating. This bit decide if AIF continue to output BCK clock after 16-bit data has been sent.</comment>
        </bits>
      </reg>
      <reg name="tone" protect="rw">
        <bits access="rw" name="enable h" pos="0" rst="0">
          <options>
            <default/>
            <option name="DISABLE" value="0"/>
            <option name="ENABLE" value="1"/>
          </options>
          <comment>
            When this bit is set, the audio interface is enabled and a comfort tone or DTMF tone is output
            on the audio interface instead of the regular data, even if the AIF_CTRL[0] enable bit is 0.
            <br/>
             0 = AIF is disabled if the AIF_CTRL[0] is also 0.
            <br/>
             1 = AIF is enabled and generates a tone.
          </comment>
        </bits>
        <bits access="rw" name="tone select" pos="1" rst="0">
          <options>
            <default/>
            <option name="DTMF" value="0"/>
            <option name="COMFORT TONE" value="1"/>
          </options>
          <comment>Select whether a DTMF of a comfort tone is generated.</comment>
        </bits>
        <bits access="rw" name="dtmf freq col" pos="5:4" rst="0">
          <options>
            <default/>
            <option name="1209 Hz" value="0"/>
            <option name="1336 Hz" value="1"/>
            <option name="1477 Hz" value="2"/>
            <option name="1633 Hz" value="3"/>
          </options>
          <comment>Frequency of the first DTMF sine wave.</comment>
        </bits>
        <bits access="rw" name="dtmf freq row" pos="7:6" rst="0">
          <options>
            <default/>
            <option name="697 Hz" value="0"/>
            <option name="770 Hz" value="1"/>
            <option name="852 Hz" value="2"/>
            <option name="941 Hz" value="3"/>
          </options>
          <comment>Frequency of the second DTMF sine wave.</comment>
        </bits>
        <bits access="rw" name="comfort freq" pos="9:8" rst="0">
          <options>
            <default/>
            <option name="425 Hz" value="0"/>
            <option name="950 Hz" value="1"/>
            <option name="1400 Hz" value="2"/>
            <option name="1800 Hz" value="3"/>
          </options>
          <comment>Frequency of comfort tone.</comment>
        </bits>
        <bits access="rw" name="tone gain" pos="13:12" rst="0">
          <comment>Tone attenuation. The Comfort Tone or DTMF is attenuated according to this programmable gain.</comment>
          <options>
            <default/>
            <option name="0 dB" value="0"/>
            <option name="m3 dB" value="1"/>
            <option name="m9 dB" value="2"/>
            <option name="m15 dB" value="3"/>
          </options>
        </bits>
      </reg>
      <reg name="side_tone" protect="rw">
        <bits access="rw" name="side tone gain" pos="3:0" rst="0">
          <comment>
            Side Tone attenuation. The side tone is attenuated according to this programmable gain.
            <br/>
             0000 = mute.
            <br/>
             0001 = -36 dB.
            <br/>
             0010 = -33 dB.
            <br/>
             0011 = -30 dB.
            <br/>
             0100 = -27 dB.
            <br/>
             0101 = -24 dB.
            <br/>
             0110 = -21 dB.
            <br/>
             0111 = -18 dB.
            <br/>
             1000 = -15 dB.
            <br/>
             1001 = -12 dB.
            <br/>
             1010 = -9 dB.
            <br/>
             1011 = -6 dB.
            <br/>
             1100 = -3 dB.
            <br/>
             1101 = 0 dB.
            <br/>
             1110 = +3 dB.
            <br/>
             1111 = +6 dB.
          </comment>
        </bits>
      </reg>
      <reg name="rx_load_pos" protect="rw">
        <bits access="rw" name="rx load position" pos="3:0" rst="0">
          <comment>set rx load position delay, the range is 0 to 15.</comment>
        </bits>
      </reg>
      <reg name="fm_record_ctrl" protect="rw">
        <bits access="rw" name="record_en" pos="0" rst="0">
          <comment>&quot;1&quot; enable fm record.</comment>
        </bits>
        <bits access="rw" name="lr_swap" pos="4" rst="0">
          <comment>&quot;1&quot; swap fm left and right channel.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="aud_2ad.xml">
    <module category="Periph" name="AUD_2AD">
      <reg name="aud_top_ctl" protect="rw">
        <bits access="rw" name="adc1_sinc_in_sel" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="adc1_iis_sel" pos="13:12" rst="0">
      </bits>
        <bits access="rw" name="adc1_en_r" pos="11" rst="0">
      </bits>
        <bits access="rw" name="adc1_en_l" pos="10" rst="0">
      </bits>
        <bits access="rw" name="adc_sinc_in_sel" pos="9:8" rst="0">
          <comment>[9:8]=='b00: select adc input data  ;
                   [9:8]=='b01: select dac output loop data ;
                   [9:8]=='b1x: force to zero ;</comment>
        </bits>
        <bits access="rw" name="adc_iis_sel" pos="7:6" rst="0">
          <comment>[6]==0: fm input to aif1; [6]=1: audio codec input to aif1;
                   [7]==0: fm input to aif2; [7]=1: audio codec input to aif2;</comment>
        </bits>
        <bits access="rw" name="dac_iis_sel" pos="5:4" rst="0">
          <comment>[5:4]=='bx1: aif1 output to audio codec ;
                   [5:4]=='b10: aif2 output to audio codec ;
                   [5:4]=='b00: zero output to audio codec ;</comment>
        </bits>
        <bits access="rw" name="adc_en_r" pos="3" rst="0">
          <comment>==1: enable adc left channel;</comment>
        </bits>
        <bits access="rw" name="dac_en_r" pos="2" rst="0">
          <comment>==1: enable dac right channel;</comment>
        </bits>
        <bits access="rw" name="adc_en_l" pos="1" rst="0">
          <comment>==1: enable adc left channel;</comment>
        </bits>
        <bits access="rw" name="dac_en_l" pos="0" rst="0">
          <comment>==1: enable adc right channel;</comment>
        </bits>
      </reg>
      <reg name="aud_clr" protect="rw">
        <bits access="w" name="adc_clr" pos="2" rst="0">
      </bits>
        <bits access="w" name="dac_clr" pos="1" rst="0">
      </bits>
        <bits access="w" name="adc1_clr" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="aud_iis_ctl" protect="rw">
        <bits access="rw" name="adc_iis_ckgate_en" pos="15" rst="0">
      </bits>
        <bits access="rw" name="dac_iis_ckgate_en" pos="14" rst="0">
      </bits>
        <bits access="rw" name="adc_bclk_pol" pos="13" rst="0">
      </bits>
        <bits access="rw" name="dac_bclk_pol" pos="12" rst="0">
      </bits>
        <bits access="rw" name="dac_sample_phase_sel" pos="11" rst="0">
      </bits>
        <bits access="rw" name="adc_iowl" pos="10:9" rst="3">
      </bits>
        <bits access="rw" name="dac_iowl" pos="8:7" rst="3">
      </bits>
        <bits access="rw" name="adc_io_mode" pos="6:5" rst="0">
      </bits>
        <bits access="rw" name="dac_io_mode" pos="4:3" rst="0">
      </bits>
        <bits access="rw" name="adc_lr_sel" pos="2" rst="0">
      </bits>
        <bits access="rw" name="dac_lr_sel" pos="1" rst="0">
      </bits>
        <bits access="rw" name="iis_clkdiv_mode" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="dac_src_ctl" protect="rw">
        <bits access="rw" name="dac_mute_en" pos="15" rst="1">
          <comment>==1: enable mute;</comment>
        </bits>
        <bits access="rw" name="dac_mute_ctl" pos="14" rst="0">
          <comment>==1: enable soft mute;</comment>
        </bits>
        <bits access="rw" name="dac_mute_div_ctl1" pos="13:10" rst="0">
          <comment>dac mute counter1 threshold, step is countrolled by counter 0;</comment>
        </bits>
        <bits access="rw" name="dac_mute_div_ctl0" pos="9:4" rst="63">
          <comment>dac mute counter0 threshold</comment>
        </bits>
        <bits access="rw" name="dac_fs_mode" pos="3:0" rst="4">
          <comment>dac fs frequency
            0:96K
            1:48K
            2:44.1K
            3:32K
            4:24K
            5:22.05K
            6:16K
            7:12K
            8:11.025K
            9:9.6K
            10:8K</comment>
        </bits>
      </reg>
      <reg name="dac_sdm_ctl0" protect="rw">
        <bits access="rw" name="dac_sdm_dolvl" pos="11:8" rst="1">
      </bits>
        <bits access="rw" name="dac_sdm_dilvl" pos="7:4" rst="0">
      </bits>
        <bits access="rw" name="dac_sdm_do" pos="3:2" rst="0">
      </bits>
        <bits access="rw" name="dac_sdm_di" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="dac_sdm_ctl1" protect="rw">
        <bits access="rw" name="dac_sdm_soft_rst_r" pos="9" rst="0">
      </bits>
        <bits access="rw" name="dac_sdm_soft_rst_l" pos="8" rst="0">
      </bits>
        <bits access="rw" name="dac_sdm_test" pos="7:0" rst="8">
      </bits>
      </reg>
      <reg name="adc_src_ctl" protect="rw">
        <bits access="rw" name="adc1_src_n" pos="7:4" rst="0">
      </bits>
        <bits access="rw" name="adc_src_n" pos="3:0" rst="0">
          <comment>adc src upsample tap, sample rate=N*4K</comment>
        </bits>
      </reg>
      <reg name="aud_loop_test" protect="rw">
        <bits access="rw" name="loop_adc_path_sel" pos="9" rst="0">
      </bits>
        <bits access="rw" name="loop_fifo_ae_lvl" pos="8:6" rst="4">
      </bits>
        <bits access="rw" name="loop_fifo_af_lvl" pos="5:3" rst="4">
      </bits>
        <bits access="rw" name="loop_path_sel" pos="2:1" rst="0">
      </bits>
        <bits access="rw" name="aud_loop_test" pos="0" rst="0">
          <comment>==1: enable audio adc parallel data loop to dac parallel data path;</comment>
        </bits>
      </reg>
      <reg name="aud_sts0" protect="r">
        <bits access="r" name="aud_int_mask" pos="5:4" rst="0">
      </bits>
        <bits access="r" name="aud_int_raw" pos="3:2" rst="0">
      </bits>
        <bits access="r" name="st_mute" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="aud_int_clr" protect="rw">
        <bits access="rw" name="aud_int_clr" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="aud_int_en" protect="rw">
        <bits access="rw" name="aud_int_en" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="audif_fifo_ctl" protect="rw">
        <bits access="rw" name="adc_fifo_af_lvl" pos="2:0" rst="3">
      </bits>
      </reg>
      <reg name="aud_dmic_ctl" protect="rw">
        <bits access="rw" name="adc1_dmic_en" pos="7" rst="0">
      </bits>
        <bits access="rw" name="clk_aud_26m_sel" pos="6" rst="0">
          <comment>==0: force to 0 to select 26m audio clock;</comment>
        </bits>
        <bits access="rw" name="adc1_dmic_lr_sel" pos="5" rst="0">
      </bits>
        <bits access="rw" name="adc1_dmic_clk_mode" pos="4:3" rst="0">
      </bits>
        <bits access="rw" name="clk_aud_26m_inv" pos="2" rst="0">
          <comment>==1: invert output mclk ;</comment>
        </bits>
        <bits access="rw" name="adc_dmic_clk_mode" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="adc1_iis_ctl" protect="rw">
        <bits access="rw" name="adc1_iis_ckgate_en" pos="6" rst="0">
      </bits>
        <bits access="rw" name="adc1_bclk_pol" pos="5" rst="0">
      </bits>
        <bits access="rw" name="adc1_iowl" pos="4:3" rst="3">
      </bits>
        <bits access="rw" name="adc1_io_mode" pos="2:1" rst="0">
      </bits>
        <bits access="rw" name="adc1_lr_sel" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="dac_sdm_dc_l" protect="rw">
        <bits access="rw" name="dac_sdm_dc_l" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="dac_sdm_dc_h" protect="rw">
        <bits access="rw" name="dac_sdm_dc_h" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="audif_ctl0" protect="rw">
        <bits access="rw" name="audif_5p_mode" pos="6" rst="0">
      </bits>
        <bits access="rw" name="ad_sync_sel" pos="5:3" rst="0">
      </bits>
        <bits access="rw" name="adc_fifo_af_lvl_r" pos="2:0" rst="1">
      </bits>
      </reg>
      <reg name="audif_adc_fifo_sts" protect="r">
        <bits access="r" name="audif_adc_fifo_af_r" pos="10" rst="0">
      </bits>
        <bits access="r" name="audif_adc_fifo_empty_r" pos="9" rst="0">
      </bits>
        <bits access="r" name="audif_adc_fifo_full_r" pos="8" rst="0">
      </bits>
        <bits access="r" name="audif_adc_fifo_raddr_r" pos="7:4" rst="0">
      </bits>
        <bits access="r" name="audif_adc_fifo_waddr_r" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="audif_dac_fifo_sts" protect="r">
        <bits access="r" name="audif_dac_fifo_empty" pos="9" rst="0">
      </bits>
        <bits access="r" name="audif_dac_fifo_full" pos="8" rst="0">
      </bits>
        <bits access="r" name="audif_dac_fifo_addr_r" pos="7:4" rst="0">
      </bits>
        <bits access="r" name="audif_dac_fifo_addr_w" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="audif_sts" protect="r">
        <bits access="r" name="audif_adc_rx_data_ready" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="audif_sts_raw" protect="r">
        <bits access="r" name="audif_adc_fifo_underfl_raw" pos="1" rst="0">
      </bits>
        <bits access="r" name="audif_dac_fifo_ovfl_raw" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="audif_sts_clr" protect="rw">
        <bits access="rw" name="ovfl_sts_clr" pos="1" rst="0">
      </bits>
        <bits access="rw" name="underfl_sts_clr" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="dac_src_step" protect="rw">
        <bits access="rw" name="dac_src_step" pos="11:0" rst="0">
      </bits>
      </reg>
      <reg name="adc_dgain" protect="rw">
        <bits access="rw" name="adc_l_dgain" pos="3:0" rst="0">
          <comment>left adc channel dgain
            4'hf: 16dB
            4'he: 14dB
            4'hd: 12dB
            4'hc: 10dB
            4'hb:  8dB
            4'ha:  6dB
            4'h9:  4dB
            4'h8:  2dB
            4'h7:  0dB
            4'h6:-2dB
            4'h5:-4dB
            4'h4:-6dB
            4'h3:-8dB
            4'h2:-10dB
            4'h1:-12dB
            4'h0:mute</comment>
        </bits>
        <bits access="rw" name="adc_r_dgain" pos="7:4" rst="0">
          <comment>right adc channel dgain
            4'hf: 16dB
            4'he: 14dB
            4'hd: 12dB
            4'hc: 10dB
            4'hb:  8dB
            4'ha:  6dB
            4'h9:  4dB
            4'h8:  2dB
            4'h7:  0dB
            4'h6:-2dB
            4'h5:-4dB
            4'h4:-6dB
            4'h3:-8dB
            4'h2:-10dB
            4'h1:-12dB
            4'h0:mute</comment>
        </bits>
        <bits access="rw" name="adc_dgain_update" pos="8" rst="0">
      </bits>
      </reg>
      <reg name="dac_dgain0" protect="rw">
        <bits access="rw" name="dac_dgain_tone_sel" pos="0" rst="0">
          <comment>right adc channel dgain
            1:sel tone dac tone dgain
            0:sel normal dac dgain</comment>
        </bits>
        <bits access="rw" name="dac_dgain_update" pos="1" rst="0">
      </bits>
      </reg>
      <reg name="dac_dgain1" protect="rw">
        <bits access="rw" name="dac_l_nor_dgain" pos="7:0" rst="0x34">
          <comment>left dac channel dgain
            [5:1] =
            5'h1f:  05dB
            5'h1e:  04dB
            5'h1d:  03dB
            5'h1c:  02dB
            5'h1b:  01dB
            5'h1a:  00dB
            5'h19: -01dB
            5'h18: -02dB
            5'h17: -03dB
            5'h16: -04dB
            5'h15: -05dB
            5'h14: -06dB
            5'h13: -07dB
            5'h12: -08dB
            5'h11: -09dB
            5'h10: -10dB
            5'h0f: -11dB
            5'h0e: -12dB
            5'h0d: -13dB
            5'h0c: -14dB
            5'h0b: -15dB
            5'h0a: -16dB
            5'h09: -17dB
            5'h08: -18dB
            5'h07: -19dB
            5'h06: -20dB
            5'h05: -21dB
            5'h04: -22dB
            5'h03: -23dB
            5'h02: -24dB
            5'h01: -25dB
            5'h00: -26dB
            [0]:1'b1,+0.5dB
            [7]:1'b1,+12dB
            [6]:1'b1,+6dB</comment>
        </bits>
        <bits access="rw" name="dac_r_nor_dgain" pos="15:8" rst="0x34">
          <comment>right dac channel dgain
            detail see  dac_l_nor_dgain[7:0]</comment>
        </bits>
      </reg>
      <reg name="dac_dgain2" protect="rw">
        <bits access="rw" name="dac_l_tone_dgain" pos="7:0" rst="0x34">
          <comment>left dac channel dgain
            detail see  dac_l_nor_dgain[7:0]</comment>
        </bits>
        <bits access="rw" name="dac_r_tone_dgain" pos="15:8" rst="0x34">
          <comment>right dac channel dgain
            detail see  dac_l_nor_dgain[7:0]</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="usbc.xml">
    <module category="System" name="USBC">
      <reg name="gotgctl" protect="rw">
        <comment>OTG Control and Status Register
The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the controller.</comment>
        <bits access="r" name="sesreqscs" pos="0" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Session Request Success (SesReqScs)</br>
            <br>The core sets this bit when a session request initiation is successful.</br>
            <br> - 1'b0: Session request failure</br>
            <br> - 1'b1: Session request success</br>
          </comment>
        </bits>
        <bits access="rw" name="sesreq" pos="1" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Session Request (SesReq)</br>
            <br>The application sets this bit to initiate a session request on the USB. The application can clear this bit by writing a 0 when the Host Negotiation Success Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET. The core clears this bit when the HstNegSucStsChng bit is cleared.</br>
            <br>If you use the USB 1.1 Full-Speed Serial Transceiver interface to initiate the session request, the application must wait until the VBUS discharges to 0.2 V, after the B-Session Valid bit in this register (GOTGCTL.BSesVld) is cleared. This discharge time varies between different PHYs and can be obtained from the PHY vendor.</br>
            <br> - 1'b0: No session request</br>
            <br> - 1'b1: Session request</br>
          </comment>
        </bits>
        <bits access="rw" name="vbvalidoven" pos="2" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>VBUS Valid Override Enable (VbvalidOvEn)</br>
            <br>This bit is used to enable/disable the software to override the Bvalid signal using the GOTGCTL.VbvalidOvVal.</br>
            <br> - 1'b1 : Internally Bvalid received from the PHY is overridden with GOTGCTL.VbvalidOvVal.</br>
            <br> - 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is used internally by the controller.</br>
          </comment>
        </bits>
        <bits access="rw" name="vbvalidovval" pos="3" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>VBUS Valid OverrideValue (VbvalidOvVal)</br>
            <br>This bit is used to set Override value for vbusvalid signal when GOTGCTL.VbvalidOvEn is set.</br>
            <br> - 1'b0 : vbusvalid value is 1'b0 when GOTGCTL.VbvalidOvEn =1</br>
            <br> - 1'b1 : vbusvalid value is 1'b1 when GOTGCTL.VbvalidOvEn =1</br>
          </comment>
        </bits>
        <bits access="rw" name="avalidoven" pos="4" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>A-Peripheral Session Valid Override Enable (AvalidOvEn)</br>
            <br>This bit is used to enable/disable the software to override the Avalid signal using the GOTGCTL.AvalidOvVal.</br>
            <br> - 1'b1: Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVal.</br>
            <br> - 1'b0: Override is disabled and avalid signal from the respective PHY selected is used internally by the core</br>
          </comment>
        </bits>
        <bits access="rw" name="avalidovval" pos="5" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>A-Peripheral Session Valid OverrideValue (AvalidOvVal)</br>
            <br>This bit is used to set Override value for Avalid signal when GOTGCTL.AvalidOvEn is set.</br>
            <br> - 1'b0 : Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1</br>
            <br> - 1'b1 : Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1</br>
          </comment>
        </bits>
        <bits access="rw" name="bvalidoven" pos="6" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>B-Peripheral Session Valid Override Value (BvalidOvEn)</br>
            <br>This bit is used to enable/disable the software to override the Bvalid signal using the GOTGCTL.BvalidOvVal. </br>
            <br> - 1'b1 : Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal.</br>
            <br> - 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is used internally by the force</br>
          </comment>
        </bits>
        <bits access="rw" name="bvalidovval" pos="7" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>B-Peripheral Session Valid OverrideValue (BvalidOvVal)</br>
            <br>This bit is used to set Override value for Bvalid signal when GOTGCTL.BvalidOvEn is set.</br>
            <br> - 1'b0 : Bvalid value is 1'b0 when GOTGCTL.BvalidOvEn =1</br>
            <br> - 1'b1 : Bvalid value is 1'b1 when GOTGCTL.BvalidOvEn =1</br>
          </comment>
        </bits>
        <bits access="r" name="hstnegscs" pos="8" rst="0">
          <comment>
            <br>Mode: HNP-capable Device</br>
            <br>Host Negotiation Success (HstNegScs)</br>
            <br>The controller sets this bit when host negotiation is successful. The controller clears this bit when the HNP Request (HNPReq) bit in this register is set.</br>
            <br> - 1'b0: Host negotiation failure</br>
            <br> - 1'b1: Host negotiation success</br>
          </comment>
        </bits>
        <bits access="rw" name="hnpreq" pos="9" rst="0">
          <comment>
            <br>Mode: HNP Capable OTG Device</br>
            <br>HNP Request (HNPReq)</br>
            <br>The application sets this bit to initiate an HNP request to the connected USB host. The application can clear this bit by writing a 0 when the Host Negotiation Success Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET. The controller clears this bit when the HstNegSucStsChng bit is cleared.</br>
            <br> - 1'b0: No HNP request</br>
            <br> - 1'b1: HNP request</br>
          </comment>
        </bits>
        <bits access="rw" name="hstsethnpen" pos="10" rst="0">
          <comment>
            <br>Mode: HNP Capable OTG Host</br>
            <br>Host Set HNP Enable (HstSetHNPEn)</br>
            <br>The application sets this bit when it has successfully enabled HNP (using the SetFeature.SetHNPEnable command) on the connected device.</br>
            <br> - 1'b0: Host Set HNP is not enabled</br>
            <br> - 1'b1: Host Set HNP is enabled</br>
          </comment>
        </bits>
        <bits access="rw" name="devhnpen" pos="11" rst="0">
          <comment>
            <br>Mode: HNP Capable OTG Device</br>
            <br> Device HNP Enabled (DevHNPEn)</br>
            <br>The application sets this bit when it successfully receives a SetFeature.SetHNPEnable command from the connected USB host.</br>
            <br> - 1'b0: HNP is not enabled in the application</br>
            <br> - 1'b1: HNP is enabled in the application</br>
          </comment>
        </bits>
        <bits access="rw" name="ehen" pos="12" rst="0">
          <comment>
            <br>Mode: SRP Capable Host</br>
            <br>Embedded Host Enable (EHEn)</br>
            <br>It is used to select between OTG A Device state Machine and Embedded Host state machine.</br>
            <br> - 1'b0: OTG A Device state machine is selected</br>
            <br> - 1'b1: Embedded Host State Machine is selected</br>
            <br>Note:</br>
            <br> This field is valid only in SRP-Capable OTG Mode (OTG_MODE=0,1).</br>
          </comment>
        </bits>
        <bits access="rw" name="dbncefltrbypass" pos="15" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Debounce Filter Bypass</br>
            <br>Bypass Debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when enabled.</br>
            <br> - 1'b0: Disabled</br>
            <br> - 1'b1: Enabled</br>
            <br/>
            <br> </br>
            <br>Note:  This register bit is valid only when debounce filters are present in core.</br>
            <br/>
          </comment>
        </bits>
        <bits access="r" name="conidsts" pos="16" rst="1">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Connector ID Status (ConIDSts)</br>
            <br>Indicates the connector ID status on a connect event.</br>
            <br> - 1'b0: The core is in A-Device mode.</br>
            <br> - 1'b1: The core is in B-Device mode.</br>
            <br/>
            <br> Note:</br>
            <br> The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later. </br>
            <br> Reset:</br>
            <br>  - 1'b0: in host only mode (OTG_MODE = 5 or 6)</br>
            <br>  - 1'b1: in all other configurations</br>
          </comment>
        </bits>
        <bits access="r" name="dbnctime" pos="17" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>Long/Short Debounce Time (DbncTime)</br>
            <br>Indicates the debounce time of a detected connection.</br>
            <br> - 1'b0: Long debounce time, used for physical connections (100 ms + 2.5 micro-sec)</br>
            <br> - 1'b1: Short debounce time, used for soft connections (2.5 micro-sec)</br>
          </comment>
        </bits>
        <bits access="r" name="asesvld" pos="18" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>A-Session Valid (ASesVld)</br>
            <br>Indicates the Host mode transceiver status.</br>
            <br> - 1'b0: A-session is not valid</br>
            <br> - 1'b1: A-session is valid</br>
            <br>Note: If you do not enabled OTG features (such as SRP and HNP), the read reset value will be 1. The vbus assigns the values internally for non-SRP or non-HNP configurations.</br>
            <br>In case of OTG_MODE=0, the reset value of this bit is 1'b0.</br>
          </comment>
        </bits>
        <bits access="r" name="bsesvld" pos="19" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>B-Session Valid (BSesVld)</br>
            <br>Indicates the Device mode transceiver status.</br>
            <br> - 1'b0: B-session is not valid.</br>
            <br> - 1'b1: B-session is valid.</br>
            <br>In OTG mode, you can use this bit to determine if the device is connected or disconnected.</br>
            <br/>
            <br>Note:</br>
            <br> - If you do not enable OTG features (such as SRP and HNP), the read reset value will be 1.The vbus assigns the values internally for non- SRP or non-HNP configurations. </br>
            <br> - In case of OTG_MODE=0, the reset value of this bit is 1'b0.</br>
            <br> - The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.</br>
          </comment>
        </bits>
        <bits access="rw" name="otgver" pos="20" rst="0">
          <comment>
            <br>OTG Version (OTGVer)</br>
            <br>Indicates the OTG revision.</br>
            <br> - 1'b0: OTG Version 1.3. In this version the core supports Data line pulsing and VBus pulsing for SRP.</br>
            <br> - 1'b1: OTG Version 2.0. In this version the core supports only Data line pulsing for SRP.</br>
          </comment>
        </bits>
        <bits access="r" name="curmod" pos="21" rst="0">
          <comment>
            <br>Current Mode of Operation (CurMod)</br>
            <br>Mode: Host and Device</br>
            <br>Indicates the current mode.</br>
            <br> - 1'b0: Device mode</br>
            <br> - 1'b1: Host mode</br>
            <br> Reset:</br>
            <br> - 1'b1 in Host-only mode (OTG_MODE=5 or 6)</br>
            <br> - 1'b0 in all other configurations</br>
            <br>Note: The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.</br>
          </comment>
        </bits>
      </reg>
      <reg name="gotgint" protect="rw">
        <comment>OTG Interrupt Register
The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.</comment>
        <bits access="rw" name="sesenddet" pos="2" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Session End Detected (SesEndDet)</br>
            <br>The controller sets this bit when the utmiotg_bvalid signal is deasserted. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="sesreqsucstschng" pos="8" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Session Request Success Status Change (SesReqSucStsChng)</br>
            <br>The core sets this bit on the success or failure of a session request. The application must read the Session Request Success bit in the OTG Control and Status register (GOTGCTL.SesReqScs) to check for success or failure. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="hstnegsucstschng" pos="9" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Host Negotiation Success Status Change (HstNegSucStsChng)</br>
            <br>The core sets this bit on the success or failure of a USB host negotiation request. The application must read the Host Negotiation Success bit of the OTG Control and Status register (GOTGCTL.HstNegScs) to check for success or failure. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="hstnegdet" pos="17" rst="0">
          <comment>
            <br>Mode:Host and Device</br>
            <br>Host Negotiation Detected (HstNegDet)</br>
            <br>The core sets this bit when it detects a host negotiation request on the USB. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="adevtoutchg" pos="18" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>A-Device Timeout Change (ADevTOUTChg)</br>
            <br>The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="dbncedone" pos="19" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>Debounce Done (DbnceDone)</br>
            <br>The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is SET in the Core USB Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, respectively). This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
      </reg>
      <reg name="gahbcfg" protect="rw">
        <comment>AHB Configuration Register
This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.</comment>
        <bits access="rw" name="glblintrmsk" pos="0" rst="0">
          <comment>
            <br>Mode: Host and device</br>
            <br>Global Interrupt Mask (GlblIntrMsk)</br>
            <br>The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit's setting, the interrupt status registers are updated by the controller.</br>
            <br> - 1'b0: Mask the interrupt assertion to the application.</br>
            <br> - 1'b1: Unmask the interrupt assertion to the application.</br>
          </comment>
        </bits>
        <bits access="rw" name="hbstlen" pos="4:1" rst="0">
          <comment>
            <br>Mode: Host and device</br>
            <br>Burst Length/Type (HBstLen)</br>
            <br>This field is used in both External and Internal DMA modes. In External DMA mode, these bits appear on dma_burst[3:0] ports, which can be used by an external wrapper to interface the External DMA Controller interface to Synopsys DW_ahb_dmac or ARM PrimeCell.</br>
            <br>External DMA Mode defines the DMA burst length in terms of 32-bit words:</br>
            <br> - 4'b0000: 1 word</br>
            <br> - 4'b0001: 4 words</br>
            <br> - 4'b0010: 8 words</br>
            <br> - 4'b0011: 16 words</br>
            <br> - 4'b0100: 32 words</br>
            <br> - 4'b0101: 64 words</br>
            <br> - 4'b0110: 128 words</br>
            <br> - 4'b0111: 256 words</br>
            <br> - Others: Reserved</br>
            <br>Internal DMA Mode AHB Master burst type:</br>
            <br> - 4'b0000 Single</br>
            <br> - 4'b0001 INCR</br>
            <br> - 4'b0011 INCR4</br>
            <br> - 4'b0101 INCR8</br>
            <br> - 4'b0111 INCR16</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
        <bits access="rw" name="dmaen" pos="5" rst="0">
          <comment>
            <br>Mode: Host and device</br>
            <br>DMA Enable (DMAEn)</br>
            <br/>
            <br>This bit is always 0 when Slave-Only mode has been selected.</br>
            <br/>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="nptxfemplvl" pos="7" rst="0">
          <comment>
            <br>Mode: Host and device</br>
            <br>Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)</br>
            <br>This bit is used only in Slave mode. In host mode and with Shared FIFO with device mode, this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.</br>
            <br>With dedicated FIFO in device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is triggered.</br>
            <br>Host mode and with Shared FIFO with device mode:</br>
            <br> - 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty</br>
            <br> - 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty </br>
            <br>Dedicated FIFO in device mode:</br>
            <br> - 1'b0: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty</br>
            <br> - 1'b1: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty</br>
          </comment>
        </bits>
        <bits access="rw" name="ptxfemplvl" pos="8" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>Periodic TxFIFO Empty Level (PTxFEmpLvl)</br>
            <br>Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This bit is used only in Slave mode.</br>
            <br> - 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty</br>
            <br> - 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty</br>
          </comment>
        </bits>
        <bits access="rw" name="remmemsupp" pos="21" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Remote Memory Support (RemMemSupp)</br>
            <br>This bit is programmed to enable the functionality to wait for the system DMA Done Signal for the DMA Write Transfers.</br>
            <br> - GAHBCFG.RemMemSupp=1</br>
            <br>The int_dma_req output signal is asserted when the DMA starts write transfer to the external memory. When the core is done with the Transfers it asserts int_dma_done signal to flag the completion of DMA writes from the controller. The core then waits for sys_dma_done signal from the system to proceed further and complete the Data Transfer corresponding to a particular Channel/Endpoint. </br>
            <br> - GAHBCFG.RemMemSupp=0</br>
            <br>The int_dma_req and int_dma_done signals are not asserted and the core proceeds with the assertion of the XferComp interrupt as soon as the DMA write transfer is done at the Core Boundary and it does not wait for the sys_dma_done signal to complete the DATA transfers.</br>
          </comment>
        </bits>
        <bits access="rw" name="notialldmawrit" pos="22" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Notify All DMA Write Transactions (NotiAllDmaWrit)</br>
            <br>This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to the Channel/Endpoint. This bit is valid only when GAHBCFG.RemMemSupp is set to 1.</br>
            <br> - GAHBCFG.NotiAllDmaWrit = 1</br>
            <br>The core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/Endpoint.</br>
            <br> - GAHBCFG.NotiAllDmaWrit = 0</br>
            <br>The core asserts int_dma_req signal only for the last transaction of DMA write transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits for sys_dma_done signal only for that transaction of DMA write to complete the transfer of a particular Channel/Endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahbsingle" pos="23" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>AHB Single Support (AHBSingle)</br>
            <br>This bit when programmed supports Single transfers for the remaining data in a transfer when the core is operating in DMA mode. </br>
            <br> - 1'b0: The remaining data in the transfer is sent using INCR burst size.</br>
            <br> - 1'b1: The remaining data in the transfer is sent using Single burst size. </br>
            <br>Note: If this feature is enabled, the AHB RETRY and SPLIT transfers still have INCR burst type. Enable this feature when the AHB Slave connected to the core does not support INCR burst (and when Split, and Retry transactions are not being used in the bus).</br>
          </comment>
        </bits>
        <bits access="rw" name="invdescendianess" pos="24" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Invert Descriptor Endianess (InvDescEndianess)</br>
            <br> - 1'b0: Descriptor Endianness is same as AHB Master Endianness.</br>
            <br> - 1'b1: </br>
            <br> -- If the AHB Master endianness is Big Endian, the Descriptor Endianness is Little Endian.</br>
            <br> -- If the AHB Master endianness is Little Endian, the Descriptor Endianness is Big Endian.</br>
          </comment>
        </bits>
      </reg>
      <reg name="gusbcfg" protect="rw">
        <comment>USB Configuration Register
This register can be used to configure the core after power-on or a changing to Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.</comment>
        <bits access="rw" name="toutcal" pos="2:0" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>HS/FS Timeout Calibration (TOutCal)</br>
            <br/>
            <br>The number of PHY clocks that the application programs in this field is added to the high-speed/full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the linestate condition can vary from one PHY to another.</br>
            <br/>
            <br>The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock are as follows:</br>
            <br/>
            <br>High-speed operation:</br>
            <br> - One 30-MHz PHY clock = 16 bit times</br>
            <br> - One 60-MHz PHY clock = 8 bit times</br>
            <br>Full-speed operation:</br>
            <br> - One 30-MHz PHY clock = 0.4 bit times</br>
            <br> - One 60-MHz PHY clock = 0.2 bit times</br>
            <br> - One 48-MHz PHY clock = 0.25 bit times</br>
            <br/>
          </comment>
        </bits>
        <bits access="r" name="phyif" pos="3" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>PHY Interface (PHYIf)</br>
            <br>The application uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is chosen, this must be Set to 8-bit mode.</br>
            <br> - 1'b0: 8 bits</br>
            <br> - 1'b1: 16 bits</br>
            <br>This bit is writable only If UTMI+ and ULPI were selected. Otherwise, this bit returns the value for the power-on interface selected during configuration.</br>
          </comment>
        </bits>
        <bits access="r" name="ulpi_utmi_sel" pos="4" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>ULPI or UTMI+ Select (ULPI_UTMI_Sel)</br>
            <br/>
            <br>The application uses this bit to select either a UTMI+ interface or ULPI Interface.</br>
            <br> - 1'b0: UTMI+ Interface</br>
            <br> - 1'b1: ULPI Interface</br>
          </comment>
        </bits>
        <bits access="rw" name="fsintf" pos="5" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Full-Speed Serial Interface Select (FSIntf)</br>
            <br/>
            <br>The application uses this bit to select either a unidirectional or bidirectional USB 1.1 full-speed serial transceiver interface.</br>
            <br> - 1'b0: 6-pin unidirectional full-speed serial interface</br>
            <br> - 1'b1: 3-pin bidirectional full-speed serial interface</br>
            <br>If a USB 1.1 Full-Speed Serial Transceiver interface was not selected, this bit is always 0, with Write Only access. If a USB 1.1 FS interface was selected, Then the application can Set this bit to select between the 3- and 6-pin interfaces, and access is Read and Write.</br>
            <br/>
            <br>Note: For supporting the new 4-pin bi-directional interface, you need to select 6-pin unidirectional FS serial mode, and add an external control to convert it to a 4-pin interface.</br>
          </comment>
        </bits>
        <bits access="rw" name="physel" pos="6" rst="0">
          <comment>
            <br>PHYSel</br>
            <br/>
            <br>Mode: Host and Device</br>
            <br/>
            <br>USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select (PHYSel)</br>
            <br>The application uses this bit to select either a high-speed UTMI+ or ULPI PHY, or a full-speed transceiver.</br>
            <br> - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY</br>
            <br> - 1'b1: USB 1.1 full-speed serial transceiver</br>
            <br>If a USB 1.1 Full-Speed Serial Transceiver interface was not selected in, this bit is always 0, with Write Only access.</br>
            <br>If a high-speed PHY interface was not selected in, this bit is always 1, with Write Only access.</br>
            <br>If both interface types were selected (parameters have non-zero values), the application uses this bit to select which interface is active, and access is Read and Write.</br>
          </comment>
        </bits>
        <bits access="rw" name="srpcap" pos="8" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>SRP-Capable (SRPCap)</br>
            <br>The application uses this bit to control the controller's SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to</br>
            <br>activate VBUS and start a session.</br>
            <br> - 1'b0: SRP capability is not enabled.</br>
            <br> - 1'b1: SRP capability is enabled.</br>
            <br>If SRP functionality is disabled by the software, the OTG signals on the PHY domain must be tied to the appropriate values.</br>
          </comment>
        </bits>
        <bits access="rw" name="hnpcap" pos="9" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>HNP-Capable (HNPCap)</br>
            <br>The application uses this bit to control the controller's HNP capabilities.</br>
            <br> - 1'b0: HNP capability is not enabled.</br>
            <br> - 1'b1: HNP capability is enabled.</br>
            <br>If HNP functionality is disabled by the software, the OTG signals on the PHY domain must be tied to the appropriate values.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbtrdtim" pos="13:10" rst="5">
          <comment>
            <br>Mode: Device only</br>
            <br>USB Turnaround Time (USBTrdTim)</br>
            <br>Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). This must be programmed to</br>
            <br> - 4'h5: When the MAC interface is 16-bit UTMI+ .</br>
            <br> - 4'h9: When the MAC interface is 8-bit UTMI+ .</br>
            <br>Note: The previous values are calculated for the minimum AHB frequency of 30 MHz. USB turnaround time is critical for certification where long cables and 5-Hubs are used. If you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, these bits can be programmed to a larger value.</br>
          </comment>
        </bits>
        <bits access="rw" name="phylpwrclksel" pos="15" rst="0">
          <comment>
            <br>PHY Low-Power Clock Select (PhyLPwrClkSel)</br>
            <br>Mode: Host and Device</br>
            <br>Selects either 480-MHz or 48-MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48-MHz clock to save power.</br>
            <br> - 1'b0: 480-MHz Internal PLL clock</br>
            <br> - 1'b1: 48-MHz External Clock</br>
            <br>In 480 MHz mode, the UTMI interface operates at either 60 or 30-MHz, depending upon whether 8- or 16-bit data width is selected.</br>
            <br>In 48-MHz mode, the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode (depending on the PHY vendor). This bit drives the utmi_fsls_low_power core output signal, and is valid only for UTMI+ PHYs.</br>
          </comment>
        </bits>
        <bits access="rw" name="termseldlpulse" pos="22" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>TermSel DLine Pulsing Selection (TermSelDLPulse)</br>
            <br>This bit selects utmi_termselect to drive data line pulse during SRP.</br>
            <br> - 1'b0: Data line pulsing using utmi_txvalid (Default).</br>
            <br> - 1'b1: Data line pulsing using utmi_termsel.</br>
          </comment>
        </bits>
        <bits access="r" name="ic_usbcap" pos="26" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>IC_USB-Capable (IC_USBCap)</br>
            <br>The application uses this bit to control the core's IC_USB capabilities.</br>
            <br> - 1'b0: IC_USB PHY Interface is not selected.</br>
            <br> - 1'b1: IC_USB PHY Interface is selected.</br>
            <br>This bit is writable only if OTG_ENABLE_IC_USB=1 and OTG_FSPHY_INTERFACE!=0.</br>
            <br>The reset value depends on the configuration parameter OTG_SELECT_IC_USB when OTG_ENABLE_IC_USB = 1. In all other cases, this bit is set to 1'b0 and the bit is read only.</br>
          </comment>
        </bits>
        <bits access="rw" name="txenddelay" pos="28" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Tx End Delay (TxEndDelay)</br>
            <br>Writing 1'b1 to this bit enables the controller to follow the TxEndDelay timings as per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote wakeup.  </br>
            <br> - 1'b0 : Normal Mode.</br>
            <br> - 1'b1 : Tx End delay.</br>
          </comment>
        </bits>
        <bits access="rw" name="forcehstmode" pos="29" rst="0">
          <comment>
            <br>Mode: Host and device</br>
            <br>Force Host Mode (ForceHstMode)</br>
            <br>Writing a 1 to this bit forces the core to host mode irrespective of utmiotg_iddig input pin.</br>
            <br> - 1'b0 : Normal Mode.</br>
            <br> - 1'b1 : Force Host Mode.</br>
            <br>After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads 0.</br>
          </comment>
        </bits>
        <bits access="rw" name="forcedevmode" pos="30" rst="0">
          <comment>
            <br>Mode:Host and device</br>
            <br>Force Device Mode (ForceDevMode)</br>
            <br>Writing a 1 to this bit forces the controller to device mode irrespective of utmiotg_iddig input pin.</br>
            <br> - 1'b0 : Normal Mode.</br>
            <br> - 1'b1 : Force Device Mode.</br>
            <br>After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads 0.</br>
          </comment>
        </bits>
        <bits access="w" name="corrupttxpkt" pos="31" rst="0">
          <comment>
            <br>Mode: Host and device</br>
            <br>Corrupt Tx packet (CorruptTxPkt)</br>
            <br>This bit is for debug purposes only. Never Set this bit to 1. The application should always write 1'b0 to this bit.</br>
          </comment>
        </bits>
      </reg>
      <reg name="grstctl" protect="rw">
        <comment>Reset Register
The application uses this register to reset various hardware features inside the controller.</comment>
        <bits access="rw" name="csftrst" pos="0" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Core Soft Reset (CSftRst)</br>
            <br>Resets the hclk and phy_clock domains as follows:</br>
            <br> - Clears the interrupts and all the CSR registers except the following register bits:</br>
            <br> -- PCGCCTL.RstPdwnModule</br>
            <br> -- PCGCCTL.GateHclk</br>
            <br> -- PCGCCTL.PwrClmp</br>
            <br> -- PCGCCTL.StopPPhyLPwrClkSelclk</br>
            <br> -- GUSBCFG.ForceDevMode</br>
            <br> -- GUSBCFG.ForceHstMode</br>
            <br> -- GUSBCFG.PhyLPwrClkSel</br>
            <br> -- GUSBCFG.DDRSel</br>
            <br> -- GUSBCFG.PHYSel</br>
            <br> -- GUSBCFG.FSIntf</br>
            <br> -- GUSBCFG.ULPI_UTMI_Sel</br>
            <br> -- GUSBCFG.PHYIf</br>
            <br> -- GUSBCFG.TxEndDelay</br>
            <br> -- GUSBCFG.TermSelDLPulse</br>
            <br> -- GUSBCFG.ULPIClkSusM</br>
            <br> -- GUSBCFG.ULPIAutoRes</br>
            <br> -- GUSBCFG.ULPIFsLs</br>
            <br> -- GGPIO</br>
            <br> -- GPWRDN</br>
            <br> -- GADPCTL</br>
            <br> -- HCFG.FSLSPclkSel</br>
            <br> -- DCFG.DevSpd</br>
            <br> -- DCTL.SftDiscon</br>
            <br> - All module state machines</br>
            <br> - All module state machines (except the AHB Slave Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed.</br>
            <br> - Any transactions on the AHB Master are terminated as soon as possible, after gracefully completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately.</br>
            <br> - When Hibernation or ADP feature is enabled, the PMU module is not reset by the Core Soft Reset.</br>
            <br>The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after</br>
            <br>all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit is cleared software must wait at least 3 PHY clocks before doing any access to the PHY domain (synchronization delay). Software must also must check that bit 31 of this register is 1 (AHB Master is IDLE) before starting any operation.</br>
            <br/>
            <br>Typically software reset is used during software development and also when you dynamically change the PHY selection bits in the USB configuration registers listed above. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper operation.</br>
          </comment>
        </bits>
        <bits access="rw" name="piufssftrst" pos="1" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)</br>
            <br/>
            <br>Resets the PIU FS Dedicated Controller</br>
            <br> All module state machines in FS Dedicated Controller of PIU are reset to the IDLE state. Used to reset the FS Dedicated controller in PIU in case of any PHY Errors like Loss of activity or Babble Error resulting in the PHY remaining in RX state for more than one frame boundary.</br>
            <br>This is a self clearing bit and core clears this bit after all the necessary logic is reset in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmcntrrst" pos="2" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>Host Frame Counter Reset (FrmCntrRst)</br>
            <br>The application writes this bit to reset the (micro)Frame number counter inside the core. When the (micro)Frame counter is reset, the subsequent SOF sent out by the core has a (micro)Frame number of 0.</br>
            <br>When application writes 1 to the bit, it might not be able to read back the value as it will get cleared by the core in a few clock cycles.</br>
          </comment>
        </bits>
        <bits access="rw" name="rxfflsh" pos="4" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>RxFIFO Flush (RxFFlsh)</br>
            <br>The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction.</br>
            <br>The application must only write to this bit after checking that the controller is neither reading from the RxFIFO nor writing to the RxFIFO.</br>
            <br/>
            <br>The application must wait until the bit is cleared before performing any other operations. This bit requires eight clocks (slowest of PHY or AHB clock) to clear.</br>
          </comment>
        </bits>
        <bits access="rw" name="txfflsh" pos="5" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>TxFIFO Flush (TxFFlsh)</br>
            <br>This bit selectively flushes a single or all transmit FIFOs, but cannot do so If the core is in the midst of a transaction.</br>
            <br>The application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO.</br>
            <br>Verify using these registers:</br>
            <br> - ReadNAK Effective Interrupt ensures the core is not reading from the FIFO</br>
            <br> - WriteGRSTCTL.AHBIdle ensures the core is not writing anything to the FIFO.</br>
            <br>Flushing is normally recommended when FIFOs are reconfigured or when switching between Shared FIFO and Dedicated Transmit FIFO operation. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear, using the slower clock of phy_clk or hclk.</br>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="10:6" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>TxFIFO Number (TxFNum)</br>
            <br>This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be changed until the core clears the TxFIFO Flush bit.</br>
            <br> - 5'h0:</br>
            <br> -- Non-periodic TxFIFO flush in Host mode</br>
            <br> -- Non-periodic TxFIFO flush in device mode when in shared FIFO operation</br>
            <br> -- Tx FIFO 0 flush in device mode when in dedicated FIFO mode</br>
            <br> - 5'h1:</br>
            <br> -- Periodic TxFIFO flush in Host mode </br>
            <br> -- Periodic TxFIFO 1 flush in Device mode when in shared FIFO operation</br>
            <br> -- TXFIFO 1 flush in device mode when in dedicated FIFO mode</br>
            <br> - 5'h2:</br>
            <br> -- Periodic TxFIFO 2 flush in Device mode when in shared FIFO operation</br>
            <br> -- TXFIFO 2 flush in device mode when in dedicated FIFO mode</br>
            <br>...</br>
            <br> - 5'hF</br>
            <br> -- Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation</br>
            <br> -- TXFIFO 15 flush in device mode when in dedicated FIFO mode</br>
            <br> - 5'h10: Flush all the transmit FIFOs in device or host mode</br>
          </comment>
        </bits>
        <bits access="r" name="dmareq" pos="30" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>DMA Request Signal (DMAReq)</br>
            <br>Indicates that the DMA request is in progress. Used for debug.</br>
          </comment>
        </bits>
        <bits access="r" name="ahbidle" pos="31" rst="1">
          <comment>
            <br>Mode: Host and Device</br>
            <br>AHB Master Idle (AHBIdle)</br>
            <br>Indicates that the AHB Master State Machine is in the IDLE condition.</br>
          </comment>
        </bits>
      </reg>
      <reg name="gintsts" protect="rw">
        <comment>Interrupt Register
This register interrupts the application for system-level events in the current mode (Device mode or Host mode).
Some of the bits in this register are valid only in Host mode, while others are valid in Device mode only. This register also indicates the current mode. To clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit.
The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically.
The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
Note: Read the reset value of GINTSTS.CurMod only after the following conditions:
 - If IDDIG_FILTER is disabled, read only after PHY clock is stable.
 - If IDDIG_FILTER is enabled, read only after the filter timer expires.</comment>
        <bits access="r" name="curmod" pos="0" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Current Mode of Operation (CurMod)</br>
            <br>Indicates the current mode.</br>
            <br> - 1'b0: Device mode</br>
            <br> - 1'b1: Host mode </br>
            <br/>
            <br> 	</br>
            <br>Note: The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later. </br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="modemis" pos="1" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Mode Mismatch Interrupt (ModeMis)</br>
            <br>The core sets this bit when the application is trying to access:</br>
            <br> - A Host mode register, when the controller is operating in Device mode</br>
            <br> - A Device mode register, when the controller is operating in Host mode</br>
            <br>The register access is completed on the AHB with an OKAY response, but is ignored by the controller internally and does not affect the operation of the controller.</br>
            <br>This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="r" name="otgint" pos="2" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>OTG Interrupt (OTGInt)</br>
            <br>The controller sets this bit to indicate an OTG protocol event. The application must read the OTG Interrupt Status (GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the GOTGINT register to clear this bit.</br>
          </comment>
        </bits>
        <bits access="rw" name="sof" pos="3" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Start of (micro)Frame (Sof)</br>
            <br/>
            <br>In Host mode, the core sets this bit to indicate that an SOF (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt.</br>
            <br/>
            <br>In Device mode, the controller sets this bit to indicate that an SOF token has been received on the USB. The application can read the Device Status register to get the current (micro)Frame number. This interrupt is seen only when the core is operating at either HS or FS. This bit can be set only by the core and the application must write 1 to clear it.</br>
            <br/>
            <br>Note: This register may return 1'b1 if read immediately after power-on reset.</br>
            <br>If the register bit reads 1'b1 immediately after power-on reset, it does not indicate that an SOF has been sent (in case of host mode) or SOF has been received (in case of device mode).</br>
            <br>The read value of this interrupt is valid only after a valid connection between host and device is established. If the bit is set after power on reset the application can clear the bit.</br>
          </comment>
        </bits>
        <bits access="r" name="rxflvl" pos="4" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>RxFIFO Non-Empty (RxFLvl)</br>
            <br/>
            <br>Indicates that there is at least one packet pending to be read from the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="nptxfemp" pos="5" rst="1">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Non-periodic TxFIFO Empty (NPTxFEmp)</br>
            <br>This interrupt is asserted when the Non-periodic TxFIFO is either half or completely empty, and there is space for at least one Entry to be written to the Non-periodic Transmit Request Queue. The half or completely empty status is determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl).</br>
            <br>In host mode, the application can use GINTSTS.NPTxFEmp with the OTG_EN_DED_TX_FIFO parameter set to either 1 or 0.</br>
            <br>In device mode, the application uses GINTSTS.NPTxFEmp when OTG_EN_DED_TX_FIFO=0. When OTG_EN_DED_TX_FIFO=1, the application uses DIEPINTn.TxFEmp.</br>
          </comment>
        </bits>
        <bits access="r" name="ginnakeff" pos="6" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Global IN Non-periodic NAK Effective (GINNakEff)</br>
            <br>Indicates that the Set Global Non-periodic IN NAK bit in the Device Control register (DCTL.SGNPInNak) set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit Set by the application. This bit can be cleared by clearing the Clear Global Non-periodic IN NAK bit in the Device Control register (DCTL.CGNPInNak). This interrupt does not necessarily mean that a NAK handshake</br>
            <br>is sent out on the USB. The STALL bit takes precedence over the NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="goutnakeff" pos="7" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Global OUT NAK Effective (GOUTNakEff)</br>
            <br>Indicates that the Set Global OUT NAK bit in the Device Control register (DCTL.SGOUTNak), Set by the application, has taken effect in the core. This bit can be cleared by writing the Clear Global OUT NAK bit in the Device Control register (DCTL.CGOUTNak).</br>
          </comment>
        </bits>
        <bits access="rw" name="erlysusp" pos="10" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Early Suspend (ErlySusp)</br>
            <br>The controller sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbsusp" pos="11" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>USB Suspend (USBSusp)</br>
            <br>The controller sets this bit to indicate that a suspend was detected on the USB. The controller enters the Suspended state when there is no activity on the linestate signal for an extended period of time.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbrst" pos="12" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>USB Reset (USBRst)</br>
            <br>The controller sets this bit to indicate that a reset is detected on the USB.</br>
          </comment>
        </bits>
        <bits access="rw" name="enumdone" pos="13" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Enumeration Done (EnumDone)</br>
            <br>The core sets this bit to indicate that speed enumeration is complete. The application must read the Device Status (DSTS) register to obtain the enumerated speed.</br>
          </comment>
        </bits>
        <bits access="rw" name="isooutdrop" pos="14" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)</br>
            <br>The controller sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum packet size packet for the isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="eopf" pos="15" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>End of Periodic Frame Interrupt (EOPF)</br>
            <br>Indicates that the period specified in the Periodic Frame Interval field of the Device Configuration register (DCFG.PerFrInt) has been reached in the current microframe.</br>
          </comment>
        </bits>
        <bits access="rw" name="epmis" pos="17" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Endpoint Mismatch Interrupt (EPMis)</br>
            <br>Note: This interrupt is valid only in shared FIFO operation.</br>
            <br>Indicates that an IN token has been received for a non-periodic endpoint, but the data for another endpoint is present in the top of the Non-periodic Transmit FIFO and the IN endpoint mismatch count programmed by the application has expired.</br>
          </comment>
        </bits>
        <bits access="r" name="iepint" pos="18" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>IN Endpoints Interrupt (IEPInt)</br>
            <br>The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in Device mode). The application must read the Device All Endpoints Interrupt (DAINT) register to determine the exact number of the IN endpoint on Device IN Endpoint-n Interrupt (DIEPINTn) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding DIEPINTn register to</br>
            <br>clear this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="oepint" pos="19" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>OUT Endpoints Interrupt (OEPInt)</br>
            <br>The controller sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in Device mode). The application must read the Device All Endpoints Interrupt (DAINT) register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register to determine the exact cause of the interrupt. The application must</br>
            <br>clear the appropriate status bit in the corresponding DOEPINTn register to clear this bit.</br>
          </comment>
        </bits>
        <bits access="rw" name="incompisoin" pos="20" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Incomplete Isochronous IN Transfer (incompISOIN)</br>
            <br>The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current microframe. This interrupt is asserted along with the End of Periodic Frame Interrupt (EOPF) bit in this register.</br>
            <br>Note: This interrupt is not asserted in Scatter/Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="incomplp" pos="21" rst="0">
          <comment>
            <br>Incomplete Periodic Transfer (incomplP)</br>
            <br>Mode: Host only</br>
            <br>In Host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending which are scheduled for the current microframe.</br>
            <br>Incomplete Isochronous OUT Transfer (incompISOOUT)</br>
            <br>Mode: Device only</br>
            <br>The Device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which the transfer is not completed in the current microframe. This interrupt is asserted along with the End of Periodic Frame Interrupt (EOPF) bit in this register.</br>
          </comment>
        </bits>
        <bits access="rw" name="fetsusp" pos="22" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Data Fetch Suspended (FetSusp)</br>
            <br>This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data. For IN endpoints due to the unavailability of TxFIFO space or Request Queue space. This interrupt is used by the application for an endpoint mismatch algorithm.</br>
            <br/>
            <br>For example, after detecting an endpoint mismatch, the application:</br>
            <br> - Sets a Global non-periodic IN NAK handshake</br>
            <br> - Disables IN endpoints</br>
            <br> - Flushes the FIFO</br>
            <br> - Determines the token sequence from the IN Token Sequence Learning Queue</br>
            <br> - Re-enables the endpoints</br>
            <br> - Clears the Global non-periodic IN NAK handshake</br>
            <br>If the Global non-periodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received. The core generates an 'IN token received when FIFO empty' interrupt. The DWC_otg then sends the host a NAK response. To avoid this scenario, the application can check the GINTSTS.FetSusp interrupt, which ensures that the FIFO is full before clearing a Global NAK handshake.</br>
            <br/>
            <br>Alternatively, the application can mask the IN token received when FIFO empty interrupt when clearing a Global IN NAK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="resetdet" pos="23" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Reset detected Interrupt (ResetDet)</br>
            <br>In Device mode, this interrupt is asserted when a reset is detected on the USB in partial power-down mode when the device is in Suspend.</br>
            <br/>
            <br>In Host mode, this interrupt is not asserted.</br>
          </comment>
        </bits>
        <bits access="r" name="prtint" pos="24" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>Host Port Interrupt (PrtInt)</br>
            <br>The core sets this bit to indicate a change in port status of one of the controller ports in Host mode. The application must read the Host Port Control and Status (HPRT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the Host Port</br>
            <br>Control and Status register to clear this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="hchint" pos="25" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>Host Channels Interrupt (HChInt)</br>
            <br>The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in Host mode). The application must read the Host All Channels Interrupt (HAINT) register to determine the exact number of the channel on which the interrupt occurred, and Then read the corresponding Host</br>
            <br>Channel-n Interrupt (HCINTn) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the HCINTn register to clear this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="ptxfemp" pos="26" rst="1">
          <comment>
            <br>Mode: Host only</br>
            <br>Periodic TxFIFO Empty (PTxFEmp)</br>
            <br>This interrupt is asserted when the Periodic Transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the Periodic Request Queue. The half or completely empty status is determined by the Periodic TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.PTxFEmpLvl).</br>
          </comment>
        </bits>
        <bits access="rw" name="conidstschng" pos="28" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Connector ID Status Change (ConIDStsChng)</br>
            <br>The core sets this bit when there is a change in connector ID status.</br>
          </comment>
        </bits>
        <bits access="rw" name="disconnint" pos="29" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>Disconnect Detected Interrupt (DisconnInt)</br>
            <br>Asserted when a device disconnect is detected.</br>
          </comment>
        </bits>
        <bits access="rw" name="sessreqint" pos="30" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Session Request/New Session Detected Interrupt (SessReqInt)</br>
            <br>In Host mode, this interrupt is asserted when a session request is detected from the device. In Host mode, this interrupt is asserted when a session request is detected from the device.</br>
            <br>In Device mode, this interrupt is asserted when the utmisrp_bvalid signal goes high.</br>
            <br>For more information on how to use this interrupt, see 'Partial Power-Down and Clock Gating Programming Model' in the Programming Guide.</br>
          </comment>
        </bits>
        <bits access="rw" name="wkupint" pos="31" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Resume/Remote Wakeup Detected Interrupt (WkUpInt)</br>
            <br>Wakeup Interrupt during Suspend(L2) or LPM(L1) state.</br>
            <br> - During Suspend(L2):</br>
            <br> -- Device Mode: This interrupt is asserted only when Host Initiated Resume is detected on USB.</br>
            <br> -- Host Mode: This interrupt is asserted only when Device Initiated Remote Wakeup is detected on USB. </br>
            <br>For more information, see 'Partial Power-Down and Clock Gating Programming Model' in the Programming Guide.</br>
            <br> - During LPM(L1):</br>
            <br> -- Device Mode: This interrupt is asserted for either Host Initiated Resume or Device Initiated Remote Wakeup on USB.</br>
            <br> -- Host Mode: This interrupt is asserted for either Host Initiated Resume or Device Initiated Remote Wakeup on USB.</br>
            <br>For more information, see 'LPM Entry and Exit Programming Model' in the Programming Guide.</br>
          </comment>
        </bits>
      </reg>
      <reg name="gintmsk" protect="rw">
        <comment>Interrupt Mask Register
This register works with the Interrupt Register (GINTSTS) to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the GINTSTS register bit corresponding to that interrupt is still set.
Note: The fields of this register change depending on host or device mode.</comment>
        <bits access="rw" name="modemismsk" pos="1" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Mode Mismatch Interrupt Mask (ModeMisMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="otgintmsk" pos="2" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>OTG Interrupt Mask (OTGIntMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="sofmsk" pos="3" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Start of (micro)Frame Mask (SofMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="rxflvlmsk" pos="4" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Receive FIFO Non-Empty Mask (RxFLvlMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="nptxfempmsk" pos="5" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ginnakeffmsk" pos="6" rst="0">
          <comment>
            <br>Mode: Device only,</br>
            <br>Global Non-periodic IN NAK Effective Mask (GINNakEffMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="goutnakeffmsk" pos="7" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Global OUT NAK Effective Mask (GOUTNakEffMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="erlysuspmsk" pos="10" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Early Suspend Mask (ErlySuspMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="usbsuspmsk" pos="11" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>USB Suspend Mask (USBSuspMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="usbrstmsk" pos="12" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>USB Reset Mask (USBRstMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="enumdonemsk" pos="13" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Enumeration Done Mask (EnumDoneMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="isooutdropmsk" pos="14" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="eopfmsk" pos="15" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>End of Periodic Frame Interrupt Mask (EOPFMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="epmismsk" pos="17" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Endpoint Mismatch Interrupt Mask (EPMisMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="iepintmsk" pos="18" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>IN Endpoints Interrupt Mask (IEPIntMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="oepintmsk" pos="19" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>OUT Endpoints Interrupt Mask (OEPIntMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="incomplpmsk" pos="21" rst="0">
          <comment>
            <br>Incomplete Periodic Transfer Mask (incomplPMsk)</br>
            <br>Mode: Host only</br>
            <br>Incomplete Isochronous OUT Transfer Interrupt Mask (incompISOOUTMsk)</br>
            <br>Mode: Device only</br>
          </comment>
        </bits>
        <bits access="rw" name="fetsuspmsk" pos="22" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Data Fetch Suspended Mask (FetSuspMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="resetdetmsk" pos="23" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Reset detected Interrupt Mask (ResetDetMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="prtintmsk" pos="24" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>Host Port Interrupt Mask (PrtIntMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="hchintmsk" pos="25" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>Host Channels Interrupt Mask (HChIntMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ptxfempmsk" pos="26" rst="0">
          <comment>
            <br>Mode: Host only</br>
            <br>Periodic TxFIFO Empty Mask (PTxFEmpMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="conidstschngmsk" pos="28" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Connector ID Status Change Mask (ConIDStsChngMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="disconnintmsk" pos="29" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Disconnect Detected Interrupt Mask (DisconnIntMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="sessreqintmsk" pos="30" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Session Request/New Session Detected Interrupt Mask (SessReqIntMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="wkupintmsk" pos="31" rst="0">
          <comment>
            <br>Mode: Host and Device</br>
            <br>Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk)</br>
            <br>The WakeUp bit is used for LPM state wake up in a way similar to that of wake up in suspend state.</br>
          </comment>
        </bits>
      </reg>
      <reg name="grxstsr" protect="r">
        <comment>Receive Status Debug Read Register
A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status read when the receive FIFO is empty and returns a value of 32'h0000_0000.
Note:
 - Use of these fields vary based on whether the core is functioning as a host or a device.
 - Do not read this register's reset value before configuring the core because the read value is 'X' in the simulation.</comment>
        <bits access="r" name="chnum" pos="3:0" rst="0">
          <comment>
            <br>Channel Number (ChNum)</br>
            <br>Mode: Host only</br>
            <br>Indicates the channel number to which the current received packet belongs.</br>
            <br>Endpoint Number (EPNum)</br>
            <br>Mode: Device only</br>
            <br>Indicates the endpoint number to which the current received packet belongs.</br>
          </comment>
        </bits>
        <bits access="r" name="bcnt" pos="14:4" rst="0">
          <comment>
            <br>Byte Count (BCnt)</br>
            <br/>
            <br>In host mode, indicates the byte count of the received IN data packet.</br>
            <br/>
            <br>In device mode, indicates the byte count of the received data packet.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16:15" rst="0">
          <comment>
            <br>Data PID (DPID)</br>
            <br/>
            <br>In host mode, indicates the Data PID of the received packet. In device mode, indicates the Data PID of the received OUT data packet.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b11: MDATA </br>
            <br>Reset: 2'h0</br>
          </comment>
        </bits>
        <bits access="r" name="pktsts" pos="20:17" rst="0">
          <comment>
            <br>Packet Status (PktSts) indicates the status of the received packet.</br>
            <br>In host mode, </br>
            <br> - 4'b0010: IN data packet received</br>
            <br> - 4'b0011: IN transfer completed (triggers an interrupt)</br>
            <br> - 4'b0101: Data toggle error (triggers an interrupt)</br>
            <br> - 4'b0111: Channel halted (triggers an interrupt)</br>
            <br> - Others: Reserved</br>
            <br>Reset:4'b0</br>
            <br/>
            <br>In device mode,</br>
            <br> - 4'b0001: Global OUT NAK (triggers an interrupt)</br>
            <br> - 4'b0010: OUT data packet received</br>
            <br> - 4'b0011: OUT transfer completed (triggers an interrupt)</br>
            <br> - 4'b0100: SETUP transaction completed (triggers an interrupt)</br>
            <br> - 4'b0110: SETUP data packet received</br>
            <br> - Others: Reserved</br>
            <br>Reset:4'h0</br>
          </comment>
        </bits>
        <bits access="r" name="fn" pos="24:21" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Frame Number (FN)</br>
            <br>This is the least significant 4 bits of the (micro)Frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported.</br>
          </comment>
        </bits>
      </reg>
      <reg name="grxstsp" protect="r">
        <comment>Receive Status Read/Pop Register
A read to the Receive Status Read and Pop register returns the contents of the top of the Receive FIFO and additionally pops the top data entry out of the RxFIFO.
The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 32'h0000_0000. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted.
Note:
 - Use of these fields vary based on whether the core is functioning as a host or a device.
 - Do not read this register's reset value before configuring the core because the read value is 'X' in the simulation.</comment>
        <bits access="r" name="chnum" pos="3:0" rst="0">
          <comment>
            <br>Channel Number (ChNum)</br>
            <br>Mode: Host only</br>
            <br>Indicates the channel number to which the current received packet belongs.</br>
            <br>Endpoint Number (EPNum)</br>
            <br>Mode: Device only</br>
            <br>Indicates the endpoint number to which the current received packet belongs.</br>
          </comment>
        </bits>
        <bits access="r" name="bcnt" pos="14:4" rst="0">
          <comment>
            <br>Byte Count (BCnt)</br>
            <br/>
            <br>In host mode, indicates the byte count of the received IN data packet.</br>
            <br/>
            <br>In device mode, indicates the byte count of the received data packet.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16:15" rst="0">
          <comment>
            <br>Data PID (DPID)</br>
            <br/>
            <br>In host mode, indicates the Data PID of the received packet. In device mode, indicates the Data PID of the received OUT data packet.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b11: MDATA </br>
            <br>Reset: 2'h0</br>
          </comment>
        </bits>
        <bits access="r" name="pktsts" pos="20:17" rst="0">
          <comment>
            <br>Packet Status (PktSts) indicates the status of the received packet.</br>
            <br>In host mode, </br>
            <br> - 4'b0010: IN data packet received</br>
            <br> - 4'b0011: IN transfer completed (triggers an interrupt)</br>
            <br> - 4'b0101: Data toggle error (triggers an interrupt)</br>
            <br> - 4'b0111: Channel halted (triggers an interrupt)</br>
            <br> - Others: Reserved</br>
            <br>Reset:4'b0</br>
            <br/>
            <br>In device mode,</br>
            <br> - 4'b0001: Global OUT NAK (triggers an interrupt)</br>
            <br> - 4'b0010: OUT data packet received</br>
            <br> - 4'b0011: OUT transfer completed (triggers an interrupt)</br>
            <br> - 4'b0100: SETUP transaction completed (triggers an interrupt)</br>
            <br> - 4'b0110: SETUP data packet received</br>
            <br> - Others: Reserved</br>
            <br>Reset:4'h0</br>
          </comment>
        </bits>
        <bits access="r" name="fn" pos="24:21" rst="0">
          <comment>
            <br>Mode: Device only</br>
            <br>Frame Number (FN)</br>
            <br>This is the least significant 4 bits of the (micro)Frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported.</br>
          </comment>
        </bits>
      </reg>
      <reg name="grxfsiz" protect="rw">
        <comment>Receive FIFO Size Register
The application can program the RAM size that must be allocated to the RxFIFO.</comment>
        <bits access="rw" name="rxfdep" pos="11:0" rst="3759">
          <comment>
            <br>Mode: Host and Device</br>
            <br>RxFIFO Depth (RxFDep)</br>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth during configuration.</br>
            <br>If Enable Dynamic FIFO Sizing is selected in coreConsultant, these flops are optimized, and reads return the power-on value.</br>
            <br>If Enable Dynamic FIFO Sizing is selected in coreConsultant, you can write a new value in this field. Programmed values must not exceed the power-on value.</br>
          </comment>
        </bits>
      </reg>
      <reg name="gnptxfsiz" protect="rw">
        <comment>Non-periodic Transmit FIFO Size Register
The application can program the RAM size and the memory start address for the Non-periodic TxFIFO
Note: The fields of this register change depending on host or device mode.</comment>
        <bits access="rw" name="nptxfstaddr" pos="11:0" rst="3759">
          <comment>
            <br>Non-periodic Transmit RAM Start Address (NPTxFStAddr)</br>
            <br>For host mode, this field is always valid.</br>
            <br>This field contains the memory start address for Non-periodic Transmit FIFO RAM. </br>
            <br> - This field is determined during coreConsultant configuration by &quot;Enable Dynamic FIFO Sizing?&quot; (OTG_DFIFO_DYNAMIC):OTG_DFIFO_DYNAMIC = 0</br>
            <br>These flops are optimized, and reads return the power-on value.</br>
            <br> - OTG_DFIFO_DYNAMIC = 1 The application can write a new value in this field. Programmed values must not exceed the power-on value set in coreConsultant.</br>
            <br>Programmed values must not exceed the power-on value set in coreConsultant.</br>
            <br>The power-on reset value of this field is specified during coreConsultant configuration by Largest Rx Data FIFO Depth (parameter OTG_RX_DFIFO_DEPTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="nptxfdep" pos="27:16" rst="3759">
          <comment>
            <br>Mode: Host only</br>
            <br>Non-periodic TxFIFO Depth (NPTxFDep)</br>
            <br>For host mode, this field is always valid.</br>
            <br>For device mode, this field is valid only when OTG_EN_DED_TX_FIFO=0.</br>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>This attribute of field is determined during coreConsultant configuration by &quot;Enable Dynamic FIFO Sizing?&quot; (OTG_DFIFO_DYNAMIC):</br>
            <br> - OTG_DFIFO_DYNAMIC = 0: These flops are optimized, and reads return the power-on value.</br>
            <br> - OTG_DFIFO_DYNAMIC = 1: The application can write a new value in this field. Programmed values must not exceed the power-on value set in coreConsultant.</br>
            <br>The power-on reset value of this field is specified during coreConsultant configuration as Largest IN Endpoint FIFO 0 Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_0).</br>
          </comment>
        </bits>
      </reg>
      <reg name="gnptxsts" protect="r">
        <comment>Non-periodic Transmit FIFO/Queue Status Register
In Device mode, this register is valid only in Shared FIFO operation.
This read-only register contains the free space information for the Non-periodic TxFIFO and the Non-periodic Transmit Request Queue.</comment>
        <bits access="r" name="nptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)</br>
            <br>Indicates the amount of free space available in the Non-periodic TxFIFO.</br>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Non-periodic TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0 &lt;= n &lt;= 32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
            <br>  Reset: Configurable</br>
          </comment>
        </bits>
        <bits access="r" name="nptxqspcavail" pos="23:16" rst="8">
          <comment>
            <br>Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail)</br>
            <br>Indicates the amount of free space available in the Non-periodic Transmit Request Queue. This queue holds both IN and OUT requests in Host mode. Device mode has only IN requests.</br>
            <br> - 8'h0: Non-periodic Transmit Request Queue is full</br>
            <br> - 8'h1: 1 location available</br>
            <br> - 8'h2: 2 locations available</br>
            <br> - n: n locations available (0 &lt;= n &lt;= 8)</br>
            <br> - Others: Reserved</br>
            <br>  Reset: Configurable</br>
          </comment>
        </bits>
        <bits access="r" name="nptxqtop" pos="30:24" rst="0">
          <comment>
            <br>Top of the Non-periodic Transmit Request Queue (NPTxQTop)</br>
            <br>Entry in the Non-periodic Tx Request Queue that is currently being processed by the MAC.</br>
            <br/>
            <br> - Bits [30:27]: Channel/endpoint number</br>
            <br> - Bits [26:25]:</br>
            <br> - 2'b00: IN/OUT token</br>
            <br> -- 2'b01: Zero-length transmit packet (device IN/host OUT)</br>
            <br> -- 2'b10: PING/CSPLIT token</br>
            <br> -- 2'b11: Channel halt command</br>
            <br> - Bit [24]: Terminate (last Entry for selected channel/endpoint)</br>
            <br> Reset: 7'h0</br>
          </comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="ggpio" protect="rw">
        <comment>General Purpose Input/Output Register
The application can use this register for general purpose input/output ports or for debugging.</comment>
        <bits access="r" name="gpi" pos="15:0" rst="0">
          <comment>
            <br/>
            <br>General Purpose Input (GPI)</br>
            <br/>
            <br>This field's read value reflects the gp_i[15:0] core input value.</br>
          </comment>
        </bits>
        <bits access="rw" name="gpo" pos="31:16" rst="0">
          <comment>
            <br/>
            <br>General Purpose Output (GPO)</br>
            <br/>
            <br>This field is driven as an output from the core, gp_o[15:0]. The</br>
            <br>application can program this field to determine the</br>
            <br>corresponding value on the gp_o[15:0] output.</br>
          </comment>
        </bits>
      </reg>
      <reg name="guid" protect="rw">
        <comment>User ID Register
This is a read/write register containing the User ID. It is implemented only if Remove Optional Features? was deselected during coreConsultant configuration (parameter OTG_RM_OPT_FEATURES = 0). The power-on value for this register is specified as the Power-on Value of User ID Register User Identification Register during coreConsultant configuration (parameter OTG_USERID). This register can be used in the following ways:
 - To store the version or revision of your system
 - To store hardware configurations that are outside the DWC_otg core
 - As a scratch register</comment>
        <bits access="rw" name="guid" pos="31:0" rst="2299527168">
          <comment>
            <br>User ID (UserID)</br>
            <br>Application-programmable ID field.</br>
            <br>Reset: Configurable</br>
          </comment>
        </bits>
      </reg>
      <reg name="gsnpsid" protect="r">
        <comment>Synopsys ID Register
This read-only register contains the release number of the core being used.</comment>
        <bits access="r" name="synopsysid" pos="31:0" rst="1330921482">
          <comment>
            <br>Release number of the controller being used currently.</br>
          </comment>
        </bits>
      </reg>
      <reg name="ghwcfg1" protect="r">
        <comment>User Hardware Configuration 1 Register
This register contains the logical endpoint direction(s) selected using coreConsultant.</comment>
        <bits access="r" name="epdir" pos="31:0" rst="0">
          <comment>
            <br>This 32-bit field uses two bits per </br>
            <br>endpoint to determine the endpoint direction.</br>
            <br/>
            <br>Endpoint</br>
            <br> - Bits [31:30]: Endpoint 15 direction</br>
            <br> - Bits [29:28]: Endpoint 14 direction</br>
            <br>...</br>
            <br> - Bits [3:2]: Endpoint 1 direction</br>
            <br> - Bits[1:0]: Endpoint 0 direction (always BIDIR)</br>
            <br>Direction</br>
            <br> - 2'b00: BIDIR (IN and OUT) endpoint</br>
            <br> - 2'b01: IN endpoint</br>
            <br> - 2'b10: OUT endpoint</br>
            <br> - 2'b11: Reserved</br>
            <br>Note: This field is configured using the OTG_EP_DIR_1(n) parameter.</br>
          </comment>
        </bits>
      </reg>
      <reg name="ghwcfg2" protect="r">
        <comment>User Hardware Configuration 2 Register
This register contains configuration options selected using coreConsultant.</comment>
        <bits access="r" name="otgmode" pos="2:0" rst="0">
          <comment>
            <br>Mode of Operation (OtgMode)</br>
            <br> - 3'b000: HNP- and SRP-Capable OTG (Host &amp; Device)</br>
            <br> - 3'b001: SRP-Capable OTG (Host &amp; Device)</br>
            <br> - 3'b010: Non-HNP and Non-SRP Capable OTG (Host and Device)</br>
            <br> - 3'b011: SRP-Capable Device</br>
            <br> - 3'b100: Non-OTG Device</br>
            <br> - 3'b101: SRP-Capable Host</br>
            <br> - 3'b110: Non-OTG Host</br>
            <br> - Others: Reserved</br>
            <br>Note: This field is configured using the OTG_MODE parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="otgarch" pos="4:3" rst="2">
          <comment>
            <br>Architecture (OtgArch)</br>
            <br> - 2'b00: Slave-Only</br>
            <br> - 2'b01: External DMA</br>
            <br> - 2'b10: Internal DMA</br>
            <br> - Others: Reserved</br>
            <br>Note: This field is configured using the OTG_ARCHITECTURE parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="singpnt" pos="5" rst="0">
          <comment>
            <br>Point-to-Point (SingPnt)</br>
            <br> - 1'b0: Multi-point application  (hub and split support)</br>
            <br> - 1'b1: Single-point application (no hub and split support)</br>
            <br>Note: This field is configured using the OTG_SINGLE_POINT parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="hsphytype" pos="7:6" rst="1">
          <comment>
            <br>High-Speed PHY Interface Type (HSPhyType)</br>
            <br> - 2'b00: High-Speed interface not supported</br>
            <br> - 2'b01: UTMI+</br>
            <br> - 2'b10: ULPI</br>
            <br> - 2'b11: UTMI+ and ULPI</br>
            <br>Note: This field is configured using the OTG_HSPHY_INTERFACE parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="fsphytype" pos="9:8" rst="1">
          <comment>
            <br>Full-Speed PHY Interface Type (FSPhyType)</br>
            <br> - 2'b00: Full-speed interface not supported</br>
            <br> - 2'b01: Dedicated full-speed interface</br>
            <br> - 2'b10: FS pins shared with UTMI+ pins</br>
            <br> - 2'b11: FS pins shared with ULPI pins</br>
            <br>Note: This field is configured using the OTG_FSPHY_INTERFACE parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="numdeveps" pos="13:10" rst="12">
          <comment>
            <br>Number of Device Endpoints (NumDevEps)</br>
            <br/>
            <br>Indicates the number of device endpoints supported by the core in Device mode.</br>
            <br/>
            <br>The range of this field is 0-15.</br>
            <br/>
            <br>Note: This field is configured using the OTG_NUM_EPS parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="numhstchnl" pos="17:14" rst="15">
          <comment>
            <br>Number of Host Channels (NumHstChnl)</br>
            <br>Indicates the number of host channels supported by the core in Host mode. The range of this field is 0-15: 0 specifies 1 channel, 15 specifies 16 channels.</br>
            <br/>
            <br>Note: This field is configured using the OTG_NUM_HOST_CHAN parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="periosupport" pos="18" rst="1">
          <comment>
            <br>Periodic OUT Channels Supported in Host Mode (PerioSupport)</br>
            <br> - 1'b0: No</br>
            <br> - 1'b1: Yes</br>
            <br>Note: This field is configured using the OTG_EN_PERIO_HOST parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="dynfifosizing" pos="19" rst="1">
          <comment>
            <br>Dynamic FIFO Sizing Enabled (DynFifoSizing)</br>
            <br> - 1'b0: No</br>
            <br> - 1'b1: Yes</br>
            <br>Note: This field is configured using the OTG_DFIFO_DYNAMIC parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="multiprocintrpt" pos="20" rst="0">
          <comment>
            <br>Multi Processor Interrupt Enabled (MultiProcIntrpt)</br>
            <br> - 1'b0: No</br>
            <br> - 1'b1: Yes</br>
            <br>Note: This field is configured using the OTG_MULTI_PROC_INTRPT parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="nptxqdepth" pos="23:22" rst="2">
          <comment>
            <br>Non-periodic Request Queue Depth (NPTxQDepth)</br>
            <br> - 2'b00: 2</br>
            <br> - 2'b01: 4</br>
            <br> - 2'b10: 8</br>
            <br> - Others: Reserved</br>
            <br>Note: This field is configured using the OTG_NPERIO_TX_QUEUE_DEPTH parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="ptxqdepth" pos="25:24" rst="2">
          <comment>
            <br>Host Mode Periodic Request Queue Depth (PTxQDepth)</br>
            <br> - 2'b00: 2</br>
            <br> - 2'b01: 4</br>
            <br> - 2'b10: 8</br>
            <br> - 2'b11:16</br>
            <br>Note: This field is configured using the OTG_PERIO_TX_QUEUE_DEPTH parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="tknqdepth" pos="30:26" rst="8">
          <comment>
            <br>Device Mode IN Token Sequence Learning Queue Depth (TknQDepth)</br>
            <br>Range: 0-30</br>
            <br/>
            <br>Note: This field is configured using the OTG_TOKEN_QUEUE_DEPTH parameter.</br>
          </comment>
        </bits>
      </reg>
      <reg name="ghwcfg3" protect="r">
        <comment>User Hardware Configuration 3 Register</comment>
        <bits access="r" name="xfersizewidth" pos="3:0" rst="8">
          <comment>
            <br>Width of Transfer Size Counters (XferSizeWidth)</br>
            <br> - 4'b0000: 11 bits</br>
            <br> - 4'b0001: 12 bits</br>
            <br>...</br>
            <br> - 4'b1000: 19 bits</br>
            <br> - Others: Reserved</br>
            <br>Note: This field is configured using the OTG_PACKET_COUNT_WIDTH parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="pktsizewidth" pos="6:4" rst="6">
          <comment>
            <br>Width of Packet Size Counters (PktSizeWidth)</br>
            <br> - 3'b000: 4 bits</br>
            <br> - 3'b001: 5 bits</br>
            <br> - 3'b010: 6 bits</br>
            <br> - 3'b011: 7 bits</br>
            <br> - 3'b100: 8 bits</br>
            <br> - 3'b101: 9 bits</br>
            <br> - 3'b110: 10 bits</br>
            <br> - Others: Reserved</br>
            <br>Note: This field is configured using the OTG_PACKET_COUNT_WIDTH parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="otgen" pos="7" rst="1">
          <comment>
            <br>OTG Function Enabled (OtgEn)</br>
            <br/>
            <br>The application uses this bit to indicate the OTG capabilities of the controller .</br>
            <br> - 1'b0: Not OTG capable</br>
            <br> - 1'b1: OTG Capable</br>
            <br>Note: This field is configured using the OTG_MODE parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="i2cintsel" pos="8" rst="0">
          <comment>
            <br>I2C Selection (I2CIntSel)</br>
            <br> - 1'b0: I2C Interface is not available on the controller.</br>
            <br> - 1'b1: I2C Interface is available on the controller.</br>
            <br>Note: This field is configured using the OTG_I2C_INTERFACE parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="vndctlsupt" pos="9" rst="0">
          <comment>
            <br>Vendor Control Interface Support (VndctlSupt)</br>
            <br/>
            <br> - 1'b0: Vendor Control Interface is not available on the core.</br>
            <br> - 1'b1: Vendor Control Interface is available.</br>
            <br>Note: This field is configured using the OTG_VENDOR_CTL_INTERFACE parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="optfeature" pos="10" rst="0">
          <comment>
            <br>Optional Features Removed (OptFeature)</br>
            <br>Indicates whether the User ID register, GPIO interface ports, and SOF toggle and counter ports were removed for gate count optimization by enabling Remove Optional Features.</br>
            <br> - 1'b0: No</br>
            <br> - 1'b1: Yes</br>
            <br>Note: This field is configured using the OTG_RM_OPT_FEATURES parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="rsttype" pos="11" rst="0">
          <comment>
            <br>Reset Style for Clocked always Blocks in RTL (RstType)</br>
            <br> - 1'b0: Asynchronous reset is used in the controller</br>
            <br> - 1'b1: Synchronous reset is used in the controller</br>
            <br>Note: This field is configured using the OTG_SYNC_RESET_TYPE parameter.</br>
          </comment>
        </bits>
        <bits access="r" name="adpsupport" pos="12" rst="1">
          <comment>
            <br>This bit indicates whether ADP logic is present within or external to the controller</br>
            <br> - 0: No ADP logic present with the controller</br>
            <br> - 1: ADP logic is present along with the controller.</br>
          </comment>
        </bits>
        <bits access="r" name="hsicmode" pos="13" rst="0">
          <comment>
            <br>HSIC mode specified for Mode of Operation</br>
            <br>Value Range: 0 - 1</br>
            <br> - 1: HSIC-capable with shared UTMI PHY interface</br>
            <br> - 0: Non-HSIC-capable</br>
          </comment>
        </bits>
        <bits access="r" name="bcsupport" pos="14" rst="0">
          <comment>
            <br>This bit indicates the controller support for Battery Charger.</br>
            <br> - 0 - No Battery Charger Support</br>
            <br> - 1 - Battery Charger support present</br>
            <br/>
          </comment>
        </bits>
        <bits access="r" name="lpmmode" pos="15" rst="0">
          <comment>
            <br>LPM mode specified for Mode of Operation.</br>
          </comment>
        </bits>
        <bits access="r" name="dfifodepth" pos="31:16" rst="3655">
          <comment>
            <br>DFIFO Depth (DfifoDepth - EP_LOC_CNT)</br>
            <br/>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 32</br>
            <br> - Maximum value is 32,768</br>
            <br>Note: This field is configured using the OTG_DFIFO_DEPTH parameter. For more information on EP_LOC_CNT, see the &quot;Endpoint Information Controller (EPINFO_CTL)&quot; section.</br>
          </comment>
        </bits>
      </reg>
      <reg name="ghwcfg4" protect="r">
        <comment>User Hardware Configuration 4 Register
Note Bit [31] is available only when Scatter/Gather DMA mode is enabled. When Scatter/Gather DMA mode is disabled, this field is reserved.</comment>
        <bits access="r" name="numdevperioeps" pos="3:0" rst="0">
          <comment>
            <br>Number of Device Mode Periodic IN Endpoints (NumDevPerioEps)</br>
            <br/>
            <br>Range: 0-15</br>
          </comment>
        </bits>
        <bits access="r" name="partialpwrdn" pos="4" rst="0">
          <comment>
            <br>Enable Partial Power Down (PartialPwrDn)</br>
            <br> - 1'b0: Partial Power Down Not Enabled</br>
            <br> - 1'b1: Partial Power Down Enabled</br>
          </comment>
        </bits>
        <bits access="r" name="ahbfreq" pos="5" rst="1">
          <comment>
            <br>Minimum AHB Frequency Less Than 60 MHz (AhbFreq)</br>
            <br> - 1'b0: No</br>
            <br> - 1'b1: Yes</br>
          </comment>
        </bits>
        <bits access="r" name="hibernation" pos="6" rst="0">
          <comment>
            <br>Enable Hibernation (Hibernation)</br>
            <br> - 1'b0: Hibernation feature not enabled</br>
            <br> - 1'b1: Hibernation feature enabled</br>
          </comment>
        </bits>
        <bits access="r" name="extendedhibernation" pos="7" rst="0">
          <comment>
            <br>Enable Hibernation</br>
            <br> - 1'b0: Extended Hibernation feature not enabled</br>
            <br> - 1'b1: Extended Hibernation feature enabled</br>
          </comment>
        </bits>
        <bits access="r" name="acgsupt" pos="12" rst="0">
          <comment>
            <br>Active Clock Gating Support</br>
            <br/>
            <br>This bit indicates that the controller supports the Dynamic (Switching) Power Reduction during periods</br>
            <br>when there is no USB and AHB Traffic. </br>
            <br> - 1'b0:  Active Clock Gating is not enabled.</br>
            <br> - 1'b1:  Active Clock Gating Enabled.</br>
            <br/>
          </comment>
        </bits>
        <bits access="r" name="enhancedlpmsupt" pos="13" rst="1">
          <comment>
            <br>Enhanced LPM Support (EnhancedLPMSupt)</br>
            <br/>
            <br>This bit indicates that the controller supports the following behavior:</br>
            <br>L1 Entry Behavior based on FIFO Status</br>
            <br> - TX FIFO</br>
            <br>     - Accept L1 Request even if ISOC OUT TX FIFO is not empty.</br>
            <br>     - Reject L1 Request if Non-Periodic TX FIFO is not empty.</br>
            <br>     - Ensure application can flush the TX FIFO while the Controller is in L1.</br>
            <br> - RX FIFO</br>
            <br>     - Accept L1 Request even if RX FIFO (common to Periodic and Non-Periodic) is not empty.</br>
            <br>     - Accept L1 Request but delay SLEEPM assertion until RX SINK Buffer is empty.</br>
            <br/>
            <br>Prevent L1 Entry if a Control Transfer is in progress on any Control Endpoint.</br>
            <br>Ability to Flush TxFIFO even if PHY Clock is gated.</br>
            <br> </br>
            <br/>
          </comment>
        </bits>
        <bits access="r" name="phydatawidth" pos="15:14" rst="0">
          <comment>
            <br>UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width</br>
            <br>(PhyDataWidth)&lt;vr&gt;When a ULPI PHY is used, an internal wrapper converts ULPI to</br>
            <br>UTMI+.</br>
            <br> - 2'b00: 8 bits</br>
            <br> - 2'b01: 16 bits</br>
            <br> - 2'b10: 8/16 bits, software selectable</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
        <bits access="r" name="numctleps" pos="19:16" rst="0">
          <comment>
            <br>Number of Device Mode Control Endpoints in Addition to</br>
            <br>Endpoint 0 (NumCtlEps)</br>
            <br>Range: 0-15</br>
          </comment>
        </bits>
        <bits access="r" name="iddgfltr" pos="20" rst="1">
          <comment>
            <br>IDDIG Filter Enable (IddgFltr)</br>
            <br> - 1'b0: No filter</br>
            <br> - 1'b1: Filter</br>
          </comment>
        </bits>
        <bits access="r" name="vbusvalidfltr" pos="21" rst="1">
          <comment>
            <br>VBUS Valid Filter Enabled (VBusValidFltr)</br>
            <br> - 1'b0: No filter</br>
            <br> - 1'b1: Filter</br>
          </comment>
        </bits>
        <bits access="r" name="avalidfltr" pos="22" rst="1">
          <comment>
            <br>a_valid Filter Enabled (AValidFltr)</br>
            <br> - 1'b0: No filter</br>
            <br> - 1'b1: Filter</br>
          </comment>
        </bits>
        <bits access="r" name="bvalidfltr" pos="23" rst="1">
          <comment>
            <br>b_valid Filter Enabled (BValidFltr)</br>
            <br> - 1'b0: No filter</br>
            <br> - 1'b1: Filter</br>
          </comment>
        </bits>
        <bits access="r" name="sessendfltr" pos="24" rst="1">
          <comment>
            <br>session_end Filter Enabled (SessEndFltr)</br>
            <br> - 1'b0: No filter</br>
            <br> - 1'b1: Filter</br>
          </comment>
        </bits>
        <bits access="r" name="dedfifomode" pos="25" rst="1">
          <comment>
            <br>Enable Dedicated Transmit FIFO for device IN Endpoints</br>
            <br>(DedFifoMode)</br>
            <br> - 1'b0 : Dedicated Transmit FIFO Operation not enabled.</br>
            <br> - 1'b1 : Dedicated Transmit FIFO Operation enabled.</br>
          </comment>
        </bits>
        <bits access="r" name="ineps" pos="29:26" rst="8">
          <comment>
            <br>Number of Device Mode IN Endpoints Including Control Endpoints (INEps)</br>
            <br> - 0: 1 IN Endpoint</br>
            <br> - 1: 2 IN Endpoints</br>
            <br> ....</br>
            <br> - 15: 16 IN Endpoints</br>
            <br/>
          </comment>
        </bits>
        <bits access="r" name="descdmaenabled" pos="30" rst="1">
          <comment>
            <br>Scatter/Gather DMA configuration</br>
            <br> - 1'b0: Non-Scatter/Gather DMA configuration</br>
            <br> - 1'b1: Scatter/Gather DMA configuration</br>
          </comment>
        </bits>
        <bits access="r" name="descdma" pos="31" rst="1">
          <comment>
            <br>Scatter/Gather DMA configuration</br>
            <br> - 1'b0: Non Dynamic configuration</br>
            <br> - 1'b1: Dynamic configuration</br>
            <br>Note: This field is configured using the OTG_EN_DESC_DMA parameter.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="gpwrdn" protect="rw">
        <comment>Global Power Down register
This is the external Hibernation control register. This register is active only during hibernation and ADP. The application can get the status of the wakeup_logic and control it through this register.</comment>
        <bits access="rw" name="pmuintsel" pos="0" rst="0">
          <comment>
            <br>PMU Interrupt Select (PMUIntSel)</br>
            <br/>
            <br>A write to this bit with 1'b1 enables the PMU to generate interrupts to the application. During this state all interrupts from the DWC_otg_core module are blocked to the application.</br>
            <br/>
            <br>Note: This bit must be set to 1'b1 before the core is put into hibernation.</br>
            <br> - 1'b0: Internal DWC_otg_core interrupt is selected</br>
            <br> - 1'b1: External DWC_otg_pmu interrupt is selected</br>
            <br>Note: This bit must not be written to during normal mode of operation.</br>
          </comment>
        </bits>
        <bits access="rw" name="pmuactv" pos="1" rst="0">
          <comment>
            <br>PMU Active (PMUActv)</br>
            <br/>
            <br>This is bit is to enable or disable the PMU logic.</br>
            <br> - 1'b0: Disable PMU module</br>
            <br> - 1'b1: Enable PMU module</br>
            <br>Note: This bit must not be written to during normal mode of operation.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="pwrdnclmp" pos="3" rst="0">
          <comment>
            <br>Power Down Clamp (PwrDnClmp)</br>
            <br/>
            <br>The application must program this bit to enable or disable the clamps to all the outputs of the core module to prevent the corruption of other active logic.</br>
            <br> - 1'b0: Disable PMU power clamp</br>
            <br> - 1'b1: Enable PMU power clamp</br>
          </comment>
        </bits>
        <bits access="rw" name="pwrdnrst_n" pos="4" rst="1">
          <comment>
            <br>Power Down ResetN (PwrDnRst_n)</br>
            <br/>
            <br>The application must program this bit to reset the core during the Hibernation exit process or during ADP when powering up the core (in case the core was powered off during ADP process).</br>
            <br> - 1'b1: The controller is in normal operation</br>
            <br> - 1'b0: reset the controller</br>
            <br>Note: This bit must not be written to during normal mode of operation.</br>
          </comment>
        </bits>
        <bits access="rw" name="pwrdnswtch" pos="5" rst="0">
          <comment>
            <br>Power Down Switch (PwrDnSwtch)</br>
            <br/>
            <br>This bit indicates to the controller whether the VDD switch is in ON/OFF state.</br>
            <br> - 1'b0: The controller is in ON state</br>
            <br> - 1'b1: The controller is in OFF state</br>
            <br>Note: This bit must not be written to during normal mode of operation.</br>
          </comment>
        </bits>
        <bits access="rw" name="disablevbus" pos="6" rst="0">
          <comment>
            <br>DisableVBUS</br>
            <br/>
            <br>Host Mode:</br>
            <br/>
            <br>The application should program this bit if HPRT0.PrtPwr was programmed to 0 before entering Hibernation. This is to indicate PMU whether session was ended before entering Hibernation.</br>
            <br> - 1'b0: HPRT0.PrtPwr was not programed to 0.</br>
            <br> - 1'b1: HPRT0.PrtPwr was programmed to 0.</br>
            <br>Device Mode:</br>
            <br/>
            <br>The application must program this bit to inform the PMU whether the bvalid valid signal is high (session valid) or low (session end) whenever the core is switched off.</br>
            <br> - 1'b0: bvalid signal is High (Session Valid)</br>
            <br> - 1'b1: bvalid signal is Low (Session End)</br>
            <br>This bit is valid only when GPWRDN.PMUActv is 1.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="srpdetect" pos="15" rst="0">
          <comment>
            <br>SRPDetect</br>
            <br/>
            <br>This field indicates that SRP has been detected by the PMU. This field generates an interrupt. After detecting SRP during hibernation the application should not restore the core. The application should get into the initialization process.</br>
            <br> - 1'b0: SRP not detected</br>
            <br> - 1'b1: SRP detected</br>
          </comment>
        </bits>
        <bits access="rw" name="srpdetectmsk" pos="16" rst="0">
          <comment>
            <br>SRPDetectMsk</br>
            <br/>
            <br>Mask for SRPDetect Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stschngint" pos="17" rst="0">
          <comment>
            <br>Status Change Interrupt (StsChngInt)</br>
            <br/>
            <br>This field indicates a status change in either the IDDIG or BSessVld signal.</br>
            <br> - 1'b0: No Status change</br>
            <br> - 1'b1: Status change detected</br>
            <br>After receiving this interrupt the application should read the GPWRDN register and interpret the change in IDDIG or BSesVld with respect to the previous value stored by the application.</br>
            <br/>
            <br>Note: When Battery Charger is enabled and the ULPI interface is used, if StsChngInt is received and the application reads GPWRDN register and determines that it is because of a change in the value of IDDIG, then StsChngInt may be generated once again within the next few clock cycles.</br>
            <br/>
            <br>This occurs because of an ambiguity in the implementation of Battery Charger Support over the ULPI interface. After receiving the StsChngInt for the second time the application can once again read the GPWRDN register. However, this time the valueIDDIG (or BSesVld) will not have changed. The application then processes the second interrupt but no further action will be required as a result.</br>
          </comment>
        </bits>
        <bits access="rw" name="stschngintmsk" pos="18" rst="0">
          <comment>
            <br>StsChngIntMsk</br>
            <br/>
            <br>Mask for StsChng Interrupt</br>
          </comment>
        </bits>
        <bits access="r" name="linestate" pos="20:19" rst="0">
          <comment>
            <br>LineState</br>
            <br/>
            <br>This field indicates the current linestate on USB as seen by the PMU module.</br>
            <br> - 2'b00: DM = 0, DP = 0.</br>
            <br> - 2'b01: DM = 0, DP = 1.</br>
            <br> - 2'b10: DM = 1, DP = 0.</br>
            <br> - 2'b11: Not-defined.</br>
            <br>This bit is valid only when GPWRDN.PMUActv is 1.</br>
          </comment>
        </bits>
        <bits access="r" name="iddig" pos="21" rst="0">
          <comment>
            <br>This bit indicates the status of the signal IDDIG. The application must read this bit after receiving GPWRDN.StsChngInt and decode based on the previous value stored by the application.</br>
            <br/>
            <br>Indicates the current mode.</br>
            <br> - 1'b0: Host mode</br>
            <br> - 1'b1: Device mode</br>
            <br>This bit is valid only when GPWRDN.PMUActv is 1.</br>
          </comment>
        </bits>
        <bits access="r" name="bsessvld" pos="22" rst="0">
          <comment>
            <br>B Session Valid (BSessVld)</br>
            <br/>
            <br>This field reflects the B session valid status signal from the PHY.</br>
            <br> - 1'b0: B-Valid is 0.</br>
            <br> - 1'b1: B-Valid is 1.</br>
            <br>This bit is valid only when GPWRDN.PMUActv is 1.</br>
          </comment>
        </bits>
        <bits access="rw" name="adpint" pos="23" rst="0">
          <comment>
            <br>ADP Interrupt (ADPInt)</br>
            <br/>
            <br>This bit is set whenever there is a ADP event.</br>
          </comment>
        </bits>
      </reg>
      <reg name="gdfifocfg" protect="rw">
        <comment>Global DFIFO Configuration Register</comment>
        <bits access="rw" name="gdfifocfg" pos="15:0" rst="3759">
          <comment>
            <br>GDFIFOCfg</br>
            <br/>
            <br>This field is for dynamic programming of the DFIFO Size. This value takes effect only when the application programs a non zero value to this register. The value programmed must conform to the guidelines described in 'FIFO RAM Allocation'. The core does not have any corrective logic if the FIFO sizes are programmed incorrectly.</br>
          </comment>
        </bits>
        <bits access="rw" name="epinfobaseaddr" pos="31:16" rst="3655">
          <comment>
            <br>EPInfoBaseAddr	</br>
            <br/>
            <br>This field provides the start address of the EP info controller.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="gadpctl" protect="rw">
        <comment>ADP Timer, Control and Status Register
This register is maintained in the PMU module. These register values are used for deciding the timing values by the ADP controller. This register is available only if the ADP controller logic is present within the HS OTG Controller. If the ADP logic is external to the HS OTG Controller, this register is reserved and the register contents are zero. For more information about ADP controller options, see &quot;ADP Programming Flow when ADP Controller Logic is Supplied with the Core &quot; in the Programming Guide.</comment>
        <bits access="rw" name="prbdschg" pos="1:0" rst="0">
          <comment>
            <br>Probe Discharge (PrbDschg)</br>
            <br/>
            <br>These bits set the times for TADP_DSCHG. These bits are defined as follows:</br>
            <br> - 2'b00:  4 msec (Scaledown  2 32Khz clock cycles)</br>
            <br> - 2'b01:  8 msec (Scaledown  4 32Khz clock cycles)</br>
            <br> - 2'b10:  16 msec (Scaledown  8 32Khz clock cycles)</br>
            <br> - 2'b11:  32 msec (Scaledown  16 32Khz clock cycles)</br>
          </comment>
        </bits>
        <bits access="rw" name="prbdelta" pos="3:2" rst="0">
          <comment>
            <br>Probe Delta (PrbDelta)</br>
            <br/>
            <br>These bits set the resolution for RTIM value. The bits are defined in units of 32 kHz clock cycles as follows:</br>
            <br> - 2'b00: 1 cycles</br>
            <br> - 2'b01: 2 cycles</br>
            <br> - 2'b10: 3 cycles</br>
            <br> - 2'b11: 4 cycles</br>
            <br>For example, if this value is chosen to 2'b01, it means that RTIM increments for every three 32Khz clock cycles.</br>
          </comment>
        </bits>
        <bits access="rw" name="prbper" pos="5:4" rst="0">
          <comment>
            <br>Probe Period (PrbPer)</br>
            <br/>
            <br>These bits sets the TadpPrd as follows:</br>
            <br> - 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)</br>
            <br> - 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)</br>
            <br> - 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)</br>
            <br> - 2'b11 - Reserved</br>
            <br>(PrbPer is also scaledown</br>
            <br> - prb_per== 2'b00 =&gt; 400 ADP clocks</br>
            <br> - prb_per== 2'b01 =&gt; 600 ADP clocks</br>
            <br> - prb_per== 2'b10 =&gt; 800 ADP clocks</br>
            <br> - prb_per==2'b11 =&gt; 1000 ADP clocks)</br>
          </comment>
        </bits>
        <bits access="r" name="rtim" pos="16:6" rst="0">
          <comment>
            <br>RAMP TIME (RTIM)</br>
            <br/>
            <br>These bits capture the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB. The bits are defined in units of 32 kHz clock cycles as follows:</br>
            <br> - 0x000 - 1 cycles</br>
            <br> - 0x001 - 2 cycles</br>
            <br> - 0x002 - 3 cycles, and so on till</br>
            <br> - 0x7FF - 2048 cycles</br>
            <br>A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.</br>
            <br>(Note for scaledown ramp_timeout =</br>
            <br> - prb_delta == 2'b00 =&gt; 200 cycles.</br>
            <br> - prb_delta == 2'b01 =&gt; 100 cycles.</br>
            <br> - prb_delta == 2'b01 =&gt; 50 cycles.</br>
            <br> - prb_delta == 2'b01 =&gt; 25 cycles.)</br>
          </comment>
        </bits>
        <bits access="rw" name="enaprb" pos="17" rst="0">
          <comment>
            <br>Enable Probe (EnaPrb)</br>
            <br/>
            <br>When programmed to 1'b1, the core performs a probe operation. This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).</br>
          </comment>
        </bits>
        <bits access="rw" name="enasns" pos="18" rst="0">
          <comment>
            <br>Enable Sense (EnaSns)</br>
            <br/>
            <br>When programmed to 1'b1, the core performs a sense operation. This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="adpres" pos="19" rst="0">
          <comment>
            <br>ADP Reset (ADPRes)</br>
            <br/>
            <br>When set, ADP controller is reset. This bit is auto-cleared after the reset procedure is complete in ADP controller. This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).</br>
          </comment>
        </bits>
        <bits access="rw" name="adpen" pos="20" rst="0">
          <comment>
            <br>ADP Enable (ADPEn)</br>
            <br/>
            <br>When set, the core performs either ADP probing or sensing based on EnaPrb or EnaSns.</br>
            <br>This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).</br>
          </comment>
        </bits>
        <bits access="rw" name="adpprbint" pos="21" rst="0">
          <comment>
            <br>ADP Probe Interrupt (AdpPrbInt)</br>
            <br/>
            <br>When this bit is set, it means that the VBUS voltage is greater than VADP_PRB or VadpPrb is reached.This bit is valid only if OTGVer = 1'b1 (GOTGCTL[20]).</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="adpsnsint" pos="22" rst="0">
          <comment>
            <br>ADP Sense Interrupt (AdpSnsInt)</br>
            <br/>
            <br>When this bit is set, it means that the VBUS voltage is greater than VadpSns value or VadpSns is reached.This bit is valid only if OTGVer = 1'b1 (GOTGCTL[20]).</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="adptoutint" pos="23" rst="0">
          <comment>
            <br>ADP Timeout Interrupt (AdpToutInt)</br>
            <br/>
            <br>This bit is relevant only for an ADP probe. When this bit is set, it means that the ramp time has completed (GADPCTL.RTIM has reached its terminal value of 0x7FF). This is a debug feature that allows software to read the ramp time after each cycle. This bit is valid only if OTGVer = 1'b1.</br>
          </comment>
        </bits>
        <bits access="rw" name="adpprbintmsk" pos="24" rst="0">
          <comment>
            <br>ADP Probe Interrupt (AdpPrbInt)</br>
            <br/>
            <br>This bit is relevant only for an ADP probe. When this bit is set, it means that the ramp time has completed (GADPCTL.RTIM has reached its terminal value of 0x7FF). This is a debug feature that allows software to read the ramp time after each cycle. This bit is valid only if OTGVer = 1'b1.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="adpsnsintmsk" pos="25" rst="0">
          <comment>
            <br>ADP Sense Interrupt Mask (AdpSnsIntMsk)</br>
            <br/>
            <br>When this bit is set, it unmasks the interrupt due to AdpSnsInt. This bit is valid only if OTG_Ver = 1'b1(GOTGCTL[20]).</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="adptoutmsk" pos="26" rst="0">
          <comment>
            <br>ADP Timeout Interrupt Mask (AdpToutMsk)</br>
            <br/>
            <br>When this bit is set, it unmasks the interrupt because of AdpTmouInt. This bit is valid only if OTG_Ver = 1'b1(GOTGCTL[20]).</br>
          </comment>
        </bits>
        <bits access="rw" name="ar" pos="28:27" rst="0">
          <comment>
            <br>Access Request (AR)</br>
            <br> - 2'b00  Read/Write Valid (updated by the core)</br>
            <br> - 2'b01  Read</br>
            <br> - 2'b10  Write</br>
            <br> - 2'b11 - Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="1248"/>
      <reg name="hptxfsiz" protect="rw">
        <comment>Host Periodic Transmit FIFO Size Register
This register holds the size and the memory start address of the Periodic TxFIFO.
Note: Read the reset value of this register only after the following conditions:
 - If IDDIG_FILTER is disabled, read only after PHY clock is stable.
 - If IDDIG_FILTER is enabled, read only after the filter timer expires.</comment>
        <bits access="rw" name="ptxfstaddr" pos="12:0" rst="7518">
          <comment>
            <br>Host Periodic TxFIFO Start Address (PTxFStAddr)</br>
            <br/>
            <br>The power-on reset value of this register is the sum of the Largest Rx Data FIFO Depth and Largest Non-periodic Tx Data FIFO Depth.These parameters are:</br>
            <br/>
            <br> In shared FIFO operation:</br>
            <br> - OTG_RX_DFIFO_DEPTH + OTG_TX_NPERIO_DFIFO_DEPTH </br>
            <br/>
            <br> In dedicated FIFO mode:</br>
            <br> - OTG_RX_DFIFO_DEPTH + OTG_TX_HNPERIO_DFIFO_DEPTH If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value. If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field.</br>
            <br/>
            <br>Programmed values must not exceed the power-on value set in coreConsultant.</br>
          </comment>
        </bits>
        <bits access="rw" name="ptxfsize" pos="27:16" rst="3759">
          <comment>
            <br>Host Periodic TxFIFO Depth (PTxFSize)</br>
            <br/>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>The power-on reset value of this register is specified as the Largest Host Mode Periodic Tx Data FIFO Depth. </br>
            <br> - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.</br>
            <br> - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. </br>
            <br>Programmed values must not exceed the power-on value set in coreConsultant.</br>
          </comment>
        </bits>
      </reg>
      <reg name="dieptxf1" protect="rw">
        <comment>Device IN Endpoint Transmit FIFO Size Register $i
This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.</comment>
        <bits access="rw" name="inepntxfstaddr" pos="11:0" rst="3791">
          <comment>
            <br>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</br>
            <br/>
            <br>This field contains the memory start address for IN endpoint Transmit FIFOn (0&lt;n&lt; = 15).</br>
            <br>The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n  1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.</br>
            <br> - If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.</br>
            <br> - If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepntxfdep" pos="25:16" rst="768">
          <comment>
            <br>IN Endpoint TxFIFO Depth (INEPnTxFDep)</br>
            <br/>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 &lt; i &lt;= 15).</br>
            <br> - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.</br>
            <br> - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .</br>
            <br>Programmed values must not exceed the power-on value</br>
          </comment>
        </bits>
      </reg>
      <reg name="dieptxf2" protect="rw">
        <comment>Device IN Endpoint Transmit FIFO Size Register $i
This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.</comment>
        <bits access="rw" name="inepntxfstaddr" pos="12:0" rst="4559">
          <comment>
            <br>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</br>
            <br/>
            <br>This field contains the memory start address for IN endpoint Transmit FIFOn (0&lt;n&lt; = 15).</br>
            <br>The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n  1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.</br>
            <br> - If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.</br>
            <br> - If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepntxfdep" pos="25:16" rst="768">
          <comment>
            <br>IN Endpoint TxFIFO Depth (INEPnTxFDep)</br>
            <br/>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 &lt; i &lt;= 15).</br>
            <br> - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.</br>
            <br> - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .</br>
            <br>Programmed values must not exceed the power-on value</br>
          </comment>
        </bits>
      </reg>
      <reg name="dieptxf3" protect="rw">
        <comment>Device IN Endpoint Transmit FIFO Size Register $i
This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.</comment>
        <bits access="rw" name="inepntxfstaddr" pos="12:0" rst="5327">
          <comment>
            <br>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</br>
            <br/>
            <br>This field contains the memory start address for IN endpoint Transmit FIFOn (0&lt;n&lt; = 15).</br>
            <br>The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n  1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.</br>
            <br> - If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.</br>
            <br> - If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepntxfdep" pos="24:16" rst="256">
          <comment>
            <br>IN Endpoint TxFIFO Depth (INEPnTxFDep)</br>
            <br/>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 &lt; i &lt;= 15).</br>
            <br> - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.</br>
            <br> - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .</br>
            <br>Programmed values must not exceed the power-on value</br>
          </comment>
        </bits>
      </reg>
      <reg name="dieptxf4" protect="rw">
        <comment>Device IN Endpoint Transmit FIFO Size Register $i
This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.</comment>
        <bits access="rw" name="inepntxfstaddr" pos="12:0" rst="5583">
          <comment>
            <br>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</br>
            <br/>
            <br>This field contains the memory start address for IN endpoint Transmit FIFOn (0&lt;n&lt; = 15).</br>
            <br>The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n  1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.</br>
            <br> - If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.</br>
            <br> - If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepntxfdep" pos="24:16" rst="256">
          <comment>
            <br>IN Endpoint TxFIFO Depth (INEPnTxFDep)</br>
            <br/>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 &lt; i &lt;= 15).</br>
            <br> - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.</br>
            <br> - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .</br>
            <br>Programmed values must not exceed the power-on value</br>
          </comment>
        </bits>
      </reg>
      <reg name="dieptxf5" protect="rw">
        <comment>Device IN Endpoint Transmit FIFO Size Register $i
This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.</comment>
        <bits access="rw" name="inepntxfstaddr" pos="12:0" rst="5839">
          <comment>
            <br>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</br>
            <br/>
            <br>This field contains the memory start address for IN endpoint Transmit FIFOn (0&lt;n&lt; = 15).</br>
            <br>The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n  1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.</br>
            <br> - If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.</br>
            <br> - If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepntxfdep" pos="24:16" rst="256">
          <comment>
            <br>IN Endpoint TxFIFO Depth (INEPnTxFDep)</br>
            <br/>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 &lt; i &lt;= 15).</br>
            <br> - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.</br>
            <br> - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .</br>
            <br>Programmed values must not exceed the power-on value</br>
          </comment>
        </bits>
      </reg>
      <reg name="dieptxf6" protect="rw">
        <comment>Device IN Endpoint Transmit FIFO Size Register $i
This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.</comment>
        <bits access="rw" name="inepntxfstaddr" pos="12:0" rst="6095">
          <comment>
            <br>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</br>
            <br/>
            <br>This field contains the memory start address for IN endpoint Transmit FIFOn (0&lt;n&lt; = 15).</br>
            <br>The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n  1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.</br>
            <br> - If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.</br>
            <br> - If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepntxfdep" pos="24:16" rst="256">
          <comment>
            <br>IN Endpoint TxFIFO Depth (INEPnTxFDep)</br>
            <br/>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 &lt; i &lt;= 15).</br>
            <br> - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.</br>
            <br> - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .</br>
            <br>Programmed values must not exceed the power-on value</br>
          </comment>
        </bits>
      </reg>
      <reg name="dieptxf7" protect="rw">
        <comment>Device IN Endpoint Transmit FIFO Size Register $i
This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.</comment>
        <bits access="rw" name="inepntxfstaddr" pos="12:0" rst="6351">
          <comment>
            <br>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</br>
            <br/>
            <br>This field contains the memory start address for IN endpoint Transmit FIFOn (0&lt;n&lt; = 15).</br>
            <br>The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n  1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.</br>
            <br> - If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.</br>
            <br> - If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepntxfdep" pos="24:16" rst="256">
          <comment>
            <br>IN Endpoint TxFIFO Depth (INEPnTxFDep)</br>
            <br/>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 &lt; i &lt;= 15).</br>
            <br> - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.</br>
            <br> - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .</br>
            <br>Programmed values must not exceed the power-on value</br>
          </comment>
        </bits>
      </reg>
      <reg name="dieptxf8" protect="rw">
        <comment>Device IN Endpoint Transmit FIFO Size Register $i
This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.</comment>
        <bits access="rw" name="inepntxfstaddr" pos="12:0" rst="6607">
          <comment>
            <br>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</br>
            <br/>
            <br>This field contains the memory start address for IN endpoint Transmit FIFOn (0&lt;n&lt; = 15).</br>
            <br>The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n  1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.</br>
            <br> - If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.</br>
            <br> - If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepntxfdep" pos="24:16" rst="256">
          <comment>
            <br>IN Endpoint TxFIFO Depth (INEPnTxFDep)</br>
            <br/>
            <br>This value is in terms of 32-bit words.</br>
            <br> - Minimum value is 16</br>
            <br> - Maximum value is 32,768</br>
            <br>The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 &lt; i &lt;= 15).</br>
            <br> - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.</br>
            <br> - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .</br>
            <br>Programmed values must not exceed the power-on value</br>
          </comment>
        </bits>
      </reg>
      <hole size="5856"/>
      <reg name="hcfg" protect="rw">
        <comment>Host Configuration Register</comment>
        <bits access="rw" name="fslspclksel" pos="1:0" rst="0">
          <comment>
            <br>FS/LS PHY Clock Select (FSLSPclkSel)</br>
            <br/>
            <br>When the core is in FS Host mode</br>
            <br> - 2'b00: PHY clock is running at 30/60 MHz</br>
            <br> - 2'b01: PHY clock is running at 48 MHz</br>
            <br> - Others: Reserved</br>
            <br>When the core is in LS Host mode</br>
            <br> - 2'b00: PHY clock is running at 30/60 MHz. When the UTMI+/ULPI PHY Low Power mode is not selected, use 30/60 MHz.</br>
            <br> - 2'b01: PHY clock is running at 48 MHz. When the UTMI+ PHY Low Power mode is selected, use 48MHz If the PHY supplies a 48 MHz clock during LS mode.</br>
            <br> - 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode, use 6 MHz when the UTMI+ PHY Low Power mode is selected and the PHY supplies a 6 MHz clock during LS mode. If you select a 6 MHz clock during LS mode, you must do a soft reset.</br>
            <br> - 2'b11: Reserved</br>
            <br>Notes:</br>
            <br> - When Core in FS mode, the internal and external clocks have the same frequency.</br>
            <br> - When Core in LS mode,</br>
            <br> -- If FSLSPclkSel = 2'b00: Internal and external clocks have the same frequency</br>
            <br> -- If FSLSPclkSel = 2'b10: Internal clock is the divided by eight version of external 48 MHz clock</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="fslssupp" pos="2" rst="0">
          <comment>
            <br>FS- and LS-Only Support (FSLSSupp)</br>
            <br/>
            <br>The application uses this bit to control the core's enumeration speed. Using this bit, the application can make the core</br>
            <br>enumerate as a FS host, even If the connected device supports HS traffic. Do not make changes to this field after initial</br>
            <br>programming.</br>
            <br> - 1'b0: HS/FS/LS, based on the maximum speed supported by the connected device</br>
            <br> - 1'b1: FS/LS-only, even If the connected device can support HS</br>
          </comment>
        </bits>
        <bits access="rw" name="ena32khzs" pos="7" rst="0">
          <comment>
            <br>Enable 32 KHz Suspend mode (Ena32KHzS)</br>
            <br/>
            <br>This bit can be set only in FS PHY interface is selected. </br>
            <br>Else, this bit needs to be set to zero. </br>
            <br>When FS PHY interface is chosen and this bit is set, </br>
            <br>the core expects that the PHY clock during Suspend is switched </br>
            <br>from 48 MHz to 32 KHz.</br>
          </comment>
        </bits>
        <bits access="rw" name="resvalid" pos="15:8" rst="2">
          <comment>
            <br>Resume Validation Period  (ResValid)</br>
            <br/>
            <br>This field is effective only when HCFG.Ena32KHzS is set.</br>
            <br>It will control the resume period when the core resumes from suspend. </br>
            <br>The core counts for 'ResValid' number of clock cycles to detect a </br>
            <br>valid resume when this is set.</br>
          </comment>
        </bits>
        <bits access="rw" name="descdma" pos="23" rst="0">
          <comment>
            <br>Enable Scatter/gather DMA in Host mode (DescDMA)</br>
            <br/>
            <br>When the Scatter/Gather DMA option selected during configuration of the RTL, the application can set this bit during initialization</br>
            <br>to enable the Scatter/Gather DMA operation.</br>
            <br/>
            <br>Note: This bit must be modified only once after a reset.</br>
            <br/>
            <br>The following combinations are available for programming:</br>
            <br> - GAHBCFG.DMAEn=0,HCFG.DescDMA=0 =&gt; Slave mode </br>
            <br> - GAHBCFG.DMAEn=0,HCFG.DescDMA=1 =&gt; Invalid</br>
            <br> - GAHBCFG.DMAEn=1,HCFG.DescDMA=0 =&gt; Buffered DMA mode </br>
            <br> - GAHBCFG.DMAEn=1,HCFG.DescDMA=1 =&gt; Scatter/Gather DMA mode</br>
          </comment>
        </bits>
        <bits access="rw" name="frlisten" pos="25:24" rst="0">
          <comment>
            <br>Frame List Entries(FrListEn)</br>
            <br/>
            <br>The value in the register specifies the number of entries in the Frame list.</br>
            <br>This field is valid only in Scatter/Gather DMA mode.</br>
            <br> - 2'b00: 8 Entries </br>
            <br> - 2'b01: 16 Entries</br>
            <br> - 2'b10: 32 Entries</br>
            <br> - 2'b11: 64 Entries</br>
          </comment>
        </bits>
        <bits access="rw" name="perschedena" pos="26" rst="0">
          <comment>
            <br>Enable Periodic Scheduling (PerSchedEna):</br>
            <br/>
            <br>Applicable in host DDMA mode only.</br>
            <br>Enables periodic scheduling within the core. Initially, the bit is reset.</br>
            <br>The core will not process any periodic channels.</br>
            <br/>
            <br>As soon as this bit is set,</br>
            <br>the core will get ready to start scheduling periodic channels and </br>
            <br>sets HCFG.PerSchedStat. The setting of HCFG.PerSchedStat indicates the core</br>
            <br>has enabled periodic scheduling. Once HCFG.PerSchedEna is set, </br>
            <br>the application is not supposed to again reset the bit unless HCFG.PerSchedStat</br>
            <br>is set.</br>
            <br/>
            <br>As soon as this bit is reset, the core will get ready to</br>
            <br>stop scheduling periodic channels and resets HCFG.PerSchedStat.</br>
          </comment>
        </bits>
        <bits access="rw" name="modechtimen" pos="31" rst="0">
          <comment>
            <br>Mode Change Ready Timer Enable (ModeChTimEn)</br>
            <br/>
            <br>This bit is used to enable/disable the Host core to wait  200 PHY clock cycles at the end of Resume to change the opmode signal to the PHY to 00 </br>
            <br>after Suspend or LPM.</br>
            <br> - 1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end of resume to the change the opmode from 2'b10 to 2'b00</br>
            <br> - 1'b1 : The Host core waits only for a linstate of SE0 at the end of resume to change the opmode from 2'b10 to 2'b00.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hfir" protect="rw">
        <comment>Host Frame Interval Register</comment>
        <bits access="rw" name="frint" pos="15:0" rst="60000">
          <comment>
            <br>Frame Interval (FrInt)</br>
            <br/>
            <br>The value that the application programs to this field specifies</br>
            <br>the interval between two consecutive SOFs (FS) or micro-</br>
            <br>SOFs (HS) or Keep-Alive tokens (HS). This field contains the</br>
            <br>number of PHY clocks that constitute the required frame</br>
            <br>interval. The Default value set in this field  is for FS operation</br>
            <br>when the PHY clock frequency is 60 MHz. The application can</br>
            <br>write a value to this register only after the Port Enable bit of the</br>
            <br>Host Port Control and Status register (HPRT.PrtEnaPort) has</br>
            <br>been Set. If no value is programmed, the core calculates the</br>
            <br>value based on the PHY clock specified in the FS/LS PHY</br>
            <br>Clock Select field of the Host Configuration register</br>
            <br>(HCFG.FSLSPclkSel). Do not change the value of this field</br>
            <br>after the initial configuration.</br>
            <br> - 125 s * (PHY clock frequency for HS)</br>
            <br> - 1 ms * (PHY clock frequency for FS/LS)</br>
          </comment>
        </bits>
        <bits access="rw" name="hfirrldctrl" pos="16" rst="0">
          <comment>
            <br>Reload Control (HFIRRldCtrl)</br>
            <br/>
            <br>This bit allows dynamic reloading of the HFIR register during run time. </br>
            <br> - 1'b0 : The HFIR cannot be reloaded dynamically</br>
            <br> - 1'b1: the HFIR can be dynamically reloaded during runtime. </br>
            <br>This bit needs to be programmed during initial configuration and its value should not be changed during runtime. </br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="hfnum" protect="r">
        <comment>Host Frame Number/Frame Time Remaining Register
This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current (micro)frame.
Note: Read the reset value of this register only after the following conditions:
 - If IDDIG_FILTER is disabled, read only when the PHY clock is stable.
 - If IDDIG_FILTER is enabled, read only after the filter timer expires.</comment>
        <bits access="r" name="frnum" pos="15:0" rst="16383">
          <comment>
            <br>Frame Number (FrNum)</br>
            <br/>
            <br>This field increments when a new SOF is transmitted on the</br>
            <br>USB, and is reset to 0 when it reaches 16'h3FFF.</br>
            <br/>
          </comment>
        </bits>
        <bits access="r" name="frrem" pos="31:16" rst="0">
          <comment>
            <br>Frame Time Remaining (FrRem)</br>
            <br/>
            <br>Indicates the amount of time remaining in the current</br>
            <br>microframe (HS) or Frame (FS/LS), in terms of PHY clocks. This</br>
            <br>field decrements on each PHY clock. When it reaches zero, this</br>
            <br>field is reloaded with the value in the Frame Interval register and</br>
            <br>a new SOF is transmitted on the USB.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hptxsts" protect="r">
        <comment>Host Periodic Transmit FIFO/Queue Status Register</comment>
        <bits access="r" name="ptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>Periodic Transmit Data FIFO Space Available (PTxFSpcAvail)</br>
            <br/>
            <br>Indicates the number of free locations available to be written to in the Periodic TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words</br>
            <br> - 16'h0    : Periodic TxFIFO is full</br>
            <br> - 16'h1    : 1 word available</br>
            <br> - 16'h2    : 2 words available</br>
            <br> - 16'hn    : n words available (where 0  n  32,768)</br>
            <br> - 16'h8000 : 32,768 words</br>
            <br> - Others   : Reserved</br>
          </comment>
        </bits>
        <bits access="r" name="ptxqspcavail" pos="23:16" rst="8">
          <comment>
            <br>Periodic Transmit Request Queue Space Available (PTxQSpcAvail)</br>
            <br/>
            <br>Indicates the number of free locations available to be written in the Periodic Transmit Request Queue. This queue holds both IN and OUT requests.</br>
            <br> - 8'h0: Periodic Transmit Request Queue is full</br>
            <br> - 8'h1: 1 location available</br>
            <br> - 8'h2: 2 locations available</br>
            <br> - n: n locations available (0 &lt;= n &lt;= 16)</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
        <bits access="r" name="ptxqtop" pos="31:24" rst="0">
          <comment>
            <br>Top of the Periodic Transmit Request Queue (PTxQTop)</br>
            <br/>
            <br>This indicates the Entry in the Periodic Tx Request Queue that is</br>
            <br>currently being processes by the MAC.</br>
            <br/>
            <br>This register is used for debugging.</br>
            <br> - Bit [31]: Odd/Even (micro)Frame</br>
            <br> -- 1'b0: send in even (micro)Frame</br>
            <br> -- 1'b1: send in odd (micro)Frame</br>
            <br> - Bits [30:27]: Channel/endpoint number</br>
            <br> - Bits [26:25]: Type</br>
            <br> -- 2'b00: IN/OUT</br>
            <br> -- 2'b01: Zero-length packet</br>
            <br> -- 2'b10: CSPLIT</br>
            <br> -- 2'b11: Disable channel command</br>
            <br> - Bit [24]: Terminate (last Entry for the selected channel/endpoint)</br>
          </comment>
        </bits>
      </reg>
      <reg name="haint" protect="r">
        <comment>Host All Channels Interrupt Register
When a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the application using the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt). This is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Host Channel-n Interrupt register.</comment>
        <bits access="r" name="haint" pos="15:0" rst="0">
          <comment>
            <br/>
            <br>Channel Interrupt for channel no.</br>
          </comment>
        </bits>
      </reg>
      <reg name="haintmsk" protect="rw">
        <comment>Host All Channels Interrupt Mask Register
The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.</comment>
        <bits access="rw" name="haintmsk" pos="15:0" rst="0">
          <comment>
            <br>Channel Interrupt Mask (HAINTMsk)</br>
            <br>One bit per channel: Bit 0 for channel 0, bit 15 for channel 15</br>
          </comment>
        </bits>
      </reg>
      <reg name="hflbaddr" protect="rw">
        <comment>Host Frame List Base Address Register
This register is present only in case of Scatter/Gather DMA. It is implemented as flops. This register holds the starting address of the Frame list information.</comment>
        <bits access="rw" name="hflbaddr" pos="31:0" rst="0">
          <comment>
            <br>The starting address of the Frame list.</br>
            <br>This register is used only for Isochronous and Interrupt Channels.</br>
          </comment>
        </bits>
      </reg>
      <hole size="256"/>
      <reg name="hprt" protect="rw">
        <comment>Host Port Control and Status Register
This register is available only in Host mode. Currently, the OTG Host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The R_SS_WC bits in this register can trigger an interrupt to the application through the Host Port Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit to clear the interrupt.</comment>
        <bits access="r" name="prtconnsts" pos="0" rst="0">
          <comment>
            <br>Port Connect Status (PrtConnSts)</br>
            <br> - 0: No device is attached to the port.</br>
            <br> - 1: A device is attached to the port.</br>
          </comment>
        </bits>
        <bits access="rw" name="prtconndet" pos="1" rst="0">
          <comment>
            <br>Port Connect Detected (PrtConnDet)</br>
            <br/>
            <br>The core sets this bit when a device connection is detected</br>
            <br>to trigger an interrupt to the application using the Host Port</br>
            <br>Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).This bit can be set only by the core and the application should write 1 to clear it.The application must write a 1 to this bit to clear the</br>
            <br>interrupt.</br>
          </comment>
        </bits>
        <bits access="rw" name="prtena" pos="2" rst="0">
          <comment>
            <br>Port Enable (PrtEna)</br>
            <br/>
            <br>A port is enabled only by the core after a reset sequence,</br>
            <br>and is disabled by an overcurrent condition, a disconnect</br>
            <br>condition, or by the application clearing this bit. The</br>
            <br>application cannot Set this bit by a register write. It can only</br>
            <br>clear it to disable the port by writing 1. This bit does not trigger any</br>
            <br>interrupt to the application.</br>
            <br> - 1'b0: Port disabled</br>
            <br> - 1'b1: Port enabled</br>
          </comment>
        </bits>
        <bits access="rw" name="prtenchng" pos="3" rst="0">
          <comment>
            <br>Port Enable/Disable Change (PrtEnChng)</br>
            <br/>
            <br>The core sets this bit when the status of the Port Enable bit [2] of this register changes.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="r" name="prtovrcurract" pos="4" rst="0">
          <comment>
            <br>Port Overcurrent Active (PrtOvrCurrAct)</br>
            <br/>
            <br>Indicates the overcurrent condition of the port.</br>
            <br> - 1'b0: No overcurrent condition</br>
            <br> - 1'b1: Overcurrent condition</br>
          </comment>
        </bits>
        <bits access="rw" name="prtovrcurrchng" pos="5" rst="0">
          <comment>
            <br>Port Overcurrent Change (PrtOvrCurrChng)</br>
            <br/>
            <br>The core sets this bit when the status of the Port Overcurrent Active bit (bit 4) in this register changes.This bit can be set only by the core and the application should write 1 to clear it</br>
          </comment>
        </bits>
        <bits access="rw" name="prtres" pos="6" rst="0">
          <comment>
            <br>Port Resume (PrtRes)</br>
            <br/>
            <br>The application sets this bit to drive resume signaling on the</br>
            <br>port. The core continues to drive the resume signal until the</br>
            <br>application clears this bit.</br>
            <br/>
            <br>If the core detects a USB remote wakeup sequence, as</br>
            <br>indicated by the Port Resume/Remote Wakeup Detected</br>
            <br>Interrupt bit of the Core Interrupt register</br>
            <br>(GINTSTS.WkUpInt), the core starts driving resume</br>
            <br>signaling without application intervention and clears this bit</br>
            <br>when it detects a disconnect condition. The read value of</br>
            <br>this bit indicates whether the core is currently driving</br>
            <br>resume signaling.</br>
            <br> - 1'b0: No resume driven</br>
            <br> - 1'b1: Resume driven</br>
            <br>When LPM is enabled, In L1 state the behavior of this bit is as follows:</br>
            <br>The application sets this bit to drive resume signaling on the port.</br>
            <br>The core continues to drive the resume signal until a pre-determined time</br>
            <br>specified in GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote</br>
            <br>wakeup sequence, as indicated by the Port L1Resume/Remote L1Wakeup Detected </br>
            <br>Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt), </br>
            <br>the core starts driving resume signaling without application intervention</br>
            <br>and clears this bit at the end of resume.This bit can be set by both core or application</br>
            <br>and also cleared by core or application. This bit is cleared by the core even if there is</br>
            <br>no device connected to the Host.</br>
          </comment>
        </bits>
        <bits access="rw" name="prtsusp" pos="7" rst="0">
          <comment>
            <br>Port Suspend (PrtSusp)</br>
            <br/>
            <br>The application sets this bit to put this port in Suspend</br>
            <br>mode. The core only stops sending SOFs when this is Set.</br>
            <br>To stop the PHY clock, the application must Set the Port</br>
            <br>Clock Stop bit, which asserts the suspend input pin of the</br>
            <br>PHY.</br>
            <br/>
            <br>The read value of this bit reflects the current suspend status</br>
            <br>of the port. This bit is cleared by the core after a remote</br>
            <br>wakeup signal is detected or the application sets the Port</br>
            <br>Reset bit or Port Resume bit in this register or the</br>
            <br>Resume/Remote Wakeup Detected Interrupt bit or</br>
            <br>Disconnect Detected Interrupt bit in the Core Interrupt</br>
            <br>register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,</br>
            <br>respectively).This bit is cleared by the core even if there is</br>
            <br>no device connected to the Host.</br>
            <br> - 1'b0: Port not in Suspend mode</br>
            <br> - 1'b1: Port in Suspend mode</br>
          </comment>
        </bits>
        <bits access="rw" name="prtrst" pos="8" rst="0">
          <comment>
            <br>Port Reset (PrtRst)</br>
            <br/>
            <br>When the application sets this bit, a reset sequence is</br>
            <br>started on this port. The application must time the reset</br>
            <br>period and clear this bit after the reset sequence is</br>
            <br>complete.</br>
            <br> - 1'b0: Port not in reset</br>
            <br> - 1'b1: Port in reset</br>
            <br>The application must leave this bit set for at least a</br>
            <br>minimum duration mentioned below to start a reset on the</br>
            <br>port. The application can leave it set for another 10 ms in</br>
            <br>addition to the required minimum duration, before clearing</br>
            <br>the bit, even though there is no maximum limit Set by the</br>
            <br>USB standard.This bit is cleared by the core even if there is</br>
            <br>no device connected to the Host.</br>
            <br> - High speed: 50 ms</br>
            <br> - Full speed/Low speed: 10 ms</br>
          </comment>
        </bits>
        <bits access="r" name="prtlnsts" pos="11:10" rst="0">
          <comment>
            <br>Port Line Status (PrtLnSts)</br>
            <br/>
            <br>Indicates the current logic level USB data lines</br>
            <br> - Bit [10]: Logic level of D+</br>
            <br> - Bit [11]: Logic level of D-</br>
          </comment>
        </bits>
        <bits access="rw" name="prtpwr" pos="12" rst="0">
          <comment>
            <br>Port Power (PrtPwr)</br>
            <br/>
            <br>The application uses this field to control power to this port (write 1'b1 to set to 1'b1</br>
            <br>and write 1'b0 to set to 1'b0), and the core can clear this bit on an over current</br>
            <br>condition.</br>
            <br> - 1'b0: Power off</br>
            <br> - 1'b1: Power on</br>
            <br/>
            <br>Note: This bit is interface independent. The application needs to program this bit for all interfaces as described in the host programming flow in the Programming Guide.</br>
          </comment>
        </bits>
        <bits access="rw" name="prttstctl" pos="16:13" rst="0">
          <comment>
            <br>Port Test Control (PrtTstCtl)</br>
            <br/>
            <br>The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port.</br>
            <br> - 4'b0000: Test mode disabled</br>
            <br> - 4'b0001: Test_J mode</br>
            <br> - 4'b0010: Test_K mode</br>
            <br> - 4'b0011: Test_SE0_NAK mode</br>
            <br> - 4'b0100: Test_Packet mode</br>
            <br> - 4'b0101: Test_Force_Enable</br>
            <br> - Others: Reserved</br>
            <br/>
            <br>To move the DWC_otg controller to test mode, you must set this field. Complete the following steps to move the DWC_otg core to test mode:</br>
            <br> - 1. Power on the core.</br>
            <br> - 2. Load the DWC_otg driver.</br>
            <br> - 3. Connect an HS device and enumerate to HS mode.</br>
            <br> - 4. Access the HPRT register to send test packets.</br>
            <br> - 5. Remove the device and connect to fixture (OPT) port. The DWC_otg host core continues sending out test packets.</br>
            <br> - 6. Test the eye diagram.</br>
          </comment>
        </bits>
        <bits access="r" name="prtspd" pos="18:17" rst="0">
          <comment>
            <br>Port Speed (PrtSpd)</br>
            <br/>
            <br>Indicates the speed of the device attached to this port.</br>
            <br> - 2'b00: High speed</br>
            <br> - 2'b01: Full speed</br>
            <br> - 2'b10: Low speed</br>
            <br> - 2'b11: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="1504"/>
      <reg name="hcchar0" protect="rw">
        <comment>Host Channel 0 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt0" protect="rw">
        <comment>Host Channel 0 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint0" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk0" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz0" protect="rw">
        <comment>Host Channel 0 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma0" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab0" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar1" protect="rw">
        <comment>Host Channel 1 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt1" protect="rw">
        <comment>Host Channel 1 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint1" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk1" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz1" protect="rw">
        <comment>Host Channel 1 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma1" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab1" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar2" protect="rw">
        <comment>Host Channel 2 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt2" protect="rw">
        <comment>Host Channel 2 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint2" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk2" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz2" protect="rw">
        <comment>Host Channel 2 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma2" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab2" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar3" protect="rw">
        <comment>Host Channel 3 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt3" protect="rw">
        <comment>Host Channel 3 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint3" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk3" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz3" protect="rw">
        <comment>Host Channel 3 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma3" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab3" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar4" protect="rw">
        <comment>Host Channel 4 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt4" protect="rw">
        <comment>Host Channel 4 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint4" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk4" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz4" protect="rw">
        <comment>Host Channel 4 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma4" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab4" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar5" protect="rw">
        <comment>Host Channel 5 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt5" protect="rw">
        <comment>Host Channel 5 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint5" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk5" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz5" protect="rw">
        <comment>Host Channel 5 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma5" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab5" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar6" protect="rw">
        <comment>Host Channel 6 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt6" protect="rw">
        <comment>Host Channel 6 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint6" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk6" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz6" protect="rw">
        <comment>Host Channel 6 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma6" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab6" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar7" protect="rw">
        <comment>Host Channel 7 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt7" protect="rw">
        <comment>Host Channel 7 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint7" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk7" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz7" protect="rw">
        <comment>Host Channel 7 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma7" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab7" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar8" protect="rw">
        <comment>Host Channel 8 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt8" protect="rw">
        <comment>Host Channel 8 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint8" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk8" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz8" protect="rw">
        <comment>Host Channel 8 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma8" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab8" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar9" protect="rw">
        <comment>Host Channel 9 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt9" protect="rw">
        <comment>Host Channel 9 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint9" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk9" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz9" protect="rw">
        <comment>Host Channel 9 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma9" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab9" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar10" protect="rw">
        <comment>Host Channel 10 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt10" protect="rw">
        <comment>Host Channel 10 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint10" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk10" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz10" protect="rw">
        <comment>Host Channel 10 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma10" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab10" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar11" protect="rw">
        <comment>Host Channel 11 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt11" protect="rw">
        <comment>Host Channel 11 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint11" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk11" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz11" protect="rw">
        <comment>Host Channel 11 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma11" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab11" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar12" protect="rw">
        <comment>Host Channel 12 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt12" protect="rw">
        <comment>Host Channel 12 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint12" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk12" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz12" protect="rw">
        <comment>Host Channel 12 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma12" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab12" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar13" protect="rw">
        <comment>Host Channel 13 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt13" protect="rw">
        <comment>Host Channel 13 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint13" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk13" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz13" protect="rw">
        <comment>Host Channel 13 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma13" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab13" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar14" protect="rw">
        <comment>Host Channel 14 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt14" protect="rw">
        <comment>Host Channel 14 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint14" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk14" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz14" protect="rw">
        <comment>Host Channel 14 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma14" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab14" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcchar15" protect="rw">
        <comment>Host Channel 15 Characteristics Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Indicates the maximum packet size of the associated endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
          <comment>
            <br>Endpoint Number (EPNum)</br>
            <br/>
            <br>Indicates the endpoint number on the device serving as the data source or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
          <comment>
            <br>Endpoint Direction (EPDir)</br>
            <br/>
            <br>Indicates whether the transaction is IN or OUT.</br>
            <br> - 1'b0: OUT</br>
            <br> - 1'b1: IN</br>
          </comment>
        </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
          <comment>
            <br>Low-Speed Device (LSpdDev)</br>
            <br/>
            <br>This field is Set by the application to indicate that this channel is communicating to a low-speed device.</br>
            <br/>
            <br>The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.</br>
            <br/>
            <br>Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Indicates the transfer type selected.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
          <comment>
            <br>Multi Count (MC) / Error Count (EC)</br>
            <br/>
            <br>When the Split Enable bit of the Host Channel-n Split Control</br>
            <br>register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to</br>
            <br>the host the number of transactions that must be executed per</br>
            <br>microframe for this periodic endpoint. For non periodic transfers,</br>
            <br>this field is used only in DMA mode, and specifies the number</br>
            <br>packets to be fetched for this channel before the internal DMA</br>
            <br>engine changes arbitration.</br>
            <br> - 2'b00: Reserved This field yields undefined results.</br>
            <br> - 2'b01: 1 transaction</br>
            <br> - 2'b10: 2 transactions to be issued for this endpoint per microframe</br>
            <br> - 2'b11: 3 transactions to be issued for this endpoint per microframe</br>
            <br>When HCSPLTn.SpltEna is Set (1'b1), this field indicates the</br>
            <br>number of immediate retries to be performed for a periodic split</br>
            <br>transactions on transaction errors. This field must be Set to at</br>
            <br>least 2'b01.</br>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>This field selects the specific device serving as the data source</br>
            <br>or sink.</br>
          </comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
          <comment>
            <br>Odd Frame (OddFrm)</br>
            <br/>
            <br>This field is set (reset) by the application to indicate that the OTG host must perform </br>
            <br>a transfer in an odd (micro)Frame. This field is applicable for only periodic </br>
            <br>(isochronous and interrupt) transactions.</br>
            <br> - 1'b0: Even (micro)Frame</br>
            <br> - 1'b1: Odd (micro)Frame</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>
            <br>Channel Disable (ChDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data</br>
            <br>on a channel, even before the transfer for that channel is</br>
            <br>complete. The application must wait for the Channel Disabled</br>
            <br>interrupt before treating the channel as disabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>
            <br>Channel Enable (ChEna)</br>
            <br/>
            <br>When Scatter/Gather mode is enabled </br>
            <br> - 1'b0: Indicates that the descriptor structure is not yet ready. </br>
            <br> - 1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with data is setup and this channel can access the descriptor. </br>
            <br>When Scatter/Gather mode is disabled </br>
            <br/>
            <br> This field is set by the application and cleared by the OTG host.  </br>
            <br> - 1'b0: Channel disabled  </br>
            <br> - 1'b1: Channel enabled</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcsplt15" protect="rw">
        <comment>Host Channel 15 Split Control Register</comment>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
          <comment>
            <br>Port Address (PrtAddr)</br>
            <br/>
            <br>This field is the port number of the recipient transaction translator.</br>
          </comment>
        </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
          <comment>
            <br>Hub Address (HubAddr)</br>
            <br/>
            <br>This field holds the device address of the transaction translator's hub.</br>
          </comment>
        </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
          <comment>
            <br>Transaction Position (XactPos)</br>
            <br/>
            <br>This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.</br>
            <br> - 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).</br>
            <br> - 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).</br>
            <br> - 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).</br>
          </comment>
        </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
          <comment>
            <br>Do Complete Split (CompSplt)</br>
            <br/>
            <br>The application sets this field to request the OTG host to perform a complete split transaction.</br>
          </comment>
        </bits>
        <bits access="rw" name="spltena" pos="31" rst="0">
          <comment>
            <br>Split Enable (SpltEna)</br>
            <br/>
            <br>The application sets this field to indicate that this channel is enabled to perform split transactions.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcint15" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Register&quot;
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed (XferCompl)</br>
            <br/>
            <br>Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.</br>
            <br> - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.</br>
            <br> - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="chhltd" pos="1" rst="0">
          <comment>
            <br>Channel Halted (ChHltd)</br>
            <br/>
            <br>In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.</br>
            <br/>
            <br>In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following</br>
            <br> - EOL being set in descriptor</br>
            <br> - AHB error</br>
            <br> - Excessive transaction errors</br>
            <br> - Babble</br>
            <br> - Stall</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="3" rst="0">
          <comment>
            <br>STALL Response Received Interrupt (STALL)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nak" pos="4" rst="0">
          <comment>
            <br>NAK Response Received Interrupt (NAK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="ack" pos="5" rst="0">
          <comment>
            <br>ACK Response Received/Transmitted Interrupt (ACK)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyet" pos="6" rst="0">
          <comment>
            <br>NYET Response Received Interrupt (NYET)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="xacterr" pos="7" rst="0">
          <comment>
            <br>Transaction Error (XactErr)</br>
            <br/>
            <br>Indicates one of the following errors occurred on the USB.</br>
            <br> - CRC check failure</br>
            <br> - Timeout</br>
            <br> - Bit stuff error</br>
            <br> - False EOP</br>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="bblerr" pos="8" rst="0">
          <comment>
            <br>Babble Error (BblErr)</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.</br>
          </comment>
        </bits>
        <bits access="rw" name="frmovrun" pos="9" rst="0">
          <comment>
            <br>Frame Overrun (FrmOvrun).</br>
            <br/>
            <br>In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core. This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.</br>
          </comment>
        </bits>
        <bits access="rw" name="datatglerr" pos="10" rst="0">
          <comment>
            <br/>
            <br>Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear</br>
            <br>it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked </br>
            <br>in the core.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="11" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. </br>
            <br>The core generates this interrupt when the descriptor accessed </br>
            <br>is not ready for the Core to process. BNA will not be generated </br>
            <br>for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcs_xact_err" pos="12" rst="0">
          <comment>
            <br>Excessive Transaction Error (XCS_XACT_ERR)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will </br>
            <br>not be generated for Isochronous channels.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>
            <br>Descriptor rollover interrupt (DESC_LST_ROLLIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit </br>
            <br>when the corresponding channel's descriptor list rolls over.</br>
            <br>For non Scatter/Gather DMA mode, this bit is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcintmsk15" protect="rw">
        <comment>&quot;Host Channel $i Interrupt Mask Register&quot;
This register reflects the mask for each channel status described in the previous section.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br/>
            <br>Transfer Completed Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
          <comment>
            <br/>
            <br>Channel Halted Mask (ChHltdMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br/>
            <br>AHB Error Mask (AHBErrMsk)</br>
            <br>In  scatter/gather  DMA  mode  for  host, </br>
            <br>interrupts will not be generated due to the corresponding bits set in </br>
            <br>HCINTn.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
          <comment>
            <br/>
            <br>BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) </br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
          <comment>
            <br/>
            <br>Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)</br>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hctsiz15" protect="rw">
        <comment>Host Channel 15 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>For an OUT, this field is the number of data bytes the host sends during the transfer.</br>
            <br/>
            <br>For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).</br>
            <br/>
            <br>The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).</br>
            <br/>
            <br>The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.</br>
            <br/>
            <br>The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).</br>
          </comment>
        </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
          <comment>
            <br>PID (Pid)</br>
            <br/>
            <br>The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA (non-control)/SETUP (control)</br>
          </comment>
        </bits>
        <bits access="rw" name="dopng" pos="31" rst="0">
          <comment>
            <br>Do Ping (DoPng)</br>
            <br/>
            <br>This bit is used only for OUT transfers.</br>
            <br>Setting this field to 1 directs the host to do PING protocol.</br>
            <br/>
            <br>Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.</br>
          </comment>
        </bits>
      </reg>
      <reg name="hcdma15" protect="rw">
        <comment>&quot;Host Channel $i DMA Address Register&quot;
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>In Buffer DMA Mode:</br>
            <br/>
            <br>[31:0]: DMA Address (DMAAddr)</br>
            <br/>
            <br>This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.</br>
            <br/>
            <br>Reset: X if not programmed as the register is in SPRAM.</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:</br>
            <br/>
            <br>[31:9]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. </br>
            <br/>
            <br>[8:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>This value is in terms of number of descriptors. The values can be from 0 to 63. </br>
            <br> - 0 -  1 descriptor. </br>
            <br> - 63 - 64 descriptors. </br>
            <br>This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.</br>
            <br/>
            <br>Reset: 6'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
            <br/>
            <br>In Scatter-Gather DMA (DescDMA) Mode for Isochronous:</br>
            <br/>
            <br>[31:N]: DMA Address (DMAAddr)</br>
            <br/>
            <br>The start address must be 512-bytes aligned.</br>
            <br/>
            <br>This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:</br>
            <br> - [31:N]: Base Address</br>
            <br> - [N-1:3]: Offset</br>
            <br> - [2:0]: 000</br>
            <br>For HS ISOC, if nTD is,</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br> - 127, N=10</br>
            <br> - 255, N=11</br>
            <br>For FS ISOC, if nTD is, </br>
            <br> - 1, N=4</br>
            <br> - 3, N=5</br>
            <br> - 7, N=6</br>
            <br> - 15, N=7</br>
            <br> - 31, N=8</br>
            <br> - 63, N=9</br>
            <br>[N-1:3]: Current Transfer Desc(CTD)</br>
            <br/>
            <br>CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.</br>
            <br/>
            <br>Reset: (N+1:3)'h0</br>
            <br/>
            <br>[2:0]: Reserved</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab15" protect="r">
        <comment>&quot;Host Channel $i DMA Buffer Address Register&quot;
This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.</comment>
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.</br>
            <br>This register is updated as and when the data transfer for the corresponding end point </br>
            <br>is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this </br>
            <br>field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <hole size="2048"/>
      <reg name="dcfg" protect="rw">
        <comment>Device Configuration Register
This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.</comment>
        <bits access="rw" name="devspd" pos="1:0" rst="0">
          <comment>
            <br>Device Speed (DevSpd)</br>
            <br/>
            <br>Indicates the speed at which the application requires the core to</br>
            <br>enumerate, or the maximum speed the application can support.</br>
            <br>However, the actual bus speed is determined only after the connect</br>
            <br>sequence is completed, and is based on the speed of the USB</br>
            <br>host to which the core is connected.</br>
          </comment>
        </bits>
        <bits access="rw" name="nzstsouthshk" pos="2" rst="0">
          <comment>
            <br>Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)</br>
            <br/>
            <br>The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer's Status stage.</br>
            <br> - 1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application.</br>
            <br> - 1'b0: Send the received OUT packet to the application (zerolength or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register.</br>
          </comment>
        </bits>
        <bits access="rw" name="ena32khzsusp" pos="3" rst="0">
          <comment>
            <br>Enable 32 KHz Suspend mode (Ena32KHzSusp) </br>
            <br/>
            <br>This bit can be set only if FS PHY interface is selected. Otherwise, this bit needs to be set to zero. If FS PHY interface is chosen and this bit is set, the PHY clock during Suspend must be switched from 48 MHz to 32 KHz. </br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="devaddr" pos="10:4" rst="0">
          <comment>
            <br>Device Address (DevAddr)</br>
            <br/>
            <br>The application must program this field after every SetAddress control command.</br>
          </comment>
        </bits>
        <bits access="rw" name="perfrint" pos="12:11" rst="0">
          <comment>
            <br>Periodic Frame Interval (PerFrInt)</br>
            <br/>
            <br>Indicates the time within a (micro)Frame at which the application</br>
            <br>must be notified using the End Of Periodic Frame Interrupt. This</br>
            <br>can be used to determine If all the isochronous traffic for that</br>
            <br>(micro)Frame is complete.</br>
            <br> - 2'b00: 80% of the (micro)Frame interval</br>
            <br> - 2'b01: 85% of the (micro)Frame interval</br>
            <br> - 2'b10: 90% of the (micro)Frame interval</br>
            <br> - 2'b11: 95% of the (micro)Frame interval</br>
          </comment>
        </bits>
        <bits access="rw" name="endevoutnak" pos="13" rst="0">
          <comment>
            <br>Enable Device OUT NAK (EnDevOutNak)</br>
            <br/>
            <br>This bit enables setting NAK for Bulk OUT endpoints after the transfer is completed for Device mode Descriptor DMA </br>
            <br> - 1'b0 : The core does not set NAK after Bulk OUT transfer complete</br>
            <br> - 1'b1  :  The core sets NAK after Bulk OUT transfer complete</br>
            <br>It bit is one time programmable after reset like any other DCFG register bits.</br>
          </comment>
        </bits>
        <bits access="rw" name="xcvrdly" pos="14" rst="0">
          <comment>
            <br>XCVRDLY</br>
            <br/>
            <br> Enables or disables delay between xcvr_sel and txvalid during device chirp </br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="erraticintmsk" pos="15" rst="0">
          <comment>
            <br>Erratic Error Interrupt Mask</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="descdma" pos="23" rst="0">
          <comment>
            <br>Enable Scatter/gather DMA in device mode (DescDMA).</br>
            <br/>
            <br>When the Scatter/Gather DMA option selected during configuration of the RTL, the application can Set this bit during initialization to enable the Scatter/Gather DMA operation.</br>
            <br/>
            <br>Note: This bit must be modified only once after a reset. The following combinations are available for programming:</br>
            <br> - GAHBCFG.DMAEn=0,DCFG.DescDMA=0 =&gt; Slave mode</br>
            <br> - GAHBCFG.DMAEn=0,DCFG.DescDMA=1 =&gt; Invalid</br>
            <br> - GAHBCFG.DMAEn=1,DCFG.DescDMA=0 =&gt; Buffered DMA mode</br>
            <br> - GAHBCFG.DMAEn=1,DCFG.DescDMA=1 =&gt; Scatter/Gather DMA mode</br>
          </comment>
        </bits>
        <bits access="rw" name="perschintvl" pos="25:24" rst="0">
          <comment>
            <br>Periodic Scheduling Interval (PerSchIntvl)</br>
            <br/>
            <br>PerSchIntvl must be programmed for Scatter/Gather DMA mode.</br>
            <br/>
            <br>This field specifies the amount of time the Internal</br>
            <br>DMA engine must allocate for fetching periodic IN endpoint data.</br>
            <br>Based on the number of periodic endpoints, this value must be</br>
            <br>specified as 25,50 or 75% of (micro)Frame.</br>
            <br> - When any periodic endpoints are active, the internal DMA engine allocates the specified amount of time in fetching periodic IN endpoint data .</br>
            <br> - When no periodic endpoints are active, Then the internal DMA engine services non-periodic endpoints, ignoring this field.</br>
            <br> - After the specified time within a (micro)Frame, the DMA switches to fetching for non-periodic endpoints.</br>
            <br> -- 2'b00: 25% of (micro)Frame.</br>
            <br> -- 2'b01: 50% of (micro)Frame.</br>
            <br> -- 2'b10: 75% of (micro)Frame.</br>
            <br> -- 2'b11: Reserved.</br>
            <br>Reset: 2'b00</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="resvalid" pos="31:26" rst="2">
          <comment>
            <br>Resume Validation Period (ResValid)</br>
            <br/>
            <br>This field is effective only when DCFG.Ena32KHzSusp is set.</br>
            <br>It controls the resume period when the core resumes from</br>
            <br>suspend. The core counts for ResValid number of clock cycles </br>
            <br>to detect a valid resume when this bit is set</br>
          </comment>
        </bits>
      </reg>
      <reg name="dctl" protect="rw">
        <comment>Device Control Register</comment>
        <bits access="rw" name="rmtwkupsig" pos="0" rst="0">
          <comment>
            <br>Remote Wakeup Signaling (RmtWkUpSig)</br>
            <br/>
            <br>When the application sets this bit, the core initiates remote</br>
            <br>signaling to wake up the USB host. The application must Set this</br>
            <br>bit to instruct the core to exit the Suspend state. As specified in</br>
            <br>the USB 2.0 specification, the application must clear this bit </br>
            <br>1-15 ms after setting it.</br>
            <br/>
            <br/>
            <br>If LPM is enabled and the core is in the L1 (Sleep) state, when the application sets this bit, the core initiates L1 remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Sleep state. As specified in the LPM specification, the hardware automatically clears this bit 50 microseconds (TL1DevDrvResume) after being set by the application. The application must not set this bit when GLPMCFG bRemoteWake from the previous LPM transaction is zero.</br>
          </comment>
        </bits>
        <bits access="rw" name="sftdiscon" pos="1" rst="1">
          <comment>
            <br>Soft Disconnect (SftDiscon)</br>
            <br/>
            <br>The application uses this bit to signal the controller to do a soft disconnect. As long as this bit is Set, the host does not see that the device is connected, and the device does not receive</br>
            <br>signals on the USB. The core stays in the disconnected state until the application clears this bit.</br>
            <br> - 1'b0: Normal operation. When this bit is cleared after a soft disconnect, the core drives the phy_opmode_o signal on the</br>
            <br>   UTMI+ to 2'b00, which generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration.</br>
            <br> - 1'b1: The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a device disconnect event to the USB host.</br>
            <br>The following is the minimum duration under various conditions for which this bit must be set for the USB host to detect a device disconnect. To accommodate clock jitter, it is</br>
            <br>recommended that the application adds some extra delay to the specified minimum duration.</br>
            <br/>
            <br>For high speed, if the device state is, </br>
            <br> - Suspended, the minimum duration is 1ms + 2.5us</br>
            <br> - Idle, the minimum duration is 3ms + 2.5us</br>
            <br> - Not Idle or Suspended (performing transactions), the minimum duration 125 us</br>
            <br>For full speed/low speed, if the device state is, </br>
            <br> - Suspended, the minimum duration is 1ms + 2.5us</br>
            <br> - Idle, the minimum duration is 2.5us</br>
            <br> - Not Idle or Suspended (performing transactions), the minimum duration 125 us</br>
            <br>Note: </br>
            <br> - This bit can be also used for ULPI/FS Serial interfaces.</br>
            <br> - This bit is not impacted by a soft reset.</br>
          </comment>
        </bits>
        <bits access="r" name="gnpinnaksts" pos="2" rst="0">
          <comment>
            <br>Global Non-periodic IN NAK Status (GNPINNakSts)</br>
            <br> - 1'b0: A handshake is sent out based on the data availability in the transmit FIFO.</br>
            <br> - 1'b1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="goutnaksts" pos="3" rst="0">
          <comment>
            <br>Global OUT NAK Status (GOUTNakSts)</br>
            <br> - 1'b0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.</br>
            <br> - 1'b1: No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped.</br>
          </comment>
        </bits>
        <bits access="rw" name="tstctl" pos="6:4" rst="0">
          <comment>
            <br>Test Control (TstCtl)</br>
            <br> - 3'b000: Test mode disabled</br>
            <br> - 3'b001: Test_J mode</br>
            <br> - 3'b010: Test_K mode</br>
            <br> - 3'b011: Test_SE0_NAK mode</br>
            <br> - 3'b100: Test_Packet mode</br>
            <br> - 3'b101: Test_Force_Enable</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
        <bits access="w" name="sgnpinnak" pos="7" rst="0">
          <comment>
            <br>Set Global Non-periodic IN NAK (SGNPInNak)</br>
            <br/>
            <br>A write to this field sets the Global Non-periodic IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN endpoints.</br>
            <br>The core can also Set this bit when a timeout condition is detected on a non-periodic endpoint in shared FIFO operation.</br>
            <br>The application must Set this bit only after making sure that the Global IN NAK Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared</br>
          </comment>
        </bits>
        <bits access="w" name="cgnpinnak" pos="8" rst="0">
          <comment>
            <br>Clear Global Non-periodic IN NAK (CGNPInNak)</br>
            <br/>
            <br>A write to this field clears the Global Non-periodic IN NAK.</br>
          </comment>
        </bits>
        <bits access="w" name="sgoutnak" pos="9" rst="0">
          <comment>
            <br>Set Global OUT NAK (SGOUTNak)</br>
            <br/>
            <br>A write to this field sets the Global OUT NAK. The application uses this bit to send a NAK handshake on all OUT endpoints.</br>
            <br>The application must set the this bit only after making sure that the Global OUT NAK Effective bit in the Core Interrupt Register (GINTSTS.GOUTNakEff) is cleared.</br>
          </comment>
        </bits>
        <bits access="w" name="cgoutnak" pos="10" rst="0">
          <comment>
            <br>Clear Global OUT NAK (CGOUTNak)</br>
            <br/>
            <br>A write to this field clears the Global OUT NAK.</br>
          </comment>
        </bits>
        <bits access="rw" name="pwronprgdone" pos="11" rst="0">
          <comment>
            <br>Power-On Programming Done (PWROnPrgDone)</br>
            <br/>
            <br>The application uses this bit to indicate that register programming is completed after a wake-up from Power Down mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="gmc" pos="14:13" rst="0">
          <comment>
            <br>Global Multi Count (GMC)</br>
            <br/>
            <br>GMC must be programmed only once after initialization.</br>
            <br>Applicable only for Scatter/Gather DMA mode. This indicates the number of packets to be serviced for that end point before moving to the next end point. It is only for non-periodic endpoints. </br>
            <br> - 2'b00: Invalid.</br>
            <br> - 2'b01: 1 packet.</br>
            <br> - 2'b10: 2 packets.</br>
            <br> - 2'b11: 3 packets.</br>
            <br>The value of this field automatically changes to 2'h1 when DCFG.DescDMA is set to 1. When Scatter/Gather DMA mode is disabled, this field is reserved. and reads 2'b00.</br>
          </comment>
        </bits>
        <bits access="rw" name="ignrfrmnum" pos="15" rst="0">
          <comment>
            <br>Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum)</br>
            <br/>
            <br>This field is also used to control the Periodic Transfer Interrupt (PTI) feature.</br>
            <br/>
            <br>Note: Do not program IgnrFrmNum bit to 1'b1 when the core is operating in threshold mode.</br>
            <br/>
            <br>Slave Mode (GAHBCFG.DMAEn=0): </br>
            <br/>
            <br>This bit is not valid in Slave mode and should not be programmed to 1.</br>
            <br/>
            <br>Scatter/Gather DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=1): </br>
            <br/>
            <br>Note: When Scatter/Gather DMA mode is enabled this feature is not applicable to High Speed, High bandwidth transfers.</br>
            <br/>
            <br>When this bit is enabled, there must be only one packet per descriptor. </br>
            <br> - 0: The core transmits the packets only in the frame number in which they are intended to be transmitted. </br>
            <br> - 1: The core ignores the frame number, sending packets immediately as the packets are ready.</br>
            <br>In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed when a ISOC IN token is received for an elapsed frame.</br>
            <br/>
            <br>Non-Scatter/Gather DMA Mode, that is, Buffer DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=0): </br>
            <br/>
            <br>When Scatter/Gather DMA mode is disabled, this field is used by the application to enable Periodic Transfer Interrupt (PTI) Mode.</br>
            <br/>
            <br>The application can program Periodic Endpoint transfers for multiple (micro)Frames.</br>
            <br> - 0: Periodic Transfer Interrupt feature is disabled, application needs to program transfers for periodic endpoints every (micro)Frame</br>
            <br> - 1: Periodic Transfer Interrupt feature is enabled, application can program transfers for multiple (micro)Frames for periodic endpoints.</br>
            <br>In the PTI mode, the application will receive Transfer Complete Interrupt after transfers for multiple (micro)Frames are completed.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakonbble" pos="16" rst="0">
          <comment>
            <br>NAK on Babble Error (NakOnBble)</br>
            <br/>
            <br>Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for the endpoint on which babble is received.</br>
          </comment>
        </bits>
        <bits access="rw" name="encontonbna" pos="17" rst="0">
          <comment>
            <br>Enable Continue on BNA (EnContOnBNA)</br>
            <br/>
            <br>This bit enables the core to continue on BNA for Bulk OUT endpoints. </br>
            <br>With this feature enabled, when a Bulk OUT or INTR OUT endpoint receives a BNA interrupt</br>
            <br>the core starts processing the descriptor that caused the BNA interrupt after </br>
            <br>the endpoint re-enables the endpoint. </br>
            <br> - 1'b0: After receiving BNA interrupt,the core disables the endpoint. When the endpoint is re-enabled by the application,the core starts processing from the DOEPDMA descriptor.</br>
            <br> - 1'b1: After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the descriptor that received the BNA interrupt.</br>
            <br/>
            <br> This bit is valid only when OTG_EN_DESC_DMA == 1'b1. It is a one-time programmable after reset bit like any other DCTL register bits.</br>
          </comment>
        </bits>
      </reg>
      <reg name="dsts" protect="r">
        <comment>Device Status Register
This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device All Interrupts (DAINT) register.</comment>
        <bits access="r" name="suspsts" pos="0" rst="0">
          <comment>
            <br>Suspend Status (SuspSts)</br>
            <br/>
            <br>In Device mode, this bit is set as long as a Suspend condition is</br>
            <br>detected on the USB. The core enters the Suspend state</br>
            <br>when there is no activity on the phy_line_state_i signal for an</br>
            <br>extended period of time. The core comes out of the suspend under the following conditions :</br>
            <br> - If there is any activity on the phy_line_state_i signal, or</br>
            <br> - If the application writes to the Remote Wakeup Signaling bit in the Device Control register (DCTL.RmtWkUpSig).</br>
            <br>When the core comes out of the suspend, this bit is set to 1'b0.</br>
          </comment>
        </bits>
        <bits access="r" name="enumspd" pos="2:1" rst="1">
          <comment>
            <br>Enumerated Speed (EnumSpd)</br>
            <br/>
            <br>Indicates the speed at which the controller has come up</br>
            <br>after speed detection through a connect or reset sequence.</br>
            <br> - 2'b00: High speed (PHY clock is running at 30 or 60 MHz)</br>
            <br> - 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)</br>
            <br> - 2'b10: Low speed (PHY clock is running at 6 MHz)</br>
            <br> - 2'b11: Full speed (PHY clock is running at 48 MHz)</br>
            <br>Low speed is not supported for devices using a UTMI+ PHY.</br>
          </comment>
        </bits>
        <bits access="r" name="errticerr" pos="3" rst="0">
          <comment>
            <br>Erratic Error (ErrticErr)</br>
            <br/>
            <br>The core sets this bit to report any erratic errors</br>
            <br>(phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at</br>
            <br>least 2 ms, due to PHY error) seen on the UTMI+.</br>
            <br>Due to erratic errors, the DWC_otg core goes into Suspended</br>
            <br>state and an interrupt is generated to the application with Early</br>
            <br>Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).</br>
            <br>If the early suspend is asserted due to an erratic error, the</br>
            <br>application can only perform a soft disconnect recover.</br>
          </comment>
        </bits>
        <bits access="r" name="soffn" pos="21:8" rst="0">
          <comment>
            <br>Frame or Microframe Number of the Received SOF  (SOFFN)</br>
            <br/>
            <br>When the core is operating at high speed, this field contains a microframe number. When the core is operating at full or low speed, this field contains a Frame number.</br>
            <br/>
            <br>Note: This register may return a non-zero value if read immediately after power-on reset.</br>
            <br>In case the register bit reads non-zero immediately after power-on reset, it does not</br>
            <br>indicate that SOF has been received from the host. The read value of this interrupt is</br>
            <br>valid only after a valid connection between host and device is established.</br>
          </comment>
        </bits>
        <bits access="r" name="devlnsts" pos="23:22" rst="0">
          <comment>
            <br>Device Line Status (DevLnSts) </br>
            <br/>
            <br>Indicates the current logic level USB data lines </br>
            <br> - DevLnSts[1]: Logic level of D+ </br>
            <br> - DevLnSts[0]: Logic level of D-</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepmsk" protect="rw">
        <comment>Device IN Endpoint Common Interrupt Mask Register
This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbldmsk" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt Mask (EPDisbldMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br>AHB Error Mask (AHBErrMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="timeoutmsk" pos="3" rst="0">
          <comment>
            <br>Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints)</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfempmsk" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmismsk" pos="5" rst="0">
          <comment>
            <br>IN Token received with EP Mismatch Mask (INTknEPMisMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeffmsk" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective Mask (INEPNakEffMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrnmsk" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun Mask (TxfifoUndrnMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="bnainintrmsk" pos="9" rst="0">
          <comment>
            <br>BNA interrupt Mask (BNAInIntrMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="nakmsk" pos="13" rst="0">
          <comment>
            <br>NAK interrupt Mask (NAKMsk)</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepmsk" protect="rw">
        <comment>Device OUT Endpoint Common Interrupt Mask Register
This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTn register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.</comment>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt Mask (XferComplMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbldmsk" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt Mask (EPDisbldMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErrMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="setupmsk" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done Mask (SetUPMsk)</br>
            <br/>
            <br>Applies to control endpoints only.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdismsk" pos="4" rst="0">
          <comment>
            <br>OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvdmsk" pos="5" rst="0">
          <comment>
            <br>Status Phase Received Mask (StsPhseRcvdMsk)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received Mask (Back2BackSETup)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterrmsk" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error Mask (OutPktErrMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaoutintrmsk" pos="9" rst="0">
          <comment>
            <br>BNA interrupt Mask (BnaOutIntrMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerrmsk" pos="12" rst="0">
          <comment>
            <br>Babble Error interrupt Mask (BbleErrMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="nakmsk" pos="13" rst="0">
          <comment>
            <br>NAK interrupt Mask (NAKMsk)</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetmsk" pos="14" rst="0">
          <comment>
            <br>NYET interrupt Mask (NYETMsk)</br>
          </comment>
        </bits>
      </reg>
      <reg name="daint" protect="r">
        <comment>Device All Endpoints Interrupt Register
When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the
application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the Core
Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). This is shown in Figure 5-2. There is
one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints.
For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are
set and cleared when the application sets and clears bits in the corresponding Device Endpoint-n Interrupt
register (DIEPINTn/DOEPINTn).</comment>
        <bits access="r" name="inepint0" pos="0" rst="0">
          <comment>
            <br>IN Endpoint 0 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint1" pos="1" rst="0">
          <comment>
            <br>IN Endpoint 1 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint2" pos="2" rst="0">
          <comment>
            <br>IN Endpoint 2 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint3" pos="3" rst="0">
          <comment>
            <br>IN Endpoint 3 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint4" pos="4" rst="0">
          <comment>
            <br>IN Endpoint 4 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint5" pos="5" rst="0">
          <comment>
            <br>IN Endpoint 5 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint6" pos="6" rst="0">
          <comment>
            <br>IN Endpoint 6 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint7" pos="7" rst="0">
          <comment>
            <br>IN Endpoint 7 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint8" pos="8" rst="0">
          <comment>
            <br>IN Endpoint 8 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint9" pos="9" rst="0">
          <comment>
            <br>IN Endpoint 9 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint10" pos="10" rst="0">
          <comment>
            <br>IN Endpoint 10 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint11" pos="11" rst="0">
          <comment>
            <br>IN Endpoint 11 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="inepint12" pos="12" rst="0">
          <comment>
            <br>IN Endpoint 12 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint0" pos="16" rst="0">
          <comment>
            <br>OUT Endpoint 0 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint1" pos="17" rst="0">
          <comment>
            <br>OUT Endpoint 1 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint2" pos="18" rst="0">
          <comment>
            <br>OUT Endpoint 2 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint3" pos="19" rst="0">
          <comment>
            <br>OUT Endpoint 3 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint4" pos="20" rst="0">
          <comment>
            <br>OUT Endpoint 4 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint5" pos="21" rst="0">
          <comment>
            <br>OUT Endpoint 5 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint6" pos="22" rst="0">
          <comment>
            <br>OUT Endpoint 6 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint7" pos="23" rst="0">
          <comment>
            <br>OUT Endpoint 7 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint8" pos="24" rst="0">
          <comment>
            <br>OUT Endpoint 8 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint9" pos="25" rst="0">
          <comment>
            <br>OUT Endpoint 9 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint10" pos="26" rst="0">
          <comment>
            <br>OUT Endpoint 10 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint11" pos="27" rst="0">
          <comment>
            <br>OUT Endpoint 11 Interrupt Bit</br>
          </comment>
        </bits>
        <bits access="r" name="outepint12" pos="28" rst="0">
          <comment>
            <br>OUT Endpoint 12 Interrupt Bit</br>
          </comment>
        </bits>
      </reg>
      <reg name="daintmsk" protect="rw">
        <comment>Device All Endpoints Interrupt Mask Register
 The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the application when an event occurs on a device endpoint. However, the Device All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt is still set.</comment>
        <bits access="rw" name="inepmsk0" pos="0" rst="0">
          <comment>
            <br>IN Endpoint 0 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk1" pos="1" rst="0">
          <comment>
            <br>IN Endpoint 1 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk2" pos="2" rst="0">
          <comment>
            <br>IN Endpoint 2 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk3" pos="3" rst="0">
          <comment>
            <br>IN Endpoint 3 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk4" pos="4" rst="0">
          <comment>
            <br>IN Endpoint 4 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk5" pos="5" rst="0">
          <comment>
            <br>IN Endpoint 5 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk6" pos="6" rst="0">
          <comment>
            <br>IN Endpoint 6 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk7" pos="7" rst="0">
          <comment>
            <br>IN Endpoint 7 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk8" pos="8" rst="0">
          <comment>
            <br>IN Endpoint 8 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk9" pos="9" rst="0">
          <comment>
            <br>IN Endpoint 9 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk10" pos="10" rst="0">
          <comment>
            <br>IN Endpoint 10 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk11" pos="11" rst="0">
          <comment>
            <br>IN Endpoint 11 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="inepmsk12" pos="12" rst="0">
          <comment>
            <br>IN Endpoint 12 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk0" pos="16" rst="0">
          <comment>
            <br>OUT Endpoint 0 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk1" pos="17" rst="0">
          <comment>
            <br>OUT Endpoint 1 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk2" pos="18" rst="0">
          <comment>
            <br>OUT Endpoint 2 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk3" pos="19" rst="0">
          <comment>
            <br>OUT Endpoint 3 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk4" pos="20" rst="0">
          <comment>
            <br>OUT Endpoint 4 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk5" pos="21" rst="0">
          <comment>
            <br>OUT Endpoint 5 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk6" pos="22" rst="0">
          <comment>
            <br>OUT Endpoint 6 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk7" pos="23" rst="0">
          <comment>
            <br>OUT Endpoint 7 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk8" pos="24" rst="0">
          <comment>
            <br>OUT Endpoint 8 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk9" pos="25" rst="0">
          <comment>
            <br>OUT Endpoint 9 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk10" pos="26" rst="0">
          <comment>
            <br>OUT Endpoint 10 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk11" pos="27" rst="0">
          <comment>
            <br>OUT Endpoint 11 Interrupt mask Bit</br>
          </comment>
        </bits>
        <bits access="rw" name="outepmsk12" pos="28" rst="0">
          <comment>
            <br>OUT Endpoint 12 Interrupt mask Bit</br>
          </comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="dvbusdis" protect="rw">
        <comment>Device VBUS Discharge Time Register
 This register specifies the VBUS discharge time after VBUS pulsing during SRP.</comment>
        <bits access="rw" name="dvbusdis" pos="15:0" rst="6103">
          <comment>
            <br>Device VBUS Discharge Time (DVBUSDis)</br>
            <br/>
            <br>Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals (VBUS discharge time in PHY clocks) / 1, 024.</br>
            <br/>
            <br>The value you use depends whether the PHY is operating at 30MHz (16-bit data width) or 60 MHz (8-bit data width).</br>
            <br/>
            <br>Depending on your VBUS load, this value can need adjustment.</br>
          </comment>
        </bits>
      </reg>
      <reg name="dvbuspulse" protect="rw">
        <comment>Device VBUS Pulsing Time Register</comment>
        <bits access="rw" name="dvbuspulse" pos="11:0" rst="1464">
          <comment>
            <br>Device VBUS Pulsing Time (DVBUSPulse)</br>
            <br/>
            <br>Specifies the VBUS pulsing time during SRP. This value equals (VBUS pulsing time in PHY clocks) / 1, 024</br>
            <br/>
            <br>The value you use depends whether the PHY is operating at 30MHz (16-bit data width) or 60 MHz (8-bit data width).</br>
          </comment>
        </bits>
      </reg>
      <reg name="dthrctl" protect="rw">
        <comment>Device Threshold Control Register</comment>
        <bits access="rw" name="nonisothren" pos="0" rst="0">
          <comment>
            <br>Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)</br>
            <br/>
            <br>When this bit is Set, the core enables thresholding for Non Isochronous IN endpoints.</br>
          </comment>
        </bits>
        <bits access="rw" name="isothren" pos="1" rst="0">
          <comment>
            <br/>
            <br>ISO IN Endpoints Threshold Enable. (ISOThrEn)</br>
            <br> </br>
            <br> When this bit is Set, the core enables thresholding for isochronous IN</br>
            <br>endpoints.</br>
          </comment>
        </bits>
        <bits access="rw" name="txthrlen" pos="10:2" rst="8">
          <comment>
            <br>Transmit Threshold Length (TxThrLen)</br>
            <br/>
            <br>This field specifies Transmit thresholding size in DWORDS. This also forms </br>
            <br>the MAC threshold and specifies the amount of data in bytes to be in the </br>
            <br>corresponding endpoint transmit FIFO, before the core can start transmit </br>
            <br>on the USB. The threshold length has to be at least eight DWORDS when the </br>
            <br>value of AHBThrRatio is 2'h00. In case the AHBThrRatio is non zero the </br>
            <br>application needs to ensure that the AHB Threshold value does not go below </br>
            <br>the recommended eight DWORD.  This field controls both isochronous and </br>
            <br>non-isochronous IN endpoint thresholds. The recommended value for ThrLen </br>
            <br>is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen).</br>
            <br/>
            <br>Note:</br>
            <br> - When OTG_ARCHITECTURE=0, the reset value of this register field is 0.</br>
            <br> - When OTG_ARCHITECTURE=2, the reset value of this register field is 8.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="ahbthrratio" pos="12:11" rst="0">
          <comment>
            <br>AHB Threshold Ratio (AHBThrRatio)</br>
            <br/>
            <br>These bits define the ratio between the AHB threshold and the MAC threshold for the</br>
            <br>transmit path only. The AHB threshold always remains less than or equal to the USB</br>
            <br>threshold, because this does not increase overhead. Both the AHB and the MAC</br>
            <br>threshold must be DWORD-aligned. The application needs to program TxThrLen and the</br>
            <br>AHBThrRatio to make the AHB Threshold value DWORD aligned. If the AHB threshold</br>
            <br>value is not DWORD aligned, the core might not behave correctly. When programming</br>
            <br>the TxThrLen and AHBThrRatio, the application must ensure that the minimum AHB</br>
            <br>threshold value does not go below 8 DWORDS to meet the USB turnaround time</br>
            <br>requirements.</br>
            <br> - 2'b00: AHB threshold = MAC threshold</br>
            <br> - 2'b01: AHB threshold = MAC threshold / 2</br>
            <br> - 2'b10: AHB threshold = MAC threshold / 4</br>
            <br> - 2'b11: AHB threshold = MAC threshold / 8</br>
          </comment>
        </bits>
        <bits access="rw" name="rxthren" pos="16" rst="0">
          <comment>
            <br>Receive Threshold Enable (RxThrEn)</br>
            <br/>
            <br>When this bit is set, the core enables thresholding in the receive direction.</br>
            <br/>
            <br>Note: We recommends that you do not enable RxThrEn, because it may cause issues in the RxFIFO especially during error conditions such as RxError and Babble.</br>
          </comment>
        </bits>
        <bits access="rw" name="rxthrlen" pos="25:17" rst="8">
          <comment>
            <br>Receive Threshold Length (RxThrLen)</br>
            <br/>
            <br>This field specifies Receive thresholding size in DWORDS.</br>
            <br>This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB.</br>
            <br>The threshold length has to be at least eight DWORDS.</br>
            <br>The recommended value for ThrLen is to be the same as the programmed</br>
            <br>AHB Burst Length (GAHBCFG.HBstLen).</br>
          </comment>
        </bits>
        <bits access="rw" name="arbprken" pos="27" rst="1">
          <comment>
            <br>Arbiter Parking Enable (ArbPrkEn)</br>
            <br/>
            <br>This bit controls internal DMA arbiter parking for IN endpoints. If thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default, arbiter parking is enabled.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepempmsk" protect="rw">
        <comment>Device IN Endpoint FIFO Empty Interrupt Mask Register
This register is valid only in Dedicated FIFO operation (OTG_EN_DED_TX_FIFO = 1). This register is used to control the IN endpoint FIFO empty interrupt generation (DIEPINTn.TxfEmp).</comment>
        <bits access="rw" name="ineptxfempmsk" pos="15:0" rst="0">
          <comment>
            <br>IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)</br>
            <br/>
            <br>These bits acts as mask bits for DIEPINTn.TxFEmp interrupt, one bit per IN Endpoint:</br>
            <br/>
            <br>Bit 0 for IN EP 0, bit 15 for IN EP 15</br>
          </comment>
        </bits>
      </reg>
      <hole size="1600"/>
      <reg name="diepctl0" protect="rw">
        <comment>Device Control IN Endpoint 0 Control Register</comment>
        <bits access="rw" name="mps" pos="1:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint.</br>
            <br> - 2'b00: 64 bytes</br>
            <br> - 2'b01: 32 bytes</br>
            <br> - 2'b10: 16 bytes</br>
            <br> - 2'b11: 8 bytes</br>
          </comment>
        </bits>
        <bits access="r" name="usbactep" pos="15" rst="1">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>This bit is always SET to 1, indicating that control endpoint 0 is always active in all configurations and interfaces.</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When this bit is set, either by the application or core, the core stops</br>
            <br>transmitting data, even If there is data available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data</br>
            <br>packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="r" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Hardcoded to 00 for control.</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a</br>
            <br>SETUP token is received for this endpoint. If a NAK bit, Global Nonperiodic</br>
            <br>IN NAK, or Global OUT NAK is set along with this bit, the STALL</br>
            <br>bit takes priority.</br>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br> - For Shared FIFO operation, this value is always set to 0, indicating that control IN endpoint 0 data is always written in the Non-Periodic Transmit FIFO.</br>
            <br> - For Dedicated FIFO operation, this value is set to the FIFO number that is assigned to IN Endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br/>
            <br>Set NAK (SNAK)</br>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>The application sets this bit to stop transmitting data on an endpoint,</br>
            <br>even before the transfer for that endpoint is complete. The application</br>
            <br>must wait for the Endpoint Disabled interrupt before treating the endpoint</br>
            <br>as disabled. The core clears this bit before setting the Endpoint Disabled</br>
            <br>Interrupt. The application must Set this bit only if Endpoint Enable is</br>
            <br>already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled for IN endpoints, this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br/>
            <br> When Scatter/Gather DMA mode is disabled (such as in buffer pointer based DMA mode) this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br>The core clears this bit before setting the following interrupts on this endpoint:</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint0" protect="rw">
        <comment>Device IN Endpoint 0 Interrupt Register
 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in the &quot;Interrupt Hierarchy&quot; figure in the databook. The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core).</br>
            <br/>
            <br>The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN Endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>The core generates this interrupt when it detects a transmit FIFO underrun condition in threshold mode for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>&lt;brIn case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz0" protect="rw">
        <comment>Device IN Endpoint 0 Transfer Size Register
The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 115. When Scatter/Gather DMA mode is enabled, this register must not be programmed by the application. If the application reads this register when Scatter/Gather DMA mode is enabled, the core returns all zeros.</comment>
        <bits access="rw" name="xfersize" pos="6:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>This field contains the transfer size in bytes for the current endpoint. The transfer size (XferSize) = Sum of buffer sizes across all descriptors in the list for the endpoint.</br>
            <br>In Buffer DMA, the core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet.</br>
            <br> - IN Endpoints: The core decrements this field every time a packet from the external memory is written to the TxFIFO.</br>
            <br> - OUT Endpoints: The core decrements this field every time a packet is read from the RxFIFO and written to the external memory.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="20:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the</br>
            <br/>
            <br>Transfer Size amount of data for endpoint 0.</br>
            <br> - IN Endpoints : This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
            <br> - OUT Endpoints: This field is decremented every time a packet (maximum size or short packet) is written to the RxFIFO.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma0" protect="rw">
        <comment>Device IN Endpoint 0 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>DMAAddr</br>
            <br/>
            <br>This field holds the start address of the external memory for storing or fetching endpoint data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts0" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 0</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab0" protect="r">
        <comment>Device IN Endpoint 16 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl1" protect="rw">
        <comment>Device Control IN Endpoint 1 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint1" protect="rw">
        <comment>Device IN Endpoint 1 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz1" protect="rw">
        <comment>Device IN Endpoint 1 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma1" protect="rw">
        <comment>Device IN Endpoint 1 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts1" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 1
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab1" protect="r">
        <comment>Device IN Endpoint 1 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl2" protect="rw">
        <comment>Device Control IN Endpoint 2 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint2" protect="rw">
        <comment>Device IN Endpoint 2 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz2" protect="rw">
        <comment>Device IN Endpoint 2 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma2" protect="rw">
        <comment>Device IN Endpoint 2 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts2" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 2
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab2" protect="r">
        <comment>Device IN Endpoint 2 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl3" protect="rw">
        <comment>Device Control IN Endpoint 3 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint3" protect="rw">
        <comment>Device IN Endpoint 3 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz3" protect="rw">
        <comment>Device IN Endpoint 3 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma3" protect="rw">
        <comment>Device IN Endpoint 3 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts3" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 3
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab3" protect="r">
        <comment>Device IN Endpoint 3 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl4" protect="rw">
        <comment>Device Control IN Endpoint 4 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint4" protect="rw">
        <comment>Device IN Endpoint 4 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz4" protect="rw">
        <comment>Device IN Endpoint 4 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma4" protect="rw">
        <comment>Device IN Endpoint 4 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts4" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 4
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab4" protect="r">
        <comment>Device IN Endpoint 4 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl5" protect="rw">
        <comment>Device Control IN Endpoint 5 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint5" protect="rw">
        <comment>Device IN Endpoint 5 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz5" protect="rw">
        <comment>Device IN Endpoint 5 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma5" protect="rw">
        <comment>Device IN Endpoint 5 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts5" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 5
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab5" protect="r">
        <comment>Device IN Endpoint 5 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl6" protect="rw">
        <comment>Device Control IN Endpoint 6 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint6" protect="rw">
        <comment>Device IN Endpoint 6 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz6" protect="rw">
        <comment>Device IN Endpoint 6 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma6" protect="rw">
        <comment>Device IN Endpoint 6 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts6" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 6
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab6" protect="r">
        <comment>Device IN Endpoint 6 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl7" protect="rw">
        <comment>Device Control IN Endpoint 7 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint7" protect="rw">
        <comment>Device IN Endpoint 7 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz7" protect="rw">
        <comment>Device IN Endpoint 7 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma7" protect="rw">
        <comment>Device IN Endpoint 7 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts7" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 7
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab7" protect="r">
        <comment>Device IN Endpoint 7 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl8" protect="rw">
        <comment>Device Control IN Endpoint 8 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint8" protect="rw">
        <comment>Device IN Endpoint 8 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz8" protect="rw">
        <comment>Device IN Endpoint 8 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma8" protect="rw">
        <comment>Device IN Endpoint 8 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts8" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 8
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab8" protect="r">
        <comment>Device IN Endpoint 8 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl9" protect="rw">
        <comment>Device Control IN Endpoint 9 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint9" protect="rw">
        <comment>Device IN Endpoint 9 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz9" protect="rw">
        <comment>Device IN Endpoint 9 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma9" protect="rw">
        <comment>Device IN Endpoint 9 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts9" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 9
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab9" protect="r">
        <comment>Device IN Endpoint 9 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl10" protect="rw">
        <comment>Device Control IN Endpoint 10 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint10" protect="rw">
        <comment>Device IN Endpoint 10 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz10" protect="rw">
        <comment>Device IN Endpoint 10 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma10" protect="rw">
        <comment>Device IN Endpoint 10 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts10" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 10
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab10" protect="r">
        <comment>Device IN Endpoint 10 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl11" protect="rw">
        <comment>Device Control IN Endpoint 11 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint11" protect="rw">
        <comment>Device IN Endpoint 11 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz11" protect="rw">
        <comment>Device IN Endpoint 11 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma11" protect="rw">
        <comment>Device IN Endpoint 11 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts11" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 11
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab11" protect="r">
        <comment>Device IN Endpoint 11 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepctl12" protect="rw">
        <comment>Device Control IN Endpoint 12 Control Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br/>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather</br>
            <br>DMA mode.</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br/>
            <br>Applies to isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>Indicates the (micro)frame number in which the core transmits/receives isochronous</br>
            <br>data for this endpoint. The application must program the even/odd (micro)frame</br>
            <br>number in which it intends to transmit/receive isochronous data for this endpoint using</br>
            <br>the SetEvnFr and SetOddFr fields in this register.</br>
            <br> - 1'b0: Even (micro)frame</br>
            <br> - 1'b1: Odd (micro)frame</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number</br>
            <br>in which to send data is provided in the transmit descriptor structure. The frame in</br>
            <br>which data is received is updated in receive descriptor structure.	</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
          <comment>
            <br>TxFIFO Number (TxFNum)</br>
            <br/>
            <br>Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic</br>
            <br>endpoints must map this to the corresponding Periodic TxFIFO number.</br>
            <br> - 4'h0: Non-Periodic TxFIFO</br>
            <br> - Others: Specified Periodic TxFIFO.number</br>
            <br>Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for</br>
            <br>applications such as mass storage. The core treats an IN endpoint as a non-periodic</br>
            <br>endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be</br>
            <br>allocated for an interrupt IN endpoint, and the number of this</br>
            <br>FIFO must be programmed into the TxFNum field. Configuring an interrupt IN</br>
            <br>endpoint as a non-periodic endpoint saves the extra periodic FIFO area.</br>
            <br/>
            <br>Dedicated FIFO Operation: These bits specify the FIFO number associated with this</br>
            <br>endpoint. Each active IN endpoint must be programmed to a separate FIFO number.</br>
            <br>This field is valid only for IN endpoints.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>SetD0PID</br>
            <br> - Set DATA0 PID (SetD0PID)</br>
            <br> -- Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> -- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.</br>
            <br>When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to</br>
            <br>receive data is updated in receive descriptor structure.</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>SetD1PID</br>
            <br> - Set DATA1 PID (SetD1PID)</br>
            <br> -- Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> -- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.</br>
            <br> - Set odd (micro)Frame (SetOddFr)</br>
            <br> -- Applies to isochronous IN and OUT endpoints only.</br>
            <br> -- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.</br>
            <br> -- This field is not applicable for Scatter-Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled,</br>
            <br> -- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> -- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> -- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> -- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint12" protect="rw">
        <comment>Device IN Endpoint 12 Interrupt Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="timeout" pos="3" rst="0">
          <comment>
            <br>Timeout Condition (TimeOUT)</br>
            <br> - In shared TX FIFO mode, applies to non-isochronous IN endpoints only.</br>
            <br> - In dedicated FIFO mode, applies only to Control IN endpoints.</br>
            <br> - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.</br>
            <br>Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="intkntxfemp" pos="4" rst="0">
          <comment>
            <br>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="intknepmis" pos="5" rst="0">
          <comment>
            <br>IN Token Received with EP Mismatch (INTknEPMis)</br>
            <br/>
            <br>Applies to non-periodic IN endpoints only.</br>
            <br/>
            <br>Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="inepnakeff" pos="6" rst="0">
          <comment>
            <br>IN Endpoint NAK Effective (INEPNakEff)</br>
            <br/>
            <br>Applies to periodic IN endpoints only.</br>
            <br/>
            <br>This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.</br>
            <br/>
            <br>This interrupt indicates that the core has sampled the NAK bit</br>
            <br/>
            <br>Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.</br>
            <br/>
            <br>This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.</br>
          </comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
          <comment>
            <br>Transmit FIFO Empty (TxFEmp)</br>
            <br/>
            <br>This bit is valid only for IN endpoints</br>
            <br/>
            <br>This interrupt is asserted when the TxFIFO for this endpoint is</br>
            <br>either half or completely empty. The half or completely empty</br>
            <br>status is determined by the TxFIFO Empty Level bit in the Core</br>
            <br>AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).</br>
          </comment>
        </bits>
        <bits access="rw" name="txfifoundrn" pos="8" rst="0">
          <comment>
            <br>Fifo Underrun (TxfifoUndrn)</br>
            <br/>
            <br>Applies to IN endpoints Only</br>
            <br/>
            <br>This bit is valid only If thresholding is enabled. The core generates this interrupt when</br>
            <br>it detects a transmit FIFO underrun condition for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz12" protect="rw">
        <comment>Device IN Endpoint 12 Transfer Size Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet from the</br>
            <br>external memory is written to the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.</br>
            <br/>
            <br>This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="mc" pos="30:29" rst="0">
          <comment>
            <br>MC</br>
            <br/>
            <br>Applies to IN endpoints only.</br>
            <br/>
            <br>For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. </br>
            <br> - 2'b01: 1 packet </br>
            <br> - 2'b10: 2 packets </br>
            <br> - 2'b11: 3 packets </br>
            <br>For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdma12" protect="rw">
        <comment>Device IN Endpoint 12 DMA Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <reg name="dtxfsts12" protect="r">
        <comment>Device IN Endpoint Transmit FIFO Status Register 12
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="3759">
          <comment>
            <br>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</br>
            <br/>
            <br>Indicates the amount of free space available in the Endpoint TxFIFO.</br>
            <br/>
            <br>Values are in terms of 32-bit words.</br>
            <br> - 16'h0: Endpoint TxFIFO is full</br>
            <br> - 16'h1: 1 word available</br>
            <br> - 16'h2: 2 words available</br>
            <br> - 16'hn: n words available (where 0  n  32,768)</br>
            <br> - 16'h8000: 32,768 words available</br>
            <br> - Others: Reserved</br>
          </comment>
        </bits>
      </reg>
      <reg name="diepdmab12" protect="r">
        <comment>Device IN Endpoint 12 Buffer Address Register
Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <hole size="768"/>
      <reg name="doepctl0" protect="rw">
        <comment>Device Control OUT Endpoint 0 Control Register</comment>
        <bits access="r" name="mps" pos="1:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0.</br>
            <br> - 2'b00: 64 bytes</br>
            <br> - 2'b01: 32 bytes</br>
            <br> - 2'b10: 16 bytes</br>
            <br> - 2'b11: 8 bytes</br>
          </comment>
        </bits>
        <bits access="r" name="usbactep" pos="15" rst="1">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>This bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit, the core</br>
            <br>stops receiving data, even If there is space in the RxFIFO to</br>
            <br>accommodate the incoming packet. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with</br>
            <br>an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="r" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>Hardcoded to 2'b00 for control.</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when</br>
            <br>a SETUP token is received for this endpoint. If a NAK bit or</br>
            <br>Global OUT NAK is Set along with this bit, the STALL bit takes</br>
            <br>priority. Irrespective of this bit's setting, the core always</br>
            <br>responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br>Clear NAK (CNAK)</br>
            <br/>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br>Using this bit, the application can control the transmission of NAK handshakes on an endpoint.</br>
            <br>The core can also set bit on a Transfer Completed interrupt, or after a SETUP is received on the endpoint.</br>
          </comment>
        </bits>
        <bits access="r" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>The application cannot disable control OUT endpoint 0.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br> - When Scatter/Gather DMA mode is enabled, for OUT endpoints this bit indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br> - When Scatter/Gather DMA mode is disabled (such as for buffer-pointer based DMA mode)this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br> - The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> -- SETUP Phase Done</br>
            <br> -- Endpoint Disabled</br>
            <br> -- Transfer Completed</br>
            <br>Note: In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory.</br>
            <br/>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint0" protect="rw">
        <comment>Device OUT Endpoint 0 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled</br>
            <br> - For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> - For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br>Note: In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory. When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint</br>
            <br>was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. </br>
            <br/>
            <br>This interrupt is asserted when the core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the core to process, such as Host busy or DMA</br>
            <br>done.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz0" protect="rw">
        <comment>Device OUT Endpoint 0 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="6:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br/>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="rw" name="supcnt" pos="30:29" rst="0">
          <comment>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma0" protect="rw">
        <comment>Device OUT Endpoint 0 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab0" protect="r">
        <comment>Device OUT Endpoint 16 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br/>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is</br>
            <br>reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl1" protect="rw">
        <comment>Device Control OUT Endpoint 1 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint1" protect="rw">
        <comment>Device OUT Endpoint 1 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz1" protect="rw">
        <comment>Device OUT Endpoint 1 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma1" protect="rw">
        <comment>Device OUT Endpoint 1 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab1" protect="r">
        <comment>Device OUT Endpoint 1 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl2" protect="rw">
        <comment>Device Control OUT Endpoint 2 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint2" protect="rw">
        <comment>Device OUT Endpoint 2 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz2" protect="rw">
        <comment>Device OUT Endpoint 2 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma2" protect="rw">
        <comment>Device OUT Endpoint 2 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab2" protect="r">
        <comment>Device OUT Endpoint 2 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl3" protect="rw">
        <comment>Device Control OUT Endpoint 3 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint3" protect="rw">
        <comment>Device OUT Endpoint 3 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz3" protect="rw">
        <comment>Device OUT Endpoint 3 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma3" protect="rw">
        <comment>Device OUT Endpoint 3 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab3" protect="r">
        <comment>Device OUT Endpoint 3 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl4" protect="rw">
        <comment>Device Control OUT Endpoint 4 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint4" protect="rw">
        <comment>Device OUT Endpoint 4 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz4" protect="rw">
        <comment>Device OUT Endpoint 4 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma4" protect="rw">
        <comment>Device OUT Endpoint 4 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab4" protect="r">
        <comment>Device OUT Endpoint 4 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl5" protect="rw">
        <comment>Device Control OUT Endpoint 5 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint5" protect="rw">
        <comment>Device OUT Endpoint 5 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz5" protect="rw">
        <comment>Device OUT Endpoint 5 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma5" protect="rw">
        <comment>Device OUT Endpoint 5 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab5" protect="r">
        <comment>Device OUT Endpoint 5 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl6" protect="rw">
        <comment>Device Control OUT Endpoint 6 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint6" protect="rw">
        <comment>Device OUT Endpoint 6 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz6" protect="rw">
        <comment>Device OUT Endpoint 6 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma6" protect="rw">
        <comment>Device OUT Endpoint 6 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab6" protect="r">
        <comment>Device OUT Endpoint 6 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl7" protect="rw">
        <comment>Device Control OUT Endpoint 7 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint7" protect="rw">
        <comment>Device OUT Endpoint 7 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz7" protect="rw">
        <comment>Device OUT Endpoint 7 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma7" protect="rw">
        <comment>Device OUT Endpoint 7 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab7" protect="r">
        <comment>Device OUT Endpoint 7 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl8" protect="rw">
        <comment>Device Control OUT Endpoint 8 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint8" protect="rw">
        <comment>Device OUT Endpoint 8 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz8" protect="rw">
        <comment>Device OUT Endpoint 8 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma8" protect="rw">
        <comment>Device OUT Endpoint 8 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab8" protect="r">
        <comment>Device OUT Endpoint 8 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl9" protect="rw">
        <comment>Device Control OUT Endpoint 9 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint9" protect="rw">
        <comment>Device OUT Endpoint 9 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz9" protect="rw">
        <comment>Device OUT Endpoint 9 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma9" protect="rw">
        <comment>Device OUT Endpoint 9 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab9" protect="r">
        <comment>Device OUT Endpoint 9 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl10" protect="rw">
        <comment>Device Control OUT Endpoint 10 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint10" protect="rw">
        <comment>Device OUT Endpoint 10 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz10" protect="rw">
        <comment>Device OUT Endpoint 10 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma10" protect="rw">
        <comment>Device OUT Endpoint 10 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab10" protect="r">
        <comment>Device OUT Endpoint 10 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl11" protect="rw">
        <comment>Device Control OUT Endpoint 11 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint11" protect="rw">
        <comment>Device OUT Endpoint 11 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz11" protect="rw">
        <comment>Device OUT Endpoint 11 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma11" protect="rw">
        <comment>Device OUT Endpoint 11 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab11" protect="r">
        <comment>Device OUT Endpoint 11 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepctl12" protect="rw">
        <comment>Device Control OUT Endpoint 12 Control Register</comment>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <comment>
            <br>Maximum Packet Size (MPS)</br>
            <br/>
            <br>The application must program this field with the maximum packet size for the current</br>
            <br>logical endpoint. This value is in bytes.</br>
          </comment>
        </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
          <comment>
            <br>USB Active Endpoint (USBActEP)</br>
            <br/>
            <br>Indicates whether this endpoint is active in the current configuration and interface. The</br>
            <br>core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After</br>
            <br>receiving the SetConfiguration and SetInterface commands, the application must</br>
            <br>program endpoint registers accordingly and set this bit.</br>
          </comment>
        </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
          <comment>
            <br>Endpoint Data PID (DPID)</br>
            <br/>
            <br>Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br/>
            <br>Contains the PID of the packet to be received or transmitted on this endpoint. The</br>
            <br>application must program the PID of the first packet to be received or transmitted on</br>
            <br>this endpoint, after the endpoint is activated. The applications use the SetD1PID and</br>
            <br>SetD0PID fields of this register to program either DATA0 or DATA1 PID.</br>
            <br> - 1'b0: DATA0</br>
            <br> - 1'b1: DATA1</br>
            <br>This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br/>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Even/Odd (Micro)Frame (EO_FrNum)</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode:</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.</br>
            <br> -- 1'b0: Even (micro)frame</br>
            <br> -- 1'b1: Odd (micro)frame</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
          <comment>
            <br>NAK Status (NAKSts)</br>
            <br/>
            <br>Indicates the following:</br>
            <br> - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.</br>
            <br> - 1'b1: The core is transmitting NAK handshakes on this endpoint.</br>
            <br>When either the application or the core sets this bit:</br>
            <br> - The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.</br>
            <br> - For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.</br>
            <br> - For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.</br>
            <br>Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.</br>
          </comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
          <comment>
            <br>Endpoint Type (EPType)</br>
            <br/>
            <br>This is the transfer type supported by this logical endpoint.</br>
            <br> - 2'b00: Control</br>
            <br> - 2'b01: Isochronous</br>
            <br> - 2'b10: Bulk</br>
            <br> - 2'b11: Interrupt</br>
          </comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
          <comment>
            <br>RESERVED</br>
          </comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>
            <br>STALL Handshake (Stall)</br>
            <br/>
            <br>Applies to non-control, non-isochronous IN and OUT endpoints only.</br>
            <br/>
            <br>The application sets this bit to stall all tokens from the USB host to this endpoint. If a</br>
            <br>NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the</br>
            <br>STALL bit takes priority. Only the application can clear this bit, never the core.</br>
            <br/>
            <br>Applies to control endpoints only.</br>
            <br/>
            <br>The application can only set this bit, and the core clears it, when a SETUP token is</br>
            <br>received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT</br>
            <br>NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's</br>
            <br>setting, the core always responds to SETUP data packets with an ACK handshake.</br>
            <br/>
          </comment>
        </bits>
        <bits access="w" name="cnak" pos="26" rst="0">
          <comment>
            <br/>
            <br>Clear NAK (CNAK)</br>
            <br>A write to this bit clears the NAK bit for the endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
          <comment>
            <br>Set NAK (SNAK)</br>
            <br/>
            <br>A write to this bit sets the NAK bit for the endpoint.</br>
            <br/>
            <br>Using this bit, the application can control the transmission of NAK</br>
            <br>handshakes on an endpoint. The core can also set this bit for an</br>
            <br>endpoint after a SETUP packet is received on that endpoint.</br>
          </comment>
        </bits>
        <bits access="w" name="setd0pid" pos="28" rst="0">
          <comment>
            <br>Set DATA0 PID (SetD0PID)</br>
            <br> - Applies to interrupt/bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.</br>
            <br> - This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="w" name="setd1pid" pos="29" rst="0">
          <comment>
            <br>Set DATA1 PID (SetD1PID)</br>
            <br> - Applies to interrupt and bulk IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.</br>
            <br> - This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.</br>
            <br>Reset: 1'b0</br>
            <br/>
            <br>Set Odd (micro)frame (SetOddFr)</br>
            <br> - Applies to isochronous IN and OUT endpoints only.</br>
            <br> - Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>
            <br>Endpoint Disable (EPDis)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>The application sets this bit to stop transmitting/receiving data on an endpoint, even</br>
            <br>before the transfer for that endpoint is complete. The application must wait for the</br>
            <br>Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears</br>
            <br>this bit before setting the Endpoint Disabled interrupt. The application must set this bit</br>
            <br>only if Endpoint Enable is already set for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>
            <br>Endpoint Enable (EPEna)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>When Scatter/Gather DMA mode is enabled,</br>
            <br> - For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.</br>
            <br> - For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.</br>
            <br>When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:</br>
            <br> - For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.</br>
            <br> - For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.</br>
            <br>The core clears this bit before setting any of the following interrupts on this endpoint:</br>
            <br> - SETUP Phase Done</br>
            <br> - Endpoint Disabled</br>
            <br> - Transfer Completed</br>
            <br>Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint12" protect="rw">
        <comment>Device OUT Endpoint 12 Interrupt Register</comment>
        <bits access="rw" name="xfercompl" pos="0" rst="0">
          <comment>
            <br>Transfer Completed Interrupt (XferCompl)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br> - When Scatter/Gather DMA mode is enabled</br>
            <br> -- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.</br>
            <br> -- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.</br>
            <br> - When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="epdisbld" pos="1" rst="0">
          <comment>
            <br>Endpoint Disabled Interrupt (EPDisbld)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This bit indicates that the endpoint is disabled per the application's request.</br>
          </comment>
        </bits>
        <bits access="rw" name="ahberr" pos="2" rst="0">
          <comment>
            <br>AHB Error (AHBErr)</br>
            <br/>
            <br>Applies to IN and OUT endpoints.</br>
            <br/>
            <br>This is generated only in Internal DMA mode when there is an</br>
            <br>AHB error during an AHB read/write. The application can read</br>
            <br>the corresponding endpoint DMA address register to get the</br>
            <br>error address.</br>
          </comment>
        </bits>
        <bits access="rw" name="setup" pos="3" rst="0">
          <comment>
            <br>SETUP Phase Done (SetUp)</br>
            <br/>
            <br>Applies to control OUT endpoints only.</br>
            <br/>
            <br>Indicates that the SETUP phase for the control endpoint is</br>
            <br>complete and no more back-to-back SETUP packets were</br>
            <br>received for the current control transfer. On this interrupt, the</br>
            <br>application can decode the received SETUP data packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="outtknepdis" pos="4" rst="0">
          <comment>
            <br>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</br>
            <br/>
            <br>Applies only to control OUT endpoints.</br>
            <br/>
            <br>Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.</br>
          </comment>
        </bits>
        <bits access="rw" name="stsphsercvd" pos="5" rst="0">
          <comment>
            <br>Status Phase Received for Control Write (StsPhseRcvd)</br>
            <br/>
            <br>This interrupt is valid only for Control OUT endpoints and only in</br>
            <br>Scatter Gather DMA mode.</br>
            <br/>
            <br>This interrupt is generated only after the core has transferred all</br>
            <br>the data that the host has sent during the data phase of a control</br>
            <br>write transfer, to the system memory buffer.</br>
            <br/>
            <br>The interrupt indicates to the application that the host has</br>
            <br>switched from data phase to the status phase of a Control Write</br>
            <br>transfer. The application can use this interrupt to ACK or STALL</br>
            <br>the Status phase, after it has decoded the data phase. This is</br>
            <br>applicable only in Case of Scatter Gather DMA mode.</br>
          </comment>
        </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
          <comment>
            <br>Back-to-Back SETUP Packets Received (Back2BackSETup)</br>
            <br/>
            <br>Applies to Control OUT endpoints only.</br>
            <br/>
            <br>This bit indicates that the core has received more than three</br>
            <br>back-to-back SETUP packets for this particular endpoint. For</br>
            <br>information about handling this interrupt,</br>
          </comment>
        </bits>
        <bits access="rw" name="outpkterr" pos="8" rst="0">
          <comment>
            <br>OUT Packet Error (OutPktErr)</br>
            <br/>
            <br>Applies to OUT endpoints Only</br>
            <br/>
            <br>This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the</br>
            <br>core detects an overflow or a CRC error for non-Isochronous OUT packet.</br>
          </comment>
        </bits>
        <bits access="rw" name="bnaintr" pos="9" rst="0">
          <comment>
            <br>BNA (Buffer Not Available) Interrupt (BNAIntr)</br>
            <br/>
            <br>This bit is valid only when Scatter/Gather DMA mode is enabled.</br>
            <br/>
            <br>The core generates this interrupt when the descriptor accessed</br>
            <br>is not ready for the Core to process, such as Host busy or DMA</br>
            <br>done</br>
          </comment>
        </bits>
        <bits access="rw" name="pktdrpsts" pos="11" rst="0">
          <comment>
            <br>Packet Drop Status (PktDrpSts)</br>
            <br/>
            <br>This bit indicates to the application that an ISOC OUT packet has been dropped. This</br>
            <br>bit does not have an associated mask bit and does not generate an interrupt.</br>
            <br/>
            <br>Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer</br>
            <br>interrupt feature is selected.</br>
          </comment>
        </bits>
        <bits access="rw" name="bbleerr" pos="12" rst="0">
          <comment>
            <br>NAK Interrupt (BbleErr)</br>
            <br/>
            <br>The core generates this interrupt when babble is received for the endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="nakintrpt" pos="13" rst="0">
          <comment>
            <br>NAK Interrupt (NAKInterrupt)</br>
            <br/>
            <br>The core generates this interrupt when a NAK is transmitted or received by the device.</br>
            <br/>
            <br>In case of isochronous IN endpoints the interrupt gets generated when a zero length</br>
            <br>packet is transmitted due to un-availability of data in the TXFifo.</br>
          </comment>
        </bits>
        <bits access="rw" name="nyetintrpt" pos="14" rst="0">
          <comment>
            <br>NYET Interrupt (NYETIntrpt)</br>
            <br/>
            <br>The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.</br>
          </comment>
        </bits>
        <bits access="rw" name="stuppktrcvd" pos="15" rst="0">
          <comment>
            <br>Setup Packet Received</br>
            <br/>
            <br>Applicable for Control OUT Endpoints in only in the Buffer DMA Mode</br>
            <br/>
            <br>Set by the controller, this bit indicates that this buffer holds 8 bytes of</br>
            <br>setup data. There is only one Setup packet per buffer. On receiving a</br>
            <br>Setup packet, the controller closes the buffer and disables the</br>
            <br>corresponding endpoint. The application has to re-enable the endpoint to</br>
            <br>receive any OUT data for the Control Transfer and reprogram the buffer</br>
            <br>start address.</br>
            <br/>
            <br>Note: Because of the above behavior, the controller can receive any</br>
            <br>number of back to back setup packets and one buffer for every setup</br>
            <br>packet is used.</br>
            <br> - 1'b0: No Setup packet received</br>
            <br> - 1'b1: Setup packet received</br>
            <br>Reset: 1'b0</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz12" protect="rw">
        <comment>Device OUT Endpoint 12 Transfer Size Register</comment>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
          <comment>
            <br>Transfer Size (XferSize)</br>
            <br/>
            <br>Indicates the transfer size in bytes for endpoint 0. The core</br>
            <br>interrupts the application only after it has exhausted the transfer</br>
            <br>size amount of data. The transfer size can be Set to the</br>
            <br>maximum packet size of the endpoint, to be interrupted at the</br>
            <br>end of each packet.</br>
            <br/>
            <br>The core decrements this field every time a packet is read from</br>
            <br>the RxFIFO and written to the external memory.</br>
          </comment>
        </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
          <comment>
            <br>Packet Count (PktCnt)</br>
            <br>This field is decremented to zero after a packet is written into the RxFIFO.</br>
          </comment>
        </bits>
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
          <comment>
            <br>RxDPID</br>
            <br/>
            <br>Applies to isochronous OUT endpoints only.</br>
            <br/>
            <br>This is the data PID received in the last packet for this endpoint.</br>
            <br> - 2'b00: DATA0</br>
            <br> - 2'b01: DATA2</br>
            <br> - 2'b10: DATA1</br>
            <br> - 2'b11: MDATA</br>
            <br>SETUP Packet Count (SUPCnt)</br>
            <br/>
            <br>Applies to control OUT Endpoints only.</br>
            <br/>
            <br>This field specifies the number of back-to-back SETUP data</br>
            <br>packets the endpoint can receive.</br>
            <br> - 2'b01: 1 packet</br>
            <br> - 2'b10: 2 packets</br>
            <br> - 2'b11: 3 packets</br>
          </comment>
        </bits>
      </reg>
      <reg name="doepdma12" protect="rw">
        <comment>Device OUT Endpoint 12 DMA Address Register</comment>
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the start address of the external memory for storing or fetching endpoint</br>
            <br>data.</br>
            <br/>
            <br>Note: For control endpoints, this field stores control OUT data packets as well as</br>
            <br>SETUP transaction data packets. When more than three SETUP packets are</br>
            <br>received back-to-back, the SETUP data packet in the memory is overwritten.</br>
            <br/>
            <br>This register is incremented on every AHB transaction. The application can give</br>
            <br>only a DWORD-aligned address.</br>
            <br> - When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.</br>
            <br> - When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.</br>
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab12" protect="r">
        <comment>Device OUT Endpoint 12 Buffer Address Register</comment>
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>
            <br>Holds the current buffer address.This register is updated as and when the data</br>
            <br>transfer for the corresponding end point is in progress.</br>
            <br/>
            <br>This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.</br>
          </comment>
        </bits>
      </reg>
      <hole size="2816"/>
      <reg name="pcgcctl" protect="rw">
        <comment>Power and Clock Gating Control Register</comment>
        <bits access="rw" name="stoppclk" pos="0" rst="0">
          <comment>
            <br>Stop Pclk (StopPclk)</br>
            <br> - The application sets this bit to stop the PHY clock (phy_clk) when the USB is suspended, the session is not valid, or the device is disconnected.</br>
            <br> - The application clears this bit when the USB is resumed or a new session starts.</br>
          </comment>
        </bits>
        <bits access="rw" name="rstpdwnmodule" pos="3" rst="0">
          <comment>
            <br>Reset Power-Down Modules (RstPdwnModule)</br>
            <br/>
            <br>This bit is valid only in Partial Power-Down mode. </br>
            <br> - The application sets this bit when the power is turned off. </br>
            <br> - The application clears this bit after the power is turned on and the PHY clock is up.</br>
            <br/>
            <br>Note: The R/W of all core registers are possible only when this bit is set to 1b0.</br>
          </comment>
        </bits>
        <bits access="r" name="physleep" pos="6" rst="0">
          <comment>
            <br>PHY In Sleep </br>
            <br/>
            <br>Indicates that the PHY is in Sleep State.</br>
          </comment>
        </bits>
        <bits access="r" name="l1suspended" pos="7" rst="0">
          <comment>
            <br>L1 Deep Sleep </br>
            <br/>
            <br>Indicates that the PHY is in deep sleep when in L1 state.</br>
          </comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="usbc11.xml">
    <module category="System" name="USBC11">
      <reg name="gotgctl" protect="rw">
        <bits access="r" name="curmod" pos="21" rst="0">
      </bits>
        <bits access="rw" name="otgver" pos="20" rst="0">
      </bits>
        <bits access="r" name="bsesvld" pos="19" rst="1">
      </bits>
        <bits access="rw" name="asesvld" pos="18" rst="1">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
        <bits access="r" name="dbnctime" pos="17" rst="0">
      </bits>
        <bits access="r" name="conidsts" pos="16" rst="1">
      </bits>
        <bits access="rw" name="dbncefltrbypass" pos="15" rst="0">
      </bits>
        <bits access="rw" name="bvalidovval" pos="7" rst="0">
      </bits>
        <bits access="rw" name="bvalidoven" pos="6" rst="0">
      </bits>
        <bits access="rw" name="avalidovval" pos="5" rst="0">
      </bits>
        <bits access="rw" name="avalidoven" pos="4" rst="0">
      </bits>
        <bits access="rw" name="vbvalidovval" pos="3" rst="0">
      </bits>
        <bits access="rw" name="vbvalidoven" pos="2" rst="0">
      </bits>
      </reg>
      <reg name="gotgint" protect="rw">
        <bits access="rc" name="dbncedone" pos="19" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="adevtoutchg" pos="18" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="hstnegdet" pos="17" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="hstnegsucstschng" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="sesreqsucstschng" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="sesenddet" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="gahbcfg" protect="rw">
        <bits access="rw" name="invdescendianess" pos="24" rst="0">
      </bits>
        <bits access="rw" name="ahbsingle" pos="23" rst="0">
      </bits>
        <bits access="rw" name="notialldmawrit" pos="22" rst="0">
      </bits>
        <bits access="rw" name="remmemsupp" pos="21" rst="0">
      </bits>
        <bits access="rw" name="nptxfemplvl" pos="7" rst="0">
      </bits>
        <bits access="rw" name="dmaen" pos="5" rst="0">
      </bits>
        <bits access="rw" name="hbstlen" pos="4:1" rst="0">
      </bits>
        <bits access="rw" name="glblintrmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="gusbcfg" protect="rw">
        <bits access="rw" name="corrupttxpkt" pos="31" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="forcedevmode" pos="30" rst="0">
      </bits>
        <bits access="rw" name="forcehstmode" pos="29" rst="0">
      </bits>
        <bits access="rw" name="txenddelay" pos="28" rst="0">
      </bits>
        <bits access="r" name="ic_usbcap" pos="26" rst="0">
      </bits>
        <bits access="r" name="termseldlpulse" pos="22" rst="0">
      </bits>
        <bits access="rw" name="usbtrdtim" pos="13:10" rst="5">
      </bits>
        <bits access="r" name="physel" pos="6" rst="1">
      </bits>
        <bits access="rw" name="fsintf" pos="5" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="phyif" pos="3" rst="0">
      </bits>
        <bits access="rw" name="toutcal" pos="2:0" rst="0">
      </bits>
      </reg>
      <reg name="grstctl" protect="rw">
        <bits access="r" name="ahbidle" pos="31" rst="1">
      </bits>
        <bits access="r" name="dmareq" pos="30" rst="0">
      </bits>
        <bits access="rw" name="txfnum" pos="10:6" rst="0">
      </bits>
        <bits access="rw" name="txfflsh" pos="5" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="rxfflsh" pos="4" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="frmcntrrst" pos="2" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="piufssftrst" pos="1" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="csftrst" pos="0" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
      </reg>
      <reg name="gintsts" protect="rw">
        <bits access="rc" name="wkupint" pos="31" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="sessreqint" pos="30" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="disconnint" pos="29" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rw" name="conidstschng" pos="28" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="r" name="hchint" pos="25" rst="0">
      </bits>
        <bits access="r" name="prtint" pos="24" rst="0">
      </bits>
        <bits access="rc" name="resetdet" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="fetsusp" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="incomplp" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="incompisoin" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="oepint" pos="19" rst="0">
      </bits>
        <bits access="r" name="iepint" pos="18" rst="0">
      </bits>
        <bits access="rc" name="epmis" pos="17" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="eopf" pos="15" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="isooutdrop" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="enumdone" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="usbrst" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="usbsusp" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="erlysusp" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="goutnakeff" pos="7" rst="0">
      </bits>
        <bits access="r" name="ginnakeff" pos="6" rst="0">
      </bits>
        <bits access="r" name="nptxfemp" pos="5" rst="1">
      </bits>
        <bits access="r" name="rxflvl" pos="4" rst="0">
      </bits>
        <bits access="rw" name="sof" pos="3" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="otgint" pos="2" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
        <bits access="rc" name="modemis" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="curmod" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="gintmsk" protect="rw">
        <bits access="rw" name="wkupintmsk" pos="31" rst="0">
      </bits>
        <bits access="rw" name="sessreqintmsk" pos="30" rst="0">
      </bits>
        <bits access="rw" name="disconnintmsk" pos="29" rst="0">
      </bits>
        <bits access="rw" name="conidstschngmsk" pos="28" rst="0">
      </bits>
        <bits access="rw" name="hchintmsk" pos="25" rst="0">
      </bits>
        <bits access="rw" name="prtintmsk" pos="24" rst="0">
      </bits>
        <bits access="rw" name="resetdetmsk" pos="23" rst="0">
      </bits>
        <bits access="rw" name="fetsuspmsk" pos="22" rst="0">
      </bits>
        <bits access="rw" name="incomplpmsk" pos="21" rst="0">
      </bits>
        <bits access="rw" name="oepintmsk" pos="19" rst="0">
      </bits>
        <bits access="rw" name="iepintmsk" pos="18" rst="0">
      </bits>
        <bits access="rw" name="epmismsk" pos="17" rst="0">
      </bits>
        <bits access="rw" name="eopfmsk" pos="15" rst="0">
      </bits>
        <bits access="rw" name="isooutdropmsk" pos="14" rst="0">
      </bits>
        <bits access="rw" name="enumdonemsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="usbrstmsk" pos="12" rst="0">
      </bits>
        <bits access="rw" name="usbsuspmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="erlysuspmsk" pos="10" rst="0">
      </bits>
        <bits access="rw" name="goutnakeffmsk" pos="7" rst="0">
      </bits>
        <bits access="rw" name="ginnakeffmsk" pos="6" rst="0">
      </bits>
        <bits access="rw" name="nptxfempmsk" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rxflvlmsk" pos="4" rst="0">
      </bits>
        <bits access="rw" name="sofmsk" pos="3" rst="0">
      </bits>
        <bits access="rw" name="otgintmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="modemismsk" pos="1" rst="0">
      </bits>
      </reg>
      <reg name="grxstsr" protect="rw">
        <bits access="r" name="fn" pos="24:21" rst="0">
      </bits>
        <bits access="rw" name="pktsts" pos="20:17" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
        <bits access="r" name="dpid" pos="16:15" rst="0">
      </bits>
        <bits access="r" name="bcnt" pos="14:4" rst="0">
      </bits>
        <bits access="rw" name="chnum" pos="3:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="grxstsp" protect="rw">
        <bits access="r" name="fn" pos="24:21" rst="0">
      </bits>
        <bits access="rw" name="pktsts" pos="20:17" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
        <bits access="r" name="dpid" pos="16:15" rst="0">
      </bits>
        <bits access="r" name="bcnt" pos="14:4" rst="0">
      </bits>
        <bits access="rw" name="chnum" pos="3:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="grxfsiz" protect="rw">
        <bits access="rw" name="rxfdep" pos="8:0" rst="297">
      </bits>
      </reg>
      <reg name="gnptxfsiz" protect="rw">
        <bits access="rw" name="nptxfdep" pos="24:16" rst="297">
      </bits>
        <bits access="rw" name="nptxfstaddr" pos="8:0" rst="297">
      </bits>
      </reg>
      <reg name="gnptxsts" protect="rw">
        <bits access="r" name="nptxqtop" pos="30:24" rst="0">
      </bits>
        <bits access="r" name="nptxqspcavail" pos="23:16" rst="8">
      </bits>
        <bits access="r" name="nptxfspcavail" pos="15:0" rst="297">
      </bits>
      </reg>
      <hole size="64"/>
      <reg name="ggpio" protect="rw">
        <bits access="rw" name="gpo" pos="31:16" rst="0">
      </bits>
        <bits access="r" name="gpi" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="guid" protect="rw">
        <bits access="rw" name="guid" pos="31:0" rst="3221291008">
      </bits>
      </reg>
      <reg name="gsnpsid" protect="r">
        <bits access="r" name="synopsysid" pos="31:0" rst="1330921482">
      </bits>
      </reg>
      <reg name="ghwcfg1" protect="r">
        <bits access="r" name="epdir" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="ghwcfg2" protect="rw">
        <bits access="r" name="tknqdepth" pos="30:26" rst="8">
      </bits>
        <bits access="r" name="ptxqdepth" pos="25:24" rst="2">
      </bits>
        <bits access="r" name="nptxqdepth" pos="23:22" rst="2">
      </bits>
        <bits access="r" name="multiprocintrpt" pos="20" rst="0">
      </bits>
        <bits access="r" name="dynfifosizing" pos="19" rst="1">
      </bits>
        <bits access="r" name="periosupport" pos="18" rst="0">
      </bits>
        <bits access="r" name="numhstchnl" pos="17:14" rst="11">
      </bits>
        <bits access="r" name="numdeveps" pos="13:10" rst="5">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="fsphytype" pos="9:8" rst="1">
      </bits>
        <bits access="r" name="hsphytype" pos="7:6" rst="0">
      </bits>
        <bits access="r" name="singpnt" pos="5" rst="0">
      </bits>
        <bits access="r" name="otgarch" pos="4:3" rst="2">
      </bits>
        <bits access="r" name="otgmode" pos="2:0" rst="2">
      </bits>
      </reg>
      <reg name="ghwcfg3" protect="r">
        <bits access="r" name="dfifodepth" pos="31:16" rst="285">
      </bits>
        <bits access="r" name="lpmmode" pos="15" rst="0">
      </bits>
        <bits access="r" name="bcsupport" pos="14" rst="0">
      </bits>
        <bits access="r" name="hsicmode" pos="13" rst="0">
      </bits>
        <bits access="r" name="adpsupport" pos="12" rst="0">
      </bits>
        <bits access="r" name="rsttype" pos="11" rst="0">
      </bits>
        <bits access="r" name="optfeature" pos="10" rst="0">
      </bits>
        <bits access="r" name="vndctlsupt" pos="9" rst="0">
      </bits>
        <bits access="r" name="i2cintsel" pos="8" rst="0">
      </bits>
        <bits access="r" name="otgen" pos="7" rst="1">
      </bits>
        <bits access="r" name="pktsizewidth" pos="6:4" rst="6">
      </bits>
        <bits access="r" name="xfersizewidth" pos="3:0" rst="8">
      </bits>
      </reg>
      <reg name="ghwcfg4" protect="rw">
        <bits access="r" name="descdma" pos="31" rst="0">
      </bits>
        <bits access="r" name="descdmaenabled" pos="30" rst="0">
      </bits>
        <bits access="r" name="ineps" pos="29:26" rst="5">
      </bits>
        <bits access="r" name="dedfifomode" pos="25" rst="1">
      </bits>
        <bits access="r" name="sessendfltr" pos="24" rst="0">
      </bits>
        <bits access="r" name="bvalidfltr" pos="23" rst="0">
      </bits>
        <bits access="r" name="avalidfltr" pos="22" rst="0">
      </bits>
        <bits access="r" name="vbusvalidfltr" pos="21" rst="0">
      </bits>
        <bits access="r" name="iddgfltr" pos="20" rst="1">
      </bits>
        <bits access="r" name="numctleps" pos="19:16" rst="0">
      </bits>
        <bits access="r" name="phydatawidth" pos="15:14" rst="2">
      </bits>
        <bits access="r" name="enhancedlpmsupt" pos="13" rst="1">
      </bits>
        <bits access="r" name="acgsupt" pos="12" rst="0">
      </bits>
        <bits access="r" name="extendedhibernation" pos="7" rst="0">
      </bits>
        <bits access="r" name="hibernation" pos="6" rst="0">
      </bits>
        <bits access="r" name="ahbfreq" pos="5" rst="1">
      </bits>
        <bits access="r" name="partialpwrdn" pos="4" rst="0">
      </bits>
        <bits access="r" name="numdevperioeps" pos="3:0" rst="0">
      </bits>
      </reg>
      <hole size="64"/>
      <reg name="gdfifocfg" protect="rw">
        <bits access="rw" name="epinfobaseaddr" pos="31:16" rst="285">
      </bits>
        <bits access="rw" name="gdfifocfg" pos="15:0" rst="297">
      </bits>
      </reg>
      <hole size="1280"/>
      <reg name="hptxfsiz" protect="rw">
        <bits access="rw" name="ptxfsize" pos="26:16" rst="1024">
      </bits>
        <bits access="rw" name="ptxfstaddr" pos="9:0" rst="594">
      </bits>
      </reg>
      <reg name="dieptxf1" protect="rw">
        <bits access="rw" name="inepntxfdep" pos="21:16" rst="32">
      </bits>
        <bits access="rw" name="inepntxfstaddr" pos="8:0" rst="329">
      </bits>
      </reg>
      <reg name="dieptxf2" protect="rw">
        <bits access="rw" name="inepntxfdep" pos="21:16" rst="32">
      </bits>
        <bits access="rw" name="inepntxfstaddr" pos="8:0" rst="361">
      </bits>
      </reg>
      <reg name="dieptxf3" protect="rw">
        <bits access="rw" name="inepntxfdep" pos="21:16" rst="32">
      </bits>
        <bits access="rw" name="inepntxfstaddr" pos="8:0" rst="393">
      </bits>
      </reg>
      <reg name="dieptxf4" protect="rw">
        <bits access="rw" name="inepntxfdep" pos="21:16" rst="32">
      </bits>
        <bits access="rw" name="inepntxfstaddr" pos="8:0" rst="425">
      </bits>
      </reg>
      <reg name="dieptxf5" protect="rw">
        <bits access="rw" name="inepntxfdep" pos="21:16" rst="32">
      </bits>
        <bits access="rw" name="inepntxfstaddr" pos="8:0" rst="457">
      </bits>
      </reg>
      <hole size="5952"/>
      <reg name="hcfg" protect="rw">
        <bits access="rw" name="modechtimen" pos="31" rst="0">
      </bits>
        <bits access="rw" name="perschedena" pos="26" rst="0">
      </bits>
        <bits access="rw" name="frlisten" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="descdma" pos="23" rst="0">
      </bits>
        <bits access="rw" name="resvalid" pos="15:8" rst="2">
      </bits>
        <bits access="rw" name="ena32khzs" pos="7" rst="0">
      </bits>
        <bits access="rw" name="fslssupp" pos="2" rst="0">
      </bits>
        <bits access="rw" name="fslspclksel" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="hfir" protect="rw">
        <bits access="rw" name="hfirrldctrl" pos="16" rst="0">
      </bits>
        <bits access="rw" name="frint" pos="15:0" rst="60000">
      </bits>
      </reg>
      <reg name="hfnum" protect="r">
        <bits access="r" name="frrem" pos="31:16" rst="0">
      </bits>
        <bits access="r" name="frnum" pos="15:0" rst="16383">
      </bits>
      </reg>
      <hole size="64"/>
      <reg name="haint" protect="rw">
        <bits access="r" name="haint" pos="11:0" rst="0">
      </bits>
      </reg>
      <reg name="haintmsk" protect="rw">
        <bits access="rw" name="haintmsk" pos="11:0" rst="0">
      </bits>
      </reg>
      <reg name="hflbaddr" protect="rw">
        <bits access="rw" name="hflbaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="256"/>
      <reg name="hprt" protect="rw">
        <bits access="r" name="prtspd" pos="18:17" rst="0">
      </bits>
        <bits access="rw" name="prttstctl" pos="16:13" rst="0">
      </bits>
        <bits access="rw" name="prtpwr" pos="12" rst="0">
      </bits>
        <bits access="r" name="prtlnsts" pos="11:10" rst="0">
      </bits>
        <bits access="rw" name="prtrst" pos="8" rst="0">
      </bits>
        <bits access="rw" name="prtsusp" pos="7" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="prtres" pos="6" rst="0">
      </bits>
        <bits access="rc" name="prtovrcurrchng" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="prtovrcurract" pos="4" rst="0">
      </bits>
        <bits access="rc" name="prtenchng" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="prtena" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="prtconndet" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="prtconnsts" pos="0" rst="0">
      </bits>
      </reg>
      <hole size="1504"/>
      <reg name="hcchar0" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <reg name="hcsplt0" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint0" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk0" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz0" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma0" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab0" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar1" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt1" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint1" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk1" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz1" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma1" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab1" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar2" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt2" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint2" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk2" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz2" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma2" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab2" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar3" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt3" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint3" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk3" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz3" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma3" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab3" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar4" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt4" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint4" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk4" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz4" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma4" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab4" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar5" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt5" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint5" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk5" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz5" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma5" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab5" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar6" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt6" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint6" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk6" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz6" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma6" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab6" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar7" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt7" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint7" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk7" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz7" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma7" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab7" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar8" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt8" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint8" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk8" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz8" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma8" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab8" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar9" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt9" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint9" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk9" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz9" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma9" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab9" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar10" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt10" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint10" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk10" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz10" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma10" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab10" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="hcchar11" protect="rw">
        <bits access="rw" name="chena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="chdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="oddfrm" pos="29" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="28:22" rst="0">
      </bits>
        <bits access="rw" name="ec" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="lspddev" pos="17" rst="0">
      </bits>
        <bits access="rw" name="epdir" pos="15" rst="0">
      </bits>
        <bits access="rw" name="epnum" pos="14:11" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <reg name="hcsplt11" protect="rw">
        <bits access="rw" name="spltena" pos="31" rst="0">
      </bits>
        <bits access="rw" name="compsplt" pos="16" rst="0">
      </bits>
        <bits access="rw" name="xactpos" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="hubaddr" pos="13:7" rst="0">
      </bits>
        <bits access="rw" name="prtaddr" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="hcint11" protect="rw">
        <bits access="rc" name="desc_lst_rollintr" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xcs_xact_err" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="datatglerr" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="frmovrun" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bblerr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xacterr" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyet" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ack" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nak" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stall" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="chhltd" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <reg name="hcintmsk11" protect="rw">
        <bits access="rw" name="desc_lst_rollintrmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnaintrmsk" pos="11" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="chhltdmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="hctsiz11" protect="rw">
        <bits access="rw" name="dopng" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="hcdma11" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="hcdmab11" protect="r">
        <bits access="r" name="hcdmab" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="3072"/>
      <reg name="dcfg" protect="rw">
        <bits access="rw" name="resvalid" pos="31:26" rst="2">
      </bits>
        <bits access="rw" name="perschintvl" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="descdma" pos="23" rst="0">
      </bits>
        <bits access="rw" name="erraticintmsk" pos="15" rst="0">
      </bits>
        <bits access="rw" name="xcvrdly" pos="14" rst="0">
      </bits>
        <bits access="rw" name="endevoutnak" pos="13" rst="0">
      </bits>
        <bits access="rw" name="perfrint" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="devaddr" pos="10:4" rst="0">
      </bits>
        <bits access="rw" name="ena32khzsusp" pos="3" rst="0">
      </bits>
        <bits access="rw" name="nzstsouthshk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="devspd" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="dctl" protect="rw">
        <bits access="rw" name="encontonbna" pos="17" rst="0">
      </bits>
        <bits access="rw" name="nakonbble" pos="16" rst="0">
      </bits>
        <bits access="rw" name="ignrfrmnum" pos="15" rst="0">
      </bits>
        <bits access="rw" name="gmc" pos="14:13" rst="0">
      </bits>
        <bits access="rw" name="pwronprgdone" pos="11" rst="0">
      </bits>
        <bits access="rw" name="cgoutnak" pos="10" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="sgoutnak" pos="9" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cgnpinnak" pos="8" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="sgnpinnak" pos="7" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="tstctl" pos="6:4" rst="0">
      </bits>
        <bits access="r" name="goutnaksts" pos="3" rst="0">
      </bits>
        <bits access="r" name="gnpinnaksts" pos="2" rst="0">
      </bits>
        <bits access="rw" name="sftdiscon" pos="1" rst="1">
      </bits>
        <bits access="rw" name="rmtwkupsig" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="dsts" protect="rw">
        <bits access="r" name="devlnsts" pos="23:22" rst="0">
      </bits>
        <bits access="rw" name="soffn" pos="21:8" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
        <bits access="r" name="errticerr" pos="3" rst="0">
      </bits>
        <bits access="r" name="enumspd" pos="2:1" rst="1">
      </bits>
        <bits access="r" name="suspsts" pos="0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepmsk" protect="rw">
        <bits access="rw" name="nakmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bnainintrmsk" pos="9" rst="0">
      </bits>
        <bits access="rw" name="txfifoundrnmsk" pos="8" rst="0">
      </bits>
        <bits access="rw" name="inepnakeffmsk" pos="6" rst="0">
      </bits>
        <bits access="rw" name="intknepmismsk" pos="5" rst="0">
      </bits>
        <bits access="rw" name="intkntxfempmsk" pos="4" rst="0">
      </bits>
        <bits access="rw" name="timeoutmsk" pos="3" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="epdisbldmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="doepmsk" protect="rw">
        <bits access="rw" name="nyetmsk" pos="14" rst="0">
      </bits>
        <bits access="rw" name="nakmsk" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bbleerrmsk" pos="12" rst="0">
      </bits>
        <bits access="rw" name="bnaoutintrmsk" pos="9" rst="0">
      </bits>
        <bits access="rw" name="outpkterrmsk" pos="8" rst="0">
      </bits>
        <bits access="rw" name="back2backsetup" pos="6" rst="0">
      </bits>
        <bits access="rw" name="stsphsercvdmsk" pos="5" rst="0">
      </bits>
        <bits access="rw" name="outtknepdismsk" pos="4" rst="0">
      </bits>
        <bits access="rw" name="setupmsk" pos="3" rst="0">
      </bits>
        <bits access="rw" name="ahberrmsk" pos="2" rst="0">
      </bits>
        <bits access="rw" name="epdisbldmsk" pos="1" rst="0">
      </bits>
        <bits access="rw" name="xfercomplmsk" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="daint" protect="rw">
        <bits access="r" name="outepint5" pos="21" rst="0">
      </bits>
        <bits access="r" name="outepint4" pos="20" rst="0">
      </bits>
        <bits access="r" name="outepint3" pos="19" rst="0">
      </bits>
        <bits access="r" name="outepint2" pos="18" rst="0">
      </bits>
        <bits access="r" name="outepint1" pos="17" rst="0">
      </bits>
        <bits access="r" name="outepint0" pos="16" rst="0">
      </bits>
        <bits access="r" name="inepint5" pos="5" rst="0">
      </bits>
        <bits access="r" name="inepint4" pos="4" rst="0">
      </bits>
        <bits access="r" name="inepint3" pos="3" rst="0">
      </bits>
        <bits access="r" name="inepint2" pos="2" rst="0">
      </bits>
        <bits access="r" name="inepint1" pos="1" rst="0">
      </bits>
        <bits access="r" name="inepint0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="daintmsk" protect="rw">
        <bits access="rw" name="outepmsk5" pos="21" rst="0">
      </bits>
        <bits access="rw" name="outepmsk4" pos="20" rst="0">
      </bits>
        <bits access="rw" name="outepmsk3" pos="19" rst="0">
      </bits>
        <bits access="rw" name="outepmsk2" pos="18" rst="0">
      </bits>
        <bits access="rw" name="outepmsk1" pos="17" rst="0">
      </bits>
        <bits access="rw" name="outepmsk0" pos="16" rst="0">
      </bits>
        <bits access="rw" name="inepmsk5" pos="5" rst="0">
      </bits>
        <bits access="rw" name="inepmsk4" pos="4" rst="0">
      </bits>
        <bits access="rw" name="inepmsk3" pos="3" rst="0">
      </bits>
        <bits access="rw" name="inepmsk2" pos="2" rst="0">
      </bits>
        <bits access="rw" name="inepmsk1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="inepmsk0" pos="0" rst="0">
      </bits>
      </reg>
      <hole size="64"/>
      <reg name="dvbusdis" protect="rw">
        <bits access="rw" name="dvbusdis" pos="15:0" rst="6103">
      </bits>
      </reg>
      <reg name="dvbuspulse" protect="rw">
        <bits access="rw" name="dvbuspulse" pos="11:0" rst="1464">
      </bits>
      </reg>
      <reg name="dthrctl" protect="rw">
        <bits access="rw" name="arbprken" pos="27" rst="1">
      </bits>
        <bits access="rw" name="rxthrlen" pos="25:17" rst="8">
      </bits>
        <bits access="rw" name="rxthren" pos="16" rst="0">
      </bits>
        <bits access="rw" name="ahbthrratio" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="txthrlen" pos="10:2" rst="8">
      </bits>
        <bits access="rw" name="isothren" pos="1" rst="0">
      </bits>
        <bits access="rw" name="nonisothren" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="diepempmsk" protect="rw">
        <bits access="rw" name="ineptxfempmsk" pos="15:0" rst="0">
      </bits>
      </reg>
      <hole size="1600"/>
      <reg name="diepctl0" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="w" name="snak" pos="27" rst="0">
      </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
      </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="r" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="usbactep" pos="15" rst="1">
      </bits>
        <bits access="r" name="nextep" pos="14:11" rst="0">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="diepctl0_mps" pos="1:0" rst="0">
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint0" protect="rw">
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="txfifoundrn" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
      </bits>
        <bits access="rc" name="inepnakeff" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intknepmis" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intkntxfemp" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="timeout" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz0" protect="rw">
        <bits access="rw" name="pktcnt" pos="20:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="diepdma0" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="dtxfsts0" protect="rw">
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="297">
      </bits>
      </reg>
      <reg name="diepdmab0" protect="r">
        <bits access="r" name="dmabufferaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="diepctl1" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="setd1pid" pos="29" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="setd0pid" pos="28" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
      </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
      </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint1" protect="rw">
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="txfifoundrn" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
      </bits>
        <bits access="rc" name="inepnakeff" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intknepmis" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intkntxfemp" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="timeout" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz1" protect="rw">
        <bits access="rw" name="mc" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="diepdma1" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="dtxfsts1" protect="rw">
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="297">
      </bits>
      </reg>
      <reg name="diepdmab1" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="diepctl2" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="setd1pid" pos="29" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="setd0pid" pos="28" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
      </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
      </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint2" protect="rw">
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="txfifoundrn" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
      </bits>
        <bits access="rc" name="inepnakeff" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intknepmis" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intkntxfemp" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="timeout" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz2" protect="rw">
        <bits access="rw" name="mc" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="diepdma2" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="dtxfsts2" protect="rw">
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="297">
      </bits>
      </reg>
      <reg name="diepdmab2" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="diepctl3" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="setd1pid" pos="29" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="setd0pid" pos="28" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
      </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
      </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint3" protect="rw">
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="txfifoundrn" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
      </bits>
        <bits access="rc" name="inepnakeff" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intknepmis" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intkntxfemp" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="timeout" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz3" protect="rw">
        <bits access="rw" name="mc" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="diepdma3" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="dtxfsts3" protect="rw">
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="297">
      </bits>
      </reg>
      <reg name="diepdmab3" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="diepctl4" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="setd1pid" pos="29" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="setd0pid" pos="28" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
      </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
      </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint4" protect="rw">
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="txfifoundrn" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
      </bits>
        <bits access="rc" name="inepnakeff" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intknepmis" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intkntxfemp" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="timeout" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz4" protect="rw">
        <bits access="rw" name="mc" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="diepdma4" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="dtxfsts4" protect="rw">
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="297">
      </bits>
      </reg>
      <reg name="diepdmab4" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="diepctl5" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="setd1pid" pos="29" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="setd0pid" pos="28" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="txfnum" pos="25:22" rst="0">
      </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
      </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="diepint5" protect="rw">
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="txfifoundrn" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="r" name="txfemp" pos="7" rst="1">
      </bits>
        <bits access="rc" name="inepnakeff" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intknepmis" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="intkntxfemp" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="timeout" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dieptsiz5" protect="rw">
        <bits access="rw" name="mc" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="diepdma5" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="dtxfsts5" protect="rw">
        <bits access="r" name="ineptxfspcavail" pos="15:0" rst="297">
      </bits>
      </reg>
      <reg name="diepdmab5" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <hole size="2560"/>
      <reg name="doepctl0" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="r" name="epdis" pos="30" rst="0">
      </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
      </bits>
        <bits access="r" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="usbactep" pos="15" rst="1">
      </bits>
        <bits access="r" name="mps" pos="1:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint0" protect="rw">
        <bits access="rc" name="stuppktrcvd" pos="15" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outpkterr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="back2backsetup" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stsphsercvd" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outtknepdis" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="setup" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz0" protect="rw">
        <bits access="rw" name="supcnt" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="doepdma0" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab0" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="doepctl1" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="setd1pid" pos="29" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="setd0pid" pos="28" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
      </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint1" protect="rw">
        <bits access="rc" name="stuppktrcvd" pos="15" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outpkterr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="back2backsetup" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stsphsercvd" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outtknepdis" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="setup" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz1" protect="rw">
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="doepdma1" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab1" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="doepctl2" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="setd1pid" pos="29" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="setd0pid" pos="28" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
      </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint2" protect="rw">
        <bits access="rc" name="stuppktrcvd" pos="15" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outpkterr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="back2backsetup" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stsphsercvd" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outtknepdis" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="setup" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz2" protect="rw">
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="doepdma2" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab2" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="doepctl3" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="setd1pid" pos="29" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="setd0pid" pos="28" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
      </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint3" protect="rw">
        <bits access="rc" name="stuppktrcvd" pos="15" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outpkterr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="back2backsetup" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stsphsercvd" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outtknepdis" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="setup" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz3" protect="rw">
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="doepdma3" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab3" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="doepctl4" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="setd1pid" pos="29" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="setd0pid" pos="28" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
      </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint4" protect="rw">
        <bits access="rc" name="stuppktrcvd" pos="15" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outpkterr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="back2backsetup" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stsphsercvd" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outtknepdis" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="setup" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz4" protect="rw">
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="doepdma4" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab4" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <reg name="doepctl5" protect="rw">
        <bits access="rw" name="epena" pos="31" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="epdis" pos="30" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="setd1pid" pos="29" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="setd0pid" pos="28" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="snak" pos="27" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="cnak" pos="26" rst="0">
          <comment>bit type is changed from w1 to rw.</comment>
        </bits>
        <bits access="rw" name="stall" pos="21" rst="0">
          <comment>bit type is changed from othr to rw.</comment>
        </bits>
        <bits access="rw" name="snp" pos="20" rst="0">
      </bits>
        <bits access="rw" name="eptype" pos="19:18" rst="0">
      </bits>
        <bits access="r" name="naksts" pos="17" rst="0">
      </bits>
        <bits access="r" name="dpid" pos="16" rst="0">
      </bits>
        <bits access="rw" name="usbactep" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mps" pos="10:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepint5" protect="rw">
        <bits access="rc" name="stuppktrcvd" pos="15" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nyetintrpt" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="nakintrpt" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bbleerr" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="pktdrpsts" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="bnaintr" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outpkterr" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="back2backsetup" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="stsphsercvd" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="outtknepdis" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="setup" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="ahberr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="epdisbld" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
        <bits access="rc" name="xfercompl" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="doeptsiz5" protect="rw">
        <bits access="r" name="rxdpid" pos="30:29" rst="0">
      </bits>
        <bits access="rw" name="pktcnt" pos="28:19" rst="0">
      </bits>
        <bits access="rw" name="xfersize" pos="18:0" rst="0">
      </bits>
      </reg>
      <reg name="doepdma5" protect="rw">
        <bits access="rw" name="dmaaddr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="doepdmab5" protect="rw">
        <bits access="rw" name="dmabufferaddr" pos="31:0" rst="0">
          <comment>bit type is changed from ru to rw.</comment>
        </bits>
      </reg>
      <hole size="4608"/>
      <reg name="pcgcctl" protect="rw">
        <bits access="r" name="l1suspended" pos="7" rst="0">
      </bits>
        <bits access="r" name="physleep" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rstpdwnmodule" pos="3" rst="0">
      </bits>
        <bits access="rw" name="stoppclk" pos="0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="sdmmc.xml">
    <module category="Periph" name="SDMMC">
      <reg name="apbi_ctrl_sdmmc" protect="rw">
        <bits access="rw" name="l_endian" pos="2:0" rst="000">
          <comment>
            Controls the big endian or little endian of the FIFO data.
            <br/>
            Take 32 bit data 0X0A0B0C0D for Example,bit[31:24]=Byte3,bit[23:16]=Byte2,bit[15:8]=Byte1,bit[7:0]=Byte0.
            <br/>
            &quot;000&quot;: the order is not changed.
            <br/>
            Byte3=&quot;0A&quot;,Byte2=&quot;0B&quot;,Byte1=&quot;0C&quot;,Byte0=&quot;0D&quot;.
            <br/>
            &quot;001&quot;: reversed on byte.
            <br/>
            Byte3=&quot;0D&quot;,Byte2=&quot;0C,Byte1=&quot;0B&quot;,Byte0=&quot;0A&quot;.
            <br/>
            &quot;010&quot;: reversed on half word.
            <br/>
            Byte3=&quot;0C&quot;,Byte2=&quot;0D,Byte1=&quot;0A&quot;,Byte0=&quot;0B&quot;.
            <br/>
            &quot;010&quot;: reversed on bit.
            <br/>
            Byte3=&quot;B0&quot;,Byte2=&quot;30,Byte1=&quot;D0&quot;,Byte0=&quot;50&quot;.
            <br/>
            &quot;100&quot;: reversed on bit.
            <br/>
            Byte3=&quot;0A&quot;,Byte2=&quot;0X,Byte1=&quot;0D&quot;,Byte0=&quot;0C&quot;.
          </comment>
        </bits>
        <bits access="rw" name="soft_rst_l" pos="3" rst="1">
          <comment>
            For the software to clear FIFO in case there is an error in communication with SD controller and some data are left behind.
            <br/>
            Active Low.
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="apbi_fifo_txrx" protect="--">
        <bits access="w" name="data_in" pos="31:0" rst="0">
          <comment>Write to the transmit FIFO</comment>
        </bits>
        <bits access="r" name="data_out" pos="31:0" rst="0">
          <comment>Read in the receive FIFO</comment>
        </bits>
      </reg>
      <hole size="16288"/>
      <reg name="sdmmc_config" protect="rw">
        <bits access="rw" name="sdmmc_sendcmd" pos="0" rst="0">
          <comment>
            SD/MMC operation begin register, active high.
            <br/>
		When '1', the controller finishes the last command and goes into suspend status. At suspend status, the controller will not execute the next command until the bit is set '0'.
          </comment>
        </bits>
        <bits access="rw" name="sdmmc_suspend" pos="1" rst="1">
          <comment>SD/MMC operation suspend register, active high.</comment>
        </bits>
        <bits access="rw" name="rsp_en" pos="4" rst="0">
          <comment>'1'indicates having a response,'0'indicates no response.</comment>
        </bits>
        <bits access="rw" name="rsp_sel" pos="6:5" rst="0">
          <options>
            <default/>
            <option name="R2" value="0b10"/>
            <option name="R3" value="0b01"/>
            <option name="OTHER" value="0b00"/>
          </options>
          <comment>Response select register,&quot;10&quot; means R2 response, &quot;01&quot; means R3 response, &quot;00&quot; means others response, &quot;11&quot; is reserved.</comment>
        </bits>
        <bits access="rw" name="rd_wt_en" pos="8" rst="0">
          <comment>'1' indicates data operation, which includes read and write.</comment>
        </bits>
        <bits access="rw" name="rd_wt_sel" pos="9" rst="0">
          <options>
            <default/>
            <option name="READ" value="0"/>
            <option name="WRITE" value="1"/>
          </options>
          <comment>'1' means write operation,'0' means read operation.</comment>
        </bits>
        <bits access="rw" name="s_m_sel" pos="10" rst="0">
          <options>
            <default/>
            <option name="SIMPLE" value="0"/>
            <option name="MULTIPLE" value="1"/>
          </options>
          <comment>'1'means multiple block data operation.</comment>
        </bits>
        <bits access="rw" name="auto_flag_en" pos="16" rst="1">
	</bits>
      </reg>
      <reg name="sdmmc_status" protect="r">
        <bits access="r" name="not_sdmmc_over" pos="0" rst="0">
          <comment>'1' means the SD/MMC operation is not over.</comment>
        </bits>
        <bits access="r" name="busy" pos="1" rst="0">
          <comment>'1' means SD/MMC is busy.</comment>
        </bits>
        <bits access="r" name="dl_busy" pos="2" rst="0">
          <comment>'1' means the data line is busy.</comment>
        </bits>
        <bits access="r" name="suspend" pos="3" rst="1">
          <comment>'1' means the controller will not perform the new command when SDMMC_SENDCMD= '1'.</comment>
        </bits>
        <bits access="r" name="rsp_error" pos="8" rst="0">
          <comment>Response CRC checks error register '1' means response CRC check error.</comment>
        </bits>
        <bits access="r" name="no_rsp_error" pos="9" rst="0">
          <comment>'1' means the card has no response to command.</comment>
        </bits>
        <bits access="r" name="crc_status" pos="14:12" rst="0">
          <comment>
            CRC check for SD/MMC write operation
            <br/>
		&quot;101&quot; transmission error
            <br/>
		&quot;010&quot; transmission right
            <br/>
		&quot;111&quot; flash programming error
          </comment>
        </bits>
        <bits access="r" name="data_error" pos="23:16" rst="0">
          <comment>8 bits data CRC check, &quot;00000000&quot; means no data error, &quot;00000001&quot; means DATA0 CRC check error, &quot;10000000&quot; means DATA7 CRC check error, each bit match one data line.</comment>
        </bits>
        <bits access="r" name="dat3_val" pos="24" rst="-">
          <comment>SDMMC DATA 3 value.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_cmd_index" protect="rw">
        <bits access="rw" name="command" pos="5:0" rst="0">
          <comment>SD/MMC command register.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_cmd_arg" protect="rw">
        <bits access="rw" name="argument" pos="31:0" rst="0">
          <comment>SD/MMC command argument register, write data to the SD/MMC card.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_resp_index" protect="r">
        <bits access="r" name="response" pos="5:0" rst="0">
          <comment>SD/MMC response index register.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_resp_arg3" protect="r">
        <bits access="r" name="argument3" pos="31:0" rst="0">
          <comment>Response argument of R1, R3 and R6, or 127 to 96 bit response argument of R2.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_resp_arg2" protect="r">
        <bits access="r" name="argument2" pos="31:0" rst="0">
          <comment>95 to 64 bit response argument of R2.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_resp_arg1" protect="r">
        <bits access="r" name="argument1" pos="31:0" rst="0">
          <comment>63 to 32 bit response argument of R2.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_resp_arg0" protect="r">
        <bits access="r" name="argument0" pos="31:0" rst="0">
          <comment>31 to 0 bit response argument of R2.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_data_width" protect="rw">
        <bits access="rw" name="sdmmc_data_width" pos="3:0" rst="0">
          <comment>
            SD/MMC data width:
            <br/>
		0x1: 1 data line
            <br/>
		0x2: 2 reserved
            <br/>
		0x4: 4 data lines
            <br/>
		0x8: 8 data lines
          </comment>
        </bits>
      </reg>
      <reg name="sdmmc_block_size" protect="rw">
        <bits access="rw" name="sdmmc_block_size" pos="3:0" rst="0">
          <comment>
            SD/MMC size of one block:
            <br/>
		0-1:reserved
            <br/>
		2: 1 word
            <br/>
		3: 2 words
            <br/>
		4: 4 words
            <br/>
		5: 8 words
            <br/>
		6: 16 words
            <br/>
            <br/>
		11: 512 words
            <br/>
		12-15 reserved
          </comment>
        </bits>
      </reg>
      <reg name="sdmmc_block_cnt" protect="rw">
        <bits access="rw" name="sdmmc_block_cnt" pos="15:0" rst="0">
          <comment>Block number that wants to transfer.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_int_status" protect="r">
        <bits access="r" name="no_rsp_int" pos="0" rst="0">
          <comment>'1' means no response.</comment>
        </bits>
        <bits access="r" name="rsp_err_int" pos="1" rst="0">
          <comment>'1' means CRC error of response.</comment>
        </bits>
        <bits access="r" name="rd_err_int" pos="2" rst="0">
          <comment>'1' means CRC error of reading data.</comment>
        </bits>
        <bits access="r" name="wr_err_int" pos="3" rst="0">
          <comment>'1' means CRC error of writing data.</comment>
        </bits>
        <bits access="r" name="dat_over_int" pos="4" rst="0">
          <comment>'1' means data transmission is over.</comment>
        </bits>
        <bits access="r" name="txdma_done_int" pos="5" rst="0">
          <comment>'1' means tx dma done.</comment>
        </bits>
        <bits access="r" name="rxdma_done_int" pos="6" rst="0">
          <comment>'1' means rx dma done.</comment>
        </bits>
        <bits access="r" name="no_rsp_sc" pos="8" rst="0">
          <comment>'1' means no response is the source of interrupt.</comment>
        </bits>
        <bits access="r" name="rsp_err_sc" pos="9" rst="0">
          <comment>'1' means CRC error of response is the source of interrupt.</comment>
        </bits>
        <bits access="r" name="rd_err_sc" pos="10" rst="0">
          <comment>'1' means CRC error of reading data is the source of interrupt.</comment>
        </bits>
        <bits access="r" name="wr_err_sc" pos="11" rst="0">
          <comment>'1' means CRC error of writing data is the source of interrupt.</comment>
        </bits>
        <bits access="r" name="dat_over_sc" pos="12" rst="0">
          <comment>'1' means the end of data transmission is the source of interrupt.</comment>
        </bits>
        <bits access="r" name="txdma_done_sc" pos="13" rst="0">
          <comment>'1' means tx dma done is the source of interrupt.</comment>
        </bits>
        <bits access="r" name="rxdma_done_sc" pos="14" rst="0">
          <comment>'1' means rx dma done is the source of interrupt.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_int_mask" protect="rw">
        <bits access="rw" name="no_rsp_mk" pos="0" rst="0">
          <comment>When no response, '1' means INT is disable.</comment>
        </bits>
        <bits access="rw" name="rsp_err_mk" pos="1" rst="0">
          <comment>When CRC error of response, '1' means INT is disable.</comment>
        </bits>
        <bits access="rw" name="rd_err_mk" pos="2" rst="0">
          <comment>When CRC error of reading data, '1' means INT is disable.</comment>
        </bits>
        <bits access="rw" name="wr_err_mk" pos="3" rst="0">
          <comment>When CRC error of writing data, '1' means INT is disable.</comment>
        </bits>
        <bits access="rw" name="dat_over_mk" pos="4" rst="0">
          <comment>When data transmission is over, '1' means INT is disable.</comment>
        </bits>
        <bits access="rw" name="txdma_done_mk" pos="5" rst="0">
          <comment>when tx dma done, '1' means INT is disabled.</comment>
        </bits>
        <bits access="rw" name="rxdma_done_mk" pos="6" rst="0">
          <comment>'1' means rx dma done, '1' means INT is disabled.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_int_clear" protect="w">
        <bits access="w" name="no_rsp_cl" pos="0" rst="0">
          <comment>Write a '1' to this bit to clear the source of interrupt in NO_RSP_SC.</comment>
        </bits>
        <bits access="w" name="rsp_err_cl" pos="1" rst="0">
          <comment>Write a '1' to this bit to clear the source of interrupt in RSP_ERR_SC.</comment>
        </bits>
        <bits access="w" name="rd_err_cl" pos="2" rst="0">
          <comment>Write a '1' to this bit to clear the source of interrupt in RD_ERR_SC.</comment>
        </bits>
        <bits access="w" name="wr_err_cl" pos="3" rst="0">
          <comment>Write a '1' to this bit to clear the source of interrupt in WR_ERR_SC.</comment>
        </bits>
        <bits access="w" name="dat_over_cl" pos="4" rst="0">
          <comment>Write a '1' to this bit to clear the source of interrupt in DAT_OVER_SC.</comment>
        </bits>
        <bits access="w" name="txdma_done_cl" pos="5" rst="0">
          <comment>Write a '1' to this bit to clear the source of interrupt in TXDMA_DONE_SC.</comment>
        </bits>
        <bits access="w" name="rxdma_done_cl" pos="6" rst="0">
          <comment>Write a '1' to this bit to clear the source of interrupt in RXDMA_DONE_SC.</comment>
        </bits>
      </reg>
      <reg name="sdmmc_trans_speed" protect="rw">
        <bits access="rw" name="sdmmc_trans_speed" pos="7:0" rst="0">
          <comment>Mclk = Pclk/(2*(SDMMC_TRANS_SPEED +1)).</comment>
        </bits>
      </reg>
      <reg name="sdmmc_mclk_adjust" protect="rw">
        <bits access="rw" name="sdmmc_mclk_adjust" pos="3:0" rst="0">
          <comment>This register may delay the mclk output.
			 When MCLK_ADJUSTER = n, Mclk is outputted with  n Pclk.</comment>
        </bits>
        <bits access="rw" name="clk_inv" pos="4" rst="0">
          <comment>Invert Mclk.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="camera.xml">
    <var name="FIFORAM_SIZE" value="80"/>
    <module category="Periph" name="CAMERA">
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="enable" pos="0" rst="0">
          <options>
            <default/>
            <option name="ENABLE" value="1"/>
            <option name="DISABLE" value="0"/>
          </options>
          <comment>Enable camera controller,high active.</comment>
        </bits>
        <bits access="rw" name="dctenable" pos="1" rst="0">
          <comment>Enable camera controller,high active.</comment>
        </bits>
        <bits access="rw" name="buf_enable" pos="2" rst="0">
    </bits>
        <bits access="rw" name="rgb_rfirst" pos="3" rst="0">
    </bits>
        <bits access="rw" name="dataformat" pos="5:4" rst="0">
          <options>
            <default/>
            <option name="RGB565" value="0"/>
            <option name="YUV422" value="1"/>
            <option name="JPEG" value="2"/>
            <option name="RESERVE" value="3"/>
          </options>
          <comment>
            &quot;0&quot; = RGB565.
            <br/>
             &quot;1&quot; = YUV422.
            <br/>
             &quot;2&quot; = Compressed Data.
            <br/>
             &quot;3&quot; = Reserved.
          </comment>
        </bits>
        <bits access="rw" name="cfg_cam_c2cse" pos="7:6" rst="0">
    </bits>
        <bits access="rw" name="reset_pol" pos="8" rst="1">
          <options>
            <default/>
            <option name="INVERT" value="1"/>
            <option name="NORMAL" value="0"/>
          </options>
          <comment>
            '0' = keep output camera reset polarity.
            <br/>
             '1' = invert output camera reset polarity.
          </comment>
        </bits>
        <bits access="rw" name="pwdn_pol" pos="9" rst="0">
          <options>
            <default/>
            <option name="INVERT" value="1"/>
            <option name="NORMAL" value="0"/>
          </options>
          <comment>
            '0' = keep output camera power down polarity.
            <br/>
             '1' = invert output camera power down polarity.
          </comment>
        </bits>
        <bits access="rw" name="vsync_pol" pos="10" rst="0">
          <options>
            <default/>
            <option name="INVERT" value="1"/>
            <option name="NORMAL" value="0"/>
          </options>
          <comment>
            '0' = keep input VSYNC polarity.
            <br/>
             '1' = invert input VSYNC polarity.
          </comment>
        </bits>
        <bits access="rw" name="href_pol" pos="11" rst="0">
          <options>
            <default/>
            <option name="INVERT" value="1"/>
            <option name="NORMAL" value="0"/>
          </options>
          <comment>
            '0' = keep input HREF polarity so data is sampled when HREF high.
            <br/>
             '1' = invert input HREF polarity so data is sampled when HREF low.
          </comment>
        </bits>
        <bits access="rw" name="pixclk_pol" pos="12" rst="0">
          <options>
            <default/>
            <option name="INVERT" value="1"/>
            <option name="NORMAL" value="0"/>
          </options>
          <comment>
            '0' = keep pix clk polarity.
            <br/>
             '1' = invert pix clk polarity.
          </comment>
        </bits>
        <bits access="rw" name="vsync_drop" pos="14" rst="1">
          <options>
            <default/>
            <option name="DROP" value="1"/>
            <option name="NORMAL" value="0"/>
          </options>
          <comment>
            '0' = VSYNC irq always exists when Frame decimation is enabled.
            <br/>
             '1' = VSYNC irq will drop when Frame data are dropped in decipation.
          </comment>
        </bits>
        <bits access="rw" name="decimfrm" pos="17:16" rst="0">
          <options>
            <default/>
            <option name="ORIGINAL" value="0"/>
            <option name="DIV_2" value="1"/>
            <option name="DIV_3" value="2"/>
            <option name="DIV_4" value="3"/>
          </options>
          <comment>
            &quot;0&quot;= All frame data will be sent.
            <br/>
             &quot;1&quot;= only one frame out of two (1/2) will be sent.
            <br/>
             &quot;2&quot;= only one frame out of three (1/3) will be sent.
            <br/>
             &quot;3&quot;= only one frame out of four (1/4) will be sent.
          </comment>
        </bits>
        <bits access="rw" name="decimcol" pos="19:18" rst="0">
          <options>
            <default/>
            <option name="ORIGINAL" value="0"/>
            <option name="DIV_2" value="1"/>
            <option name="DIV_3" value="2"/>
            <option name="DIV_4" value="3"/>
          </options>
          <comment>
            &quot;0&quot;= Pixel Decimation Disabled.
            <br/>
             &quot;1&quot;= Pixel Decimation 1/2.
            <br/>
             &quot;2&quot;= Pixel Decimation 1/3.
            <br/>
             &quot;3&quot;= Pixel Decimation 1/4.
          </comment>
        </bits>
        <bits access="rw" name="decimrow" pos="21:20" rst="0">
          <options>
            <default/>
            <option name="ORIGINAL" value="0"/>
            <option name="DIV_2" value="1"/>
            <option name="DIV_3" value="2"/>
            <option name="DIV_4" value="3"/>
          </options>
          <comment>
            &quot;0&quot;= line Decimation Disabled.
            <br/>
             &quot;1&quot;= line Decimation 1/2.
            <br/>
             &quot;2&quot;= line Decimation 1/3.
            <br/>
             &quot;3&quot;= line Decimation 1/4.
          </comment>
        </bits>
        <bits access="rw" name="reorder" pos="26:24" rst="0">
          <comment>
            Controls the Re-ordering of the FIFO data.
            <br/>
             In following table, for input data, right comes before left. So YUYV means V comes first.
            <br/>
             for output data, right data is the LSB. So YUYV means V is stored in low 8-bit (byte0) of 32-bit word.
            <br/>
            <br/>
             If Bit 26 is '1', byte2 and byte0 is Y.
            <br/>
             If Bit 25 is '1', both byte2/byte3 and byte1/byte0 interchange.
            <br/>
             If Bit 24 is '1', byte U and V should interchange. (UV bytes can be decided using bit 26).
            <br/>
            <br/>
             input YUYV, output YUYV: &quot;000&quot;
            <br/>
             input YVYU, output YUYV: &quot;001&quot;
            <br/>
             input UYVY, output YUYV: &quot;110&quot;
            <br/>
             input VYUY, output YUYV: &quot;111&quot;
            <br/>
            <br/>
             input YUYV, output UYVY: &quot;010&quot;
            <br/>
             input YVYU, output UYVY: &quot;011&quot;
            <br/>
             input UYVY, output UYVY: &quot;100&quot;
            <br/>
             input VYUY, output UYVY: &quot;101&quot;
            <br/>
            <br/>
             input YUYV, output YVYU: &quot;001&quot;
            <br/>
             input YVYU, output YVYU: &quot;000&quot;
            <br/>
             input UYVY, output YVYU: &quot;111&quot;
            <br/>
             input VYUY, output YVYU: &quot;110&quot;
            <br/>
            <br/>
             input YUYV, output VYUY: &quot;011&quot;
            <br/>
             input YVYU, output VYUY: &quot;010&quot;
            <br/>
             input UYVY, output VYUY: &quot;101&quot;
            <br/>
             input VYUY, output VYUY: &quot;100&quot;
            <br/>
            <br/>
             Decimation will reorder data flow also. Input UYVY becomes YUVY after decimation.
                      This reorder is corrected using Bit 26 infomation.
          </comment>
        </bits>
        <bits access="rw" name="cropen" pos="28" rst="0">
          <options>
            <default/>
            <option name="ENABLE" value="1"/>
            <option name="DISABLE" value="0"/>
          </options>
          <comment>
            &quot;0&quot;= Cropping Disabled.
            <br/>
             &quot;1&quot;= Cropping Enabled.
            <br/>
             Note: this bit should set to '0' when bit field &quot;DataFormat&quot; is &quot;10&quot; (compressed data)
          </comment>
        </bits>
        <bits access="rw" name="bist mode" pos="30" rst="0">
          <options>
            <default/>
            <option name="BIST" value="1"/>
            <option name="NORMAL" value="0"/>
          </options>
          <comment>In Bist Mode, FIFO RAM are read and write by its address, FIFO mode is disabled.</comment>
        </bits>
        <bits access="rw" name="test" pos="31" rst="0">
          <options>
            <default/>
            <option name="TEST" value="1"/>
            <option name="NORMAL" value="0"/>
          </options>
          <comment>Debug only. A RGB565 test card is sent to system bus instead of real data from sensor.</comment>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="ovfl" pos="0" rst="0">
          <comment>
            '1' = FIFO over-write IRQ status.
            <br/>
             Write to corresponding bit in IRQ CLEAR register will clear this bit.
          </comment>
        </bits>
        <bits access="r" name="vsync_r" pos="1" rst="0">
          <comment>
            '1' = VSYNC rising edge IRQ status
            <br/>
             Write to corresponding bit in IRQ CLEAR register will clear this bit.
          </comment>
        </bits>
        <bits access="r" name="vsync_f" pos="2" rst="0">
          <comment>
            '1' = VSYNC falling edge IRQ status
            <br/>
             Write to corresponding bit in IRQ CLEAR register will clear this bit.
          </comment>
        </bits>
        <bits access="r" name="dma done" pos="3" rst="0">
          <comment>
            '1' = DMA Done IRQ status
            <br/>
             Write to corresponding bit in IRQ CLEAR register will clear this bit.
          </comment>
        </bits>
        <bits access="r" name="fifo empty" pos="4" rst="1">
          <comment>'1' = FIFO Empty status, not clear-able.</comment>
        </bits>
        <bits access="r" name="spi ovfl" pos="5" rst="0">
        </bits>
      </reg>
      <reg name="data" protect="r">
        <bits access="r" name="rx_data" pos="31:0" rst="0">
          <comment>Read in the receive FIFO</comment>
        </bits>
      </reg>
      <reg name="irq mask" protect="rw">
        <bits access="rw" name="ovfl" pos="0" rst="0">
          <comment>'1' = FIFO over-write enable</comment>
        </bits>
        <bits access="rw" name="vsync_r" pos="1" rst="0">
          <comment>'1' = VSYNC rising edge enable</comment>
        </bits>
        <bits access="rw" name="vsync_f" pos="2" rst="0">
          <comment>'1' = VSYNC falling edge enable</comment>
        </bits>
        <bits access="rw" name="dma done" pos="3" rst="0">
          <comment>'1' = DMA Done enable</comment>
        </bits>
      </reg>
      <reg name="irq clear" protect="w">
        <bits access="w" name="ovfl" pos="0" rst="0">
          <comment>Write '1' to clear FIFO over-write interrupt</comment>
        </bits>
        <bits access="w" name="vsync_r" pos="1" rst="0">
          <comment>Write '1' to clear VSYNC rising edge interrupt</comment>
        </bits>
        <bits access="w" name="vsync_f" pos="2" rst="0">
          <comment>Write '1' to clear VSYNC falling edge interrupt</comment>
        </bits>
        <bits access="w" name="dma done" pos="3" rst="0">
          <comment>Write '1' to clear DMA Done interrupt</comment>
        </bits>
      </reg>
      <reg name="irq cause" protect="r">
        <bits access="r" name="ovfl" pos="0" rst="0">
          <comment>'1' = FIFO over-write cause</comment>
        </bits>
        <bits access="r" name="vsync_r" pos="1" rst="0">
          <comment>'1' = VSYNC rising edge cause</comment>
        </bits>
        <bits access="r" name="vsync_f" pos="2" rst="0">
          <comment>'1' = VSYNC falling edge cause</comment>
        </bits>
        <bits access="r" name="dma done" pos="3" rst="0">
          <comment>'1' = DMA Done cause</comment>
        </bits>
      </reg>
      <reg name="cmd set" protect="rw">
        <bits access="rs" name="pwdn" pos="0" rst="1">
          <comment>Power down pin of CMOS sensor .</comment>
        </bits>
        <bits access="rs" name="reset" pos="4" rst="1">
          <comment>
            Reset pin of CMOS sensor.
            <br/>
            Active Low.
          </comment>
        </bits>
        <bits access="s" name="fifo reset" pos="8" rst="0">
          <comment>For the software to clear FIFO. This bit is auto-reset to 0.</comment>
        </bits>
      </reg>
      <reg name="cmd clr" protect="rw">
        <bits access="rc" name="pwdn" pos="0" rst="1">
          <comment>Power down pin of CMOS sensor .</comment>
        </bits>
        <bits access="rc" name="reset" pos="4" rst="1">
          <comment>Reset pin of CMOS sensor.</comment>
        </bits>
      </reg>
      <reg name="dstwincol" protect="rw">
        <bits access="rw" name="dstwincolstart" pos="11:0" rst="0">
          <comment>start pixel of cropped window.</comment>
        </bits>
        <bits access="rw" name="dstwincolend" pos="27:16" rst="0">
          <comment>end pixel of cropped window.</comment>
        </bits>
      </reg>
      <reg name="dstwinrow" protect="rw">
        <bits access="rw" name="dstwinrowstart" pos="11:0" rst="0">
          <comment>start line of cropped window.</comment>
        </bits>
        <bits access="rw" name="dstwinrowend" pos="27:16" rst="0">
          <comment>end line of cropped window.</comment>
        </bits>
      </reg>
      <reg name="scl config" protect="rw">
        <bits access="rw" name="scale en" pos="0" rst="0">
        </bits>
        <bits access="rw" name="data_out_swap" pos="4" rst="0">
          <comment>swap camera data output [15:0],[31:16].</comment>
        </bits>
        <bits access="rw" name="scale col" pos="9:8" rst="0">
        </bits>
        <bits access="rw" name="scale row" pos="17:16" rst="0">
        </bits>
      </reg>
      <reg name="spi camera reg0" protect="rw">
        <bits access="rw" name="camera_spi_slave_en" pos="0" rst="0">
          <comment>spi slave enable.</comment>
        </bits>
        <bits access="rw" name="camera_spi_master_en" pos="1" rst="0">
          <comment>spi master enable.</comment>
        </bits>
        <bits access="rw" name="yuv_out_format" pos="4:2" rst="0">
          <comment>yuv out format.
			  3'b000: data_serial_mux = {Y0,U0,Y1,V0};
        3'b001: data_serial_mux = {Y0,V0,Y1,U0};
        3'b010: data_serial_mux = {U0,Y0,V0,Y1};
        3'b011: data_serial_mux = {U0,Y1,V0,Y0};
        3'b100: data_serial_mux = {V0,Y1,U0,Y0};
        3'b101: data_serial_mux = {V0,Y0,U0,Y1};
        3'b110: data_serial_mux = {Y1,V0,Y0,U0};
        3'b111: data_serial_mux = {Y1,U0,Y0,V0};</comment>
        </bits>
        <bits access="rw" name="overflow_rstn_only_vsync_low" pos="5" rst="0">
          <comment>overflow rstn only vsync low.</comment>
        </bits>
        <bits access="rw" name="overflow_observe_only_vsync_low" pos="6" rst="0">
          <comment>overflow_observe_only_vsync_low.</comment>
        </bits>
        <bits access="rw" name="overflow_rstn_en" pos="7" rst="0">
          <comment>overflow_rstn enable</comment>
        </bits>
        <bits access="rw" name="big_end_dis" pos="8" rst="0">
          <comment>big_end_dis</comment>
        </bits>
        <bits access="rw" name="overflow_inv" pos="9" rst="0">
          <comment>overflow inv control</comment>
        </bits>
        <bits access="rw" name="href_inv" pos="10" rst="0">
          <comment>href inv control</comment>
        </bits>
        <bits access="rw" name="vsync_inv" pos="11" rst="0">
          <comment>vsync inv control</comment>
        </bits>
        <bits access="rw" name="block_num_per_line" pos="21:12" rst="0">
          <comment>block_num_per_line[9:0] pixels num of a line</comment>
        </bits>
        <bits access="rw" name="line_num_per_frame" pos="31:22" rst="0">
          <comment>line_num_per_frame[9:0] lines num of a frame</comment>
        </bits>
      </reg>
      <reg name="spi camera reg1" protect="rw">
        <bits access="rw" name="camera_clk_div_num" pos="15:0" rst="0">
          <comment>camera_clk_div_num</comment>
        </bits>
        <bits access="rw" name="cts_spi_master_reg" pos="16" rst="0">
          <comment>cts_spi_master_reg</comment>
        </bits>
        <bits access="rw" name="ssn_cm_inv" pos="17" rst="0">
          <comment>ssn_cm inv control</comment>
        </bits>
        <bits access="rw" name="sck_cm_inv" pos="18" rst="0">
          <comment>sck_cm inv control</comment>
        </bits>
        <bits access="rw" name="ssn_spi_oenb_dr" pos="19" rst="0">
          <comment>ssn_spi_oen select, 1:from reg  0: from logic</comment>
        </bits>
        <bits access="rw" name="ssn_spi_oenb_reg" pos="20" rst="0">
          <comment>ssn_spi_oenb reg</comment>
        </bits>
        <bits access="rw" name="sck_spi_oenb_dr" pos="21" rst="0">
          <comment>sck_spi_oenb select, 1:from reg 0:from logic</comment>
        </bits>
        <bits access="rw" name="sck_spi_oenb_reg" pos="22" rst="0">
          <comment>sck_spi_oenb reg</comment>
        </bits>
        <bits access="rw" name="sdo_spi_swap" pos="29" rst="0">
          <comment>sdo_spi_swap reg,swap camera_spi_0 and camera_spi_1</comment>
        </bits>
        <bits access="rw" name="clk_inv" pos="30" rst="0">
          <comment>clk inv control</comment>
        </bits>
        <bits access="rw" name="sck_ddr_en" pos="31" rst="0">
          <comment>sck double edge enable</comment>
        </bits>
      </reg>
      <reg name="spi camera reg2" protect="rw">
        <bits access="rw" name="ssn_wait_length" pos="7:0" rst="0">
          <comment>ssn_wait_length[7:0]</comment>
        </bits>
        <bits access="rw" name="init_wait_length" pos="15:8" rst="0">
          <comment>init_wait_length[7:0]</comment>
        </bits>
        <bits access="rw" name="word_num_per_block" pos="23:16" rst="0">
          <comment>word_num_per_block[7:0]</comment>
        </bits>
        <bits access="rw" name="ssn_cs_delay" pos="25:24" rst="0">
          <comment>ssn_cs_delay[1:0]</comment>
        </bits>
        <bits access="rw" name="data_receive_choose_bit" pos="27:26" rst="0">
          <comment>data_receive_choose_bit[1:0]</comment>
        </bits>
        <bits access="rw" name="ready_cs_inv" pos="28" rst="0">
          <comment>ready_cs_inv</comment>
        </bits>
        <bits access="rw" name="ssn_cs_inv" pos="29" rst="0">
          <comment>ssn_cs_inv</comment>
        </bits>
        <bits access="rw" name="eco_bypass_isp" pos="31" rst="0">
          <comment>eco_bypass_isp</comment>
        </bits>
      </reg>
line_wait_length[15:0]
      <reg name="spi camera reg3" protect="rw">
        <bits access="rw" name="line_wait_length" pos="15:0" rst="0">
          <comment>line_wait_length</comment>
        </bits>
        <bits access="rw" name="block_wait_length" pos="23:16" rst="0">
          <comment>block_wait_length[7:0]</comment>
        </bits>
        <bits access="rw" name="ssn_high_length" pos="31:24" rst="0">
          <comment>ssn_high_length[7:0]</comment>
        </bits>
      </reg>
      <reg name="spi camera reg4" protect="rw">
        <bits access="rw" name="camera_spi_master_en_2" pos="0" rst="0">
          <comment>camera_spi_master no ssn mode enable</comment>
        </bits>
        <bits access="rw" name="sdo_line_choose_bit" pos="2:1" rst="0">
          <comment>sdo_line_choose_bit[1:0] 0:1 line 1: 2lines 2:4lines</comment>
        </bits>
        <bits access="rw" name="data_size_choose_bit" pos="3" rst="0">
          <comment>data_size_choose_bit  1: from reg  0:from logic</comment>
        </bits>
        <bits access="rw" name="image_height_choose_bit" pos="4" rst="0">
          <comment>image_height_choose_bit  1: from reg  0:from logic</comment>
        </bits>
        <bits access="rw" name="image_width_choose_bit" pos="5" rst="0">
          <comment>image_width_choose_bit 1: from reg  0:from logic</comment>
        </bits>
        <bits access="rw" name="block_num_per_packet" pos="15:6" rst="0">
          <comment>block_num_per_packet[9:0]</comment>
        </bits>
        <bits access="rw" name="spi_data0_phase_sel" pos="17:16" rst="0">
          <comment>0: spi data0 delay 0
			          1: spi data0 delay 2 cycles spi_cam_clk
			          2: spi data0 delay 3 cycles spi_cam_clk
			          3: spi data0 delay 4 cycles spi_cam_clk</comment>
        </bits>
        <bits access="rw" name="spi_data1_phase_sel" pos="19:18" rst="0">
          <comment>0: spi data1 delay 0
			          1: spi data1 delay 2 cycles spi_cam_clk
			          2: spi data1 delay 3 cycles spi_cam_clk
			          3: spi data1 delay 4 cycles spi_cam_clk</comment>
        </bits>
      </reg>
      <reg name="spi camera reg5" protect="rw">
        <bits access="rw" name="sync_code" pos="23:0" rst="0">
          <comment>sync code</comment>
        </bits>
      </reg>
      <reg name="spi camera reg6" protect="rw">
        <bits access="rw" name="packet_id_data_start" pos="7:0" rst="0">
          <comment>packet_id_data_start</comment>
        </bits>
        <bits access="rw" name="packet_id_line_start" pos="15:8" rst="0">
          <comment>packet_id_line_start</comment>
        </bits>
        <bits access="rw" name="packet_id_frame_end" pos="23:16" rst="0">
          <comment>packet_id_frame_end</comment>
        </bits>
        <bits access="rw" name="packet_id_frame_start" pos="31:24" rst="0">
          <comment>packet_id_frame_start</comment>
        </bits>
      </reg>
      <reg name="spi camera obs0" protect="rw">
        <bits access="ro" name="line_id[15:0]" pos="15:0" rst="0">
          <comment>line_id[15:0]</comment>
        </bits>
        <bits access="ro" name="data_id[7:0]" pos="23:16" rst="0">
          <comment>data_id[7:0]</comment>
        </bits>
        <bits access="ro" name="observe_data_size_wrong" pos="24" rst="0">
          <comment>observe_data_size_wrong</comment>
        </bits>
        <bits access="ro" name="observe_image_height_wrong" pos="25" rst="0">
          <comment>observe_image_height_wrong</comment>
        </bits>
        <bits access="ro" name="observe_image_width_wrong" pos="26" rst="0">
          <comment>observe_image_width_wrong</comment>
        </bits>
        <bits access="ro" name="observe_line_num_wrong" pos="27" rst="0">
          <comment>observe_line_num_wrong</comment>
        </bits>
        <bits access="ro" name="observe_data_id_wrong" pos="28" rst="0">
          <comment>observe_data_id_wrong</comment>
        </bits>
      </reg>
      <reg name="spi camera obs1" protect="rw">
        <bits access="ro" name="image_height" pos="15:0" rst="0">
          <comment>image_height[15:0]</comment>
        </bits>
        <bits access="ro" name="image_width" pos="31:16" rst="0">
          <comment>image_width[15:0]</comment>
        </bits>
      </reg>
      <reg name="csi config reg0" protect="rw">
        <bits access="rw" name="num_d_term_en" pos="7:0" rst="8">
          <comment>num_d_term_en[7:0]  term time reg</comment>
        </bits>
        <bits access="rw" name="cur_frame_line_num" pos="20:8" rst="240">
          <comment>cur_frame_line_num[12:0]</comment>
        </bits>
        <bits access="rw" name="data_lp_in_choose_bit" pos="22:21" rst="0">
          <comment>data_lp_in_choose_bit[1:0]</comment>
        </bits>
        <bits access="rw" name="clk_lp_inv" pos="23" rst="0">
          <comment>clk_lp inv</comment>
        </bits>
        <bits access="rw" name="trail_data_wrong_choose_bit" pos="24" rst="0">
          <comment>trail_data_wrong_choose_bit 1:secelt trail1  0:select trail0</comment>
        </bits>
        <bits access="rw" name="sync_bypass" pos="25" rst="0">
          <comment>sync_bypass</comment>
        </bits>
        <bits access="rw" name="rdata_bit_inv_en" pos="26" rst="0">
          <comment>rdata_bit_inv en</comment>
        </bits>
        <bits access="rw" name="hs_sync_find_en" pos="27" rst="0">
          <comment>hs_sync_find en</comment>
        </bits>
        <bits access="rw" name="line_packet_enable" pos="28" rst="0">
          <comment>line_packet_enable</comment>
        </bits>
        <bits access="rw" name="ecc_bypass" pos="29" rst="0">
          <comment>ecc_bypass</comment>
        </bits>
        <bits access="rw" name="data_lane_choose_bit" pos="30" rst="0">
          <comment>data_lane_choose_bit  1:select lane2  0:select lane1</comment>
        </bits>
        <bits access="rw" name="csi_module_enable" pos="31" rst="0">
          <comment>csi_module_enable</comment>
        </bits>
      </reg>
      <reg name="csi config reg1" protect="rw">
        <bits access="rw" name="num_hs_settle" pos="7:0" rst="8">
          <comment>num_hs_settle[7:0]  set hs settle time</comment>
        </bits>
        <bits access="rw" name="lp_data_length_choose_bit" pos="10:8" rst="0">
          <comment>lp_data_length_choose_bit[2:0]  set data length</comment>
        </bits>
        <bits access="rw" name="data_clk_lp_posedge_choose" pos="13:11" rst="0">
          <comment>data_clk_lp_posedge_choose[2:0]  select delay cycles</comment>
        </bits>
        <bits access="rw" name="clk_lp_ck_inv" pos="14" rst="0">
          <comment>clk_lp_ck_inv</comment>
        </bits>
        <bits access="rw" name="rclr_mask_en" pos="15" rst="1">
          <comment>rclr_mask_en</comment>
        </bits>
        <bits access="rw" name="rinc_mask_en" pos="16" rst="1">
          <comment>rinc_mask_en</comment>
        </bits>
        <bits access="rw" name="hs_enable_mask_en" pos="17" rst="1">
          <comment>hs_enable_mask_en</comment>
        </bits>
        <bits access="rw" name="den_csi_inv_bit" pos="18" rst="0">
          <comment>den_csi_inv_bit</comment>
        </bits>
        <bits access="rw" name="hsync_csi_inv_bit" pos="19" rst="0">
          <comment>hsync_csi_inv_bit</comment>
        </bits>
        <bits access="rw" name="vsync_csi_inv_bit" pos="20" rst="0">
          <comment>vsync_csi_inv_bit</comment>
        </bits>
        <bits access="rw" name="hs_data2_enable_reg" pos="21" rst="0">
          <comment>hs_data2_enable_reg</comment>
        </bits>
        <bits access="rw" name="hs_data1_enable_reg" pos="22" rst="0">
          <comment>hs_data1_enable_reg</comment>
        </bits>
        <bits access="rw" name="hs_data1_enable_choose_bit" pos="23" rst="0">
          <comment>hs_data1_enable_choose_bit</comment>
        </bits>
        <bits access="rw" name="hs_data1_enable_dr" pos="24" rst="0">
          <comment>hs_data1_enable_dr 1:select reg  0:select logic</comment>
        </bits>
        <bits access="rw" name="data2_terminal_enable_reg" pos="25" rst="0">
          <comment>data2_terminal_enable_reg</comment>
        </bits>
        <bits access="rw" name="data1_terminal_enable_reg" pos="26" rst="0">
          <comment>data1_terminal_enable_reg</comment>
        </bits>
        <bits access="rw" name="data1_terminal_enable_dr" pos="27" rst="0">
          <comment>data1_terminal_enable_dr 1:select reg  0:select logic</comment>
        </bits>
        <bits access="rw" name="lp_data_interrupt_clr" pos="28" rst="0">
          <comment>lp_data_interrupt_clr, clear flag</comment>
        </bits>
        <bits access="rw" name="lp_cmd_interrupt_clr" pos="29" rst="0">
          <comment>lp_cmd_interrupt_clr, clear flag</comment>
        </bits>
        <bits access="rw" name="lp_data_clr" pos="30" rst="0">
          <comment>lp_data_clr, clear data out</comment>
        </bits>
        <bits access="rw" name="lp_cmd_clr" pos="31" rst="0">
          <comment>lp_cmd_clr, clear cmd out</comment>
        </bits>
      </reg>
      <reg name="csi config reg2" protect="rw">
        <bits access="rw" name="num_hs_settle_clk" pos="15:0" rst="4096">
          <comment>num_hs_settle_clk[15:0], set hs settle counter</comment>
        </bits>
        <bits access="rw" name="num_c_term_en" pos="31:16" rst="4112">
          <comment>num_c_term_en[15:0],set clk term counter</comment>
        </bits>
      </reg>
      <reg name="csi config reg3" protect="rw">
        <bits access="rw" name="clk_lp_in_choose_bit" pos="7:6" rst="0">
          <comment>clk_lp_in_choose_bit</comment>
        </bits>
        <bits access="rw" name="pu_lprx_reg" pos="8" rst="0">
          <comment>pu_lprx_reg</comment>
        </bits>
        <bits access="rw" name="pu_hsrx_reg" pos="9" rst="0">
          <comment>pu_hsrx_reg</comment>
        </bits>
        <bits access="rw" name="pu_dr" pos="10" rst="0">
          <comment>pu_dr, 1:select reg  0:select logic</comment>
        </bits>
        <bits access="rw" name="data_pnsw_reg" pos="11" rst="0">
          <comment>data_pnsw_reg</comment>
        </bits>
        <bits access="rw" name="hs_clk_enable_reg" pos="12" rst="0">
          <comment>hs_clk_enable_reg</comment>
        </bits>
        <bits access="rw" name="hs_clk_enable_choose_bit" pos="13" rst="0">
          <comment>hs_clk_enable_choose_bit</comment>
        </bits>
        <bits access="rw" name="hs_clk_enable_dr" pos="14" rst="0">
          <comment>hs_clk_enable_dr  1:select reg  0:select logic</comment>
        </bits>
        <bits access="rw" name="clk_terminal_enable_reg" pos="15" rst="0">
          <comment>clk_terminal_enable_reg</comment>
        </bits>
        <bits access="rw" name="clk_terminal_enable_dr" pos="16" rst="0">
          <comment>clk_terminal_enable_dr   1:select reg  0:select logic</comment>
        </bits>
        <bits access="rw" name="observe_reg_5_low8_choose" pos="17" rst="0">
          <comment>observe_reg_5_low8_choose</comment>
        </bits>
        <bits access="rw" name="ecc_error_flag_reg" pos="18" rst="0">
          <comment>ecc_error_flag_reg</comment>
        </bits>
        <bits access="rw" name="ecc_error_dr" pos="19" rst="0">
          <comment>ecc_error_dr</comment>
        </bits>
        <bits access="rw" name="csi_channel_sel" pos="20" rst="0">
          <comment>csi_channel_sel</comment>
        </bits>
        <bits access="rw" name="two_lane_bit_reverse" pos="21" rst="0">
          <comment>two_lane_bit_reverse, reverse high and low 8bit</comment>
        </bits>
        <bits access="rw" name="data2_lane_bit_reverse" pos="22" rst="0">
          <comment>data2_lane_bit_reverse 1:select revert data</comment>
        </bits>
        <bits access="rw" name="data1_lane_bit_reverse" pos="23" rst="0">
          <comment>data1_lane_bit_reverse 1:select revert data</comment>
        </bits>
        <bits access="rw" name="data2_hs_no_mask" pos="24" rst="0">
          <comment>data2_hs_no_mask  1:data only valid when sync assert</comment>
        </bits>
        <bits access="rw" name="data1_hs_no_mask" pos="25" rst="0">
          <comment>data1_hs_no_mask  1:data only valid when sync assert</comment>
        </bits>
        <bits access="rw" name="pu_lprx_d2_reg" pos="26" rst="0">
          <comment>pu_lprx_d2_reg</comment>
        </bits>
        <bits access="rw" name="pu_lprx_d1_reg" pos="27" rst="0">
          <comment>pu_lprx_d1_reg</comment>
        </bits>
        <bits access="rw" name="clk_edge_sel" pos="29" rst="0">
          <comment>clk_edge_sel</comment>
        </bits>
        <bits access="rw" name="clk_x2_sel" pos="30" rst="0">
          <comment>clk_x2_sel</comment>
        </bits>
        <bits access="rw" name="single_data_lane_en" pos="31" rst="0">
          <comment>single_data_lane_en  1:1lane  0:2lanes</comment>
        </bits>
      </reg>
      <reg name="csi config reg4" protect="rw">
        <bits access="rw" name="num_hs_clk_useful" pos="30:0" rst="0">
          <comment>num_hs_clk_useful[30:0]   hs clk useful counter</comment>
        </bits>
        <bits access="rw" name="num_hs_clk_useful_en" pos="31" rst="0">
          <comment>num_hs_clk_useful_en</comment>
        </bits>
      </reg>
      <reg name="csi config reg5" protect="rw">
        <bits access="rw" name="vc_id_set" pos="1:0" rst="0">
          <comment>vc_id_set[1:0]</comment>
        </bits>
        <bits access="rw" name="data_lp_inv" pos="2" rst="0">
          <comment>data_lp_inv</comment>
        </bits>
        <bits access="rw" name="fifo_rclr_8809p_reg" pos="3" rst="0">
          <comment>fifo_rclr_8809p_reg</comment>
        </bits>
        <bits access="rw" name="fifo_wclr_8809p_reg" pos="4" rst="0">
          <comment>fifo_wclr_8809p_reg</comment>
        </bits>
        <bits access="rw" name="hs_sync_16bit_8809p_mode" pos="5" rst="0">
          <comment>hs_sync_16bit_8809p_mode</comment>
        </bits>
        <bits access="rw" name="d_term_small_8809p_en" pos="6" rst="0">
          <comment>d_term_small_8809p_en</comment>
        </bits>
        <bits access="rw" name="data_line_inv_8809p_en" pos="7" rst="0">
          <comment>data_line_inv_8809p_en</comment>
        </bits>
        <bits access="rw" name="hs_enable_8809p_mode" pos="8" rst="0">
          <comment>hs_enable_8809p_mode</comment>
        </bits>
        <bits access="rw" name="sp_to_trail_8809p_en" pos="9" rst="0">
          <comment>sp_to_trail_8809p_en</comment>
        </bits>
        <bits access="rw" name="trail_wrong_8809p_bypass" pos="10" rst="0">
          <comment>trail_wrong_8809p_bypass</comment>
        </bits>
        <bits access="rw" name="rinc_trail_8809p_bypass" pos="11" rst="0">
          <comment>rinc_trail_8809p_bypass</comment>
        </bits>
        <bits access="rw" name="hs_data_enable_8809p_mode" pos="12" rst="0">
          <comment>hs_data_enable_8809p_mode</comment>
        </bits>
        <bits access="rw" name="hs_clk_enable_8809p_mode" pos="13" rst="0">
          <comment>hs_clk_enable_8809p_mode</comment>
        </bits>
        <bits access="rw" name="data_type_re_check_en" pos="14" rst="0">
          <comment>data_type_re_check_en</comment>
        </bits>
        <bits access="rw" name="sync_id_reg" pos="22:15" rst="0">
          <comment>sync_id_reg</comment>
        </bits>
        <bits access="rw" name="sync_id_dr" pos="23" rst="0">
          <comment>sync_id_dr</comment>
        </bits>
        <bits access="rw" name="csi_observe_choose_bit" pos="28:24" rst="0">
          <comment>csi_observe_choose_bit</comment>
        </bits>
        <bits access="rw" name="crc_error_flag_reg" pos="29" rst="0">
          <comment>crc_error_flag_reg</comment>
        </bits>
        <bits access="rw" name="crc_error_flag_dr" pos="30" rst="0">
          <comment>crc_error_flag_dr  1:select reg 0:select logic</comment>
        </bits>
        <bits access="rw" name="csi_rinc_new_mode_dis" pos="31" rst="0">
          <comment>csi_rinc_new_mode_dis</comment>
        </bits>
      </reg>
      <reg name="csi config reg6" protect="rw">
        <bits access="rw" name="data_type_dp_reg" pos="5:0" rst="0">
          <comment>data_type_dp_reg[5:0],  set data type</comment>
        </bits>
        <bits access="rw" name="data_type_le_reg" pos="11:6" rst="0">
          <comment>data_type_le_reg  line end type</comment>
        </bits>
        <bits access="rw" name="data_type_ls_reg" pos="17:12" rst="0">
          <comment>data_type_ls_reg  line start type</comment>
        </bits>
        <bits access="rw" name="data_type_fe_reg" pos="23:18" rst="0">
          <comment>data_type_fe_reg  frame end type</comment>
        </bits>
        <bits access="rw" name="data_type_fs_reg" pos="29:24" rst="0">
          <comment>data_type_fs_reg  frame start type</comment>
        </bits>
        <bits access="rw" name="data_type_dp_dr" pos="30" rst="0">
          <comment>1: only support raw8   0:support more type</comment>
        </bits>
        <bits access="rw" name="data_type_dr" pos="31" rst="0">
          <comment>1:select reg value</comment>
        </bits>
      </reg>
      <reg name="csi config reg7" protect="rw">
        <bits access="rw" name="data_lane_16bits_mode" pos="2" rst="0">
          <comment>data_lane_16bits_mode</comment>
        </bits>
        <bits access="rw" name="terminal_2_hs_exchage_8809p" pos="3" rst="0">
          <comment>terminal_2_hs_exchage_8809p</comment>
        </bits>
        <bits access="rw" name="terminal_1_hs_exchage_8809p" pos="4" rst="0">
          <comment>terminal_1_hs_exchage_8809p</comment>
        </bits>
        <bits access="rw" name="data2_terminal_enable_8809p_dr" pos="5" rst="0">
          <comment>data2_terminal_enable_8809p_dr</comment>
        </bits>
        <bits access="rw" name="hs_data2_enable_8809p_dr" pos="6" rst="0">
          <comment>hs_data2_enable_8809p_dr</comment>
        </bits>
        <bits access="rw" name="csi_dout_test_8809p_en" pos="7" rst="0">
          <comment>csi_dout_test_8809p_en</comment>
        </bits>
        <bits access="rw" name="csi_dout_test_8809p" pos="15:8" rst="0">
          <comment>csi_dout_test_8809p[7:0]</comment>
        </bits>
        <bits access="rw" name="num_d_term_en" pos="23:16" rst="0">
          <comment>num_d_term_en[15:8]</comment>
        </bits>
        <bits access="rw" name="num_hs_settle" pos="31:24" rst="0">
          <comment>num_hs_settle[15:8]</comment>
        </bits>
      </reg>
      <reg name="csi obs4" protect="rw">
        <bits access="rw" name="hs_data_state" pos="13:0" rst="0">
          <comment>hs_data_state[13:0]</comment>
        </bits>
        <bits access="rw" name="phy_data_state" pos="28:14" rst="0">
          <comment>phy_data_state[14:0]</comment>
        </bits>
        <bits access="rw" name="fifo_wfull_almost" pos="29" rst="0">
          <comment>fifo_wfull_almost</comment>
        </bits>
        <bits access="rw" name="fifo_wfull" pos="30" rst="0">
          <comment>fifo_wfull</comment>
        </bits>
        <bits access="rw" name="fifo_wempty" pos="31" rst="1">
          <comment>fifo_wempty</comment>
        </bits>
      </reg>
      <reg name="csi obs5" protect="rw">
        <bits access="ro" name="csi_observe_reg_5_low" pos="7:0" rst="0">
          <comment>if observe_reg_5_low8_choose=1, out is data_id[7:0], else out is lp_cmd_out[7:0]</comment>
        </bits>
        <bits access="ro" name="lp_data_interrupt_flag" pos="8" rst="0">
          <comment>lp_data_interrupt_flag</comment>
        </bits>
        <bits access="ro" name="lp_cmd_interrupt_flag" pos="9" rst="0">
          <comment>lp_data_interrupt_flag</comment>
        </bits>
        <bits access="ro" name="phy_clk_state" pos="18:10" rst="0">
          <comment>phy_clk_state[8:0]</comment>
        </bits>
        <bits access="ro" name="fifo_rcount" pos="27:19" rst="0">
          <comment>fifo_rcount[8:0]</comment>
        </bits>
        <bits access="ro" name="crc_error" pos="28" rst="0">
          <comment>crc_error</comment>
        </bits>
        <bits access="ro" name="err_ecc_corrected_flag" pos="29" rst="0">
          <comment>err_ecc_corrected_flag</comment>
        </bits>
        <bits access="ro" name="err_data_corrected_flag" pos="30" rst="0">
          <comment>err_data_corrected_flag</comment>
        </bits>
        <bits access="ro" name="err_data_zero_flag" pos="31" rst="1">
          <comment>err_data_zero_flag</comment>
        </bits>
      </reg>
      <reg name="csi obs6" protect="rw">
        <bits access="ro" name="csi_observe_reg_6" pos="31:0" rst="0">
          <comment>if observe_reg_5_low8_choose=1, out is csi_observe_mon, else out is lp_data_out[63:32]</comment>
        </bits>
      </reg>
      <reg name="csi obs7" protect="rw">
        <bits access="ro" name="csi_observe_reg_7" pos="31:0" rst="0">
          <comment>csi_observe_reg_7[31:0]</comment>
        </bits>
      </reg>
      <reg name="csi enable" protect="rw">
        <bits access="rw" name="csi_enable" pos="0" rst="0">
          <comment>csi_enable</comment>
        </bits>
      </reg>
      <reg name="csi config reg8" protect="rw">
        <bits access="rw" name="dly_sel_clkn_reg" pos="3:0" rst="0">
          <comment>dly_sel_clkn_reg,set clkn delay,to csi analog phy</comment>
        </bits>
        <bits access="rw" name="dly_sel_clkp_reg" pos="7:4" rst="0">
          <comment>dly_sel_clkp_reg,set clkp delay,to csi analog phy</comment>
        </bits>
        <bits access="rw" name="dly_sel_data2_reg" pos="11:8" rst="0">
          <comment>dly_sel_data2_reg,set data2 delay,to csi analog phy</comment>
        </bits>
        <bits access="rw" name="dly_sel_data1_reg" pos="15:12" rst="0">
          <comment>dly_sel_data1_reg,set data1 delay,to csi analog phy</comment>
        </bits>
        <bits access="rw" name="vth_sel" pos="16" rst="0">
          <comment>vth_sel,to csi analog phy</comment>
        </bits>
      </reg>
      <hole size="222*32"/>
      <struct count="FIFORAM_SIZE" name="fiforam">
        <reg name="ramdata" protect="r">
          <bits access="r" name="data" pos="31:0" rst="0">
            <comment>Direct FIFO Ram Access. They are enabled only in Bist Mode.</comment>
            <options>
              <mask/>
              <shift/>
              <default/>
            </options>
          </bits>
        </reg>
      </struct>
      <hole size="176*32"/>
      <reg name="soft_reset" protect="rw">
        <bits access="rw" name="dsp_reset" pos="0" rst="0x1">
          <comment>rstn of dsp</comment>
        </bits>
      </reg>
      <hole size="17*32"/>
      <reg name="awb_x1_min" protect="rw">
        <bits access="rw" name="awb_x1_min" pos="7:0" rst="0x78">
          <comment>for A ctd block, u2.7 format
                  awb_x1_min[8:0]=[awb_ctd_msb[0],awb_x1_min[7:0]]</comment>
        </bits>
      </reg>
      <reg name="awb_x1_max" protect="rw">
        <bits access="rw" name="awb_x1_max" pos="7:0" rst="0x99">
          <comment>for A ctd block, u2.7 format
                  awb_x1_max[8:0]=[awb_ctd_msb[1],awb_x1_max[7:0]]</comment>
        </bits>
      </reg>
      <reg name="awb_y1_min" protect="rw">
        <bits access="rw" name="awb_y1_min" pos="7:0" rst="0x27">
          <comment>for A ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_y1_max" protect="rw">
        <bits access="rw" name="awb_y1_max" pos="7:0" rst="0x3c">
          <comment>for A ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_x2_min" protect="rw">
        <bits access="rw" name="awb_x2_min" pos="7:0" rst="0x5b">
          <comment>for TL84 ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_x2_max" protect="rw">
        <bits access="rw" name="awb_x2_max" pos="7:0" rst="0x70">
          <comment>for TL84 ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_y2_min" protect="rw">
        <bits access="rw" name="awb_y2_min" pos="7:0" rst="0x34">
          <comment>for TL84 ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_y2_max" protect="rw">
        <bits access="rw" name="awb_y2_max" pos="7:0" rst="0x4d">
          <comment>for TL84 ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_x3_min" protect="rw">
        <bits access="rw" name="awb_x3_min" pos="7:0" rst="0x44">
          <comment>for CWF ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_x3_max" protect="rw">
        <bits access="rw" name="awb_x3_max" pos="7:0" rst="0x5a">
          <comment>for CWF ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_y3_min" protect="rw">
        <bits access="rw" name="awb_y3_min" pos="7:0" rst="0x2b">
          <comment>for CWF ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_y3_max" protect="rw">
        <bits access="rw" name="awb_y3_max" pos="7:0" rst="0x44">
          <comment>for CWF ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_x4_min" protect="rw">
        <bits access="rw" name="awb_x4_min" pos="7:0" rst="0x42">
          <comment>for Indoor ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_x4_max" protect="rw">
        <bits access="rw" name="awb_x4_max" pos="7:0" rst="0x5c">
          <comment>for Indoor ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_y4_min" protect="rw">
        <bits access="rw" name="awb_y4_min" pos="7:0" rst="0x4f">
          <comment>for Indoor ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_y4_max" protect="rw">
        <bits access="rw" name="awb_y4_max" pos="7:0" rst="0x68">
          <comment>for Indoor ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_x5_min" protect="rw">
        <bits access="rw" name="awb_x5_min" pos="7:0" rst="0x2d">
          <comment>for D65 ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_x5_max" protect="rw">
        <bits access="rw" name="awb_x5_max" pos="7:0" rst="0x47">
          <comment>for D65 ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_y5_min" protect="rw">
        <bits access="rw" name="awb_y5_min" pos="7:0" rst="0x6d">
          <comment>for D65 ctd block, u2.7 format
                  awb_y5_min[8:0]=[awb_ctd_msb[2],awb_y5_min[7:0]]</comment>
        </bits>
      </reg>
      <reg name="awb_y5_max" protect="rw">
        <bits access="rw" name="awb_y5_max" pos="7:0" rst="0x83">
          <comment>for D65 ctd block, u2.7 format
                  awb_y5_max[8:0]=[awb_ctd_msb[3],awb_y5_max[7:0]]</comment>
        </bits>
      </reg>
      <reg name="awb_skin_x1_min" protect="rw">
        <bits access="rw" name="awb_skin_x1_min" pos="7:0" rst="0x90">
          <comment>for TL84 skin ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_skin_x1_max" protect="rw">
        <bits access="rw" name="awb_skin_x1_max" pos="7:0" rst="0xa8">
          <comment>for TL84 skin ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_skin_y1_min" protect="rw">
        <bits access="rw" name="awb_skin_y1_min" pos="7:0" rst="0x28">
          <comment>for TL84 skin ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_skin_y1_max" protect="rw">
        <bits access="rw" name="awb_skin_y1_max" pos="7:0" rst="0x45">
          <comment>for TL84 skin ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_skin_x2_min" protect="rw">
        <bits access="rw" name="awb_skin_x2_min" pos="7:0" rst="0x73">
          <comment>for CWF skin ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_skin_x2_max" protect="rw">
        <bits access="rw" name="awb_skin_x2_max" pos="7:0" rst="0x8c">
          <comment>for CWF skin ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_skin_y2_min" protect="rw">
        <bits access="rw" name="awb_skin_y2_min" pos="7:0" rst="0x18">
          <comment>for CWF skin ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_skin_y2_max" protect="rw">
        <bits access="rw" name="awb_skin_y2_max" pos="7:0" rst="0x39">
          <comment>for CWF skin ctd block, u1.7 format</comment>
        </bits>
      </reg>
      <reg name="awb_ctd_msb" protect="rw">
        <bits access="rw" name="awb_x1_min_msb" pos="0" rst="0x0">
          <comment>awb_x1_min[8:0]=[awb_x1_min_msb,awb_x1_min[7:0]]</comment>
        </bits>
        <bits access="rw" name="awb_x1_max_msb" pos="1" rst="0x0">
          <comment>awb_x1_max[8:0]=[awb_x1_max_msb,awb_x1_max[7:0]]</comment>
        </bits>
        <bits access="rw" name="awb_y5_min_msb" pos="2" rst="0x0">
          <comment>awb_y5_min[8:0]=[awb_y5_min_msb,awb_y5_min[7:0]]</comment>
        </bits>
        <bits access="rw" name="awb_y5_max_msb" pos="3" rst="0x0">
          <comment>awb_y5_max[8:0]=[awb_y5_max_msb,awb_y5_max[7:0]]</comment>
        </bits>
        <bits access="rw" name="awb_adj_mode" pos="5:4" rst="0x0">
          <comment>2d0: awb_adj_sig=1
                  2d1: awb_adj_sig= crsum_abs&gt;vld_cnt_cr_thr x2 or  cbsum_abs&gt;vld_cnt_cb_thr x2
                  2d2: awb_adj_sig= crsum_abs&gt;vld_cnt_cr_thr x3 or  cbsum_abs&gt;vld_cnt_cb_thr x3
                  2d3: awb_adj_sig= crsum_abs&gt;vld_cnt_cr_thr x2 and cbsum_abs&gt;vld_cnt_cb_thr x2</comment>
        </bits>
        <bits access="rw" name="awb_ratio_mode" pos="7:6" rst="0x0">
          <comment>2d3: awb_ratio_lmax=4
                  2d2: awb_ratio_lmax=2
                  2d1: awb_ratio_lmax=0
                  2d0: awb_ratio_lmax= according to the proportion of cnt_max and cnt_lmax</comment>
        </bits>
      </reg>
      <reg name="int_dif_thr_mid" protect="rw">
        <bits access="rw" name="int_dif_thr_mid" pos="7:0" rst="0x18">
          <comment/>
        </bits>
      </reg>
      <reg name="lb_soft_rstn" protect="rw">
        <bits access="rw" name="lb_soft_rstn" pos="0" rst="0x1">
          <comment/>
        </bits>
      </reg>
      <reg name="vsync_end_high" protect="rw">
        <bits access="rw" name="vsync_end_high" pos="7:0" rst="0x0">
          <comment>vsync_end_reg=[vsync_end_high,vsync_end_low]</comment>
        </bits>
      </reg>
      <reg name="vsync_end_low" protect="rw">
        <bits access="rw" name="vsync_end_low" pos="7:0" rst="0x01">
          <comment>vsync_end_reg=[vsync_end_high,vsync_end_low]</comment>
        </bits>
      </reg>
      <reg name="line_numl" protect="rw">
        <bits access="rw" name="line_numl" pos="7:0" rst="0xe8">
          <comment>line_num = [line_numH,line_numL]</comment>
        </bits>
      </reg>
      <reg name="pix_numl" protect="rw">
        <bits access="rw" name="pix_numl" pos="7:0" rst="0x88">
          <comment>pix_num = [pix_numH,pix_numL]</comment>
        </bits>
      </reg>
      <reg name="pix_line_numh" protect="rw">
        <bits access="rw" name="line_numh" pos="0" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="pix_numh_rsvd" pos="3:1" rst="0x0">
          <comment>not used here</comment>
        </bits>
        <bits access="rw" name="pix_numh" pos="5:4" rst="0x2">
          <comment/>
        </bits>
        <bits access="rw" name="line_numh_rsvd" pos="7:6" rst="0x0">
          <comment>not used here</comment>
        </bits>
      </reg>
      <reg name="lb_ctrl" protect="rw">
        <bits access="rw" name="low_order" pos="0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="use_fb_reg" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="not_cvp_reg" pos="2" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="first_byte_reg" pos="5:3" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="data_format" protect="rw">
        <bits access="rw" name="data_format" pos="1:0" rst="0x0">
          <comment>00:YUV/RAW8(para)
                  01:RAW8(mipi)
                  10:RAW10(mipi)</comment>
        </bits>
      </reg>
      <reg name="lb_enable" protect="rw">
        <bits access="rw" name="lb_enable" pos="0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="vh_inv" protect="rw">
        <bits access="rw" name="hsync_inv" pos="0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="vsync_inv" pos="1" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="line_cnt_l" protect="ro">
        <bits access="ro" name="line_cnt_l" pos="7:0" rst="0x0">
          <comment>line_cnt=[line_cnt_H[1:0], [7:0]]</comment>
        </bits>
      </reg>
      <reg name="line_cnt_h" protect="ro">
        <bits access="ro" name="line_cnt_h" pos="1:0" rst="0x0">
          <comment>line_cnt=[line_cnt_H[1:0], line_cnt_L]</comment>
        </bits>
      </reg>
      <reg name="num_check" protect="rw">
        <bits access="ro" name="line_num_check" pos="0" rst="0x0">
          <comment/>
        </bits>
        <bits access="ro" name="byte_num_check" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="wo" name="line_num_clear" pos="4" rst="0x0">
          <comment/>
        </bits>
        <bits access="wo" name="byte_num_clear" pos="5" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dci_ctrl_reg" protect="rw">
        <bits access="rw" name="kl_low_light_fix" pos="0" rst="0x1">
          <comment>1: kl 0: kldci ()</comment>
        </bits>
        <bits access="rw" name="kl_reg_fix" pos="1" rst="0x1">
          <comment>1: kl 0: kldci</comment>
        </bits>
        <bits access="rw" name="ku_low_light_fix" pos="2" rst="0x1">
          <comment>1: ku 0: kudci ()</comment>
        </bits>
        <bits access="rw" name="ku_reg_fix" pos="3" rst="0x1">
          <comment>1: ku 0: kudci</comment>
        </bits>
        <bits access="rw" name="hofst" pos="5:4" rst="0x0">
          <comment>hist 2</comment>
        </bits>
        <bits access="rw" name="vbh_sel" pos="7:6" rst="0x0">
          <comment>00: 0x98regae_dark_hist_reg
                  01: 0x98regyave_target_RO_reg
                  other: 0x98regyave_contr_reg</comment>
        </bits>
      </reg>
      <reg name="dci_ofst_reg" protect="rw">
        <bits access="rw" name="kl_ofstx1" pos="3:0" rst="0x8">
          <comment>kl_ofstx1[4:0] = [kl_ofstx1, 1b0] (kl0x80)</comment>
        </bits>
        <bits access="rw" name="ku_ofstx1" pos="7:4" rst="0x8">
          <comment>ku_ofstx1[4:0] = [ku_ofstx1, 1b0] (kl0x80)</comment>
        </bits>
      </reg>
      <reg name="dci_hist_reg" protect="rw">
        <bits access="rw" name="dk_histx1" pos="3:0" rst="0x8">
          <comment>dk_histx1[4:0] = [dk_histx1, 1b0] (dhist)</comment>
        </bits>
        <bits access="rw" name="br_histx1" pos="7:4" rst="0x8">
          <comment>br_histx1[4:0] = [br_histx1, 1b0] (bhist)</comment>
        </bits>
      </reg>
      <reg name="ae_sw_ctrl_reg" protect="rw">
        <bits access="rw" name="nexp_sw_in" pos="3:0" rst="0x0">
          <comment>swaeswexp/gainnexphw//</comment>
        </bits>
        <bits access="wo" name="ae_ext_adj_start" pos="7" rst="0x0">
          <comment>sw/hwae,SWae,</comment>
        </bits>
      </reg>
      <reg name="ae_thr_reg" protect="rw">
        <bits access="rw" name="thr_dark" pos="3:0" rst="0x3">
          <comment>THR_dark[4:0] = [THR_dark, 1'b0] (ytarget-yave  THR_darkae)</comment>
        </bits>
        <bits access="rw" name="thr_bright" pos="7:4" rst="0x8">
          <comment>THR_bright[4:0] = [THR_bright,1'b0](yave-ytargetTHR_brightae)</comment>
        </bits>
      </reg>
      <reg name="ae_misc_ctrl_reg" protect="rw">
        <bits access="rw" name="ofst_dec_low_sel" pos="1:0" rst="0x0">
          <comment>ytarget_dec
                  2d3:4indexytargetregd[3:0]8index08
                  2d2:2indexytargetregd[3:0]8index016
                  2d1:1indexytargetregd[3:0]8index032
                  2d0:1indexytargetregd[3:0]8index064</comment>
        </bits>
        <bits access="rw" name="ofst_dec_high_sel" pos="3:2" rst="0x0">
          <comment>ytarget_dec
                  2d3:4indexytargetregc[7:4]8index_max8
                  2d2:2indexytargetregc[7:4]8index_max16
                  2d1:1indexytargetregd[7:4]8index_max32
                  2d0:1indexytargetregd[7:4]8index_max64</comment>
        </bits>
        <bits access="rw" name="force_adj1" pos="4" rst="0x0">
          <comment>1yave_diff_2frame</comment>
        </bits>
        <bits access="rw" name="force_adj2" pos="5" rst="0x0">
          <comment>1THR_big</comment>
        </bits>
        <bits access="rw" name="force_adj3" pos="6" rst="0x0">
          <comment>1bhist&gt;0@is_dark</comment>
        </bits>
        <bits access="rw" name="index_ofst_no_step" pos="7" rst="0x0">
          <comment>1index_ofst</comment>
        </bits>
      </reg>
      <reg name="csup_xx_reg" protect="rw">
        <bits access="rw" name="x_low" pos="3:0" rst="0x0">
          <comment>@nexp</comment>
        </bits>
        <bits access="rw" name="x_high" pos="7:4" rst="0x8">
          <comment>@nexp</comment>
        </bits>
      </reg>
      <reg name="contr_ythr_reg" protect="rw">
        <bits access="rw" name="csup_gain_low_th_h" pos="0" rst="0x1">
          <comment>low_th = [[0], lsc_blc_gain_th[7:6]](nexp=low_th)</comment>
        </bits>
        <bits access="rw" name="csup_gain_high_th" pos="3:1" rst="0x3">
          <comment>nexp&gt;(8+high_th)</comment>
        </bits>
        <bits access="rw" name="fixed_contr_ythr" pos="7:4" rst="0x8">
          <comment>Fixed Ythr of contr = [[7:4], 4d0]</comment>
        </bits>
      </reg>
      <reg name="contr_yave_offset_reg" protect="rw">
        <bits access="rw" name="yave_offset_reg" pos="5:0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="ythr_sel" pos="6" rst="0x1">
          <comment>1: dynamic yave (Yave)
                  0: fixed ythr contr_ythr_reg</comment>
        </bits>
        <bits access="rw" name="yave_offset_sign" pos="7" rst="0x0">
          <comment>YaveYthrofst (01)</comment>
        </bits>
      </reg>
      <reg name="contr_ku_lo_reg" protect="rw">
        <bits access="rw" name="ku" pos="6:0" rst="0x20">
          <comment>upper@Low gain
                  Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin))</comment>
        </bits>
        <bits access="rw" name="ku_sign" pos="7" rst="0x1">
          <comment>1: 0</comment>
        </bits>
      </reg>
      <reg name="contr_kl_lo_reg" protect="rw">
        <bits access="rw" name="kl" pos="6:0" rst="0x20">
          <comment>lower@Low gain
                  Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin)</comment>
        </bits>
        <bits access="rw" name="kl_sign" pos="7" rst="0x1">
          <comment>1: 0</comment>
        </bits>
      </reg>
      <reg name="contr_ku_mid_reg" protect="rw">
        <bits access="rw" name="ku" pos="6:0" rst="0x10">
          <comment>upper@Mid gain
                  Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin))</comment>
        </bits>
        <bits access="rw" name="ku_sign" pos="7" rst="0x1">
          <comment>1: 0</comment>
        </bits>
      </reg>
      <reg name="contr_kl_mid_reg" protect="rw">
        <bits access="rw" name="kl" pos="6:0" rst="0x10">
          <comment>lower@Mid gain
                  Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin)</comment>
        </bits>
        <bits access="rw" name="kl_sign" pos="7" rst="0x1">
          <comment>1: 0</comment>
        </bits>
      </reg>
      <reg name="contr_ku_hi_reg" protect="rw">
        <bits access="rw" name="ku" pos="6:0" rst="0x70">
          <comment>upper@High gain
                  Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin))</comment>
        </bits>
        <bits access="rw" name="ku_sign" pos="7" rst="0x0">
          <comment>1: 0</comment>
        </bits>
      </reg>
      <reg name="contr_kl_hi_reg" protect="rw">
        <bits access="rw" name="kl" pos="6:0" rst="0x70">
          <comment>lower@High gain
                  Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin)</comment>
        </bits>
        <bits access="rw" name="kl_sign" pos="7" rst="0x0">
          <comment>1: 0</comment>
        </bits>
      </reg>
      <reg name="luma_offset_lo_reg" protect="rw">
        <bits access="rw" name="offset" pos="5:0" rst="0x0">
          <comment>@Low gain</comment>
        </bits>
        <bits access="rw" name="algo_sel" pos="6" rst="0x0">
          <comment>1: Yout = (256-offset)*Yin/256 + offset
                  0: Yout = Yin + offset</comment>
        </bits>
        <bits access="rw" name="offset_sign" pos="7" rst="0x0">
          <comment>0   1</comment>
        </bits>
      </reg>
      <reg name="luma_offset_mid_reg" protect="rw">
        <bits access="rw" name="offset" pos="5:0" rst="0x0">
          <comment>@Mid gain</comment>
        </bits>
        <bits access="rw" name="algo_sel" pos="6" rst="0x0">
          <comment>1: Yout = (256-offset)*Yin/256 + offset
                  0: Yout = Yin + offset</comment>
        </bits>
        <bits access="rw" name="offset_sign" pos="7" rst="0x0">
          <comment>0   1</comment>
        </bits>
      </reg>
      <reg name="luma_offset_hi_reg" protect="rw">
        <bits access="rw" name="offset" pos="5:0" rst="0x0">
          <comment>@High gain</comment>
        </bits>
        <bits access="rw" name="algo_sel" pos="6" rst="0x0">
          <comment>1: Yout = (256-offset)*Yin/256 + offset
                  0: Yout = Yin + offset</comment>
        </bits>
        <bits access="rw" name="offset_sign" pos="7" rst="0x0">
          <comment>0   1</comment>
        </bits>
      </reg>
      <reg name="u_gain_lo_reg" protect="rw">
        <bits access="rw" name="u_gain_lo_reg" pos="7:0" rst="0xb0">
          <comment>Cb@Low gain0x80 just x1.0</comment>
        </bits>
      </reg>
      <reg name="v_gain_lo_reg" protect="rw">
        <bits access="rw" name="v_gain_lo_reg" pos="7:0" rst="0xb0">
          <comment>Cr@Low gain0x80 just x1.0</comment>
        </bits>
      </reg>
      <reg name="u_gain_mid_reg" protect="rw">
        <bits access="rw" name="u_gain_mid_reg" pos="7:0" rst="0xa0">
          <comment>Cb@Mid gain0x80 just x1.0</comment>
        </bits>
      </reg>
      <reg name="v_gain_mid_reg" protect="rw">
        <bits access="rw" name="v_gain_mid_reg" pos="7:0" rst="0xa0">
          <comment>Cr@Mid gain0x80 just x1.0</comment>
        </bits>
      </reg>
      <reg name="u_gain_hi_reg" protect="rw">
        <bits access="rw" name="u_gain_hi_reg" pos="7:0" rst="0x80">
          <comment>Cb@High gain0x80 just x1.0</comment>
        </bits>
      </reg>
      <reg name="v_gain_hi_reg" protect="rw">
        <bits access="rw" name="v_gain_hi_reg" pos="7:0" rst="0x80">
          <comment>Cr@High gain0x80 just x1.0</comment>
        </bits>
      </reg>
      <reg name="again_sel_th0_reg" protect="rw">
        <bits access="rw" name="contr_gain_low_th" pos="2:0" rst="0x4">
          <comment>@luma/contr/satur(nexp=low_th)</comment>
        </bits>
        <bits access="rw" name="again_sel_th0_rsvd" pos="3" rst="0x0">
          <comment>not used here</comment>
        </bits>
        <bits access="rw" name="contr_gain_hi_th" pos="6:4" rst="0x3">
          <comment>@luma/contr/satur(nexp&gt;(8+high_th))</comment>
        </bits>
      </reg>
      <reg name="awb_cc_type_ctrl_reg" protect="rw">
        <bits access="rw" name="cc_type_mode" pos="3:0" rst="0x0">
          <comment>4'd0:         cc_type = 0; //D65
                  4'd1:         cc_type = 1; //U30
                  4'd2:if(is_outdoor) cc_type = 0;
                       else           cc_type = 1;
                  4'd3:if(ana_gain&gt;=cc_gain_th) cc_type = 0;
                       else                     cc_type = 1;
                  4'd4:if(rgain_bigger)         cc_type = 0; //D65
                       else if(bgain_bigger)    cc_type = 1; //U30
                  4'd5: if(is_outdoor)          cc_type = 0;
                        else if(rgain_bigger)   cc_type = 0;
                        else if(bgain_bigger)   cc_type = 1;
                  4'd6: if(is_outdoor)                 cc_type = 0;
                        else if(ana_gain=cc_gain_th) cc_type = 0;
                        else if(rgain_bigger)          cc_type = 0;
                        else if(bgain_bigger)          cc_type = 1;
                  4'd7: if(is_outdoor)                 cc_type = 0;
                        else if(ana_gain=cc_gain_th) cc_type = 1;
                        else if(rgain_bigger)          cc_type = 0;
                        else if(bgain_bigger)          cc_type = 1;
                  4'd8: if(r_awb_gain_outr_low_non_A)cc_type = 1;
                        else if(r_awb_gain_out(r_low_non_A+8)) cc_type = 0;
                  4d9: if(awb_idx_max2)       cc_type = 1;
                         else if(awb_idx_max2)  cc_type = 0;
                  other: SW driven  ( reg1c2)</comment>
        </bits>
        <bits access="rw" name="cc_gain_hi_th" pos="6:4" rst="0x0">
          <comment>nexp&gt;(8+high_th)</comment>
        </bits>
        <bits access="rw" name="luma_first" pos="7" rst="0x0">
          <comment>1:  0:</comment>
        </bits>
      </reg>
      <reg name="awb_cc_type_th_reg" protect="rw">
        <bits access="rw" name="r_big_th" pos="3:0" rst="0x1">
          <comment>r_big_th=[awb_cc_type_th_reg[3:0], 2d0]</comment>
        </bits>
        <bits access="rw" name=" b_big_th" pos="7:4" rst="0x1">
          <comment>b_big_th=[awb_cc_type_th_reg[7:4], 2d0]</comment>
        </bits>
      </reg>
      <reg name="isp_wrapper_ctrl_1" protect="rw">
        <bits access="rw" name="pout_mode" pos="1:0" rst="0x0">
          <comment>00: YUV422     01: RGB565
                  10: raw bayer  11: clip out</comment>
        </bits>
        <bits access="rw" name="yuv_mode" pos="3:2" rst="0x0">
          <comment>00:YUYV       01:YVYU
                  10:UYVY       11:VYUY
                 (Note:[2] uv_sel  0:UV  1:VU)</comment>
        </bits>
        <bits access="rw" name="vsync_toggle" pos="4" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="mipi_rstn" pos="5" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name=" hsync_fix" pos="6" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="top_dummy" protect="rw">
        <bits access="rw" name="top_dummy" pos="6:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="left_dummy" protect="rw">
        <bits access="rw" name="left_dummy" pos="7:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="isp_wrapper_ctrl_2" protect="rw">
        <bits access="rw" name="rgb_mode_reg" pos="2:0" rst="0x0">
          <comment>Case(rgb_mode_reg)  @clip out
                  3'd0: to_n_clp_data     3'd1: y_data
                  3'd2: cnr_1d_cb         3'd3: cnr_1d_cr
                  3'd4: c_data            3'd5: yc2r_data
                  3'd6: yc2g_data         3'd7: yc2b_data
                  Note:rgb_mode_reg[0] is also used to
                  1, select the line of sub_YUV output</comment>
        </bits>
        <bits access="rw" name="sub_mode" pos="3" rst="0x0">
          <comment>not used, sca_reg=1:sub mode</comment>
        </bits>
        <bits access="rw" name="mon_mode_reg" pos="4" rst="0x0">
          <comment>bypass vsync_in and hsync_in</comment>
        </bits>
        <bits access="rw" name="oclk_inv_reg" pos="5" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="isp_out_en" pos="6" rst="0x1">
          <comment/>
        </bits>
      </reg>
      <reg name="line_num_l_reg" protect="rw">
        <bits access="rw" name="line_num_l_reg" pos="5:0" rst="0x3c">
          <comment>Line_num=[lin_num_l_reg[5:0], 3d0]</comment>
        </bits>
      </reg>
      <reg name="pix_num_l_reg" protect="rw">
        <bits access="rw" name="pix_num_l_reg" pos="6:0" rst="0x50">
          <comment>Pix_num=[pix_num_l_reg[6:0], 3d0]</comment>
        </bits>
        <bits access="rw" name="csi_mon_reg" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="v_dummy" protect="rw">
        <bits access="rw" name="vbot_dummy_reg" pos="3:0" rst="0x2">
          <comment>HsyncNvsync</comment>
        </bits>
        <bits access="rw" name="vtop_dummy_reg" pos="7:4" rst="0x0">
          <comment>Mvsync
                  top_dummy&gt;16, vtop_dummy=top_dummy-[7:4]</comment>
        </bits>
      </reg>
      <reg name="scg" protect="rw">
        <bits access="rw" name="kukl_sel" pos="0" rst="0x1">
          <comment>1blc[ku, kl]</comment>
        </bits>
        <bits access="rw" name="reg94_rd_sel" pos="1" rst="0x1">
          <comment>1:nexp[3:0]  0:mono_color</comment>
        </bits>
        <bits access="rw" name="bayer_out_sel" pos="2" rst="0x0">
          <comment>1: dpc_out  0: bayer_data</comment>
        </bits>
        <bits access="rw" name="csup_en" pos="3" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="y_gamma_en" pos="5:4" rst="0x3">
          <comment>1: enable 0: disable
                  y_gamma_en = is_outdoor ? scg_reg[5] : scg_reg[4]</comment>
        </bits>
        <bits access="rw" name="yuv_sdi_en" pos="6" rst="0x1">
          <comment>1: SDI  0: BT.601</comment>
        </bits>
        <bits access="rw" name="reg92_rd_sel" pos="7" rst="0x0">
          <comment>1: [ae_ok, nexp_sel[1:0], awb_ok, exp[11:8]]
                  0: [ae_ok, 1b0, nexp_sel[1:0], awb_ok, exp[10:8]]
                     labview</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b0" protect="rw">
        <bits access="rw" name="y_gamma_b0" pos="7:0" rst="0x0">
          <comment>(0x00)0      (0x00)0     (0x00)0</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b1" protect="rw">
        <bits access="rw" name="y_gamma_b1" pos="7:0" rst="0x10">
          <comment>(0x13)19     (0x10)16    (0x08)8</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b2" protect="rw">
        <bits access="rw" name="y_gamma_b2" pos="7:0" rst="0x1c">
          <comment>(0x20)32     (0x1c)28    (0x10)16</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b4" protect="rw">
        <bits access="rw" name="y_gamma_b4" pos="7:0" rst="0x30">
          <comment>(0x36)54     (0x30)48    (0x20)32</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b6" protect="rw">
        <bits access="rw" name="y_gamma_b6" pos="7:0" rst="0x43">
          <comment>(0x49)73     (0x43)67    (0x30)48</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b8" protect="rw">
        <bits access="rw" name="y_gamma_b8" pos="7:0" rst="0x54">
          <comment>(0x5a)90     (0x54)84    (0x40)64</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b10" protect="rw">
        <bits access="rw" name="y_gamma_b10" pos="7:0" rst="0x65">
          <comment>(0x6b)107    (0x65)101   (0x50)80</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b12" protect="rw">
        <bits access="rw" name="y_gamma_b12" pos="7:0" rst="0x75">
          <comment>(0x7b)123    (0x75)117   (0x60)96</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b16" protect="rw">
        <bits access="rw" name="y_gamma_b16" pos="7:0" rst="0x93">
          <comment>RW(0x98)152    (0x93)147   (0x80)128</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b20" protect="rw">
        <bits access="rw" name="y_gamma_b20" pos="7:0" rst="0xb0">
          <comment>(0xb4)180    (0xb0)176   (0xa0)160</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b24" protect="rw">
        <bits access="rw" name="y_gamma_b24" pos="7:0" rst="0xcb">
          <comment>(0xce)206    (0xcb)203   (0xc0)192</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b28" protect="rw">
        <bits access="rw" name="y_gamma_b28" pos="7:0" rst="0xe6">
          <comment>(0xe7)231    (0xe6)230   (0xe0)224</comment>
        </bits>
      </reg>
      <reg name="y_gamma_b32" protect="rw">
        <bits access="rw" name="y_gamma_b32" pos="7:0" rst="0x0">
          <comment>0.75    0.8   1.0</comment>
        </bits>
      </reg>
      <reg name="r_awb_gain_in" protect="rw">
        <bits access="rw" name="r_awb_gain_in" pos="7:0" rst="0x40">
          <comment>r_gain_manual 2.6 format</comment>
        </bits>
      </reg>
      <reg name="g_awb_gain_in" protect="rw">
        <bits access="rw" name="g_awb_gain_in" pos="7:0" rst="0x40">
          <comment>g_gain_manual 2.6 format</comment>
        </bits>
      </reg>
      <reg name="b_awb_gain_in" protect="rw">
        <bits access="rw" name="b_awb_gain_in" pos="7:0" rst="0x40">
          <comment>b_gain_manual 2.6 format</comment>
        </bits>
      </reg>
      <reg name="r_drc_gain_in" protect="rw">
        <bits access="rw" name="r_drc_gain_in" pos="7:0" rst="0x40">
          <comment>2.6 format</comment>
        </bits>
      </reg>
      <reg name="gr_drc_gain_in" protect="rw">
        <bits access="rw" name="gr_drc_gain_in" pos="7:0" rst="0x40">
          <comment>2.6 format</comment>
        </bits>
      </reg>
      <reg name="gb_drc_gain_in" protect="rw">
        <bits access="rw" name="gb_drc_gain_in" pos="7:0" rst="0x40">
          <comment>2.6 format</comment>
        </bits>
      </reg>
      <reg name="b_drc_gain_in" protect="rw">
        <bits access="rw" name="b_drc_gain_in" pos="7:0" rst="0x40">
          <comment>2.6 format</comment>
        </bits>
      </reg>
      <reg name="ae_ctrl" protect="rw">
        <bits access="rw" name="ana_gain_in" pos="5:0" rst="0x8">
          <comment/>
        </bits>
        <bits access="rw" name="ae_update_en" pos="6" rst="0x1">
          <comment>also update cc_type,gamma_type,is_outdoor</comment>
        </bits>
        <bits access="rw" name="ae_en" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="ae_ctrl2" protect="rw">
        <bits access="rw" name=" awb_adj_sel" pos="1:0" rst="0x1">
          <comment>00: AWB
                  01: AWB
                  10: yaveAWB
                  11: nexpAWB</comment>
        </bits>
        <bits access="rw" name="gap_ae" pos="2" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="gap_be" pos="3" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="ae_action_period" pos="6:4" rst="0x4">
          <comment/>
        </bits>
        <bits access="rw" name="yave_mon_sel" pos="7" rst="0x0">
          <comment>1: mon ae index  0:mon awb_debug</comment>
        </bits>
      </reg>
      <reg name="ae_ctrl3" protect="rw">
        <bits access="rw" name="yave_use_mean" pos="1:0" rst="0x3">
          <comment>0yave        1yave
                  2yave    3yave</comment>
        </bits>
        <bits access="rw" name="yave_diff_thr_reg" pos="3:2" rst="0x1">
          <comment>07/0f/17/1f Yave</comment>
        </bits>
        <bits access="rw" name="yave_sel" pos="5:4" rst="0x2">
          <comment>00: y2ave x1.0    01: y2ave x1.5
                  10: y3ave x1.0    11: y3ave x1.5</comment>
        </bits>
        <bits access="rw" name="yave_plus_bh_mode" pos="6" rst="0x1">
          <comment>1:plus bh   0: only yave</comment>
        </bits>
        <bits access="rw" name="ywave_plus_bh_mode" pos="7" rst="0x1">
          <comment>1:plus bh   0: only ywave</comment>
        </bits>
      </reg>
      <reg name="ae_ctrl4" protect="rw">
        <bits access="rw" name="ae_hist_big_en" pos="0" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="ae_hist_too_big_en" pos="1" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="hist_ofst0" pos="3:2" rst="0x2">
          <comment/>
        </bits>
        <bits access="rw" name="index_ofst0" pos="5:4" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="index_ofst1" pos="7:6" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="ae_win_start" protect="rw">
        <bits access="rw" name="pcnt_left" pos="3:0" rst="0x2">
          <comment>pcnt_left =[ae_win_start_reg[3:0] ,1'd0]</comment>
        </bits>
        <bits access="rw" name="lcnt_top" pos="7:4" rst="0x2">
          <comment>lcnt_top =[ae_win_start_reg[7:4] ,1'd0]</comment>
        </bits>
      </reg>
      <reg name="ae_win_width" protect="rw">
        <bits access="rw" name="ae_win_width" pos="7:0" rst="0x95">
          <comment>ae(yave) win_width = [ae_win_width[7:0], 2'd0]</comment>
        </bits>
      </reg>
      <reg name="ae_win_height" protect="rw">
        <bits access="rw" name="ae_win_height" pos="7:0" rst="0xdc">
          <comment>ae(yave) ae_win_height = [ae_win_height[7:0], 1'd0]</comment>
        </bits>
      </reg>
      <reg name="exp_init" protect="rw">
        <bits access="rw" name="exp_init" pos="7:0" rst="0x0">
          <comment>exp[7:0](ae_enMCUexp_init[6:0]indexae)</comment>
        </bits>
      </reg>
      <reg name="exp_ceil_init" protect="rw">
        <bits access="rw" name="exp_ceil_init" pos="3:0" rst="0x1">
          <comment>exp[11:8]</comment>
        </bits>
      </reg>
      <reg name="ae_exp_1e" protect="rw">
        <bits access="rw" name="ae_exp_1e" pos="7:0" rst="0x4a">
          <comment>10msexp</comment>
        </bits>
      </reg>
      <reg name="ae_diff_thr" protect="rw">
        <bits access="rw" name="thr2_dark" pos="3:0" rst="0x8">
          <comment>(ytarget)
                  THR_dark(reg41)
                  THR22index1
                  THR24index2
                  THR26index4+ofst0
                  THR28index8+ofst1
                                    index16</comment>
        </bits>
        <bits access="rw" name="thr2_bright" pos="7:4" rst="0x8">
          <comment>(ytarget)
                  THR_bright(reg41)
                  THR22index1
                  THR24index2
                  THR26index4+ofst0
                  THR28index8+ofst1
                                    index16</comment>
        </bits>
      </reg>
      <reg name="ae_bh_sel" protect="rw">
        <bits access="rw" name="bh_factor_indoor" pos="2:0" rst="0x3">
          <comment/>
        </bits>
        <bits access="rw" name="bh_factor_outdoor" pos="5:3" rst="0x2">
          <comment>Bh = Bh_mean * bh_factor /8
                  bh_factor = is_outdoor? bh_factor_outdoor : bh_factor_indoor</comment>
        </bits>
        <bits access="rw" name="bh_mean_sel" pos="7:6" rst="0x2">
          <comment>00:  curr frame     01:  2 frame ave
                  10:  3 frame ave    11:  4 frame ave</comment>
        </bits>
      </reg>
      <reg name="awb_ctrl" protect="rw">
        <bits access="rw" name="awb_sw_mon_en" pos="0" rst="0x0">
          <comment>awb_mon_out[7:0][cbsum_abs_eq, crsum_abs_eq]SWAWB</comment>
        </bits>
        <bits access="rw" name="fast_2x" pos="1" rst="0x0">
          <comment>2.0xr/b</comment>
        </bits>
        <bits access="rw" name="fast_4x" pos="2" rst="0x0">
          <comment>4.0xr/b</comment>
        </bits>
        <bits access="rw" name="awb_action_period" pos="5:3" rst="0x4">
          <comment>0: 1frame  or 2frame</comment>
        </bits>
        <bits access="rw" name="awb_update_en" pos="6" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="awb_en" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="awb_ctrl2" protect="rw">
        <bits access="rw" name="awb_mon_sel" pos="2:0" rst="0x0">
          <comment>[  2]  0:readback blc  1: readback awb
                  [1:0]  0: crsum_abs    1:cbsum_abs
                         2: vld_cnt      3:awb_idx_lmax and max</comment>
        </bits>
        <bits access="rw" name="awb_vld_sel" pos="3" rst="0x0">
          <comment>AWB</comment>
        </bits>
        <bits access="rw" name="awb_vld_mode" pos="6:4" rst="0x0">
          <comment>3'd0:awb_vld=vld_max||(vld_lmax and awb_ratio_lmax);
                  3'd1: awb_vld = awb_vld1;
                  3'd2: awb_vld = awb_vld2;
                  3'd3: awb_vld = awb_vld3;
                  3'd4: awb_vld = awb_vld4;
                  3'd5: awb_vld = awb_vld5;
                  3'd6: awb_vld =!skin_vld;
                  3'd7: awb_vld = awb_vld1|awb_vld2|awb_vld3| awb_vld4 | awb_vld5;</comment>
        </bits>
        <bits access="ro" name="awb_adj" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="awb_y_max" protect="rw">
        <bits access="rw" name="awb_y_max" pos="7:0" rst="0xf0">
          <comment>Y  Y_maxAWB</comment>
        </bits>
      </reg>
      <reg name="awb_stop" protect="rw">
        <bits access="rw" name="awb_stop_cb_neg_level" pos="1:0" rst="0x1">
          <comment>Levelawb_stop</comment>
        </bits>
        <bits access="rw" name="awb_stop_cb_pos_level" pos="3:2" rst="0x1">
          <comment>Levelawb_stop</comment>
        </bits>
        <bits access="rw" name="awb_stop_cr_neg_level" pos="5:4" rst="0x1">
          <comment>Levelawb_stop</comment>
        </bits>
        <bits access="rw" name="awb_stop_cr_pos_level" pos="7:6" rst="0x1">
          <comment>Levelawb_stop</comment>
        </bits>
      </reg>
      <reg name="awb_algo" protect="rw">
        <bits access="rw" name="awb_algo" pos="7:0" rst="0x80">
          <comment>[7:0]awb_algo_thr
                  Y &gt; cr_abs+cb_abs+awb_algo_reg
                  //</comment>
        </bits>
      </reg>
      <reg name="awb_ctrl3" protect="rw">
        <bits access="rw" name="cr_ofst_lt1x" pos="0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="cr_ofst_gt1x" pos="1" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="cb_ofst_lt1x" pos="2" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="cb_ofst_gt1x" pos="3" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="awb_sum_vld_sel" pos="4" rst="0x0">
          <comment>0: (vld_cntawb_vld_thr)
                  1: (vld_cntawb_vld_thr)and(crsum_absawb_vld_thr)and(cbsum_absawb_vld_thr)</comment>
        </bits>
        <bits access="rw" name="awb_stop_sel_reg" pos="5" rst="0x1">
          <comment>0: awb_stopcb/cr
                  1:</comment>
        </bits>
        <bits access="rw" name="awb_skin_sel" pos="6" rst="0x0">
          <comment>0: use CTD block to detect skin
                  1: use cb,cr to detect skin</comment>
        </bits>
        <bits access="rw" name="awb_algo_mode" pos="7" rst="0x1">
          <comment>0: cb+cr
                  1: cb/cr</comment>
        </bits>
      </reg>
      <reg name="awb_ctrl4" protect="rw">
        <bits access="rw" name="awb_ctrl4" pos="7:0" rst="0x10">
          <comment>awb_vld_thr = [awb_ctrl4[7:0], 4'hf]</comment>
        </bits>
      </reg>
      <reg name="dig_gain_in" protect="rw">
        <bits access="rw" name="dig_gain_in" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="y_init_thr" protect="rw">
        <bits access="rw" name="y_init_mode" pos="0" rst="0x1">
          <comment>1:    0</comment>
        </bits>
        <bits access="rw" name="y_low_en" pos="1" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="y_high_en" pos="2" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="y_low_thr" pos="7:3" rst="0x8">
          <comment>y_low_thr = [1h0, y_thr_reg[7:3], 2'h0]
                  y_high_thr = ~y_low_thr</comment>
        </bits>
      </reg>
      <reg name="y_ave_target" protect="rw">
        <bits access="rw" name="y_ave_target" pos="7:0" rst="0x78">
          <comment/>
        </bits>
      </reg>
      <reg name="y_lmt_offset" protect="rw">
        <bits access="rw" name="y_low_limit" pos="2:0" rst="0x5">
          <comment>Only for awb_adj, yaveAWB
                  y_low_limit = y_ave_target - [y_lmt_offset_reg[2:0],4'd0]</comment>
        </bits>
        <bits access="rw" name="y_lmt_ofst" pos="3" rst="0x0">
          <comment>not used here</comment>
        </bits>
        <bits access="rw" name="y_high_limit" pos="6:4" rst="0x6">
          <comment>Only for awb_adj, yaveAWB
                  y_high_limit = y_ave_target+ [y_lmt_offset_reg[6:4],4'd0]</comment>
        </bits>
      </reg>
      <reg name="again_sel_th2" protect="rw">
        <bits access="rw" name="ynr_gain_low_th" pos="2:0" rst="0x4">
          <comment>nexp=low_th</comment>
        </bits>
        <bits access="rw" name="again_sel_th2" pos="3" rst="0x0">
          <comment>not used here</comment>
        </bits>
        <bits access="rw" name="ynr_gain_hi_th" pos="6:4" rst="0x3">
          <comment>nexp&gt;(8+high_th)</comment>
        </bits>
      </reg>
      <reg name="yave_target_chg1" protect="rw">
        <bits access="rw" name="yave_target_ofst_l" pos="3:0" rst="0x4">
          <comment>yave_target (yave_target0)</comment>
        </bits>
        <bits access="rw" name="yave_target_ofst_h" pos="7:4" rst="0x8">
          <comment>yave_target (yave_target0)</comment>
        </bits>
      </reg>
      <reg name="image_eff_reg" protect="rw">
        <bits access="rw" name="grey_en" pos="0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="sepia_en" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="negative_en" pos="2" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="color_bar_en" pos="3" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="image_eff_rsvd" pos="4" rst="0x0">
          <comment>not used here</comment>
        </bits>
        <bits access="rw" name="reg93_sel" pos="5" rst="0x0">
          <comment>1reg93vbright_hist</comment>
        </bits>
        <bits access="rw" name="reg94_sel" pos="6" rst="0x0">
          <comment>1reg94vdark_hist</comment>
        </bits>
        <bits access="rw" name="sharp_mon" pos="7" rst="0x0">
          <comment>display edge pixel for sharpness</comment>
        </bits>
      </reg>
      <reg name="ywave_out" protect="ro">
        <bits access="ro" name="ywave_out" pos="7:0" rst="0x0">
          <comment>Ywave+bhist histYwave</comment>
        </bits>
      </reg>
      <reg name="ae_bright_hist" protect="ro">
        <bits access="ro" name="ae_bright_hist" pos="7:0" rst="0x0">
          <comment>bright hist</comment>
        </bits>
      </reg>
      <reg name="yave_out" protect="ro">
        <bits access="ro" name="yave_out" pos="7:0" rst="0x0">
          <comment>Yave+bhisthistYave</comment>
        </bits>
      </reg>
      <reg name="exp_out" protect="ro">
        <bits access="ro" name="exp_out" pos="7:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="misc_out" protect="ro">
        <bits access="ro" name="exp_out_h" pos="2:0" rst="0x1">
          <comment>exp_out[10:8]</comment>
        </bits>
        <bits access="ro" name="awb_ok" pos="3" rst="0x0">
          <comment/>
        </bits>
        <bits access="ro" name="nexp_sel" pos="5:4" rst="0x0">
          <comment>nexp_selbnr/dpc/int_dif</comment>
        </bits>
        <bits access="ro" name="fixed_0" pos="6" rst="0x0">
          <comment/>
        </bits>
        <bits access="ro" name="ae_ok" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="awb_debug_out" protect="ro">
        <bits access="ro" name="awb_crgt" pos="1:0" rst="0x0">
          <comment>00: cr_lt_1x     01: cr_gt_1x
                  10: cr_gt_2x    11: cr_gt_4x</comment>
        </bits>
        <bits access="ro" name="awb_cbgt" pos="3:2" rst="0x0">
          <comment>00: cb_lt_1x    01: cb_gt_1x
                  10: cb_gt_2x    11: cb_gt_4x</comment>
        </bits>
        <bits access="ro" name="awb_crsum_sign" pos="4" rst="0x0">
          <comment>0:crsum   (5R  B+4G)
                  1:crsum   (5R  B+4G)</comment>
        </bits>
        <bits access="ro" name="awb_cbsum_sign" pos="5" rst="0x0">
          <comment>0:cbsum   (3B  R+2G)
                  1:cbsum   (3B  R+2G)</comment>
        </bits>
        <bits access="ro" name="awb_cbcr" pos="6" rst="0x0">
          <comment>0: crsum_abs  cbsum_abs  (crsum)
                  1: crsum_abs  cbsum_abs  (cbsum)</comment>
        </bits>
        <bits access="ro" name="awb_sum_vld" pos="7" rst="0x0">
          <comment>ae_index
                  Note: regd[5]? ae_vbright_hist :
                  reg75[7]? ae_index[6:0] : awb_debug;</comment>
        </bits>
      </reg>
      <reg name="mono_color" protect="ro">
        <bits access="ro" name="mono_color" pos="7:0" rst="0x0">
          <comment>YUVnexp vdark_hist
                  Note:  regd[6]? ae_vdark_hist :
                         reg5F[1]? nexp[3:0] : mono_color</comment>
        </bits>
      </reg>
      <reg name="r_awb_gain" protect="ro">
        <bits access="ro" name="r_awb_gain" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="b_awb_gain" protect="ro">
        <bits access="ro" name="b_awb_gain" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="misc_status" protect="ro">
        <bits access="ro" name="ana_gain_out" pos="5:0" rst="0x0">
          <comment/>
        </bits>
        <bits access="ro" name="cc_type" pos="6" rst="0x0">
          <comment/>
        </bits>
        <bits access="ro" name="is_outdoor" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="yave_contr" protect="ro">
        <bits access="ro" name="yave_contr" pos="7:0" rst="0x0">
          <comment>yavehist
                  Vbh_sel[1]? Yave_contr_reg :
                  Vbh_sel[0]? Yave_target_RO_reg : ae_dark_hist
                  NoteVbh_sel[1:0] = reg3d[7:6]</comment>
        </bits>
      </reg>
      <reg name="gamma_type" protect="rw">
        <bits access="rw" name="gamma_type_mode" pos="2:0" rst="0x2">
          <comment>3d0:  gamma_type=0
                  3d1:  gamma_type=1
                  3d2:  gamma_type=is_outdoor
                  3d3:  gamma_type=ana_gain&gt;=gamma_gain_th
                  default:gamma_type=gamma_type_sw</comment>
        </bits>
        <bits access="rw" name="gamma_gain_hi_th" pos="5:3" rst="0x4">
          <comment>nexp&gt;(8+high_th)</comment>
        </bits>
        <bits access="rw" name="vgas" pos="7:6" rst="0x3">
          <comment>00:QVGA  240x320   01:QVGA 320x240
                  10:CIF   352x288   11:VGA  640x480</comment>
        </bits>
      </reg>
      <reg name="blc_line" protect="rw">
        <bits access="rw" name="blc_line" pos="7:0" rst="0x0">
          <comment>line_sel = [line_init_H, blc_line_reg[7:0]]</comment>
        </bits>
      </reg>
      <reg name="lsc_xx" protect="rw">
        <bits access="rw" name="x_low" pos="3:0" rst="0x8">
          <comment>lsc gain@</comment>
        </bits>
        <bits access="rw" name="x_high" pos="7:4" rst="0x8">
          <comment>lsc gain@</comment>
        </bits>
      </reg>
      <reg name="lsc_blc_gain_th" protect="rw">
        <bits access="rw" name="lsc_gain_low_th" pos="2:0" rst="0x4">
          <comment>nexp=low_th</comment>
        </bits>
        <bits access="rw" name="lsc_gain_hi_th" pos="5:3" rst="0x3">
          <comment>nexp&gt;(8+high_th)</comment>
        </bits>
        <bits access="rw" name="csup_gain_low_th" pos="7:6" rst="0x0">
          <comment>low_th = [csup_gain_low_th_H, [7:6]](nexp=low_th)</comment>
        </bits>
      </reg>
      <reg name="blc_ctrl" protect="rw">
        <bits access="rw" name="blc_out_mode" pos="1:0" rst="0x0">
          <comment>2'd0: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_01]
                  2'd1: [blc_out0_reg,blc_out1_reg] = [blc_10, blc_11]
                  2'd2: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_10]
                  2'd3: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_11]</comment>
        </bits>
        <bits access="rw" name="line_init_h" pos="2" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="blc_ofst_sign" pos="3" rst="0x0">
          <comment>0: plus   1: minus</comment>
        </bits>
        <bits access="rw" name="blc_mode" pos="5:4" rst="0x0">
          <comment>00: 1frame           01: 2frame ave
                  10: 3frame ave       11: 4frame ave</comment>
        </bits>
        <bits access="rw" name="blc_sel" pos="6" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="blc_en" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="blc_init" protect="rw">
        <bits access="rw" name="blc00_ofst" pos="3:0" rst="0x0">
          <comment>blc00_ofst =[blc_init_reg[3:0] , 1'b0]</comment>
        </bits>
        <bits access="rw" name="blc01_ofst" pos="7:4" rst="0x0">
          <comment>blc01_ofst =[blc_init_reg[7:4] , 1'b0]</comment>
        </bits>
      </reg>
      <reg name="blc_offset" protect="rw">
        <bits access="rw" name="blc10_ofst" pos="3:0" rst="0x0">
          <comment>blc10_ofst =[blc_offset_reg[3:0] , 1'b0]</comment>
        </bits>
        <bits access="rw" name="blc11_ofst" pos="7:4" rst="0x0">
          <comment>blc11_ofst =[blc_offset_reg[7:4] , 1'b0]</comment>
        </bits>
      </reg>
      <reg name="blc_thr" protect="rw">
        <bits access="rw" name="blc_thr" pos="5:0" rst="0x3e">
          <comment>High limit of black level pixel
                  blcofst</comment>
        </bits>
      </reg>
      <reg name="lsc_xy_cent" protect="rw">
        <bits access="rw" name="y_cent" pos="3:0" rst="0x4">
          <comment>y_cent=[3:0]+240</comment>
        </bits>
        <bits access="rw" name="x_cent" pos="7:4" rst="0x4">
          <comment>x_cent=[7:4]+320</comment>
        </bits>
      </reg>
      <reg name="cnr_dif_thr" protect="rw">
        <bits access="rw" name="cnr_v_en" pos="0" rst="0x1">
          <comment>CNR</comment>
        </bits>
        <bits access="rw" name="cnr_h_en" pos="1" rst="0x1">
          <comment>CNR</comment>
        </bits>
        <bits access="rw" name="vcnr_sel" pos="2" rst="0x1">
          <comment>1:  0:</comment>
        </bits>
        <bits access="rw" name="edge_mon" pos="3" rst="0x0">
          <comment>edge monitor</comment>
        </bits>
        <bits access="rw" name="awb_skin_mode" pos="6:4" rst="0x0">
          <comment>3d0: never skip           3d1: skip 2/8 skin point
                  3d2: skip 3/8 skin point  3d3: skip 4/8 skin point
                  3d4: skip 5/8 skin point  3d5: skip 6/8 skin point
                  3d6: skip 7/8 skin point  3d7: skip 8/8 skin point</comment>
        </bits>
        <bits access="ro" name="gamma_type" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="cnr_thr" protect="rw">
        <bits access="rw" name="cnr_thr_v" pos="2:0" rst="0x0">
          <comment>cnr_thr_v  = [cnr_thr[2:0], 2'd3]</comment>
        </bits>
        <bits access="rw" name="edge_en_v" pos="3" rst="0x0">
          <comment>enable</comment>
        </bits>
        <bits access="rw" name="cnr_thr_h" pos="6:4" rst="0x0">
          <comment>cnr_thr_h  = [cnr_thr[6:4], 2'd3]</comment>
        </bits>
        <bits access="rw" name="edge_en_h" pos="7" rst="0x0">
          <comment>enable</comment>
        </bits>
      </reg>
      <reg name="gamma_ctrl" protect="rw">
        <bits access="rw" name="gamma_p_id " pos="0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="gamma_l_id " pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="gamma_en_non_outdoor" pos="2" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="gamma_en_outdoor" pos="3" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="lsc_p_id" pos="4" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="lsc_l_id" pos="5" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="lsc_en_non_outdoor" pos="6" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="lsc_en_outdoor" pos="7" rst="0x1">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b0" protect="rw">
        <bits access="rw" name="bayer_gamma_b0" pos="7:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b1" protect="rw">
        <bits access="rw" name="bayer_gamma_b1" pos="7:0" rst="0x9">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b2" protect="rw">
        <bits access="rw" name="bayer_gamma_b2" pos="7:0" rst="0x10">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b3" protect="rw">
        <bits access="rw" name="bayer_gamma_b3" pos="7:0" rst="0x16">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b4" protect="rw">
        <bits access="rw" name="bayer_gamma_b4" pos="7:0" rst="0x1c">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b6" protect="rw">
        <bits access="rw" name="bayer_gamma_b6" pos="7:0" rst="0x27">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b8" protect="rw">
        <bits access="rw" name="bayer_gamma_b8" pos="7:0" rst="0x30">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b10" protect="rw">
        <bits access="rw" name="bayer_gamma_b10" pos="7:0" rst="0x3a">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b12" protect="rw">
        <bits access="rw" name="bayer_gamma_b12" pos="7:0" rst="0x43">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b16" protect="rw">
        <bits access="rw" name="bayer_gamma_b16" pos="7:0" rst="0x54">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b20" protect="rw">
        <bits access="rw" name="bayer_gamma_b20" pos="7:0" rst="0x65">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b24" protect="rw">
        <bits access="rw" name="bayer_gamma_b24" pos="7:0" rst="0x75">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b28" protect="rw">
        <bits access="rw" name="bayer_gamma_b28" pos="7:0" rst="0x84">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b32" protect="rw">
        <bits access="rw" name="bayer_gamma_b32" pos="7:0" rst="0x93">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b36" protect="rw">
        <bits access="rw" name="bayer_gamma_b36" pos="7:0" rst="0xa1">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b40" protect="rw">
        <bits access="rw" name="bayer_gamma_b40" pos="7:0" rst="0xb0">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b48" protect="rw">
        <bits access="rw" name="bayer_gamma_b48" pos="7:0" rst="0xcb">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b56" protect="rw">
        <bits access="rw" name="bayer_gamma_b56" pos="7:0" rst="0xe6">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma_b64" protect="rw">
        <bits access="rw" name="bayer_gamma_b64" pos="7:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="blc_out0" protect="ro">
        <bits access="ro" name="blc_out0" pos="7:0" rst="0x0">
          <comment>~awb_mon_sel? blc_out0_reg : kukl_sel ? kl : awb_mon_out[7:0]</comment>
        </bits>
      </reg>
      <reg name="blc_out1" protect="ro">
        <bits access="ro" name="blc_out1" pos="7:0" rst="0x0">
          <comment>~awb_mon_sel? blc_out1_reg : kukl_sel ? ku : awb_mon_out[15:8]
                   Note: awb_mon_sel = reg1[2] Kukl_sel    = reg5F[0]</comment>
        </bits>
      </reg>
      <reg name="dpc_ctrl_0" protect="rw">
        <bits access="rw" name="dpc_on" pos="0" rst="0x1">
          <comment>dpc on</comment>
        </bits>
        <bits access="rw" name="adp_med_sel" pos="1" rst="0x0">
          <comment>1: median  0:adp_median
                  sel=(nexp[3:0]&gt;dpc_ctrl0[3:2])? 1 : dpc_ctrl0[1]
                  This adp_med is used in int_dif_data and nrf_data_out</comment>
        </bits>
        <bits access="rw" name="ana_gain_cmp" pos="3:2" rst="0x2">
          <comment/>
        </bits>
        <bits access="rw" name="rsvd" pos="4" rst="0x0">
          <comment>not used here</comment>
        </bits>
        <bits access="rw" name="nrf_gaus_sel" pos="5" rst="0x0">
          <comment>1:gausian filter  0:median filter</comment>
        </bits>
        <bits access="rw" name="bayer_nr_on" pos="6" rst="0x0">
          <comment>bayer nr on</comment>
        </bits>
        <bits access="rw" name="cc_on" pos="7" rst="0x0">
          <comment>cc on</comment>
        </bits>
      </reg>
      <reg name="dpc_ctrl_1" protect="rw">
        <bits access="rw" name="int_flg_cmp" pos="1:0" rst="0x1">
          <comment>00: always not meet
          01: all round point must meet
          10: can be one except point
          11: can be two except point</comment>
        </bits>
        <bits access="rw" name="abs_sign_all_cmp" pos="3:2" rst="0x3">
          <comment>00: can be three sign diff with other
            01: can be two sign diff with other
            10: can be one sign diff with other
            11: 8 same sign</comment>
        </bits>
        <bits access="rw" name="int_dif_sel" pos="4" rst="0x0">
          <comment>1: gausian filter  0:median filter</comment>
        </bits>
      </reg>
      <reg name="y_thr_lo" protect="rw">
        <bits access="rw" name="y_thr_lo" pos="7:0" rst="0x12">
          <comment>Y_thr  @</comment>
        </bits>
      </reg>
      <reg name="y_thr_mid" protect="rw">
        <bits access="rw" name="y_thr_mid" pos="7:0" rst="0x18">
          <comment>Y_thr  @mid</comment>
        </bits>
      </reg>
      <reg name="y_thr_hi" protect="rw">
        <bits access="rw" name="y_thr_hi" pos="7:0" rst="0x18">
          <comment>Y_thr  @</comment>
        </bits>
      </reg>
      <reg name="intp_cfa_hv" protect="rw">
        <bits access="rw" name="cfa_v_thr_l" pos="2:0" rst="0x0">
          <comment>cfa_v_thr[2:0]</comment>
        </bits>
        <bits access="rw" name="rsvd1" pos="3" rst="0x0">
          <comment>not used here</comment>
        </bits>
        <bits access="rw" name="cfa_h_thr_l" pos="6:4" rst="0x0">
          <comment>cfa_h_thr[2:0]</comment>
        </bits>
        <bits access="rw" name="rsvd2" pos="7" rst="0x0">
          <comment>not used here</comment>
        </bits>
      </reg>
      <reg name="manual_adj" protect="rw">
        <bits access="rw" name="b_gain_adj" pos="0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="g_gain_adj" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="r_gain_adj" pos="2" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="ana_gain_adj" pos="3" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="adj_direction" pos="4" rst="0x0">
          <comment>0: inc  1:dec</comment>
        </bits>
        <bits access="rw" name="index_manual_adj" pos="5" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="in_capture_awb" pos="6" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="in_capture_ae" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="dpc_int_thr_lo" protect="rw">
        <bits access="rw" name="dpc_int_thr_lo" pos="7:0" rst="0x10">
          <comment/>
        </bits>
      </reg>
      <reg name="dpc_int_thr_hi" protect="rw">
        <bits access="rw" name="dpc_int_thr_hi" pos="7:0" rst="0x30">
          <comment/>
        </bits>
      </reg>
      <reg name="again_sel_th1" protect="rw">
        <bits access="rw" name="bnr_gain_low_th" pos="2:0" rst="0x4">
          <comment>nexp=low_th @bnr/dpc/int_dif/sharp/cnr</comment>
        </bits>
        <bits access="rw" name="again_sel_th1_rsvd" pos="3" rst="0x0">
          <comment>not used here</comment>
        </bits>
        <bits access="rw" name="bnr_gain_hi_th" pos="6:4" rst="0x3">
          <comment>nexp&gt;(8+high_th) @bnr/dpc/int_dif/sharp/cnr</comment>
        </bits>
      </reg>
      <reg name="dpc_nr_lf_str_lo" protect="rw">
        <bits access="rw" name="dpc_nr_lf_str_lo" pos="7:0" rst="0x80">
          <comment>bnr low frequency str @Low gain @
                  (ff)</comment>
        </bits>
      </reg>
      <reg name="dpc_nr_hf_str_lo" protect="rw">
        <bits access="rw" name="dpc_nr_hf_str_lo" pos="7:0" rst="0x10">
          <comment>bnr high frequency str @Low gain
                  (ff)</comment>
        </bits>
      </reg>
      <reg name="dpc_nr_area_thr_lo" protect="rw">
        <bits access="rw" name="dpc_nr_area_thr_lo" pos="7:0" rst="0x80">
          <comment>4.4 format, 16x ~ 1/16x @Low gain
                  HF</comment>
        </bits>
      </reg>
      <reg name="dpc_nr_lf_str_mid" protect="rw">
        <bits access="rw" name="dpc_nr_lf_str_mid" pos="7:0" rst="0xa0">
          <comment>bnr low frequency str @Mid gain
                  (ff)</comment>
        </bits>
      </reg>
      <reg name="dpc_nr_hf_str_mid" protect="rw">
        <bits access="rw" name="dpc_nr_hf_str_mid" pos="7:0" rst="0x20">
          <comment>bnr high frequency str @Mid gain
                  (ff)</comment>
        </bits>
      </reg>
      <reg name="dpc_nr_area_thr_mid" protect="rw">
        <bits access="rw" name="dpc_nr_area_thr_mid" pos="7:0" rst="0x80">
          <comment>4.4 format, 16x ~ 1/16x @Mid gain
                  HF</comment>
        </bits>
      </reg>
      <reg name="dpc_nr_lf_str_hi" protect="rw">
        <bits access="rw" name="dpc_nr_lf_str_hi" pos="7:0" rst="0xc0">
          <comment>bnr low frequency str @high gain @
                  (ff)</comment>
        </bits>
      </reg>
      <reg name="dpc_nr_hf_str_hi" protect="rw">
        <bits access="rw" name="dpc_nr_hf_str_hi" pos="7:0" rst="0x40">
          <comment>bnr high frequency str @high gain
                  (ff)</comment>
        </bits>
      </reg>
      <reg name="dpc_nr_area_thr_hi" protect="rw">
        <bits access="rw" name="dpc_nr_area_thr_hi" pos="7:0" rst="0x80">
          <comment>4.4 format, 16x ~ 1/16x @high gain
                  HF</comment>
        </bits>
      </reg>
      <reg name="intp_ctrl" protect="rw">
        <bits access="rw" name="pid_inv_en" pos="0" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="lid_inv_en" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="gfilter_en" pos="2" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="gfilter3_en" pos="3" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="gfliter5_en" pos="4" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="sort_sel" pos="7:5" rst="0x3">
          <comment>0: 9        1:7
                  2: 5  3:3
                  4: median              5: adp_median</comment>
        </bits>
      </reg>
      <reg name="intp_cfa_h_thr" protect="rw">
        <bits access="rw" name="intp_cfa_h_thr" pos="7:0" rst="0x0">
          <comment>cfa_h_thr=[intp_cfa_h_thr[7:0], intp_cfa_hv[6:4]]</comment>
        </bits>
      </reg>
      <reg name="intp_cfa_v_thr" protect="rw">
        <bits access="rw" name="intp_cfa_v_thr" pos="7:0" rst="0x0">
          <comment>cfa_v_thr=[intp_cfa_v_thr[7:0], intp_cfa_hv[2:0]]</comment>
        </bits>
      </reg>
      <reg name="intp_grgb_sel_lmt" protect="rw">
        <bits access="rw" name="intp_grgb_sel_lmt" pos="7:0" rst="0x8">
          <comment/>
        </bits>
      </reg>
      <reg name="intp_gf_lmt_thr" protect="rw">
        <bits access="rw" name="intp_gf_lmt_thr" pos="7:0" rst="0x83">
          <comment>gf_lmt_thr=[3d0, intp_gf_lmt_thr_reg]</comment>
        </bits>
      </reg>
      <reg name="cc_r_offset" protect="rw">
        <bits access="rw" name="cc_r_offset" pos="7:0" rst="0x0">
          <comment>S7 format, before cc</comment>
        </bits>
      </reg>
      <reg name="cc_g_offset" protect="rw">
        <bits access="rw" name="cc_g_offset" pos="7:0" rst="0x0">
          <comment>S7 format, before cc</comment>
        </bits>
      </reg>
      <reg name="cc_b_offset" protect="rw">
        <bits access="rw" name="cc_b_offset" pos="7:0" rst="0x0">
          <comment>S7 format, before cc</comment>
        </bits>
      </reg>
      <reg name="cc_00" protect="rw">
        <bits access="rw" name="cc_00" pos="7:0" rst="0x58">
          <comment>S1.6 format, x1=64, cc00+cc01+cc02=1</comment>
        </bits>
      </reg>
      <reg name="cc_01" protect="rw">
        <bits access="rw" name="cc_01" pos="7:0" rst="0x90">
          <comment/>
        </bits>
      </reg>
      <reg name="cc_10" protect="rw">
        <bits access="rw" name="cc_10" pos="7:0" rst="0x88">
          <comment>S1.6 format, x1=64, cc10+cc11+cc12=1</comment>
        </bits>
      </reg>
      <reg name="cc_11" protect="rw">
        <bits access="rw" name="cc_11" pos="7:0" rst="0x50">
          <comment/>
        </bits>
      </reg>
      <reg name="cc_20" protect="rw">
        <bits access="rw" name="cc_20" pos="7:0" rst="0x88">
          <comment>S1.6 format, x1=64, cc20+cc21+cc22=1</comment>
        </bits>
      </reg>
      <reg name="cc_21" protect="rw">
        <bits access="rw" name="cc_21" pos="7:0" rst="0x90">
          <comment/>
        </bits>
      </reg>
      <reg name="cc_r_offset_post" protect="rw">
        <bits access="rw" name="cc_r_offset_post" pos="7:0" rst="0x0">
          <comment>S7 format, after cc</comment>
        </bits>
      </reg>
      <reg name="cc_g_offset_post" protect="rw">
        <bits access="rw" name="cc_g_offset_post" pos="7:0" rst="0x0">
          <comment>S7 format, after cc</comment>
        </bits>
      </reg>
      <reg name="cc_b_offset_post" protect="rw">
        <bits access="rw" name="cc_b_offset_post" pos="7:0" rst="0x0">
          <comment>S7 format, after cc</comment>
        </bits>
      </reg>
      <reg name="cc2_r_offset" protect="rw">
        <bits access="rw" name="cc2_r_offset" pos="7:0" rst="0x0">
          <comment>S7 format, before cc</comment>
        </bits>
      </reg>
      <reg name="cc2_g_offset" protect="rw">
        <bits access="rw" name="cc2_g_offset" pos="7:0" rst="0x0">
          <comment>S7 format, before cc</comment>
        </bits>
      </reg>
      <reg name="cc2_b_offset" protect="rw">
        <bits access="rw" name="cc2_b_offset" pos="7:0" rst="0x0">
          <comment>S7 format, before cc</comment>
        </bits>
      </reg>
      <reg name="cc2_00" protect="rw">
        <bits access="rw" name="cc2_00" pos="7:0" rst="0x40">
          <comment>S1.6 format, x1=64, cc00+cc01+cc02=1</comment>
        </bits>
      </reg>
      <reg name="cc2_01" protect="rw">
        <bits access="rw" name="cc2_01" pos="7:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="cc2_10" protect="rw">
        <bits access="rw" name="cc2_10" pos="7:0" rst="0x0">
          <comment>S1.6 format, x1=64, cc10+cc11+cc12=1</comment>
        </bits>
      </reg>
      <reg name="cc2_11" protect="rw">
        <bits access="rw" name="cc2_11" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="cc2_20" protect="rw">
        <bits access="rw" name="cc2_20" pos="7:0" rst="0x0">
          <comment>S1.6 format, x1=64, cc20+cc21+cc22=1</comment>
        </bits>
      </reg>
      <reg name="cc2_21" protect="rw">
        <bits access="rw" name="cc2_21" pos="7:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="sharp_lmt" protect="rw">
        <bits access="rw" name="sharp_lmt" pos="6:0" rst="0x7f">
          <comment>sharp data</comment>
        </bits>
        <bits access="rw" name="sharp_final_h" pos="7" rst="0x0">
          <comment>db/da/d9</comment>
        </bits>
      </reg>
      <reg name="sharp_mode" protect="rw">
        <bits access="rw" name="sharp_cmp_gap_lo" pos="3:0" rst="0x0">
          <comment>sharp_cmp&gt; (sharp_nr_area_thr[6:0]+sharp_cmp_gap)</comment>
        </bits>
        <bits access="rw" name="sharp_final" pos="5:4" rst="0x0">
          <comment>0: delay_df
                  1: delay_de
                  2: delay_dd
                  3: delay_dc</comment>
        </bits>
        <bits access="rw" name="sharp_sel" pos="6" rst="0x0">
          <comment>1:ppdif_sum
                  0:pp_dif (8)</comment>
        </bits>
        <bits access="rw" name="rgb_test_pattern" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="sharp_gain_str_lo" protect="rw">
        <bits access="rw" name="sharp_gain_str_lo" pos="7:0" rst="0x60">
          <comment>plus @Low gain (2.6 format)@</comment>
        </bits>
      </reg>
      <reg name="sharp_nr_area_thr_lo" protect="rw">
        <bits access="rw" name="sharp_nr_area_thr_lo" pos="6:0" rst="0x10">
          <comment>Sharp@Low gain
                  (edge)</comment>
        </bits>
      </reg>
      <reg name="sharp_gain_str_mid" protect="rw">
        <bits access="rw" name="sharp_gain_str_mid" pos="7:0" rst="0x60">
          <comment>plus @Mid gain (2.6 format)</comment>
        </bits>
      </reg>
      <reg name="sharp_nr_area_thr_mid" protect="rw">
        <bits access="rw" name="sharp_nr_area_thr_mid" pos="6:0" rst="0x10">
          <comment>Sharp@Mid gain
                  (edge)</comment>
        </bits>
      </reg>
      <reg name="sharp_gain_str_hi" protect="rw">
        <bits access="rw" name="sharp_gain_str_hi" pos="7:0" rst="0x60">
          <comment>plus @high gain (2.6 format)@</comment>
        </bits>
      </reg>
      <reg name="sharp_nr_area_thr_hi" protect="rw">
        <bits access="rw" name="sharp_nr_area_thr_hi" pos="6:0" rst="0x10">
          <comment>Sharp@high gain
                  (edge)</comment>
        </bits>
      </reg>
      <reg name="ynr_ctrl_reg" protect="rw">
        <bits access="rw" name="ynr_on" pos="0" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="ynr_edge_methode" pos="2:1" rst="0">
          <comment>(Ey)
        2d0:Ey_H/V/D1/D2
        2d1:
        2d2:
        2d3:</comment>
        </bits>
        <bits access="rw" name="sharp_on" pos="3" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="sharp_plus_mode" pos="5:4" rst="0">
          <comment>(sharpness)
                  00:
                  if(i_y_data8'ha0)       sharp_data = sharp_out[6:2];
                  else if(i_y_data8'h80)  sharp_data = sharp_out[6:1];
                  else                      sharp_data = sharp_out[6:0];
                  01: 0x80pixelsharpness
                  10: 0x90pixelsharpness
                  11:  No change</comment>
        </bits>
        <bits access="rw" name="y_ae_sel" pos="7:6" rst="0">
          <comment>AEYin
                  00:y=yuv_y
                  01:y=y_gamma   // after ygamma
                  10:y=luma_y_out // after y_luma
                  11:y=contr_y_out // after y_contr</comment>
        </bits>
      </reg>
      <reg name="ynr_lf_method_str" protect="rw">
        <bits access="rw" name="ynr_lf_method_str" pos="7:0" rst="0x00">
          <comment>GMYc</comment>
        </bits>
      </reg>
      <reg name="ynr_lf_str_lo" protect="rw">
        <bits access="rw" name="ynr_lf_str_lo" pos="7:0" rst="0x80">
          <comment>@low gain
                 GMYc128Ey</comment>
        </bits>
      </reg>
      <reg name="ynr_hf_str_lo" protect="rw">
        <bits access="rw" name="ynr_hf_str_lo" pos="7:0" rst="0x10">
          <comment>@low gain
               GMYc128Ey</comment>
        </bits>
      </reg>
      <reg name="ynr_area_thr_lo" protect="rw">
        <bits access="rw" name="ynr_area_thr_lo" pos="7:0" rst="0xc0">
          <comment>4.4 format, 16x ~ 1/16x @low gain
               HF</comment>
        </bits>
      </reg>
      <reg name="ynr_lf_str_mid" protect="rw">
        <bits access="rw" name="ynr_lf_str_mid" pos="7:0" rst="0xa0">
          <comment>@Mid gain
         GMYc128Ey</comment>
        </bits>
      </reg>
      <reg name="ynr_hf_str_mid" protect="rw">
        <bits access="rw" name="ynr_hf_str_mid" pos="7:0" rst="0x20">
          <comment>@Mid gain
        GMYc128Ey</comment>
        </bits>
      </reg>
      <reg name="ynr_area_thr_mid" protect="rw">
        <bits access="rw" name="ynr_area_thr_mid" pos="7:0" rst="0x80">
          <comment>4.4 format, 16x ~ 1/16x @Mid gain
                  HF</comment>
        </bits>
      </reg>
      <reg name="ynr_lf_str_hi" protect="rw">
        <bits access="rw" name="ynr_lf_str_hi" pos="7:0" rst="0xc0">
          <comment>@high gain
                GMYc128Ey</comment>
        </bits>
      </reg>
      <reg name="ynr_hf_str_hi" protect="rw">
        <bits access="rw" name="ynr_hf_str_hi" pos="7:0" rst="0x40">
          <comment>@high gain
               GMYc128Ey</comment>
        </bits>
      </reg>
      <reg name="ynr_area_thr_hi " protect="rw">
        <bits access="rw" name="ynr_area_thr_hi " pos="7:0" rst="0x20">
          <comment>4.4 format, 16x ~ 1/16x @high gain
                   HF</comment>
        </bits>
      </reg>
      <reg name="hue_sin_reg " protect="rw">
        <bits access="rw" name="hue_sin_reg " pos="7:0" rst="0x2c">
          <comment>sinx[7:0]=256*sin(x*pi/180)</comment>
        </bits>
      </reg>
      <reg name="hue_cos_reg" protect="rw">
        <bits access="rw" name="hue_cosx_reg" pos="6:0" rst="0x7c">
          <comment>cosx[7:0]=256*cos(x*pi/180)
                  cosx[7] fixed as 1, As abs(x) = pi/4</comment>
        </bits>
        <bits access="rw" name="sin_sign_reg" pos="7" rst="1">
          <comment>1: sinx is negative
        	      0: sinx is positive</comment>
        </bits>
      </reg>
      <reg name="cnr_1d_ctrl_reg" protect="rw">
        <bits access="rw" name="cnr_dif_thr_mid" pos="3:0" rst="0x8">
          <comment>CNR@Mid gain</comment>
        </bits>
        <bits access="rw" name="cnr_1d_on" pos="4" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name=" satur_on" pos="5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="hue_on" pos="6" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="cnr_xx_reg" protect="rw">
        <bits access="rw" name="cnr_dif_thr_low" pos="3:0" rst="0x4">
          <comment>CNR@Low gain</comment>
        </bits>
        <bits access="rw" name="cnr_dif_thr_high" pos="7:4" rst="0xc">
          <comment>CNR@High gain</comment>
        </bits>
      </reg>
      <reg name="in5_low_th_reg" protect="rw">
        <bits access="rw" name="in5_low_th_reg" pos="7:0" rst="0x40">
          <comment>Center point smaller than around, black point</comment>
        </bits>
      </reg>
      <reg name="in5_high_th_reg" protect="rw">
        <bits access="rw" name="in5_high_th_reg" pos="7:0" rst="0x90">
          <comment>Center point bigger than around, white point</comment>
        </bits>
      </reg>
      <hole size="72*32"/>
      <reg name="p2_up_r_reg" protect="rw">
        <bits access="rw" name="p2_up_r_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_up_g_reg" protect="rw">
        <bits access="rw" name="p2_up_g_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_up_b_reg" protect="rw">
        <bits access="rw" name="p2_up_b_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_down_r_reg" protect="rw">
        <bits access="rw" name="p2_down_r_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_down_g_reg" protect="rw">
        <bits access="rw" name="p2_down_g_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_down_b_reg" protect="rw">
        <bits access="rw" name="p2_down_b_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_left_r_reg" protect="rw">
        <bits access="rw" name="p2_left_r_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_left_g_reg" protect="rw">
        <bits access="rw" name="p2_left_g_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_left_b_reg" protect="rw">
        <bits access="rw" name="p2_left_b_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_right_r_reg" protect="rw">
        <bits access="rw" name="p2_right_r_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_right_g_reg" protect="rw">
        <bits access="rw" name="p2_right_g_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p2_right_b_reg" protect="rw">
        <bits access="rw" name="p2_right_b_reg" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q1_r_reg" protect="rw">
        <bits access="rw" name="p4_q1_r_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q1_g_reg" protect="rw">
        <bits access="rw" name="p4_q1_g_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q1_b_reg" protect="rw">
        <bits access="rw" name="p4_q1_b_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q2_r_reg" protect="rw">
        <bits access="rw" name="p4_q2_r_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q2_g_reg" protect="rw">
        <bits access="rw" name="p4_q2_g_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q2_b_reg" protect="rw">
        <bits access="rw" name="p4_q2_b_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q3_r_reg" protect="rw">
        <bits access="rw" name="p4_q3_r_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q3_g_reg" protect="rw">
        <bits access="rw" name="p4_q3_g_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q3_b_reg" protect="rw">
        <bits access="rw" name="p4_q3_b_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q4_r_reg" protect="rw">
        <bits access="rw" name="p4_q4_r_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q4_g_reg" protect="rw">
        <bits access="rw" name="p4_q4_g_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="p4_q4_b_reg" protect="rw">
        <bits access="rw" name="p4_q4_b_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="ae_e00_sta_reg" protect="rw">
        <bits access="rw" name="ae_e00_sta_line" pos="5:0" rst="0x2">
          <comment>E00</comment>
        </bits>
      </reg>
      <reg name="ae_e00_num_reg" protect="rw">
        <bits access="rw" name="ae_e00_num" pos="3:0" rst="0x7">
          <comment>E00</comment>
        </bits>
        <bits access="rw" name="ae_e00_interval" pos="5:4" rst="0x2">
          <comment>E00 max is 3Line</comment>
        </bits>
      </reg>
      <reg name="ae_e01_sta_reg" protect="rw">
        <bits access="rw" name="ae_e01_sta_line" pos="5:0" rst="0x10">
          <comment>E01</comment>
        </bits>
      </reg>
      <reg name="ae_e01_num_reg" protect="rw">
        <bits access="rw" name="ae_e01_num" pos="3:0" rst="0x4">
          <comment>E01</comment>
        </bits>
        <bits access="rw" name="ae_e01_interval" pos="6:4" rst="0x4">
          <comment>E01 max is 7Line</comment>
        </bits>
      </reg>
      <reg name="ae_e02_sta_reg" protect="rw">
        <bits access="rw" name="ae_e02_sta_line" pos="6:0" rst="0x20">
          <comment>E02max is 7F</comment>
        </bits>
      </reg>
      <reg name="ae_e02_num_reg" protect="rw">
        <bits access="rw" name="ae_e02_num" pos="3:0" rst="0x6">
          <comment>E02</comment>
        </bits>
        <bits access="rw" name="ae_e02_interval" pos="7:4" rst="0x8">
          <comment>E02 max is 15Line</comment>
        </bits>
      </reg>
      <reg name="ae_e1_sta_reg" protect="rw">
        <bits access="rw" name="ae_e1_sta_gain" pos="5:0" rst="0x0">
          <comment>E1 (64)</comment>
        </bits>
      </reg>
      <reg name="ae_e1_num_reg" protect="rw">
        <bits access="rw" name="ae_e1_num_reg" pos="3:0" rst="0x7">
          <comment>E1 (1E)</comment>
        </bits>
      </reg>
      <reg name="ae_e2_sta_reg" protect="rw">
        <bits access="rw" name="ae_e2_sta_gain" pos="5:0" rst="0x0">
          <comment>E2 (64)</comment>
        </bits>
      </reg>
      <reg name="ae_e2_num_reg" protect="rw">
        <bits access="rw" name="ae_e2_num_reg" pos="3:0" rst="0x4">
          <comment>E2 (2E)</comment>
        </bits>
      </reg>
      <reg name="ae_e3_sta_reg" protect="rw">
        <bits access="rw" name="ae_e3_sta_gain" pos="5:0" rst="0x0">
          <comment>E3 (64)</comment>
        </bits>
      </reg>
      <reg name="ae_e3_num_reg" protect="rw">
        <bits access="rw" name="ae_e3_num_reg" pos="3:0" rst="0x3">
          <comment>E3 (3E)</comment>
        </bits>
      </reg>
      <reg name="ae_e4_sta_reg" protect="rw">
        <bits access="rw" name="ae_e4_sta_gain" pos="5:0" rst="0x0">
          <comment>E4 (64)</comment>
        </bits>
      </reg>
      <reg name="ae_e4_num_reg" protect="rw">
        <bits access="rw" name="ae_e4_num_reg" pos="4:0" rst="0x9">
          <comment>E4 (4E)</comment>
        </bits>
      </reg>
      <reg name="ae_e5_sta_reg" protect="rw">
        <bits access="rw" name="ae_e5_sta_gain" pos="5:0" rst="0xa">
          <comment>E5 (64)</comment>
        </bits>
      </reg>
      <reg name="ae_e5_num_reg" protect="rw">
        <bits access="rw" name="ae_e5_num_reg" pos="4:0" rst="0x8">
          <comment>E5 (5E)</comment>
        </bits>
      </reg>
      <reg name="ae_e6_sta_reg" protect="rw">
        <bits access="rw" name="ae_e6_sta_gain" pos="5:0" rst="0x15">
          <comment>E6 (64)</comment>
        </bits>
      </reg>
      <reg name="ae_e6_num_reg" protect="rw">
        <bits access="rw" name="ae_e6_num_reg" pos="3:0" rst="0x6">
          <comment>E6 (6E)</comment>
        </bits>
      </reg>
      <reg name="ae_e7_sta_reg" protect="rw">
        <bits access="rw" name="ae_e7_sta_gain" pos="5:0" rst="0x1d">
          <comment>E7 (64)</comment>
        </bits>
      </reg>
      <reg name="ae_e7_num_reg" protect="rw">
        <bits access="rw" name="ae_e7_num_reg" pos="3:0" rst="0x3">
          <comment>E7 (7E)</comment>
        </bits>
      </reg>
      <reg name="ae_e8_sta_reg" protect="rw">
        <bits access="rw" name="ae_e8_sta_gain" pos="5:0" rst="0x20">
          <comment>E8 (64)</comment>
        </bits>
      </reg>
      <reg name="ae_e8_num_reg" protect="rw">
        <bits access="rw" name="ae_e8_num_reg" pos="3:0" rst="0x3">
          <comment>E8 (8E)</comment>
        </bits>
      </reg>
      <reg name="ae_e9_sta_reg" protect="rw">
        <bits access="rw" name="ae_e9_sta_gain" pos="5:0" rst="0x23">
          <comment>E9 (64)</comment>
        </bits>
      </reg>
      <reg name="ae_e9_num_reg" protect="rw">
        <bits access="rw" name="ae_e9_num_reg" pos="3:0" rst="0x3">
          <comment>E9 (9E)</comment>
        </bits>
      </reg>
      <reg name="ae_ea_sta_reg" protect="rw">
        <bits access="rw" name="ae_ea_sta_gain" pos="5:0" rst="0x26">
          <comment>Ea (64)</comment>
        </bits>
      </reg>
      <reg name="ae_ea_num_reg" protect="rw">
        <bits access="rw" name="ae_ea_num_reg" pos="3:0" rst="0x3">
          <comment>Ea (aE)</comment>
        </bits>
      </reg>
      <reg name="ae_eb_sta_reg" protect="rw">
        <bits access="rw" name="ae_eb_sta_gain" pos="5:0" rst="0x29">
          <comment>Eb (64)</comment>
        </bits>
      </reg>
      <reg name="ae_eb_num_reg" protect="rw">
        <bits access="rw" name="ae_eb_num_reg" pos="3:0" rst="0x3">
          <comment>Eb (bE)</comment>
        </bits>
      </reg>
      <reg name="ae_ec_sta_reg" protect="rw">
        <bits access="rw" name="ae_ec_sta_gain" pos="5:0" rst="0x2c">
          <comment>Ec (64)</comment>
        </bits>
      </reg>
      <reg name="ae_ec_num_reg" protect="rw">
        <bits access="rw" name="ae_ec_num_reg" pos="3:0" rst="0x5">
          <comment>Ec (cE)</comment>
        </bits>
      </reg>
      <reg name="ae_ed_sta_reg" protect="rw">
        <bits access="rw" name="ae_ed_sta_gain" pos="5:0" rst="0x0">
          <comment>Ed (64)</comment>
        </bits>
      </reg>
      <reg name="ae_ed_num_reg" protect="rw">
        <bits access="rw" name="ae_ed_num_reg" pos="3:0" rst="0x0">
          <comment>Ed (dE)</comment>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b0" protect="rw">
        <bits access="rw" name="bayer_gamma2_b0" pos="7:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b1" protect="rw">
        <bits access="rw" name="bayer_gamma2_b1" pos="7:0" rst="0x20">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b2" protect="rw">
        <bits access="rw" name="bayer_gamma2_b2" pos="7:0" rst="0x2d">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b3" protect="rw">
        <bits access="rw" name="bayer_gamma2_b3" pos="7:0" rst="0x37">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b4" protect="rw">
        <bits access="rw" name="bayer_gamma2_b4" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b6" protect="rw">
        <bits access="rw" name="bayer_gamma2_b6" pos="7:0" rst="0x4e">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b8" protect="rw">
        <bits access="rw" name="bayer_gamma2_b8" pos="7:0" rst="0x5a">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b10" protect="rw">
        <bits access="rw" name="bayer_gamma2_b10" pos="7:0" rst="0x65">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b12" protect="rw">
        <bits access="rw" name="bayer_gamma2_b12" pos="7:0" rst="0x6f">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b16" protect="rw">
        <bits access="rw" name="bayer_gamma2_b16" pos="7:0" rst="0x80">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b20" protect="rw">
        <bits access="rw" name="bayer_gamma2_b20" pos="7:0" rst="0x8f">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b24" protect="rw">
        <bits access="rw" name="bayer_gamma2_b24" pos="7:0" rst="0x9c">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b28" protect="rw">
        <bits access="rw" name="bayer_gamma2_b28" pos="7:0" rst="0xa9">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b32" protect="rw">
        <bits access="rw" name="bayer_gamma2_b32" pos="7:0" rst="0xb5">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b36" protect="rw">
        <bits access="rw" name="bayer_gamma2_b36" pos="7:0" rst="0xc0">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b40" protect="rw">
        <bits access="rw" name="bayer_gamma2_b40" pos="7:0" rst="0xca">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b48" protect="rw">
        <bits access="rw" name="bayer_gamma2_b48" pos="7:0" rst="0xdd">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b56" protect="rw">
        <bits access="rw" name="bayer_gamma2_b56" pos="7:0" rst="0xef">
          <comment/>
        </bits>
      </reg>
      <reg name="bayer_gamma2_b64" protect="rw">
        <bits access="rw" name="bayer_gamma2_b64" pos="7:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="y_thr7_lo_reg" protect="rw">
        <bits access="rw" name="y_thr7_lo_reg" pos="7:0" rst="0x30">
          <comment>Y_thr7 (for 2 dead point) @</comment>
        </bits>
      </reg>
      <reg name="y_thr7_mid_reg" protect="rw">
        <bits access="rw" name="y_thr7_mid_reg" pos="7:0" rst="0x38">
          <comment>Y_thr7 (for 2 dead point) @ mid</comment>
        </bits>
      </reg>
      <reg name="y_thr7_hi_reg" protect="rw">
        <bits access="rw" name="y_thr7_hi_reg" pos="7:0" rst="0x40">
          <comment>Y_thr7 (for 2 dead point) @</comment>
        </bits>
      </reg>
      <reg name="dpa_new_ctrl_reg" protect="rw">
        <bits access="rw" name="inflg_ctrl_reg_0" pos="0" rst="0x1">
          <comment>0: check one black dead point
                   1: don't check one black dead point</comment>
        </bits>
        <bits access="rw" name="inflg_ctrl_reg_1" pos="1" rst="0x1">
          <comment>0: check 2 black dead point
                   1: don't check 2 black dead point</comment>
        </bits>
        <bits access="rw" name="inflg_ctrl_reg_2" pos="2" rst="0x1">
          <comment>0: don't check 2 dead point
              1: check 2 dead point</comment>
        </bits>
      </reg>
      <reg name="dpa_new_ctrl_hi_reg" protect="rw">
        <bits access="rw" name="inflg_ctrl_reg0_h" pos="0" rst="0x0">
          <comment>(Note)
                   0: check one black dead point
                   1: don't check one black dead point</comment>
        </bits>
        <bits access="rw" name="inflg_ctrl_reg1_h" pos="1" rst="0x0">
          <comment>(Note)
                   0: check 2 black dead point
                   1: don't check 2 black dead point</comment>
        </bits>
        <bits access="rw" name="inflg_ctrl_reg2_h" pos="2" rst="0x1">
          <comment>(Note)
                   0: don't check 2 dead point
                   1: check 2 dead point</comment>
        </bits>
        <bits access="rw" name="threshold_rsvd" pos="4:3" rst="0x2">
          <comment>not used here</comment>
        </bits>
      </reg>
      <reg name="ae_index_gap" protect="rw">
        <bits access="rw" name="gap_2e" pos="0" rst="0x0">
          <comment>2E 12</comment>
        </bits>
        <bits access="rw" name="gap_3e" pos="1" rst="0x0">
          <comment>3E 12</comment>
        </bits>
        <bits access="rw" name="gap_4e" pos="2" rst="0x0">
          <comment>4E 12</comment>
        </bits>
        <bits access="rw" name="gap_5e" pos="3" rst="0x0">
          <comment>5E 12</comment>
        </bits>
        <bits access="rw" name="gap_6e" pos="4" rst="0x0">
          <comment>6E 12</comment>
        </bits>
        <bits access="rw" name="gap_7e" pos="5" rst="0x0">
          <comment>7E 12</comment>
        </bits>
        <bits access="rw" name="gap_8e" pos="6" rst="0x0">
          <comment>8E 12</comment>
        </bits>
        <bits access="rw" name="gap_9e" pos="7" rst="0x0">
          <comment>9E 12</comment>
        </bits>
      </reg>
      <reg name="awb_calc_height_reg" protect="rw">
        <bits access="rw" name="awb_calc_height_reg" pos="7:0" rst="0xf0">
          <comment>awb_win_height = [[7:0],1'd0]
            //4:3 and keep height as even number</comment>
        </bits>
      </reg>
      <reg name="drc_r_clp_value_reg" protect="rw">
        <bits access="rw" name="drc_r_clp_value_reg" pos="5:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="drc_gr_clp_value_reg" protect="rw">
        <bits access="rw" name="drc_gr_clp_value_reg" pos="5:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="drc_gb_clp_value_reg" protect="rw">
        <bits access="rw" name="drc_gb_clp_value_reg" pos="5:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="drc_b_clp_value_reg" protect="rw">
        <bits access="rw" name="drc_b_clp_value_reg" pos="5:0" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="sepia_cr_reg" protect="rw">
        <bits access="rw" name="sepia_cr_reg" pos="7:0" rst="0xab">
          <comment>blue: 0x72  red: 0xD4  brown:0xAB</comment>
        </bits>
      </reg>
      <reg name="sepia_cb_reg" protect="rw">
        <bits access="rw" name="sepia_cb_reg" pos="7:0" rst="0x60">
          <comment>blue: 0xD4  red: 0x64  brown:0x60</comment>
        </bits>
      </reg>
      <reg name="csup_y_min_hi_reg" protect="rw">
        <bits access="rw" name="csup_y_min_hi_reg" pos="7:0" rst="0xdc">
          <comment/>
        </bits>
      </reg>
      <reg name="csup_gain_hi_reg" protect="rw">
        <bits access="rw" name="csup_gain_hi_reg" pos="7:0" rst="0x00">
          <comment>0x20~ff (x1~8) ()</comment>
        </bits>
      </reg>
      <reg name="csup_y_max_low_reg" protect="rw">
        <bits access="rw" name="csup_y_max_low_reg" pos="7:0" rst="0x40">
          <comment/>
        </bits>
      </reg>
      <reg name="csup_gain_low_reg" protect="rw">
        <bits access="rw" name="csup_gain_low_reg" pos="7:0" rst="0x00">
          <comment>0x20~ff (x1~8) ()</comment>
        </bits>
      </reg>
      <reg name="ae_dk_hist_thr_reg" protect="rw">
        <bits access="rw" name="ae_dk_hist_thr_reg" pos="7:0" rst="0x48">
          <comment>If bhist&gt;bhist_too_big_thr, then bhist_too_big</comment>
        </bits>
      </reg>
      <reg name="ae_br_hist_thr_reg" protect="rw">
        <bits access="rw" name="ae_br_hist_thr_reg" pos="7:0" rst="0x18">
          <comment>If bhist&gt;bhist_big_thr, then bhist_big</comment>
        </bits>
      </reg>
      <reg name="hist_bp_level_reg" protect="rw">
        <bits access="rw" name="hist_bp_level_reg" pos="7:0" rst="0xd0">
          <comment>Y level of bhist and 4pbhist</comment>
        </bits>
      </reg>
      <reg name="outdoor_th_reg" protect="rw">
        <bits access="rw" name="outdoor_th" pos="3:0" rst="0x4">
          <comment>outdoor_th=[outdoor_th_reg[3:0], 4'd0]</comment>
        </bits>
        <bits access="rw" name="non_outdoor_th" pos="7:4" rst="0x8">
          <comment>non_outdoor_th=[outdoor_th_reg[7:4], 4'd0]</comment>
        </bits>
      </reg>
      <reg name="awb_rgain_low_reg" protect="rw">
        <bits access="rw" name="awb_rgain_low_reg" pos="7:2" rst="0xe">
          <comment>Low limit of rgain = [[7:2], 2d0]</comment>
        </bits>
      </reg>
      <reg name="awb_rgain_high_reg" protect="rw">
        <bits access="rw" name="awb_rgain_high_reg" pos="7:2" rst="0x1c">
          <comment>High limit of rgain = [[7:2], 2d0]</comment>
        </bits>
      </reg>
      <reg name="awb_bgain_low_reg" protect="rw">
        <bits access="rw" name="awb_bgain_low_reg" pos="7:2" rst="0xe">
          <comment>Low limit of bgain = [[7:2], 2d0]</comment>
        </bits>
      </reg>
      <reg name="awb_bgain_high_reg" protect="rw">
        <bits access="rw" name="awb_bgain_high_reg" pos="7:2" rst="0x20">
          <comment>High limit of bgain = [[7:2], 2d0]</comment>
        </bits>
      </reg>
      <reg name="awb_calc_start_reg" protect="rw">
        <bits access="rw" name="awb_win_y_start" pos="3:0" rst="0x1">
          <comment>awb_win_y_start = [[3:0], 2'd0];</comment>
        </bits>
        <bits access="rw" name="awb_win_x_start" pos="7:4" rst="0x1">
          <comment>awb_win_x_start = [[7:4], 2'd0];</comment>
        </bits>
      </reg>
      <reg name="awb_calc_width_reg" protect="rw">
        <bits access="rw" name="awb_calc_width_reg" pos="7:0" rst="0xa0">
          <comment>awb_win_width =[[7:0],2'd0];
            //4:3 and keep height as even number</comment>
        </bits>
      </reg>
      <reg name="hist_dp_level_reg" protect="rw">
        <bits access="rw" name="hist_dp_level_reg" pos="7:0" rst="0x30">
          <comment>Y level of dark_hist</comment>
        </bits>
      </reg>
      <reg name="awb_y_fmin" protect="rw">
        <bits access="rw" name="awb_y_fmin" pos="7:0" rst="0x40">
          <comment>for skin</comment>
        </bits>
      </reg>
      <reg name="awb_y_fmax" protect="rw">
        <bits access="rw" name="awb_y_fmax" pos="7:0" rst="0xb4">
          <comment>for skin</comment>
        </bits>
      </reg>
      <reg name="awb_cb_fmin" protect="rw">
        <bits access="rw" name="awb_cb_fmin" pos="7:0" rst="0x4d">
          <comment>for skin</comment>
        </bits>
      </reg>
      <reg name="awb_cb_fmax" protect="rw">
        <bits access="rw" name="awb_cb_fmax" pos="7:0" rst="0x7f">
          <comment>for skin</comment>
        </bits>
      </reg>
      <reg name="awb_cr_fmin" protect="rw">
        <bits access="rw" name="awb_cr_fmin" pos="7:0" rst="0x85">
          <comment>for skin</comment>
        </bits>
      </reg>
      <reg name="awb_cr_fmax" protect="rw">
        <bits access="rw" name="awb_cr_fmax" pos="7:0" rst="0xad">
          <comment>for skin</comment>
        </bits>
      </reg>
      <reg name="awb_y_fmin2" protect="rw">
        <bits access="rw" name="awb_y_fmin2" pos="7:0" rst="0x40">
          <comment>for mono color</comment>
        </bits>
      </reg>
      <reg name="awb_y_fmax2" protect="rw">
        <bits access="rw" name="awb_y_fmax2" pos="7:0" rst="0xb4">
          <comment>for mono color</comment>
        </bits>
      </reg>
      <reg name="awb_cb_fmin2" protect="rw">
        <bits access="rw" name="awb_cb_fmin2" pos="7:0" rst="0x34">
          <comment>for mono color</comment>
        </bits>
      </reg>
      <reg name="awb_cb_fmax2" protect="rw">
        <bits access="rw" name="awb_cb_fmax2" pos="7:0" rst="0x5c">
          <comment>for mono color</comment>
        </bits>
      </reg>
      <reg name="awb_cr_fmin2" protect="rw">
        <bits access="rw" name="awb_cr_fmin2" pos="7:0" rst="0x24">
          <comment>for mono color</comment>
        </bits>
      </reg>
      <reg name="awb_cr_fmax2" protect="rw">
        <bits access="rw" name="awb_cr_fmax2" pos="7:0" rst="0x4c">
          <comment>for mono color</comment>
        </bits>
      </reg>
      <reg name="ae_use_mean" protect="rw">
        <bits access="rw" name="ycave_use_mean" pos="1:0" rst="0x3">
          <comment>0yave        1yave
                  2yave    3yave</comment>
        </bits>
        <bits access="rw" name="ywave_use_mean" pos="3:2" rst="0x3">
          <comment>0yave        1yave
                  2yave    3yave</comment>
        </bits>
        <bits access="rw" name="yave_weight_mode" pos="4" rst="0x1">
          <comment>0: win yave     1: ywave</comment>
        </bits>
        <bits access="rw" name="nexp_out_sel_reg" pos="5" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="ae_ext_adj_val_reg" pos="6" rst="0x1">
          <comment/>
        </bits>
        <bits access="rw" name="ae_ext_adj_on_reg" pos="7" rst="0x1">
          <comment/>
        </bits>
      </reg>
      <reg name="ae_weight_sta" protect="rw">
        <bits access="rw" name="ywave_pcnt_left" pos="3:0" rst="0x4">
          <comment>ae ywave</comment>
        </bits>
        <bits access="rw" name="ywave_lcnt_top" pos="7:4" rst="0x4">
          <comment>ae ywave</comment>
        </bits>
      </reg>
      <reg name="ae_qwidth" protect="rw">
        <bits access="rw" name="qwidth" pos="7:0" rst="0xa0">
          <comment>QVGA 240x320 :8d60      QVGA 320x240: 8d80
                  CIF  352x288: 8d88       VGA 640x480: 8d160</comment>
        </bits>
      </reg>
      <reg name="ae_qheight" protect="rw">
        <bits access="rw" name="qheight" pos="6:0" rst="0x78">
          <comment>QVGA 240x320 :8d80      QVGA 320x240: 8d60
                  CIF  352x288: 8d72       VGA 640x480: 8d120</comment>
        </bits>
        <bits access="rw" name="ywave_sel" pos="7" rst="0x0">
          <comment>0: x1(CIFx1)  1:x1.5</comment>
        </bits>
      </reg>
      <reg name="ae_win_sta" protect="rw">
        <bits access="rw" name="yave_pcnt_sta" pos="3:0" rst="0x2">
          <comment>yave pcnt_sta=[[3:0], 1b0]</comment>
        </bits>
        <bits access="rw" name="yave_lcnt_sta" pos="7:4" rst="0x2">
          <comment>yave lcnt_sta=[[7:4], 1b0]</comment>
        </bits>
      </reg>
      <reg name="ae_width" protect="rw">
        <bits access="rw" name="width" pos="7:0" rst="0x95">
          <comment>yave Width=[[7:0],  2d0]
                  QVGA 240x320 :10d216     QVGA 320x240: 10d304
                  CIF  352x288: 10d304      VGA 640x480: 10d596</comment>
        </bits>
      </reg>
      <reg name="ae_height" protect="rw">
        <bits access="rw" name="height" pos="7:0" rst="0xdc">
          <comment>yave Height=[[7:0], 1d0]
                  QVGA 240x320 :10d304     QVGA 320x240: 10d216
                  CIF   352x288: 10d216      VGA 640x480: 10d440</comment>
        </bits>
      </reg>
      <reg name="sw_update" protect="rw">
        <bits access="rw" name="cc_type_sw" pos="0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="is_outdoor_sw" pos="1" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="gamma_type_sw" pos="2" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="sw_update_rsvd" pos="3" rst="0x0">
          <comment>not used here</comment>
        </bits>
        <bits access="rw" name="is_outdoor_mode" pos="6:4" rst="0x0">
          <comment>3'd0:   is_outdoor = 0;
                  3'd1:   is_outdoor = 1;
                  3'd2:
                       if(ana_gain==0) begin
                         if(expoutdoor_th)          is_outdoor = 1;
                         else if(expnon_outdoor_th) is_outdoor = 0;    end
                       else                           is_outdoor = 0;
                  3'd3:
                       if(ana_gain==0 and rgain_bigger) begin
                         if(expoutdoor_th)          is_outdoor = 1;
                         else if(expnon_outdoor_th) is_outdoor = 0;   end
                       else                           is_outdoor = 0;
                 default:
                       if(vsync_rp_d and sw_update_en)    is_outdoor = is_outdoor_sw;</comment>
        </bits>
        <bits access="rw" name="awb_outdoor_en" pos="7" rst="0x0">
          <comment>1: when is_outdoor=1, only detect white point at D65 and Indoor CTD block
                  0: dont care is_outdoor, detect white point at all ctd block</comment>
        </bits>
      </reg>
      <reg name="awb_ctrl5" protect="rw">
        <bits access="rw" name="r_low_non_a" pos="7:0" rst="0x3c">
          <comment/>
        </bits>
      </reg>
      <reg name="awb_ctrl6" protect="rw">
        <bits access="rw" name="awb_stop_h" pos="3:0" rst="0x0">
          <comment>awb_stop_cr_pos_level =[[3],awb_stop_reg[7:6]];
                  awb_stop_cr_neg_level =[[2],awb_stop_reg[5:4]];
                  awb_stop_cb_pos_level =[[1],awb_stop_reg[3:2]];
                  awb_stop_cb_neg_level =[[0],awb_stop_reg[1:0]];</comment>
        </bits>
        <bits access="rw" name="awb_adj_again" pos="5:4" rst="0x0">
          <comment>awb_adj_again = [2'b11, [5:4]]</comment>
        </bits>
        <bits access="rw" name="awb_algo_en" pos="6" rst="0x0">
          <comment>1: add awb_algo_thr condition to detect white point@A
                  0: detect white point according to A ctd block</comment>
        </bits>
        <bits access="rw" name="check_r_low" pos="7" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="sca_reg" protect="rw">
        <bits access="rw" name="sca_mode" pos="2:0" rst="0x0">
          <comment>0: normal(no scale)
                  1: sub(yuv sub mode)
                  2: sca_320x240(1/2)
                  3: sca_176x144(1/3)
                  4: sca_160x120(1/4)
                  5: sca352x288(2/3)
                  6: sca352x288(3/5)
                  7: 3/4</comment>
        </bits>
      </reg>
      <reg name="ae_ee_sta_reg" protect="rw">
        <bits access="rw" name="ae_ee_sta_gain" pos="5:0" rst="0x0">
          <comment>Ee (64)</comment>
        </bits>
      </reg>
      <reg name="ae_ee_num_reg" protect="rw">
        <bits access="rw" name="ae_ee_num_reg" pos="3:0" rst="0x0">
          <comment>Ee (eE)</comment>
        </bits>
      </reg>
      <reg name="ae_ef_sta_reg" protect="rw">
        <bits access="rw" name="ae_ef_sta_gain" pos="5:0" rst="0x0">
          <comment>Ef (64)</comment>
        </bits>
      </reg>
      <reg name="ae_ef_num_reg" protect="rw">
        <bits access="rw" name="ae_ef_num_reg" pos="3:0" rst="0x0">
          <comment>Ef (fE)</comment>
        </bits>
      </reg>
      <reg name="ae_thr_big_reg" protect="rw">
        <bits access="rw" name="ae_thr_big_dark" pos="3:0" rst="0x6">
          <comment>ae_thr_big = [reg1CA[3:0],2d0]@dark</comment>
        </bits>
        <bits access="rw" name="ae_thr_big_bright" pos="7:4" rst="0x8">
          <comment>ae_thr_big = [reg1CA[7:4],2d0]@bright</comment>
        </bits>
      </reg>
      <reg name="sharp_gain_minus_low" protect="rw">
        <bits access="rw" name="sharp_gain_minus_low" pos="7:0" rst="0x70">
          <comment>sharp gain @low gain(2.6 format)</comment>
        </bits>
      </reg>
      <reg name="sharp_gain_minus_mid" protect="rw">
        <bits access="rw" name="sharp_gain_minus_mid" pos="7:0" rst="0x90">
          <comment>sharp gain @medium gain(2.6 format)</comment>
        </bits>
      </reg>
      <reg name="sharp_gain_minus_hi" protect="rw">
        <bits access="rw" name="sharp_gain_minus_hi" pos="7:0" rst="0xb0">
          <comment>sharp gain @high gain(2.6 format)</comment>
        </bits>
      </reg>
      <reg name="sharp_mode_mid_hi" protect="rw">
        <bits access="rw" name="sharp_cmp_gap_mid" pos="3:0" rst="0x8">
          <comment>sharp_cmp&gt; (sharp_nr_area_thr[6:0]+sharp_cmp_gap)</comment>
        </bits>
        <bits access="rw" name="sharp_cmp_gap_hi" pos="7:4" rst="0x8">
          <comment>sharp_cmp&gt; (sharp_nr_area_thr[6:0]+sharp_cmp_gap)</comment>
        </bits>
      </reg>
      <reg name="fw_version_reg" protect="rw">
        <bits access="rw" name="fw_version" pos="7:0" rst="0x00">
          <comment/>
        </bits>
      </reg>
      <reg name="awb_y_min_reg" protect="rw">
        <bits access="rw" name="awb_y_min" pos="7:0" rst="0x40">
          <comment>Y = Y_min ( AWB)</comment>
        </bits>
      </reg>
      <reg name="y_red_coef_reg" protect="rw">
        <bits access="rw" name="y_red_coef" pos="7:0" rst="0x4d">
          <comment/>
        </bits>
      </reg>
      <reg name="y_blue_coef_reg" protect="rw">
        <bits access="rw" name="y_blue_coef" pos="7:0" rst="0x1d">
          <comment/>
        </bits>
      </reg>
      <reg name="cb_red_coef_reg" protect="rw">
        <bits access="rw" name="cb_red_coef" pos="7:0" rst="0x2b">
          <comment/>
        </bits>
      </reg>
      <reg name="cr_blue_coef_reg" protect="rw">
        <bits access="rw" name="cr_blue_coef" pos="7:0" rst="0x15">
          <comment/>
        </bits>
      </reg>
      <reg name="hist_vbp_level_reg" protect="rw">
        <bits access="rw" name="hist_vbp_level" pos="7:0" rst="0xd8">
          <comment>Y level of vbright_hist</comment>
        </bits>
      </reg>
      <reg name="hist_vdp_level_reg" protect="rw">
        <bits access="rw" name="hist_vdp_level" pos="7:0" rst="0x18">
          <comment>Y level of vdark_hist</comment>
        </bits>
      </reg>
      <hole size="40*32"/>
    </module>
  </archive>
  <archive relative="adi_mst.xml">
    <module category="Periph" name="ADI_MST">
      <reg name="adi_version" protect="rw">
        <bits access="rw" name="adi_version_low" pos="3:0" rst="0">
          <comment>adi low bits version.</comment>
        </bits>
        <bits access="r" name="adi_version_high" pos="15:4" rst="0x10">
          <comment>adi high bits version,read only.</comment>
        </bits>
      </reg>
      <reg name="adi_ctrl" protect="rw">
        <bits access="rw" name="addr_byte_sel" pos="1:0" rst="0">
          <comment>addr mode for access. &quot;00&quot; word mode,means addr[x:2],&quot;01&quot; half word,means addr[x:1], &quot;1x&quot; byte mode, means addr[x:0].</comment>
        </bits>
        <bits access="rw" name="wr_bit_flag" pos="2" rst="0">
          <comment>configure write bit flag.</comment>
        </bits>
        <bits access="rw" name="addr_bits_sel" pos="4:3" rst="0">
          <comment>addr bit number configure, &quot;00&quot; address is 12 bits, &quot;01&quot; address is 10 bits, &quot;10&quot; address is 15 bits.</comment>
        </bits>
        <bits access="rw" name="wr_cmd_en" pos="5" rst="0">
          <comment>&quot;1&quot; write uses command mode, in this mode, must first configure channel addr, then data.</comment>
        </bits>
      </reg>
      <reg name="adi_pril" protect="rw">
        <bits access="rw" name="chnl0_pri" pos="2:0" rst="0">
          <comment>write channel 0 priority. 0 has lowest priority, 4 has highest priority.</comment>
        </bits>
        <bits access="rw" name="chnl1_pri" pos="5:3" rst="0">
          <comment>read channel 1 priority. 0 has lowest priority, 4 has highest priority.</comment>
        </bits>
        <bits access="rw" name="event0_pri" pos="8:6" rst="0">
          <comment>read channel 2 priority. 0 has lowest priority, 4 has highest priority.</comment>
        </bits>
        <bits access="rw" name="event1_pri" pos="11:9" rst="0">
          <comment>read channel 3 priority. 0 has lowest priority, 4 has highest priority.</comment>
        </bits>
        <bits access="rw" name="event2_pri" pos="14:12" rst="0">
          <comment>read channel 4 priority. 0 has lowest priority, 4 has highest priority.</comment>
        </bits>
        <bits access="rw" name="event3_pri" pos="17:15" rst="0">
          <comment>read channel 5 priority. 0 has lowest priority, 4 has highest priority.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="adi_int_en" protect="rw">
        <bits access="rw" name="wfifo_en" pos="0" rst="0">
          <comment>&quot;1&quot; write command fifo enable.</comment>
        </bits>
        <bits access="rw" name="fifo_overflow_int_en" pos="3" rst="0">
          <comment>fifo overfolow interrupt mask.</comment>
        </bits>
      </reg>
      <reg name="adi_int_raw" protect="r">
        <bits access="r" name="fifo_overflow_raw" pos="3" rst="0">
          <comment>fifo overfolow interrupt without mask status.</comment>
        </bits>
      </reg>
      <reg name="adi_int_status" protect="r">
        <bits access="r" name="fifo_overflow_status" pos="3" rst="0">
          <comment>fifo overfolow interrupt with mask status.</comment>
        </bits>
      </reg>
      <reg name="adi_int_clear" protect="w">
        <bits access="w" name="fifo_overflow_clear" pos="3" rst="0">
          <comment>fifo overfolow interrupt clear.</comment>
        </bits>
      </reg>
      <reg name="adi_cfg0" protect="rw">
        <bits access="rw" name="rf_gssi_frame_len" pos="5:0" rst="0x3d">
          <comment>total adi frame length = rf_gssi_cmd_len + rf_gssi_data_len.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_cmd_len" pos="10:6" rst="0x14">
          <comment>total adi cmd length = rf_gssi_addr_len + read/write flag.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_data_len" pos="15:11" rst="0x10">
          <comment>total adi data length .</comment>
        </bits>
        <bits access="rw" name="rf_gssi_wr_pos" pos="20:16" rst="0x10">
          <comment>write bit position in frame stream .</comment>
        </bits>
        <bits access="rw" name="rf_gssi_wr_pol" pos="21" rst="0x0">
          <comment>&quot;1&quot; write means 1, &quot;0&quot; write means 0.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_sync_sel" pos="22" rst="0x1">
          <comment>&quot;1&quot; hardware auto generate sync, &quot;0&quot; software generates sync.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_sync_mode" pos="23" rst="0x1">
          <comment>&quot;1&quot; sync is pulse, &quot;0&quot; sync is level.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_sync" pos="24" rst="0x0">
          <comment>&quot;1&quot; software generates sync.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_sck_rev" pos="25" rst="0x0">
          <comment>&quot;1&quot; invert output sck.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_oe_cfg" pos="26" rst="0x1">
          <comment>output oen : &quot;1&quot; oen add dummy cycle, &quot;0&quot; oen not add dummy cycle.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_ie_cfg" pos="27" rst="0x0">
          <comment>reserved.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_dummy_clk_en" pos="28" rst="0x1">
          <comment>&quot;1&quot; output dummy_clock, &quot;0&quot; gate dummy clock.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_fast_mode" pos="29" rst="0x0">
          <comment>&quot;1&quot; rx sample delay 1 adi clk cycle, &quot;0&quot; delay 0 adi clk cycle.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_sck_all_on" pos="30" rst="0x1">
          <comment>&quot;1&quot; sck always on, &quot;0&quot; audo gate  clock.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_wr_disable" pos="31" rst="0x0">
          <comment>&quot;1&quot; write bit disable, &quot;0&quot; write bit enable.</comment>
        </bits>
      </reg>
      <reg name="adi_cfg1" protect="rw">
        <bits access="rw" name="rf_gssi_ng_tx" pos="0" rst="1">
          <comment>&quot;1&quot; tx data at negedge of sck.&quot;0&quot; tx data at posedge of sck.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_ng_rx" pos="1" rst="0">
          <comment>&quot;1&quot; rx data at negedge of sck.&quot;0&quot; rx data at posedge of sck.</comment>
        </bits>
        <bits access="rw" name="rf_gssi_clk_div" pos="9:2" rst="0">
          <comment>F_sck = F_clk/(2*(rf_gssi_clk_div+1))</comment>
        </bits>
        <bits access="rw" name="rf_gssi_sync_head_len" pos="12:10" rst="0">
          <comment>sync before data transfer</comment>
        </bits>
        <bits access="rw" name="rf_gssi_sync_end_len" pos="15:13" rst="0">
          <comment>sync end data transfer</comment>
        </bits>
        <bits access="rw" name="rf_gssi_dummy_len" pos="19:16" rst="3">
          <comment>extral dummy sck</comment>
        </bits>
        <bits access="rw" name="rf_gssi_sample_delay" pos="20" rst="0">
          <comment>extral dummy sck</comment>
        </bits>
        <bits access="rw" name="rf_gssi_scc_len" pos="23:21" rst="0">
          <comment>start sequence condition, only used in RFFE</comment>
        </bits>
        <bits access="rw" name="rf_gssi_wbp_len" pos="26:24" rst="0">
          <comment>master turn around to salve length , only used in RFFE</comment>
        </bits>
        <bits access="rw" name="rf_gssi_rbp_len" pos="30:28" rst="0">
          <comment>slave turn around to master length , only used in RFFE</comment>
        </bits>
        <bits access="rw" name="rf_gssi_strtbit_mode" pos="31" rst="0">
          <comment>&quot;1&quot; 2 wires enable</comment>
        </bits>
      </reg>
      <reg name="arm_rd_cmd" protect="rw">
        <bits access="rw" name="arm_rd_cmd" pos="16:0" rst="0">
          <comment>configure read address and start a read operation.</comment>
        </bits>
      </reg>
      <reg name="arm_rd_data" protect="r">
        <bits access="r" name="arm_rd_cmd" pos="15:0" rst="0">
          <comment>read data from analog die.</comment>
        </bits>
        <bits access="r" name="arm_rd_addr" pos="30:16" rst="0">
          <comment>read address map to arm_red_cmd[16:2].</comment>
        </bits>
        <bits access="r" name="arm_rd_cmd_busy" pos="31" rst="0">
          <comment>1 means has not been read back.</comment>
        </bits>
      </reg>
      <reg name="arm_cmd_status" protect="r">
        <bits access="r" name="arm_wr_status" pos="0" rst="0">
          <comment>&quot;1&quot; write channel is busy</comment>
        </bits>
        <bits access="r" name="arm_rd_status" pos="1" rst="0">
          <comment>&quot;1&quot; read channel is busy</comment>
        </bits>
        <bits access="r" name="adi_busy" pos="4" rst="0">
          <comment>&quot;1&quot; adi operation is busy</comment>
        </bits>
        <bits access="r" name="wfifo full" pos="8" rst="0">
          <comment>wfifo full status</comment>
        </bits>
        <bits access="r" name="wfifo empty" pos="9" rst="0">
          <comment>wfifo empty status</comment>
        </bits>
        <bits access="r" name="wfifo fill data level" pos="14:12" rst="0">
          <comment>wfifo fill data number</comment>
        </bits>
        <bits access="r" name="adi fsm status" pos="19:16" rst="0">
          <comment>adi fsm status</comment>
        </bits>
        <bits access="r" name="event0 wr status" pos="20" rst="0">
          <comment>event 0 wr status</comment>
        </bits>
        <bits access="r" name="event1 wr status" pos="21" rst="0">
          <comment>event 1 wr status</comment>
        </bits>
        <bits access="r" name="event2 wr status" pos="22" rst="0">
          <comment>event 2 wr status</comment>
        </bits>
        <bits access="r" name="event3 wr status" pos="23" rst="0">
          <comment>event 3 wr status</comment>
        </bits>
      </reg>
      <reg name="adi_chanel_en" protect="rw">
        <bits access="rw" name="event0 trigger negedge en" pos="0" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="event0 trigger posedge en" pos="1" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="event1 trigger negedge en" pos="2" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="event1 trigger posedge en" pos="3" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="event2 trigger negedge en" pos="4" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="event2 trigger posedge en" pos="5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="event3 trigger negedge en" pos="6" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="event3 trigger posedge en" pos="7" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="adi_cmd_wr" protect="rw">
        <bits access="rw" name="adi_cmd_wr" pos="16:0" rst="0">
          <comment>the address map to the PMIC chip space, just for write operation</comment>
        </bits>
      </reg>
      <reg name="adi_dat_wr" protect="rw">
        <bits access="rw" name="adi_dat_wr" pos="15:0" rst="0">
          <comment>the dat to the PMIC chip space, just for write operation</comment>
        </bits>
      </reg>
      <reg name="event0_waddr" protect="rw">
        <bits access="rw" name="event0_waddr" pos="16:0" rst="0x634">
          <comment/>
        </bits>
      </reg>
      <reg name="event1_waddr" protect="rw">
        <bits access="rw" name="event1_waddr" pos="16:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="event2_waddr" protect="rw">
        <bits access="rw" name="event2_waddr" pos="16:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="event3_waddr" protect="rw">
        <bits access="rw" name="event3_waddr" pos="16:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="event0_wdata" protect="rw">
        <bits access="rw" name="event0_neg_wdata" pos="15:0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="event0_pos_wdata" pos="31:16" rst="0x1">
          <comment/>
        </bits>
      </reg>
      <reg name="event1_wdata" protect="rw">
        <bits access="rw" name="event1_neg_wdata" pos="15:0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="event1_pos_wdata" pos="31:16" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="event2_wdata" protect="rw">
        <bits access="rw" name="event2_neg_wdata" pos="15:0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="event2_pos_wdata" pos="31:16" rst="0x0">
          <comment/>
        </bits>
      </reg>
      <reg name="event3_wdata" protect="rw">
        <bits access="rw" name="event3_neg_wdata" pos="15:0" rst="0x0">
          <comment/>
        </bits>
        <bits access="rw" name="event3_pos_wdata" pos="31:16" rst="0x0">
          <comment/>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="analog_reg.xml">
    <module category="ANALOG_IF" name="ANALOG_REG">
      <reg name="apll_reg0" protect="rw">
        <bits access="r" name="apll_lock" pos="2" rst="0">
      </bits>
        <bits access="rw" name="apll_lp_mode_en" pos="1" rst="0">
      </bits>
        <bits access="rw" name="apll_clk_ap_en" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="apll_reg1" protect="rw">
        <bits access="rw" name="apll_pfd_dly_num" pos="19:17" rst="0">
      </bits>
        <bits access="rw" name="apll_vreg_bit" pos="16:13" rst="8">
      </bits>
        <bits access="rw" name="apll_reg_res_bit" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="apll_cpbias_ibit" pos="10:8" rst="4">
      </bits>
        <bits access="rw" name="apll_cpc2_ibit" pos="7:5" rst="4">
      </bits>
        <bits access="rw" name="apll_cpr2_ibit" pos="4:2" rst="4">
      </bits>
        <bits access="rw" name="apll_pcon_mode" pos="1" rst="0">
      </bits>
        <bits access="rw" name="apll_refmulti2_en" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="apll_reg2" protect="rw">
        <bits access="rw" name="apll_test_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="apll_sdm_clk_test_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="apll_vco_high_test" pos="1" rst="0">
      </bits>
        <bits access="rw" name="apll_vco_low_test" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="sdm_apll_reg0" protect="rw">
        <bits access="rw" name="sdm_apll_fbc_inv" pos="8" rst="0">
      </bits>
        <bits access="rw" name="sdm_apll_pu" pos="7" rst="1">
      </bits>
        <bits access="rw" name="sdm_apll_sdm_clk_sel_rst" pos="6" rst="1">
      </bits>
        <bits access="rw" name="sdm_apll_sdm_clk_sel_nor" pos="5" rst="0">
      </bits>
        <bits access="rw" name="sdm_apll_pu_pll_dr" pos="4" rst="0">
      </bits>
        <bits access="rw" name="sdm_apll_pu_pll_reg" pos="3" rst="0">
      </bits>
        <bits access="rw" name="sdm_apll_int_dec_sel" pos="2:0" rst="3">
      </bits>
      </reg>
      <reg name="sdm_apll_reg1" protect="rw">
        <bits access="rw" name="sdm_apll_sdm_freq" pos="31:0" rst="495573150">
          <comment>freq/26*2^25    768Mhz</comment>
        </bits>
      </reg>
      <reg name="sdm_apll_reg2" protect="rw">
        <bits access="rw" name="sdm_apll_dither_bypass" pos="11" rst="1">
      </bits>
        <bits access="rw" name="sdm_apll_sdm_resetn_dr" pos="10" rst="0">
      </bits>
        <bits access="rw" name="sdm_apll_sdm_resetn_reg" pos="9" rst="0">
      </bits>
        <bits access="rw" name="sdm_apll_sdm_reset_time_sel" pos="8:7" rst="1">
      </bits>
        <bits access="rw" name="sdm_apll_sdmclk_sel_time_sel" pos="6:5" rst="1">
      </bits>
        <bits access="rw" name="sdm_apll_clk_gen_en_reg" pos="4" rst="1">
      </bits>
        <bits access="rw" name="sdm_apll_clkout_en_counter_sel" pos="3:2" rst="2">
      </bits>
        <bits access="rw" name="sdm_apll_lock_counter_sel" pos="1:0" rst="1">
      </bits>
      </reg>
      <reg name="sdm_apll_reg3" protect="r">
        <bits access="r" name="sdm_apll_sdm_resetn" pos="2" rst="0">
      </bits>
        <bits access="r" name="sdm_apll_lock_steady" pos="1" rst="0">
      </bits>
        <bits access="r" name="sdm_apll_clk_ready" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="sdm_apll_reg4" protect="rw">
        <bits access="rw" name="sdm_apll_sdm_en" pos="29" rst="1">
      </bits>
        <bits access="rw" name="sdm_apll_ss_en" pos="28" rst="0">
      </bits>
        <bits access="rw" name="sdm_apll_ss_devi" pos="27:16" rst="0">
      </bits>
        <bits access="rw" name="sdm_apll_ss_devi_step" pos="15:0" rst="0">
      </bits>
      </reg>
      <hole size="256"/>
      <reg name="mempll_reg0" protect="rw">
        <bits access="r" name="mempll_lock" pos="2" rst="0">
      </bits>
        <bits access="rw" name="mempll_lp_mode_en" pos="1" rst="0">
      </bits>
        <bits access="rw" name="mempll_clk_mem_en" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="mempll_reg1" protect="rw">
        <bits access="rw" name="mempll_pfd_dly_num" pos="19:17" rst="0">
      </bits>
        <bits access="rw" name="mempll_vreg_bit" pos="16:13" rst="8">
      </bits>
        <bits access="rw" name="mempll_reg_res_bit" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="mempll_cpbias_ibit" pos="10:8" rst="4">
      </bits>
        <bits access="rw" name="mempll_cpc2_ibit" pos="7:5" rst="4">
      </bits>
        <bits access="rw" name="mempll_cpr2_ibit" pos="4:2" rst="4">
      </bits>
        <bits access="rw" name="mempll_pcon_mode" pos="1" rst="0">
      </bits>
        <bits access="rw" name="mempll_refmulti2_en" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="mempll_reg2" protect="rw">
        <bits access="rw" name="mempll_test_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="mempll_sdm_clk_test_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="mempll_vco_high_test" pos="1" rst="0">
      </bits>
        <bits access="rw" name="mempll_vco_low_test" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="sdm_mempll_reg0" protect="rw">
        <bits access="rw" name="sdm_mempll_fbc_inv" pos="8" rst="0">
      </bits>
        <bits access="rw" name="sdm_mempll_pu" pos="7" rst="1">
      </bits>
        <bits access="rw" name="sdm_mempll_sdm_clk_sel_rst" pos="6" rst="1">
      </bits>
        <bits access="rw" name="sdm_mempll_sdm_clk_sel_nor" pos="5" rst="0">
      </bits>
        <bits access="rw" name="sdm_mempll_pu_pll_dr" pos="4" rst="0">
      </bits>
        <bits access="rw" name="sdm_mempll_pu_pll_reg" pos="3" rst="0">
      </bits>
        <bits access="rw" name="sdm_mempll_int_dec_sel" pos="2:0" rst="3">
      </bits>
      </reg>
      <reg name="sdm_mempll_reg1" protect="rw">
        <bits access="rw" name="sdm_mempll_sdm_freq" pos="31:0" rst="516222030">
          <comment>800Mhz</comment>
        </bits>
      </reg>
      <reg name="sdm_mempll_reg2" protect="rw">
        <bits access="rw" name="sdm_mempll_dither_bypass" pos="11" rst="1">
      </bits>
        <bits access="rw" name="sdm_mempll_sdm_resetn_dr" pos="10" rst="0">
      </bits>
        <bits access="rw" name="sdm_mempll_sdm_resetn_reg" pos="9" rst="0">
      </bits>
        <bits access="rw" name="sdm_mempll_sdm_reset_time_sel" pos="8:7" rst="1">
      </bits>
        <bits access="rw" name="sdm_mempll_sdmclk_sel_time_sel" pos="6:5" rst="1">
      </bits>
        <bits access="rw" name="sdm_mempll_clk_gen_en_reg" pos="4" rst="1">
      </bits>
        <bits access="rw" name="sdm_mempll_clkout_en_counter_sel" pos="3:2" rst="2">
      </bits>
        <bits access="rw" name="sdm_mempll_lock_counter_sel" pos="1:0" rst="1">
      </bits>
      </reg>
      <reg name="sdm_mempll_reg3" protect="r">
        <bits access="r" name="sdm_mempll_sdm_resetn" pos="2" rst="0">
      </bits>
        <bits access="r" name="sdm_mempll_lock_steady" pos="1" rst="0">
      </bits>
        <bits access="r" name="sdm_mempll_clk_ready" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="sdm_mempll_reg4" protect="rw">
        <bits access="rw" name="sdm_mempll_sdm_en" pos="29" rst="1">
      </bits>
        <bits access="rw" name="sdm_mempll_ss_en" pos="28" rst="0">
      </bits>
        <bits access="rw" name="sdm_mempll_ss_devi" pos="27:16" rst="0">
      </bits>
        <bits access="rw" name="sdm_mempll_ss_devi_step" pos="15:0" rst="0">
      </bits>
      </reg>
      <hole size="256"/>
      <reg name="usb_reg0" protect="rw">
        <bits access="rw" name="usb_tx_rstn" pos="9" rst="1">
      </bits>
        <bits access="rw" name="usb_cdr_clk_edge_bit" pos="8" rst="0">
          <comment>1: clk_datarx
0: inv of clk_datarx</comment>
        </bits>
        <bits access="rw" name="usb_rst_intp_enable" pos="7" rst="0">
          <comment>1: enable rst intepolator by squelch
0: disable rst by squelch</comment>
        </bits>
        <bits access="rw" name="usb_updn_mode" pos="6" rst="0">
          <comment>default: 1'h0</comment>
        </bits>
        <bits access="rw" name="usb_phase_sel" pos="5:4" rst="2">
          <comment>tx clk samle data  phase</comment>
        </bits>
        <bits access="rw" name="usb_cdr_gain" pos="3:0" rst="9">
          <comment>set cdr gain</comment>
        </bits>
      </reg>
      <reg name="usb_reg1" protect="rw">
        <bits access="rw" name="usb_vref_ibit" pos="14:13" rst="2">
          <comment>internal bias current</comment>
        </bits>
        <bits access="rw" name="usb_vref_vbit" pos="12:10" rst="4">
          <comment>internal bias voltage</comment>
        </bits>
        <bits access="rw" name="usb_v575m_sel_bit" pos="9:7" rst="4">
          <comment>squelch threshold voltage</comment>
        </bits>
        <bits access="rw" name="usb_v125m_sel_bit" pos="6:4" rst="4">
          <comment>disconnect threshold voltage</comment>
        </bits>
        <bits access="rw" name="usb_hs_lvlout_bit" pos="3:0" rst="8">
          <comment>hi-speed differential signal voltage</comment>
        </bits>
      </reg>
      <reg name="usb_reg2" protect="rw">
        <bits access="rw" name="usb_squelch_aux" pos="14" rst="0">
          <comment>if charged(1: squelch threshold voltage is reduced;0 hold)</comment>
        </bits>
        <bits access="rw" name="usb_discnnxt_mode_sel" pos="13" rst="0">
          <comment>1: differential signal
0: single-end signal</comment>
        </bits>
        <bits access="rw" name="usb_squelch_mode_sel" pos="12" rst="0">
          <comment>1: differential signal
 0: single-end signal</comment>
        </bits>
        <bits access="rw" name="usb_vbg_sel" pos="11" rst="0">
          <comment>1: internal reference voltage
 0: bandgap voltage</comment>
        </bits>
        <bits access="rw" name="usb_pu_otg" pos="10" rst="1">
          <comment>1: enable otg
 0: disable otg</comment>
        </bits>
        <bits access="rw" name="usb_vbusvld_bit" pos="9" rst="0">
          <comment>1: set vbusvld to 1'h1; 0: not set</comment>
        </bits>
        <bits access="rw" name="usb_pu_usb_dev" pos="8" rst="1">
          <comment>if pwr_on=01:pullup and pulldown circuit power on;0 off)</comment>
        </bits>
        <bits access="rw" name="usb_pwr_on" pos="7" rst="0">
          <comment>1:pullup and pulldown circuit power always on
0:power is controled by pu_usb_dev</comment>
        </bits>
        <bits access="rw" name="usb_pu_pkd" pos="6" rst="1">
          <comment>1:enable disconnect dectector circuit
0:dsiable</comment>
        </bits>
        <bits access="rw" name="usb_pu_1v8" pos="5" rst="1">
          <comment>1:enable 1.8V voltage
0:dsiable</comment>
        </bits>
        <bits access="rw" name="usb_pu_1v2" pos="4" rst="1">
          <comment>1:enable 1.2V voltage
0:dsiable</comment>
        </bits>
        <bits access="rw" name="usb_pu_iref" pos="3" rst="1">
          <comment>1:enable current generator circuit
0:disable</comment>
        </bits>
        <bits access="rw" name="usb_pu_hsrx" pos="2" rst="1">
          <comment>1:enable hi-speed rx
0 disable</comment>
        </bits>
        <bits access="rw" name="usb_pu_hstx" pos="1" rst="1">
          <comment>1:enable hi-speed tx
0 disable</comment>
        </bits>
        <bits access="rw" name="usb_pu_lptx" pos="0" rst="1">
          <comment>1:enable full/low-speed tx
0 disable</comment>
        </bits>
      </reg>
      <reg name="usb_reg3" protect="rw">
        <bits access="rw" name="usb_det_en" pos="12" rst="0">
          <comment>enable charger ac detect</comment>
        </bits>
        <bits access="rw" name="usb_loopback" pos="11" rst="0">
          <comment>1: loopback data to tx
0: hi-speed data to tx</comment>
        </bits>
        <bits access="rw" name="usb_en_pattern" pos="10" rst="0">
          <comment>enable loopback;</comment>
        </bits>
        <bits access="rw" name="usb_pattern" pos="9:0" rst="0">
          <comment>loopback data RW</comment>
        </bits>
      </reg>
      <reg name="usb_reg4" protect="rw">
        <bits access="rw" name="usb_io33_enable" pos="10" rst="1">
          <comment>1:enable lptx bias
0: disable lptx bias(should lead power up of avdd3v3)</comment>
        </bits>
        <bits access="rw" name="usb_res_term_bit" pos="9:8" rst="2">
          <comment>hi-speed term res</comment>
        </bits>
        <bits access="rw" name="usb_lptx_drv_sel" pos="7:0" rst="255">
          <comment>full/low-speed tx driver strength;</comment>
        </bits>
      </reg>
      <reg name="usb_pll1" protect="rw">
        <bits access="rw" name="usb_pll_vreg_bit" pos="14:11" rst="8">
          <comment>internal regulator's voltage bit,default:4'h1000</comment>
        </bits>
        <bits access="rw" name="usb_reg_res_bit" pos="10:9" rst="2">
          <comment>internal regulator rout bit</comment>
        </bits>
        <bits access="rw" name="usb_pll_cpbias_ibit" pos="8:6" rst="4">
          <comment>loop filter R2 bit</comment>
        </bits>
        <bits access="rw" name="usb_pll_cpc2_ibit" pos="5:3" rst="4">
          <comment>loop filter c2 bit</comment>
        </bits>
        <bits access="rw" name="usb_pll_cpr2_ibit" pos="2:0" rst="4">
          <comment>loop filter r2 bit</comment>
        </bits>
      </reg>
      <reg name="usb_pll2" protect="rw">
        <bits access="rw" name="usb_pcon_mode" pos="6" rst="0">
          <comment>pll_presc mode selectdefault:1'h0</comment>
        </bits>
        <bits access="rw" name="usb_refmulti2_en" pos="5" rst="1">
          <comment>reference frequency select</comment>
        </bits>
        <bits access="rw" name="usb_pll_test_en" pos="4" rst="0">
          <comment>PLL TEST mode enable</comment>
        </bits>
        <bits access="rw" name="usb_sdm_clk_test_en" pos="3" rst="0">
          <comment>output clk select:
0 VCO
1 sdm_clk</comment>
        </bits>
        <bits access="rw" name="usb_vco_high_test" pos="2" rst="0">
          <comment>force VCO run at highest frequency</comment>
        </bits>
        <bits access="rw" name="usb_vco_low_test" pos="1" rst="0">
          <comment>force VCO run at lowest frequency</comment>
        </bits>
        <bits access="rw" name="usb_pll_clk_960m_en" pos="0" rst="1">
          <comment>enable 960MHz clk output</comment>
        </bits>
      </reg>
      <reg name="usb_suspend" protect="rw">
        <bits access="rw" name="usb_pu_suspend_bypass" pos="5" rst="0">
      </bits>
        <bits access="rw" name="usb_pu_otg_suspend" pos="4" rst="0">
      </bits>
        <bits access="rw" name="usb_pu_pkd_suspend" pos="3" rst="0">
      </bits>
        <bits access="rw" name="usb_pu_iref_suspend" pos="2" rst="0">
      </bits>
        <bits access="rw" name="usb_pu_hsrx_suspend" pos="1" rst="0">
      </bits>
        <bits access="rw" name="usb_pu_hstx_suspend" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="usb11_reg" protect="rw">
        <bits access="rw" name="usb11_suspend_bypass" pos="14" rst="0">
      </bits>
        <bits access="rw" name="usb11_usb_standby" pos="13" rst="0">
      </bits>
        <bits access="rw" name="usb11_usb_ctrl" pos="12:10" rst="1">
      </bits>
        <bits access="rw" name="usb11_pu_usb" pos="9" rst="1">
      </bits>
        <bits access="rw" name="usb11_io_bias_en" pos="8" rst="1">
      </bits>
        <bits access="rw" name="usb11_lptx_drvsel" pos="7:0" rst="255">
      </bits>
      </reg>
      <reg name="usb_mon" protect="r">
        <bits access="r" name="usb_dp_chr" pos="4" rst="0">
      </bits>
        <bits access="r" name="usb_dm_chr" pos="3" rst="0">
      </bits>
        <bits access="r" name="usb_correct" pos="2" rst="0">
          <comment>loopback test output</comment>
        </bits>
        <bits access="r" name="usb_lock" pos="1" rst="0">
          <comment>pll lock signal</comment>
        </bits>
        <bits access="r" name="usb_pll_lock" pos="0" rst="0">
          <comment>pll lock signal to UTMI</comment>
        </bits>
      </reg>
      <reg name="usb_reserved" protect="rw">
        <bits access="rw" name="usb_reg_resv" pos="15:0" rst="8">
          <comment>reserved for USB</comment>
        </bits>
      </reg>
      <reg name="sdm_usbpll_reg0" protect="rw">
        <bits access="rw" name="sdm_usbpll_fbc_inv" pos="8" rst="0">
      </bits>
        <bits access="rw" name="sdm_usbpll_pu" pos="7" rst="1">
      </bits>
        <bits access="rw" name="sdm_usbpll_sdm_clk_sel_rst" pos="6" rst="1">
      </bits>
        <bits access="rw" name="sdm_usbpll_sdm_clk_sel_nor" pos="5" rst="0">
      </bits>
        <bits access="rw" name="sdm_usbpll_pu_pll_dr" pos="4" rst="0">
      </bits>
        <bits access="rw" name="sdm_usbpll_pu_pll_reg" pos="3" rst="0">
      </bits>
        <bits access="rw" name="sdm_usbpll_int_dec_sel" pos="2:0" rst="3">
      </bits>
      </reg>
      <reg name="sdm_usbpll_reg1" protect="rw">
        <bits access="rw" name="sdm_usbpll_sdm_freq" pos="31:0" rst="619466436">
          <comment>960Mhz</comment>
        </bits>
      </reg>
      <reg name="sdm_usbpll_reg2" protect="rw">
        <bits access="rw" name="sdm_usbpll_dither_bypass" pos="11" rst="1">
      </bits>
        <bits access="rw" name="sdm_usbpll_sdm_resetn_dr" pos="10" rst="0">
      </bits>
        <bits access="rw" name="sdm_usbpll_sdm_resetn_reg" pos="9" rst="0">
      </bits>
        <bits access="rw" name="sdm_usbpll_sdm_reset_time_sel" pos="8:7" rst="1">
      </bits>
        <bits access="rw" name="sdm_usbpll_sdmclk_sel_time_sel" pos="6:5" rst="1">
      </bits>
        <bits access="rw" name="sdm_usbpll_clk_gen_en_reg" pos="4" rst="1">
      </bits>
        <bits access="rw" name="sdm_usbpll_clkout_en_counter_sel" pos="3:2" rst="2">
      </bits>
        <bits access="rw" name="sdm_usbpll_lock_counter_sel" pos="1:0" rst="1">
      </bits>
      </reg>
      <reg name="sdm_usbpll_reg3" protect="r">
        <bits access="r" name="sdm_usbpll_sdm_resetn" pos="2" rst="0">
      </bits>
        <bits access="r" name="sdm_usbpll_lock_steady" pos="1" rst="0">
      </bits>
        <bits access="r" name="sdm_usbpll_clk_ready" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="sdm_usbpll_reg4" protect="rw">
        <bits access="rw" name="sdm_usbpll_sdm_en" pos="29" rst="1">
      </bits>
        <bits access="rw" name="sdm_usbpll_ss_en" pos="28" rst="0">
      </bits>
        <bits access="rw" name="sdm_usbpll_ss_devi" pos="27:16" rst="0">
      </bits>
        <bits access="rw" name="sdm_usbpll_ss_devi_step" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="usb_digphy_ana1" protect="rw">
        <bits access="rw" name="usb_digphy_ana_1" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="usb_digphy_ana2" protect="rw">
        <bits access="rw" name="usb_digphy_ana_2" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="usb_digphy_ana3" protect="rw">
        <bits access="rw" name="usb_digphy_ana_3" pos="31:0" rst="32">
      </bits>
      </reg>
      <reg name="usb_digphy_ana4" protect="rw">
        <bits access="rw" name="usb_digphy_ana_4" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="usb11_digphy_ana_reg" protect="rw">
        <bits access="rw" name="usb11_digphy_ana" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="352"/>
      <reg name="ddr_pad_cfg" protect="rw">
        <bits access="rw" name="ddr_latch" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_pad_cfg" protect="rw">
        <bits access="rw" name="psram_latch" pos="0" rst="0">
      </bits>
      </reg>
      <hole size="448"/>
      <reg name="sdm_dsipll_reg0" protect="rw">
        <bits access="rw" name="sdm_dsipll_fbc_inv" pos="8" rst="0">
      </bits>
        <bits access="rw" name="sdm_dsipll_pu" pos="7" rst="1">
      </bits>
        <bits access="rw" name="sdm_dsipll_sdm_clk_sel_rst" pos="6" rst="1">
      </bits>
        <bits access="rw" name="sdm_dsipll_sdm_clk_sel_nor" pos="5" rst="0">
      </bits>
        <bits access="rw" name="sdm_dsipll_pu_pll_dr" pos="4" rst="0">
      </bits>
        <bits access="rw" name="sdm_dsipll_pu_pll_reg" pos="3" rst="0">
      </bits>
        <bits access="rw" name="sdm_dsipll_int_dec_sel" pos="2:0" rst="3">
      </bits>
      </reg>
      <reg name="sdm_dsipll_reg1" protect="rw">
        <bits access="rw" name="sdm_dsipll_sdm_freq" pos="31:0" rst="645277538">
          <comment>freq/26*2^25    1000Mhz</comment>
        </bits>
      </reg>
      <reg name="sdm_dsipll_reg2" protect="rw">
        <bits access="rw" name="sdm_dsipll_dither_bypass" pos="11" rst="1">
      </bits>
        <bits access="rw" name="sdm_dsipll_sdm_resetn_dr" pos="10" rst="0">
      </bits>
        <bits access="rw" name="sdm_dsipll_sdm_resetn_reg" pos="9" rst="0">
      </bits>
        <bits access="rw" name="sdm_dsipll_sdm_reset_time_sel" pos="8:7" rst="1">
      </bits>
        <bits access="rw" name="sdm_dsipll_sdmclk_sel_time_sel" pos="6:5" rst="1">
      </bits>
        <bits access="rw" name="sdm_dsipll_clk_gen_en_reg" pos="4" rst="1">
      </bits>
        <bits access="rw" name="sdm_dsipll_clkout_en_counter_sel" pos="3:2" rst="2">
      </bits>
        <bits access="rw" name="sdm_dsipll_lock_counter_sel" pos="1:0" rst="1">
      </bits>
      </reg>
      <reg name="sdm_dsipll_reg3" protect="r">
        <bits access="r" name="sdm_dsipll_sdm_resetn" pos="2" rst="0">
      </bits>
        <bits access="r" name="sdm_dsipll_lock_steady" pos="1" rst="0">
      </bits>
        <bits access="r" name="sdm_dsipll_clk_ready" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="sdm_dsipll_reg4" protect="rw">
        <bits access="rw" name="sdm_dsipll_sdm_en" pos="29" rst="1">
      </bits>
        <bits access="rw" name="sdm_dsipll_ss_en" pos="28" rst="0">
      </bits>
        <bits access="rw" name="sdm_dsipll_ss_devi" pos="27:16" rst="0">
      </bits>
        <bits access="rw" name="sdm_dsipll_ss_devi_step" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="mipi_lvds_phy_reg" protect="rw">
        <bits access="rw" name="lvdspll_refmulti2_en" pos="3" rst="1">
      </bits>
        <bits access="rw" name="lvdspll_sdm_sel" pos="2" rst="1">
      </bits>
        <bits access="rw" name="lvds_rx_terminal_enable" pos="1" rst="0">
      </bits>
        <bits access="rw" name="csi_lvds_mode" pos="0" rst="1">
      </bits>
      </reg>
      <hole size="320"/>
      <reg name="pad_ctrl_resv" protect="rw">
        <bits access="rw" name="reg_pad_ctrl_resv" pos="31:0" rst="0">
          <comment>reserved</comment>
        </bits>
      </reg>
      <reg name="pad_resetb_cfg" protect="rw">
        <bits access="rw" name="pad_resetb_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_resetb_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_resetb_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_resetb_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_adi_cfg" protect="rw">
        <bits access="rw" name="pad_adi_scl_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_adi_scl_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_adi_scl_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_adi_scl_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_adi_sda_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_adi_sda_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_adi_sda_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_adi_sda_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_adi_sync_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_adi_sync_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_adi_sync_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_adi_sync_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_ap_jtag_cfg" protect="rw">
        <bits access="rw" name="pad_ap_jtag_tck_drv" pos="24:23" rst="2">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tck_ie" pos="22" rst="1">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tck_se" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tck_wpus" pos="20" rst="0">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_drv" pos="19:18" rst="2">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_ie" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_se" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tdi_wpus" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tdo_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tms_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tms_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tms_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_ap_jtag_tms_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_ap_jtag_trst_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_ap_jtag_trst_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_ap_jtag_trst_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_ap_jtag_trst_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_spi_camera_cfg" protect="rw">
        <bits access="rw" name="pad_spi_camera_sck_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_camera_sck_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_camera_sck_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_camera_sck_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_camera_si_0_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_camera_si_0_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_camera_si_0_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_camera_si_0_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_camera_si_1_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_camera_si_1_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_camera_si_1_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_camera_si_1_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_camera_cfg" protect="rw">
        <bits access="rw" name="pad_camera_wpdi" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_camera_pwdn_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_camera_pwdn_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_camera_pwdn_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_camera_pwdn_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_camera_ref_clk_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_camera_ref_clk_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_camera_ref_clk_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_camera_ref_clk_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_camera_rst_l_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_camera_rst_l_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_camera_rst_l_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_camera_rst_l_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_debug_host_cfg" protect="rw">
        <bits access="rw" name="pad_debug_host_clk_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_debug_host_clk_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_debug_host_clk_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_debug_host_clk_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_debug_host_rx_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_debug_host_rx_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_debug_host_rx_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_debug_host_rx_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_debug_host_tx_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_debug_host_tx_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_debug_host_tx_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_debug_host_tx_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_gpio_cfg1" protect="rw">
        <bits access="rw" name="pad_gpio_0_drv" pos="19:18" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_0_ie" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_0_se" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_0_wpus" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_1_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_1_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_1_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_1_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_2_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_2_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_2_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_2_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_3_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_3_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_3_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_3_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_gpio_cfg2" protect="rw">
        <bits access="rw" name="pad_gpio_4_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_4_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_4_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_4_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_5_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_5_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_5_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_5_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_7_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_7_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_7_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_7_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_gpo_cfg" protect="rw">
        <bits access="rw" name="pad_gpio_8_drv" pos="24:23" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_8_ie" pos="22" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_8_se" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_8_wpus" pos="20" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_9_drv" pos="19:18" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_9_ie" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_9_se" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_9_wpus" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_10_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_10_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_10_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_10_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_11_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_11_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_11_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_11_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_12_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_12_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_12_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_12_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_i2c_cfg" protect="rw">
        <bits access="rw" name="pad_i2c_m1_scl_drv" pos="19:18" rst="2">
      </bits>
        <bits access="rw" name="pad_i2c_m1_scl_ie" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pad_i2c_m1_scl_se" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pad_i2c_m1_scl_wpus" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_i2c_m1_sda_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_i2c_m1_sda_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_i2c_m1_sda_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_i2c_m1_sda_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_14_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_14_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_14_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_14_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_15_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_15_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_15_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_15_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_aud_ad_cfg" protect="rw">
        <bits access="rw" name="pad_aud_ad_d0_drv" pos="29:28" rst="2">
      </bits>
        <bits access="rw" name="pad_aud_ad_d0_ie" pos="27" rst="1">
      </bits>
        <bits access="rw" name="pad_aud_ad_d0_se" pos="26" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_ad_d0_wpus" pos="25" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_ad_sync_drv" pos="24:23" rst="2">
      </bits>
        <bits access="rw" name="pad_aud_ad_sync_ie" pos="22" rst="1">
      </bits>
        <bits access="rw" name="pad_aud_ad_sync_se" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_ad_sync_wpus" pos="20" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_da_d0_drv" pos="19:18" rst="2">
      </bits>
        <bits access="rw" name="pad_aud_da_d0_ie" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pad_aud_da_d0_se" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_da_d0_wpus" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_da_d1_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_aud_da_d1_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_aud_da_d1_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_da_d1_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_da_sync_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_aud_da_sync_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_aud_da_sync_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_da_sync_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_sclk_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_aud_sclk_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_aud_sclk_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_aud_sclk_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_keyin_cfg" protect="rw">
        <bits access="rw" name="pad_key_wpdi" pos="30" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_0_drv" pos="29:28" rst="2">
      </bits>
        <bits access="rw" name="pad_keyin_0_ie" pos="27" rst="1">
      </bits>
        <bits access="rw" name="pad_keyin_0_se" pos="26" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_0_wpus" pos="25" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_1_drv" pos="24:23" rst="2">
      </bits>
        <bits access="rw" name="pad_keyin_1_ie" pos="22" rst="1">
      </bits>
        <bits access="rw" name="pad_keyin_1_se" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_1_wpus" pos="20" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_2_drv" pos="19:18" rst="2">
      </bits>
        <bits access="rw" name="pad_keyin_2_ie" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pad_keyin_2_se" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_2_wpus" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_3_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_keyin_3_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_keyin_3_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_3_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_4_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_keyin_4_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_keyin_4_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_4_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_5_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_keyin_5_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_keyin_5_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_keyin_5_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_keyout_cfg" protect="rw">
        <bits access="rw" name="pad_keyout_0_drv" pos="29:28" rst="2">
      </bits>
        <bits access="rw" name="pad_keyout_0_ie" pos="27" rst="1">
      </bits>
        <bits access="rw" name="pad_keyout_0_se" pos="26" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_0_wpus" pos="25" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_1_drv" pos="24:23" rst="2">
      </bits>
        <bits access="rw" name="pad_keyout_1_ie" pos="22" rst="1">
      </bits>
        <bits access="rw" name="pad_keyout_1_se" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_1_wpus" pos="20" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_2_drv" pos="19:18" rst="2">
      </bits>
        <bits access="rw" name="pad_keyout_2_ie" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pad_keyout_2_se" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_2_wpus" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_3_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_keyout_3_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_keyout_3_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_3_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_4_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_keyout_4_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_keyout_4_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_4_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_5_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_keyout_5_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_keyout_5_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_keyout_5_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_lcd_cfg" protect="rw">
        <bits access="rw" name="pad_lcd_msen" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_lcd_ms" pos="14" rst="0">
      </bits>
        <bits access="rw" name="pad_lcd_fmark_drv" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pad_lcd_fmark_ie" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pad_lcd_fmark_se" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_lcd_fmark_spu" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_lcd_rstb_drv" pos="6:3" rst="2">
      </bits>
        <bits access="rw" name="pad_lcd_rstb_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_lcd_rstb_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_lcd_rstb_spu" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_gpio13_cfg" protect="rw">
        <bits access="rw" name="pad_mipidsi_wpdi" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_misc_l_wpdi" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_misc_r_wpdi" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_13_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_13_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_13_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_13_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_rfdig_gpio_cfg1" protect="rw">
        <bits access="rw" name="pad_rf_wpdi" pos="25" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_drv" pos="24:23" rst="2">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_ie" pos="22" rst="1">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_se" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_0_wpus" pos="20" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_drv" pos="19:18" rst="2">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_ie" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_se" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_1_wpus" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_2_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_3_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_4_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_rfdig_gpio_cfg2" protect="rw">
        <bits access="rw" name="pad_rfdig_gpio_5_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_5_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_5_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_5_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_6_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_rfdig_gpio_7_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_sdmmc1_others_cfg" protect="rw">
        <bits access="rw" name="pad_sdmmc1_ms" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_msen" pos="14" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_clk_drv" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pad_sdmmc1_clk_ie" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pad_sdmmc1_clk_se" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_clk_spu" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_drv" pos="6:3" rst="2">
      </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_cmd_spu" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_sdmmc1_data_cfg" protect="rw">
        <bits access="rw" name="pad_sdmmc1_data_0_drv" pos="27:24" rst="2">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_0_ie" pos="23" rst="1">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_0_se" pos="22" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_0_spu" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_drv" pos="20:17" rst="2">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_ie" pos="16" rst="1">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_se" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_1_spu" pos="14" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_drv" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_ie" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_se" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_2_spu" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_drv" pos="6:3" rst="2">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_sdmmc1_data_3_spu" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_sim_1_cfg" protect="rw">
        <bits access="rw" name="pad_sim_1_ms" pos="22" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_1_msen" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_1_clk_drv" pos="20:17" rst="2">
      </bits>
        <bits access="rw" name="pad_sim_1_clk_ie" pos="16" rst="1">
      </bits>
        <bits access="rw" name="pad_sim_1_clk_se" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_1_clk_spu" pos="14" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_1_dio_drv" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pad_sim_1_dio_ie" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pad_sim_1_dio_se" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_1_dio_spu" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_1_rst_drv" pos="6:3" rst="2">
      </bits>
        <bits access="rw" name="pad_sim_1_rst_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_sim_1_rst_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_1_rst_spu" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_sim_2_cfg" protect="rw">
        <bits access="rw" name="pad_sim_2_ms" pos="22" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_2_msen" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_2_clk_drv" pos="20:17" rst="2">
      </bits>
        <bits access="rw" name="pad_sim_2_clk_ie" pos="16" rst="1">
      </bits>
        <bits access="rw" name="pad_sim_2_clk_se" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_2_clk_spu" pos="14" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_2_dio_drv" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pad_sim_2_dio_ie" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pad_sim_2_dio_se" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_2_dio_spu" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_2_rst_drv" pos="6:3" rst="2">
      </bits>
        <bits access="rw" name="pad_sim_2_rst_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_sim_2_rst_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_sim_2_rst_spu" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_spi_flash_cfg1" protect="rw">
        <bits access="rw" name="pad_nand_flash_sel_drv" pos="25:24" rst="2">
      </bits>
        <bits access="rw" name="pad_nand_flash_sel_ie" pos="23" rst="1">
      </bits>
        <bits access="rw" name="pad_nand_flash_sel_se" pos="22" rst="0">
      </bits>
        <bits access="rw" name="pad_nand_flash_sel_wpus" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_sel_drv" pos="20:17" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_flash_sel_ie" pos="16" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_flash_sel_se" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_sel_spu" pos="14" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_clk_drv" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_flash_clk_ie" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_flash_clk_se" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_clk_spu" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_cs_drv" pos="6:3" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_flash_cs_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_flash_cs_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_cs_spu" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_spi_flash_cfg2" protect="rw">
        <bits access="rw" name="pad_spi_flash_ms" pos="29" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_msen" pos="28" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_drv" pos="27:24" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_ie" pos="23" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_se" pos="22" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_0_spu" pos="21" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_drv" pos="20:17" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_ie" pos="16" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_se" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_1_spu" pos="14" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_drv" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_ie" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_se" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_2_spu" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_drv" pos="6:3" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_flash_sio_3_spu" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_spi_lcd_cfg1" protect="rw">
        <bits access="rw" name="pad_spi_lcd_clk_drv" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_lcd_clk_ie" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_lcd_clk_se" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_lcd_clk_spu" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_lcd_cs_drv" pos="6:3" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_lcd_cs_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_lcd_cs_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_lcd_cs_spu" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_spi_lcd_cfg2" protect="rw">
        <bits access="rw" name="pad_spi_lcd_sdc_drv" pos="20:17" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_lcd_sdc_ie" pos="16" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_lcd_sdc_se" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_lcd_sdc_spu" pos="14" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_lcd_select_drv" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_lcd_select_ie" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_lcd_select_se" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_lcd_select_spu" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_lcd_sio_drv" pos="6:3" rst="2">
      </bits>
        <bits access="rw" name="pad_spi_lcd_sio_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_spi_lcd_sio_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_spi_lcd_sio_spu" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_tst_cfg" protect="rw">
        <bits access="rw" name="pad_tst_h_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_tst_h_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_tst_h_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_tst_h_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_uart_1_cfg" protect="rw">
        <bits access="rw" name="pad_gpio_18_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_18_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_18_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_18_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_19_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_19_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_19_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_19_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_uart_2_cfg" protect="rw">
        <bits access="rw" name="pad_gpio_22_drv" pos="19:18" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_22_ie" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_22_se" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_22_wpus" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_23_drv" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_23_ie" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_23_se" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_23_wpus" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_20_drv" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_20_ie" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_20_se" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_20_wpus" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_21_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_21_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_gpio_21_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_21_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pad_secure_boot_mode_cfg" protect="rw">
        <bits access="rw" name="pad_secure_boot_mode_drv" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="pad_secure_boot_mode_ie" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pad_secure_boot_mode_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_secure_boot_mode_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <hole size="64"/>
      <reg name="resv0" protect="rw">
        <bits access="rw" name="reg_resv0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv1" protect="rw">
        <bits access="rw" name="reg_resv1" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv2" protect="rw">
        <bits access="rw" name="reg_resv2" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv3" protect="rw">
        <bits access="rw" name="reg_resv3" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv4" protect="rw">
        <bits access="rw" name="reg_resv4" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv5" protect="rw">
        <bits access="rw" name="reg_resv5" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv6" protect="rw">
        <bits access="rw" name="reg_resv6" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv7" protect="rw">
        <bits access="rw" name="reg_resv7" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv8" protect="rw">
        <bits access="rw" name="reg_resv8" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv9" protect="rw">
        <bits access="rw" name="reg_resv9" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv10" protect="rw">
        <bits access="rw" name="reg_resv10" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv11" protect="rw">
        <bits access="rw" name="reg_resv11" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv12" protect="rw">
        <bits access="rw" name="reg_resv12" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv13" protect="rw">
        <bits access="rw" name="reg_resv13" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv14" protect="rw">
        <bits access="rw" name="reg_resv14" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="resv15" protect="rw">
        <bits access="rw" name="reg_resv15" pos="31:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="lvds.xml">
    <module category="ANALOG_IF" name="LVDS">
      <reg name="dlhssb_en" protect="rw">
        <bits access="rw" name="config_dlhssb_en" pos="1:0" rst="0">
          <comment>2 dedicated enable for 2 DL HSSBs, bit0-lane0, bit1-lane1</comment>
        </bits>
      </reg>
      <reg name="ulhssb_en" protect="rw">
        <bits access="rw" name="config_ulhssb_en" pos="1:0" rst="0">
          <comment>2 dedicated enable for 2 UL HSSBs, bit0-lane0, bit1-lane1</comment>
        </bits>
      </reg>
      <reg name="dlfifo_clr" protect="rw">
        <bits access="rw" name="config_dlfifo_clr" pos="0:0" rst="0">
          <comment>DL FIFO reset and clear</comment>
        </bits>
      </reg>
      <reg name="ulfifo_clr" protect="rw">
        <bits access="rw" name="config_ulfifo_clr" pos="0:0" rst="0">
          <comment>UL FIFO reset and clear</comment>
        </bits>
      </reg>
      <reg name="syncword10b_d" protect="rw">
        <bits access="rw" name="config_syncword10b_d" pos="7:0" rst="90">
          <comment>SYNC WORD for lvds dest</comment>
        </bits>
      </reg>
      <reg name="syncword10b_s" protect="rw">
        <bits access="rw" name="config_syncword10b_s" pos="7:0" rst="90">
          <comment>SYNC WORD for lvds src</comment>
        </bits>
      </reg>
      <reg name="reverse_mode_en" protect="rw">
        <bits access="rw" name="config_reverse_mode_en" pos="0:0" rst="0">
          <comment>bit reverse enable</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="syncidx0" protect="rw">
        <bits access="rw" name="config_sync_idx0" pos="3:0" rst="0">
          <comment>bit offset index used in byte training stage for lane0</comment>
        </bits>
      </reg>
      <reg name="syncidx1" protect="rw">
        <bits access="rw" name="config_sync_idx1" pos="3:0" rst="0">
          <comment>bit offset index used in byte training stage for lane1</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="rx_byte_training_ok" protect="rw">
        <bits access="rw" name="config_rx_byte_training_ok" pos="0:0" rst="0">
          <comment>Byte Training Done from SW</comment>
        </bits>
      </reg>
      <reg name="rx_bit_training_ok" protect="rw">
        <bits access="rw" name="config_rx_bit_training_ok" pos="0:0" rst="0">
          <comment>Bit Training Done from SW</comment>
        </bits>
      </reg>
      <reg name="ulrdy" protect="rw">
        <bits access="rw" name="config_ul_rdy" pos="0:0" rst="0">
          <comment>data ready from DFE for ulfifo to lvds</comment>
        </bits>
      </reg>
      <reg name="len_payload" protect="rw">
        <bits access="rw" name="config_len_payload" pos="9:0" rst="0">
          <comment>Payload max length for timeout check, 0-disabled</comment>
        </bits>
      </reg>
      <reg name="len_sync" protect="rw">
        <bits access="rw" name="config_len_sync" pos="9:0" rst="0">
          <comment>Sync max length for timeout check, 0-disabled</comment>
        </bits>
      </reg>
      <reg name="fix_pattern" protect="rw">
        <bits access="rw" name="config_fix_pattern" pos="0:0" rst="0">
          <comment>LVDS tx fixed pattern instead of data from ulfifo</comment>
        </bits>
      </reg>
      <reg name="pattern0" protect="rw">
        <bits access="rw" name="config_pattern0" pos="31:0" rst="4294967295">
          <comment>LVDS tx fixed pattern0[31:0]</comment>
        </bits>
      </reg>
      <reg name="pattern1" protect="rw">
        <bits access="rw" name="config_pattern1" pos="31:0" rst="0">
          <comment>LVDS tx fixed pattern1[31:0]</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="sample_width" protect="rw">
        <bits access="rw" name="config_sample_width" pos="1:0" rst="0">
          <comment>[1]: 0-2 cycles per word , 1-1cycle per word for  LVDS_TX
[0]: 0-2 cycles per word , 1-1cycle per word for  LVDS_RX</comment>
        </bits>
      </reg>
      <reg name="downsample" protect="rw">
        <bits access="rw" name="config_mode_mt_tx" pos="11:10" rst="0">
          <comment>0-mode0, 1-mode1, 2-mode2, 3-mode3 for tx</comment>
        </bits>
        <bits access="rw" name="config_mode_mt_rx" pos="9:8" rst="0">
          <comment>0-mode0, 1-mode1, 2-mode2, 3-mode3 for rx</comment>
        </bits>
        <bits access="rw" name="config_rate_cnt_tx" pos="7:6" rst="0">
          <comment>number of cycles to read from Fifo under MT mode for both tx</comment>
        </bits>
        <bits access="rw" name="config_rate_cnt_rx" pos="5:4" rst="0">
          <comment>number of cycles to read from Fifo under MT mode for both rx</comment>
        </bits>
        <bits access="rw" name="config_mt_en" pos="3:2" rst="0">
          <comment>[3]: 0- Non-MT mode, 1-MT enable for rx
[2]: 0- Non-MT mode, 1-MT enable for tx</comment>
        </bits>
        <bits access="rw" name="config_1x2x" pos="1:0" rst="0">
          <comment>[1]: 0-1x clock, 1-2x clock for rx
[0]: 0-1x clock, 1-2x clock for tx</comment>
        </bits>
      </reg>
      <reg name="tx_bit_training_ok" protect="rw">
        <bits access="rw" name="config_tx_bit_training_ok" pos="0:0" rst="0">
          <comment>bit training Done for lvds tx</comment>
        </bits>
      </reg>
      <reg name="tx_byte_training_ok" protect="rw">
        <bits access="rw" name="config_tx_byte_training_ok" pos="0:0" rst="0">
          <comment>byte training Done for lvds tx</comment>
        </bits>
      </reg>
      <reg name="latch_word0_0" protect="r">
        <bits access="r" name="reg_latch_word0_0" pos="31:0" rst="0">
          <comment>report bit or byte training results word0 for lane0</comment>
        </bits>
      </reg>
      <reg name="latch_word0_1" protect="r">
        <bits access="r" name="reg_latch_word0_1" pos="31:0" rst="0">
          <comment>report bit or byte training results word1 for lane0</comment>
        </bits>
      </reg>
      <reg name="latch_word1_0" protect="r">
        <bits access="r" name="reg_latch_word1_0" pos="31:0" rst="0">
          <comment>report bit or byte training results word0 for lane1</comment>
        </bits>
      </reg>
      <reg name="latch_word1_1" protect="r">
        <bits access="r" name="reg_latch_word1_1" pos="31:0" rst="0">
          <comment>report bit or byte training results word1 for lane1</comment>
        </bits>
      </reg>
      <reg name="state_monitor" protect="r">
        <bits access="r" name="dest_lane1_fstate" pos="29:27" rst="0">
          <comment>dest_lane1_fstate</comment>
        </bits>
        <bits access="r" name="dest_lane0_fstate" pos="26:24" rst="0">
          <comment>dest_lane0_fstate</comment>
        </bits>
        <bits access="r" name="dest_lane1_state" pos="23:21" rst="0">
          <comment>dest_lane1_state</comment>
        </bits>
        <bits access="r" name="dest_lane1_mstate" pos="20:18" rst="0">
          <comment>dest_lane1_mstate</comment>
        </bits>
        <bits access="r" name="dest_lane0_state" pos="17:15" rst="0">
          <comment>dest_lane0_state</comment>
        </bits>
        <bits access="r" name="dest_lane0_mstate" pos="14:12" rst="0">
          <comment>dest_lane0_mstate</comment>
        </bits>
        <bits access="r" name="src_lane1_state" pos="11:9" rst="0">
          <comment>src_lane1_state</comment>
        </bits>
        <bits access="r" name="src_lane1_mstate" pos="8:6" rst="0">
          <comment>src_lane1_mstate</comment>
        </bits>
        <bits access="r" name="src_lane0_state" pos="5:3" rst="0">
          <comment>src_lane0_state</comment>
        </bits>
        <bits access="r" name="src_lane0_mstate" pos="2:0" rst="0">
          <comment>src_lane0_mstate</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="res_lvds_bb" protect="rw">
        <bits access="rw" name="config_res_lvds_bb" pos="15:0" rst="0">
          <comment>reserved register for lvds bb
[15]: for RX, 1-use SW configure Sync index enable, 0-use HW anto sync detection
[14]: for TX, 1-use SW configure Sync index enable, 0-use HW anto sync detection
[13]: for RX, 1-use LFSR for BIST , 0-use normal data for RX
[12]: for TX, 1-use LFSR for BIST , 0-use normal data for TX</comment>
        </bits>
      </reg>
      <reg name="clock_lvds" protect="rw">
        <bits access="rw" name="config_clock_lvds" pos="15:0" rst="0">
          <comment>configure register for lvds used by IQMUX:
[15:12]: reserved
[11]: software reset for LVDS digital TX
[10]: software reset for LVDS digital RX
[9]:   software reset for LVDS analog TX
[8]:   software reset for LVDS analog RX
[7:3]:   reserved
[2]:   clock gating enable for MT clock divided from mt2lvds@61.44MHz clock.
[1]:   clock gating enable to LVDS digital rx related clocks
[0]:   clock gating enable to LVDS digital tx related clocks</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="latch" protect="rw">
        <bits access="rw" name="config_latch" pos="0:0" rst="0">
          <comment>Latch trigger for capturing 8 lvds received Bytes</comment>
        </bits>
      </reg>
      <reg name="header_config" protect="rw">
        <bits access="rw" name="config_header" pos="10:3" rst="255">
          <comment>header to be received or transmitted for LVDS</comment>
        </bits>
        <bits access="rw" name="config_header_len" pos="2:0" rst="0">
          <comment>number of header to be received or transmitted for LVDS</comment>
        </bits>
      </reg>
      <reg name="rx_state_status" protect="r">
        <bits access="r" name="lvds_rx_state_machine" pos="5:0" rst="0">
          <comment>mstate and fstate machine rerport for lvds_rx debug purpose</comment>
        </bits>
      </reg>
      <reg name="tx_state_status" protect="r">
        <bits access="r" name="lvds_tx_state_machine" pos="5:0" rst="0">
          <comment>mstate and state machine rerport for lvds_tx debug purpose</comment>
        </bits>
      </reg>
      <reg name="rx_pll_stable_time" protect="rw">
        <bits access="rw" name="lvds_rx_pll_stable_time" pos="15:0" rst="0">
          <comment>16 bit counter for LVDS_RX PLL stable time wait</comment>
        </bits>
      </reg>
      <reg name="tx_pll_stable_time" protect="rw">
        <bits access="rw" name="lvds_tx_pll_stable_time" pos="15:0" rst="0">
          <comment>16 bit counter for LVDS_TX PLL stable time wait</comment>
        </bits>
      </reg>
      <reg name="interrupt" protect="r">
        <bits access="r" name="lvds_interrupt_raw" pos="1:1" rst="0">
          <comment>raw interrupt status, write 1 to clear</comment>
        </bits>
        <bits access="r" name="lvds_interrupt" pos="0:0" rst="0">
          <comment>interrupt status after masked raw interrupt status</comment>
        </bits>
      </reg>
      <reg name="interrupt_ctrl" protect="rw">
        <bits access="rw" name="lvds_interrupt_clear" pos="4:4" rst="0">
          <comment>write 1 to clear interrupt</comment>
        </bits>
        <bits access="rw" name="lvds_interrupt_source_sel" pos="3:1" rst="0">
          <comment>raw interrupt source select</comment>
        </bits>
        <bits access="rw" name="lvds_interrupt_mask" pos="0:0" rst="0">
          <comment>raw interrupt mask for latch done</comment>
        </bits>
      </reg>
      <reg name="lane0_bist_result" protect="r">
        <bits access="r" name="bist_error_cnt_lane0" pos="16:1" rst="0">
          <comment>number of errors for lvds lane0 bist enabled period</comment>
        </bits>
        <bits access="r" name="bist_fail_ind_lane0" pos="0:0" rst="0">
          <comment>1: bist fail for lane0, 0: bist pass for lane0</comment>
        </bits>
      </reg>
      <reg name="lane1_bist_result" protect="r">
        <bits access="r" name="bist_error_cnt_lane1" pos="16:1" rst="0">
          <comment>number of errors for lvds lane1 bist enabled period</comment>
        </bits>
        <bits access="r" name="bist_fail_ind_lane1" pos="0:0" rst="0">
          <comment>1: bist fail for lane1, 0: bist pass for lane0</comment>
        </bits>
      </reg>
      <hole size="544"/>
      <reg name="lvds_reset" protect="rw">
        <bits access="rw" name="lvds_rx_rstn" pos="1:1" rst="1">
          <comment>reset for LVDS RX path, active low</comment>
        </bits>
        <bits access="rw" name="lvds_tx_rstn" pos="0:0" rst="1">
          <comment>soft reset for LVDS TX path, active low</comment>
        </bits>
      </reg>
      <reg name="clk_band" protect="rw">
        <bits access="rw" name="lvds_clk_band" pos="3:0" rst="1">
          <comment>reg for PLL divisor
lvds_clk_band=3'b0001 with pll_din=7'h08
lvds_clk_band=3'b0010 with pll_din=7'h10
lvds_clk_band=3'b0100 with pll_din=7'h20
lvds_clk_band=3'b1000 with pll_din=7'h40</comment>
        </bits>
      </reg>
      <reg name="phase_sel" protect="rw">
        <bits access="rw" name="lvds_phase_sel" pos="2:0" rst="4">
          <comment>1st phase coarse tuning between TX_DATA and TX_CLOCK</comment>
        </bits>
      </reg>
      <reg name="rx_data_pnsw" protect="rw">
        <bits access="rw" name="lvds_rx_data_pnsw" pos="1:0" rst="0">
          <comment>input P and N switch</comment>
        </bits>
      </reg>
      <reg name="rx_dl8p_sel" protect="rw">
        <bits access="rw" name="lvds_rx_dl8p_sel" pos="31:0" rst="0">
          <comment>phase fine tuning between RX_DATA and RX_CLOCK</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="rx_dl128p_sel" protect="rw">
        <bits access="rw" name="lvds_rx_dl128p_sel" pos="13:0" rst="0">
          <comment>phase coarse tuning between RX_DATA and RX_CLOCK</comment>
        </bits>
      </reg>
      <reg name="rx_pu_diff2cmos" protect="rw">
        <bits access="rw" name="lvds_rx_pu_diff2cmos" pos="4:0" rst="0">
          <comment>RX BUFFER enable</comment>
        </bits>
      </reg>
      <reg name="rx_vcom_sel" protect="rw">
        <bits access="rw" name="lvds_rx_vcom_sel" pos="4:0" rst="0">
          <comment>RX BUFFER select</comment>
        </bits>
      </reg>
      <reg name="tx_dl8p_sel" protect="rw">
        <bits access="rw" name="lvds_tx_dl8p_sel" pos="14:0" rst="0">
          <comment>phase fine tuning between TX_DATA and TX_CLOCK</comment>
        </bits>
      </reg>
      <reg name="tx_dl128p_sel" protect="rw">
        <bits access="rw" name="lvds_tx_dl128p_sel" pos="6:0" rst="0">
          <comment>2nd phase coarse tuning between TX_DATA and TX_CLOCK</comment>
        </bits>
      </reg>
      <reg name="tx_hz_enable" protect="rw">
        <bits access="rw" name="lvds_tx_hz_enable" pos="4:0" rst="31">
          <comment>LVDS DRIVER tri-state enable</comment>
        </bits>
      </reg>
      <reg name="tx_iref_bit" protect="rw">
        <bits access="rw" name="lvds_tx_iref_bit" pos="3:0" rst="8">
          <comment>LVDS DRIVER strength adjust</comment>
        </bits>
      </reg>
      <reg name="tx_vcm_bit" protect="rw">
        <bits access="rw" name="lvds_tx_vcm_bit" pos="2:0" rst="4">
          <comment>LVDS DRIVER output common mode voltage adjust</comment>
        </bits>
      </reg>
      <reg name="tx_vdm_bit" protect="rw">
        <bits access="rw" name="lvds_tx_vdm_bit" pos="2:0" rst="4">
          <comment>LVDS DRIVER output difference mode voltage adjust</comment>
        </bits>
      </reg>
      <reg name="reg_res" protect="rw">
        <bits access="rw" name="lvds_reg_res" pos="31:0" rst="2228240">
          <comment>LVDS reserved register
[2:0]:pll_rx_clk_ref_dig
[4]:pll_rx_clk_ref_dig_enable
[20:18]:pll_rx_clk_ref_xtal
[17]:pll_rx_clk_ref_xtal_enable</comment>
        </bits>
      </reg>
      <reg name="pll_refdiv2_enable" protect="rw">
        <bits access="rw" name="lvds_pll_refdiv2_enable" pos="0:0" rst="0">
          <comment>enable for PLL reference clock being input clock divided by 2</comment>
        </bits>
      </reg>
      <reg name="pll_clk_rstb" protect="rw">
        <bits access="rw" name="lvds_pll_clk_rstb" pos="0:0" rst="0">
          <comment>PLL output clock enable</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="pll_din" protect="rw">
        <bits access="rw" name="lvds_pll_din" pos="6:0" rst="8">
          <comment>set with lvds_clk_band</comment>
        </bits>
      </reg>
      <reg name="pll_pcon" protect="rw">
        <bits access="rw" name="lvds_pll_pcon" pos="2:0" rst="0">
          <comment>PLL divisor decimal part,fixed to 0</comment>
        </bits>
      </reg>
      <reg name="pll_refmulti2_enable" protect="rw">
        <bits access="rw" name="lvds_pll_refmulti2_en" pos="0:0" rst="0">
          <comment>PLL refmulit2 enable</comment>
        </bits>
      </reg>
      <hole size="192"/>
      <reg name="pll_vreg_bit" protect="rw">
        <bits access="rw" name="lvds_pll_vreg_bit" pos="3:0" rst="8">
          <comment>PLL Regulator voltage adjust</comment>
        </bits>
      </reg>
      <reg name="pu_pll" protect="rw">
        <bits access="rw" name="lvds_pu_pll" pos="0:0" rst="0">
          <comment>PLL power up</comment>
        </bits>
      </reg>
      <reg name="pll_lock" protect="r">
        <bits access="r" name="lvds_pll_lock" pos="0:0" rst="0">
          <comment>PLL lock status
0:unlock
1:lock</comment>
        </bits>
      </reg>
      <reg name="pll_reg0" protect="rw">
        <bits access="rw" name="lvds_pll_reg0" pos="15:0" rst="3106">
          <comment>PLL 1st  reserved register</comment>
        </bits>
      </reg>
      <reg name="pll_reg1" protect="rw">
        <bits access="rw" name="lvds_pll_reg1" pos="15:0" rst="128">
          <comment>PLL 2nd  reserved register</comment>
        </bits>
      </reg>
      <reg name="lvds_monitor_select" protect="rw">
        <bits access="rw" name="lvds_monitor_sel" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="lane1_pattern0" protect="rw">
        <bits access="rw" name="config_lane1_pattern0" pos="31:0" rst="4294967295">
          <comment>LVDS tx fixed pattern0[31:0]</comment>
        </bits>
      </reg>
      <reg name="lane1_pattern1" protect="rw">
        <bits access="rw" name="config_lane1_pattern1" pos="31:0" rst="0">
          <comment>LVDS tx fixed pattern1[31:0]</comment>
        </bits>
      </reg>
      <reg name="lvds2dfe_latch_reg_0" protect="r">
        <bits access="r" name="lvds2dfe_latch_reg0" pos="31:0" rst="0">
          <comment>LVDS2DFE latch reg0</comment>
        </bits>
      </reg>
      <reg name="lvds2dfe_latch_reg_1" protect="r">
        <bits access="r" name="lvds2dfe_latch_reg1" pos="31:0" rst="0">
          <comment>LVDS2DFE latch reg1</comment>
        </bits>
      </reg>
      <reg name="topbist_control" protect="rw">
        <bits access="rw" name="top2lvds_bist_en" pos="17" rst="0">
          <comment>top bist en</comment>
        </bits>
        <bits access="r" name="err_flag" pos="16" rst="0">
      </bits>
        <bits access="r" name="err_cnt" pos="15:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="sys_imem.xml">
    <var name="NB_ROM_PATCH" value="8"/>
    <var name="INT_ROM_SIZE" value="64*1024"/>
    <var name="INT_SRAM_SIZE" value="64*1024"/>
    <module category="System" name="SYS_IMEM">
      <struct count="NB_ROM_PATCH/2" name="patch_pagespy_ctrl">
        <reg name="patch_pagespy_start" protect="rw">
          <bits access="rw" name="patch_valid" pos="31:31">
      </bits>
          <bits access="rw" name="pagespy_enable" pos="30:30">
      </bits>
          <bits access="rw" name="pagespy_detectr" pos="29:29">
      </bits>
          <bits access="rw" name="pagespy_detectw" pos="28:28">
      </bits>
          <bits access="rw" name="patch_addr_pagespy_start_addr" pos="27:0">
      </bits>
        </reg>
        <reg name="patch_pagespy_end" protect="rw">
          <bits access="rw" name="patch_valid" pos="31:31">
      </bits>
          <bits access="rw" name="patch_addr_pagespy_end_addr" pos="27:0">
      </bits>
        </reg>
      </struct>
      <struct count="NB_ROM_PATCH/2" name="pagespy_info">
        <reg name="pagespy_info0" protect="rw">
          <bits access="r" name="pagespy_status" pos="11:11">
      </bits>
          <bits access="r" name="pagespy_hitr" pos="10:10">
      </bits>
          <bits access="r" name="pagespy_hitw" pos="9:9">
      </bits>
          <bits access="r" name="pagespy_aid" pos="8:0">
      </bits>
        </reg>
        <reg name="pagespy_info1" protect="rw">
          <bits access="r" name="pagespy_addr" pos="31:0">
      </bits>
        </reg>
      </struct>
    </module>
    <module category="Memory" name="INT_ROM">
      <memory name="boot rom" size="INT_ROM_SIZE">
        <comment>Internal Bootrom Space</comment>
      </memory>
    </module>
    <module category="Memory" name="INT_SRAM">
      <memory name="int sram" size="INT_SRAM_SIZE">
        <comment>Internal SRam Space</comment>
      </memory>
    </module>
  </archive>
  <archive relative="sys_axi_cfg.xml">
    <module category="System" name="SYS_AXI_CFG">
      <struct name="address region">
        <reg name="remap" protect="w">
      </reg>
        <hole size="4*8"/>
        <reg count="64" name="security" protect="w">
          <bits name="secure" pos="15:0">
        </bits>
        </reg>
        <hole size="3832*8"/>
      </struct>
      <struct name="periperal id">
        <hole size="4048*8"/>
        <reg name="peripheral id4" protect="r">
      </reg>
        <reg name="peripheral id5" protect="r">
      </reg>
        <reg name="peripheral id6" protect="r">
      </reg>
        <reg name="peripheral id7" protect="r">
      </reg>
        <reg name="peripheral id0" protect="r">
          <bits access="r" name="part number[7:0]" pos="7:0">
        </bits>
        </reg>
        <reg name="peripheral id1" protect="r">
          <bits access="r" name="part number[11:8]" pos="3:0">
        </bits>
          <bits access="r" name="jep106[3:0]" pos="7:4">
        </bits>
        </reg>
        <reg name="peripheral id2" protect="r">
          <bits access="r" name="jep106[6:4]" pos="3:0">
        </bits>
        </reg>
        <reg name="peripheral id3" protect="r">
      </reg>
        <reg name="component id0" protect="r">
      </reg>
        <reg name="component id1" protect="r">
      </reg>
        <reg name="component id2" protect="r">
      </reg>
        <reg name="component id3" protect="r">
      </reg>
      </struct>
    </module>
  </archive>
  <archive relative="dmc400.xml">
    <module category="Periph" name="DMC400">
      <reg name="memc_status" protect="r">
        <bits access="r" name="memc_status" pos="1:0" rst="0">
          <options>
            <option name="config" value="0"/>
            <option name="low_power" value="1"/>
            <option name="paused" value="2"/>
            <option name="ready" value="3"/>
          </options>
        </bits>
      </reg>
      <reg name="memc_config" protect="r">
        <bits access="r" name="system_interfaces_cfg" pos="1:0" rst="0">
          <options>
            <option name="1_system_interface" value="0"/>
            <option name="2_system_interface" value="1"/>
            <option name="4_system_interface" value="3"/>
          </options>
        </bits>
        <bits access="r" name="memory_interfaces_cfg" pos="5:4" rst="0">
          <options>
            <option name="1_memory_interface" value="0"/>
            <option name="2_memory_interface" value="1"/>
          </options>
        </bits>
        <bits access="r" name="memory_data_width_cfg" pos="9:8" rst="1">
          <options>
            <option name="32bit_phy_if" value="1"/>
            <option name="64bit_phy_if" value="2"/>
            <option name="128bit_phy_if" value="3"/>
          </options>
        </bits>
        <bits access="r" name="memory_chip_selects_cfg" pos="13:12" rst="0">
          <options>
            <option name="1_chip_sel" value="0"/>
            <option name="2_chip_sel" value="1"/>
          </options>
        </bits>
        <bits access="r" name="read_queue_depth_cfg" pos="18:16" rst="0">
          <options>
            <option name="16_entry" value="0"/>
            <option name="32_entry" value="1"/>
            <option name="64_entry" value="3"/>
            <option name="128_entry" value="7"/>
          </options>
        </bits>
        <bits access="r" name="write_queue_depth_cfg" pos="22:20" rst="1">
          <options>
            <option name="16_entry" value="0"/>
            <option name="32_entry" value="1"/>
            <option name="64_entry" value="3"/>
            <option name="128_entry" value="7"/>
          </options>
        </bits>
        <bits access="r" name="max_burst_length_cfg" pos="25:24" rst="3">
          <options>
            <option name="2_dmc_cycle" value="1"/>
            <option name="4_dmc_cycle" value="2"/>
            <option name="8_dmc_cycle" value="3"/>
          </options>
        </bits>
        <bits access="r" name="memory_ecc_cfg" pos="28" rst="0">
          <options>
            <option name="false" value="0"/>
            <option name="true" value="1"/>
          </options>
        </bits>
      </reg>
      <reg name="memc_cmd" protect="w">
        <bits access="w" name="memc_cmd" pos="2:0" rst="0">
          <options>
            <option name="config" value="0"/>
            <option name="sleep" value="1"/>
            <option name="pause" value="2"/>
            <option name="go" value="3"/>
            <option name="invalidate" value="4"/>
          </options>
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="address_control" protect="rw">
        <bits access="rw" name="column_bits" pos="3:0" rst="0">
          <options>
            <option name="8_col_bits" value="0"/>
            <option name="9_col_bits" value="1"/>
            <option name="10_col_bits" value="2"/>
            <option name="11_col_bits" value="3"/>
            <option name="12_col_bits" value="4"/>
          </options>
        </bits>
        <bits access="rw" name="row_bits" pos="11:8" rst="2">
          <options>
            <option name="13_row_bits" value="2"/>
            <option name="14_row_bits" value="3"/>
            <option name="15_row_bits" value="4"/>
            <option name="16_row_bits" value="5"/>
          </options>
        </bits>
        <bits access="rw" name="bank_bits" pos="19:16" rst="3">
          <options>
            <option name="2_bank_bits_4bk" value="2"/>
            <option name="3_bank_bits_8bk" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="chip_bits" pos="25:24" rst="0">
          <options>
            <option name="0_chip_bits_1cs" value="0"/>
            <option name="1_chip_bits_2cs" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="channel_bits" pos="29:28" rst="0">
          <options>
            <option name="0_channel_bits_1memif" value="0"/>
            <option name="1_channel_bits_2memif" value="1"/>
          </options>
        </bits>
      </reg>
      <reg name="decode_control" protect="rw">
        <bits access="rw" name="addr_decode" pos="1:0" rst="0">
          <options>
            <option name="channel_chip_row_bank_col" value="0"/>
            <option name="row_channel_chip_bank_col" value="1"/>
            <option name="chip_bank_row_channel_col" value="2"/>
            <option name="row_chip_bank_channel_col" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="strip_decode" pos="7:4" rst="5">
          <options>
            <option name="page_addr_13_12" value="0"/>
            <option name="page_addr_12_11" value="1"/>
            <option name="page_addr_11_10" value="2"/>
            <option name="page_addr_10_9" value="3"/>
            <option name="page_addr_9_8" value="4"/>
            <option name="page_addr_8_7" value="5"/>
            <option name="page_addr_7_6" value="6"/>
            <option name="page_addr_6_5" value="7"/>
          </options>
        </bits>
      </reg>
      <reg name="format_control" protect="rw">
        <bits access="rw" name="mem_width" pos="1:0" rst="1">
          <options>
            <option name="phy_width_32_x16_ddr" value="1"/>
            <option name="phy_width_64_x32_ddr" value="2"/>
            <option name="phy_width_128_x64_ddr" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="mem_burst" pos="9:8" rst="2">
          <options>
            <option name="mem_burst_2_ddr_bl4" value="1"/>
            <option name="mem_burst_4_ddr_bl8" value="2"/>
            <option name="mem_burst_8_ddr_bl16" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="acc_granu" pos="25:24" rst="2">
          <options>
            <option name="acc_granu_1_ddr_2n" value="0"/>
            <option name="acc_granu_2_ddr_4n" value="1"/>
            <option name="acc_granu_4_ddr_8n" value="2"/>
            <option name="acc_granu_8_ddr_16n" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="align_boundary" pos="29:28" rst="2">
          <options>
            <option name="align_boundary_1_col_1bit" value="0"/>
            <option name="align_boundary_2_col_2bit" value="1"/>
            <option name="align_boundary_4_col_3bit" value="2"/>
            <option name="align_boundary_8_col_4bit" value="3"/>
          </options>
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="low_power_control" protect="rw">
        <bits access="rw" name="stop_mem_clock_idle" pos="0" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="stop_mem_clock_sref" pos="1" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="auto_power_down" pos="2" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="auto_self_refresh" pos="3" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="asr_period" pos="7:4" rst="1">
        </bits>
      </reg>
      <hole size="(3)*32"/>
      <reg name="turnaround_priority" protect="rw">
        <bits access="rw" name="turnaround_priority" pos="3:0" rst="0">
        </bits>
        <bits access="rw" name="turnaround_limit" pos="7:4" rst="0">
        </bits>
      </reg>
      <reg name="hit_priority" protect="rw">
        <bits access="rw" name="hit_priority" pos="3:0" rst="0">
        </bits>
        <bits access="rw" name="hit_limit" pos="7:4" rst="0">
        </bits>
      </reg>
      <reg name="qos0_control" protect="rw">
        <bits access="rw" name="qos0_priority" pos="3:0" rst="0">
        </bits>
        <bits access="rw" name="qos0_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos1_control" protect="rw">
        <bits access="rw" name="qos1_priority" pos="3:0" rst="1">
        </bits>
        <bits access="rw" name="qos1_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos2_control" protect="rw">
        <bits access="rw" name="qos2_priority" pos="3:0" rst="2">
        </bits>
        <bits access="rw" name="qos2_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos3_control" protect="rw">
        <bits access="rw" name="qos3_priority" pos="3:0" rst="3">
        </bits>
        <bits access="rw" name="qos3_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos4_control" protect="rw">
        <bits access="rw" name="qos4_priority" pos="3:0" rst="4">
        </bits>
        <bits access="rw" name="qos4_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos5_control" protect="rw">
        <bits access="rw" name="qos5_priority" pos="3:0" rst="5">
        </bits>
        <bits access="rw" name="qos5_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos6_control" protect="rw">
        <bits access="rw" name="qos6_priority" pos="3:0" rst="6">
        </bits>
        <bits access="rw" name="qos6_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos7_control" protect="rw">
        <bits access="rw" name="qos7_priority" pos="3:0" rst="7">
        </bits>
        <bits access="rw" name="qos7_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos8_control" protect="rw">
        <bits access="rw" name="qos8_priority" pos="3:0" rst="8">
        </bits>
        <bits access="rw" name="qos8_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos9_control" protect="rw">
        <bits access="rw" name="qos9_priority" pos="3:0" rst="9">
        </bits>
        <bits access="rw" name="qos9_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos10_control" protect="rw">
        <bits access="rw" name="qos10_priority" pos="3:0" rst="10">
        </bits>
        <bits access="rw" name="qos10_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos11_control" protect="rw">
        <bits access="rw" name="qos11_priority" pos="3:0" rst="11">
        </bits>
        <bits access="rw" name="qos11_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos12_control" protect="rw">
        <bits access="rw" name="qos12_priority" pos="3:0" rst="12">
        </bits>
        <bits access="rw" name="qos12_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="qos13_control" protect="rw">
        <bits access="rw" name="qos13_priority" pos="3:0" rst="13">
        </bits>
        <bits access="rw" name="qos13_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos14_control" protect="rw">
        <bits access="rw" name="qos14_priority" pos="3:0" rst="14">
        </bits>
        <bits access="rw" name="qos14_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="qos15_control" protect="rw">
        <bits access="rw" name="qos15_priority" pos="3:0" rst="15">
        </bits>
        <bits access="rw" name="qos15_timeout" pos="11:8" rst="0">
        </bits>
      </reg>
      <reg name="timeout_control" protect="rw">
        <bits access="rw" name="timeout_prescalar" pos="1:0" rst="1">
          <options>
            <option name="8_clk" value="0"/>
            <option name="16_clk" value="1"/>
            <option name="32_clk" value="2"/>
            <option name="64_clk" value="3"/>
          </options>
        </bits>
      </reg>
      <reg name="queue_control" protect="rw">
        <bits access="rw" name="s0_reserve" pos="3:0" rst="0">
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="write_priority_control" protect="rw">
        <bits access="rw" name="write_threshold_en" pos="0" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="write_fill_priority_1_16ths" pos="7:4" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_2_16ths" pos="11:8" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_3_16ths" pos="15:12" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_4_16ths" pos="19:16" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_5_16ths" pos="23:20" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_6_16ths" pos="27:24" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_7_16ths" pos="31:28" rst="0">
        </bits>
      </reg>
      <reg name="write_priority_control2" protect="rw">
        <bits access="rw" name="write_fill_priority_8_16ths" pos="3:0" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_9_16ths" pos="7:4" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_10_16ths" pos="11:8" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_11_16ths" pos="15:12" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_12_16ths" pos="19:16" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_13_16ths" pos="23:20" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_14_16ths" pos="27:24" rst="0">
        </bits>
        <bits access="rw" name="write_fill_priority_15_16ths" pos="31:28" rst="0">
        </bits>
      </reg>
      <reg name="read_priority_control" protect="rw">
        <bits access="rw" name="read_escalation" pos="0" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="read_in_burst_prioritisation" pos="1" rst="1">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="read_fill_priority_1_16ths" pos="7:4" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_2_16ths" pos="11:8" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_3_16ths" pos="15:12" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_4_16ths" pos="19:16" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_5_16ths" pos="23:20" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_6_16ths" pos="27:24" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_7_16ths" pos="31:28" rst="0">
        </bits>
      </reg>
      <reg name="read_priority_control2" protect="rw">
        <bits access="rw" name="read_fill_priority_8_16ths" pos="3:0" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_9_16ths" pos="7:4" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_10_16ths" pos="11:8" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_11_16ths" pos="15:12" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_12_16ths" pos="19:16" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_13_16ths" pos="23:20" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_14_16ths" pos="27:24" rst="0">
        </bits>
        <bits access="rw" name="read_fill_priority_15_16ths" pos="31:28" rst="0">
        </bits>
      </reg>
      <reg name="access_address_match" protect="rw">
        <bits access="rw" name="access_address_match" pos="31:12" rst="0">
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="access_address_mask" protect="rw">
        <bits access="rw" name="access_address_mask" pos="31:12" rst="0">
        </bits>
      </reg>
      <hole size="(23)*32"/>
      <reg name="channel_status" protect="r">
        <bits access="r" name="m0_state" pos="3:0" rst="1">
          <options>
            <option name="standby" value="0"/>
            <option name="dpd" value="1"/>
            <option name="idle" value="2"/>
            <option name="self_refresh" value="3"/>
            <option name="reading" value="4"/>
            <option name="power_down" value="5"/>
            <option name="writing" value="6"/>
          </options>
        </bits>
        <bits access="r" name="m1_state" pos="7:4" rst="0">
          <options>
            <option name="standby" value="0"/>
            <option name="dpd" value="1"/>
            <option name="idle" value="2"/>
            <option name="self_refresh" value="3"/>
            <option name="reading" value="4"/>
            <option name="power_down" value="5"/>
            <option name="writing" value="6"/>
          </options>
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="direct_cmd" protect="w">
        <bits access="w" name="direct_addr" pos="15:0" rst="0">
        </bits>
        <bits access="w" name="direct_ba" pos="18:16" rst="0">
        </bits>
        <bits access="w" name="chip_addr" pos="20" rst="0">
          <options>
            <option name="chip_0" value="0"/>
            <option name="chip_1" value="1"/>
          </options>
        </bits>
        <bits access="w" name="channel_addr" pos="24" rst="0">
          <options>
            <option name="channel_0" value="0"/>
            <option name="channel_1" value="1"/>
          </options>
        </bits>
        <bits access="w" name="direct_cmd" pos="31:28" rst="0">
          <options>
            <option name="nop" value="0"/>
            <option name="mrs" value="1"/>
            <option name="prechargeall" value="2"/>
            <option name="autorefresh" value="3"/>
            <option name="selfrefresh_entry" value="4"/>
            <option name="zqc" value="5"/>
            <option name="mrr" value="6"/>
            <option name="powerdown_entry" value="7"/>
            <option name="deep_powerdown_entry" value="8"/>
          </options>
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="mr_data" protect="r">
        <bits access="r" name="mr_data" pos="7:0" rst="0">
        </bits>
      </reg>
      <hole size="(3)*32"/>
      <reg name="refresh_control" protect="rw">
        <bits access="rw" name="per_bank_refresh" pos="0" rst="0">
          <options>
            <option name="all_bank_autorefresh" value="0"/>
            <option name="pre_bank_autorefresh" value="1"/>
          </options>
        </bits>
      </reg>
      <hole size="(55)*32"/>
      <reg name="t_refi" protect="rw">
        <bits access="rw" name="t_refi" pos="10:0" rst="0x100">
        </bits>
      </reg>
      <reg name="t_rfc" protect="rw">
        <bits access="rw" name="t_rfc" pos="8:0" rst="0x23">
        </bits>
        <bits access="rw" name="t_rfcab" pos="24:16" rst="0x23">
        </bits>
      </reg>
      <reg name="t_mrr" protect="rw">
        <bits access="rw" name="t_mrr" pos="2:0" rst="2">
        </bits>
      </reg>
      <reg name="t_mrw" protect="rw">
        <bits access="rw" name="t_mrw" pos="6:0" rst="2">
        </bits>
      </reg>
      <hole size="(2)*32"/>
      <reg name="t_rcd" protect="rw">
        <bits access="rw" name="t_rcd" pos="3:0" rst="5">
        </bits>
      </reg>
      <reg name="t_ras" protect="rw">
        <bits access="rw" name="t_ras" pos="5:0" rst="0xe">
        </bits>
      </reg>
      <reg name="t_rp" protect="rw">
        <bits access="rw" name="t_rp" pos="4:0" rst="5">
        </bits>
      </reg>
      <reg name="t_rpall" protect="rw">
        <bits access="rw" name="t_rpall" pos="4:0" rst="5">
        </bits>
      </reg>
      <reg name="t_rrd" protect="rw">
        <bits access="rw" name="t_rrd" pos="3:0" rst="4">
        </bits>
      </reg>
      <reg name="t_faw" protect="rw">
        <bits access="rw" name="t_faw" pos="5:0" rst="0x14">
        </bits>
      </reg>
      <reg name="read_latency" protect="rw">
        <bits access="rw" name="read_latency" pos="3:0" rst="5">
        </bits>
      </reg>
      <reg name="t_rtr" protect="rw">
        <bits access="rw" name="t_rtr" pos="3:0" rst="4">
        </bits>
      </reg>
      <reg name="t_rtw" protect="rw">
        <bits access="rw" name="t_rtw" pos="4:0" rst="6">
        </bits>
      </reg>
      <reg name="t_rtp" protect="rw">
        <bits access="rw" name="t_rtp" pos="3:0" rst="0">
        </bits>
      </reg>
      <reg name="write_latency" protect="rw">
        <bits access="rw" name="write_latency" pos="3:0" rst="4">
        </bits>
      </reg>
      <reg name="t_wr" protect="rw">
        <bits access="rw" name="t_wr" pos="4:0" rst="5">
        </bits>
      </reg>
      <reg name="t_wtr" protect="rw">
        <bits access="rw" name="t_wtr" pos="4:0" rst="4">
        </bits>
        <bits access="rw" name="t_wtr_cs" pos="20:16" rst="4">
        </bits>
      </reg>
      <reg name="t_wtw" protect="rw">
        <bits access="rw" name="t_wtw" pos="21:16" rst="4">
        </bits>
      </reg>
      <reg name="t_eckd" protect="rw">
        <bits access="rw" name="t_eckd" pos="3:0" rst="5">
        </bits>
      </reg>
      <reg name="t_xckd" protect="rw">
        <bits access="rw" name="t_xckd" pos="3:0" rst="5">
        </bits>
      </reg>
      <reg name="t_ep" protect="rw">
        <bits access="rw" name="t_ep" pos="3:0" rst="2">
        </bits>
      </reg>
      <reg name="t_xp" protect="rw">
        <bits access="rw" name="t_xp" pos="4:0" rst="2">
        </bits>
        <bits access="rw" name="t_xpdll" pos="20:16" rst="2">
        </bits>
      </reg>
      <reg name="t_esr" protect="rw">
        <bits access="rw" name="t_esr" pos="8:0" rst="0xe">
        </bits>
      </reg>
      <reg name="t_xsr" protect="rw">
        <bits access="rw" name="t_xsr" pos="9:0" rst="0x100">
        </bits>
        <bits access="rw" name="t_xsrdll" pos="25:16" rst="0x100">
        </bits>
      </reg>
      <reg name="t_srckd" protect="rw">
        <bits access="rw" name="t_srckd" pos="3:0" rst="5">
        </bits>
      </reg>
      <reg name="t_cksrd" protect="rw">
        <bits access="rw" name="t_cksrd" pos="3:0" rst="5">
        </bits>
      </reg>
      <hole size="(36)*32"/>
      <reg name="t_rddata_en" protect="rw">
        <bits access="rw" name="t_rddata_en" pos="3:0" rst="1">
        </bits>
      </reg>
      <reg name="t_phywrlat" protect="rw">
        <bits access="rw" name="t_phywrlat" pos="3:0" rst="1">
        </bits>
        <bits access="rw" name="t_phywrdata" pos="8" rst="1">
        </bits>
      </reg>
      <reg name="rdlvl_control" protect="rw">
        <bits access="rw" name="rdlvl_mode" pos="1:0" rst="0">
          <options>
            <option name="no_training" value="0"/>
            <option name="phy_independent_mode" value="1"/>
            <option name="phy_evaluation_mode" value="2"/>
          </options>
        </bits>
        <bits access="rw" name="rdlvl_setup" pos="4" rst="0">
          <options>
            <option name="mrs_prior_train" value="0"/>
            <option name="nop_prior_train" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="rdlvl_cmd" pos="8" rst="0">
          <options>
            <option name="read_for_train" value="0"/>
            <option name="mrr_for_train" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="rdlvl_refresh" pos="12" rst="1">
          <options>
            <option name="prechargeall_prior_train" value="0"/>
            <option name="prechargeall_autorefresh_prior_train" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="rdlvl_reg_sel" pos="16" rst="0">
          <options>
            <option name="mr32_for_train" value="0"/>
            <option name="mr40_for_train" value="1"/>
          </options>
        </bits>
      </reg>
      <reg name="rdlvl_mrs" protect="rw">
        <bits access="rw" name="rdlvl_mrs" pos="2:0" rst="4">
        </bits>
      </reg>
      <reg name="rdlvl_direct" protect="w">
        <bits access="w" name="rdlvl_req" pos="1:0" rst="0">
          <options>
            <option name="read_eye_train" value="1"/>
            <option name="read_gate_train" value="2"/>
          </options>
        </bits>
        <bits access="w" name="rdlvl_chip_addr" pos="24" rst="0">
          <options>
            <option name="chip_0" value="0"/>
            <option name="chip_1" value="1"/>
          </options>
        </bits>
        <bits access="w" name="rdlvl_channel_addr" pos="28" rst="0">
          <options>
            <option name="channel_0" value="0"/>
            <option name="channel_1" value="1"/>
          </options>
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="t_rdlvl_en" protect="rw">
        <bits access="rw" name="t_rdlvl_en" pos="5:0" rst="1">
        </bits>
      </reg>
      <reg name="t_rdlvl_rr" protect="rw">
        <bits access="rw" name="t_rdlvl_rr" pos="5:0" rst="4">
        </bits>
      </reg>
      <hole size="(2)*32"/>
      <reg name="wrlvl_control" protect="rw">
        <bits access="rw" name="wrlvl_mode" pos="1:0" rst="0">
          <options>
            <option name="no_training" value="0"/>
            <option name="phy_independent_mode" value="1"/>
            <option name="phy_evaluation_mode" value="2"/>
          </options>
        </bits>
        <bits access="rw" name="wrlvl_refresh" pos="12" rst="1">
          <options>
            <option name="prechargeall_prior_train" value="0"/>
            <option name="prechargeall_autorefresh_prior_train" value="1"/>
          </options>
        </bits>
      </reg>
      <reg name="wrlvl_mrs" protect="rw">
        <bits access="rw" name="wrlvl_mrs" pos="12:0" rst="0x86">
        </bits>
      </reg>
      <reg name="wrlvl_direct" protect="w">
        <bits access="w" name="wrlvl_req" pos="0" rst="0">
        </bits>
        <bits access="w" name="wrlvl_chip_addr" pos="24" rst="0">
          <options>
            <option name="chip_0" value="0"/>
            <option name="chip_1" value="1"/>
          </options>
        </bits>
        <bits access="w" name="wrlvl_channel_addr" pos="28" rst="0">
          <options>
            <option name="channel_0" value="0"/>
            <option name="channel_1" value="1"/>
          </options>
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="t_wrlvl_en" protect="rw">
        <bits access="rw" name="t_wrlvl_en" pos="5:0" rst="1">
        </bits>
      </reg>
      <reg name="t_wrlvl_ww" protect="rw">
        <bits access="rw" name="t_wrlvl_ww" pos="5:0" rst="4">
        </bits>
      </reg>
      <hole size="(2)*32"/>
      <reg name="phy_power_control" protect="rw">
        <bits access="rw" name="lp_wr_en" pos="0" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="lp_rd_en" pos="1" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="lp_idle_en" pos="2" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="lp_pd_en" pos="3" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="lp_sref_en" pos="4" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="lp_dpd_en" pos="5" rst="0">
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="lp_wakeup_wr" pos="11:8" rst="0">
        </bits>
        <bits access="rw" name="lp_wakeup_rd" pos="15:12" rst="0">
        </bits>
        <bits access="rw" name="lp_wakeup_idle" pos="19:16" rst="0">
        </bits>
        <bits access="rw" name="lp_wakeup_pd" pos="23:20" rst="0">
        </bits>
        <bits access="rw" name="lp_wakeup_sref" pos="27:24" rst="0">
        </bits>
        <bits access="rw" name="lp_wakeup_dpd" pos="31:28" rst="0">
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="phy_update_control" protect="rw">
        <bits access="rw" name="phyupd_type_00" pos="1:0" rst="0">
          <options>
            <option name="sref" value="0"/>
            <option name="stall" value="1"/>
            <option name="refnstall" value="2"/>
            <option name="defer" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="phyupd_type_01" pos="3:2" rst="0">
          <options>
            <option name="sref" value="0"/>
            <option name="stall" value="1"/>
            <option name="refnstall" value="2"/>
            <option name="defer" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="phyupd_type_10" pos="5:4" rst="0">
          <options>
            <option name="sref" value="0"/>
            <option name="stall" value="1"/>
            <option name="refnstall" value="2"/>
            <option name="defer" value="3"/>
          </options>
        </bits>
        <bits access="rw" name="phyupd_type_11" pos="7:6" rst="0">
          <options>
            <option name="sref" value="0"/>
            <option name="stall" value="1"/>
            <option name="refnstall" value="2"/>
            <option name="defer" value="3"/>
          </options>
        </bits>
      </reg>
      <hole size="(43)*32"/>
      <reg name="user_status" protect="r">
        <bits access="r" name="user_status" pos="7:0" rst="0">
        </bits>
      </reg>
      <reg name="user_config0" protect="rw">
        <bits access="rw" name="user_config0" pos="7:0" rst="0">
        </bits>
      </reg>
      <reg name="user_config1" protect="rw">
        <bits access="rw" name="user_config1" pos="7:0" rst="0">
        </bits>
      </reg>
      <hole size="(637)*32"/>
      <reg name="integ_cfg" protect="rw">
        <bits access="rw" name="integ_test_en" pos="0" rst="0">
        </bits>
      </reg>
      <hole size="(1)*32"/>
      <reg name="integ_outputs" protect="w">
        <bits access="w" name="combined_integ" pos="0" rst="0">
        </bits>
        <bits access="w" name="ecc_sec_integ" pos="1" rst="0">
        </bits>
        <bits access="w" name="ecc_ded_integ" pos="2" rst="0">
        </bits>
        <bits access="w" name="ecc_overflow_integ" pos="3" rst="0">
        </bits>
      </reg>
      <hole size="(117)*32"/>
      <reg name="periph_id_0" protect="r">
        <bits access="r" name="part_0" pos="7:0" rst="0x40">
        </bits>
      </reg>
      <reg name="periph_id_1" protect="r">
        <bits access="r" name="part_1" pos="3:0" rst="4">
        </bits>
        <bits access="r" name="des_0" pos="7:4" rst="0xb">
        </bits>
      </reg>
      <reg name="periph_id_2" protect="r">
        <bits access="r" name="des_1" pos="2:0" rst="3">
        </bits>
        <bits access="r" name="jedec" pos="3" rst="1">
        </bits>
        <bits access="r" name="revision" pos="7:4" rst="1">
        </bits>
      </reg>
      <reg name="periph_id_3" protect="r">
        <bits access="r" name="cmod" pos="7:0" rst="0">
        </bits>
      </reg>
      <reg name="component_id_0" protect="r">
        <bits access="r" name="prmbl_0" pos="7:0" rst="0xd">
        </bits>
      </reg>
      <reg name="component_id_1" protect="r">
        <bits access="r" name="prmbl_1" pos="3:0" rst="0">
        </bits>
        <bits access="r" name="pclass" pos="7:4" rst="0xf">
        </bits>
      </reg>
      <reg name="component_id_2" protect="r">
        <bits access="r" name="prmbl_2" pos="7:0" rst="5">
        </bits>
      </reg>
      <reg name="component_id_3" protect="r">
        <bits access="r" name="prmbl_3" pos="7:0" rst="0xb1">
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="lpddr_phy.xml">
    <module category="Periph" name="LPDDR_PHY">
      <reg name="lpddr_rf_cfg_phy" protect="rw">
        <bits access="rw" name="rf_phy_init_complete" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_clock_gate" protect="rw">
        <bits access="rw" name="rf_clk_gate_ag_rd_en" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_clk_gate_ag_wr_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_clk_gate_ag_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_clk_gate_fg_en" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_clk_gate_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_sample_resync" protect="rw">
        <bits access="rw" name="rf_data_resync_sel" pos="31:16" rst="0">
      </bits>
        <bits access="rw" name="rf_sample_resync_auto_en" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_sample_resync" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_lpi" protect="rw">
        <bits access="rw" name="rf_cwakeup_s0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_cwakeup_m0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_lpi_sel_m0" pos="0" rst="0">
      </bits>
      </reg>
      <hole size="1920"/>
      <reg name="lpddr_rf_cfg_ext" protect="rw">
        <bits access="rw" name="rf_data_resync_ext" pos="23:20" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_ext" pos="19:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_ie_ext" pos="15:12" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_oe_ext" pos="11:8" rst="0">
      </bits>
        <bits access="rw" name="rf_data_ie_ext" pos="7:4" rst="0">
      </bits>
        <bits access="rw" name="rf_data_oe_ext" pos="3:0" rst="0">
      </bits>
      </reg>
      <hole size="2016"/>
      <reg name="lpddr_rfdll_cfg_dll" protect="rw">
        <bits access="w" name="rfdll_reset" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rfdll_status_cpst_idle" protect="r">
        <bits access="r" name="rfdl_cpst_st_idle_ds1" pos="2" rst="1">
      </bits>
        <bits access="r" name="rfdl_cpst_st_idle_ds0" pos="1" rst="1">
      </bits>
        <bits access="r" name="rfdl_cpst_st_idle_ac" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_ac" protect="rw">
        <bits access="rw" name="rf_dll_lock_wait_ac" pos="31:28" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_auto_err_clr_en_ac" pos="27" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_pd_cnt_ac" pos="26:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_thr_ac" pos="23:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_en_ac" pos="15" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_clk_sel_ac" pos="14" rst="0">
      </bits>
        <bits access="w" name="rf_dll_err_clr_ac" pos="13" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_auto_ref_en_ac" pos="12" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_start_ac" pos="11" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_en_ac" pos="10" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_auto_clr_en_ac" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_clr_ac" pos="8" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rfdll_status_dll_ac" protect="r">
        <bits access="r" name="rfdll_error_ac" pos="29" rst="0">
      </bits>
        <bits access="r" name="rfdll_locked_ac" pos="28" rst="0">
      </bits>
        <bits access="r" name="rfdll_st_ac" pos="27:25" rst="0">
      </bits>
        <bits access="r" name="rfdl_cpst_st_ac" pos="24" rst="0">
      </bits>
        <bits access="r" name="rfdll_cnt_ac" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_0_wr_ac" protect="rw">
        <bits access="rw" name="rf_clkwr_dl_cpst_en_ac" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_dl_cpst_minus_ac" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_qtr_dl_cpst_offset_ac" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_clkwr_qtr_cnt_ac" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_qtr_dl_sel_ac" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_raw_dl_cpst_offset_ac" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_clkwr_raw_cnt_ac" pos="14:8" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_raw_dl_sel_ac" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_1_wr_ac" protect="rw">
        <bits access="rw" name="rf_dly_out_a3_dl_sel" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_a2_dl_sel" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_a1_dl_sel" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_a0_dl_sel" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_2_wr_ac" protect="rw">
        <bits access="rw" name="rf_dly_out_a7_dl_sel" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_a6_dl_sel" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_a5_dl_sel" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_a4_dl_sel" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_3_wr_ac" protect="rw">
        <bits access="rw" name="rf_dly_out_a9_dl_sel" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_a8_dl_sel" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_4_wr_ac" protect="rw">
        <bits access="rw" name="rf_dly_out_clk_dl_sel" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_cke_dl_sel" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_csn_dl_sel" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rfdll_status_max_cnt_ac" protect="r">
        <bits access="r" name="rfdll_max_cnt_f3_ac" pos="30:24" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f2_ac" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f1_ac" pos="14:8" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f0_ac" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rfdll_status_min_cnt_ac" protect="r">
        <bits access="r" name="rfdll_min_cnt_f3_ac" pos="30:24" rst="127">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f2_ac" pos="22:16" rst="127">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f1_ac" pos="14:8" rst="127">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f0_ac" pos="6:0" rst="127">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_sel_wr_ac" protect="rw">
        <bits access="rw" name="rf_phy_io_cke1_sel_ac" pos="21" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_cke0_sel_ac" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_csn_sel_ac" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a9_sel_ac" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a8_sel_ac" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a7_sel_ac" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a6_sel_ac" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a5_sel_ac" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a4_sel_ac" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a3_sel_ac" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a2_sel_ac" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a1_sel_ac" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a0_sel_ac" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_ie_wr_ac" protect="rw">
        <bits access="rw" name="rf_phy_io_cke1_ie_ac" pos="21" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_cke0_ie_ac" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_csn_ie_ac" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a9_ie_ac" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a8_ie_ac" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a7_ie_ac" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a6_ie_ac" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a5_ie_ac" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a4_ie_ac" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a3_ie_ac" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a2_ie_ac" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a1_ie_ac" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a0_ie_ac" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_oe_wr_ac" protect="rw">
        <bits access="rw" name="rf_phy_io_cke1_oe_ac" pos="21" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_cke0_oe_ac" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_csn_oe_ac" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a9_oe_ac" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a8_oe_ac" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a7_oe_ac" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a6_oe_ac" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a5_oe_ac" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a4_oe_ac" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a3_oe_ac" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a2_oe_ac" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a1_oe_ac" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a0_oe_ac" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_out_wr_ac" protect="rw">
        <bits access="rw" name="rf_phy_io_cke1_out_ac" pos="21" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_cke0_out_ac" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_csn_out_ac" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a9_out_ac" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a8_out_ac" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a7_out_ac" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a6_out_ac" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a5_out_ac" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a4_out_ac" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a3_out_ac" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a2_out_ac" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a1_out_ac" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_a0_out_ac" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_ds0" protect="rw">
        <bits access="rw" name="rf_dll_lock_wait_ds0" pos="31:28" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_auto_err_clr_en_ds0" pos="27" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_pd_cnt_ds0" pos="26:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_thr_ds0" pos="23:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_en_ds0" pos="15" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_clk_sel_ds0" pos="14" rst="0">
      </bits>
        <bits access="w" name="rf_dll_err_clr_ds0" pos="13" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_auto_ref_en_ds0" pos="12" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_start_ds0" pos="11" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_en_ds0" pos="10" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_auto_clr_en_ds0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_clr_ds0" pos="8" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rfdll_status_dll_ds0" protect="r">
        <bits access="r" name="rfdll_error_ds0" pos="29" rst="0">
      </bits>
        <bits access="r" name="rfdll_locked_ds0" pos="28" rst="0">
      </bits>
        <bits access="r" name="rfdll_st_ds0" pos="27:25" rst="0">
      </bits>
        <bits access="r" name="rfdl_cpst_st_ds0" pos="24" rst="0">
      </bits>
        <bits access="r" name="rfdll_cnt_ds0" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_0_wr_ds0" protect="rw">
        <bits access="rw" name="rf_clkwr_dl_cpst_en_ds0" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_dl_cpst_minus_ds0" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_qtr_dl_cpst_offset_ds0" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_clkwr_qtr_cnt_ds0" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_qtr_dl_sel_ds0" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_raw_dl_cpst_offset_ds0" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_clkwr_raw_cnt_ds0" pos="14:8" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_raw_dl_sel_ds0" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_1_wr_ds0" protect="rw">
        <bits access="rw" name="rf_dqs_in_pos_dl_cpst_en_ds0" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_dl_cpst_minus_ds0" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_qtr_dl_cpst_offset_ds0" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_pos_qtr_cnt_ds0" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_qtr_dl_sel_ds0" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_raw_dl_cpst_offset_ds0" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_pos_raw_cnt_ds0" pos="14:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_raw_dl_sel_ds0" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_2_wr_ds0" protect="rw">
        <bits access="rw" name="rf_dqs_in_neg_dl_cpst_en_ds0" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_dl_cpst_minus_ds0" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_qtr_dl_cpst_offset_ds0" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_neg_qtr_cnt_ds0" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_qtr_dl_sel_ds0" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_raw_dl_cpst_offset_ds0" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_neg_raw_cnt_ds0" pos="14:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_raw_dl_sel_ds0" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_3_wr_ds0" protect="rw">
        <bits access="rw" name="rf_dqs_gate_dl_cpst_en_ds0" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_dl_cpst_minus_ds0" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_qtr_dl_cpst_offset_ds0" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_gate_qtr_cnt_ds0" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_qtr_dl_sel_ds0" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_raw_dl_cpst_offset_ds0" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_gate_raw_cnt_ds0" pos="14:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_raw_dl_sel_ds0" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_4_wr_ds0" protect="rw">
        <bits access="rw" name="rf_dly_out_d3_dl_sel_ds0" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d2_dl_sel_ds0" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d1_dl_sel_ds0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d0_dl_sel_ds0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_5_wr_ds0" protect="rw">
        <bits access="rw" name="rf_dly_out_d7_dl_sel_ds0" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d6_dl_sel_ds0" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d5_dl_sel_ds0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d4_dl_sel_ds0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_6_wr_ds0" protect="rw">
        <bits access="rw" name="rf_dly_in_d3_dl_sel_ds0" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d2_dl_sel_ds0" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d1_dl_sel_ds0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d0_dl_sel_ds0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_7_wr_ds0" protect="rw">
        <bits access="rw" name="rf_dly_in_d7_dl_sel_ds0" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d6_dl_sel_ds0" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d5_dl_sel_ds0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d4_dl_sel_ds0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_8_wr_ds0" protect="rw">
        <bits access="rw" name="rf_dly_in_dqs_dl_sel_ds0" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_dqm_dl_sel_ds0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_dqs_dl_sel_ds0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rfdll_status_max_cnt_ds0" protect="r">
        <bits access="r" name="rfdll_max_cnt_f3_ds0" pos="30:24" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f2_ds0" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f1_ds0" pos="14:8" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f0_ds0" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rfdll_status_min_cnt_ds0" protect="r">
        <bits access="r" name="rfdll_min_cnt_f3_ds0" pos="30:24" rst="127">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f2_ds0" pos="22:16" rst="127">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f1_ds0" pos="14:8" rst="127">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f0_ds0" pos="6:0" rst="127">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_sel_wr_ds0" protect="rw">
        <bits access="rw" name="rf_phy_io_dqs_sel_ds0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_sel_ds0" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_sel_ds0" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_sel_ds0" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_sel_ds0" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_sel_ds0" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_sel_ds0" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_sel_ds0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_sel_ds0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_sel_ds0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_ie_wr_ds0" protect="rw">
        <bits access="rw" name="rf_phy_io_dqs_ie_ds0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_ie_ds0" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_ie_ds0" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_ie_ds0" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_ie_ds0" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_ie_ds0" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_ie_ds0" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_ie_ds0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_ie_ds0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_ie_ds0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_oe_wr_ds0" protect="rw">
        <bits access="rw" name="rf_phy_io_dqs_oe_ds0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_oe_ds0" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_oe_ds0" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_oe_ds0" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_oe_ds0" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_oe_ds0" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_oe_ds0" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_oe_ds0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_oe_ds0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_oe_ds0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_out_wr_ds0" protect="rw">
        <bits access="rw" name="rf_phy_io_dqs_out_ds0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_out_ds0" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_out_ds0" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_out_ds0" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_out_ds0" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_out_ds0" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_out_ds0" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_out_ds0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_out_ds0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_out_ds0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_ds1" protect="rw">
        <bits access="rw" name="rf_dll_lock_wait_ds1" pos="31:28" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_auto_err_clr_en_ds1" pos="27" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_pd_cnt_ds1" pos="26:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_thr_ds1" pos="23:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_en_ds1" pos="15" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_clk_sel_ds1" pos="14" rst="0">
      </bits>
        <bits access="w" name="rf_dll_err_clr_ds1" pos="13" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_auto_ref_en_ds1" pos="12" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_start_ds1" pos="11" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_en_ds1" pos="10" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_auto_clr_en_ds1" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_clr_ds1" pos="8" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rfdll_status_dll_ds1" protect="r">
        <bits access="r" name="rfdll_error_ds1" pos="29" rst="0">
      </bits>
        <bits access="r" name="rfdll_locked_ds1" pos="28" rst="0">
      </bits>
        <bits access="r" name="rfdll_st_ds1" pos="27:25" rst="0">
      </bits>
        <bits access="r" name="rfdl_cpst_st_ds1" pos="24" rst="0">
      </bits>
        <bits access="r" name="rfdll_cnt_ds1" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_0_wr_ds1" protect="rw">
        <bits access="rw" name="rf_clkwr_dl_cpst_en_ds1" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_dl_cpst_minus_ds1" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_qtr_dl_cpst_offset_ds1" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_clkwr_qtr_cnt_ds1" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_qtr_dl_sel_ds1" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_raw_dl_cpst_offset_ds1" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_clkwr_raw_cnt_ds1" pos="14:8" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_raw_dl_sel_ds1" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_1_wr_ds1" protect="rw">
        <bits access="rw" name="rf_dqs_in_pos_dl_cpst_en_ds1" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_dl_cpst_minus_ds1" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_qtr_dl_cpst_offset_ds1" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_pos_qtr_cnt_ds1" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_qtr_dl_sel_ds1" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_raw_dl_cpst_offset_ds1" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_pos_raw_cnt_ds1" pos="14:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_raw_dl_sel_ds1" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_2_wr_ds1" protect="rw">
        <bits access="rw" name="rf_dqs_in_neg_dl_cpst_en_ds1" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_dl_cpst_minus_ds1" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_qtr_dl_cpst_offset_ds1" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_neg_qtr_cnt_ds1" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_qtr_dl_sel_ds1" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_raw_dl_cpst_offset_ds1" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_neg_raw_cnt_ds1" pos="14:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_raw_dl_sel_ds1" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_3_wr_ds1" protect="rw">
        <bits access="rw" name="rf_dqs_gate_dl_cpst_en_ds1" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_dl_cpst_minus_ds1" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_qtr_dl_cpst_offset_ds1" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_gate_qtr_cnt_ds1" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_qtr_dl_sel_ds1" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_raw_dl_cpst_offset_ds1" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_gate_raw_cnt_ds1" pos="14:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_raw_dl_sel_ds1" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_4_wr_ds1" protect="rw">
        <bits access="rw" name="rf_dly_out_d3_dl_sel_ds1" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d2_dl_sel_ds1" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d1_dl_sel_ds1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d0_dl_sel_ds1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_5_wr_ds1" protect="rw">
        <bits access="rw" name="rf_dly_out_d7_dl_sel_ds1" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d6_dl_sel_ds1" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d5_dl_sel_ds1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d4_dl_sel_ds1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_6_wr_ds1" protect="rw">
        <bits access="rw" name="rf_dly_in_d3_dl_sel_ds1" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d2_dl_sel_ds1" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d1_dl_sel_ds1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d0_dl_sel_ds1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_7_wr_ds1" protect="rw">
        <bits access="rw" name="rf_dly_in_d7_dl_sel_ds1" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d6_dl_sel_ds1" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d5_dl_sel_ds1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d4_dl_sel_ds1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_dll_dl_8_wr_ds1" protect="rw">
        <bits access="rw" name="rf_dly_in_dqs_dl_sel_ds1" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_dqm_dl_sel_ds1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_dqs_dl_sel_ds1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rfdll_status_max_cnt_ds1" protect="r">
        <bits access="r" name="rfdll_max_cnt_f3_ds1" pos="30:24" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f2_ds1" pos="22:16" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f1_ds1" pos="14:8" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f0_ds1" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rfdll_status_min_cnt_ds1" protect="r">
        <bits access="r" name="rfdll_min_cnt_f3_ds1" pos="30:24" rst="127">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f2_ds1" pos="22:16" rst="127">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f1_ds1" pos="14:8" rst="127">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f0_ds1" pos="6:0" rst="127">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_sel_wr_ds1" protect="rw">
        <bits access="rw" name="rf_phy_io_dqs_sel_ds1" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_sel_ds1" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_sel_ds1" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_sel_ds1" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_sel_ds1" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_sel_ds1" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_sel_ds1" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_sel_ds1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_sel_ds1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_sel_ds1" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_ie_wr_ds1" protect="rw">
        <bits access="rw" name="rf_phy_io_dqs_ie_ds1" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_ie_ds1" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_ie_ds1" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_ie_ds1" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_ie_ds1" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_ie_ds1" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_ie_ds1" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_ie_ds1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_ie_ds1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_ie_ds1" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_oe_wr_ds1" protect="rw">
        <bits access="rw" name="rf_phy_io_dqs_oe_ds1" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_oe_ds1" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_oe_ds1" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_oe_ds1" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_oe_ds1" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_oe_ds1" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_oe_ds1" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_oe_ds1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_oe_ds1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_oe_ds1" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_cfg_phy_iomux_out_wr_ds1" protect="rw">
        <bits access="rw" name="rf_phy_io_dqs_out_ds1" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_out_ds1" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_out_ds1" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_out_ds1" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_out_ds1" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_out_ds1" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_out_ds1" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_out_ds1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_out_ds1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_out_ds1" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_status_phy_data_in" protect="r">
        <bits access="r" name="rf_phy_data_in" pos="15:0" rst="0">
      </bits>
      </reg>
      <hole size="2496"/>
      <reg name="lpddr_drf_cfg" protect="rw">
        <bits access="rw" name="drf_clkdmem_out_sel" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_reg_sel" protect="rw">
        <bits access="rw" name="drf_reg_sel" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_ie_sel_f0" protect="rw">
        <bits access="rw" name="drf_dqs_ie_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_oe_sel_f0" protect="rw">
        <bits access="rw" name="drf_dqs_oe_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_out_sel_f0" protect="rw">
        <bits access="rw" name="drf_dqs_out_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_gate_sel_f0" protect="rw">
        <bits access="rw" name="drf_dqs_gate_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_data_ie_sel_f0" protect="rw">
        <bits access="rw" name="drf_data_ie_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_data_oe_sel_f0" protect="rw">
        <bits access="rw" name="drf_data_oe_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_read_en_sel_f0" protect="rw">
        <bits access="rw" name="drf_read_en_sel_f0" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_ie_sel_f1" protect="rw">
        <bits access="rw" name="drf_dqs_ie_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_oe_sel_f1" protect="rw">
        <bits access="rw" name="drf_dqs_oe_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_out_sel_f1" protect="rw">
        <bits access="rw" name="drf_dqs_out_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_gate_sel_f1" protect="rw">
        <bits access="rw" name="drf_dqs_gate_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_data_ie_sel_f1" protect="rw">
        <bits access="rw" name="drf_data_ie_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_data_oe_sel_f1" protect="rw">
        <bits access="rw" name="drf_data_oe_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_read_en_sel_f1" protect="rw">
        <bits access="rw" name="drf_read_en_sel_f1" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_ie_sel_f2" protect="rw">
        <bits access="rw" name="drf_dqs_ie_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_oe_sel_f2" protect="rw">
        <bits access="rw" name="drf_dqs_oe_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_out_sel_f2" protect="rw">
        <bits access="rw" name="drf_dqs_out_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_gate_sel_f2" protect="rw">
        <bits access="rw" name="drf_dqs_gate_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_data_ie_sel_f2" protect="rw">
        <bits access="rw" name="drf_data_ie_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_data_oe_sel_f2" protect="rw">
        <bits access="rw" name="drf_data_oe_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_read_en_sel_f2" protect="rw">
        <bits access="rw" name="drf_read_en_sel_f2" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_ie_sel_f3" protect="rw">
        <bits access="rw" name="drf_dqs_ie_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_oe_sel_f3" protect="rw">
        <bits access="rw" name="drf_dqs_oe_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_out_sel_f3" protect="rw">
        <bits access="rw" name="drf_dqs_out_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dqs_gate_sel_f3" protect="rw">
        <bits access="rw" name="drf_dqs_gate_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_data_ie_sel_f3" protect="rw">
        <bits access="rw" name="drf_data_ie_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_data_oe_sel_f3" protect="rw">
        <bits access="rw" name="drf_data_oe_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_read_en_sel_f3" protect="rw">
        <bits access="rw" name="drf_read_en_sel_f3" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dll_mode_f0" protect="rw">
        <bits access="rw" name="drf_dll_satu_mode_f0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_half_mode_f0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_clk_mode_f0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dll_cnt_f0" protect="rw">
        <bits access="rw" name="drf_dll_auto_cnt_f0" pos="29:20" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_satu_cnt_f0" pos="19:10" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_init_cnt_f0" pos="9:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dll_mode_f1" protect="rw">
        <bits access="rw" name="drf_dll_satu_mode_f1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_half_mode_f1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_clk_mode_f1" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dll_cnt_f1" protect="rw">
        <bits access="rw" name="drf_dll_auto_cnt_f1" pos="29:20" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_satu_cnt_f1" pos="19:10" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_init_cnt_f1" pos="9:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dll_mode_f2" protect="rw">
        <bits access="rw" name="drf_dll_satu_mode_f2" pos="2" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_half_mode_f2" pos="1" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_clk_mode_f2" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dll_cnt_f2" protect="rw">
        <bits access="rw" name="drf_dll_auto_cnt_f2" pos="29:20" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_satu_cnt_f2" pos="19:10" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_init_cnt_f2" pos="9:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dll_mode_f3" protect="rw">
        <bits access="rw" name="drf_dll_satu_mode_f3" pos="2" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_half_mode_f3" pos="1" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_clk_mode_f3" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_cfg_dll_cnt_f3" protect="rw">
        <bits access="rw" name="drf_dll_auto_cnt_f3" pos="29:20" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_satu_cnt_f3" pos="19:10" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_init_cnt_f3" pos="9:0" rst="0">
      </bits>
      </reg>
      <hole size="832"/>
      <reg name="lpddr_drf_train_cfg" protect="rw">
        <bits access="rw" name="drf_dmc_rdlvl_gate_en" pos="21" rst="0">
      </bits>
        <bits access="rw" name="drf_phy_rdlvl_gate_en" pos="20" rst="0">
      </bits>
        <bits access="rw" name="drf_dmc_rdlvl_en" pos="17" rst="0">
      </bits>
        <bits access="rw" name="drf_phy_rdlvl_en" pos="16" rst="0">
      </bits>
        <bits access="rw" name="drf_dmc_wrlvl_en" pos="13" rst="0">
      </bits>
        <bits access="rw" name="drf_phy_wrlvl_en" pos="12" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_type_3" pos="11:10" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_type_2" pos="9:8" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_type_1" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_type_0" pos="5:4" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_type_sel" pos="2:1" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_mr_data_0" protect="r">
        <bits access="r" name="drf_mr_data_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_drf_mr_data_1" protect="r">
        <bits access="r" name="drf_mr_data_1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="1952"/>
      <reg name="lpddr_rf_irq_ctrl" protect="rw">
        <bits access="rw" name="rf_irq_en_dll_unlock_ds1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_dll_unlock_ds0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_dll_unlock_ac" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_irq_status_clr" protect="rw">
        <bits access="w" name="rf_irq_st_clr_dll_unlock_ds1" pos="2" rst="0">
      </bits>
        <bits access="w" name="rf_irq_st_clr_dll_unlock_ds0" pos="1" rst="0">
      </bits>
        <bits access="w" name="rf_irq_st_clr_dll_unlock_ac" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_irq_status" protect="r">
        <bits access="r" name="rf_irq_st_dll_unlock_ds1" pos="2" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_dll_unlock_ds0" pos="1" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_dll_unlock_ac" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_irq_cnt_clr" protect="rw">
        <bits access="w" name="rf_irq_cnt_clr_dll_unlock_ds1" pos="2" rst="0">
      </bits>
        <bits access="w" name="rf_irq_cnt_clr_dll_unlock_ds0" pos="1" rst="0">
      </bits>
        <bits access="w" name="rf_irq_cnt_clr_dll_unlock_ac" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_irq_cnt_dll_unlock_ac" protect="r">
        <bits access="r" name="rf_irq_cnt_overflow_dll_unlock_ac" pos="31" rst="0">
      </bits>
        <bits access="r" name="rf_irq_cnt_dll_unlock_ac" pos="30:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_irq_cnt_dll_unlock_ds0" protect="r">
        <bits access="r" name="rf_irq_cnt_overflow_dll_unlock_ds0" pos="31" rst="0">
      </bits>
        <bits access="r" name="rf_irq_cnt_dll_unlock_ds0" pos="30:0" rst="0">
      </bits>
      </reg>
      <reg name="lpddr_rf_irq_cnt_dll_unlock_ds1" protect="r">
        <bits access="r" name="rf_irq_cnt_overflow_dll_unlock_ds1" pos="31" rst="0">
      </bits>
        <bits access="r" name="rf_irq_cnt_dll_unlock_ds1" pos="30:0" rst="0">
      </bits>
      </reg>
      <hole size="1824"/>
      <reg name="io_rf_ddr_rpull_cfg" protect="rw">
        <bits access="rw" name="ddr_ck_rpull" pos="3:2" rst="0">
      </bits>
        <bits access="rw" name="ddr_dqs_rpull" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="io_rf_ddr_drv_cfg" protect="rw">
        <bits access="rw" name="ddr_drvnc" pos="19:15" rst="16">
      </bits>
        <bits access="rw" name="ddr_drvnd" pos="14:10" rst="16">
      </bits>
        <bits access="rw" name="ddr_drvpc" pos="9:5" rst="16">
      </bits>
        <bits access="rw" name="ddr_drvpd" pos="4:0" rst="16">
      </bits>
      </reg>
      <reg name="io_rf_ddr_pad_cfg" protect="rw">
        <bits access="rw" name="ddr_lp2c" pos="1" rst="1">
      </bits>
        <bits access="rw" name="ddr_lp2d" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="io_rf_ddr_vref_cfg" protect="rw">
        <bits access="rw" name="ddr_sel_int" pos="13:8" rst="32">
      </bits>
        <bits access="rw" name="ddr_sel_pad" pos="7:2" rst="32">
      </bits>
        <bits access="rw" name="ddr_vref_en_int" pos="1" rst="1">
      </bits>
        <bits access="rw" name="ddr_vref_en_pad" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="io_rf_ddr_zq_cfg" protect="rw">
        <bits access="rw" name="ddr_cal_zq_cal" pos="6" rst="0">
      </bits>
        <bits access="rw" name="ddr_cal_zq_pd" pos="5" rst="1">
      </bits>
        <bits access="rw" name="ddr_zprog" pos="4:0" rst="16">
      </bits>
      </reg>
      <reg name="io_rf_ddr_zq_mon" protect="r">
        <bits access="r" name="ddr_calover" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="io_rf_ddr_odt_cfg" protect="rw">
        <bits access="rw" name="ddr_odt_read_enable" pos="2" rst="0">
      </bits>
        <bits access="rw" name="ddr_odt_write_enable" pos="1" rst="1">
      </bits>
        <bits access="rw" name="ddr_odt_to_pad" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="io_rf_ddr_reserved" protect="rw">
        <bits access="rw" name="ddr_reg_resv" pos="31:0" rst="4294901760">
      </bits>
      </reg>
      <reg name="io_rf_psram_drv_cfg" protect="rw">
        <bits access="rw" name="psram_drvn" pos="12:8" rst="16">
      </bits>
        <bits access="rw" name="psram_drvp" pos="7:3" rst="16">
      </bits>
        <bits access="rw" name="psram_slewrate" pos="2:1" rst="0">
      </bits>
        <bits access="rw" name="psram_fix_read0" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="io_rf_psram_pad_en_cfg" protect="rw">
        <bits access="rw" name="psram_pad_clkn_en" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="io_rf_psram_pull_cfg" protect="rw">
        <bits access="rw" name="psram_cen_pull1_bit" pos="11:10" rst="1">
      </bits>
        <bits access="rw" name="psram_clk_pull0_bit" pos="9:8" rst="1">
      </bits>
        <bits access="rw" name="psram_clkn_pull1_bit" pos="7:6" rst="1">
      </bits>
        <bits access="rw" name="psram_dm_pull1_bit" pos="5:4" rst="1">
      </bits>
        <bits access="rw" name="psram_dq_pull0_bit" pos="3:2" rst="0">
      </bits>
        <bits access="rw" name="psram_dqs_pull0_bit" pos="1:0" rst="1">
      </bits>
      </reg>
      <reg name="io_rf_psram_reserved" protect="rw">
        <bits access="rw" name="psram_reg_resv" pos="31:0" rst="4294901760">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="psram_phy.xml">
    <module category="Periph" name="PSRAM_PHY">
      <reg name="psram_rf_cfg_phy" protect="rw">
        <bits access="rw" name="rf_phy_init_complete" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_clock_gate" protect="rw">
        <bits access="rw" name="rf_clk_gate_ag_rd_en" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_clk_gate_ag_wr_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_clk_gate_ag_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_clk_gate_fg_en" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_clk_gate_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_lpi" protect="rw">
        <bits access="rw" name="rf_cwakeup_s0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_cwakeup_m0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_lpi_sel_m0" pos="0" rst="0">
      </bits>
      </reg>
      <hole size="1952"/>
      <reg name="psram_rfdll_cfg_dll" protect="rw">
        <bits access="w" name="rfdll_reset" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rfdll_status_cpst_idle" protect="r">
        <bits access="r" name="rfdl_cpst_st_idle_ads1" pos="1" rst="1">
      </bits>
        <bits access="r" name="rfdl_cpst_st_idle_ads0" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="psram_rf_status_phy_data_in" protect="r">
        <bits access="r" name="rf_phy_data_in" pos="15:0" rst="0">
      </bits>
      </reg>
      <hole size="1952"/>
      <reg name="psram_rf_cfg_dll_ads0" protect="rw">
        <bits access="rw" name="rf_dll_lock_wait_ads0" pos="31:28" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_auto_err_clr_en_ads0" pos="27" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_pd_cnt_ads0" pos="26:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_thr_ads0" pos="23:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_en_ads0" pos="15" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_clk_sel_ads0" pos="14" rst="0">
      </bits>
        <bits access="w" name="rf_dll_err_clr_ads0" pos="13" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_auto_ref_en_ads0" pos="12" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_start_ads0" pos="11" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_en_ads0" pos="10" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_auto_clr_en_ads0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_clr_ads0" pos="8" rst="0">
      </bits>
      </reg>
      <reg name="psram_rfdll_status_dll_ads0" protect="r">
        <bits access="r" name="rfdll_error_ads0" pos="29" rst="0">
      </bits>
        <bits access="r" name="rfdll_locked_ads0" pos="28" rst="0">
      </bits>
        <bits access="r" name="rfdll_st_ads0" pos="27:25" rst="0">
      </bits>
        <bits access="r" name="rfdl_cpst_st_ads0" pos="24" rst="0">
      </bits>
        <bits access="r" name="rfdll_cnt_ads0" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_0_wr_ads0" protect="rw">
        <bits access="rw" name="rf_clkwr_dl_cpst_en_ads0" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_dl_cpst_minus_ads0" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_qtr_dl_cpst_offset_ads0" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_clkwr_qtr_cnt_ads0" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_qtr_dl_sel_ads0" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_raw_dl_cpst_offset_ads0" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_clkwr_raw_cnt_ads0" pos="15:8" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_raw_dl_sel_ads0" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_1_wr_ads0" protect="rw">
        <bits access="rw" name="rf_dqs_in_pos_dl_cpst_en_ads0" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_dl_cpst_minus_ads0" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_qtr_dl_cpst_offset_ads0" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_pos_qtr_cnt_ads0" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_qtr_dl_sel_ads0" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_raw_dl_cpst_offset_ads0" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_pos_raw_cnt_ads0" pos="15:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_raw_dl_sel_ads0" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_2_wr_ads0" protect="rw">
        <bits access="rw" name="rf_dqs_in_neg_dl_cpst_en_ads0" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_dl_cpst_minus_ads0" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_qtr_dl_cpst_offset_ads0" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_neg_qtr_cnt_ads0" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_qtr_dl_sel_ads0" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_raw_dl_cpst_offset_ads0" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_neg_raw_cnt_ads0" pos="15:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_raw_dl_sel_ads0" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_3_wr_ads0" protect="rw">
        <bits access="rw" name="rf_dqs_gate_dl_cpst_en_ads0" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_dl_cpst_minus_ads0" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_qtr_dl_cpst_offset_ads0" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_gate_qtr_cnt_ads0" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_qtr_dl_sel_ads0" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_raw_dl_cpst_offset_ads0" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_gate_raw_cnt_ads0" pos="15:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_raw_dl_sel_ads0" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_4_wr_ads0" protect="rw">
        <bits access="rw" name="rf_dly_out_cen_dl_sel_ads0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_clk_dl_sel_ads0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_5_wr_ads0" protect="rw">
        <bits access="rw" name="rf_dly_out_d3_dl_sel_ads0" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d2_dl_sel_ads0" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d1_dl_sel_ads0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d0_dl_sel_ads0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_6_wr_ads0" protect="rw">
        <bits access="rw" name="rf_dly_out_d7_dl_sel_ads0" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d6_dl_sel_ads0" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d5_dl_sel_ads0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d4_dl_sel_ads0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_7_wr_ads0" protect="rw">
        <bits access="rw" name="rf_dly_in_d3_dl_sel_ads0" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d2_dl_sel_ads0" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d1_dl_sel_ads0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d0_dl_sel_ads0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_8_wr_ads0" protect="rw">
        <bits access="rw" name="rf_dly_in_d7_dl_sel_ads0" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d6_dl_sel_ads0" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d5_dl_sel_ads0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d4_dl_sel_ads0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_9_wr_ads0" protect="rw">
        <bits access="rw" name="rf_dly_in_dqs_dl_sel_ads0" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_dqm_dl_sel_ads0" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_dqs_dl_sel_ads0" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rfdll_status_max_cnt_ads0" protect="r">
        <bits access="r" name="rfdll_max_cnt_f3_ads0" pos="31:24" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f2_ads0" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f1_ads0" pos="15:8" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f0_ads0" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rfdll_status_min_cnt_ads0" protect="r">
        <bits access="r" name="rfdll_min_cnt_f3_ads0" pos="31:24" rst="255">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f2_ads0" pos="23:16" rst="255">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f1_ads0" pos="15:8" rst="255">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f0_ads0" pos="7:0" rst="255">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_phy_iomux_sel_wr_ads0" protect="rw">
        <bits access="rw" name="rf_phy_io_csn_sel_ads0" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_clk_sel_ads0" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqs_sel_ads0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_sel_ads0" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_sel_ads0" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_sel_ads0" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_sel_ads0" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_sel_ads0" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_sel_ads0" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_sel_ads0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_sel_ads0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_sel_ads0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_phy_iomux_ie_wr_ads0" protect="rw">
        <bits access="rw" name="rf_phy_io_csn_ie_ads0" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_clk_ie_ads0" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqs_ie_ads0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_ie_ads0" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_ie_ads0" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_ie_ads0" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_ie_ads0" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_ie_ads0" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_ie_ads0" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_ie_ads0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_ie_ads0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_ie_ads0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_phy_iomux_oe_wr_ads0" protect="rw">
        <bits access="rw" name="rf_phy_io_csn_oe_ads0" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_clk_oe_ads0" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqs_oe_ads0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_oe_ads0" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_oe_ads0" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_oe_ads0" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_oe_ads0" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_oe_ads0" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_oe_ads0" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_oe_ads0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_oe_ads0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_oe_ads0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_phy_iomux_out_wr_ads0" protect="rw">
        <bits access="rw" name="rf_phy_io_csn_out_ads0" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_clk_out_ads0" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqs_out_ads0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_out_ads0" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_out_ads0" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_out_ads0" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_out_ads0" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_out_ads0" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_out_ads0" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_out_ads0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_out_ads0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_out_ads0" pos="0" rst="0">
      </bits>
      </reg>
      <hole size="1472"/>
      <reg name="psram_rf_cfg_dll_ads1" protect="rw">
        <bits access="rw" name="rf_dll_lock_wait_ads1" pos="31:28" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_auto_err_clr_en_ads1" pos="27" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_pd_cnt_ads1" pos="26:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_thr_ads1" pos="23:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_en_ads1" pos="15" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_clk_sel_ads1" pos="14" rst="0">
      </bits>
        <bits access="w" name="rf_dll_err_clr_ads1" pos="13" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_auto_ref_en_ads1" pos="12" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_start_ads1" pos="11" rst="0">
      </bits>
        <bits access="rw" name="rf_dl_cpst_en_ads1" pos="10" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_auto_clr_en_ads1" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_dll_clr_ads1" pos="8" rst="0">
      </bits>
      </reg>
      <reg name="psram_rfdll_status_dll_ads1" protect="r">
        <bits access="r" name="rfdll_error_ads1" pos="29" rst="0">
      </bits>
        <bits access="r" name="rfdll_locked_ads1" pos="28" rst="0">
      </bits>
        <bits access="r" name="rfdll_st_ads1" pos="27:25" rst="0">
      </bits>
        <bits access="r" name="rfdl_cpst_st_ads1" pos="24" rst="0">
      </bits>
        <bits access="r" name="rfdll_cnt_ads1" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_0_wr_ads1" protect="rw">
        <bits access="rw" name="rf_clkwr_dl_cpst_en_ads1" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_dl_cpst_minus_ads1" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_qtr_dl_cpst_offset_ads1" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_clkwr_qtr_cnt_ads1" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_qtr_dl_sel_ads1" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_raw_dl_cpst_offset_ads1" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_clkwr_raw_cnt_ads1" pos="15:8" rst="0">
      </bits>
        <bits access="rw" name="rf_clkwr_raw_dl_sel_ads1" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_1_wr_ads1" protect="rw">
        <bits access="rw" name="rf_dqs_in_pos_dl_cpst_en_ads1" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_dl_cpst_minus_ads1" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_qtr_dl_cpst_offset_ads1" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_pos_qtr_cnt_ads1" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_qtr_dl_sel_ads1" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_raw_dl_cpst_offset_ads1" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_pos_raw_cnt_ads1" pos="15:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_pos_raw_dl_sel_ads1" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_2_wr_ads1" protect="rw">
        <bits access="rw" name="rf_dqs_in_neg_dl_cpst_en_ads1" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_dl_cpst_minus_ads1" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_qtr_dl_cpst_offset_ads1" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_neg_qtr_cnt_ads1" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_qtr_dl_sel_ads1" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_raw_dl_cpst_offset_ads1" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_in_neg_raw_cnt_ads1" pos="15:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_in_neg_raw_dl_sel_ads1" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_3_wr_ads1" protect="rw">
        <bits access="rw" name="rf_dqs_gate_dl_cpst_en_ads1" pos="31" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_dl_cpst_minus_ads1" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_qtr_dl_cpst_offset_ads1" pos="29:28" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_gate_qtr_cnt_ads1" pos="27:26" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_qtr_dl_sel_ads1" pos="25:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_raw_dl_cpst_offset_ads1" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="rfdl_dqs_gate_raw_cnt_ads1" pos="15:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dqs_gate_raw_dl_sel_ads1" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_4_wr_ads1" protect="rw">
        <bits access="rw" name="rf_dly_out_cen_dl_sel_ads1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_clk_dl_sel_ads1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_5_wr_ads1" protect="rw">
        <bits access="rw" name="rf_dly_out_d3_dl_sel_ads1" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d2_dl_sel_ads1" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d1_dl_sel_ads1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d0_dl_sel_ads1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_6_wr_ads1" protect="rw">
        <bits access="rw" name="rf_dly_out_d7_dl_sel_ads1" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d6_dl_sel_ads1" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d5_dl_sel_ads1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_d4_dl_sel_ads1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_7_wr_ads1" protect="rw">
        <bits access="rw" name="rf_dly_in_d3_dl_sel_ads1" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d2_dl_sel_ads1" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d1_dl_sel_ads1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d0_dl_sel_ads1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_8_wr_ads1" protect="rw">
        <bits access="rw" name="rf_dly_in_d7_dl_sel_ads1" pos="28:24" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d6_dl_sel_ads1" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d5_dl_sel_ads1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_in_d4_dl_sel_ads1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_dll_dl_9_wr_ads1" protect="rw">
        <bits access="rw" name="rf_dly_in_dqs_dl_sel_ads1" pos="20:16" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_dqm_dl_sel_ads1" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="rf_dly_out_dqs_dl_sel_ads1" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rfdll_status_max_cnt_ads1" protect="r">
        <bits access="r" name="rfdll_max_cnt_f3_ads1" pos="31:24" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f2_ads1" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f1_ads1" pos="15:8" rst="0">
      </bits>
        <bits access="r" name="rfdll_max_cnt_f0_ads1" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rfdll_status_min_cnt_ads1" protect="r">
        <bits access="r" name="rfdll_min_cnt_f3_ads1" pos="31:24" rst="255">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f2_ads1" pos="23:16" rst="255">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f1_ads1" pos="15:8" rst="255">
      </bits>
        <bits access="r" name="rfdll_min_cnt_f0_ads1" pos="7:0" rst="255">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_phy_iomux_sel_wr_ads1" protect="rw">
        <bits access="rw" name="rf_phy_io_csn_sel_ads1" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_clk_sel_ads1" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqs_sel_ads1" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_sel_ads1" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_sel_ads1" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_sel_ads1" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_sel_ads1" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_sel_ads1" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_sel_ads1" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_sel_ads1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_sel_ads1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_sel_ads1" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_phy_iomux_ie_wr_ads1" protect="rw">
        <bits access="rw" name="rf_phy_io_csn_ie_ads1" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_clk_ie_ads1" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqs_ie_ads1" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_ie_ads1" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_ie_ads1" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_ie_ads1" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_ie_ads1" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_ie_ads1" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_ie_ads1" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_ie_ads1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_ie_ads1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_ie_ads1" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_phy_iomux_oe_wr_ads1" protect="rw">
        <bits access="rw" name="rf_phy_io_csn_oe_ads1" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_clk_oe_ads1" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqs_oe_ads1" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_oe_ads1" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_oe_ads1" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_oe_ads1" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_oe_ads1" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_oe_ads1" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_oe_ads1" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_oe_ads1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_oe_ads1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_oe_ads1" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_cfg_phy_iomux_out_wr_ads1" protect="rw">
        <bits access="rw" name="rf_phy_io_csn_out_ads1" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_clk_out_ads1" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqs_out_ads1" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_dqm_out_ads1" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d7_out_ads1" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d6_out_ads1" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d5_out_ads1" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d4_out_ads1" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d3_out_ads1" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d2_out_ads1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d1_out_ads1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_phy_io_d0_out_ads1" pos="0" rst="0">
      </bits>
      </reg>
      <hole size="1472"/>
      <reg name="psram_drf_cfg" protect="rw">
        <bits access="rw" name="drf_clkdmem_out_sel" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_reg_sel" protect="rw">
        <bits access="rw" name="drf_reg_sel" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_ie_sel_f0" protect="rw">
        <bits access="rw" name="drf_dqs_ie_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_oe_sel_f0" protect="rw">
        <bits access="rw" name="drf_dqs_oe_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_out_sel_f0" protect="rw">
        <bits access="rw" name="drf_dqs_out_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_gate_sel_f0" protect="rw">
        <bits access="rw" name="drf_dqs_gate_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_data_ie_sel_f0" protect="rw">
        <bits access="rw" name="drf_data_ie_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_data_oe_sel_f0" protect="rw">
        <bits access="rw" name="drf_data_oe_sel_f0" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_ie_sel_f1" protect="rw">
        <bits access="rw" name="drf_dqs_ie_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_oe_sel_f1" protect="rw">
        <bits access="rw" name="drf_dqs_oe_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_out_sel_f1" protect="rw">
        <bits access="rw" name="drf_dqs_out_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_gate_sel_f1" protect="rw">
        <bits access="rw" name="drf_dqs_gate_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_data_ie_sel_f1" protect="rw">
        <bits access="rw" name="drf_data_ie_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_data_oe_sel_f1" protect="rw">
        <bits access="rw" name="drf_data_oe_sel_f1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_ie_sel_f2" protect="rw">
        <bits access="rw" name="drf_dqs_ie_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_oe_sel_f2" protect="rw">
        <bits access="rw" name="drf_dqs_oe_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_out_sel_f2" protect="rw">
        <bits access="rw" name="drf_dqs_out_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_gate_sel_f2" protect="rw">
        <bits access="rw" name="drf_dqs_gate_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_data_ie_sel_f2" protect="rw">
        <bits access="rw" name="drf_data_ie_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_data_oe_sel_f2" protect="rw">
        <bits access="rw" name="drf_data_oe_sel_f2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_ie_sel_f3" protect="rw">
        <bits access="rw" name="drf_dqs_ie_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_oe_sel_f3" protect="rw">
        <bits access="rw" name="drf_dqs_oe_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_out_sel_f3" protect="rw">
        <bits access="rw" name="drf_dqs_out_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dqs_gate_sel_f3" protect="rw">
        <bits access="rw" name="drf_dqs_gate_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_data_ie_sel_f3" protect="rw">
        <bits access="rw" name="drf_data_ie_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_data_oe_sel_f3" protect="rw">
        <bits access="rw" name="drf_data_oe_sel_f3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dll_mode_f0" protect="rw">
        <bits access="rw" name="drf_dll_satu_mode_f0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_half_mode_f0" pos="1" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_clk_mode_f0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dll_cnt_f0" protect="rw">
        <bits access="rw" name="drf_dll_auto_cnt_f0" pos="29:20" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_satu_cnt_f0" pos="19:10" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_init_cnt_f0" pos="9:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dll_mode_f1" protect="rw">
        <bits access="rw" name="drf_dll_satu_mode_f1" pos="2" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_half_mode_f1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_clk_mode_f1" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dll_cnt_f1" protect="rw">
        <bits access="rw" name="drf_dll_auto_cnt_f1" pos="29:20" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_satu_cnt_f1" pos="19:10" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_init_cnt_f1" pos="9:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dll_mode_f2" protect="rw">
        <bits access="rw" name="drf_dll_satu_mode_f2" pos="2" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_half_mode_f2" pos="1" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_clk_mode_f2" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dll_cnt_f2" protect="rw">
        <bits access="rw" name="drf_dll_auto_cnt_f2" pos="29:20" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_satu_cnt_f2" pos="19:10" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_init_cnt_f2" pos="9:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dll_mode_f3" protect="rw">
        <bits access="rw" name="drf_dll_satu_mode_f3" pos="2" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_half_mode_f3" pos="1" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_clk_mode_f3" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_cfg_dll_cnt_f3" protect="rw">
        <bits access="rw" name="drf_dll_auto_cnt_f3" pos="29:20" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_satu_cnt_f3" pos="19:10" rst="0">
      </bits>
        <bits access="rw" name="drf_dll_init_cnt_f3" pos="9:0" rst="0">
      </bits>
      </reg>
      <hole size="960"/>
      <reg name="psram_drf_format_control" protect="rw">
        <bits access="rw" name="drf_memory_burst" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_rcd" protect="rw">
        <bits access="rw" name="drf_t_rcd" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_rddata_en" protect="rw">
        <bits access="rw" name="drf_t_rddata_en" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_phywrlat" protect="rw">
        <bits access="rw" name="drf_t_phywrlat" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_cph_wr" protect="rw">
        <bits access="rw" name="drf_t_cph_wr" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_cph_rd" protect="rw">
        <bits access="rw" name="drf_t_cph_rd_optm" pos="4" rst="0">
      </bits>
        <bits access="rw" name="drf_t_cph_rd" pos="2:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_data_oe_ext" protect="rw">
        <bits access="rw" name="drf_t_data_oe_cmd_ext" pos="7:4" rst="0">
      </bits>
        <bits access="rw" name="drf_t_data_oe_wdata_ext" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_dqs_oe_ext" protect="rw">
        <bits access="rw" name="drf_t_dqs_oe_ext" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_xphs" protect="rw">
        <bits access="rw" name="drf_t_xphs" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_rddata_vld_sync" protect="rw">
        <bits access="rw" name="drf_t_rddata_vld_sync" pos="2:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_rddata_late" protect="rw">
        <bits access="rw" name="drf_t_rddata_late" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_t_rddata_valid_early" protect="rw">
        <bits access="rw" name="drf_t_rddata_valid_early" pos="1:0" rst="0">
      </bits>
      </reg>
      <hole size="1664"/>
      <reg name="psram_drf_train_cfg" protect="rw">
        <bits access="rw" name="drf_dmc_rdlvl_gate_en" pos="21" rst="0">
      </bits>
        <bits access="rw" name="drf_phy_rdlvl_gate_en" pos="20" rst="0">
      </bits>
        <bits access="rw" name="drf_dmc_rdlvl_en" pos="17" rst="0">
      </bits>
        <bits access="rw" name="drf_phy_rdlvl_en" pos="16" rst="0">
      </bits>
        <bits access="rw" name="drf_dmc_wrlvl_en" pos="13" rst="0">
      </bits>
        <bits access="rw" name="drf_phy_wrlvl_en" pos="12" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_type_3" pos="11:10" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_type_2" pos="9:8" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_type_1" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_type_0" pos="5:4" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_type_sel" pos="2:1" rst="0">
      </bits>
        <bits access="rw" name="drf_phyupd_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_mr_data_en" protect="rw">
        <bits access="rw" name="drf_mr_data_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_mr_data_0" protect="r">
        <bits access="r" name="drf_mr_data_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_drf_mr_data_1" protect="r">
        <bits access="r" name="drf_mr_data_1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="1920"/>
      <reg name="psram_rf_irq_ctrl" protect="rw">
        <bits access="rw" name="rf_irq_en_disc_rd_ads1" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_disc_wr_ads1" pos="19" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_disc_mrr_ads1" pos="18" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_disc_mrw_ads1" pos="17" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_disc_rst_ads1" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_disc_rd_ads0" pos="12" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_disc_wr_ads0" pos="11" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_disc_mrr_ads0" pos="10" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_disc_mrw_ads0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_disc_rst_ads0" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_rddata_timeout_ads1" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_rddata_timeout_ads0" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_dll_unlock_ads1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_en_dll_unlock_ads0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_irq_status_clr" protect="rw">
        <bits access="rw" name="rf_irq_st_clr_disc_rd_ads1" pos="20" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_disc_wr_ads1" pos="19" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_disc_mrr_ads1" pos="18" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_disc_mrw_ads1" pos="17" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_disc_rst_ads1" pos="16" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_disc_rd_ads0" pos="12" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_disc_wr_ads0" pos="11" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_disc_mrr_ads0" pos="10" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_disc_mrw_ads0" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_disc_rst_ads0" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_rddata_timeout_ads1" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_rddata_timeout_ads0" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_dll_unlock_ads1" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rf_irq_st_clr_dll_unlock_ads0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_irq_status" protect="r">
        <bits access="r" name="rf_irq_st_disc_rd_ads1" pos="20" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_disc_wr_ads1" pos="19" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_disc_mrr_ads1" pos="18" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_disc_mrw_ads1" pos="17" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_disc_rst_ads1" pos="16" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_disc_rd_ads0" pos="12" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_disc_wr_ads0" pos="11" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_disc_mrr_ads0" pos="10" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_disc_mrw_ads0" pos="9" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_disc_rst_ads0" pos="8" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_rddata_timeout_ads1" pos="5" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_rddata_timeout_ads0" pos="4" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_dll_unlock_ads1" pos="1" rst="0">
      </bits>
        <bits access="r" name="rf_irq_st_dll_unlock_ads0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_irq_cnt_clr" protect="rw">
        <bits access="w" name="rf_irq_cnt_clr_dll_unlock_ads1" pos="1" rst="0">
      </bits>
        <bits access="w" name="rf_irq_cnt_clr_dll_unlock_ads0" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_irq_cnt_dll_unlock_ads0" protect="r">
        <bits access="r" name="rf_irq_cnt_overflow_dll_unlock_ads0" pos="31" rst="0">
      </bits>
        <bits access="r" name="rf_irq_cnt_dll_unlock_ads0" pos="30:0" rst="0">
      </bits>
      </reg>
      <reg name="psram_rf_irq_cnt_dll_unlock_ads1" protect="r">
        <bits access="r" name="rf_irq_cnt_overflow_dll_unlock_ads1" pos="31" rst="0">
      </bits>
        <bits access="r" name="rf_irq_cnt_dll_unlock_ads1" pos="30:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="lpddr_psram.xml">
    <module category="Memory" name="LPDDR_MEM">
      <var name="LPDDR_MEM_SIZE" value="0x04000000"/>
      <memory name="lpddr_mem" size="LPDDR_MEM_SIZE">
	</memory>
    </module>
    <module category="Memory" name="PSRAM_MEM">
      <var name="PSRAM_MEM_SIZE" value="0x01000000"/>
      <memory name="psram_mem" size="PSRAM_MEM_SIZE">
	</memory>
    </module>
  </archive>
  <archive relative="dbg_a5.xml">
    <module category="Debug" name="DBG_A5">
      <reg name="dbgdidr" protect="r">
        <bits access="r" name="wrp" pos="31:28" rst="1">
          <comment>Number of Watchpoint Register Pairs:
For the Cortex-A5 processor, this field reads as b0001 to indicate two WRPs are
implemented.</comment>
        </bits>
        <bits access="r" name="brp" pos="27:24" rst="2">
          <comment>Number of Breakpoint Register Pairs:
For the Cortex-A5 processor, this field reads as b0010 to indicate three BRPs are
implemented.</comment>
        </bits>
        <bits access="r" name="context" pos="23:20" rst="0">
          <comment>Number of Breakpoint Register Pairs with context ID comparison capability:
For the Cortex-A5 processor, this field reads as b0000 to indicate one BRP has context ID
capability.</comment>
        </bits>
        <bits access="r" name="dbg_arch_ver" pos="19:16" rst="3">
          <comment>Debug architecture version:
b0011 = ARMv7 Debug with Extended CP14 interface implemented.</comment>
        </bits>
        <bits access="r" name="devid_imp" pos="15" rst="1">
          <comment>For the Cortex-A5 processor, this field reads as b1 to indicate that the Debug Device ID
Register, DBGDEVID is implemented</comment>
        </bits>
        <bits access="r" name="sec_usr_halt_dbg_not_support" pos="14" rst="1">
          <comment>For the Cortex-A5 processor, this field reads as b1 to indicate that Secure User halting debug
is not supported</comment>
        </bits>
        <bits access="r" name="pc_sample_reg" pos="13" rst="1">
          <comment>Program Counter Sample Register, DBGPCSR.
For the Cortex-A5 processor, this field reads as b1 to indicate that DBGPCSR is
implemented as debug register 33.</comment>
        </bits>
        <bits access="r" name="sec_extension" pos="12" rst="1">
          <comment>Security extensions bit:
For the Cortex-A5 processor, this field reads as b1 to indicate that the debug security
extensions are implemented.</comment>
        </bits>
        <bits access="r" name="variant" pos="7:4" rst="0">
          <comment>Implementation-defined variant number. This number is incremented on functional changes.
The value matches bits [23:20] of the ID Code Register in CP15 c0.</comment>
        </bits>
        <bits access="r" name="revision" pos="3:0" rst="0">
          <comment>Implementation-defined revision number. This number is incremented on bug fixes. The
value matches bits [3:0] of the ID Code Register in CP15 c0.</comment>
        </bits>
      </reg>
      <reg name="dbgdscrint" protect="rw">
        <bits access="r" name="rxfull" pos="30" rst="0">
          <comment>The DBGDTRRX Register full flag:
0 = DBGDTRRX empty, reset value
1 = DBGDTRRX full.
When set, this flag indicates that there is data available in the Receive Data Transfer Register,
DBGDTRRX. It is automatically set on writes to the DBGDTRRXext by the debugger, and is cleared
when the processor reads the CP14 DBGDTRRXint. If the flag is not set, reads of the DBGDTRRX return
an Unpredictable value.</comment>
        </bits>
        <bits access="r" name="txfull" pos="29" rst="0">
          <comment>The DBGDTRTX Register full flag:
0 = DBGDTRTX empty, reset value
1 = DBGDTRTX full.
When clear, this flag indicates that the Transmit Data Transfer Register, DBGDTRTX is ready for data
write. It is automatically cleared on reads of the DBGDTRTXext by the debugger, and is set when the
processor writes to the CP14 DBGDTRTXint. If this bit is set and the processor attempts to write to the
DBGDTRTXint, results are Unpredictable.</comment>
        </bits>
        <bits access="r" name="rxfull_l" pos="27" rst="0">
          <comment>The latched DBGDTRRX Register full flag. This flag is read in one of the following ways:
? in DBGDSCRint using a CP14 instruction
? in DBGDSCRext using the APB interface or CP14 instruction.
Reads of DBGDSCRint return an Unpredictable value for this bit.
Reads of DBGDSCRext return the same value as RXfull.
If a write to the DBGDTRRXext address succeeds, RXfull_l is set to 1.</comment>
        </bits>
        <bits access="r" name="txfull_l" pos="26" rst="0">
          <comment>The latched DBGDTRTX Register full flag. This flag is read in one of the following ways:
? in DBGDSCRint using a CP14 instruction
? in DBGDSCRext using the APB interface or CP14 instruction.
Reads of DBGDSCRint return an Unpredictable value for this bit.
Reads of DBGDSCRext return the same value as TXfull.
If a read to the DBGDTRTXext address succeeds, TXfull_l is cleared.</comment>
        </bits>
        <bits access="r" name="sticky_pipeline_advance" pos="25" rst="0">
          <comment>Sticky pipeline advance bit. This bit enables the debugger to detect whether the processor is idle. In some
situations, this might mean that the system bus port is deadlocked. This bit is set to 1 every time the
processor pipeline retires one instruction. A write to DBGDRCR[3] clears this bit. See Debug Run Control
Register on page 9-19.
0 = no instruction has completed execution since the last time this bit was cleared, reset value
1 = an instruction has completed execution since the last time this bit was cleared.</comment>
        </bits>
        <bits access="r" name="instrcompl_l" pos="24" rst="0">
          <comment>The latched InstrCompl flag. This flag is read in one of the following ways:
? in DBGDSCRint using CP14 instructions
? in DBGDSCRext using the APB interface.
When in Non-debug state, all reads of DBGDSCR return an Unpredictable value for this bit. Otherwise,
reads through the CP14 interface return an Unpredictable value for this bit.
Reads of the DBGDSCRext APB address return the same value as InstrCompl.
If a write to the DBGITR APB address succeeds while in Stall or Nonblocking mode, InstrCompl_l and
InstrCompl are cleared.
If a write to the DBGDTRRXext APB address or a read to the DBGDTRTXext APB address succeeds
while in Fast mode, InstrCompl_l and InstrCompl are cleared.
InstrCompl is the instruction complete bit. This internal flag determines whether the processor has
completed execution of an instruction issued through the APB interface.
0 = the processor is currently executing an instruction fetched from the DBGITR Register, reset value
1 = the processor is not currently executing an instruction fetched from the DBGITR Register.</comment>
        </bits>
        <bits access="rw" name="extdccmode" pos="21:20" rst="0">
          <comment>External DCC access mode. This is a read and write field. You can use this field to optimize DTR and
DBGITR traffic between a debugger and the processor:
b00 = Nonblocking mode, reset value
b01 = Stall mode
b10 = Fast mode
b11 = reserved.
Note
? This field only affects the behavior of DBGDSCR, DTR, and DBGITR accesses through the APB
port, and not through CP14 debug instructions.
? Nonblocking mode is the default setting. Improper use of the other modes might result in the debug
access bus becoming jammed.
See External DCC and DBGITR access mode on page 9-17 for more information.</comment>
        </bits>
        <bits access="r" name="discardasynchronousabort" pos="19" rst="0">
          <comment>Discard asynchronous abort. This read-only bit is set while the processor is in debug state and is cleared
on exit from debug state. While this bit is set, the processor does not record asynchronous Data Aborts.
However, the sticky asynchronous Data Abort bit is set to 1.
0 = asynchronous Data Aborts not discarded, reset value
1 = asynchronous Data Aborts discarded.</comment>
        </bits>
        <bits access="r" name="non_sec_status" pos="18" rst="0">
          <comment>Non-secure state status bit:
0 = the processor is in Secure state or the processor is in Monitor mode
1 = the processor is in Non-secure state and is not in Monitor mode.</comment>
        </bits>
        <bits access="r" name="sec_previledge_noninvasive_dbg_disabled" pos="17" rst="0">
          <comment>Secure privileged noninvasive debug disabled:
0 = ((NIDEN || DBGEN) &amp;&amp; (SPNIDEN || SPIDEN)) is HIGH
1 = ((NIDEN || DBGEN) &amp;&amp; (SPNIDEN || SPIDEN)) is LOW.
This value is the inverse of bit [6] of the Authentication Status Register. See Authentication Status Register
on page 9-33.</comment>
        </bits>
        <bits access="r" name="sec_previledge_invasive_dbg_disabled" pos="16" rst="0">
          <comment>Secure privileged invasive debug disabled:
0 = (DBGEN &amp;&amp; SPIDEN) is HIGH
1 = (DBGEN &amp;&amp; SPIDEN) is LOW.
This value is the inverse of bit [4] of the Authentication Status Register. See Authentication Status Register
on page 9-33.</comment>
        </bits>
        <bits access="rw" name="monitor_debug_mode_enable" pos="15" rst="0">
          <comment>The Monitor debug-mode enable bit. This is a read and write bit.
0 = Monitor debug-mode disabled, reset value
1 = Monitor debug-mode enabled.
If Halting debug-mode is enabled, bit [14] is set, then the processor is in Halting debug-mode regardless
of the value of bit [15]. If the external interface input DBGEN is LOW, DBGDSCR[15] reads as 0. If
DBGEN is HIGH, then the read value reverts to the programmed value.</comment>
        </bits>
        <bits access="rw" name="galting_debug_mode" pos="14" rst="0">
          <comment>The Halting debug-mode enable bit. This is a read and write bit.
0 = Halting debug-mode disabled, reset value
1 = Halting debug-mode enabled.
If the external interface input DBGEN is LOW, DBGDSCR[14] reads as 0. If DBGEN is HIGH, then the
read value reverts to the programmed value.</comment>
        </bits>
        <bits access="rw" name="execute_instruction_enable" pos="13" rst="0">
          <comment>Execute ARM instruction enable bit. This is a read and write bit.
0 = disabled, reset value
1 = enabled.
If this bit is set and a DBGITR write succeeds, the processor fetches an instruction from the DBGITR for
execution. If this bit is set to 1 when the processor is not in debug state, the behavior of the processor is
Unpredictable.</comment>
        </bits>
        <bits access="rw" name="cp14_dbg_user_disable_ctrl" pos="12" rst="0">
          <comment>CP14 debug user access disable control bit. This is a read and write bit.
0 = CP14 debug user access enable, reset value
1 = CP14 debug user access disable.
If this bit is set and a User mode process tries to access any CP14 debug registers, the Undefined
instruction exception is taken.</comment>
        </bits>
        <bits access="rw" name="interrupt_disable" pos="11" rst="0">
          <comment>Interrupts disable bit. This is a read and write bit.
0 = interrupts enabled, reset value
1 = interrupts disabled.
If this bit is set, the IRQ and FIQ input signals are disabled. The external debugger can set this bit before
it executes code in normal state as part of the debugging process. If this bit is set to 1, an interrupt does
not take control of the program flow. For example, the debugger might use this bit to execute an OS service
routine to bring a page from disk into memory. It might be undesirable to service any interrupt during the
routine execution.
This bit is ignored when either:
? DBGDSCR[15:14] == 0b00
? DBGEN is LOW.</comment>
        </bits>
        <bits access="rw" name="dbgack" pos="10" rst="0">
          <comment>Debug Acknowledge bit. This is a read and write bit. If this bit is set to 1, both the DBGACK and
DBGTRIGGER output signals are forced HIGH, regardless of the processor state. The external debugger
can use this bit if it wants the system to behave as if the processor is in debug state. Some systems rely on
DBGACK to determine whether the application or debugger generates the data accesses. The reset value
is 0.</comment>
        </bits>
        <bits access="r" name="sticky_undefined" pos="8" rst="0">
          <comment>Sticky Undefined bit:
0 = No Undefined instruction exception occurred in debug state since the last time this bit was cleared.
This is the reset value.
1 = An Undefined instruction exception has occurred while in debug state since the last time this bit was
cleared.
This flag detects Undefined instruction exceptions generated by instructions issued to the processor
through the DBGITR. This bit is set to 1 when an Undefined instruction exception occurs while the
processor is in debug state. Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register
on page 9-19.</comment>
        </bits>
        <bits access="r" name="sticky_async_abort" pos="7" rst="0">
          <comment>Sticky asynchronous Data Abort bit:
0 = no asynchronous Aborts occurred since the last time this bit was cleared, reset value
1 = an asynchronous Abort occurred since the last time this bit was cleared.
This flag detects asynchronous Aborts triggered by instructions issued to the processor through the
DBGITR. This bit is set to 1 when an asynchronous Abort occurs while the processor is in debug state.
Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register on page 9-19.</comment>
        </bits>
        <bits access="r" name="sticky_sync_abort" pos="6" rst="0">
          <comment>Sticky synchronous Data Abort bit:
0 = no synchronous Data Abort occurred since the last time this bit was cleared, reset value
1 = a synchronous Data Abort occurred since the last time this bit was cleared.
This flag detects synchronous Data Aborts generated by instructions issued to the processor through the
DBGITR. This bit is set to 1 when a synchronous Data Abort occurs while the processor is in debug state.
Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register on page 9-19.
When this is set, no instructions are issued through the DBGITR. Writes to DBGITR are ignored and, if
ExtDCCmode is configured for Fast mode, reads of DBGDTRTXext and writes of DBGDTRRXext are
ignored.</comment>
        </bits>
        <bits access="r" name="moe" pos="5:2" rst="0">
          <comment>MOE, Method of entry bits. This is a read and write field.
b0000 = a DRCR[0] halting debug event occurred, reset value
b0001 = a breakpoint occurred
b0010 = not supported
b0011 = a BKPT instruction occurred
b0100 = an EDBGRQ halting debug event occurred
b0101 = a vector catch debug event occurred
b1010 = a synchronous watchpoint debug event occurred
other = reserved.
These bits are set to indicate any of:
? the cause of a debug exception
? the cause for entering debug state.
A Prefetch Abort or Data Abort handler must check the value of the CP15 Fault Status Register to
determine whether a debug exception occurred and then use these bits to determine the specific debug
event.</comment>
        </bits>
        <bits access="r" name="core_restarted" pos="1" rst="0">
          <comment>Core restarted bit:
0 = The processor is exiting debug state.
1 = The processor has exited debug state. This is the reset value.
The debugger can poll this bit to determine when the processor responds to a request to leave debug state</comment>
        </bits>
        <bits access="r" name="core_halted" pos="0" rst="0">
          <comment>Core halted bit:
0 = The processor is in normal state. This is the reset value.
1 = The processor is in debug state.
The debugger can poll this bit to determine when the processor has entered debug state.</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="dbgvcr" protect="rw">
        <bits access="rw" name="dbgvcr" pos="17:0" rst="0">
          <comment>DBGVCR</comment>
        </bits>
      </reg>
      <hole size="768"/>
      <reg name="dbgdtrrxext" protect="rw">
        <bits access="rw" name="dtrrx" pos="31:0" rst="0">
          <comment>dtrrx</comment>
        </bits>
      </reg>
      <reg name="dbgitr" protect="r">
        <bits access="r" name="old_pcsr" pos="31:0" rst="0">
          <comment>old location of PCSR</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dbgdtrtxext" protect="rw">
        <bits access="rw" name="dtrrx" pos="31:0" rst="0">
          <comment>dtrrx</comment>
        </bits>
      </reg>
      <reg name="dbgdrcr" protect="rw">
        <bits access="rw" name="cancel_biu_req" pos="4" rst="0">
          <comment>Cancel BIU request</comment>
        </bits>
        <bits access="rw" name="clear_sticky_pipeline_advance" pos="3" rst="0">
          <comment>Clear sticky pipeline advance. Writing a 1 to this bit clears DBGDSCR[25].</comment>
        </bits>
        <bits access="rw" name="clear_sticky_exception" pos="2" rst="0">
          <comment>Clear sticky exceptions. Writing a 1 to this bit clears DBGDSCR[8:6].</comment>
        </bits>
        <bits access="rw" name="restart_request" pos="1" rst="0">
          <comment>Restart request. Writing a 1 to this bit requests that the processor leaves debug state. This request
is held until the processor exits debug state. When the debugger makes this request, it polls
DBGDSCR[1] until it reads 1. This bit always reads as zero. Writes are ignored when the processor
is not in debug state.</comment>
        </bits>
        <bits access="rw" name="halt_request" pos="0" rst="0">
          <comment>Halt request. Writing a 1 to this bit triggers a halting debug event, that is, a request that the
processor enters debug state. This request is held until the debug state entry occurs. When the
debugger makes this request, it polls DBGDSCR[0] until it reads 1. This bit always reads as zero.
Writes are ignored when the processor is already in debug state.</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="dbgpcsr" protect="r">
        <bits access="r" name="pc_sample_value" pos="31:2" rst="0">
          <comment>The sampled value of bits [31:2] of the Program Counter</comment>
        </bits>
        <bits access="r" name="pc_meaning" pos="1:0" rst="0">
          <comment>Meaning of Program Counter Sample value:
b00 = References an ARM state instruction.
bx1 = References a Thumb or ThumbEE state instruction.
b10 = Jazelle-DBX.</comment>
        </bits>
      </reg>
      <reg name="dbgcidsr" protect="r">
        <bits access="r" name="context_id" pos="31:0" rst="0">
          <comment>context ID</comment>
        </bits>
      </reg>
      <hole size="704"/>
      <reg name="dbgbvr0" protect="rw">
        <bits access="rw" name="breaking_point_0" pos="31:0" rst="0">
          <comment>Breakpoint value. The reset value is Unpredictable
Contains the breakpoint value that corresponds to either an instruction
address or a context ID. Breakpoints can be set on:
? an instruction address
? a context ID value
? an instruction address and context ID pair.
For an instruction address and context ID pair, two BRPs must be linked.
A debug event is generated when both the instruction address and the
context ID pair match at the same time.
Note
? Only BRP2 supports context ID comparison.
? DBGBVR0[1:0] and DBGBVR1[1:0] are SBZP on writes and RAZ on reads because
these registers do not support context ID comparisons.
? The context ID value for DBGBVR2 to match with is given by the contents of the CP15
Context ID Register. See Chapter 4 System Control for information on the Context ID
Register.</comment>
        </bits>
      </reg>
      <reg name="dbgbvr1" protect="rw">
        <bits access="rw" name="breaking_point_1" pos="31:0" rst="0">
          <comment>Breakpoint value. The reset value is Unpredictable</comment>
        </bits>
      </reg>
      <reg name="dbgbvr2" protect="rw">
        <bits access="rw" name="breaking_point_2" pos="31:0" rst="0">
          <comment>Breakpoint value. The reset value is Unpredictable</comment>
        </bits>
      </reg>
      <hole size="416"/>
      <reg name="dbgbcr0" protect="rw">
        <bits access="r" name="breakpoint_address_mask" pos="28:24" rst="0">
          <comment>Breakpoint address mask.
RAZ/WI
b00000 = no mask</comment>
        </bits>
        <bits access="rw" name="m" pos="22:20" rst="0">
          <comment>Meaning of DBGBVR:
b000 = instruction virtual address match
b001 = linked instruction virtual address match
b010 = unlinked context ID
b011 = linked context ID
b100 = instruction virtual address mismatch
b101 = linked instruction virtual address mismatch
b11x = reserved.
Note
DBGBCR0[21] and DBGBCR1[21] are RAZ on reads because these registers do not have context ID
comparison capability.</comment>
        </bits>
        <bits access="rw" name="linked_brp" pos="19:16" rst="0">
          <comment>Linked BRP number. The binary number encoded here indicates another BRP to link this one with.
Note
? If a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated
? If this BRP is linked to another BRP that is not configured for linked context ID matching, it is
Unpredictable whether a breakpoint debug event is generated.</comment>
        </bits>
        <bits access="rw" name="secure_state_access_control" pos="15:14" rst="9">
          <comment>Secure state access control. This field enables the breakpoint to be conditional on the security state of the
processor.
b00 = breakpoint matches in both Secure and Non-secure state
b01 = breakpoint only matches in Non-secure state
b10 = breakpoint only matches in Secure state
b11 = reserved.</comment>
        </bits>
        <bits access="rw" name="byte_address_select" pos="8:5" rst="0">
          <comment>Byte address select. For breakpoints programmed to match an instruction address, you must write a
word-aligned address to the DBGBVR. You can then use this field to program the breakpoint so it hits
only if you access certain byte addresses.
If you program the BRP for instruction address match:
b0000 = the breakpoint never hits
b0011 = the breakpoint hits if any of the two bytes starting at address DBGBVR &amp; 0xFFFFFFFC +0 is
accessed
b1100 = the breakpoint hits if any of the two bytes starting at address DBGBVR &amp; 0xFFFFFFFC +2 is
accessed
b1111 = the breakpoint hits if any of the four bytes starting at address DBGBVR &amp; 0xFFFFFFFC +0 is
accessed.
If you program the BRP for instruction address mismatch, the breakpoint hits where the corresponding
instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction
address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint.
If you program the BRP for context ID comparison, this field must be set to b1111. Otherwise, breakpoint
and watchpoint debug events might not be generated as expected.</comment>
        </bits>
        <bits access="rw" name="s" pos="2:1" rst="0">
          <comment>Supervisor access control. The breakpoint can be conditioned on the mode of the processor.
b00 = User, System, or Supervisor
b01 = privileged
b10 = User
b11 = any.</comment>
        </bits>
        <bits access="rw" name="b" pos="0" rst="0">
          <comment>Breakpoint enable:
0 = breakpoint disabled, reset value
1 = breakpoint enabled.</comment>
        </bits>
      </reg>
      <reg name="dbgbcr1" protect="rw">
        <bits access="r" name="breakpoint_address_mask" pos="28:24" rst="0">
          <comment>Breakpoint address mask.
RAZ/WI
b00000 = no mask</comment>
        </bits>
        <bits access="rw" name="m" pos="22:20" rst="0">
          <comment>Meaning of DBGBVR:
b000 = instruction virtual address match
b001 = linked instruction virtual address match
b010 = unlinked context ID
b011 = linked context ID
b100 = instruction virtual address mismatch
b101 = linked instruction virtual address mismatch
b11x = reserved.
Note
DBGBCR0[21] and DBGBCR1[21] are RAZ on reads because these registers do not have context ID
comparison capability.</comment>
        </bits>
        <bits access="rw" name="linked_brp" pos="19:16" rst="0">
          <comment>Linked BRP number. The binary number encoded here indicates another BRP to link this one with.
Note
? If a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated
? If this BRP is linked to another BRP that is not configured for linked context ID matching, it is
Unpredictable whether a breakpoint debug event is generated.</comment>
        </bits>
        <bits access="rw" name="secure_state_access_control" pos="15:14" rst="0">
          <comment>Secure state access control. This field enables the breakpoint to be conditional on the security state of the
processor.
b00 = breakpoint matches in both Secure and Non-secure state
b01 = breakpoint only matches in Non-secure state
b10 = breakpoint only matches in Secure state
b11 = reserved.</comment>
        </bits>
        <bits access="rw" name="byte_address_select" pos="8:5" rst="0">
          <comment>Byte address select. For breakpoints programmed to match an instruction address, you must write a
word-aligned address to the DBGBVR. You can then use this field to program the breakpoint so it hits
only if you access certain byte addresses.
If you program the BRP for instruction address match:
b0000 = the breakpoint never hits
b0011 = the breakpoint hits if any of the two bytes starting at address DBGBVR &amp; 0xFFFFFFFC +0 is
accessed
b1100 = the breakpoint hits if any of the two bytes starting at address DBGBVR &amp; 0xFFFFFFFC +2 is
accessed
b1111 = the breakpoint hits if any of the four bytes starting at address DBGBVR &amp; 0xFFFFFFFC +0 is
accessed.
If you program the BRP for instruction address mismatch, the breakpoint hits where the corresponding
instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction
address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint.
If you program the BRP for context ID comparison, this field must be set to b1111. Otherwise, breakpoint
and watchpoint debug events might not be generated as expected.</comment>
        </bits>
        <bits access="rw" name="s" pos="2:1" rst="0">
          <comment>Supervisor access control. The breakpoint can be conditioned on the mode of the processor.
b00 = User, System, or Supervisor
b01 = privileged
b10 = User
b11 = any.</comment>
        </bits>
        <bits access="rw" name="b" pos="0" rst="0">
          <comment>Breakpoint enable:
0 = breakpoint disabled, reset value
1 = breakpoint enabled.</comment>
        </bits>
      </reg>
      <reg name="dbgbcr2" protect="rw">
        <bits access="r" name="breakpoint_address_mask" pos="28:24" rst="0">
          <comment>Breakpoint address mask.
RAZ/WI
b00000 = no mask</comment>
        </bits>
        <bits access="rw" name="m" pos="22:20" rst="0">
          <comment>Meaning of DBGBVR:
b000 = instruction virtual address match
b001 = linked instruction virtual address match
b010 = unlinked context ID
b011 = linked context ID
b100 = instruction virtual address mismatch
b101 = linked instruction virtual address mismatch
b11x = reserved.
Note
DBGBCR0[21] and DBGBCR1[21] are RAZ on reads because these registers do not have context ID
comparison capability.</comment>
        </bits>
        <bits access="rw" name="linked_brp" pos="19:16" rst="0">
          <comment>Linked BRP number. The binary number encoded here indicates another BRP to link this one with.
Note
? If a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated
? If this BRP is linked to another BRP that is not configured for linked context ID matching, it is
Unpredictable whether a breakpoint debug event is generated.</comment>
        </bits>
        <bits access="rw" name="secure_state_access_control" pos="15:14" rst="0">
          <comment>Secure state access control. This field enables the breakpoint to be conditional on the security state of the
processor.
b00 = breakpoint matches in both Secure and Non-secure state
b01 = breakpoint only matches in Non-secure state
b10 = breakpoint only matches in Secure state
b11 = reserved.</comment>
        </bits>
        <bits access="rw" name="byte_address_select" pos="8:5" rst="0">
          <comment>Byte address select. For breakpoints programmed to match an instruction address, you must write a
word-aligned address to the DBGBVR. You can then use this field to program the breakpoint so it hits
only if you access certain byte addresses.
If you program the BRP for instruction address match:
b0000 = the breakpoint never hits
b0011 = the breakpoint hits if any of the two bytes starting at address DBGBVR &amp; 0xFFFFFFFC +0 is
accessed
b1100 = the breakpoint hits if any of the two bytes starting at address DBGBVR &amp; 0xFFFFFFFC +2 is
accessed
b1111 = the breakpoint hits if any of the four bytes starting at address DBGBVR &amp; 0xFFFFFFFC +0 is
accessed.
If you program the BRP for instruction address mismatch, the breakpoint hits where the corresponding
instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction
address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint.
If you program the BRP for context ID comparison, this field must be set to b1111. Otherwise, breakpoint
and watchpoint debug events might not be generated as expected.</comment>
        </bits>
        <bits access="rw" name="s" pos="2:1" rst="0">
          <comment>Supervisor access control. The breakpoint can be conditioned on the mode of the processor.
b00 = User, System, or Supervisor
b01 = privileged
b10 = User
b11 = any.</comment>
        </bits>
        <bits access="rw" name="b" pos="0" rst="0">
          <comment>Breakpoint enable:
0 = breakpoint disabled, reset value
1 = breakpoint enabled.</comment>
        </bits>
      </reg>
      <hole size="416"/>
      <reg name="dbgbwvr0" protect="rw">
        <bits access="rw" name="watchpoint_addr" pos="31:2" rst="0">
          <comment>Watchpoint address</comment>
        </bits>
      </reg>
      <reg name="dbgbwvr1" protect="rw">
        <bits access="rw" name="watchpoint_addr" pos="31:2" rst="0">
          <comment>Watchpoint address</comment>
        </bits>
      </reg>
      <reg name="dbgbwvr2" protect="rw">
        <bits access="rw" name="watchpoint_addr" pos="31:2" rst="0">
          <comment>Watchpoint address</comment>
        </bits>
      </reg>
      <hole size="416"/>
      <reg name="dbgbwcr0" protect="rw">
        <bits access="rw" name="watchpoint_address_mask" pos="28:24" rst="0">
          <comment>This field watches a range of addresses by masking lower order address bits out of the watchpoint
comparison:
b00000 = no mask
b00001 = reserved
b00010 = reserved
b00011 = 0x00000007 mask for data address
b00100 = 0x0000000F mask for data address
b00101 = 0x0000001F mask for data address
.
.
.
b11111 = 0x7FFFFFFF mask for data address.
Note
? If bits [28:24] are not set to b00000, bits [12:5] must be set to b11111111. Otherwise the behavior is
Unpredictable.
? If [28:24] are not set to b00000, the corresponding DBGWVR bits that are not being included in the
comparison SBZ. Otherwise the behavior is Unpredictable.
To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a
debugger sets bits [28:24] to b00111, and bits [12:5] to b11111111. This is compatible with both ARMv7
debug compliant implementations that have an 8-bit byte address select field (bits [12:5]) and with those
that have a 4-bit byte address select field (bits [8:5]).</comment>
        </bits>
        <bits access="rw" name="e" pos="20" rst="0">
          <comment>Enable linking bit:
0 = linking disabled
1 = linking enabled.
When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP
field.</comment>
        </bits>
        <bits access="rw" name="linked_brp" pos="19:16" rst="0">
          <comment>Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP
with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is
Unpredictable whether a watchpoint debug event is generated.</comment>
        </bits>
        <bits access="rw" name="secure_state_access_control" pos="15:14" rst="0">
          <comment>Secure state access control. This field enables the watchpoint to be conditioned on the security state of the
processor.
b00 = watchpoint matches in both Secure and Non-secure state
b01 = watchpoint only matches in Non-secure state
b10 = watchpoint only matches in Secure state
b11 = reserved</comment>
        </bits>
        <bits access="rw" name="byte_address_select" pos="8:5" rst="0">
          <comment>Byte address select. The DBGWVR is programmed with word-aligned address. You can use this field to
program the watchpoint so it only hits if certain byte addresses are accessed.</comment>
        </bits>
        <bits access="rw" name="load_store" pos="4:3" rst="0">
          <comment>Load/store access. The watchpoint can be conditioned to the type of access being done.
b00 = reserved
b01 = load, load exclusive, or swap
b10 = store, store exclusive or swap
b11 = either.
SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggers a watchpoint
on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local
monitor within the processor.</comment>
        </bits>
        <bits access="rw" name="s" pos="2:1" rst="0">
          <comment>Privileged access controlb. The watchpoint can be conditioned to the privilege of the access being done:
b00 = reserved
b01 = privileged, match if the processor does a privileged access to memory
b10 = User, match only on nonprivileged accesses
b11 = either, match all accesses</comment>
        </bits>
        <bits access="rw" name="w" pos="0" rst="0">
          <comment>Watchpoint enable:
0 = watchpoint disabled, reset value
1 = watchpoint enabled.</comment>
        </bits>
      </reg>
      <reg name="dbgbwcr1" protect="rw">
        <bits access="rw" name="watchpoint_address_mask" pos="28:24" rst="0">
          <comment>This field watches a range of addresses by masking lower order address bits out of the watchpoint
comparison:
b00000 = no mask
b00001 = reserved
b00010 = reserved
b00011 = 0x00000007 mask for data address
b00100 = 0x0000000F mask for data address
b00101 = 0x0000001F mask for data address
.
.
.
b11111 = 0x7FFFFFFF mask for data address.
Note
? If bits [28:24] are not set to b00000, bits [12:5] must be set to b11111111. Otherwise the behavior is
Unpredictable.
? If [28:24] are not set to b00000, the corresponding DBGWVR bits that are not being included in the
comparison SBZ. Otherwise the behavior is Unpredictable.
To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a
debugger sets bits [28:24] to b00111, and bits [12:5] to b11111111. This is compatible with both ARMv7
debug compliant implementations that have an 8-bit byte address select field (bits [12:5]) and with those
that have a 4-bit byte address select field (bits [8:5]).</comment>
        </bits>
        <bits access="rw" name="e" pos="20" rst="0">
          <comment>Enable linking bit:
0 = linking disabled
1 = linking enabled.
When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP
field.</comment>
        </bits>
        <bits access="rw" name="linked_brp" pos="19:16" rst="0">
          <comment>Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP
with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is
Unpredictable whether a watchpoint debug event is generated.</comment>
        </bits>
        <bits access="rw" name="secure_state_access_control" pos="15:14" rst="0">
          <comment>Secure state access control. This field enables the watchpoint to be conditioned on the security state of the
processor.
b00 = watchpoint matches in both Secure and Non-secure state
b01 = watchpoint only matches in Non-secure state
b10 = watchpoint only matches in Secure state
b11 = reserved</comment>
        </bits>
        <bits access="rw" name="byte_address_select" pos="8:5" rst="0">
          <comment>Byte address select. The DBGWVR is programmed with word-aligned address. You can use this field to
program the watchpoint so it only hits if certain byte addresses are accessed.</comment>
        </bits>
        <bits access="rw" name="load_store" pos="4:3" rst="0">
          <comment>Load/store access. The watchpoint can be conditioned to the type of access being done.
b00 = reserved
b01 = load, load exclusive, or swap
b10 = store, store exclusive or swap
b11 = either.
SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggers a watchpoint
on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local
monitor within the processor.</comment>
        </bits>
        <bits access="rw" name="s" pos="2:1" rst="0">
          <comment>Privileged access controlb. The watchpoint can be conditioned to the privilege of the access being done:
b00 = reserved
b01 = privileged, match if the processor does a privileged access to memory
b10 = User, match only on nonprivileged accesses
b11 = either, match all accesses</comment>
        </bits>
        <bits access="rw" name="w" pos="0" rst="0">
          <comment>Watchpoint enable:
0 = watchpoint disabled, reset value
1 = watchpoint enabled.</comment>
        </bits>
      </reg>
      <reg name="dbgbwcr2" protect="rw">
        <bits access="rw" name="watchpoint_address_mask" pos="28:24" rst="0">
          <comment>This field watches a range of addresses by masking lower order address bits out of the watchpoint
comparison:
b00000 = no mask
b00001 = reserved
b00010 = reserved
b00011 = 0x00000007 mask for data address
b00100 = 0x0000000F mask for data address
b00101 = 0x0000001F mask for data address
.
.
.
b11111 = 0x7FFFFFFF mask for data address.
Note
? If bits [28:24] are not set to b00000, bits [12:5] must be set to b11111111. Otherwise the behavior is
Unpredictable.
? If [28:24] are not set to b00000, the corresponding DBGWVR bits that are not being included in the
comparison SBZ. Otherwise the behavior is Unpredictable.
To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a
debugger sets bits [28:24] to b00111, and bits [12:5] to b11111111. This is compatible with both ARMv7
debug compliant implementations that have an 8-bit byte address select field (bits [12:5]) and with those
that have a 4-bit byte address select field (bits [8:5]).</comment>
        </bits>
        <bits access="rw" name="e" pos="20" rst="0">
          <comment>Enable linking bit:
0 = linking disabled
1 = linking enabled.
When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP
field.</comment>
        </bits>
        <bits access="rw" name="linked_brp" pos="19:16" rst="0">
          <comment>Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP
with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is
Unpredictable whether a watchpoint debug event is generated.</comment>
        </bits>
        <bits access="rw" name="secure_state_access_control" pos="15:14" rst="0">
          <comment>Secure state access control. This field enables the watchpoint to be conditioned on the security state of the
processor.
b00 = watchpoint matches in both Secure and Non-secure state
b01 = watchpoint only matches in Non-secure state
b10 = watchpoint only matches in Secure state
b11 = reserved</comment>
        </bits>
        <bits access="rw" name="byte_address_select" pos="8:5" rst="0">
          <comment>Byte address select. The DBGWVR is programmed with word-aligned address. You can use this field to
program the watchpoint so it only hits if certain byte addresses are accessed.</comment>
        </bits>
        <bits access="rw" name="load_store" pos="4:3" rst="0">
          <comment>Load/store access. The watchpoint can be conditioned to the type of access being done.
b00 = reserved
b01 = load, load exclusive, or swap
b10 = store, store exclusive or swap
b11 = either.
SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggers a watchpoint
on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local
monitor within the processor.</comment>
        </bits>
        <bits access="rw" name="s" pos="2:1" rst="0">
          <comment>Privileged access controlb. The watchpoint can be conditioned to the privilege of the access being done:
b00 = reserved
b01 = privileged, match if the processor does a privileged access to memory
b10 = User, match only on nonprivileged accesses
b11 = either, match all accesses</comment>
        </bits>
        <bits access="rw" name="w" pos="0" rst="0">
          <comment>Watchpoint enable:
0 = watchpoint disabled, reset value
1 = watchpoint enabled.</comment>
        </bits>
      </reg>
      <hole size="2464"/>
      <reg name="dbgoslar" protect="w">
        <bits access="w" name="dbgoslar" pos="31:0" rst="0">
          <comment>Write 0xC5ACCE55 to this field to unlock the DBG.
Write any other value to this field to lock the DBG</comment>
        </bits>
      </reg>
      <reg name="dbgoslsr" protect="r">
        <bits access="r" name="oslm_0" pos="3" rst="0">
          <comment>OSLM[0]</comment>
        </bits>
        <bits access="r" name="oslm_1" pos="3" rst="0">
          <comment>OSLM[1]
OS Lock Model implemented field. This field identifies the form of OS Save and Restore
mechanism implemented.
The possible values are:
0b00 No OS Save and Restore mechanism implemented. OS Lock not implemented.
v7 Debug only.
0b01 OS Lock and DBGOSSRR implemented. v7 Debug only.
0b10 OS Lock implemented. DBGOSSRR not implemented. v7.1 Debug only.
0b11 Reserved.
Note
This field is split across two non-contiguous bits in the register.</comment>
        </bits>
        <bits access="r" name="ntt" pos="2" rst="0">
          <comment>Not 32-bit access. This bit is always RAZ. It indicates that a 32-bit access is needed to write the key
to the OS Lock Access Register.</comment>
        </bits>
        <bits access="r" name="oslk" pos="1" rst="0">
          <comment>OS Lock Status. The possible values are:
0 OS Lock not set.
1 OS Lock set.
If the OS Save and Restore mechanism is not implemented this bit is UNK.
The OS Lock is set or cleared by writing to the DBGOSLAR.</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="dbgprcr" protect="rw">
        <bits access="rw" name="hold_non_debug_logic_reset" pos="2" rst="0">
          <comment>Hold non-debug logic reset:
0 = Do not hold the non-debug logic reset on power-up or warm reset.
1 = Hold the non-debug logic of the processor in reset on power-up or warm reset.
The processor is held in this state until this flag is cleared to 0.</comment>
        </bits>
        <bits access="r" name="warm_reset_request" pos="1" rst="0">
          <comment>Warm reset request, RAZ</comment>
        </bits>
        <bits access="rw" name="dbgnopwrdwn" pos="0" rst="0">
          <comment>When set to 1, the DBGNOPWRDWN output signal is HIGH. This output is connected to the system
power controller and is interpreted as a request to operate in emulate mode. In this mode, the
Cortex-A5 processor and ETM are not actually powered down when requested by software or
hardware handshakes.
0 = DBGNOPWRDWN is LOW. This is the reset value.
1 = DBGNOPWRDWN is HIGH.</comment>
        </bits>
      </reg>
      <reg name="dbgprsr" protect="r">
        <bits access="r" name="sticky_reset_status" pos="3" rst="0">
          <comment>Sticky reset status</comment>
        </bits>
        <bits access="r" name="reset_status" pos="2" rst="0">
          <comment>Reset status</comment>
        </bits>
        <bits access="r" name="sticky_pwrdn_status" pos="1" rst="0">
          <comment>Sticky power-down status. RAZ</comment>
        </bits>
        <bits access="r" name="powerup_status" pos="0" rst="0">
          <comment>Power up status. RAO</comment>
        </bits>
      </reg>
      <hole size="24320"/>
      <reg name="dbgitmiscout" protect="rw">
        <bits access="w" name="dbgrestarted" pos="9" rst="0">
          <comment>Set value of the DBGRESTARTED output pin</comment>
        </bits>
        <bits access="w" name="pmuirq" pos="4" rst="0">
          <comment>Set value of PMUIRQ output pin.</comment>
        </bits>
        <bits access="w" name="dbgack" pos="0" rst="0">
          <comment>Set value of the DBGACK output pin.</comment>
        </bits>
      </reg>
      <reg name="dbgitmiscin" protect="r">
        <bits access="r" name="dbgrestart" pos="11" rst="0">
          <comment>Read value of the DBGRESTART input pin</comment>
        </bits>
        <bits access="r" name="nfiq" pos="2" rst="1">
          <comment>Read value of nFIQ input pin.</comment>
        </bits>
        <bits access="r" name="nirq" pos="1" rst="1">
          <comment>Read value of nIRQ input pin.</comment>
        </bits>
        <bits access="r" name="edbgrq" pos="0" rst="0">
          <comment>Read value of EDBGRQ input pin.</comment>
        </bits>
      </reg>
      <reg name="dbgitctrl" protect="rw">
        <bits access="rw" name="intmode" pos="0" rst="0">
          <comment>Controls whether the processor is in normal operating mode or integration mode:
b0 = normal operation
b1 = integration mode enabled.</comment>
        </bits>
      </reg>
      <hole size="1248"/>
      <reg name="dbgclaimset" protect="rw">
        <bits access="rw" name="claim_tags" pos="7:0" rst="255">
          <comment>Indicates the claim tags.
Writing 1 to a bit in this register sets that particular claim. You can read the claim status at the Claim Tag Clear
Register. For example, if you write 1 to bit [3] of this register, bit [3] of the Claim Tag Clear Register is read as 1.
Writing 0 to a specific claim tag bit has no effect. This register always reads 0xFF, indicating that up to eight
claims can be set.</comment>
        </bits>
      </reg>
      <reg name="dbgclaimclr" protect="rw">
        <bits access="rw" name="claim_tags" pos="7:0" rst="0">
          <comment>Indicates the claim tag status. Writing 1 to a specific claim tag clear bit clears that claim tag. Reading this
register returns the current claim tag value. For example, if you write 1 to bit [3] of this register, it is read as 0.
The reset value is 0.</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="dbglar" protect="w">
        <bits access="w" name="lock_access_control" pos="31:0" rst="0">
          <comment>Lock access control. To unlock the debug registers, write a 0xC5ACCE55 key to this register. To lock the debug
registers, write any other value. Accesses to locked debug registers are ignored. The reset value is 0</comment>
        </bits>
      </reg>
      <reg name="dbglsr" protect="r">
        <bits access="r" name="lar_32_bits" pos="2" rst="0">
          <comment>Read as zero. It indicates that a 32-bit access is required to write the key to the Lock Access Register</comment>
        </bits>
        <bits access="r" name="etm_locked" pos="1" rst="0">
          <comment>This bit indicates the status of the debug registers lock.
0 = Lock clear. Debug register writes are permitted.
1 = Lock set. Debug register writes are ignored.
The Debug reset value of this bit is 1.</comment>
        </bits>
        <bits access="r" name="lock_reg_impl" pos="0" rst="1">
          <comment>Read-as-One</comment>
        </bits>
      </reg>
      <reg name="dbgauthstatus" protect="r">
        <bits access="r" name="snid_1" pos="7" rst="1">
          <comment>Secure noninvasive debug enable field</comment>
        </bits>
        <bits access="r" name="snid_2" pos="6" rst="1">
          <comment>DBGEN || NIDEN) &amp;&amp; (SPIDEN || SPNIDEN</comment>
        </bits>
        <bits access="r" name="sid_1" pos="5" rst="1">
          <comment>Secure invasive debug enable field</comment>
        </bits>
        <bits access="r" name="sid_2" pos="4" rst="1">
          <comment>DBGEN &amp;&amp; SPIDEN</comment>
        </bits>
        <bits access="r" name="nsnid_1" pos="3" rst="1">
          <comment>Non-secure noninvasive debug field</comment>
        </bits>
        <bits access="r" name="nsnid_2" pos="2" rst="1">
          <comment>DBGEN || NIDEN</comment>
        </bits>
        <bits access="r" name="nsid_1" pos="1" rst="1">
          <comment>Non-secure invasive debug enable</comment>
        </bits>
        <bits access="r" name="nsid_2" pos="0" rst="1">
          <comment>DBGEN</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="dbgdevid" protect="r">
      </reg>
      <reg name="dbgdevtype" protect="r">
        <bits access="r" name="sub_type" pos="7:4" rst="1">
          <comment>Indicates that the sub-type of the Cortex-A5 processor is core. This value is 0x1.</comment>
        </bits>
        <bits access="r" name="main_class" pos="3:0" rst="5">
          <comment>Indicates that the main class of the Cortex-A5 processor is debug logic. This value is 0x5.</comment>
        </bits>
      </reg>
      <reg name="dbgpidr4" protect="r">
        <bits access="r" name="n" pos="7:4" rst="0">
          <comment>Indicates the number of blocks occupied by the Cortex-A5 processor. This field is always set to 0.</comment>
        </bits>
        <bits access="r" name="jep106_con_code" pos="3:0" rst="4">
          <comment>Indicates the JEDEC JEP106 Continuation Code. For the Cortex-A5 processor, this value is 0x4.</comment>
        </bits>
      </reg>
      <reg name="dbgpidr5" protect="r">
      </reg>
      <reg name="dbgpidr6" protect="r">
      </reg>
      <reg name="dbgpidr7" protect="r">
      </reg>
      <reg name="dbgpidr0" protect="r">
        <bits access="r" name="part_number" pos="7:0" rst="5">
          <comment>Indicates bits [7:0] of the part number for the Cortex-A5 processor. This value is 0x05.</comment>
        </bits>
      </reg>
      <reg name="dbgpidr1" protect="r">
        <bits access="r" name="jep106_id_3_0" pos="7:4" rst="11">
          <comment>Indicates bits of the JEDEC JEP106 Identity Code. This value is 0xB.</comment>
        </bits>
        <bits access="r" name="part_number_11_8" pos="3:0" rst="12">
          <comment>Indicates bits [11:8] of the part number for the Cortex-A5 processor. This value is 0xC</comment>
        </bits>
      </reg>
      <reg name="dbgpidr2" protect="r">
        <bits access="r" name="rev_number" pos="7:4" rst="1">
          <comment>Indicates the revision number for the Cortex-A5 processor. This value changes based on the
product major and minor revision. This value is set to 1 indicating revision r0p1.</comment>
        </bits>
        <bits access="r" name="jedec_val_in_use" pos="3" rst="1">
          <comment>Always 1. Indicates that a JEDEC assigned value is used.</comment>
        </bits>
        <bits access="r" name="jep106_id_6_4" pos="2:0" rst="3">
          <comment>Indicates bits [6:4] of the JEDEC JEP106 Identity Code. This value is set to 0x3.</comment>
        </bits>
      </reg>
      <reg name="dbgpidr3" protect="r">
        <bits access="r" name="revand" pos="7:4" rst="0">
          <comment>Indicates the manufacturer revision number. This value changes based on the manufacturer
metal fixes. This value is set to 0.</comment>
        </bits>
        <bits access="r" name="customized_val" pos="3:0" rst="0">
          <comment>For the Cortex-A5 processor, this value is set to 0.</comment>
        </bits>
      </reg>
      <reg name="dbgcidr0" protect="r">
        <bits access="r" name="cid_7_0" pos="7:0" rst="13">
          <comment>Component identifier, bits [7:0].</comment>
        </bits>
      </reg>
      <reg name="dbgcidr1" protect="r">
        <bits access="r" name="component_class" pos="7:4" rst="9">
          <comment>Component class (component identifier, bits [15:12]).</comment>
        </bits>
        <bits access="r" name="cid_11_8" pos="3:0" rst="0">
          <comment>Component identifier, bits [11:8].</comment>
        </bits>
      </reg>
      <reg name="dbgcidr2" protect="r">
        <bits access="r" name="cid_23_16" pos="7:0" rst="5">
          <comment>Component identifier, bits [23:16].</comment>
        </bits>
      </reg>
      <reg name="dbgcidr3" protect="r">
        <bits access="r" name="cid_31_24" pos="7:0" rst="177">
          <comment>Component identifier, bits [31:24].</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="pmu_a5.xml">
    <module category="Debug" name="PMU_A5">
      <reg name="pmxevcntr0" protect="rw">
        <bits access="rw" name="event_counter0" pos="31:0" rst="0">
          <comment>PMU Event counter 0</comment>
        </bits>
      </reg>
      <reg name="pmxevcntr1" protect="rw">
        <bits access="rw" name="event_counter1" pos="31:0" rst="0">
          <comment>PMU Event counter 1</comment>
        </bits>
      </reg>
      <hole size="928"/>
      <reg name="pmccntr" protect="rw">
        <bits access="rw" name="pmccntr" pos="31:0" rst="0">
          <comment>Counts processor clock cycles</comment>
        </bits>
      </reg>
      <hole size="7168"/>
      <reg name="pmxevtyper0" protect="rw">
        <bits access="rw" name="sel" pos="7:0" rst="0">
          <comment>Specifies the event selected as described in the ARM Architecture Reference Manual.
Event EVNTBUS
bit position Description
0x00 - Software increment. The register is incremented only on writes to the Software Increment Register. See
Software Increment Register on page 10-7.
0x01 [0] Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache. Includes the
speculative linefills in the count.
0x02 [1] Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB. Includes the speculative
requests in the count.
0x03 [2] Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache. Counts
the number of allocations performed in the Data Cache because of a read or a write
0x04 [3] Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache.
This includes speculative reads.
0x05 [4] Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB. This does not
include micro TLB misses because of PLD, PLI, CP15 Cache operation by MVA and CP15 VA to PA
operations.
0x06 [5] Data read architecturally executed. Counts the number of data read instructions accepted by the Load Store
Unit. This includes counting the speculative and aborted LDR/LDM, and the reads because of the SWP
instructions.
0x07 [6] Data write architecturally executed. Counts the number of data write instructions accepted by the Load
Store Unit. This includes counting the speculative and aborted STR/STM, and the writes because of the SWP
instructions.
0x08 [7] Instruction architecturally executed.
0x09 [8] Exception taken. Counts the number of exceptions architecturally taken.
0x0A [9] Exception return architecturally executed. The following instructions are reported on this event:
0x0B [10] Change to ContextID retired. Counts the number of instructions architecturally executed writing into the
ContextID Register.
0x0C [11] Software change of PC.
0x0D [12] Immediate branch architecturally executed (taken or not taken). This includes the branches which are
flushed due to a previous load/store which aborts late.
0x0E [13] Procedure return (other than exception returns) architecturally executed.
0x0F [14] Unaligned load-store.
0x10 [15] Branch mispredicted/not predicted. Counts the number of mispredicted or not-predicted branches executed.
This includes the branches which are flushed because of a previous load/store which aborts late.
0x11 - Cycle counter.
0x12 [16] Branches or other change in program flow that could have been predicted by the branch prediction resources
of the processor. This includes the branches which are flushed because of a previous load/store which aborts
late.
0x13 [17] Data memory access.
0x14 [18] Instruction Cache access.
0x15 [19] Data cache eviction.
0x86 [20] IRQ exception taken.
0x87 [21] FIQ exception taken.
0xC0 [22] External memory request.
0xC1 [23] Non-cacheable external memory request.
0xC2 [24] Linefill because of prefetch.
0xC3 [25] Prefetch linefill dropped.
0xC4 [26] Entering read allocate mode.
0xC5 [27] Read allocate mode.
0xC6 [28] Reserved.
0xC7 - ETM Ext Out[0].
0xC8 - ETM Ext Out[1].
0xC9 [29] Data Write operation that stalls the pipeline because the store buffer is full.</comment>
        </bits>
      </reg>
      <hole size="10144"/>
      <reg name="pmccfiltr" protect="rw">
        <bits access="rw" name="p" pos="31" rst="0">
      </bits>
        <bits access="rw" name="u" pos="30" rst="0">
      </bits>
        <bits access="rw" name="nsk" pos="29" rst="0">
      </bits>
        <bits access="rw" name="nsu" pos="28" rst="0">
      </bits>
      </reg>
      <hole size="6176"/>
      <reg name="pmcntenset" protect="rw">
        <bits access="rw" name="c" pos="31" rst="0">
          <comment>Cycle counter enable set:
0 = disable
1 = enable.</comment>
        </bits>
        <bits access="rw" name="p1" pos="1" rst="0">
          <comment>Counter 1 enable</comment>
        </bits>
        <bits access="rw" name="p0" pos="0" rst="0">
          <comment>Counter 0 enable</comment>
        </bits>
      </reg>
      <hole size="224"/>
      <reg name="pmcntenclr" protect="rw">
        <bits access="rw" name="c" pos="31" rst="0">
          <comment>Cycle counter enable clear:
0 = disable
1 = enable.</comment>
        </bits>
        <bits access="rw" name="p1" pos="1" rst="0">
          <comment>Counter 1 enable</comment>
        </bits>
        <bits access="rw" name="p0" pos="0" rst="0">
          <comment>Counter 0 enable</comment>
        </bits>
      </reg>
      <hole size="224"/>
      <reg name="pmintenset" protect="rw">
        <bits access="rw" name="c" pos="31" rst="9">
          <comment>PMCCNTR overflow interrupt request enable.
When reading this register:
0 = interrupt request disabled
1 = interrupt request enabled.
When writing to this register:
0 = no action
1 = interrupt request enabled.</comment>
        </bits>
        <bits access="rw" name="p1" pos="1" rst="0">
          <comment>PMC1 overflow interrupt request enable</comment>
        </bits>
        <bits access="rw" name="p0" pos="0" rst="0">
          <comment>PMC0 overflow interrupt request enable.</comment>
        </bits>
      </reg>
      <hole size="224"/>
      <reg name="pmintenclr" protect="rw">
        <bits access="rw" name="c" pos="31" rst="9">
          <comment>PMCCNTR overflow interrupt clear bit.
When reading this register:
0 = interrupt request disabled
1 = interrupt request enabled.
When writing to this register:
0 = no action
1 = interrupt request cleared.</comment>
        </bits>
        <bits access="rw" name="p1" pos="1" rst="0">
          <comment>Clear interrupt request on PMC1 overflow.</comment>
        </bits>
        <bits access="rw" name="p0" pos="0" rst="0">
          <comment>Clear interrupt request on PMC0 overflow</comment>
        </bits>
      </reg>
      <hole size="224"/>
      <reg name="pmovsr" protect="rw">
        <bits access="rw" name="c" pos="31" rst="0">
          <comment>Cycle counter overflow flag:
0 = disable
1 = enable.</comment>
        </bits>
        <bits access="rw" name="p1" pos="1" rst="0">
          <comment>Counter 1 overflow flag</comment>
        </bits>
        <bits access="rw" name="p0" pos="0" rst="0">
          <comment>Counter 0 overflow flag</comment>
        </bits>
      </reg>
      <hole size="224"/>
      <reg name="pmswinc" protect="rw">
        <bits access="w" name="p1" pos="1" rst="0">
          <comment>Increment Counter 1. When writing this register, a value of 1 increments the counter, and value of 0 does nothing.</comment>
        </bits>
        <bits access="w" name="p0" pos="0" rst="0">
          <comment>Increment Counter 1. When writing this register, a value of 1 increments the counter, and value of 0 does nothing.</comment>
        </bits>
      </reg>
      <hole size="2784"/>
      <reg name="pmcfgr" protect="r">
        <bits access="r" name="uen" pos="19" rst="1">
          <comment>User mode enable supported (using PMUSERENR)</comment>
        </bits>
        <bits access="r" name="ex" pos="16" rst="1">
          <comment>Event export supported</comment>
        </bits>
        <bits access="r" name="ccd" pos="15" rst="1">
          <comment>Cycle counter pre-scale supported</comment>
        </bits>
        <bits access="r" name="cc" pos="14" rst="1">
          <comment>Cycle counter implemented</comment>
        </bits>
        <bits access="r" name="size" pos="12:11" rst="3">
          <comment>32-bit counters implemented</comment>
        </bits>
        <bits access="r" name="n" pos="4:0" rst="2">
          <comment>2 event counters implemented</comment>
        </bits>
      </reg>
      <reg name="pmcr" protect="rw">
        <bits access="r" name="imp" pos="31:24" rst="65">
          <comment>Specifies the implementor code:
0x41 = ARM.
This field is read-only and write ignored.</comment>
        </bits>
        <bits access="r" name="idcode" pos="23:16" rst="5">
          <comment>Specifies the identification code:
0x5
This field is read-only and write ignored.</comment>
        </bits>
        <bits access="r" name="n" pos="15:11" rst="2">
          <comment>Specifies the number of counters implemented:
0x2 = two counters implemented.
This field is read-only and write ignored.</comment>
        </bits>
        <bits access="rw" name="dp" pos="5" rst="0">
          <comment>Disables cycle counter, PMCCNTR, when prohibited:
0 = count is enabled in prohibited regions. This is the reset value.
1 = count is disabled in prohibited regions.</comment>
        </bits>
        <bits access="rw" name="x" pos="4" rst="0">
          <comment>Enables export of the events from the event bus to an external monitoring block, such as an ETM:
0 = export disabled. This is the reset value.
1 = export enabled.</comment>
        </bits>
        <bits access="rw" name="d" pos="3" rst="0">
          <comment>Cycle count divider:
0 = count every clock cycle when enabled. This is the reset value.
1 = count every 64th clock cycle when enabled.</comment>
        </bits>
        <bits access="rw" name="c" pos="2" rst="0">
          <comment>Cycle counter reset, write only bit, RAZ:
0 = no action
1 = reset cycle counter, PMCCNTR, to zero.</comment>
        </bits>
        <bits access="rw" name="p" pos="1" rst="0">
          <comment>Performance counter reset, write only bit, RAZ:
0 = no action
1 = reset all performance counters to zero, not including PMCCNTR.</comment>
        </bits>
        <bits access="rw" name="e" pos="0" rst="0">
          <comment>Enable bit:
0 = disable all counters, including PMCCNTR. This is the reset value.
1 = enable all counters including PMCCNTR.</comment>
        </bits>
      </reg>
      <reg name="pmuserenr" protect="rw">
        <bits access="rw" name="en" pos="0" rst="0">
          <comment>User mode enable. 0 is the reset value</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="pmceid0" protect="r">
        <bits access="r" name="bus_cycle" pos="29" rst="0">
          <comment>Bus cycle</comment>
        </bits>
        <bits access="r" name="wr_to_tlb" pos="28" rst="0">
          <comment>Write to translation table base</comment>
        </bits>
        <bits access="r" name="instr_specultate_exec" pos="27" rst="0">
          <comment>Instruction speculatively executed</comment>
        </bits>
        <bits access="r" name="local_mem_err" pos="26" rst="0">
          <comment>Local memory error</comment>
        </bits>
        <bits access="r" name="bus_access" pos="25" rst="0">
          <comment>Bus access</comment>
        </bits>
        <bits access="r" name="l2_dc_write_back" pos="24" rst="0">
          <comment>Level 2 data cache write-back</comment>
        </bits>
        <bits access="r" name="l2_dc_refill" pos="23" rst="0">
          <comment>Level 2 data cache refill</comment>
        </bits>
        <bits access="r" name="l2_dc_access" pos="22" rst="0">
          <comment>Level 2 data cache access</comment>
        </bits>
        <bits access="r" name="l1_dc_write_back" pos="21" rst="0">
          <comment>Level 1 data cache write-back</comment>
        </bits>
        <bits access="r" name="l1_ic_access" pos="20" rst="0">
          <comment>Level 1 instruction cache access</comment>
        </bits>
        <bits access="r" name="data_mem_access" pos="19" rst="0">
          <comment>Data memory access</comment>
        </bits>
        <bits access="r" name="predict_branch_speculate_exec" pos="18" rst="0">
          <comment>Predictable branch speculatively executed</comment>
        </bits>
        <bits access="r" name="cycle" pos="17" rst="0">
          <comment>Cycle</comment>
        </bits>
        <bits access="r" name="mispredict_branch" pos="16" rst="0">
          <comment>Mispredicted or not predicted branch speculatively executed</comment>
        </bits>
        <bits access="r" name="unaligned_ld_strore" pos="15" rst="0">
          <comment>Unaligned load or store</comment>
        </bits>
        <bits access="r" name="proc_ret" pos="14" rst="0">
          <comment>Procedure return</comment>
        </bits>
        <bits access="r" name="imm_branch" pos="13" rst="0">
          <comment>Immediate branch</comment>
        </bits>
        <bits access="r" name="sw_change_pc" pos="12" rst="0">
          <comment>Software change of the PC</comment>
        </bits>
        <bits access="r" name="wr_to_context" pos="11" rst="0">
          <comment>Write to CONTEXTIDR</comment>
        </bits>
        <bits access="r" name="excep_ret" pos="10" rst="0">
          <comment>Exception return</comment>
        </bits>
        <bits access="r" name="excep_taken" pos="9" rst="0">
          <comment>Exception taken</comment>
        </bits>
        <bits access="r" name="instr_arch_exec" pos="8" rst="0">
          <comment>Instruction architecturally executed</comment>
        </bits>
        <bits access="r" name="store" pos="7" rst="0">
          <comment>Store</comment>
        </bits>
        <bits access="r" name="load" pos="6" rst="0">
          <comment>Load</comment>
        </bits>
        <bits access="r" name="l1_data_tlb_refill" pos="5" rst="0">
          <comment>Level 1 data TLB refill</comment>
        </bits>
        <bits access="r" name="l1_dc_access" pos="4" rst="0">
          <comment>Level 1 data cache access</comment>
        </bits>
        <bits access="r" name="l1_dc_refill" pos="3" rst="0">
          <comment>Level 1 data cache refill</comment>
        </bits>
        <bits access="r" name="l1_instr_tlb_refill" pos="2" rst="0">
          <comment>Level 1 instruction TLB refill</comment>
        </bits>
        <bits access="r" name="l1_ic_refill" pos="1" rst="0">
          <comment>Level 1 instruction cache refill</comment>
        </bits>
        <bits access="r" name="sw_inc" pos="0" rst="0">
          <comment>Software increment</comment>
        </bits>
      </reg>
      <hole size="3168"/>
      <reg name="pmlar" protect="w">
        <bits access="w" name="lock_access_control" pos="31:0" rst="0">
          <comment>Lock access control. To unlock the performance monitor registers, write a 0xC5ACCE55 key to this register. To
lock the performance monitor registers, write any other value. Accesses to locked performance monitor
registers are ignored. The reset value is 0.</comment>
        </bits>
      </reg>
      <reg name="pmlsr" protect="r">
        <bits access="r" name="lar_32_bits" pos="2" rst="0">
          <comment>Read as zero. It indicates that a 32-bit access is required to write the key to the Lock Access Register</comment>
        </bits>
        <bits access="r" name="etm_locked" pos="1" rst="0">
          <comment>This bit indicates the status of the debug registers lock.
0 = Lock clear. Debug register writes are permitted.
1 = Lock set. Debug register writes are ignored.
The Debug reset value of this bit is 1.</comment>
        </bits>
        <bits access="r" name="lock_reg_impl" pos="0" rst="1">
          <comment>Read-as-One</comment>
        </bits>
      </reg>
      <reg name="pmauthstatus" protect="r">
        <bits access="r" name="snid_1" pos="7" rst="1">
          <comment>Secure noninvasive debug enable field</comment>
        </bits>
        <bits access="r" name="snid_2" pos="6" rst="1">
          <comment>DBGEN || NIDEN) &amp;&amp; (SPIDEN || SPNIDEN</comment>
        </bits>
        <bits access="r" name="sid_1" pos="5" rst="1">
          <comment>Secure invasive debug enable field</comment>
        </bits>
        <bits access="r" name="sid_2" pos="4" rst="1">
          <comment>DBGEN &amp;&amp; SPIDEN</comment>
        </bits>
        <bits access="r" name="nsnid_1" pos="3" rst="1">
          <comment>Non-secure noninvasive debug field</comment>
        </bits>
        <bits access="r" name="nsnid_2" pos="2" rst="1">
          <comment>DBGEN || NIDEN</comment>
        </bits>
        <bits access="r" name="nsid" pos="1:0" rst="0">
          <comment>Non-secure invasive debug enable</comment>
        </bits>
      </reg>
      <hole size="128"/>
      <reg name="pmdevtype" protect="r">
        <bits access="r" name="sub_type" pos="7:4" rst="1">
          <comment>Indicates that the sub-type of the Cortex-A5 processor is core. This value is 0x1.</comment>
        </bits>
        <bits access="r" name="main_class" pos="3:0" rst="6">
          <comment>Indicates that the main class of the Cortex-A5 processor is performance monitor. This value is 0x6.</comment>
        </bits>
      </reg>
      <reg name="pmpidr4" protect="r">
        <bits access="r" name="n" pos="7:4" rst="0">
          <comment>Indicates the number of blocks occupied by the Cortex-A5 processor. This field is always set to 0.</comment>
        </bits>
        <bits access="r" name="jep106_con_code" pos="3:0" rst="4">
          <comment>Indicates the JEDEC JEP106 Continuation Code. For the Cortex-A5 processor, this value is 0x4.</comment>
        </bits>
      </reg>
      <reg name="pmpidr5" protect="r">
      </reg>
      <reg name="pmpidr6" protect="r">
      </reg>
      <reg name="pmpidr7" protect="r">
      </reg>
      <reg name="pmpidr0" protect="r">
        <bits access="r" name="part_number" pos="7:0" rst="165">
          <comment>Indicates bits [7:0] of the part number for the Cortex-A5 processor. This value is 0xA5.</comment>
        </bits>
      </reg>
      <reg name="pmpidr1" protect="r">
        <bits access="r" name="jep106_id_3_0" pos="7:4" rst="11">
          <comment>Indicates bits of the JEDEC JEP106 Identity Code. This value is 0xB.</comment>
        </bits>
        <bits access="r" name="part_number_11_8" pos="3:0" rst="9">
          <comment>Indicates bits [11:8] of the part number for the Cortex-A5 processor. This value is 0x9.</comment>
        </bits>
      </reg>
      <reg name="pmpidr2" protect="r">
        <bits access="r" name="rev_number" pos="7:4" rst="1">
          <comment>Indicates the revision number for the Cortex-A5 processor. This value changes based on the
product major and minor revision. This value is set to 1 indicating revision r0p1.</comment>
        </bits>
        <bits access="r" name="jedec_val_in_use" pos="3" rst="1">
          <comment>Always 1. Indicates that a JEDEC assigned value is used.</comment>
        </bits>
        <bits access="r" name="jep106_id_6_4" pos="2:0" rst="3">
          <comment>Indicates bits [6:4] of the JEDEC JEP106 Identity Code. This value is set to 0x3.</comment>
        </bits>
      </reg>
      <reg name="pmpidr3" protect="r">
        <bits access="r" name="revand" pos="7:4" rst="0">
          <comment>Indicates the manufacturer revision number. This value changes based on the manufacturer
metal fixes. This value is set to 0.</comment>
        </bits>
        <bits access="r" name="customized_val" pos="3:0" rst="0">
          <comment>For the Cortex-A5 processor, this value is set to 0.</comment>
        </bits>
      </reg>
      <reg name="pmcidr0" protect="r">
        <bits access="r" name="cid_7_0" pos="7:0" rst="13">
          <comment>Component identifier, bits [7:0].</comment>
        </bits>
      </reg>
      <reg name="pmcidr1" protect="r">
        <bits access="r" name="component_class" pos="7:4" rst="9">
          <comment>Component class (component identifier, bits [15:12]).</comment>
        </bits>
        <bits access="r" name="cid_11_8" pos="3:0" rst="0">
          <comment>Component identifier, bits [11:8].</comment>
        </bits>
      </reg>
      <reg name="pmcidr2" protect="r">
        <bits access="r" name="cid_23_16" pos="7:0" rst="5">
          <comment>Component identifier, bits [23:16].</comment>
        </bits>
      </reg>
      <reg name="pmcidr3" protect="r">
        <bits access="r" name="cid_31_24" pos="7:0" rst="177">
          <comment>Component identifier, bits [31:24].</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="etm_a5.xml">
    <module category="Debug" name="ETM_A5">
      <reg name="etmcr" protect="rw">
        <bits access="rw" name="enable_timestamping" pos="28" rst="0">
          <comment>Set to 1 to enable timestamping.
On an ETM reset this bit is 0.</comment>
        </bits>
        <bits access="rw" name="core_select" pos="27:25" rst="0">
          <comment>If an ETM is shared between multiple cores, selects which core to trace. For the maximum value permitted, see bits [14:12] of the System Configuration Register. See the Embedded Trace Macrocell Architecture Specification for more information.
To guarantee that the ETM is correctly synchronized to the new core, you must update these bits as follows:
1:Set bit [10], ETM programming, and bit [0], ETM power down, to 1.
2:Change the core select bits.
3:Clear bit [0], ETM power down, to 0.
4:Perform other programming required as normal. On an ETM reset this field is zero.</comment>
        </bits>
        <bits access="r" name="instr_res_access_ctrl" pos="24" rst="0">
          <comment>Instrumentation resources access control, ETM-A5 does not implement any instrumentation resources and therefore this bit is RAZ.</comment>
        </bits>
        <bits access="r" name="dis_sw_wr" pos="23" rst="0">
          <comment>Disable software writes. ETM-A5 does not support this feature and therefore this bit is RAZ.</comment>
        </bits>
        <bits access="r" name="dis_reg_wr_from_debugger" pos="22" rst="0">
          <comment>Disable register writes from the debugger. ETM-A5 does not support this feature and therefore this bit is RAZ.</comment>
        </bits>
        <bits access="rw" name="port_size_3" pos="21" rst="0">
          <comment>Port size[3].Use this bit in conjunction with bits [6:4].On an ETM reset this bit is 0, corresponding to the 32-bit port size.</comment>
        </bits>
        <bits access="rw" name="data_only_mode" pos="20" rst="0">
          <comment>0:Instruction trace enabled.
1:Instruction trace disabled. Data-only tracing is possible in this mode. On an ETM reset this bit is 0.</comment>
        </bits>
        <bits access="rw" name="filter_cprt" pos="19" rst="0">
          <comment>Use this bit in conjunction with bit [1], the MonitorCPRT bit. For details see Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later in the Embedded Trace Macrocell Architecture Specification.</comment>
        </bits>
        <bits access="rw" name="suppressdata" pos="18" rst="0">
          <comment>Use this bit with bit [7] to suppress data. For details see Data suppression in the Embedded Trace Macrocell Architecture Specification.On an ETM reset this bit is 0.</comment>
        </bits>
        <bits access="rw" name="port_mode_1_0" pos="17:16" rst="0">
          <comment>These bits are used, in conjunction with bit [13], to set the trace port clocking mode. ETM-A5 supports only dynamic mode, corresponding to the value b000, but you can write other values to these bits, and a read of the register returns the value written. Writing another value to these bits has no effect on the ETM. Bit [11] of the System Configuration Register indicates if these bits are set to select a supported clocking mode.On an ETM reset these bits are zero.</comment>
        </bits>
        <bits access="rw" name="contextidsize" pos="15:14" rst="0">
          <comment>b00                   No Context ID tracing.
b01                   Context ID bits [7:0] traced.
b10                   Context ID bits [15:0]
b11                   Context ID bits [31:0] traced.
Note Only the number of bytes specified is traced even if the new value is larger than this.On an ETM reset this field is zero.</comment>
        </bits>
        <bits access="rw" name="port_mode_2" pos="13" rst="0">
          <comment>See the description of bits [17:16].On an ETM reset this bit is 0.</comment>
        </bits>
        <bits access="rw" name="cycle-accuratetracing" pos="12" rst="0">
          <comment>Set this bit to 1 if you want the trace to include a precise cycle count of executed instructions. This is achieved by adding extra information into the trace, giving cycle counts even when TraceEnable is inactive.On an ETM reset this bit is 0.</comment>
        </bits>
        <bits access="rw" name="etm_port_sel" pos="11" rst="0">
          <comment>This bit controls an external output, ETMEN. The possible values are:
0                       ETMEN is LOW.
1                       ETMEN is HIGH.
You can use the ETMEN signal to control the routing of trace port signals to shared GPIO pins on your SoC, under the control of logic external to the ETM.Trace software tools must set this bit to 1 to ensure that trace output is enabled from this ETM.</comment>
        </bits>
        <bits access="rw" name="etm_programming" pos="10" rst="1">
          <comment>When set to 1, the ETM is being programmed. For more information, see ETM Programming bit and associated state in the Embedded Trace Macrocell Architecture Specification.</comment>
        </bits>
        <bits access="rw" name="debugrequestcontrol" pos="9" rst="0">
          <comment>If you set this bit to 1, when the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables the Cortex-A5 processor to be forced into Debug state. On an ETM reset this bit is 0.</comment>
        </bits>
        <bits access="rw" name="branchoutput" pos="8" rst="0">
          <comment>Set this bit to 1 if you want the ETM to output all branch addresses, even if the branch isbecause of a direct branch instruction. Setting this bit to 1 enables reconstruction of the program flow without having access to the memory image of the code being executed.On an ETM reset this bit is 0.</comment>
        </bits>
        <bits access="r" name="stallprocessor" pos="7" rst="0">
          <comment>ETM-A5 does not implement FIFOFULL stalling of the processor, and therefore this bit is RAZ.</comment>
        </bits>
        <bits access="rw" name="portsize[2:0]" pos="6:4" rst="4">
          <comment>Use this field with bit [21] to specify the port size.The port size determines how many external pins are available to output the trace information on ATDATA[31:0]. ETM-A5 supports only the 32-bit port size, corresponding to a Port size[3:0] value of b0100, but you can write other values to these bits, and a read of the register returns the value written. Writing other values to these bits has no effect on the ETM.Bit [10] of the System Configuration Register indicates if these bits are set to select an unsupported port size.For more information see the Embedded Trace Macrocell Architecture Specification. On an ETM reset this field is b100, corresponding to the 32-bit port size.</comment>
        </bits>
        <bits access="rw" name="dataaccess" pos="3:2" rst="0">
          <comment>This field configures the data tracing mode. The possible values are:
b00                   No data tracing.
b01                   Trace only the data portion of the access.
b10                   Trace only the address portion of the access.
b11                   Trace both the address and the data of the access. On an ETM reset this field is zero.</comment>
        </bits>
        <bits access="rw" name="monitorcprt" pos="1" rst="0">
          <comment>This field controls whether CPRTs are traced. The possible values are:
0                       CPRTs not traced.
1                       CPRTs traced.
This bit is used with bit [19]. For details see Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later in the Embedded Trace Macrocell Architecture Specification.</comment>
        </bits>
        <bits access="rw" name="etmpowerdown" pos="0" rst="1">
          <comment>A pin controlled by this bit enables the ETM power to be controlled externally, see Control of ETM power down. The sense of this bit is inverted, and drives the ETMPWRUP signal. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1, ETM tracing is disabled and accesses to any registers other than this register and the Lock Access Register are ignored.On an ETM reset this bit is set to 1.</comment>
        </bits>
      </reg>
      <reg name="etmccr" protect="r">
        <bits access="r" name="etmidrpresent." pos="31" rst="1">
          <comment>ETMIDR present.</comment>
        </bits>
        <bits access="r" name="softwareaccessissupported." pos="27" rst="1">
          <comment>Software access is supported.</comment>
        </bits>
        <bits access="r" name="tracestart/stopblockispresent." pos="26" rst="1">
          <comment>Trace start/stop block is present.</comment>
        </bits>
        <bits access="r" name="numberofcontextidcomparators" pos="25:24" rst="1">
          <comment>Number of Context ID comparators.</comment>
        </bits>
        <bits access="r" name="fifofulllogicabsent." pos="23" rst="0">
          <comment>FIFOFULL logic absent.</comment>
        </bits>
        <bits access="r" name="number_ext_out" pos="21:20" rst="0">
          <comment>Number of external outputs. Determined by the MAXEXTOUT[1:0] inputs.The value of these bits is the minimum of MAXEXTOUT[1:0] and 2, because ETM-A5 supports a maximum of 2 external outputs.</comment>
        </bits>
        <bits access="r" name="number_ext_in" pos="19:17" rst="0">
          <comment>Number of external inputs. Determined by the MAXEXTIN[2:0] inputs. The value of these bits is the minimum of MAXEXTIN[2:0] and 4, because ETM-A5 supports a maximum of 4 external inputs.</comment>
        </bits>
        <bits access="r" name="sequncer_is_present" pos="16" rst="1">
          <comment>The sequencer is present.</comment>
        </bits>
        <bits access="r" name="number_counters" pos="15:13" rst="2">
          <comment>Number of counters.</comment>
        </bits>
        <bits access="r" name="number_mm_decoder" pos="12:8" rst="0">
          <comment>Number of memory map decoders.</comment>
        </bits>
        <bits access="r" name="number_data_comparator" pos="7:4" rst="2">
          <comment>Number of data comparators.</comment>
        </bits>
        <bits access="r" name="number_pair_addr_comparator" pos="3:0" rst="4">
          <comment>Number of pairs of address comparators.</comment>
        </bits>
      </reg>
      <reg name="etmtrigger" protect="rw">
        <bits access="rw" name="func" pos="16:14" rst="0">
          <comment>function:
0: A
1: NOT(A)
2: A AND B
3: NOT(A) AND B
4: NOT(A) AND NOT(B)
5: A OR B
6: NOT(A) OR B
7: NOT(A) OR NOT(B)</comment>
        </bits>
        <bits access="rw" name="resource_b" pos="13:7" rst="0">
          <comment>Resource B
[13:11]: resource type
[10:7]: resource index</comment>
        </bits>
        <bits access="rw" name="resource_a" pos="6:0" rst="0">
          <comment>Resource A</comment>
        </bits>
      </reg>
      <reg name="etmasicctlr" protect="rw">
        <bits access="rw" name="asic_ctl" pos="7:0" rst="0">
          <comment>ASICCTL[7:0]:
when a bit in this field is set to 0 the corresponding bit of ASICCTL[7:0] is LOW
when a bit in this field is set to 1 the corresponding bit of ASICCTL[7:0] is HIGH.</comment>
        </bits>
      </reg>
      <reg name="etmsr" protect="rw">
        <bits access="rw" name="trig_bit" pos="3" rst="0">
          <comment>v3.1 Trigger bit. Set when the trigger occurs, and prevents the trigger from being output until the
ETM is programmed again. This bit exists in all architecture versions, but can
only be accessed in ETMv3.1 and later as described in ETM Programming bit and
associated state on page 3-97.</comment>
        </bits>
        <bits access="r" name="curr_status_trace" pos="2" rst="0">
          <comment>Holds the current status of the trace start/stop resource. If set to 1, it indicates that
a trace on address has been matched, without a corresponding trace off address match</comment>
        </bits>
        <bits access="r" name="curr_effect_val_etm_prog_bit" pos="1" rst="0">
          <comment>The current effective value of the ETM Programming bit, bit [10] of the ETMCR.
You must wait for this bit to go to 1 before you start to program the ETM as
described in ETM Programming bit and associated state on page 3-97.
If you read other bits in the ETMSR while this bit is 0, some instructions might
not have taken effect. ARM recommends that you set the ETM Programming bit
and wait for this bit to go to 1 before reading the overflow bit.
In ETMv3.2 and later this bit remains 0 if there is any data in the FIFO. This
ensures that the FIFO is empty before the ETM programming is changed.
In ETMv3.5 this bit is set when the OS Lock is set. See OS Lock Status Register,
ETMOSLSR, ETMv3.3 and later on page 3-166.
In ETMv3.5 this bit must be polled before saving or restoring state. See Access
permissions for ETMv3.5, multiple power domains on page 3-224</comment>
        </bits>
        <bits access="r" name="trace_overflow" pos="0" rst="0">
          <comment>If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0
when either:
? trace is restarted.
? the ETM Power Down bit, bit [0] of ETMCR, is set to 1.
Setting or clearing the ETM Programming bit does not cause this bit to be cleared
to 0.</comment>
        </bits>
      </reg>
      <reg name="etmscr" protect="r">
        <bits access="r" name="no_fetch_comp" pos="17" rst="1">
          <comment>No Fetch comparisons. If this bit is set to 1, address comparators cannot perform
fetch-stage comparisons. Setting bits [2:0] of an ETMACTR to b000, instruction fetch
causes the comparator to have UNPREDICTABLE behavior.</comment>
        </bits>
        <bits access="r" name="number_support_processor" pos="14:12" rst="0">
          <comment>Number of supported processors minus 1.
The value given here is the maximum value that can be written to bits [27:25] of the
ETMCR, register 0x000. This field must be b000 if the ETM supports Direct JTAG access</comment>
        </bits>
        <bits access="r" name="port_mode_support" pos="11" rst="1">
          <comment>Port mode supported.
Set to 1 if the currently selected port mode is supported internally or externally.</comment>
        </bits>
        <bits access="r" name="port_size_support" pos="10" rst="1">
          <comment>Port size supported.
Set to 1 if the currently selected port size is supported internally or externally for the
currently selected port mode. Enables more complex port sizes to be supported</comment>
        </bits>
        <bits access="r" name="max_port_size_3" pos="9" rst="0">
          <comment>Maximum port size[3]. This bit is used in conjunction with bits [2:0].</comment>
        </bits>
        <bits access="r" name="fifofull_support" pos="8" rst="0">
          <comment>If set to 1, FIFOFULL is supported. This bit is used in conjunction with bit [23] of the
ETMCCR, register 0x001.</comment>
        </bits>
        <bits access="r" name="max_port_size_2_0" pos="2:0" rst="4">
          <comment>Maximum port size[2:0]. This bit is used in conjunction with bit [9]. The value given here
is the maximum size supported by both the ETM and the ASIC. Smaller sizes might or
might not be supported. Check bit [10] for precise information on supported modes. See
bits [6:4] in ETMCR bit assignments on page 3-101.</comment>
        </bits>
      </reg>
      <reg name="etmtsscr" protect="rw">
        <bits access="rw" name="stop_addr" pos="31:16" rst="0">
          <comment>When a bit is set to 1, it selects a single address comparator 16-1 as stop addresses. For
example, bit [16] set to 1 selects single address comparator 1 as a stop address.</comment>
        </bits>
        <bits access="rw" name="start_addr" pos="15:0" rst="0">
          <comment>When a bit is set to 1, it selects a single address comparator 16-1 as start addresses. For
example, bit [0] set to 1 selects single address comparator 1 as a start address.</comment>
        </bits>
      </reg>
      <reg name="etmtecr2" protect="rw">
        <bits access="rw" name="slect_address_comparator" pos="15:0" rst="0">
          <comment>When a bit is set to 1, it selects a single address comparator 16-1 for include/exclude
control. For example, bit [0] set to 1 selects single address comparator 1.</comment>
        </bits>
      </reg>
      <reg name="etmteevr" protect="rw">
        <bits access="rw" name="func" pos="16:14" rst="0">
          <comment>function:
0: A
1: NOT(A)
2: A AND B
3: NOT(A) AND B
4: NOT(A) AND NOT(B)
5: A OR B
6: NOT(A) OR B
7: NOT(A) OR NOT(B)</comment>
        </bits>
        <bits access="rw" name="resource_b" pos="13:7" rst="0">
          <comment>Resource B
[13:11]: resource type
[10:7]: resource index</comment>
        </bits>
        <bits access="rw" name="resource_a" pos="6:0" rst="0">
          <comment>Resource A</comment>
        </bits>
      </reg>
      <reg name="etmtecr1" protect="rw">
        <bits access="rw" name="trace_start_stop_en" pos="25" rst="0">
          <comment>Trace start/stop enable. The possible values of this bit are:
0 Tracing is unaffected by the trace start/stop logic.
1 Tracing is controlled by the trace on and off addresses configured for the
trace start/stop logic. See The trace start/stop block on page 2-40.
The trace start/stop resource (resource 0x5F) is unaffected by the value of this bit.</comment>
        </bits>
        <bits access="rw" name="include_exclude_ctrl" pos="24" rst="0">
          <comment>Include/exclude control. The possible values of this bit are:
0 Include. The specified resources indicate the regions where tracing can
occur. When outside this region tracing is prevented.
1 Exclude. The resources, specified in bits [23:0] and in the ETMTECR2,
indicate regions to be excluded from the trace. When outside an exclude
region, tracing can occur.</comment>
        </bits>
        <bits access="rw" name="select_mm_decoder" pos="23:8" rst="0">
          <comment>When a bit is set to 1, it selects memory map decode 16-1 for include/exclude control. For
example, bit [8] set to 1 selects MMD 1.</comment>
        </bits>
        <bits access="rw" name="select_addr_range_comparator" pos="7:0" rst="0">
          <comment>When a bit is set to 1, it selects address range comparator 8-1 for include/exclude control.
For example, bit [0] set to 1 selects address range comparator 1.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="etmfflr" protect="rw">
        <bits access="rw" name="number_bytes_left_fifo" pos="7:0" rst="0">
          <comment>The number of bytes left in the FIFO, below which the FIFOFULL or
SuppressData signal is asserted. For example, setting this value to 15 causes data
trace suppression or processor stalling, if enabled, when there are less than 15 free
bytes in the FIFO.</comment>
        </bits>
      </reg>
      <reg name="etmvdevr" protect="rw">
        <bits access="rw" name="func" pos="16:14" rst="0">
          <comment>function:
0: A
1: NOT(A)
2: A AND B
3: NOT(A) AND B
4: NOT(A) AND NOT(B)
5: A OR B
6: NOT(A) OR B
7: NOT(A) OR NOT(B)</comment>
        </bits>
        <bits access="rw" name="resource_b" pos="13:7" rst="0">
          <comment>Resource B
[13:11]: resource type
[10:7]: resource index</comment>
        </bits>
        <bits access="rw" name="resource_a" pos="6:0" rst="0">
          <comment>Resource A</comment>
        </bits>
      </reg>
      <reg name="etmvdcr1" protect="rw">
        <bits access="rw" name="select_addr_comparator_exclude" pos="31:16" rst="0">
          <comment>When a bit is set to 1, it selects single address comparator 16 to 1 for exclude control. For
example, bit [16] set to 1 selects single address comparator 1.</comment>
        </bits>
        <bits access="rw" name="select_addr_comparator_include" pos="15:0" rst="0">
          <comment>When a bit is set to 1, it selects single address comparator 16 to 1 for include control. For
example, bit [0] set to 1 selects single address comparator 1.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="etmvdcr3" protect="rw">
        <bits access="rw" name="exclude_ctrl" pos="16" rst="0">
          <comment>Exclude-only control. The possible values of this bit are:
0 Mixed mode. ViewData operates in a mixed mode, and both include and
exclude resources can be programmed.
1 Exclude-only mode. ViewData is programmed only in an excluding mode.
If none of the excluding resources match, tracing can occur.</comment>
        </bits>
        <bits access="rw" name="select_addr_comparator_exclude" pos="15:8" rst="0">
          <comment>When a bit is set to 1, it selects address range comparator 8-1 for exclude control. For
example, bit [8] set to 1 selects address range comparator 1.</comment>
        </bits>
        <bits access="rw" name="select_addr_comparator_include" pos="7:0" rst="0">
          <comment>When a bit is set to 1, it selects address range comparator 8-1 for include control. For
example, bit [0] set to 1 selects address range comparator 1.</comment>
        </bits>
      </reg>
      <reg name="etmacvr1" protect="rw">
        <bits access="rw" name="addr_value" pos="31:0" rst="0">
          <comment>Address value</comment>
        </bits>
      </reg>
      <reg name="etmacvr2" protect="rw">
        <bits access="rw" name="addr_value" pos="31:0" rst="0">
          <comment>Address value</comment>
        </bits>
      </reg>
      <reg name="etmacvr3" protect="rw">
        <bits access="rw" name="addr_value" pos="31:0" rst="0">
          <comment>Address value</comment>
        </bits>
      </reg>
      <reg name="etmacvr4" protect="rw">
        <bits access="rw" name="addr_value" pos="31:0" rst="0">
          <comment>Address value</comment>
        </bits>
      </reg>
      <reg name="etmacvr5" protect="rw">
        <bits access="rw" name="addr_value" pos="31:0" rst="0">
          <comment>Address value</comment>
        </bits>
      </reg>
      <reg name="etmacvr6" protect="rw">
        <bits access="rw" name="addr_value" pos="31:0" rst="0">
          <comment>Address value</comment>
        </bits>
      </reg>
      <reg name="etmacvr7" protect="rw">
        <bits access="rw" name="addr_value" pos="31:0" rst="0">
          <comment>Address value</comment>
        </bits>
      </reg>
      <reg name="etmacvr8" protect="rw">
        <bits access="rw" name="addr_value" pos="31:0" rst="0">
          <comment>Address value</comment>
        </bits>
      </reg>
      <hole size="256"/>
      <reg name="etmactr1" protect="rw">
        <bits access="rw" name="vmid_comp_enable" pos="15" rst="0">
          <comment>Virtual Machine ID (VMID) comparison enable, if the processor implements the
Virtualization Extensions.b
A value of 1 means that the address comparator matches only if the current VMID matches
the value stored in the ETMVMIDCVR. See VMID Comparator Value Register,
ETMVMIDCVR, ETMv3.5 on page 3-164.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions</comment>
        </bits>
        <bits access="rw" name="hyp_mode_comp_enable" pos="14" rst="0">
          <comment>Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b
A value of 1 means that the address comparator also matches if the processor is operating
in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions.</comment>
        </bits>
        <bits access="rw" name="state_mode_comp_enable" pos="13:10" rst="0">
          <comment>State and mode comparison control. The assignment of these bits is:
Bit [13, 11] Non-secure state comparison control.
Bit [12, 10] Secure state comparison control.
For each pair of bits, the encoding is:
b00 Match in all modes in this state.
b01 Do not match in any modes in this state.
b10 Match in all modes except User mode in this state.
b11 Match only in User mode in this state.
If the processor does not implement the Security Extensions, bits [13, 11] are reserved,
RAZ/WI.
See Filtering by state and mode, in ETMv3.5 on page 3-131</comment>
        </bits>
        <bits access="rw" name="context_id_comp_ctrl" pos="9:8" rst="0">
          <comment>Context ID comparator control. The permitted values of this field are:
b00 Ignore Context ID comparator.
b01 Address comparator matches only if Context ID comparator value 1
matches.
b10 Address comparator matches only if Context ID comparator value 2
matches.
b11 Address comparator matches only if Context ID comparator value 3
matches.</comment>
        </bits>
        <bits access="rw" name="exact_match" pos="7" rst="0">
          <comment>Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses
occur. See Exact matching, in ETMv2.0 and later on page 2-54.</comment>
        </bits>
        <bits access="rw" name="data_value_comp_ctrl" pos="6:5" rst="0">
          <comment>Data value comparison control. The permitted values of this field are:
b00 No data value comparison is made.
b01 Comparator can match only if data value matches.
b11 Comparator can match only if data value does not match.
The value of b10 is reserved and must not be used.
Note:
The b11 encoding was introduced in ETM architecture version 1.2. Previously this value
was reserved.
For details of the effect of this field on data value comparison, see Exact matching for data
address comparisons on page 2-56.</comment>
        </bits>
        <bits access="rw" name="comp_access_size" pos="4:3" rst="0">
          <comment>Comparison access size. The permitted values of this field are:
b00 Java instruction (from ETM architecture version 1.3 only) or byte data.
b01 Thumb instruction or halfword data.
b11 ARM instruction or word data.
The value of b10 is reserved and must not be used.
For more information, see Comparator access size on page 2-49.</comment>
        </bits>
        <bits access="rw" name="access_type" pos="2:0" rst="0">
          <comment>Access type. The permitted values of this field are:
b000c Instruction fetch.
b001 Instruction execute.
b010 Instruction executed and passed condition code test.
b011 Instruction executed and failed condition code test.
b100 Data load or store.
b101 Data load.
b110 Data store.
The value of b111 is reserved and must not be used.
Note:
? The b010 and b011 encodings were introduced in ETM architecture version 1.2.
Previously these values were reserved.
? From ETMv3.3, if data address comparisons are not supported, writing b100, b101
or b110 to this field causes UNPREDICTABLE behavior. See No data address
comparator option, ETMv3.3 and later on page 2-25 for more information.</comment>
        </bits>
      </reg>
      <reg name="etmactr2" protect="rw">
        <bits access="rw" name="vmid_comp_enable" pos="15" rst="0">
          <comment>Virtual Machine ID (VMID) comparison enable, if the processor implements the
Virtualization Extensions.b
A value of 1 means that the address comparator matches only if the current VMID matches
the value stored in the ETMVMIDCVR. See VMID Comparator Value Register,
ETMVMIDCVR, ETMv3.5 on page 3-164.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions</comment>
        </bits>
        <bits access="rw" name="hyp_mode_comp_enable" pos="14" rst="0">
          <comment>Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b
A value of 1 means that the address comparator also matches if the processor is operating
in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions.</comment>
        </bits>
        <bits access="rw" name="state_mode_comp_enable" pos="13:10" rst="0">
          <comment>State and mode comparison control. The assignment of these bits is:
Bit [13, 11] Non-secure state comparison control.
Bit [12, 10] Secure state comparison control.
For each pair of bits, the encoding is:
b00 Match in all modes in this state.
b01 Do not match in any modes in this state.
b10 Match in all modes except User mode in this state.
b11 Match only in User mode in this state.
If the processor does not implement the Security Extensions, bits [13, 11] are reserved,
RAZ/WI.
See Filtering by state and mode, in ETMv3.5 on page 3-131</comment>
        </bits>
        <bits access="rw" name="context_id_comp_ctrl" pos="9:8" rst="0">
          <comment>Context ID comparator control. The permitted values of this field are:
b00 Ignore Context ID comparator.
b01 Address comparator matches only if Context ID comparator value 1
matches.
b10 Address comparator matches only if Context ID comparator value 2
matches.
b11 Address comparator matches only if Context ID comparator value 3
matches.</comment>
        </bits>
        <bits access="rw" name="exact_match" pos="7" rst="0">
          <comment>Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses
occur. See Exact matching, in ETMv2.0 and later on page 2-54.</comment>
        </bits>
        <bits access="rw" name="data_value_comp_ctrl" pos="6:5" rst="0">
          <comment>Data value comparison control. The permitted values of this field are:
b00 No data value comparison is made.
b01 Comparator can match only if data value matches.
b11 Comparator can match only if data value does not match.
The value of b10 is reserved and must not be used.
Note:
The b11 encoding was introduced in ETM architecture version 1.2. Previously this value
was reserved.
For details of the effect of this field on data value comparison, see Exact matching for data
address comparisons on page 2-56.</comment>
        </bits>
        <bits access="rw" name="comp_access_size" pos="4:3" rst="0">
          <comment>Comparison access size. The permitted values of this field are:
b00 Java instruction (from ETM architecture version 1.3 only) or byte data.
b01 Thumb instruction or halfword data.
b11 ARM instruction or word data.
The value of b10 is reserved and must not be used.
For more information, see Comparator access size on page 2-49.</comment>
        </bits>
        <bits access="rw" name="access_type" pos="2:0" rst="0">
          <comment>Access type. The permitted values of this field are:
b000c Instruction fetch.
b001 Instruction execute.
b010 Instruction executed and passed condition code test.
b011 Instruction executed and failed condition code test.
b100 Data load or store.
b101 Data load.
b110 Data store.
The value of b111 is reserved and must not be used.
Note:
? The b010 and b011 encodings were introduced in ETM architecture version 1.2.
Previously these values were reserved.
? From ETMv3.3, if data address comparisons are not supported, writing b100, b101
or b110 to this field causes UNPREDICTABLE behavior. See No data address
comparator option, ETMv3.3 and later on page 2-25 for more information.</comment>
        </bits>
      </reg>
      <reg name="etmactr3" protect="rw">
        <bits access="rw" name="vmid_comp_enable" pos="15" rst="0">
          <comment>Virtual Machine ID (VMID) comparison enable, if the processor implements the
Virtualization Extensions.b
A value of 1 means that the address comparator matches only if the current VMID matches
the value stored in the ETMVMIDCVR. See VMID Comparator Value Register,
ETMVMIDCVR, ETMv3.5 on page 3-164.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions</comment>
        </bits>
        <bits access="rw" name="hyp_mode_comp_enable" pos="14" rst="0">
          <comment>Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b
A value of 1 means that the address comparator also matches if the processor is operating
in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions.</comment>
        </bits>
        <bits access="rw" name="state_mode_comp_enable" pos="13:10" rst="0">
          <comment>State and mode comparison control. The assignment of these bits is:
Bit [13, 11] Non-secure state comparison control.
Bit [12, 10] Secure state comparison control.
For each pair of bits, the encoding is:
b00 Match in all modes in this state.
b01 Do not match in any modes in this state.
b10 Match in all modes except User mode in this state.
b11 Match only in User mode in this state.
If the processor does not implement the Security Extensions, bits [13, 11] are reserved,
RAZ/WI.
See Filtering by state and mode, in ETMv3.5 on page 3-131</comment>
        </bits>
        <bits access="rw" name="context_id_comp_ctrl" pos="9:8" rst="0">
          <comment>Context ID comparator control. The permitted values of this field are:
b00 Ignore Context ID comparator.
b01 Address comparator matches only if Context ID comparator value 1
matches.
b10 Address comparator matches only if Context ID comparator value 2
matches.
b11 Address comparator matches only if Context ID comparator value 3
matches.</comment>
        </bits>
        <bits access="rw" name="exact_match" pos="7" rst="0">
          <comment>Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses
occur. See Exact matching, in ETMv2.0 and later on page 2-54.</comment>
        </bits>
        <bits access="rw" name="data_value_comp_ctrl" pos="6:5" rst="0">
          <comment>Data value comparison control. The permitted values of this field are:
b00 No data value comparison is made.
b01 Comparator can match only if data value matches.
b11 Comparator can match only if data value does not match.
The value of b10 is reserved and must not be used.
Note:
The b11 encoding was introduced in ETM architecture version 1.2. Previously this value
was reserved.
For details of the effect of this field on data value comparison, see Exact matching for data
address comparisons on page 2-56.</comment>
        </bits>
        <bits access="rw" name="comp_access_size" pos="4:3" rst="0">
          <comment>Comparison access size. The permitted values of this field are:
b00 Java instruction (from ETM architecture version 1.3 only) or byte data.
b01 Thumb instruction or halfword data.
b11 ARM instruction or word data.
The value of b10 is reserved and must not be used.
For more information, see Comparator access size on page 2-49.</comment>
        </bits>
        <bits access="rw" name="access_type" pos="2:0" rst="0">
          <comment>Access type. The permitted values of this field are:
b000c Instruction fetch.
b001 Instruction execute.
b010 Instruction executed and passed condition code test.
b011 Instruction executed and failed condition code test.
b100 Data load or store.
b101 Data load.
b110 Data store.
The value of b111 is reserved and must not be used.
Note:
? The b010 and b011 encodings were introduced in ETM architecture version 1.2.
Previously these values were reserved.
? From ETMv3.3, if data address comparisons are not supported, writing b100, b101
or b110 to this field causes UNPREDICTABLE behavior. See No data address
comparator option, ETMv3.3 and later on page 2-25 for more information.</comment>
        </bits>
      </reg>
      <reg name="etmactr4" protect="rw">
        <bits access="rw" name="vmid_comp_enable" pos="15" rst="0">
          <comment>Virtual Machine ID (VMID) comparison enable, if the processor implements the
Virtualization Extensions.b
A value of 1 means that the address comparator matches only if the current VMID matches
the value stored in the ETMVMIDCVR. See VMID Comparator Value Register,
ETMVMIDCVR, ETMv3.5 on page 3-164.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions</comment>
        </bits>
        <bits access="rw" name="hyp_mode_comp_enable" pos="14" rst="0">
          <comment>Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b
A value of 1 means that the address comparator also matches if the processor is operating
in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions.</comment>
        </bits>
        <bits access="rw" name="state_mode_comp_enable" pos="13:10" rst="0">
          <comment>State and mode comparison control. The assignment of these bits is:
Bit [13, 11] Non-secure state comparison control.
Bit [12, 10] Secure state comparison control.
For each pair of bits, the encoding is:
b00 Match in all modes in this state.
b01 Do not match in any modes in this state.
b10 Match in all modes except User mode in this state.
b11 Match only in User mode in this state.
If the processor does not implement the Security Extensions, bits [13, 11] are reserved,
RAZ/WI.
See Filtering by state and mode, in ETMv3.5 on page 3-131</comment>
        </bits>
        <bits access="rw" name="context_id_comp_ctrl" pos="9:8" rst="0">
          <comment>Context ID comparator control. The permitted values of this field are:
b00 Ignore Context ID comparator.
b01 Address comparator matches only if Context ID comparator value 1
matches.
b10 Address comparator matches only if Context ID comparator value 2
matches.
b11 Address comparator matches only if Context ID comparator value 3
matches.</comment>
        </bits>
        <bits access="rw" name="exact_match" pos="7" rst="0">
          <comment>Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses
occur. See Exact matching, in ETMv2.0 and later on page 2-54.</comment>
        </bits>
        <bits access="rw" name="data_value_comp_ctrl" pos="6:5" rst="0">
          <comment>Data value comparison control. The permitted values of this field are:
b00 No data value comparison is made.
b01 Comparator can match only if data value matches.
b11 Comparator can match only if data value does not match.
The value of b10 is reserved and must not be used.
Note:
The b11 encoding was introduced in ETM architecture version 1.2. Previously this value
was reserved.
For details of the effect of this field on data value comparison, see Exact matching for data
address comparisons on page 2-56.</comment>
        </bits>
        <bits access="rw" name="comp_access_size" pos="4:3" rst="0">
          <comment>Comparison access size. The permitted values of this field are:
b00 Java instruction (from ETM architecture version 1.3 only) or byte data.
b01 Thumb instruction or halfword data.
b11 ARM instruction or word data.
The value of b10 is reserved and must not be used.
For more information, see Comparator access size on page 2-49.</comment>
        </bits>
        <bits access="rw" name="access_type" pos="2:0" rst="0">
          <comment>Access type. The permitted values of this field are:
b000c Instruction fetch.
b001 Instruction execute.
b010 Instruction executed and passed condition code test.
b011 Instruction executed and failed condition code test.
b100 Data load or store.
b101 Data load.
b110 Data store.
The value of b111 is reserved and must not be used.
Note:
? The b010 and b011 encodings were introduced in ETM architecture version 1.2.
Previously these values were reserved.
? From ETMv3.3, if data address comparisons are not supported, writing b100, b101
or b110 to this field causes UNPREDICTABLE behavior. See No data address
comparator option, ETMv3.3 and later on page 2-25 for more information.</comment>
        </bits>
      </reg>
      <reg name="etmactr5" protect="rw">
        <bits access="rw" name="vmid_comp_enable" pos="15" rst="0">
          <comment>Virtual Machine ID (VMID) comparison enable, if the processor implements the
Virtualization Extensions.b
A value of 1 means that the address comparator matches only if the current VMID matches
the value stored in the ETMVMIDCVR. See VMID Comparator Value Register,
ETMVMIDCVR, ETMv3.5 on page 3-164.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions</comment>
        </bits>
        <bits access="rw" name="hyp_mode_comp_enable" pos="14" rst="0">
          <comment>Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b
A value of 1 means that the address comparator also matches if the processor is operating
in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions.</comment>
        </bits>
        <bits access="rw" name="state_mode_comp_enable" pos="13:10" rst="0">
          <comment>State and mode comparison control. The assignment of these bits is:
Bit [13, 11] Non-secure state comparison control.
Bit [12, 10] Secure state comparison control.
For each pair of bits, the encoding is:
b00 Match in all modes in this state.
b01 Do not match in any modes in this state.
b10 Match in all modes except User mode in this state.
b11 Match only in User mode in this state.
If the processor does not implement the Security Extensions, bits [13, 11] are reserved,
RAZ/WI.
See Filtering by state and mode, in ETMv3.5 on page 3-131</comment>
        </bits>
        <bits access="rw" name="context_id_comp_ctrl" pos="9:8" rst="0">
          <comment>Context ID comparator control. The permitted values of this field are:
b00 Ignore Context ID comparator.
b01 Address comparator matches only if Context ID comparator value 1
matches.
b10 Address comparator matches only if Context ID comparator value 2
matches.
b11 Address comparator matches only if Context ID comparator value 3
matches.</comment>
        </bits>
        <bits access="rw" name="exact_match" pos="7" rst="0">
          <comment>Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses
occur. See Exact matching, in ETMv2.0 and later on page 2-54.</comment>
        </bits>
        <bits access="rw" name="data_value_comp_ctrl" pos="6:5" rst="0">
          <comment>Data value comparison control. The permitted values of this field are:
b00 No data value comparison is made.
b01 Comparator can match only if data value matches.
b11 Comparator can match only if data value does not match.
The value of b10 is reserved and must not be used.
Note:
The b11 encoding was introduced in ETM architecture version 1.2. Previously this value
was reserved.
For details of the effect of this field on data value comparison, see Exact matching for data
address comparisons on page 2-56.</comment>
        </bits>
        <bits access="rw" name="comp_access_size" pos="4:3" rst="0">
          <comment>Comparison access size. The permitted values of this field are:
b00 Java instruction (from ETM architecture version 1.3 only) or byte data.
b01 Thumb instruction or halfword data.
b11 ARM instruction or word data.
The value of b10 is reserved and must not be used.
For more information, see Comparator access size on page 2-49.</comment>
        </bits>
        <bits access="rw" name="access_type" pos="2:0" rst="0">
          <comment>Access type. The permitted values of this field are:
b000c Instruction fetch.
b001 Instruction execute.
b010 Instruction executed and passed condition code test.
b011 Instruction executed and failed condition code test.
b100 Data load or store.
b101 Data load.
b110 Data store.
The value of b111 is reserved and must not be used.
Note:
? The b010 and b011 encodings were introduced in ETM architecture version 1.2.
Previously these values were reserved.
? From ETMv3.3, if data address comparisons are not supported, writing b100, b101
or b110 to this field causes UNPREDICTABLE behavior. See No data address
comparator option, ETMv3.3 and later on page 2-25 for more information.</comment>
        </bits>
      </reg>
      <reg name="etmactr6" protect="rw">
        <bits access="rw" name="vmid_comp_enable" pos="15" rst="0">
          <comment>Virtual Machine ID (VMID) comparison enable, if the processor implements the
Virtualization Extensions.b
A value of 1 means that the address comparator matches only if the current VMID matches
the value stored in the ETMVMIDCVR. See VMID Comparator Value Register,
ETMVMIDCVR, ETMv3.5 on page 3-164.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions</comment>
        </bits>
        <bits access="rw" name="hyp_mode_comp_enable" pos="14" rst="0">
          <comment>Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b
A value of 1 means that the address comparator also matches if the processor is operating
in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions.</comment>
        </bits>
        <bits access="rw" name="state_mode_comp_enable" pos="13:10" rst="0">
          <comment>State and mode comparison control. The assignment of these bits is:
Bit [13, 11] Non-secure state comparison control.
Bit [12, 10] Secure state comparison control.
For each pair of bits, the encoding is:
b00 Match in all modes in this state.
b01 Do not match in any modes in this state.
b10 Match in all modes except User mode in this state.
b11 Match only in User mode in this state.
If the processor does not implement the Security Extensions, bits [13, 11] are reserved,
RAZ/WI.
See Filtering by state and mode, in ETMv3.5 on page 3-131</comment>
        </bits>
        <bits access="rw" name="context_id_comp_ctrl" pos="9:8" rst="0">
          <comment>Context ID comparator control. The permitted values of this field are:
b00 Ignore Context ID comparator.
b01 Address comparator matches only if Context ID comparator value 1
matches.
b10 Address comparator matches only if Context ID comparator value 2
matches.
b11 Address comparator matches only if Context ID comparator value 3
matches.</comment>
        </bits>
        <bits access="rw" name="exact_match" pos="7" rst="0">
          <comment>Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses
occur. See Exact matching, in ETMv2.0 and later on page 2-54.</comment>
        </bits>
        <bits access="rw" name="data_value_comp_ctrl" pos="6:5" rst="0">
          <comment>Data value comparison control. The permitted values of this field are:
b00 No data value comparison is made.
b01 Comparator can match only if data value matches.
b11 Comparator can match only if data value does not match.
The value of b10 is reserved and must not be used.
Note:
The b11 encoding was introduced in ETM architecture version 1.2. Previously this value
was reserved.
For details of the effect of this field on data value comparison, see Exact matching for data
address comparisons on page 2-56.</comment>
        </bits>
        <bits access="rw" name="comp_access_size" pos="4:3" rst="0">
          <comment>Comparison access size. The permitted values of this field are:
b00 Java instruction (from ETM architecture version 1.3 only) or byte data.
b01 Thumb instruction or halfword data.
b11 ARM instruction or word data.
The value of b10 is reserved and must not be used.
For more information, see Comparator access size on page 2-49.</comment>
        </bits>
        <bits access="rw" name="access_type" pos="2:0" rst="0">
          <comment>Access type. The permitted values of this field are:
b000c Instruction fetch.
b001 Instruction execute.
b010 Instruction executed and passed condition code test.
b011 Instruction executed and failed condition code test.
b100 Data load or store.
b101 Data load.
b110 Data store.
The value of b111 is reserved and must not be used.
Note:
? The b010 and b011 encodings were introduced in ETM architecture version 1.2.
Previously these values were reserved.
? From ETMv3.3, if data address comparisons are not supported, writing b100, b101
or b110 to this field causes UNPREDICTABLE behavior. See No data address
comparator option, ETMv3.3 and later on page 2-25 for more information.</comment>
        </bits>
      </reg>
      <reg name="etmactr7" protect="rw">
        <bits access="rw" name="vmid_comp_enable" pos="15" rst="0">
          <comment>Virtual Machine ID (VMID) comparison enable, if the processor implements the
Virtualization Extensions.b
A value of 1 means that the address comparator matches only if the current VMID matches
the value stored in the ETMVMIDCVR. See VMID Comparator Value Register,
ETMVMIDCVR, ETMv3.5 on page 3-164.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions</comment>
        </bits>
        <bits access="rw" name="hyp_mode_comp_enable" pos="14" rst="0">
          <comment>Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b
A value of 1 means that the address comparator also matches if the processor is operating
in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions.</comment>
        </bits>
        <bits access="rw" name="state_mode_comp_enable" pos="13:10" rst="0">
          <comment>State and mode comparison control. The assignment of these bits is:
Bit [13, 11] Non-secure state comparison control.
Bit [12, 10] Secure state comparison control.
For each pair of bits, the encoding is:
b00 Match in all modes in this state.
b01 Do not match in any modes in this state.
b10 Match in all modes except User mode in this state.
b11 Match only in User mode in this state.
If the processor does not implement the Security Extensions, bits [13, 11] are reserved,
RAZ/WI.
See Filtering by state and mode, in ETMv3.5 on page 3-131</comment>
        </bits>
        <bits access="rw" name="context_id_comp_ctrl" pos="9:8" rst="0">
          <comment>Context ID comparator control. The permitted values of this field are:
b00 Ignore Context ID comparator.
b01 Address comparator matches only if Context ID comparator value 1
matches.
b10 Address comparator matches only if Context ID comparator value 2
matches.
b11 Address comparator matches only if Context ID comparator value 3
matches.</comment>
        </bits>
        <bits access="rw" name="exact_match" pos="7" rst="0">
          <comment>Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses
occur. See Exact matching, in ETMv2.0 and later on page 2-54.</comment>
        </bits>
        <bits access="rw" name="data_value_comp_ctrl" pos="6:5" rst="0">
          <comment>Data value comparison control. The permitted values of this field are:
b00 No data value comparison is made.
b01 Comparator can match only if data value matches.
b11 Comparator can match only if data value does not match.
The value of b10 is reserved and must not be used.
Note:
The b11 encoding was introduced in ETM architecture version 1.2. Previously this value
was reserved.
For details of the effect of this field on data value comparison, see Exact matching for data
address comparisons on page 2-56.</comment>
        </bits>
        <bits access="rw" name="comp_access_size" pos="4:3" rst="0">
          <comment>Comparison access size. The permitted values of this field are:
b00 Java instruction (from ETM architecture version 1.3 only) or byte data.
b01 Thumb instruction or halfword data.
b11 ARM instruction or word data.
The value of b10 is reserved and must not be used.
For more information, see Comparator access size on page 2-49.</comment>
        </bits>
        <bits access="rw" name="access_type" pos="2:0" rst="0">
          <comment>Access type. The permitted values of this field are:
b000c Instruction fetch.
b001 Instruction execute.
b010 Instruction executed and passed condition code test.
b011 Instruction executed and failed condition code test.
b100 Data load or store.
b101 Data load.
b110 Data store.
The value of b111 is reserved and must not be used.
Note:
? The b010 and b011 encodings were introduced in ETM architecture version 1.2.
Previously these values were reserved.
? From ETMv3.3, if data address comparisons are not supported, writing b100, b101
or b110 to this field causes UNPREDICTABLE behavior. See No data address
comparator option, ETMv3.3 and later on page 2-25 for more information.</comment>
        </bits>
      </reg>
      <reg name="etmactr8" protect="rw">
        <bits access="rw" name="vmid_comp_enable" pos="15" rst="0">
          <comment>Virtual Machine ID (VMID) comparison enable, if the processor implements the
Virtualization Extensions.b
A value of 1 means that the address comparator matches only if the current VMID matches
the value stored in the ETMVMIDCVR. See VMID Comparator Value Register,
ETMVMIDCVR, ETMv3.5 on page 3-164.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions</comment>
        </bits>
        <bits access="rw" name="hyp_mode_comp_enable" pos="14" rst="0">
          <comment>Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b
A value of 1 means that the address comparator also matches if the processor is operating
in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345.
This bit is reserved, RAZ if the processor does not implement the Virtualization extensions.</comment>
        </bits>
        <bits access="rw" name="state_mode_comp_enable" pos="13:10" rst="0">
          <comment>State and mode comparison control. The assignment of these bits is:
Bit [13, 11] Non-secure state comparison control.
Bit [12, 10] Secure state comparison control.
For each pair of bits, the encoding is:
b00 Match in all modes in this state.
b01 Do not match in any modes in this state.
b10 Match in all modes except User mode in this state.
b11 Match only in User mode in this state.
If the processor does not implement the Security Extensions, bits [13, 11] are reserved,
RAZ/WI.
See Filtering by state and mode, in ETMv3.5 on page 3-131</comment>
        </bits>
        <bits access="rw" name="context_id_comp_ctrl" pos="9:8" rst="0">
          <comment>Context ID comparator control. The permitted values of this field are:
b00 Ignore Context ID comparator.
b01 Address comparator matches only if Context ID comparator value 1
matches.
b10 Address comparator matches only if Context ID comparator value 2
matches.
b11 Address comparator matches only if Context ID comparator value 3
matches.</comment>
        </bits>
        <bits access="rw" name="exact_match" pos="7" rst="0">
          <comment>Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses
occur. See Exact matching, in ETMv2.0 and later on page 2-54.</comment>
        </bits>
        <bits access="rw" name="data_value_comp_ctrl" pos="6:5" rst="0">
          <comment>Data value comparison control. The permitted values of this field are:
b00 No data value comparison is made.
b01 Comparator can match only if data value matches.
b11 Comparator can match only if data value does not match.
The value of b10 is reserved and must not be used.
Note:
The b11 encoding was introduced in ETM architecture version 1.2. Previously this value
was reserved.
For details of the effect of this field on data value comparison, see Exact matching for data
address comparisons on page 2-56.</comment>
        </bits>
        <bits access="rw" name="comp_access_size" pos="4:3" rst="0">
          <comment>Comparison access size. The permitted values of this field are:
b00 Java instruction (from ETM architecture version 1.3 only) or byte data.
b01 Thumb instruction or halfword data.
b11 ARM instruction or word data.
The value of b10 is reserved and must not be used.
For more information, see Comparator access size on page 2-49.</comment>
        </bits>
        <bits access="rw" name="access_type" pos="2:0" rst="0">
          <comment>Access type. The permitted values of this field are:
b000c Instruction fetch.
b001 Instruction execute.
b010 Instruction executed and passed condition code test.
b011 Instruction executed and failed condition code test.
b100 Data load or store.
b101 Data load.
b110 Data store.
The value of b111 is reserved and must not be used.
Note:
? The b010 and b011 encodings were introduced in ETM architecture version 1.2.
Previously these values were reserved.
? From ETMv3.3, if data address comparisons are not supported, writing b100, b101
or b110 to this field causes UNPREDICTABLE behavior. See No data address
comparator option, ETMv3.3 and later on page 2-25 for more information.</comment>
        </bits>
      </reg>
      <hole size="256"/>
      <reg name="etmdcvr1" protect="rw">
        <bits access="rw" name="data_value_comp1" pos="31:0" rst="0">
          <comment>Data value for comparison</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="etmdcvr3" protect="rw">
        <bits access="rw" name="data_value_comp3" pos="31:0" rst="0">
          <comment>Data value for comparison</comment>
        </bits>
      </reg>
      <hole size="416"/>
      <reg name="etmdcmr1" protect="rw">
        <bits access="rw" name="data_mask1" pos="31:0" rst="0">
          <comment>Data mask</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="etmdcmr3" protect="rw">
        <bits access="rw" name="data_mask3" pos="31:0" rst="0">
          <comment>Data mask</comment>
        </bits>
      </reg>
      <hole size="416"/>
      <reg name="etmcntrldvr1" protect="rw">
        <bits access="rw" name="load_count1" pos="15:0" rst="0">
          <comment>Initial count</comment>
        </bits>
      </reg>
      <reg name="etmcntrldvr2" protect="rw">
        <bits access="rw" name="load_count2" pos="15:0" rst="0">
          <comment>Initial count</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="etmcntenr1" protect="rw">
        <bits access="rw" name="count_enable_source" pos="17" rst="0">
          <comment>Count enable source in ETMv1.x. When set to 0, the counter is continuously enabled and
decrements every cycle regardless of the count enable event. When set to 1, the count
enable event is used to enable the counter. ARM recommends that bit [17] is always set to
1 and that the count enable event is used to control counter operation, using 0x6F (TRUE)
if a free running counter is required.
Note
This bit is not supported in ETMv2.0 and later, and is always set to 1 in these ETM
architecture versions.</comment>
        </bits>
        <bits access="rw" name="func" pos="16:14" rst="0">
          <comment>function:
0: A
1: NOT(A)
2: A AND B
3: NOT(A) AND B
4: NOT(A) AND NOT(B)
5: A OR B
6: NOT(A) OR B
7: NOT(A) OR NOT(B)</comment>
        </bits>
        <bits access="rw" name="resource_b" pos="13:7" rst="0">
          <comment>Resource B
[13:11]: resource type
[10:7]: resource index</comment>
        </bits>
        <bits access="rw" name="resource_a" pos="6:0" rst="0">
          <comment>Resource A</comment>
        </bits>
      </reg>
      <reg name="etmcntenr2" protect="rw">
        <bits access="rw" name="count_enable_source" pos="17" rst="0">
          <comment>Count enable source in ETMv1.x. When set to 0, the counter is continuously enabled and
decrements every cycle regardless of the count enable event. When set to 1, the count
enable event is used to enable the counter. ARM recommends that bit [17] is always set to
1 and that the count enable event is used to control counter operation, using 0x6F (TRUE)
if a free running counter is required.
Note
This bit is not supported in ETMv2.0 and later, and is always set to 1 in these ETM
architecture versions.</comment>
        </bits>
        <bits access="rw" name="func" pos="16:14" rst="0">
          <comment>function:
0: A
1: NOT(A)
2: A AND B
3: NOT(A) AND B
4: NOT(A) AND NOT(B)
5: A OR B
6: NOT(A) OR B
7: NOT(A) OR NOT(B)</comment>
        </bits>
        <bits access="rw" name="resource_b" pos="13:7" rst="0">
          <comment>Resource B
[13:11]: resource type
[10:7]: resource index</comment>
        </bits>
        <bits access="rw" name="resource_a" pos="6:0" rst="0">
          <comment>Resource A</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="etmcntrldevr1" protect="rw">
        <bits access="rw" name="func" pos="16:14" rst="0">
          <comment>function:
0: A
1: NOT(A)
2: A AND B
3: NOT(A) AND B
4: NOT(A) AND NOT(B)
5: A OR B
6: NOT(A) OR B
7: NOT(A) OR NOT(B)</comment>
        </bits>
        <bits access="rw" name="resource_b" pos="13:7" rst="0">
          <comment>Resource B
[13:11]: resource type
[10:7]: resource index</comment>
        </bits>
        <bits access="rw" name="resource_a" pos="6:0" rst="0">
          <comment>Resource A</comment>
        </bits>
      </reg>
      <reg name="etmcntrldevr2" protect="rw">
        <bits access="rw" name="func" pos="16:14" rst="0">
          <comment>function:
0: A
1: NOT(A)
2: A AND B
3: NOT(A) AND B
4: NOT(A) AND NOT(B)
5: A OR B
6: NOT(A) OR B
7: NOT(A) OR NOT(B)</comment>
        </bits>
        <bits access="rw" name="resource_b" pos="13:7" rst="0">
          <comment>Resource B
[13:11]: resource type
[10:7]: resource index</comment>
        </bits>
        <bits access="rw" name="resource_a" pos="6:0" rst="0">
          <comment>Resource A</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="etmcntvr1" protect="rw">
        <bits access="rw" name="curr_counter_val" pos="15:0" rst="0">
          <comment>Current counter value. From ETM v3.1, when the Programming bit is set to 1 you
can write to an ETMCNTVR to set the current value of the counter. See ETM Programming bit and associated state on page 3-97 for more information.</comment>
        </bits>
      </reg>
      <reg name="etmcntvr2" protect="rw">
        <bits access="rw" name="curr_counter_val" pos="15:0" rst="0">
          <comment>Current counter value. From ETM v3.1, when the Programming bit is set to 1 you
can write to an ETMCNTVR to set the current value of the counter. See ETM Programming bit and associated state on page 3-97 for more information.</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="etmsqabevr1" protect="rw">
        <bits access="rw" name="sequencer_state_trans_event" pos="16:0" rst="0">
          <comment>Sequencer state transition event</comment>
        </bits>
      </reg>
      <reg name="etmsqabevr2" protect="rw">
        <bits access="rw" name="sequencer_state_trans_event" pos="16:0" rst="0">
          <comment>Sequencer state transition event</comment>
        </bits>
      </reg>
      <reg name="etmsqabevr3" protect="rw">
        <bits access="rw" name="sequencer_state_trans_event" pos="16:0" rst="0">
          <comment>Sequencer state transition event</comment>
        </bits>
      </reg>
      <reg name="etmsqabevr4" protect="rw">
        <bits access="rw" name="sequencer_state_trans_event" pos="16:0" rst="0">
          <comment>Sequencer state transition event</comment>
        </bits>
      </reg>
      <reg name="etmsqabevr5" protect="rw">
        <bits access="rw" name="sequencer_state_trans_event" pos="16:0" rst="0">
          <comment>Sequencer state transition event</comment>
        </bits>
      </reg>
      <reg name="etmsqabevr6" protect="rw">
        <bits access="rw" name="sequencer_state_trans_event" pos="16:0" rst="0">
          <comment>Sequencer state transition event</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="etmsqr" protect="rw">
        <bits access="rw" name="curr_sequencer_state" pos="1:0" rst="0">
          <comment>Current sequencer state.The permitted values of this field are:
b00 Sequencer currently in state 1.
b01 Sequencer currently in state 2.
b10 Sequencer currently in state 3.
The value of b11 is reserved.
From ETMv3.1, when the Programming bit is set to 1, software can write to this
field to force the sequencer to a particular state. The effect of writing b11 to this
field is UNPREDICTABLE, and software must not write this value.</comment>
        </bits>
      </reg>
      <reg name="etmextoutevr1" protect="rw">
        <bits access="rw" name="func" pos="16:14" rst="0">
          <comment>function:
0: A
1: NOT(A)
2: A AND B
3: NOT(A) AND B
4: NOT(A) AND NOT(B)
5: A OR B
6: NOT(A) OR B
7: NOT(A) OR NOT(B)</comment>
        </bits>
        <bits access="rw" name="resource_b" pos="13:7" rst="0">
          <comment>Resource B
[13:11]: resource type
[10:7]: resource index</comment>
        </bits>
        <bits access="rw" name="resource_a" pos="6:0" rst="0">
          <comment>Resource A</comment>
        </bits>
      </reg>
      <reg name="etmextoutevr2" protect="rw">
        <bits access="rw" name="func" pos="16:14" rst="0">
          <comment>function:
0: A
1: NOT(A)
2: A AND B
3: NOT(A) AND B
4: NOT(A) AND NOT(B)
5: A OR B
6: NOT(A) OR B
7: NOT(A) OR NOT(B)</comment>
        </bits>
        <bits access="rw" name="resource_b" pos="13:7" rst="0">
          <comment>Resource B
[13:11]: resource type
[10:7]: resource index</comment>
        </bits>
        <bits access="rw" name="resource_a" pos="6:0" rst="0">
          <comment>Resource A</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="etmcidcvr" protect="rw">
        <bits access="rw" name="context_id" pos="31:0" rst="0">
          <comment>Context ID value</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="etmcidcmr" protect="r">
        <bits access="r" name="context_id_mask" pos="31:0" rst="0">
          <comment>Context ID mask value</comment>
        </bits>
      </reg>
      <hole size="256"/>
      <reg name="etmsyncfr" protect="rw">
        <bits access="rw" name="sync_freq" pos="11:0" rst="1024">
          <comment>Synchronization frequency. Default value is 1024.</comment>
        </bits>
      </reg>
      <reg name="etmidr" protect="r">
        <bits access="r" name="branch_packet_encode_impl" pos="20" rst="0">
          <comment>Branch packet encoding implemented. The possible values of this bit are:
0 The ETM implements the original branch packet encoding. See Branch
packet formats with the original address encoding scheme on page 7-310.
1 The ETM implements the alternative branch packet encoding. See Branch
packet formats with the alternative address encoding scheme on
page 7-313.</comment>
        </bits>
        <bits access="r" name="sec_ext_support" pos="19" rst="1">
          <comment>Support for Security Extensions. The possible values of this bit are:
0 The ETM behaves as if the processor is in Secure state at all times.
1 The ARM architecture Security Extensions are implemented by the
processor</comment>
        </bits>
        <bits access="r" name="thumb_32bit_instr_support" pos="18" rst="1">
          <comment>Support for 32-bit Thumb instructions. The possible values of this bit are:
0: A 32-bit Thumb instruction is traced as two instructions, and exceptions
might occur between these two instructions.
1: A 32-bit Thumb instruction is traced as a single instruction. See 32-bit
Thumb instructions on page 4-240 for more information.</comment>
        </bits>
        <bits access="r" name="load_pc_first" pos="16" rst="0">
          <comment>Load PC first. If this bit is set to 1, LSMs with the PC in the list load the PC first, followed
by the other registers in the normal order. This can be decompressed by using the following
procedure:
1. Calculate the number of items transferred by the LSM by looking at the code image.
2. As each item is read, assign an address equal to 4 greater than the previous one as
normal.
3. When the number of items read equals the total number of items transferred, subtract
(4 * number of items) from each address other than the first.
Note
This means that a branch address can be traced before the remaining data values of an
instruction. While this has never been prohibited in the protocol, care must be taken to
ensure that this case is correctly handled.</comment>
        </bits>
        <bits access="r" name="processor_family" pos="15:12" rst="15">
          <comment>Processor family. The meaning of this field depends on the value of the Implementer
code.The following apply if Implementer code = 0x41, for ARM Limited:
b0000 ARM7 processor.
b0001 ARM9 processor.
b0010 ARM10 processor.
b0011 ARM11 processor
b1111 Processor family is defined elsewhere. See The Processor family field on
page 3-157 for more information.
When the Implementer code = 0x41, all other values are reserved by ARM Limited.
For any other Implementer code the permitted values of this field are defined by the
implementer.</comment>
        </bits>
        <bits access="r" name="major_etm_arch_ver" pos="11:8" rst="2">
          <comment>Major ETM architecture version number. See The ETM architecture version. Possible
values of this field are:
b0000 ETMv1.
b0001 ETMv2.
b0010 ETMv3.
All other values are reserved.</comment>
        </bits>
        <bits access="r" name="minor_etm_arch_ver" pos="7:4" rst="5">
          <comment>Minor ETM architecture version number. See The ETM architecture version.</comment>
        </bits>
        <bits access="r" name="impl_rev" pos="3:0" rst="0">
          <comment>Implementation revision. See Implementation revision on page 3-157</comment>
        </bits>
      </reg>
      <reg name="etmccer" protect="r">
        <bits access="r" name="timestamp_packet_size" pos="29" rst="1">
          <comment>Timestamp packet size.
This bit is 0 if the size of the packet is 48 bits. This bit is 1 if the size of the packet is 64 bits.</comment>
        </bits>
        <bits access="r" name="timestamp_packet_encoding" pos="28" rst="1">
          <comment>Timestamp packet encoding.
This bit is 1 if the timestamp packet is encoded as a natural binary number. This bit is 0 if
the packet is gray coded. For more information see Encoding of the timestamp value on
page 7-343.</comment>
        </bits>
        <bits access="r" name="reduced_func_counter" pos="27" rst="0">
          <comment>Reduced function counter.
This bit is 1 if counter 1 is implemented as a reduced function counter. This bit is 0 if all
counters are implemented as full-function counters.</comment>
        </bits>
        <bits access="r" name="virt_extension_impl" pos="26" rst="0">
          <comment>The Virtualization Extensions are implemented.
This bit is 1 if the Virtualization Extensions are implemented, and 0 if not implemented.</comment>
        </bits>
        <bits access="r" name="timestamp_impl" pos="22" rst="1">
          <comment>Timestamping implemented.
This bit is 1 if timestamping is implemented, and 0 if it is not implemented</comment>
        </bits>
        <bits access="r" name="etmeibcr_impl" pos="21" rst="0">
          <comment>ETMEIBCR implemented.
This bit is 1 if the register is implemented, and 0 if it is not implemented.</comment>
        </bits>
        <bits access="r" name="trace_embedice_start_stop" pos="20" rst="0">
          <comment>Trace Start/Stop block can use EmbeddedICE watchpoint inputs.
This bit is 1 if the Trace Start/Stop block can use these inputs, and is 0 otherwise.</comment>
        </bits>
        <bits access="r" name="number_embedice_watch_point" pos="19:16" rst="0">
          <comment>Number of EmbeddedICE watchpoint inputs implemented.
This field can take any value from b0000 (0 inputs) to b1000 (8 inputs).</comment>
        </bits>
        <bits access="r" name="number_instr_resource" pos="15:13" rst="0">
          <comment>Number of Instrumentation resources supported. The maximum value of this field is b100,
for four Instrumentation resources.
For more information see Instrumentation resources, from ETMv3.3 on page 2-69.</comment>
        </bits>
        <bits access="r" name="addr_comparison_not_support" pos="12" rst="0">
          <comment>Set to 1 if data address comparisons are not supported.
For more information see No data address comparator option, ETMv3.3 and later on
page 2-25.</comment>
        </bits>
        <bits access="r" name="all_reg_readable" pos="11" rst="1">
          <comment>Set to 1 if all registers are readable</comment>
        </bits>
        <bits access="r" name="size_extended_ext_input" pos="10:3" rst="30">
          <comment>Size of extended external input bus.
This field must be 0 if bits [2:0] are 0.</comment>
        </bits>
        <bits access="r" name="numer_extended_input_sel" pos="2:0" rst="2">
          <comment>Number of extended external input selectors.</comment>
        </bits>
      </reg>
      <reg name="etmextinselr" protect="rw">
        <bits access="rw" name="exteneded_external_input_sel4" pos="31:24" rst="0">
          <comment>Extended external input selector 4</comment>
        </bits>
        <bits access="rw" name="exteneded_external_input_sel3" pos="23:16" rst="0">
          <comment>Extended external input selector 3</comment>
        </bits>
        <bits access="rw" name="exteneded_external_input_sel2" pos="15:8" rst="0">
          <comment>Extended external input selector 2</comment>
        </bits>
        <bits access="rw" name="exteneded_external_input_sel1" pos="7:0" rst="0">
          <comment>Extended external input selector 1</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="etmtsevr" protect="rw">
        <bits access="rw" name="stop_resource_sel" pos="23:16" rst="0">
          <comment>Stop resource selection. Setting a bit in this field to 1 selects the corresponding
EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to
input 1, bit [17] to input 2, and this pattern continues up to bit [23] corresponding to
input 8.</comment>
        </bits>
        <bits access="rw" name="start_resource_sel" pos="7:0" rst="0">
          <comment>Start resource selection. Setting a bit in this field to 1 selects the corresponding
EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to
input 1, bit [1] to input 2, and this pattern continues up to bit [7] corresponding to input 8.</comment>
        </bits>
      </reg>
      <reg name="etmauxcr" protect="rw">
        <bits access="rw" name="auxcr" pos="2:0" rst="0">
      </bits>
      </reg>
      <reg name="etmtraceidr" protect="rw">
        <bits access="rw" name="trace_id_ouput" pos="6:0" rst="0">
          <comment>Trace ID to output onto the trace bus.
On an ETM reset this field is cleared to 0x00.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="etmidr2" protect="r">
        <bits access="r" name="order_trans_swp" pos="1" rst="0">
          <comment>Identifies the order of transfers for a SWP or SWPB instruction:
0 = the Load transfer is traced before the Store transfer
1 = the Store transfer is traced before the Load transfer</comment>
        </bits>
        <bits access="r" name="order_trans_rfe" pos="0" rst="0">
          <comment>Identifies the order of transfers for the RFE instruction:
0 = the PC transfer is traced before the CPSR transfer
1 = the CPSR transfer is traced before the PC transfer</comment>
        </bits>
      </reg>
      <hole size="2112"/>
      <reg name="etmpdsr" protect="r">
        <bits access="r" name="os_lock_status" pos="5" rst="0">
          <comment>OS lock status. The value of this bit is the same as the value of bit [1] of the ETMOSLSR,
which indicates whether the ETM trace registers are locked. See OS Lock Status Register,
ETMOSLSR, ETMv3.3 and later on page 3-166.
This bit is UNKNOWN when the ETM is powered down</comment>
        </bits>
        <bits access="r" name="sticky_reg_state" pos="1" rst="0">
          <comment>Sticky Register state bit. The possible values of this bit are:
0 ETM Trace Registers have not been powered down since this register was
last read.
1 ETM Trace Registers have been powered down since this register was last
read, and have lost their state.
When the core power domain of the ETM is powered down or reset, this bit is set to 1.
Reads of this register when the core power domain is powered down or held in reset return
1 for this bit, and do not change the value of this bit.
Reads of this register when the core power domain is powered up and not held in reset
return the current value of this bit, and then clear this bit to 0. If the Software Lock
mechanism is locked and the ETMPDSR read is made through the memory mapped
interface, this bit is not cleared.
In ETMv3.3 and ETMv3.4,when this bit is set, accesses to any ETM Trace Registers return
an error response.
In ETMv3.5, the value of this bit has no effect on accesses to the ETM Trace Registers.</comment>
        </bits>
        <bits access="r" name="etm_powerup" pos="0" rst="0">
          <comment>ETM powered up bit. The value of this bit indicates whether you can access the ETM Trace
Registers. The possible values are:
0 ETM Trace Registers cannot be accessed.
1 ETM Trace Registers can be accessed.
When this bit is set to 0, accesses to any ETM Trace Registers return an error response.</comment>
        </bits>
      </reg>
      <hole size="24096"/>
      <reg name="itmiscout" protect="w">
        <bits access="w" name="extout" pos="9:8" rst="0">
          <comment>Drives the EXTOUT[1:0] output pins</comment>
        </bits>
        <bits access="w" name="etmwfxready" pos="5" rst="1">
          <comment>Drives the nETMWFXREADY output pin</comment>
        </bits>
        <bits access="w" name="etmdbgrq" pos="4" rst="0">
          <comment>Drives the ETMDBGRQ output pina</comment>
        </bits>
      </reg>
      <reg name="itmiscin" protect="r">
        <bits access="r" name="etmwfxpending" pos="5" rst="0">
          <comment>Returns the value of the ETMWFXPENDING input pin</comment>
        </bits>
        <bits access="r" name="dbgack" pos="4" rst="0">
          <comment>Returns the value of the DBGACK input pin</comment>
        </bits>
        <bits access="r" name="extin" pos="3:0" rst="0">
          <comment>Returns the value of the EXTIN[3:0] input pins</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="ittriggerreq" protect="w">
        <bits access="w" name="trigger" pos="0" rst="1">
          <comment>Drives the TRIGGER output pin</comment>
        </bits>
      </reg>
      <reg name="itatbdata0" protect="r">
        <bits access="r" name="drive_atdata1" pos="4:0" rst="0">
          <comment>Drives the ATDATA[31, 23, 15, 7, 0] output pins</comment>
        </bits>
      </reg>
      <reg name="itatbctr2" protect="r">
        <bits access="r" name="syncreq" pos="2" rst="0">
          <comment>Returns the value of the SYNCREQ input pin</comment>
        </bits>
        <bits access="r" name="afvalid" pos="1" rst="0">
          <comment>Returns the value of the AFVALID input pin</comment>
        </bits>
        <bits access="r" name="atready" pos="0" rst="0">
          <comment>Returns the value of the ATREADY input pin</comment>
        </bits>
      </reg>
      <reg name="itatbctr1" protect="w">
        <bits access="w" name="atid" pos="6:0" rst="0">
          <comment>Drives the ATID[6:0] output pins</comment>
        </bits>
      </reg>
      <reg name="itatbctr0" protect="w">
        <bits access="w" name="atbytes" pos="9:8" rst="0">
          <comment>Drives the ATBYTES[1:0] output pins</comment>
        </bits>
        <bits access="w" name="afready" pos="1" rst="0">
          <comment>Drives the AFREADY output pin</comment>
        </bits>
        <bits access="w" name="atvalid" pos="0" rst="0">
          <comment>Drives the ATVALID output pin</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="etmitctrl" protect="rw">
        <bits access="rw" name="int_mode" pos="0" rst="0">
          <comment>When this bit is set to 1, the device enters an integration mode to enable Topology Detection
or Integration Testing to be checked.
On an ETM reset this bit is cleared to 0.</comment>
        </bits>
      </reg>
      <hole size="1248"/>
      <reg name="etmclaimset" protect="rw">
        <bits access="rw" name="tag_bits_set" pos="7:0" rst="255">
          <comment>On reads, returns 0xFF.
On writes, a 1 in a bit position causes the corresponding bit in the claim tag value to be set.</comment>
        </bits>
      </reg>
      <reg name="etmclaimclr" protect="rw">
        <bits access="rw" name="tag_bits_clr" pos="7:0" rst="0">
          <comment>On reads, returns the current claim tag value.
On writes, a 1 in a bit position causes the corresponding bit in the claim tag value to be
cleared to 0.
On an ETM reset this field is cleared to 0x00.</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="etmlar" protect="w">
        <bits access="w" name="etmlar" pos="31:0" rst="0">
          <comment>Write 0xC5ACCE55 to this field to unlock the ETM.
Write any other value to this field to lock the ETM</comment>
        </bits>
      </reg>
      <reg name="etmlsr" protect="r">
        <bits access="r" name="etmlar_32_bits" pos="2" rst="0">
          <comment>Reads as b0. Indicates that the ETMLAR is 32 bits</comment>
        </bits>
        <bits access="r" name="etm_locked" pos="1" rst="0">
          <comment>Indicates whether the ETM is locked. The possible values of this bit are:
0 Writes are permitted.
1 ETM locked. Writes are ignored.
If this register is accessed from an interface where the lock registers are ignored, this field
reads as 0 regardless of whether the ETM is locked.</comment>
        </bits>
        <bits access="r" name="lock_reg_impl" pos="0" rst="0">
          <comment>Indicates whether the lock registers are implemented for this interface. The possible values
of this bit are:
0 This access is from an interface that ignores the lock registers.
1 This access is from an interface that requires the ETM to be unlocked.</comment>
        </bits>
      </reg>
      <reg name="etmauthstatus" protect="r">
        <bits access="r" name="snid" pos="7:6" rst="0">
          <comment>Permission for Secure non-invasive debug.</comment>
        </bits>
        <bits access="r" name="sid" pos="5:4" rst="0">
          <comment>Reads as b00, Secure invasive debug not supported by the ETM</comment>
        </bits>
        <bits access="r" name="nsnid" pos="3:2" rst="0">
          <comment>Permission for Non-secure non-invasive debug.
This field is only implemented if the processor implemented with the ETM implements the
Security Extensions. When this field is implemented the possible values of the field are:
b10 Non-secure non-invasive debug disabled.
b11 Non-secure non-invasive debug enabled.
This field is a logical OR of the NIDEN and DBGEN signals. It takes the value b11 when
the OR is TRUE, and b10 when the OR is FALSE.
If the processor does not support the Security Extensions, bits [3:2] are reserved, RAZ.</comment>
        </bits>
        <bits access="r" name="nsid" pos="1:0" rst="0">
          <comment>Reads as b00, Non-secure invasive debug not supported by the ETM.</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="etmdevid" protect="r">
      </reg>
      <reg name="etmdevtype" protect="r">
        <bits access="r" name="sub_type" pos="7:4" rst="1">
          <comment>0x1 Sub type, processor trace</comment>
        </bits>
        <bits access="r" name="main_type" pos="3:0" rst="3">
          <comment>0x3 Main type, trace source</comment>
        </bits>
      </reg>
      <reg name="etmpidr4" protect="r">
        <bits access="r" name="n" pos="7:4" rst="0">
          <comment>n, where 2n is number of 4KB blocks used.</comment>
        </bits>
        <bits access="r" name="jep106_con_code" pos="3:0" rst="4">
          <comment>JEP 106 continuation code</comment>
        </bits>
      </reg>
      <reg name="etmpidr5" protect="r">
      </reg>
      <reg name="etmpidr6" protect="r">
      </reg>
      <reg name="etmpidr7" protect="r">
      </reg>
      <reg name="etmpidr0" protect="r">
        <bits access="r" name="part_number" pos="7:0" rst="85">
          <comment>Part Number[7:0].
Middle and Lower BCD value of Device Number.</comment>
        </bits>
      </reg>
      <reg name="etmpidr1" protect="r">
        <bits access="r" name="jep106_id_3_0" pos="7:4" rst="1">
          <comment>JEP 106 identity code[3:0]</comment>
        </bits>
        <bits access="r" name="part_number_11_8" pos="3:0" rst="9">
          <comment>Part Number[11:8].
Upper Binary Coded Decimal (BCD) value of Device Number.</comment>
        </bits>
      </reg>
      <reg name="etmpidr2" protect="r">
        <bits access="r" name="rev_number" pos="7:4" rst="3">
          <comment>Revision Number of Peripheral. This value is the same as the
Implementation revision field of the ETMIDR, see ETM ID Register on
page 3-19.</comment>
        </bits>
        <bits access="r" name="jedec_val_in_use" pos="3" rst="1">
          <comment>Always 1. Indicates that a JEDEC assigned value is used.</comment>
        </bits>
        <bits access="r" name="jep106_id_6_4" pos="2:0" rst="3">
          <comment>JEP 106 identity code[6:4].</comment>
        </bits>
      </reg>
      <reg name="etmpidr3" protect="r">
        <bits access="r" name="revand" pos="7:4" rst="0">
          <comment>RevAnd (at top level). Manufacturer revision number.</comment>
        </bits>
        <bits access="r" name="customized_val" pos="3:0" rst="0">
          <comment>Customer Modified.
0x0 indicates from ARM</comment>
        </bits>
      </reg>
      <reg name="etmcidr0" protect="r">
        <bits access="r" name="cid_7_0" pos="7:0" rst="13">
          <comment>Component identifier, bits [7:0].</comment>
        </bits>
      </reg>
      <reg name="etmcidr1" protect="r">
        <bits access="r" name="component_class" pos="7:4" rst="9">
          <comment>Component class (component identifier, bits [15:12]).</comment>
        </bits>
        <bits access="r" name="cid_11_8" pos="3:0" rst="0">
          <comment>Component identifier, bits [11:8].</comment>
        </bits>
      </reg>
      <reg name="etmcidr2" protect="r">
        <bits access="r" name="cid_23_16" pos="7:0" rst="5">
          <comment>Component identifier, bits [23:16].</comment>
        </bits>
      </reg>
      <reg name="etmcidr3" protect="r">
        <bits access="r" name="cid_31_24" pos="7:0" rst="177">
          <comment>Component identifier, bits [31:24].</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cti.xml">
    <module category="Debug" name="CTI">
      <reg name="cticontrol" protect="rw">
        <bits access="rw" name="glben" pos="0" rst="0">
          <comment>Enables or disables the CTI.
0 When this bit is 0, all cross-triggering mapping logic functionality is disabled.
1 When this bit is 1, cross-triggering mapping logic functionality is enabled.</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="ctiintack" protect="rw">
        <bits access="w" name="intack" pos="7:0" rst="0">
          <comment>Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout
output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing
it to be cleared.</comment>
        </bits>
      </reg>
      <reg name="ctiappset" protect="rw">
        <bits access="rw" name="appset" pos="3:0" rst="0">
          <comment>Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the
register for each channel.
Reads as follows:
0 Application trigger is inactive.
1 Application trigger is active.
Writes as follows:
0 No effect.
1 Generate channel event.</comment>
        </bits>
      </reg>
      <reg name="ctiappclear" protect="rw">
        <bits access="w" name="appclear" pos="3:0" rst="0">
          <comment>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each
channel. On writes, for each bit:
0 Has no effect.
1 Clears the corresponding channel event.</comment>
        </bits>
      </reg>
      <reg name="ctiapppulse" protect="rw">
        <bits access="w" name="appulse" pos="3:0" rst="0">
          <comment>Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of
the register for each channel. On writes, for each bit:
0 Has no effect.
1 Generate an event pulse on the corresponding channel.</comment>
        </bits>
      </reg>
      <reg name="ctiinen0" protect="rw">
        <bits access="w" name="triginen" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated.
There is one bit of the field for each of the four channels. On writes, for each bit:
0 Input trigger 0 events are ignored by the corresponding channel.
1 When an event is received on input trigger 0, ctitrigin[0], generate an event on the
channel corresponding to this bit.</comment>
        </bits>
      </reg>
      <reg name="ctiinen1" protect="rw">
        <bits access="w" name="triginen" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated.
There is one bit of the field for each of the four channels. On writes, for each bit:
0 Input trigger 0 events are ignored by the corresponding channel.
1 When an event is received on input trigger 0, ctitrigin[1], generate an event on the
channel corresponding to this bit.</comment>
        </bits>
      </reg>
      <reg name="ctiinen2" protect="rw">
        <bits access="w" name="triginen" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated.
There is one bit of the field for each of the four channels. On writes, for each bit:
0 Input trigger 0 events are ignored by the corresponding channel.
1 When an event is received on input trigger 0, ctitrigin[2], generate an event on the
channel corresponding to this bit.</comment>
        </bits>
      </reg>
      <reg name="ctiinen3" protect="rw">
        <bits access="w" name="triginen" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated.
There is one bit of the field for each of the four channels. On writes, for each bit:
0 Input trigger 0 events are ignored by the corresponding channel.
1 When an event is received on input trigger 0, ctitrigin[3], generate an event on the
channel corresponding to this bit.</comment>
        </bits>
      </reg>
      <reg name="ctiinen4" protect="rw">
        <bits access="w" name="triginen" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated.
There is one bit of the field for each of the four channels. On writes, for each bit:
0 Input trigger 0 events are ignored by the corresponding channel.
1 When an event is received on input trigger 0, ctitrigin[4], generate an event on the
channel corresponding to this bit.</comment>
        </bits>
      </reg>
      <reg name="ctiinen5" protect="rw">
        <bits access="w" name="triginen" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated.
There is one bit of the field for each of the four channels. On writes, for each bit:
0 Input trigger 0 events are ignored by the corresponding channel.
1 When an event is received on input trigger 0, ctitrigin[5], generate an event on the
channel corresponding to this bit.</comment>
        </bits>
      </reg>
      <reg name="ctiinen6" protect="rw">
        <bits access="w" name="triginen" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated.
There is one bit of the field for each of the four channels. On writes, for each bit:
0 Input trigger 0 events are ignored by the corresponding channel.
1 When an event is received on input trigger 6, ctitrigin[6], generate an event on the
channel corresponding to this bit.</comment>
        </bits>
      </reg>
      <reg name="ctiinen7" protect="rw">
        <bits access="w" name="triginen" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated.
There is one bit of the field for each of the four channels. On writes, for each bit:
0 Input trigger 0 events are ignored by the corresponding channel.
1 When an event is received on input trigger 7, ctitrigin[7], generate an event on the
channel corresponding to this bit.</comment>
        </bits>
      </reg>
      <hole size="768"/>
      <reg name="ctiouten0" protect="rw">
        <bits access="w" name="trigouten" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is
one bit of the field for each of the four channels. On writes, for each bit
0 The corresponding channel is ignored by the output trigger 0.
1 When an event occurs on the channel corresponding to this bit, generate an event
on output event 0, ctitrigout[0].</comment>
        </bits>
      </reg>
      <reg name="ctiouten1" protect="rw">
        <bits access="w" name="trigouten" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is
one bit of the field for each of the four channels. On writes, for each bit
0 The corresponding channel is ignored by the output trigger 0.
1 When an event occurs on the channel corresponding to this bit, generate an event
on output event 1, ctitrigout[1].</comment>
        </bits>
      </reg>
      <reg name="ctiouten2" protect="rw">
        <bits access="w" name="trigouten" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is
one bit of the field for each of the four channels. On writes, for each bit
0 The corresponding channel is ignored by the output trigger 0.
1 When an event occurs on the channel corresponding to this bit, generate an event
on output event 2, ctitrigout[2].</comment>
        </bits>
      </reg>
      <reg name="ctiouten3" protect="rw">
        <bits access="w" name="trigouten" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is
one bit of the field for each of the four channels. On writes, for each bit
0 The corresponding channel is ignored by the output trigger 0.
1 When an event occurs on the channel corresponding to this bit, generate an event
on output event 3, ctitrigout[3].</comment>
        </bits>
      </reg>
      <reg name="ctiouten4" protect="rw">
        <bits access="w" name="trigouten" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is
one bit of the field for each of the four channels. On writes, for each bit
0 The corresponding channel is ignored by the output trigger 0.
1 When an event occurs on the channel corresponding to this bit, generate an event
on output event 4, ctitrigout[4].</comment>
        </bits>
      </reg>
      <reg name="ctiouten5" protect="rw">
        <bits access="w" name="trigouten" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is
one bit of the field for each of the four channels. On writes, for each bit
0 The corresponding channel is ignored by the output trigger 0.
1 When an event occurs on the channel corresponding to this bit, generate an event
on output event 5, ctitrigout[5].</comment>
        </bits>
      </reg>
      <reg name="ctiouten6" protect="rw">
        <bits access="w" name="trigouten" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is
one bit of the field for each of the four channels. On writes, for each bit
0 The corresponding channel is ignored by the output trigger 0.
1 When an event occurs on the channel corresponding to this bit, generate an event
on output event 6, ctitrigout[6].</comment>
        </bits>
      </reg>
      <reg name="ctiouten7" protect="rw">
        <bits access="w" name="trigouten" pos="3:0" rst="0">
          <comment>Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is
one bit of the field for each of the four channels. On writes, for each bit
0 The corresponding channel is ignored by the output trigger 0.
1 When an event occurs on the channel corresponding to this bit, generate an event
on output event 7, ctitrigout[7].</comment>
        </bits>
      </reg>
      <hole size="896"/>
      <reg name="ctitriginstatus" protect="rw">
        <bits access="w" name="triginstatus" pos="7:0" rst="0">
          <comment>Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.
1 ctitrigin is active.
0 ctitrigin is inactive.
Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN.</comment>
        </bits>
      </reg>
      <reg name="ctitrigoutstatus" protect="rw">
        <bits access="w" name="trigoutstatus" pos="7:0" rst="0">
          <comment>Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output.
1 ctitrigout is active.
0 ctitrigout is inactive.</comment>
        </bits>
      </reg>
      <reg name="ctichinstatus" protect="rw">
        <bits access="w" name="ctichinstatus" pos="3:0" rst="0">
          <comment>Shows the status of the ctichin inputs. There is one bit of the field for each channel input.
0 ctichin is inactive.
1 ctichin is active.
Because the register provides a view of the raw ctichin inputs, the reset value is UNKNOWN.</comment>
        </bits>
      </reg>
      <reg name="ctichoutstatus" protect="rw">
        <bits access="w" name="ctichoutstatus" pos="3:0" rst="0">
          <comment>Shows the status of the ctichout outputs. There is one bit of the field for each channel output.
0 ctichout is inactive.
1 ctichout is active.</comment>
        </bits>
      </reg>
      <reg name="ctigate" protect="rw">
        <bits access="rw" name="ctigateen3" pos="3" rst="1">
          <comment>Enable ctichout3. Set to 0 to disable channel propagation.</comment>
        </bits>
        <bits access="rw" name="ctigateen2" pos="2" rst="1">
          <comment>Enable ctichout2. Set to 0 to disable channel propagation.</comment>
        </bits>
        <bits access="rw" name="ctigateen1" pos="1" rst="1">
          <comment>Enable ctichout1. Set to 0 to disable channel propagation.</comment>
        </bits>
        <bits access="rw" name="ctigateen0" pos="0" rst="1">
          <comment>Enable ctichout0. Set to 0 to disable channel propagation.</comment>
        </bits>
      </reg>
      <reg name="asicctl" protect="rw">
        <bits access="w" name="asicctl" pos="7:0" rst="0">
          <comment>When external multiplexing is implemented for trigger signals, then the number of multiplexed signals on
each trigger must be shown in the Device ID Register. This is done using a Verilog define EXTMUXNUM.</comment>
        </bits>
      </reg>
      <hole size="27808"/>
      <reg name="itchinack" protect="rw">
        <bits access="w" name="ctchinack" pos="3:0" rst="0">
          <comment>Sets the value of the ctichinack outputs</comment>
        </bits>
      </reg>
      <reg name="ittriginack" protect="rw">
        <bits access="w" name="cttriginack" pos="7:0" rst="0">
          <comment>Sets the value of the ctitriginack outputs.</comment>
        </bits>
      </reg>
      <reg name="itchout" protect="rw">
        <bits access="w" name="ctchout" pos="3:0" rst="0">
          <comment>Sets the value of the ctichout outputs</comment>
        </bits>
      </reg>
      <reg name="ittrigout" protect="rw">
        <bits access="w" name="cttrigout" pos="7:0" rst="0">
          <comment>Sets the value of the ctitrigout outputs.</comment>
        </bits>
      </reg>
      <reg name="itchoutack" protect="rw">
        <bits access="w" name="ctchoutack" pos="3:0" rst="0">
          <comment>Reads the values of the ctichoutack inputs</comment>
        </bits>
      </reg>
      <reg name="ittrigoutack" protect="rw">
        <bits access="w" name="cttrigoutack" pos="7:0" rst="0">
          <comment>Reads the value of the ctitrigoutack inputs</comment>
        </bits>
      </reg>
      <reg name="itchin" protect="rw">
        <bits access="w" name="ctchin" pos="3:0" rst="0">
          <comment>Reads the value of the ctichin inputs</comment>
        </bits>
      </reg>
      <reg name="ittrigin" protect="rw">
        <bits access="w" name="cttrigin" pos="7:0" rst="0">
          <comment>Reads the values of the ctitrigin inputs.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="itctrl" protect="rw">
        <bits access="w" name="ime" pos="0" rst="0">
          <comment>Integration Mode Enable.
0 Disable integration mode.
1 Enable integration mode.
Note
The CTI must also be enabled using the CTICONTROL register for integration mode operation.</comment>
        </bits>
      </reg>
      <hole size="1248"/>
      <reg name="claimset" protect="rw">
        <bits access="w" name="set" pos="3:0" rst="15">
          <comment>On reads, for each bit:
1 Claim tag bit is implemented
On writes, for each bit:
0 Has no effect.
1 Sets the relevant bit of the claim tag.</comment>
        </bits>
      </reg>
      <reg name="claimclr" protect="rw">
        <bits access="w" name="clr" pos="3:0" rst="0">
          <comment>On reads, for each bit:
0 Claim tag bit is not set.
1 Claim tag bit is set.
On writes, for each bit:
0 Has no effect.
1 Clears the relevant bit of the claim tag.</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="lar" protect="r">
        <bits access="r" name="key" pos="31:0" rst="0">
          <comment>Software lock key value.
0xC5ACCE55 Clear the software lock.
All other write values set the software lock.</comment>
        </bits>
      </reg>
      <reg name="lsr" protect="rw">
        <bits access="rw" name="ntt" pos="2" rst="0">
          <comment>Register size indicator. Always 0. Indicates that the LAR is implemented as 32-bit.</comment>
        </bits>
        <bits access="rw" name="slk" pos="1" rst="1">
          <comment>0 Indicates that write operations are permitted from this interface.
1 Indicates that write operations are not permitted from this interface. Read
operations are permitted.</comment>
        </bits>
        <bits access="rw" name="sli" pos="0" rst="1">
          <comment>Software Lock Implemented. Indicates that a lock control mechanism is present from this
interface.
0 Indicates that a lock control mechanism is not present from this interface. Write
operations to the LAR are ignored.
1 Indicates that a lock control mechanism is present from this interface</comment>
        </bits>
      </reg>
      <reg name="authstatus" protect="rw">
        <bits access="rw" name="snid" pos="7:6" rst="0">
          <comment>Always 0b00. The security level for Secure non-invasive debug is not implemented or is controlled
elsewhere.</comment>
        </bits>
        <bits access="rw" name="sid" pos="5:4" rst="1">
          <comment>Always 0b00 Secure invasive debug is not implemented or is controlled elsewhere.</comment>
        </bits>
        <bits access="rw" name="nsnid" pos="3:2" rst="1">
          <comment>Indicates the security level for Non-secure non-invasive debug:
0b10 Disabled.
0b11 Enabled.</comment>
        </bits>
        <bits access="rw" name="nsid" pos="1:0" rst="1">
          <comment>Indicates the security level for Non-secure invasive debug:
0b10 Disabled.
0b11 Enabled.</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="devid" protect="r">
        <bits access="r" name="numch" pos="19:16" rst="4">
          <comment>Number of ECT channels available.</comment>
        </bits>
        <bits access="r" name="numtrig" pos="15:8" rst="8">
          <comment>Number of ECT triggers available.</comment>
        </bits>
        <bits access="r" name="extmuxnum" pos="4:0" rst="0">
          <comment>Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are
using asicctl. The default value of 0b00000 indicates that no multiplexing is present.
This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly.</comment>
        </bits>
      </reg>
      <reg name="devtype" protect="r">
        <bits access="r" name="sub" pos="7:4" rst="1">
          <comment>Sub-classification of the type of the debug component as specified in the ARM? CoreSight?
Architecture Specification within the major classification as specified in the MAJOR field.
0b0001 Indicates that this component is a cross-triggering component.</comment>
        </bits>
        <bits access="r" name="major" pos="3:0" rst="4">
          <comment>Major classification of the type of the debug component as specified in the ARM? CoreSight?
Architecture Specification for this debug and trace component.
0b0100 Indicates that this component allows a debugger to control other components in a
CoreSight SoC-400 system.</comment>
        </bits>
      </reg>
      <reg name="pidr4" protect="r">
        <bits access="r" name="size" pos="7:4" rst="0">
          <comment>Always 0b0000. Indicates that the device only occupies 4KB of memory.</comment>
        </bits>
        <bits access="r" name="des_2" pos="3:0" rst="4">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b0100 JEDEC continuation code.</comment>
        </bits>
      </reg>
      <reg name="pidr5" protect="r">
      </reg>
      <reg name="pidr6" protect="r">
      </reg>
      <reg name="pidr7" protect="r">
      </reg>
      <reg name="pidr0" protect="r">
        <bits access="r" name="part_0" pos="7:0" rst="6">
          <comment>Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this
part number.
0x06 Indicates bits[7:0] of the part number of the component</comment>
        </bits>
      </reg>
      <reg name="pidr1" protect="r">
        <bits access="r" name="des_0" pos="7:4" rst="11">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code.</comment>
        </bits>
        <bits access="r" name="part_1" pos="3:0" rst="9">
          <comment>Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this
part number.
0b1001 Indicates bits[11:8] of the part number of the component.</comment>
        </bits>
      </reg>
      <reg name="pidr2" protect="r">
        <bits access="r" name="revision" pos="7:4" rst="5">
          <comment>0b0101 This device is at r1p0.</comment>
        </bits>
        <bits access="r" name="jedec" pos="3" rst="1">
          <comment>Always 1. Indicates that a JEDEC assigned value is used.</comment>
        </bits>
        <bits access="r" name="des_1" pos="2:0" rst="3">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code.</comment>
        </bits>
      </reg>
      <reg name="pidr3" protect="r">
        <bits access="r" name="revand" pos="7:4" rst="0">
          <comment>Indicates minor errata fixes specific to the revision of the component being used, for example
metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the
component designers ensure that a metal fix can change this field if required, for example, by
driving it from registers that reset to 0b0000.
0b0000 Indicates that there are no errata fixes to this component.</comment>
        </bits>
        <bits access="r" name="cmod" pos="3:0" rst="0">
          <comment>Customer Modified. Indicates whether the customer has modified the behavior of the component.
In most cases, this field is 0b0000. Customers change this value when they make authorized
modifications to this component.
0b0000 Indicates that the customer has not modified this component.</comment>
        </bits>
      </reg>
      <reg name="cidr0" protect="r">
        <bits access="r" name="prmbl_0" pos="7:0" rst="13">
          <comment>Preamble[0]. Contains bits[7:0] of the component identification code.
0x0D Bits[7:0] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr1" protect="r">
        <bits access="r" name="class" pos="7:4" rst="9">
          <comment>Class of the component, for example, whether the component is a ROM table or a generic
CoreSight SoC-400 component. Contains bits[15:12] of the component identification code.
0b1001 Indicates that the component is a CoreSight SoC-400 component.</comment>
        </bits>
        <bits access="r" name="prmbl_1" pos="3:0" rst="0">
          <comment>Preamble[1]. Contains bits[11:8] of the component identification code.
0b0000 Bits[11:8] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr2" protect="r">
        <bits access="r" name="prmbl_2" pos="7:0" rst="5">
          <comment>Preamble[2]. Contains bits[23:16] of the component identification code.
0x05 Bits[23:16] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr3" protect="r">
        <bits access="r" name="prmbl_3" pos="7:0" rst="177">
          <comment>Preamble[3]. Contains bits[31:24] of the component
identification code.
0xB1 Bits[31:24] of the identification code.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="etb.xml">
    <module category="Debug" name="ETB">
      <hole size="32"/>
      <reg name="rdp" protect="r">
        <bits access="r" name="etb_ram_depth" pos="31:0" rst="0">
          <comment>Defines the depth, in words, of the trace RAM.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="sts" protect="r">
        <bits access="r" name="ftempty" pos="3" rst="1">
          <comment>Formatter pipeline is empty. All data is stored to RAM.
0 Formatter pipeline is not empty.
1 Formatter pipeline is empty.</comment>
        </bits>
        <bits access="r" name="acqcomp" pos="2" rst="0">
          <comment>The acquisition complete flag indicates that the capture is completed when the formatter stops
because of any of the methods defined in the FFCR, or CTL.TraceCaptEn is 0. This sets
FFSR.FtStopped to 1.
0 Acquisition is not complete.
1 Acquisition is complete.</comment>
        </bits>
        <bits access="r" name="triggered" pos="1" rst="0">
          <comment>The Triggered bit is set when the component observes a trigger during programming the FFCR.
Note
This field does not indicate that the formatter embedded a trigger in the trace data.
0 A trigger is not observed.
1 A trigger is observed.</comment>
        </bits>
        <bits access="r" name="full" pos="0" rst="0">
          <comment>The flag indicates whether the RAM is full or not.
0 The RAM write pointer is not wrapped around. The RAM is not full.
1 The RAM write pointer is wrapped around. The RAM is full.</comment>
        </bits>
      </reg>
      <reg name="rrd" protect="r">
        <bits access="r" name="ram_read_data" pos="31:0" rst="0">
          <comment>Data read from the ETB Trace RAM.</comment>
        </bits>
      </reg>
      <reg name="rrp" protect="rw">
        <bits access="rw" name="ram_read_pointer" pos="9:0" rst="0">
          <comment>Sets the read pointer to the required value. The read pointer reads entries from the Trace RAM
through the APB interface.</comment>
        </bits>
      </reg>
      <reg name="rwp" protect="rw">
        <bits access="rw" name="ram_write_pointer" pos="9:0" rst="0">
          <comment>The RAM Write Pointer Register sets the write pointer to the required value. The write pointer
writes entries from the CoreSight bus to the Trace RAM.</comment>
        </bits>
      </reg>
      <reg name="trg" protect="rw">
        <bits access="rw" name="trigger_counter" pos="9:0" rst="0">
          <comment>The counter is used as follows:
Trace after The counter is set to a large value, slightly less than the number of entries
in the RAM.
Trace before The counter is set to a small value.
Trace about The counter is set to half the depth of the trace RAM.
You must not write to this register when trace capture is enabled, FFSR.FtStopped is 0, and
CTL.TraceCaptEn is 1. When a write is attempted, then the register is not updated. A read
operation is permitted when trace capture is enabled.</comment>
        </bits>
      </reg>
      <reg name="ctl" protect="rw">
        <bits access="rw" name="tracecapten" pos="0" rst="0">
          <comment>ETB Trace Capture Enable. This is the master enable bit that sets FtStopped to HIGH when
TraceCaptEn is LOW. When capture is disabled, any remaining data in the ATB formatter is
stored to RAM. When all of the data is stored, the formatter outputs FtStopped. Capture is fully
disabled, or complete, when FtStopped goes HIGH. See ETB Formatter and Flush Status
Register.
0 Disable trace capture.
1 Enable trace capture.</comment>
        </bits>
      </reg>
      <reg name="rwd" protect="rw">
        <bits access="rw" name="ram_write_data" pos="31:0" rst="0">
          <comment>When CTL.TraceCaptEn is 0:
? Writes to this register write the data to the ETB trace RAM. The RAM Write Pointer
Register value is incremented.
? Reads of this register return an UNKNOWN value.
When CTL.TraceCaptEn is 1:
? Writes to this register are ignored. The data is not written to the ETB trace RAM and the
RAM Write Pointer is not affected.
? Reads of this register return an UNKNOWN value.</comment>
        </bits>
      </reg>
      <hole size="5824"/>
      <reg name="ffsr" protect="rw">
        <bits access="rw" name="ftstopped" pos="1" rst="1">
          <comment>Formatter stopped. The formatter has received a stop request signal and all trace data and
post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes
HIGH.
0 Formatter is not stopped.
1 Formatter is stopped.</comment>
        </bits>
        <bits access="rw" name="flinprog" pos="0" rst="0">
          <comment>Flush In Progress. This is an indication of the current state of afvalids.
0 afvalids is LOW.
1 afvalids is HIGH.</comment>
        </bits>
      </reg>
      <reg name="ffcr" protect="rw">
        <bits access="rw" name="stoptrig" pos="13" rst="0">
          <comment>Stops trace capture after a trigger event is observed. The reset value is 0.
0 Disable stopping of the formatter after a trigger event is observed.
1 Enable stopping of the formatter after a trigger event is observed.</comment>
        </bits>
        <bits access="rw" name="stopfl" pos="12" rst="0">
          <comment>Stops trace capture after the next flush completes. The reset value is 0.
0 Disable stopping the formatter when a flush completes.
1 Enable stopping the formatter when a flush completes.</comment>
        </bits>
        <bits access="rw" name="trigfl" pos="10" rst="0">
          <comment>Indicates a Trigger-on-Flush completion.
0 Disable trigger indication on flush completion.
1 Enable trigger indication on flush completion.</comment>
        </bits>
        <bits access="rw" name="trigevt" pos="9" rst="0">
          <comment>Indicates a trigger on a trigger event.
0 Disable trigger indication on a trigger event.
1 Enable trigger indication on a trigger event.</comment>
        </bits>
        <bits access="rw" name="trigin" pos="8" rst="0">
          <comment>Indicates a trigger when trigin is asserted.
0 Disable trigger indication when trigin is asserted.
1 Enable trigger indication when trigin is asserted.</comment>
        </bits>
        <bits access="rw" name="fonman" pos="6" rst="0">
          <comment>Initiates a manual flush. This bit is set to 0 after the flush has been serviced. The reset value is 0.
0 Manual flush is not initiated.
1 Manual flush is initiated.</comment>
        </bits>
        <bits access="rw" name="fontrig" pos="5" rst="0">
          <comment>Flushes the data in the system when a trigger event occurs. The reset value is 0.
0 Disable flush generation when a trigger event occurs.
1 Enable flush generation when a trigger event occurs.</comment>
        </bits>
        <bits access="rw" name="enable_flush_in" pos="4" rst="0">
          <comment>Enables use of the flushin input. The reset value is 0.
0 Disable flush generation using the flushin interface.
1 Enable flush generation using the flushin interface.</comment>
        </bits>
        <bits access="rw" name="enfcont" pos="1" rst="0">
          <comment>When EnFTC is 1, this bit controls whether triggers are recorded in the trace stream. Most usage
models require Continuous mode, where this bit is set to 1. The reset value is 0. See Modes of
operation on page 10-5 for more information.
Note
This bit can only be changed when FtStopped is HIGH.
0 Triggers are not embedded in the trace stream.
1 Triggers are embedded in the trace stream.</comment>
        </bits>
        <bits access="rw" name="enftc" pos="0" rst="0">
          <comment>Enable formatting. Most usage models require Continuous mode, where this bit is set to 1. The
reset value is 0. See Modes of operation on page 10-5 for more information.
Note
This bit can only be changed when FtStopped is HIGH.
0 Formatting is disabled.
1 Formatting is enabled.</comment>
        </bits>
      </reg>
      <hole size="24256"/>
      <reg name="itmiscop0" protect="rw">
        <bits access="w" name="full" pos="1" rst="0">
          <comment>Sets the value of full output.
0 Sets the value to 0.
1 Sets the value to 1.</comment>
        </bits>
        <bits access="w" name="acqcomp" pos="0" rst="0">
          <comment>Sets the value of acqcomp output.
0 Sets the value to 0.
1 Sets the value to 1.</comment>
        </bits>
      </reg>
      <reg name="ittrflinack" protect="rw">
        <bits access="w" name="flushinack" pos="1" rst="0">
          <comment>Sets the value of flushinack.
0 Sets the value of FLUSHINACK to 0.
1 Sets the value of FLUSHINACK to 1.</comment>
        </bits>
        <bits access="w" name="triginack" pos="0" rst="0">
          <comment>Sets the value of triginack.
0 Sets the value of TRIGINACK to 0.
1 Sets the value of TRIGINACK to 1.</comment>
        </bits>
      </reg>
      <reg name="ittrflin" protect="r">
        <bits access="r" name="flushin" pos="1" rst="0">
          <comment>Reads the value of flushin.
0 flushin is LOW.
1 flushin is HIGH.</comment>
        </bits>
        <bits access="r" name="trigin" pos="0" rst="0">
          <comment>TRIGIN Reads the value of trigin.
0 trigin is LOW.
1 trigin is HIGH.</comment>
        </bits>
      </reg>
      <reg name="itatbdata0" protect="rw">
        <bits access="rw" name="atdata_31" pos="4" rst="0">
          <comment>Reads the value of atdatas[31].
0 atdatas[31] is 0.
1 atdatas[31] is 1.</comment>
        </bits>
        <bits access="rw" name="atdata_23" pos="3" rst="0">
          <comment>Reads the value of atdatas[23].
0 atdatas[23] is 0.
1 atdatas[23] is 1.</comment>
        </bits>
        <bits access="rw" name="atdata_15" pos="2" rst="0">
          <comment>Reads the value of atdatas[15].
0 atdatas[15] is 0.
1 atdatas[15] is 1.</comment>
        </bits>
        <bits access="rw" name="atdata_7" pos="1" rst="0">
          <comment>Reads the value of atdatas[7].
0 atdatas[7] is 0.
1 atdatas[7] is 1.</comment>
        </bits>
        <bits access="rw" name="atdata_0" pos="0" rst="0">
          <comment>Reads the value of atdatas[0].
0 atdatas[0] is 0.
1 atdatas[0] is 1.</comment>
        </bits>
      </reg>
      <reg name="itatbctr2" protect="rw">
        <bits access="w" name="afvalids" pos="1" rst="0">
          <comment>Sets the value of afvalids.
0 Sets the value of afvalids to 0.
1 Sets the value of afvalids to 1.</comment>
        </bits>
        <bits access="w" name="atreadys" pos="0" rst="0">
          <comment>Sets the value of atreadys.
0 Sets the value of atreadys to 0.
1 Sets the value of atreadys to 1.</comment>
        </bits>
      </reg>
      <reg name="itatbctr1" protect="rw">
        <bits access="w" name="atid" pos="6:0" rst="0">
          <comment>Reads the value of atids</comment>
        </bits>
      </reg>
      <reg name="itatbctr0" protect="rw">
        <bits access="rw" name="atbytes" pos="9:8" rst="0">
          <comment>Reads the value of atbytess</comment>
        </bits>
        <bits access="rw" name="afready" pos="1" rst="0">
          <comment>Reads the value of afreadys.
0 afreadys is 0.
1 afreadys is 1.</comment>
        </bits>
        <bits access="rw" name="atvalid" pos="0" rst="0">
          <comment>Reads the value of atvalids.
0 atvalids is 0.
1 atvalids is 1.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="itctrl" protect="rw">
        <bits access="w" name="ime" pos="0" rst="0">
          <comment>Integration Mode Enable.
0 Disable integration mode.
1 Enable integration mode.</comment>
        </bits>
      </reg>
      <hole size="1248"/>
      <reg name="claimset" protect="rw">
        <bits access="w" name="set" pos="3:0" rst="15">
          <comment>On reads, for each bit:
1 Claim tag bit is implemented
On writes, for each bit:
0 Has no effect.
1 Sets the relevant bit of the claim tag.</comment>
        </bits>
      </reg>
      <reg name="claimclr" protect="rw">
        <bits access="w" name="clr" pos="3:0" rst="0">
          <comment>On reads, for each bit:
0 Claim tag bit is not set.
1 Claim tag bit is set.
On writes, for each bit:
0 Has no effect.
1 Clears the relevant bit of the claim tag.</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="lar" protect="r">
        <bits access="r" name="key" pos="31:0" rst="0">
          <comment>Software lock key value.
0xC5ACCE55 Clear the software lock.
All other write values set the software lock.</comment>
        </bits>
      </reg>
      <reg name="lsr" protect="rw">
        <bits access="rw" name="ntt" pos="2" rst="0">
          <comment>Register size indicator. Always 0. Indicates that the LAR is implemented as 32-bit.</comment>
        </bits>
        <bits access="rw" name="slk" pos="1" rst="1">
          <comment>0 Indicates that write operations are permitted from this interface.
1 Indicates that write operations are not permitted from this interface. Read
operations are permitted.</comment>
        </bits>
        <bits access="rw" name="sli" pos="0" rst="1">
          <comment>Software Lock Implemented. Indicates that a lock control mechanism is present from this
interface.
0 Indicates that a lock control mechanism is not present from this interface. Write
operations to the LAR are ignored.
1 Indicates that a lock control mechanism is present from this interface</comment>
        </bits>
      </reg>
      <reg name="authstatus" protect="rw">
        <bits access="rw" name="snid" pos="7:6" rst="0">
          <comment>Always 0b00. The security level for Secure non-invasive debug is not implemented or is controlled
elsewhere.</comment>
        </bits>
        <bits access="rw" name="sid" pos="5:4" rst="1">
          <comment>Always 0b00 Secure invasive debug is not implemented or is controlled elsewhere.</comment>
        </bits>
        <bits access="rw" name="nsnid" pos="3:2" rst="1">
          <comment>Indicates the security level for Non-secure non-invasive debug:
0b10 Disabled.
0b11 Enabled.</comment>
        </bits>
        <bits access="rw" name="nsid" pos="1:0" rst="1">
          <comment>Indicates the security level for Non-secure invasive debug:
0b10 Disabled.
0b11 Enabled.</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="devid" protect="r">
        <bits access="r" name="ramclk" pos="5" rst="0">
          <comment>This bit returns 0 on reads to indicate that the ETB RAM operates synchronously to atclk.
0 The ETB RAM operates synchronously to atclk.</comment>
        </bits>
        <bits access="r" name="extmuxnum" pos="4:0" rst="0">
          <comment>Number of external multiplexing available. Non-zero values indicate the type of ATB
multiplexing on the input to the ATB.
0b0000 Only 0x00 is supported, that is, no multiplexing is present. This value helps detect
the ATB structure.</comment>
        </bits>
      </reg>
      <reg name="devtype" protect="r">
        <bits access="r" name="sub" pos="7:4" rst="2">
          <comment>Sub-classification of the type of the debug component as specified in the ARM? CoreSight?
Architecture Specification within the major classification as specified in the MAJOR field.
0b0010 This component is a trace buffer, ETB.</comment>
        </bits>
        <bits access="r" name="major" pos="3:0" rst="1">
          <comment>Major classification of the type of the debug component as specified in the ARM? CoreSight?
Architecture Specification for this debug and trace component.
0b0001 This component is a trace sink component.</comment>
        </bits>
      </reg>
      <reg name="pidr4" protect="r">
        <bits access="r" name="size" pos="7:4" rst="0">
          <comment>Always 0b0000. Indicates that the device only occupies 4KB of memory.</comment>
        </bits>
        <bits access="r" name="des_2" pos="3:0" rst="4">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b0100 JEDEC continuation code.</comment>
        </bits>
      </reg>
      <reg name="pidr5" protect="r">
      </reg>
      <reg name="pidr6" protect="r">
      </reg>
      <reg name="pidr7" protect="r">
      </reg>
      <reg name="pidr0" protect="r">
        <bits access="r" name="part_0" pos="7:0" rst="7">
          <comment>Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this
part number.
0x07 Indicates bits[7:0] of the part number of the component.</comment>
        </bits>
      </reg>
      <reg name="pidr1" protect="r">
        <bits access="r" name="des_0" pos="7:4" rst="11">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code.</comment>
        </bits>
        <bits access="r" name="part_1" pos="3:0" rst="9">
          <comment>Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this
part number.
0b1001 Indicates bits[11:8] of the part number of the component.</comment>
        </bits>
      </reg>
      <reg name="pidr2" protect="r">
        <bits access="r" name="revision" pos="7:4" rst="4">
          <comment>0b0100 This device is at r0p5.</comment>
        </bits>
        <bits access="r" name="jedec" pos="3" rst="1">
          <comment>Always 1. Indicates that a JEDEC assigned value is used.</comment>
        </bits>
        <bits access="r" name="des_1" pos="2:0" rst="3">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code.</comment>
        </bits>
      </reg>
      <reg name="pidr3" protect="r">
        <bits access="r" name="revand" pos="7:4" rst="0">
          <comment>Indicates minor errata fixes specific to the revision of the component being used, for example
metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the
component designers ensure that a metal fix can change this field if required, for example, by
driving it from registers that reset to 0b0000.
0b0000 Indicates that there are no errata fixes to this component.</comment>
        </bits>
        <bits access="r" name="cmod" pos="3:0" rst="0">
          <comment>Customer Modified. Indicates whether the customer has modified the behavior of the component.
In most cases, this field is 0b0000. Customers change this value when they make authorized
modifications to this component.
0b0000 Indicates that the customer has not modified this component.</comment>
        </bits>
      </reg>
      <reg name="cidr0" protect="r">
        <bits access="r" name="prmbl_0" pos="7:0" rst="13">
          <comment>Preamble[0]. Contains bits[7:0] of the component identification code.
0x0D Bits[7:0] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr1" protect="r">
        <bits access="r" name="class" pos="7:4" rst="9">
          <comment>Class of the component, for example, whether the component is a ROM table or a generic
CoreSight SoC-400 component. Contains bits[15:12] of the component identification code.
0b1001 Indicates that the component is a CoreSight SoC-400 component.</comment>
        </bits>
        <bits access="r" name="prmbl_1" pos="3:0" rst="0">
          <comment>Preamble[1]. Contains bits[11:8] of the component identification code.
0b0000 Bits[11:8] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr2" protect="r">
        <bits access="r" name="prmbl_2" pos="7:0" rst="5">
          <comment>Preamble[2]. Contains bits[23:16] of the component identification code.
0x05 Bits[23:16] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr3" protect="r">
        <bits access="r" name="prmbl_3" pos="7:0" rst="177">
          <comment>Preamble[3]. Contains bits[31:24] of the component
identification code.
0xB1 Bits[31:24] of the identification code.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="atb_funnel.xml">
    <module category="Debug" name="ATB_FUNNEL">
      <reg name="ctrl_reg" protect="rw">
        <bits access="rw" name="ht" pos="11:8" rst="3">
          <comment>Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you
can use this setting to minimize switching. When a source has nothing to transmit, then another
source is selected irrespective of the minimum number of transactions. The ATB funnel holds for
the minimum hold time and one additional transaction. The actual hold time is the register value
plus 1. The maximum value that can be entered is 0b1110 and this equates to 15 transactions. 0b1111
is reserved.
0b0000 1 transaction hold time.
0b0001 2 transactions hold time.
0b0010 3 transactions hold time.
0b0011 4 transactions hold time.
0b0100 5 transactions hold time.
0b0101 6 transactions hold time.
0b0110 7 transactions hold time.
0b0111 8 transactions hold time.
0b1000 9 transactions hold time.
0b1001 10 transactions hold time.
0b1010 11 transactions hold time.
0b1011 12 transactions hold time.
0b1100 13 transactions hold time.
0b1101 14 transactions hold time.
0b1110 15 transactions hold time.</comment>
        </bits>
        <bits access="rw" name="ens7" pos="7" rst="0">
          <comment>Enable slave port 7.
The reset value is 0.
0 Slave port disabled.
This excludes the port from the priority selection scheme.
1 Slave port enabled.</comment>
        </bits>
        <bits access="rw" name="ens6" pos="6" rst="0">
          <comment>Enable slave port 6.
The reset value is 0.
0 Slave port disabled.
This excludes the port from the priority selection scheme.
1 Slave port enabled.</comment>
        </bits>
        <bits access="rw" name="ens5" pos="5" rst="0">
          <comment>Enable slave port 5.
The reset value is 0.
0 Slave port disabled.
This excludes the port from the priority selection scheme.
1 Slave port enabled.</comment>
        </bits>
        <bits access="rw" name="ens4" pos="4" rst="0">
          <comment>Enable slave port 4.
The reset value is 0.
0 Slave port disabled.
This excludes the port from the priority selection scheme.
1 Slave port enabled.</comment>
        </bits>
        <bits access="rw" name="ens3" pos="3" rst="0">
          <comment>Enable slave port 3.
The reset value is 0.
0 Slave port disabled.
This excludes the port from the priority selection scheme.
1 Slave port enabled.</comment>
        </bits>
        <bits access="rw" name="ens2" pos="2" rst="0">
          <comment>Enable slave port 2.
The reset value is 0.
0 Slave port disabled.
This excludes the port from the priority selection scheme.
1 Slave port enabled.</comment>
        </bits>
        <bits access="rw" name="ens1" pos="1" rst="0">
          <comment>Enable slave port 1.
The reset value is 0.
0 Slave port disabled.
This excludes the port from the priority selection scheme.
1 Slave port enabled.</comment>
        </bits>
        <bits access="rw" name="ens0" pos="0" rst="0">
          <comment>Enable slave port 0.
The reset value is 0.
0 Slave port disabled.
This excludes the port from the priority selection scheme.
1 Slave port enabled.</comment>
        </bits>
      </reg>
      <reg name="priority_ctrl_reg" protect="rw">
        <bits access="rw" name="priport7" pos="23:21" rst="0">
          <comment>Priority value of the eighth slave port.</comment>
        </bits>
        <bits access="rw" name="priport6" pos="20:18" rst="0">
          <comment>Priority value of the seventh slave port.</comment>
        </bits>
        <bits access="rw" name="priport5" pos="17:15" rst="0">
          <comment>Priority value of the sixth slave port.</comment>
        </bits>
        <bits access="rw" name="priport4" pos="14:12" rst="0">
          <comment>Priority value of the fifth slave port.</comment>
        </bits>
        <bits access="rw" name="priport3" pos="11:9" rst="0">
          <comment>Priority value of the fourth slave port.</comment>
        </bits>
        <bits access="rw" name="priport2" pos="8:6" rst="0">
          <comment>Priority value of the third slave port.</comment>
        </bits>
        <bits access="rw" name="priport1" pos="5:3" rst="0">
          <comment>Priority value of the second slave port.</comment>
        </bits>
        <bits access="rw" name="priport0" pos="2:0" rst="0">
          <comment>Priority value of the first slave port.</comment>
        </bits>
      </reg>
      <hole size="30496"/>
      <reg name="itatbdata0" protect="rw">
        <bits access="rw" name="atdata127" pos="16" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[127] of the enabled port. A write access writes to
atdatam[127] of the enabled port.
0 atdata[127] of the enabled port is LOW.
1 atdata[127] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata119" pos="15" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[119] of the enabled port. A write access writes to
atdatam[119] of the enabled port.
0 atdata[119] of the enabled port is LOW.
1 atdata[119] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata111" pos="14" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[111] of the enabled port. A write access writes to
atdatam[111] of the enabled port.
0 atdata[111] of the enabled port is LOW.
1 atdata[111] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata103" pos="13" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[103] of the enabled port. A write access writes to
atdatam[103] of the enabled port.
0 atdata[103] of the enabled port is LOW.
1 atdata[103] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata95" pos="12" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[95] of the enabled port. A write access writes to
atdatam[95] of the enabled port.
0 atdata[95] of the enabled port is LOW.
1 atdata[95] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata87" pos="11" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[87] of the enabled port. A write access writes to
atdatam[87] of the enabled port.
0 atdata[87] of the enabled port is LOW.
1 atdata[87] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata79" pos="10" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[79] of the enabled port. A write access writes to
atdatam[79] of the enabled port.
0 atdata[79] of the enabled port is LOW.
1 atdata[79] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata71" pos="9" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[71] of the enabled port. A write access writes to
atdatam[71] of the enabled port.
0 atdata[71] of the enabled port is LOW.
1 atdata[71] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata63" pos="8" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[63] of the enabled port. A write access writes to
atdatam[63] of the enabled port.
0 atdata[63] of the enabled port is LOW.
1 atdata[63] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata55" pos="7" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[55] of the enabled port. A write access writes to
atdatam[55] of the enabled port.
0 atdata[55] of the enabled port is LOW.
1 atdata[55] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata47" pos="6" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[47] of the enabled port. A write access writes to
atdatam[47] of the enabled port.
0 atdata[47] of the enabled port is LOW.
1 atdata[47] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata39" pos="5" rst="0">
          <comment>A read access returns the value of atdatas&lt;x&gt;[39] of the enabled port. A write access writes to
atdatam[39] of the enabled port.
0 atdata[39] of the enabled port is LOW.
1 atdata[39] of the enabled port is HIGH.</comment>
        </bits>
        <bits access="rw" name="atdata_31" pos="4" rst="0">
          <comment>Reads the value of atdatas[31].
0 atdatas[31] is 0.
1 atdatas[31] is 1.</comment>
        </bits>
        <bits access="rw" name="atdata_23" pos="3" rst="0">
          <comment>Reads the value of atdatas[23].
0 atdatas[23] is 0.
1 atdatas[23] is 1.</comment>
        </bits>
        <bits access="rw" name="atdata_15" pos="2" rst="0">
          <comment>Reads the value of atdatas[15].
0 atdatas[15] is 0.
1 atdatas[15] is 1.</comment>
        </bits>
        <bits access="rw" name="atdata_7" pos="1" rst="0">
          <comment>Reads the value of atdatas[7].
0 atdatas[7] is 0.
1 atdatas[7] is 1.</comment>
        </bits>
        <bits access="rw" name="atdata_0" pos="0" rst="0">
          <comment>Reads the value of atdatas[0].
0 atdatas[0] is 0.
1 atdatas[0] is 1.</comment>
        </bits>
      </reg>
      <reg name="itatbctr2" protect="rw">
        <bits access="rw" name="afvalid" pos="1" rst="0">
          <comment>A read access returns the value of afvalidm.
A write access outputs the data to afvalidsn, where the value of the Ctrl_Reg at 0x000 defines n.
0 Pin is at logic 0.
1 Pin is at logic 1.</comment>
        </bits>
        <bits access="rw" name="atready" pos="0" rst="0">
          <comment>A read access returns the value of atreadym.
A write access outputs the data to atreadysn, where the value of the Ctrl_Reg at 0x000 defines n.
0 Pin is at logic 0.
1 Pin is at logic 1.</comment>
        </bits>
      </reg>
      <reg name="itatbctr1" protect="rw">
        <bits access="rw" name="atid" pos="6:0" rst="0">
          <comment>A read returns the value of the atidsn signals, where the value of the Control Register at 0x000
defines n.
A write outputs the value to the atidm port.</comment>
        </bits>
      </reg>
      <reg name="itatbctr0" protect="rw">
        <bits access="rw" name="atbytes" pos="9:8" rst="0">
          <comment>A read returns the value of the atbytessn signal, where the value of the Ctrl_Reg at 0x000 defines n.
A write outputs the value to atbytesm.</comment>
        </bits>
        <bits access="rw" name="afready" pos="1" rst="0">
          <comment>A read returns the value of the afreadysn signal, where the value of the Ctrl_Reg at 0x000 defines
n.
A write outputs the value to afreadym.</comment>
        </bits>
        <bits access="rw" name="atvalid" pos="0" rst="0">
          <comment>A read returns the value of the atvalidsn signal, where the value of the Ctrl_Reg at 0x000 defines n.
A write outputs the value to atvalidm.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="itctrl" protect="rw">
        <bits access="rw" name="ime" pos="0" rst="0">
          <comment>Integration Mode Enable.
0 Disable integration mode.
1 Enable integration mode.</comment>
        </bits>
      </reg>
      <hole size="1248"/>
      <reg name="claimset" protect="rw">
        <bits access="rw" name="set" pos="3:0" rst="15">
          <comment>On reads, for each bit:
1 Claim tag bit is implemented
On writes, for each bit:
0 Has no effect.
1 Sets the relevant bit of the claim tag.</comment>
        </bits>
      </reg>
      <reg name="claimclr" protect="rw">
        <bits access="w" name="clr" pos="3:0" rst="0">
          <comment>On reads, for each bit:
0 Claim tag bit is not set.
1 Claim tag bit is set.
On writes, for each bit:
0 Has no effect.
1 Clears the relevant bit of the claim tag.</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="lockaccess" protect="r">
        <bits access="r" name="key" pos="31:0" rst="0">
          <comment>Software lock key value.
0xC5ACCE55 Clear the software lock.
All other write values set the software lock.</comment>
        </bits>
      </reg>
      <reg name="lockstatus" protect="r">
        <bits access="r" name="ntt" pos="2" rst="0">
          <comment>Register size indicator. Always 0. Indicates that the LAR is implemented as 32-bit.</comment>
        </bits>
        <bits access="r" name="slk" pos="1" rst="1">
          <comment>0 Indicates that write operations are permitted from this interface.
1 Indicates that write operations are not permitted from this interface. Read
operations are permitted.</comment>
        </bits>
        <bits access="r" name="sli" pos="0" rst="1">
          <comment>Software Lock Implemented. Indicates that a lock control mechanism is present from this
interface.
0 Indicates that a lock control mechanism is not present from this interface. Write
operations to the LAR are ignored.
1 Indicates that a lock control mechanism is present from this interface</comment>
        </bits>
      </reg>
      <reg name="authstatus" protect="rw">
        <bits access="rw" name="snid" pos="7:6" rst="0">
          <comment>Always 0b00. The security level for Secure non-invasive debug is not implemented or is controlled
elsewhere.</comment>
        </bits>
        <bits access="rw" name="sid" pos="5:4" rst="1">
          <comment>Always 0b00 Secure invasive debug is not implemented or is controlled elsewhere.</comment>
        </bits>
        <bits access="rw" name="nsnid" pos="3:2" rst="1">
          <comment>Indicates the security level for Non-secure non-invasive debug:
0b10 Disabled.
0b11 Enabled.</comment>
        </bits>
        <bits access="rw" name="nsid" pos="1:0" rst="1">
          <comment>Indicates the security level for Non-secure invasive debug:
0b10 Disabled.
0b11 Enabled.</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="devid" protect="r">
        <bits access="r" name="scheme" pos="7:4" rst="3">
          <comment>Indicates the priority scheme implemented in this component.
0b0011 Program the slave ports to have higher or lower priority with respect to each other.</comment>
        </bits>
        <bits access="r" name="portcount" pos="3:0" rst="8">
          <comment>Indicates the number of input ports connected. 0x0 and 0x1 are illegal values.
0b0010 Two ATB slave ports.
0b0011 Three ATB slave ports.
0b0100 Four ATB slave ports.
0b0101 Five ATB slave ports.
0b0110 Six ATB slave ports.
0b0111 Seven ATB slave ports.
0b1000 Eight ATB slave ports.</comment>
        </bits>
      </reg>
      <reg name="devtype" protect="r">
        <bits access="r" name="sub" pos="7:4" rst="1">
          <comment>Sub-classification of the type of the debug component as specified in the ARM? CoreSight?
Architecture Specification within the major classification as specified in the MAJOR field:
0b0001 This component arbitrates ATB inputs mapping to ATB outputs.</comment>
        </bits>
        <bits access="r" name="major" pos="3:0" rst="2">
          <comment>Major classification of the type of the debug component as specified in the ARM? CoreSight?
Architecture Specification for this debug and trace component:
0b0010 This component has both ATB inputs and ATB outputs.</comment>
        </bits>
      </reg>
      <reg name="pidr4" protect="r">
        <bits access="r" name="size" pos="7:4" rst="0">
          <comment>Always 0b0000. Indicates that the device only occupies 4KB of memory.</comment>
        </bits>
        <bits access="r" name="des_2" pos="3:0" rst="4">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b0100 JEDEC continuation code.</comment>
        </bits>
      </reg>
      <reg name="pidr5" protect="r">
      </reg>
      <reg name="pidr6" protect="r">
      </reg>
      <reg name="pidr7" protect="r">
      </reg>
      <reg name="pidr0" protect="r">
        <bits access="r" name="part_0" pos="7:0" rst="8">
          <comment>Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this
part number.
0x08 Indicates bits[7:0] of the part number of the component.</comment>
        </bits>
      </reg>
      <reg name="pidr1" protect="r">
        <bits access="r" name="des_0" pos="7:4" rst="11">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code.</comment>
        </bits>
        <bits access="r" name="part_0" pos="3:0" rst="9">
          <comment>Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this
part number.
0b1001 Indicates bits[11:8] of the part number of the component.</comment>
        </bits>
      </reg>
      <reg name="pidr2" protect="r">
        <bits access="r" name="revision" pos="7:4" rst="3">
          <comment>0b0011, This device is at r1p1.</comment>
        </bits>
        <bits access="r" name="jedec" pos="3" rst="1">
          <comment>Always 1. Indicates that a JEDEC assigned value is used.</comment>
        </bits>
        <bits access="r" name="des_1" pos="2:0" rst="3">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code.</comment>
        </bits>
      </reg>
      <reg name="pidr3" protect="r">
        <bits access="r" name="revand" pos="7:4" rst="0">
          <comment>Indicates minor errata fixes specific to the revision of the component being used, for example
metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the
component designers ensure that a metal fix can change this field if required, for example, by
driving it from registers that reset to 0b0000.
0b0000 Indicates that there are no errata fixes to this component.</comment>
        </bits>
        <bits access="r" name="cmod" pos="3:0" rst="0">
          <comment>Customer Modified. Indicates whether the customer has modified the behavior of the component.
In most cases, this field is 0b0000. Customers change this value when they make authorized
modifications to this component.
0b0000 Indicates that the customer has not modified this component.</comment>
        </bits>
      </reg>
      <reg name="cidr0" protect="r">
        <bits access="r" name="prmbl_0" pos="7:0" rst="13">
          <comment>Preamble[0]. Contains bits[7:0] of the component identification code.
0x0D Bits[7:0] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr1" protect="r">
        <bits access="r" name="class" pos="7:4" rst="9">
          <comment>Class of the component, for example, whether the component is a ROM table or a generic
CoreSight SoC-400 component. Contains bits[15:12] of the component identification code.
0b1001 Indicates that the component is a CoreSight SoC-400 component.</comment>
        </bits>
        <bits access="r" name="prmbl_1" pos="3:0" rst="0">
          <comment>Preamble[1]. Contains bits[11:8] of the component identification code.
0b0000 Bits[11:8] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr2" protect="r">
        <bits access="r" name="prmbl_2" pos="7:0" rst="5">
          <comment>Preamble[2]. Contains bits[23:16] of the component identification code.
0x05 Bits[23:16] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr3" protect="r">
        <bits access="r" name="prmbl_3" pos="7:0" rst="177">
          <comment>Preamble[3]. Contains bits[31:24] of the component
identification code.
0xB1 Bits[31:24] of the identification code.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="timestamp.xml">
    <module category="Debug" name="TIMESTAMP">
      <reg name="cntcr" protect="rw">
        <bits access="rw" name="hdbg" pos="1" rst="0">
          <comment>Halt on Debug.
0 Do not halt on debug, HLTDBG signal into the counter has no
effect.
1 Halt on debug, when HLTDBG is driven HIGH, the count value is
held static.</comment>
        </bits>
        <bits access="rw" name="en" pos="0" rst="0">
          <comment>Enable.
0 The counter is disabled and not incrementing.
1 The counter is enabled and is incrementing.</comment>
        </bits>
      </reg>
      <reg name="cntsr" protect="r">
        <bits access="r" name="dbgh" pos="1" rst="0">
          <comment>Debug Halted.</comment>
        </bits>
      </reg>
      <reg name="cntcvl" protect="rw">
        <bits access="rw" name="cntcvl_l_32" pos="31:0" rst="0">
          <comment>Current value of the timestamp counter, lower 32 bits. To change the current timestamp value,
write the lower 32 bits of the new value to this register before writing the upper 32 bits to
CNTCVU. The timestamp value is not changed until the CNTCVU register is written to.</comment>
        </bits>
      </reg>
      <reg name="cntcvu" protect="rw">
        <bits access="rw" name="cntcvl_u_32" pos="31:0" rst="0">
          <comment>Current value of the timestamp counter, upper 32 bits. To change the current timestamp value,
write the lower 32 bits of the new value to CNTCVL before writing the upper 32 bits to this
register. The 64-bit timestamp value is updated with the value from both writes when this register
is written to.</comment>
        </bits>
      </reg>
      <hole size="128"/>
      <reg name="cntfid0" protect="rw">
        <bits access="rw" name="freq" pos="31:0" rst="0">
          <comment>Frequency in number of ticks per second. You can specify up to 4GHz.</comment>
        </bits>
      </reg>
      <hole size="32096"/>
      <reg name="pidr4" protect="r">
        <bits access="r" name="size" pos="7:4" rst="0">
          <comment>Always 0b0000. Indicates that the device only occupies 4KB of memory.</comment>
        </bits>
        <bits access="r" name="des_2" pos="3:0" rst="4">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b0100 JEDEC continuation code.</comment>
        </bits>
      </reg>
      <reg name="pidr5" protect="r">
      </reg>
      <reg name="pidr6" protect="r">
      </reg>
      <reg name="pidr7" protect="r">
      </reg>
      <reg name="pidr0" protect="r">
        <bits access="r" name="part_0" pos="7:0" rst="1">
          <comment>Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number.
0x01 Indicates bits[7:0] of the part number of the component.</comment>
        </bits>
      </reg>
      <reg name="pidr1" protect="r">
        <bits access="r" name="des_0" pos="7:4" rst="11">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the
component.
0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code.</comment>
        </bits>
        <bits access="r" name="part_1" pos="3:0" rst="1">
          <comment>Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number.
0b0001 Indicates bits[11:8] of the part number of the component.</comment>
        </bits>
      </reg>
      <reg name="pidr2" protect="r">
        <bits access="r" name="revision" pos="7:4" rst="1">
          <comment>0b0001 This device is at r0p1.</comment>
        </bits>
        <bits access="r" name="jedec" pos="3" rst="1">
          <comment>Always 1. Indicates that a JEDEC assigned value is used.</comment>
        </bits>
        <bits access="r" name="des_1" pos="2:0" rst="3">
          <comment>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.
0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code.</comment>
        </bits>
      </reg>
      <reg name="pidr3" protect="r">
        <bits access="r" name="revand" pos="7:4" rst="0">
          <comment>Indicates minor errata fixes specific to the revision of the component being used, for example
metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the
component designers ensure that a metal fix can change this field if required, for example, by
driving it from registers that reset to 0b0000.
0b0000 Indicates that there are no errata fixes to this component.</comment>
        </bits>
        <bits access="r" name="cmod" pos="3:0" rst="0">
          <comment>Customer Modified. Indicates whether the customer has modified the behavior of the component.
In most cases, this field is 0b0000. Customers change this value when they make authorized
modifications to this component.
0b0000 Indicates that the customer has not modified this component.</comment>
        </bits>
      </reg>
      <reg name="cidr0" protect="r">
        <bits access="r" name="prmbl_0" pos="7:0" rst="13">
          <comment>Preamble[0]. Contains bits[7:0] of the component identification code.
0x0D Bits[7:0] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr1" protect="r">
        <bits access="r" name="class" pos="7:4" rst="9">
          <comment>Class of the component, for example, whether the component is a ROM table or a generic
CoreSight SoC-400 component. Contains bits[15:12] of the component identification code.
0b1001 Indicates that the component is a CoreSight SoC-400 component.</comment>
        </bits>
        <bits access="r" name="prmbl_1" pos="3:0" rst="0">
          <comment>Preamble[1]. Contains bits[11:8] of the component identification code.
0b0000 Bits[11:8] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr2" protect="r">
        <bits access="r" name="prmbl_2" pos="7:0" rst="5">
          <comment>Preamble[2]. Contains bits[23:16] of the component identification code.
0x05 Bits[23:16] of the identification code.</comment>
        </bits>
      </reg>
      <reg name="cidr3" protect="r">
        <bits access="r" name="prmbl_3" pos="7:0" rst="177">
          <comment>Preamble[3]. Contains bits[31:24] of the component
identification code.
0xB1 Bits[31:24] of the identification code.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_zsp_uart.xml">
    <module category="Periph" name="CP_ZSP_UART">
      <reg name="uart_tx" protect="rw">
        <bits access="rw" name="tx_data" pos="31:0" rst="0">
          <comment>transmit data register</comment>
        </bits>
      </reg>
      <reg name="uart_rx" protect="r">
        <bits access="r" name="rx_data" pos="7:0" rst="0">
          <comment>receive data register</comment>
        </bits>
      </reg>
      <reg name="uart_baud" protect="rw">
        <bits access="rw" name="baud_const" pos="13:10" rst="15">
          <comment>baud rate divider constant N:  (N&gt;=4)
0011:  N=4
...
0111:  N=8
...
1111:  N=16</comment>
        </bits>
        <bits access="rw" name="baud_div" pos="9:0" rst="13">
          <comment>baud rate divider coeffcientbaud rate formula is:
BAUD RATE = Fclk/(Nx(BAUD_DIV+1))
default baud rate is 115.2K, N=16, Ffun=26MHz.</comment>
        </bits>
      </reg>
      <reg name="uart_conf" protect="rw">
        <bits access="rw" name="tx_endian" pos="12" rst="0">
          <comment>choose big or little endian
0: little endian
1: big endian</comment>
        </bits>
        <bits access="rw" name="rxrst" pos="11" rst="0">
          <comment>RX FIFO reset control
1:  RX FIFO reset
0:  RX FIFO not reset; or set 1'b1, auto clear to 1'b0</comment>
        </bits>
        <bits access="rw" name="txrst" pos="10" rst="0">
          <comment>TX FIFO reset control
1:  TX FIFO reset
0:  TX FIFO not reset;or set to 1'b1,auto clear to 1'b0</comment>
        </bits>
        <bits access="rw" name="tout_hwfc" pos="9" rst="0">
          <comment>after RX timeout, enable hardware flow control (on condition that HWFC is enable)
1:  after RX timeout,enable hardware flow control. Do not accept data until the timeout bit has been cleared, so that disable the hardware flow control
0:  after RX timeout, disable hardware flow control</comment>
        </bits>
        <bits access="rw" name="rx_trig_hwfc" pos="8" rst="0">
          <comment>RX trigger RTS enable control (on condition that HWFC is enable)
1:  enable RX TRIG trigger RTS flow signal
0:  disable RX TRIG trigger RTS flow signal</comment>
        </bits>
        <bits access="rw" name="hwfc" pos="7" rst="1">
          <comment>hardware flow control bit
1:  enable
0:  disable</comment>
        </bits>
        <bits access="rw" name="tout_ie" pos="6" rst="0">
          <comment>RX timeout interrupt control bit
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="tx_ie" pos="5" rst="0">
          <comment>TX data interrupt control bit
1: enable TX interrupt
0: disable TX interrupt</comment>
        </bits>
        <bits access="rw" name="rx_ie" pos="4" rst="0">
          <comment>RX data interrupt control bit
1: enable RX interrupt
0: disable RX interrupt</comment>
        </bits>
        <bits access="rw" name="st_check" pos="3" rst="0">
          <comment>stop bit detection control bit
1: enable stop bit detection
0: disable stop bit detection</comment>
        </bits>
        <bits access="rw" name="stop_bit" pos="2" rst="1">
          <comment>stop bit control bit
1: 2bit stop bit
0: 1bit stop bit</comment>
        </bits>
        <bits access="rw" name="parity" pos="1" rst="0">
          <comment>check bit
1: odd check
0: even check</comment>
        </bits>
        <bits access="rw" name="check" pos="0" rst="0">
          <comment>check bit enable or not
1: enable
0: disable</comment>
        </bits>
      </reg>
      <reg name="uart_txtrig" protect="rw">
        <bits access="rw" name="tx_trig" pos="7:0" rst="0">
          <comment>TX FIFO trigger setting
00000000: 0 byte trigger
00000001: 1 byte trigger
00000010: 2 bytes trigger
00000011: 3 bytes trigger
00000100: 4 bytes trigger
01111110: 126bytes trigger
01111111: 127bytes trigger
10000000: don't trigger</comment>
        </bits>
      </reg>
      <reg name="uart_rxtrig" protect="rw">
        <bits access="rw" name="rx_trig" pos="7:0" rst="1">
          <comment>RX FIFO trigger settings
00000000: don't trigger
00000001: 1 byte trigger
00000010: 2 bytes trigger
00000011: 3 bytes trigger
00000100: 4 bytes trigger
01111111: 127bytes trigger
10000000: 128bytes trigger</comment>
        </bits>
      </reg>
      <reg name="uart_delay" protect="rw">
        <bits access="rw" name="two_tx_delay" pos="11:8" rst="0">
          <comment>configure the time interval between sending data twice
0000:  interval 0 baud rate clock
0001:  interval 1 baud rate clock
1111:  interval 15 baud rate clock</comment>
        </bits>
        <bits access="rw" name="toutcnt" pos="7:0" rst="43">
          <comment>configure the threshold value of the UART timeout interrupt counter
00000000:  configure the initial value of 0 baud rate clock
00000001:  configure the initial value of 1 baud rate clock
00000010:  configure the initial value of  2 baud rate clock
11111111:  configure the initial value of 255 baud rate clock</comment>
        </bits>
      </reg>
      <reg name="uart_status" protect="rw">
        <bits access="rc" name="rts" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.
          request to send status bit
1: prohibit far-end to send
0: request far-end to send</comment>
        </bits>
        <bits access="rc" name="cts" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.
          clear the sending status bit
1: prohibit home terminal to send
0: allow home terminal to send</comment>
        </bits>
        <bits access="rc" name="st_error" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the received data stop bit state
1: stop bit error
0: stop bit right</comment>
        </bits>
        <bits access="rc" name="p_error" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          RX data parity status
1: parity error
0:  parity right</comment>
        </bits>
        <bits access="rc" name="timeout_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          RX data timeout interrupt status bit
1: timeout
0: not timeout</comment>
        </bits>
        <bits access="rc" name="rx_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          RX data interrupt status bit
1: RX_FIFO_CNTRX_TRIG
0: RX_FIFO_CNT&lt;RX_TRIG</comment>
        </bits>
        <bits access="rc" name="tx_int" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          TX data interrupt status bit
1: TX_FIFO_CNT TX_TRIG
0: TX_FIFO_CNT &gt;TX_TRIG</comment>
        </bits>
      </reg>
      <reg name="uart_txfifo_stat" protect="r">
        <bits access="r" name="tx_fifo_cnt" pos="7:0" rst="0">
          <comment>TX FIFO data number
00000000: TX FIFO has 0 data
00000001: TX FIFO has 1 data
01111111: TX FIFO has 127 data
10000000: TX FIFO has 128 data</comment>
        </bits>
      </reg>
      <reg name="uart_rxfifo_stat" protect="r">
        <bits access="r" name="rx_fifo_cnt" pos="7:0" rst="0">
          <comment>RX FIFO data number
00000000: RX FIFO has 0 data
00000001: RX FIFO has 1 data
01111111: RX FIFO has 127 data
10000000: RX FIFO has 128 data</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_adc.xml">
    <module category="RDA2720M" name="RDA2720M_ADC">
      <reg name="adc_version" protect="r">
        <bits access="r" name="auxadc_version" pos="15:0" rst="1536">
          <comment>IP version r6p0</comment>
        </bits>
      </reg>
      <reg name="adc_cfg_ctrl" protect="rw">
        <bits access="rw" name="adc_offset_cal_en" pos="12" rst="0">
          <comment>Auxadc offset function enable 0: disable offset calibration function 1: enable offset calibration function When set 1, the adc inner offset is calibrated and not include in output data</comment>
        </bits>
        <bits access="rw" name="rg_auxad_average" pos="10:8" rst="1">
          <comment>auxadc convert data out average control: 000: disable adc average, output 12bit data and valid after once conversion; 001: adc convert twice and output the average data; 010: adc convert 4 times and output the average data; 011: adc convert 8 times and output the average data; 100: adc convert 16 times and output the average data; 101: adc convert 32 times and output the average data; 110: adc convert 64 times and output the average data; 111: adc convert 128 times and output the average data;</comment>
        </bits>
        <bits access="rw" name="sw_ch_run_num" pos="7:4" rst="0">
          <comment>the number of SW channel accessing, N+1.</comment>
        </bits>
        <bits access="rw" name="adc_12b" pos="2" rst="1">
          <comment>No use, reserved</comment>
        </bits>
        <bits access="rw" name="sw_ch_run" pos="1" rst="0">
          <comment>SW channel run, Write 1 to run a SW channel accessing, it is cleared by HW.</comment>
        </bits>
        <bits access="rw" name="adc_en" pos="0" rst="0">
          <comment>ADC global enable, 0: ADC module disable; 1: ADC module enable.</comment>
        </bits>
      </reg>
      <reg name="adc_sw_ch_cfg" protect="rw">
        <bits access="rw" name="adc_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.6.6.3 Application note</comment>
        </bits>
        <bits access="rw" name="adc_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="adc_cs" pos="4:0" rst="0">
          <comment>ADC software config channel ID. ADC software config channel ID. 4h0:for BAT_DET 4h1:for general ADCI1 4h2:for general ADCI2 4h3:for general ADCI3 5h4: for general ADCI4 5h5: for VBAT_SENSE 5h6: no use 5h7 TYPEC_CC1 5h8 for THM sensor 5h9: for TYPEC_CC2 5hA-5hC: no use 5hD: for DCDC_CALOUT 5hE, for VCHGSEN 5hF, for VCHG_BG 5h10, for PROG2ADC 5h11, 5h12: no use 5h13: for SD_AVDD 5h14: for AUDIO_HEADMIC 5h15: for LDO_CALOUT0 5h16: for LDO_CALOUT1 5h17: for LDO_CALOUT2 5h18-5h1C: no use 5h1D: for DAC self offset calibretion 5h1E: for DP 5h1F: for DM</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch0_cfg" protect="rw">
        <bits access="rw" name="frq_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="frq_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="frq_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="frq_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch1_cfg" protect="rw">
        <bits access="rw" name="frq_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="frq_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="frq_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="frq_cs" pos="4:0" rst="0">
          <comment>ADC channel ID</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch2_cfg" protect="rw">
        <bits access="rw" name="frq_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="frq_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="frq_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="frq_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch3_cfg" protect="rw">
        <bits access="rw" name="frq_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="frq_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="frq_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="frq_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch4_cfg" protect="rw">
        <bits access="rw" name="frq_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="frq_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="frq_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="frq_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch5_cfg" protect="rw">
        <bits access="rw" name="frq_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see Application note</comment>
        </bits>
        <bits access="rw" name="frq_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="frq_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="frq_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch6_cfg" protect="rw">
        <bits access="rw" name="frq_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="frq_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="frq_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="frq_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch7_cfg" protect="rw">
        <bits access="rw" name="frq_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="frq_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="frq_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="frq_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_slow_hw_ch0_cfg" protect="rw">
        <bits access="rw" name="req_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="req_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="req_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="req_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_slow_hw_ch1_cfg" protect="rw">
        <bits access="rw" name="req_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="req_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="req_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="req_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_slow_hw_ch2_cfg" protect="rw">
        <bits access="rw" name="req_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="req_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="req_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="req_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_slow_hw_ch3_cfg" protect="rw">
        <bits access="rw" name="req_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="req_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="req_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="req_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_slow_hw_ch4_cfg" protect="rw">
        <bits access="rw" name="req_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="req_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="req_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="req_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_slow_hw_ch5_cfg" protect="rw">
        <bits access="rw" name="req_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="req_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="req_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="req_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_slow_hw_ch6_cfg" protect="rw">
        <bits access="rw" name="req_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="req_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="req_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="req_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_slow_hw_ch7_cfg" protect="rw">
        <bits access="rw" name="req_scale" pos="10:9" rst="0">
          <comment>ADC scale setting for current ADC channel, more detail see 7.7.6 Application note</comment>
        </bits>
        <bits access="rw" name="req_delay_en" pos="7" rst="0">
          <comment>current channel delay enable, 0-diable; 1-enable.</comment>
        </bits>
        <bits access="rw" name="req_slow" pos="6" rst="0">
          <comment>ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks.</comment>
        </bits>
        <bits access="rw" name="req_cs" pos="4:0" rst="0">
          <comment>ADC channel ID Same as ADC_SW_CH_CFG adc_cs</comment>
        </bits>
      </reg>
      <reg name="adc_hw_ch_delay" protect="rw">
        <bits access="rw" name="hw_ch_delay" pos="7:0" rst="0">
          <comment>ADC HW channel accessing delay, its unit is ADC clock. It can be use for signal without enough setup time</comment>
        </bits>
      </reg>
      <reg name="adc_dat" protect="r">
        <bits access="r" name="adc_dat" pos="11:0" rst="0">
          <comment>ADC conversion result. When with one more result, each read gets one result.</comment>
        </bits>
      </reg>
      <reg name="adc_cfg_int_en" protect="rw">
        <bits access="rw" name="adc_irq_en" pos="0" rst="0">
          <comment>ADC interrupt enable, 0: interrupt disable; 1: interrupt enable.</comment>
        </bits>
      </reg>
      <reg name="adc_cfg_int_clr" protect="rw">
        <bits access="w" name="adc_irq_clr" pos="0" rst="0">
          <comment>ADC interrupt clear. Write &quot;1&quot; to clear.</comment>
        </bits>
      </reg>
      <reg name="adc_cfg_int_sts" protect="r">
        <bits access="r" name="adc_irq_sts" pos="0" rst="0">
          <comment>ADC masked interrupt.</comment>
        </bits>
      </reg>
      <reg name="adc_cfg_int_raw" protect="r">
        <bits access="r" name="adc_irq_raw" pos="0" rst="0">
          <comment>ADC raw interrupt.</comment>
        </bits>
      </reg>
      <reg name="adc_debug" protect="r">
        <bits access="r" name="adc_dbg_ch" pos="15:11" rst="31">
          <comment>Current accessing channel, 0~7: fast HW channel 0~7; 8: SW channel; 9~16: slow HW channel 0~7; 31: NO request;</comment>
        </bits>
        <bits access="r" name="adc_dbg_state" pos="10:8" rst="0">
          <comment>ADC state machine status, 0: idle; 1: fast HW req; 2: SW req; 3: slow HW req; 4: fast HW wait; 5: slow HW wait; Others: reserved</comment>
        </bits>
        <bits access="r" name="adc_dbg_cnt" pos="7:0" rst="0">
          <comment>ADC internal counter status, 0: idle; 1~n: work or wait counter;</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_timer_en" protect="rw">
        <bits access="rw" name="adc_fast_hw_ch7_timer_en" pos="7" rst="0">
          <comment>ADC fast HW channel7 timer enable, 0: disable; 1: enable;</comment>
        </bits>
        <bits access="rw" name="adc_fast_hw_ch6_timer_en" pos="6" rst="0">
          <comment>ADC fast HW channel6 timer enable, 0: disable; 1: enable;</comment>
        </bits>
        <bits access="rw" name="adc_fast_hw_ch5_timer_en" pos="5" rst="0">
          <comment>ADC fast HW channel5 timer enable, 0: disable; 1: enable;</comment>
        </bits>
        <bits access="rw" name="adc_fast_hw_ch4_timer_en" pos="4" rst="0">
          <comment>ADC fast HW channel4 timer enable, 0: disable; 1: enable;</comment>
        </bits>
        <bits access="rw" name="adc_fast_hw_ch3_timer_en" pos="3" rst="0">
          <comment>ADC fast HW channel3 timer enable, 0: disable; 1: enable;</comment>
        </bits>
        <bits access="rw" name="adc_fast_hw_ch2_timer_en" pos="2" rst="0">
          <comment>ADC fast HW channel2 timer enable, 0: disable; 1: enable;</comment>
        </bits>
        <bits access="rw" name="adc_fast_hw_ch1_timer_en" pos="1" rst="0">
          <comment>ADC fast HW channel1 timer enable, 0: disable; 1: enable;</comment>
        </bits>
        <bits access="rw" name="adc_fast_hw_ch0_timer_en" pos="0" rst="0">
          <comment>ADC fast HW channel0 timer enable, 0: disable; 1: enable;</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_timer_div" protect="rw">
        <bits access="rw" name="adc_fast_hw_timer_div" pos="15:0" rst="0">
          <comment>ADC fast HW channel timer working clock divider</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch0_timer_thresh" protect="rw">
        <bits access="rw" name="adc_fast_hw_ch0_timer_thresh" pos="15:0" rst="0">
          <comment>ADC fast HW channel0 timer  threshold</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch1_timer_thresh" protect="rw">
        <bits access="rw" name="adc_fast_hw_ch1_timer_thresh" pos="15:0" rst="0">
          <comment>ADC fast HW channel1 timer  threshold</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch2_timer_thresh" protect="rw">
        <bits access="rw" name="adc_fast_hw_ch2_timer_thresh" pos="15:0" rst="0">
          <comment>ADC fast HW channel2 timer  threshold</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch3_timer_thresh" protect="rw">
        <bits access="rw" name="adc_fast_hw_ch3_timer_thresh" pos="15:0" rst="0">
          <comment>ADC fast HW channel3 timer  threshold</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch4_timer_thresh" protect="rw">
        <bits access="rw" name="adc_fast_hw_ch4_timer_thresh" pos="15:0" rst="0">
          <comment>ADC fast HW channel4 timer  threshold</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch5_timer_thresh" protect="rw">
        <bits access="rw" name="adc_fast_hw_ch5_timer_thresh" pos="15:0" rst="0">
          <comment>ADC fast HW channel5 timer  threshold</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch6_timer_thresh" protect="rw">
        <bits access="rw" name="adc_fast_hw_ch6_timer_thresh" pos="15:0" rst="0">
          <comment>ADC fast HW channel6 timer  threshold</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch7_timer_thresh" protect="rw">
        <bits access="rw" name="adc_fast_hw_ch7_timer_thresh" pos="15:0" rst="0">
          <comment>ADC fast HW channel7 timer  threshold</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch0_dat" protect="r">
        <bits access="r" name="adc_fast_hw_ch0_dat" pos="11:0" rst="0">
          <comment>ADC fast HW channel0 data</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch1_dat" protect="r">
        <bits access="r" name="adc_fast_hw_ch1_dat" pos="11:0" rst="0">
          <comment>ADC fast HW channel1 data</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch2_dat" protect="r">
        <bits access="r" name="adc_fast_hw_ch2_dat" pos="11:0" rst="0">
          <comment>ADC fast HW channel2 data</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch3_dat" protect="r">
        <bits access="r" name="adc_fast_hw_ch3_dat" pos="11:0" rst="0">
          <comment>ADC fast HW channel3 data</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch4_dat" protect="r">
        <bits access="r" name="adc_fast_hw_ch4_dat" pos="11:0" rst="0">
          <comment>ADC fast HW channel4 data</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch5_dat" protect="r">
        <bits access="r" name="adc_fast_hw_ch5_dat" pos="11:0" rst="0">
          <comment>ADC fast HW channel5 data</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch6_dat" protect="r">
        <bits access="r" name="adc_fast_hw_ch6_dat" pos="11:0" rst="0">
          <comment>ADC fast HW channel6 data</comment>
        </bits>
      </reg>
      <reg name="adc_fast_hw_ch7_dat" protect="r">
        <bits access="r" name="adc_fast_hw_ch7_dat" pos="11:0" rst="0">
          <comment>ADC fast HW channel7 data</comment>
        </bits>
      </reg>
      <reg name="auxad_ctl0" protect="rw">
        <bits access="rw" name="rg_auxad_ref_sel" pos="5" rst="0">
          <comment>output to analog 0: adc reference voltage is generated by local resister devider 1: adc reference voltage is direct from bandgap 1.25v voltage.</comment>
        </bits>
        <bits access="rw" name="rg_auxad_thm_cal" pos="4" rst="0">
          <comment>output to analog THM calibration enable signal, 0: disable THM calibration(default) 1: enable THM calibration, must set high 100us before AUXADC measure THM voltage and start the calibration</comment>
        </bits>
        <bits access="rw" name="rg_auxad_currentsen_en" pos="0" rst="0">
          <comment>output to analog Aux ADC current sense enable signal, active high, default 0.</comment>
        </bits>
      </reg>
      <reg name="auxad_ctl1" protect="r">
        <bits access="r" name="rg_adc_fast_hw_ch7_dvld" pos="7" rst="0">
          <comment>ADC fast HW channel7 data valid.</comment>
        </bits>
        <bits access="r" name="rg_adc_fast_hw_ch6_dvld" pos="6" rst="0">
          <comment>ADC fast HW channel6 data valid.</comment>
        </bits>
        <bits access="r" name="rg_adc_fast_hw_ch5_dvld" pos="5" rst="0">
          <comment>ADC fast HW channel5 data valid.</comment>
        </bits>
        <bits access="r" name="rg_adc_fast_hw_ch4_dvld" pos="4" rst="0">
          <comment>ADC fast HW channel4 data valid.</comment>
        </bits>
        <bits access="r" name="rg_adc_fast_hw_ch3_dvld" pos="3" rst="0">
          <comment>ADC fast HW channel3 data valid.</comment>
        </bits>
        <bits access="r" name="rg_adc_fast_hw_ch2_dvld" pos="2" rst="0">
          <comment>ADC fast HW channel2 data valid.</comment>
        </bits>
        <bits access="r" name="rg_adc_fast_hw_ch1_dvld" pos="1" rst="0">
          <comment>ADC fast HW channel1 data valid.</comment>
        </bits>
        <bits access="r" name="rg_adc_fast_hw_ch0_dvld" pos="0" rst="0">
          <comment>ADC fast HW channel0 data valid.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_aud.xml">
    <module category="RDA2720M" name="RDA2720M_AUD">
      <reg name="aud_cfga_clr" protect="rw">
        <bits access="rc" name="ear_shutdown_clr" pos="10" rst="0">
          <comment>bit type is changed from wc to rc.
          ear shut down clear</comment>
        </bits>
        <bits access="rc" name="hp_shutdown_clr" pos="9" rst="0">
          <comment>bit type is changed from wc to rc.
          hp shut down clear</comment>
        </bits>
        <bits access="rc" name="pa_shutdown_clr" pos="8" rst="0">
          <comment>bit type is changed from wc to rc.
          pa shut down clear</comment>
        </bits>
        <bits access="rc" name="aud_int_clr" pos="7:0" rst="0">
          <comment>bit type is changed from wc to rc.
          [7:0]={audio_rcv_depop,audio_pacal_irq,audio_hp_dpop_irq,ovp_irq,otp_irq,pa_ocp_irq,ear_ocp_irq,hp_ocp_irq}</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_hid_cfg0" protect="rw">
        <bits access="rw" name="aud_dbnc_en" pos="2:1" rst="0">
          <comment>[0]: audio HEAD_INSERT debounce enable [1]: audio HEAD_BUTTON_OUT debounce enable</comment>
        </bits>
        <bits access="rw" name="hid_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="aud_cfga_hid_cfg1" protect="rw">
        <bits access="rw" name="hid_high_dbnc_thd0" pos="15:8" rst="0">
          <comment>low debounce threshold(clock 1k), for HEAD_INSERT signal</comment>
        </bits>
        <bits access="rw" name="hid_low_dbnc_thd0" pos="7:0" rst="0">
          <comment>high debounce threshold(clock 1k), for HEAD_INSERT signal</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_hid_cfg2" protect="rw">
        <bits access="rw" name="hid_tmr_t1t2_step" pos="9:5" rst="0">
          <comment>head insert detect T1/T2 timer step (clock 1k)</comment>
        </bits>
        <bits access="rw" name="hid_tmr_t0" pos="4:0" rst="0">
          <comment>head insert detect T0 timer , (clock 1k)</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_hid_cfg3" protect="rw">
        <bits access="rw" name="hid_tmr_t1" pos="15:0" rst="0">
          <comment>head insert detect T1 timer ,step: HID_TMR_T1T2_STEP</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_hid_cfg4" protect="rw">
        <bits access="rw" name="hid_tmr_t2" pos="15:0" rst="0">
          <comment>head insert detect T2 timer ,step: HID_TMR_T1T2_STEP</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_hid_cfg5" protect="rw">
        <bits access="rw" name="hid_high_dbnc_thd1" pos="15:8" rst="0">
          <comment>low debounce threshold(clock 1k), for HEAD_BUTTON_OUT signal</comment>
        </bits>
        <bits access="rw" name="hid_low_dbnc_thd1" pos="7:0" rst="0">
          <comment>high debounce threshold(clock 1k), for HEAD_BUTTON_OUT signal</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_hid_sts0" protect="r">
        <bits access="r" name="ear_shutdown" pos="10" rst="0">
          <comment>ear_shutdown</comment>
        </bits>
        <bits access="r" name="hp_shutdown" pos="9" rst="0">
          <comment>hp_shutdown</comment>
        </bits>
        <bits access="r" name="pa_shutdown" pos="8" rst="0">
          <comment>pa_shutdown</comment>
        </bits>
        <bits access="r" name="audio_head_insert_out" pos="7" rst="0">
          <comment>head insert detect out: AUDIO_HEAD_INSERT_OUT state</comment>
        </bits>
        <bits access="r" name="audio_head_button_out" pos="6" rst="0">
          <comment>head button detect out : AUDIO_HEAD_BUTTON_OUT state</comment>
        </bits>
        <bits access="r" name="aud_dbnc_sts1" pos="5:3" rst="0">
          <comment>u1 debounce state machine  status</comment>
        </bits>
        <bits access="r" name="aud_dbnc_sts0" pos="2:0" rst="0">
          <comment>u0 debounce state machine  status</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_prt_cfg_0" protect="rw">
        <bits access="rw" name="ear_shutdown_en" pos="9" rst="0">
          <comment>ear_shutdown_enable</comment>
        </bits>
        <bits access="rw" name="hp_shutdown_en" pos="8" rst="0">
          <comment>hp_shutdown_enable</comment>
        </bits>
        <bits access="rw" name="pa_shutdown_en2" pos="7" rst="0">
          <comment>pa_shutdown_enable2</comment>
        </bits>
        <bits access="rw" name="pa_shutdown_en1" pos="6" rst="0">
          <comment>pa_shutdown_enable1</comment>
        </bits>
        <bits access="rw" name="pa_shutdown_en0" pos="5" rst="0">
          <comment>pa_shutdown_enable0</comment>
        </bits>
        <bits access="rw" name="aud_clk_sel" pos="4" rst="1">
          <comment>1:32k_clk 0:1k_clk</comment>
        </bits>
        <bits access="rw" name="aud_prt_en" pos="3" rst="0">
          <comment>protect enable</comment>
        </bits>
        <bits access="rw" name="otp_pd_thd" pos="2:0" rst="3">
          <comment>over-temperature protection threshold</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_prt_cfg_1" protect="rw">
        <bits access="rw" name="otp_precis" pos="14:12" rst="2">
          <comment>over-temperature protection precis</comment>
        </bits>
        <bits access="rw" name="ovp_pd_thd" pos="11:9" rst="2">
          <comment>overvoltage protection threshold</comment>
        </bits>
        <bits access="rw" name="ovp_precis" pos="8:6" rst="0">
          <comment>overvoltage protection precis</comment>
        </bits>
        <bits access="rw" name="ocp_pd_thd" pos="5:3" rst="3">
          <comment>overcurrent protection threshold</comment>
        </bits>
        <bits access="rw" name="ocp_precis" pos="2:0" rst="2">
          <comment>overcurrent protection precis</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_rd_sts" protect="r">
        <bits access="r" name="aud_irq_raw" pos="15:8" rst="0">
          <comment>int status: [7:0]={audio_rcv_depop,audio_pacal_irq,audio_hp_dpop_irq,ovp_irq,otp_irq,pa_ocp_irq,ear_ocp_irq,hp_ocp_irq}</comment>
        </bits>
        <bits access="r" name="aud_irq_msk" pos="7:0" rst="0">
          <comment>int mask = aud_irq_raw &amp; aud_int_en</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_int_module_ctrl" protect="rw">
        <bits access="rw" name="aud_int_en" pos="7:0" rst="0">
          <comment>int enable: [7:0]={audio_rcv_depop,audio_pacal_irq,audio_hp_dpop_irq,ovp_irq,otp_irq,pa_ocp_irq,ear_ocp_irq,hp_ocp_irq}</comment>
        </bits>
      </reg>
      <reg name="aud_cfga_lp_module_ctrl" protect="rw">
        <bits access="rw" name="adc_en_r" pos="5" rst="0">
          <comment>adc right enable</comment>
        </bits>
        <bits access="rw" name="dac_en_r" pos="4" rst="0">
          <comment>dac right enable</comment>
        </bits>
        <bits access="rw" name="adc_en_l" pos="3" rst="0">
          <comment>adc left enable</comment>
        </bits>
        <bits access="rw" name="dac_en_l" pos="2" rst="0">
          <comment>adc right enable</comment>
        </bits>
        <bits access="rw" name="audio_loop_map_sel" pos="1" rst="1">
      </bits>
        <bits access="rw" name="audio_adie_loop_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="ana_et2" protect="rw">
        <bits access="rw" name="dem_bypass" pos="4" rst="0">
          <comment>bypass DEM</comment>
        </bits>
        <bits access="rw" name="rg_aud_dalr_mix_sel" pos="3:2" rst="0">
          <comment>Audio DACL &amp; DACR output mixer select 00 = R/L         01 = R/0 10 = 0/L         11 = 0/0</comment>
        </bits>
        <bits access="rw" name="rg_aud_das_mix_sel" pos="1:0" rst="0">
          <comment>Audio DACL &amp; DACR output mixer select 00 = L + R       01 = 2 x L 10 = 2 x R       11 = 0</comment>
        </bits>
      </reg>
      <reg name="clk_en" protect="rw">
        <bits access="rw" name="clk_aud_loop_inv_en" pos="5" rst="0">
      </bits>
        <bits access="rw" name="clk_aud_6p5m_en" pos="4" rst="0">
      </bits>
        <bits access="rw" name="clk_aud_loop_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="clk_aud_hid_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="clk_aud_1k_en" pos="1" rst="0">
      </bits>
        <bits access="rw" name="clk_aud_32k_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="soft_rst" protect="rw">
        <bits access="rc" name="aud_dac_post_soft_rst" pos="5" rst="0">
          <comment>bit type is changed from wc to rc.</comment>
        </bits>
        <bits access="rc" name="aud_dig_6p5m_soft_rst" pos="4" rst="0">
          <comment>bit type is changed from wc to rc.</comment>
        </bits>
        <bits access="rc" name="aud_dig_loop_soft_rst" pos="3" rst="0">
          <comment>bit type is changed from wc to rc.</comment>
        </bits>
        <bits access="rc" name="aud_hid_soft_rst" pos="2" rst="0">
          <comment>bit type is changed from wc to rc.</comment>
        </bits>
        <bits access="rc" name="aud_1k_soft_rst" pos="1" rst="0">
          <comment>bit type is changed from wc to rc.</comment>
        </bits>
        <bits access="rc" name="aud_32k_soft_rst" pos="0" rst="0">
          <comment>bit type is changed from wc to rc.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_aud_codec.xml">
    <module category="RDA2720M" name="RDA2720M_AUD_CODEC">
      <reg name="ana_pmu0" protect="rw">
        <bits access="rw" name="rg_aud_vb_en" pos="15" rst="0">
          <comment>Audio LDO VB enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_vb_nleak_pd" pos="14" rst="0">
          <comment>Audio LDO VB prevent reverse flow back power down signal 0 = power up          1 = power down</comment>
        </bits>
        <bits access="rw" name="rg_aud_vb_hdmc_sp_pd" pos="13" rst="1">
          <comment>Audio LDO VB SLEEP MODE PD signal 0 = EN   1 = PD</comment>
        </bits>
        <bits access="rw" name="rg_aud_bg_en" pos="12" rst="0">
          <comment>Audio BG EN 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_bias_en" pos="11" rst="0">
          <comment>Audio BIAS EN 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_micbias_en" pos="10" rst="0">
          <comment>Audio Microphone bias enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_hmic_bias_en" pos="9" rst="0">
          <comment>Audio Headset Micbias enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_hmic_sleep_en" pos="8" rst="0">
          <comment>Audio HeadMic SLEEP MODE EN signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_mic_sleep_en" pos="7" rst="0">
          <comment>Audio  MIC SLEEP MODE EN signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_vbg_sel" pos="6" rst="0">
          <comment>Audio BG Voltage 0 :BG=1.55V         1: BG=1.5V</comment>
        </bits>
        <bits access="rw" name="rg_aud_vbg_temp_biastune" pos="5" rst="0">
          <comment>Audio BG Bias option 0 = normal          1 = debug mode</comment>
        </bits>
        <bits access="rw" name="rg_aud_vbg_temp_tune" pos="4:3" rst="0">
          <comment>Audio BG tune TC option 00: normal         01: TC reduce 10: TC reduce more   11: TC enhance</comment>
        </bits>
        <bits access="rw" name="rg_aud_micbias_plgb" pos="2" rst="1">
          <comment>Audio MICBIAS power down signal (do not control discharge circuit) 0 = power up          1 = power down</comment>
        </bits>
        <bits access="rw" name="rg_aud_hmicbias_vref_sel" pos="1" rst="0">
          <comment>Audio Headmic VREF 0 = main-BG         1 = AUD_BG</comment>
        </bits>
        <bits access="rw" name="rg_hmic_comp_mode1_en" pos="0" rst="0">
          <comment>HMIC_COMP_MODE_EN: 0 = disable           1 = headmicbias filter RC integrated in chip</comment>
        </bits>
      </reg>
      <reg name="ana_pmu1" protect="rw">
        <bits access="rw" name="rg_aud_vb_cal" pos="15:11" rst="16">
          <comment>Audio LDO_VB output voltage calibration signal 00000 = -13.3%       00001 = -12.5%        00010 = -11.7%        00011 = -10.8% 00100 = -10%        00101 = -9.2%        00110 = -8.4%        00111 = -7.5% 01000 = -6.7%        01001 = -5.8%        01010 =-5%        01011 = -4.2% 01100 = -3.3%        01101 = -2.5%        01110 = -1.67%        01111 = -0.83% 10000 = 0               10001 = 0.83%        10010 = 1.67%         10011 = 2.5% 10100 = 3.3%         10101 = 4.2%         10110 = 5%         10111 =5.8% 11000 = 6.7%         11001 = 7.5%         11010 = 8.4%         11011 = 9.2% 11100 = 10%         11101 = 10.8%         11110 = 11.7%         11111 = 12.5%</comment>
        </bits>
        <bits access="rw" name="rg_aud_vb_v" pos="10:6" rst="16">
          <comment>Audio ADC/DAC/DRV VCM &amp; LDO VB output voltage control bit (VB should be set larger than 3.0V) 00000 -00011 = forbidden 00100 = 3.0V        00101 = 3.025V        00110 = 3.05V        00111 = 3.075V 01000 = 3.1V        01001 = 3.125V        01010 =3.15V        01011 = 3.175V 01100 = 3.2V        01101 = 3.225V        01110 = 3.25V        01111 = 3.275V 10000 = 3.3V        10001 = 3.325V        10010 = 3.35V        10011 = 3.375V 10100 = 3.4V        10101 = 3.425V        10110 = 3.45V        10111 =3.475V 11000 = 3.5V        11001 = 3.525V        11010 = 3.55V        11011 = 3.575V 11100 = 3.6V        11101 - 11111 = forbidden</comment>
        </bits>
        <bits access="rw" name="rg_aud_hmic_bias_v" pos="5:3" rst="5">
          <comment>Audio headmicbias output voltage control bit 000 = 2.2V        001 = 2.4V        010 = 2.5V        011 = 2.6V 100 = 2.7V        101 = 2.8V        110 = 2.9V        111 = 3.0V</comment>
        </bits>
        <bits access="rw" name="rg_aud_micbias_v" pos="2:0" rst="2">
          <comment>Audio MICBIAS output voltage select signal 000 = 2.2V        001 = 2.4V        010 = 2.5V        011 = 2.6V 100 = 2.7V        101 = 2.8V        110 = 2.9V        111 = 3.0V</comment>
        </bits>
      </reg>
      <reg name="ana_pmu2" protect="rw">
        <bits access="rw" name="rg_aud_hp_ib" pos="15:14" rst="0">
          <comment>AUD HP-PGA BIAS current: 00:X1  11:X2</comment>
        </bits>
        <bits access="rw" name="rg_aud_hp_ibcur3" pos="13:11" rst="2">
          <comment>AUD HP-PGA 3rd stage BIAS current: 000: 5uA    001:7.5uA     010:10uA   011: 12.5uA 100: 15uA  101: 17.5uA  110:20uA   111: 22.5uA</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ab_i" pos="10:9" rst="1">
          <comment>Audio PA class-AB mode Quiescent current decreasing level 00=3.5mA, 01=2.5mA, 10=1.9mA, 11=1.6mA</comment>
        </bits>
        <bits access="rw" name="rg_aud_adpga_ibias_sel" pos="8:5" rst="0">
          <comment>Audio ADC &amp; PGA ibias current control bit &lt;3:2&gt; control the ibias of the PGA 00 = 10uA        01 = 7.5uA        10 = 5uA        11 = 5uA &lt;1:0&gt; control the ibias of the modulator 00 = 5uA        01 = 3.75uA        10 = 2.5uA        11 = 2.5uA</comment>
        </bits>
        <bits access="rw" name="rg_aud_da_ig" pos="4:3" rst="0">
          <comment>Audio DACL &amp; DACR output gain control bit 00 = 0dB            01 = -0.75dB       1x=-1.5dB</comment>
        </bits>
        <bits access="rw" name="rg_aud_drv_pm_sel" pos="2:1" rst="3">
          <comment>HP&amp;RCV DRV SEL 00:  input gm/2, miller cap cut 01:  input gm/2, miller cap normal 10:  input gm normal, miller cap cut 11:  input gm normal, miller cap normal</comment>
        </bits>
      </reg>
      <reg name="ana_pmu3" protect="rw">
        <bits access="rw" name="rg_aud_pa_otp_pd" pos="15" rst="1">
          <comment>Audio PA over temperature protection circuit power down signal 0 = power up     1 = power down</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_otp_t" pos="14:12" rst="6">
          <comment>Audio PA over temperature protection circuit temperature select 000: 4C -&gt; -14C     001: 25C -&gt; 8C 010: 47C -&gt; 31C         011: 68C -&gt; 52C 100: 89C -&gt; 74C         101: 110C -&gt; 95C 110: 130C -&gt; 115C      111: 150C -&gt; 135C</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ovp_pd" pos="11" rst="1">
          <comment>Audio VBAT_PA over voltage protection circuit power down signal 0 = power up          1 = power down</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ovp_thd" pos="10" rst="0">
          <comment>Audio VBAT_PA over voltage protection circuit threshold select 0 = 0.3V                1 = 0.6V</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ovp_v" pos="9:7" rst="0">
          <comment>Audio VBAT_PA over voltage protection circuit voltage select RG_AUD_PA_OVP_THD = 0/1 000 = 5.8 -&gt; 5.5/5.2       001 = 6.0 -&gt; 5.7/5.4 010 = 6.2 -&gt; 5.9/5.6        011 = 6.4 -&gt; 6.1/5.8 100 = 6.6 -&gt; 6.3/6.0        101 = 6.8 -&gt; 6.5/6.2 110 = 7.0 -&gt; 6.7/6.4  111 = 7.2 -&gt; 6.9/6.6</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ocp_pd" pos="6" rst="1">
          <comment>Audio PA over current protection circuit power down signal 0 = power up,1 = power down</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ocp_s" pos="5" rst="1">
          <comment>Audio PA class-AB mode over current protection circuit current select 0=800mA  1=1000mA</comment>
        </bits>
        <bits access="rw" name="rg_aud_drv_ocp_pd" pos="4" rst="1">
          <comment>Audio PA over current protection circuit power down signal 0 = power up,1 = power down</comment>
        </bits>
        <bits access="rw" name="rg_aud_drv_ocp_mode" pos="3:2" rst="0">
          <comment>Audio Driver over current protection current select HP mode: 00--108mA      01--150mA    10--156mA     11--195mA RCV mode: 00--209mA    01300mA  10310mA 11-- 400mA</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_vcm_v" pos="1:0" rst="1">
          <comment>Audio PA VCOM voltage control bit 00 = 0.55xVDD  01 = 0.5xVDD  10 = 0.45xVDD  11 = 0.4xVDD</comment>
        </bits>
      </reg>
      <reg name="ana_pmu4" protect="rw">
        <bits access="rw" name="rg_aud_pa_ksel" pos="14:13" rst="2">
          <comment>Audio PA class-D mode PWM Gain select 00 = 1                 01 = 1.5 10 = 1.67              11 = 2</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_degsel" pos="12:11" rst="1">
          <comment>Audio PA class-D mode PWM logic delay time select 00 = 7ns               01 = 14ns 10  =24ns             11 = 29ns</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_emi_l" pos="10:8" rst="0">
          <comment>Audio PA class-D output edge slew rate control 000 = 2ns       001 = 4ns      010 = 6ns       011 = 8ns 100 = 10ns     101=12ns      110 = 14ns      111 = 16ns</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ss_en" pos="7" rst="0">
          <comment>Audio PA class-D mode spread spectrum enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ss_rst" pos="6" rst="0">
          <comment>Audio PA class-D mode spread spectrum reset enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ss_f" pos="5:4" rst="0">
          <comment>Audio PA class-D mode spread spectrum dither level select signal when PA_DTRI_F&lt;1:0&gt; = 00/01/10/11 00 = 3.2%/1.6%/0.8%/0.4% 01 =   9%/4.7%/2.3%/1.2% 10 =  22%/ 11%/5.5%/2.7% 11 =  47%/ 23%/ 12%/  6%</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ss_32k_en" pos="3" rst="0">
          <comment>Audio PA class-D mode spread spectrum 32k dither clock select signal 0 = disable           1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ss_t" pos="2:0" rst="0">
          <comment>Audio PA class-D mode spread spectrum dither clock divider select signal 000 = 1           001 = 1/2          010 = 1/4          011 = 1/8 100 = 1/16        101 = 1/32         110 = 1/64        111 = 1/128</comment>
        </bits>
      </reg>
      <reg name="ana_pmu5" protect="rw">
        <bits access="rw" name="rg_aud_pa_d_en" pos="14" rst="0">
          <comment>Audio Speaker PA class-D mode enable signal 0 = disable (CLASS-AB mode)      1 = enable(CLASS-D mode)</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_dflck_en" pos="13" rst="0">
          <comment>Audio Speaker PA class-D mode switching frequency locking enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_dflck_rsl" pos="12" rst="0">
          <comment>Audio Speaker PA class-D mode switching frequency locking resolution select 0 = 1X                 1 = 2X</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_dtri_fc" pos="11:9" rst="2">
          <comment>Audio Speaker PA class-D mode switching frequency select 000 = 330kHz    001 = 490kHz      010 = 650KHz      011 = 810KHz 100 = 970kHz    101 = 1.12MHz    110 = 1.27MHz    111 = 1.42MHz</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_dtri_ff" pos="8:3" rst="0">
          <comment>Audio PA class-D mode Switching frequency hopping level 000000=0Hz             000001=1*2.5KHz      000010=2*2.5KHz      000011=3*2.5KHz 000100=4*2.5KHz     000101=5*2.5KHz      000110=6*2.5KHz      000111=7*2.5KHz 001000=8*2.5KHz    001001=9*2.5KHz      001010=10*2.5KHz    001011=11*2.5KHz 001100=12*2.5KHz    001101=13*2.5KHz    001110=14*2.5KHz    001111=15*2.5KHz 010000=16*2.5KHz    010001=17*2.5KHz    010010=18*2.5KHz    010011=19*2.5KHz 010100=20*2.5KHz 010101=21*2.5KHz    010110=22*2.5KHz    010111=23*2.5KHz 011000=24*2.5KHz    011001=25*2.5KHz    011010=26*2.5KHz    011011=27*2.5KHz 011100=28*2.5KHz    011101=29*2.5KHz    011110=30*2.5KHz    011111=31*2.5KHz 100000=32*2.5KHz 100001=33*2.5KHz    100010=34*2.5KHz    100011=35*2.5KHz 100100=36*2.5KHz    100101=37*2.5KHz    100110=38*2.5KHz    100111=39*2.5KHz 101000=40*2.5KHz    101001=41*2.5KHz    101010=42*2.5KHz    101011=43*2.5KHz 101100=44*2.5KHz 101101=45*2.5KHz    101110=46*2.5KHz    101111=47*2.5KHz 110000=48*2.5KHz    110001=49*2.5KHz    110010=50*2.5KHz    110011=51*2.5KHz 110100=52*2.5KHz    110101=53*2.5KHz    110110=54*2.5KHz    110111=55*2.5KHz 111000=56*2.5KHz 111001=57*2.5KHz    111010=58*2.5KHz    111011=59*2.5KHz 111100=60*2.5KHz    111101=61*2.5KHz    111110=62*2.5KHz    111111=63*2.5KHz</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_stop_en" pos="2" rst="0">
          <comment>Audio PA Driver stop output enable signal 0 = disable,  1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_sh_det_en" pos="1" rst="0">
          <comment>Audio PA output short to VBAT detect enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_sl_det_en" pos="0" rst="0">
          <comment>Audio PA output short to GND detect enable signal 0 = disable          1 = enable</comment>
        </bits>
      </reg>
      <reg name="ana_clk0" protect="rw">
        <bits access="rw" name="rg_aud_dig_clk_6p5m_en" pos="14" rst="0">
          <comment>Audio digital core clcok input enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_dig_clk_loop_en" pos="13" rst="0">
          <comment>Audio digital loop clcok input enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_ana_clk_en" pos="12" rst="0">
          <comment>Audio analog core clcok input enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_ad_clk_en" pos="11" rst="0">
          <comment>Audio analog ADC clock input enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_ad_clk_rst" pos="10" rst="1">
          <comment>Audio analog ADC clock reset enable signal 0 = EN          1 = RESET</comment>
        </bits>
        <bits access="rw" name="rg_aud_da_clk_en" pos="9" rst="0">
          <comment>Audio DAC clock input enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_drv_clk_en" pos="8" rst="0">
          <comment>Audio DRV clock input enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_dcdcgen_clk_en" pos="7" rst="0">
          <comment>Audio DCDC GEN clock input enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_dcdcmem_clk_en" pos="6" rst="0">
          <comment>Audio DCDC MEM clock input enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_dcdccore_clk_en" pos="5" rst="0">
          <comment>Audio DCDC CORE clock input enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_vad_en" pos="4" rst="0">
          <comment>Audio VAD enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_ad_clk_f" pos="3:2" rst="0">
          <comment>Audio ADC clock frequency select (based on Fclk=6.5MHz) 00 = Fclk            01 = Fclk / 2</comment>
        </bits>
        <bits access="rw" name="rg_aud_da_clk_f" pos="1:0" rst="0">
          <comment>Audio DAC clock frequency select (based on Fclk=6.5MHz) 00 = Fclk              01/11 = Fclk x 2 10 = Fclk / 2</comment>
        </bits>
      </reg>
      <reg name="ana_cdc0" protect="rw">
        <bits access="rw" name="rg_aud_adpga_ibias_en" pos="15" rst="0">
          <comment>Audio PGA&amp;ADC BIAS en signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_adpga_ibuf_en" pos="14" rst="0">
          <comment>Audio PGA &amp; ADC VCM buffer enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_adpgal_en" pos="13" rst="0">
          <comment>Audio ADC PGAL enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_adpgar_en" pos="12" rst="0">
          <comment>Audio ADC PGAR enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_adpgal_byp" pos="11:10" rst="0">
          <comment>Audio ADC PGAL bypass select signal 00 = normal input                 01 = HEADMIC to ADCL 10/11 = All disconnected</comment>
        </bits>
        <bits access="rw" name="rg_aud_adpgar_byp" pos="9:8" rst="0">
          <comment>Audio ADC PGAR bypass select signal 00 = normal input                 01 = HEADMIC to ADCR 10/11 = All disconnected</comment>
        </bits>
        <bits access="rw" name="rg_aud_adl_en" pos="7" rst="0">
          <comment>Audio ADCL enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_adl_rst" pos="6" rst="0">
          <comment>Audio ADCL reset enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_adr_en" pos="5" rst="0">
          <comment>Audio ADCR enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_adr_rst" pos="4" rst="0">
          <comment>Audio ADCR reset enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_vref_sfcur" pos="3" rst="0">
          <comment>Audio ADC VREF current drv increasing by 1.3 times enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_shmic_dpop" pos="2" rst="0">
          <comment>Headmic button release depop signal 0 = disable    1 = depop</comment>
        </bits>
        <bits access="rw" name="rg_aud_shmic_dpopvcm_en" pos="1" rst="0">
          <comment>Headmic button release depop signal to VCM enable 0 = disable    1 = depop</comment>
        </bits>
        <bits access="rw" name="rg_aud_adc_bulksw" pos="0" rst="0">
          <comment>Reserved</comment>
        </bits>
      </reg>
      <reg name="ana_cdc1" protect="rw">
        <bits access="rw" name="rg_aud_advcmi_int_sel" pos="13:12" rst="1">
          <comment>ADPGA_Internal common voltage select 00: 0.5*VB      01: 0.45*VB      10: 0.425*VB      11:0.4*VB</comment>
        </bits>
        <bits access="rw" name="rg_aud_adpgal_g" pos="11:9" rst="1">
          <comment>Audio ADC PGAL Gain control 000 = 0dB        001 = 3dB       010 = 6dB        011 = 12dB 100 = 18dB      101 = 24dB     110 = 30dB       111 = 36dB</comment>
        </bits>
        <bits access="rw" name="rg_aud_adpgar_g" pos="8:6" rst="1">
          <comment>Audio ADC PGAR Gain control 000 = 0dB        001 = 3dB       010 = 6dB        011 = 12dB 100 = 18dB      101 = 24dB     110 = 30dB       111 = 36dB</comment>
        </bits>
        <bits access="rw" name="rg_aud_dalr_os_d" pos="5:3" rst="0">
          <comment>Audio DACL/R dc offset trim bit 000 = 0                    001 = +1/20*VFS       010 = +2/20*VFS        011 = +1/20*VFS 100 = 0           101 = -1/20*VFS        110 = -2/20*VFS        111 = -1/20*VFS</comment>
        </bits>
        <bits access="rw" name="rg_aud_das_os_d" pos="2:0" rst="0">
          <comment>Audio DACS dc offset trim bit 000 = 0           001 = +1/20*VFS       010 = +2/20*VFS        011 = +1/20*VFS 100 = 0                     101 = -1/20*VFS        110 = -2/20*VFS        111 = -1/20*VFS</comment>
        </bits>
      </reg>
      <reg name="ana_cdc2" protect="rw">
        <bits access="rw" name="rg_aud_das_en" pos="13" rst="0">
          <comment>Audio DACS enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_dal_en" pos="12" rst="0">
          <comment>Audio DACL enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_dar_en" pos="11" rst="0">
          <comment>Audio DACR enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="hpl_floopen" pos="10" rst="0">
          <comment>Audio Driver HPL dummy loop enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="hpl_floop_end" pos="9" rst="0">
          <comment>Audio Driver HPL dummy loop end enable signal 0 = disable          1 = enable: true loop fade in</comment>
        </bits>
        <bits access="rw" name="hpr_floopen" pos="8" rst="0">
          <comment>Audio Driver HPR dummy loop enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="hpr_floop_end" pos="7" rst="0">
          <comment>Audio Driver HPR dummy loop end enable signal 0 = disable          1 = enable: true loop fade in</comment>
        </bits>
        <bits access="rw" name="rcv_floopen" pos="6" rst="0">
          <comment>Audio Driver RCV dummy loop enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rcv_floop_end" pos="5" rst="0">
          <comment>Audio Driver RCV dummy loop end enable signal 0 = disable          1 = enable: true loop fade in</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpl_en" pos="4" rst="0">
          <comment>Audio Driver HPL output enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpr_en" pos="3" rst="0">
          <comment>Audio Driver HPR output enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpbuf_en" pos="2" rst="0">
          <comment>Audio Driver vcm buffer enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_rcv_en" pos="1" rst="0">
          <comment>Audio Driver RCV output enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_en" pos="0" rst="0">
          <comment>Audio Speaker PA (Driver SPKL) enable signal 0 = disable          1 = enable</comment>
        </bits>
      </reg>
      <reg name="ana_cdc3" protect="rw">
        <bits access="rw" name="rg_aud_dalr_os_en" pos="12" rst="0">
          <comment>Audio DACL/R dc offset enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_das_os_en" pos="11" rst="0">
          <comment>Audio DACS dc offset enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ng_en" pos="10" rst="0">
          <comment>NG_PA enable control 0 = mute disable          1 = mute enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_sdalhpl" pos="9" rst="0">
          <comment>Audio DACL to HPL enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_sdarhpr" pos="8" rst="0">
          <comment>Audio DACR to HPR enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_sdalrcv" pos="7" rst="0">
          <comment>Audio DACL to Receiver/Earpiece enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_sdapa" pos="6" rst="0">
          <comment>Audio DACS to PA enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_shmicpa_debug" pos="5" rst="0">
          <comment>Audio HMIC to PA enable signal 0 = disable          1 = enable when debug=1, HMIC to PA path on, no matter &quot;RG_AUD_SDAPA&quot; when debug=0, HMIC to PA path off, &quot;RG_AUD_SDAPA&quot; is enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_smicdrv_debug" pos="4" rst="0">
          <comment>Audio MIC to HPL enable signal 0 = disable          1 = enable when debug=1, MIC to HPL path on , &quot;RG_AUD_SDALHPL&quot;/&quot;RG_AUD_SDALRCV&quot; is dis-enable when debug=0, MIC to HPL path off , &quot;RG_AUD_SDALHPL&quot;/&quot;RG_AUD_SDALRCV&quot; is enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_smic1pgal" pos="3" rst="0">
          <comment>MIC1 to Audio ADC PGAL enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_smic2pgar" pos="2" rst="0">
          <comment>MIC2 to Audio ADC PGAR enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_shmicpgal" pos="1" rst="0">
          <comment>HEADMIC to Audio ADC PGAL enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_shmicpgar" pos="0" rst="0">
          <comment>HEADMIC to Audio ADC PGAR enable signal 0 = disable          1 = enable</comment>
        </bits>
      </reg>
      <reg name="ana_cdc4" protect="rw">
        <bits access="rw" name="rg_aud_pa_g" pos="15:12" rst="1">
          <comment>Audio Speaker Driver PGA Gain control &lt;3:2&gt;For Class-D PGA, dft=00 00 = 0dB        01 = 1.5dB        10 = 3dB        11 = 3dB &lt;1:0&gt;For Class-AB PGA 00 = -3dB(20K)  01 = 0dB(28K)  10 = 1.16dB(32K)  11 = 1.16dB(32K)</comment>
        </bits>
        <bits access="rw" name="rg_aud_rcv_g" pos="11:8" rst="2">
          <comment>Audio Receiver/Earpiece Driver RCV_P/RCV_N PGA Gain control 0010 =   6dB     0011 =   3dB 0100 =  0dB      0101 =  -3dB     0110 = -6dB      0111 = -9dB 1000 = -12dB    1001 = -15dB    1010 = -18dB    1111 = mute</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpl_g" pos="7:4" rst="4">
          <comment>Audio Headphone left channel Gain control  0100 =  0dB      0101 =  -3dB     0110 = -6dB      0111 = -9dB 1000 = -12dB    1001 = -15dB    1010 = -18dB    1111 = mute</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpr_g" pos="3:0" rst="4">
          <comment>Audio Headphone right channel Gain control  0100 =  0dB      0101 =  -3dB     0110 = -6dB      0111 = -9dB 1000 = -12dB    1001 = -15dB    1010 = -18dB    1111 = mute</comment>
        </bits>
      </reg>
      <reg name="ana_hdt0" protect="rw">
        <bits access="rw" name="rg_aud_hedet_mux2adc_sel_pd" pos="15" rst="0">
          <comment>MUX2ADC SEL PD 0 = power up      1 = power down</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_buf_en" pos="14" rst="0">
          <comment>Audio signal input to AuxADC enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_bdet_en" pos="13" rst="0">
          <comment>Audio headset button detect circuit enable signal 0 =disable         1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_v2i_en" pos="12" rst="0">
          <comment>Audio headset detect signal RG_HP_DRIVER_EN software control enable signal 0 = DG_HP_DRIVER_EN work       1 = RG_HP_DRIVER_EN work</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_vref_en" pos="11" rst="0">
          <comment>Audio headset detect reference voltage circuit enable signal 0 =disable         1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_micdet_en" pos="10" rst="0">
          <comment>Audio headset mic detect circuit power enable signal 0 =disable         1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_v2ad_scale" pos="9" rst="0">
          <comment>Audio signal input to AuxADC scale select signal 0 =little scale       1 =large scale(4:1)</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_ldet_l_filter" pos="8" rst="0">
          <comment>Audio headset_LINT low detect filter enable signal 0 = no filter        1 = filter</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_buf_chop" pos="7" rst="0">
          <comment>Audio signal input to AuxADC buffer chop signal (1kHz)</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_mux2adc_sel" pos="6:4" rst="0">
          <comment>Audio signal input to AuxADC select 000 = HEADMIC_IN_DET 001 = HEADSET_L_INT 010 = HP_L 011 = HP_R                                     100 = AVDD_VB 101 = VDDPA                                 110 = MICBIAS 111 = HEADMIC_BIAS</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_v2i_sel" pos="3:0" rst="0">
          <comment>Audio headset detect circuit current select signal 0000 =0        0001 = 0.5u                  0010 =1u      0011 = 1.5u                  0100 =2u      0101 = 2.5u                  0110 =3u      0111 = 3.5u                  1000 =4u      1001 = 4.5u      1010 =5u      1011 = 5.5u</comment>
        </bits>
      </reg>
      <reg name="ana_hdt1" protect="rw">
        <bits access="rw" name="rg_aud_hedet_micdet_ref_sel" pos="15:13" rst="6">
          <comment>Audio headset_L_INT insert detect voltage select signal (VDDIO=2.8V) 000 = 2V              001 =2.1V 010 = 2.2V              011 =2.3V        100 = 2.4V              100 =2.5V 110 = 2.6V              111 = 2.7V</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_micdet_hys_sel" pos="12:11" rst="1">
          <comment>Audio headset button detect circuit hysteresis sel signal 00 = 10mV          01 = 20mV         10 =  40mV           11 =forbidden</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_ldet_refl_sel" pos="10:8" rst="0">
          <comment>Audio headset_L_INT insert detect voltage select signal (VDDIO=2.8V) 000 = 25mV              001 =50mV 010 = 100mV              011 = 150mV        100 = 200mV              100 =250mV 110 = 300mV              111 = 350mV</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_ldet_refh_sel" pos="7:6" rst="0">
          <comment>Audio headset_L_INT insert detect voltage select signal (VDDIO=2.8V) 00 = 1.7V              01 = 1.8V 10 = 1.9V              11 = 2V</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_ldet_pu_pd" pos="5:4" rst="1">
          <comment>Audio L_DET pull up power down signal 00 = power up          01 = power down 10/11 = high-z</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_ldet_l_hys_sel" pos="3:2" rst="1">
          <comment>Audio headset button detect circuit hysteresis sel signal 00 = 10mV          01 = 20mV         10 =  40mV           11 =forbidden</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_ldet_h_hys_sel" pos="1:0" rst="1">
          <comment>Audio headset button detect circuit hysteresis sel signal 00 = 10mV          01 = 20mV         10 =  40mV           11 =forbidden</comment>
        </bits>
      </reg>
      <reg name="ana_hdt2" protect="rw">
        <bits access="rw" name="rg_chg_proc_sts_bypass" pos="13" rst="0">
          <comment>BYPASS CHG_STS signal 1 = bypass CHG_EN     0 = dis-bypass CHG_EN</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_jack_type" pos="12:11" rst="0">
          <comment>Audio Headphone jack type select (Head_L_INT) 00 = Tie High       01 = Tie Low 10 = No Spring    11 = forbidden</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_bdet_ref_sel" pos="10:7" rst="0">
          <comment>Audio head microphone button pressed detect voltage select signal (VDDIO=2.8V) 0000 = 1.0V         0001 = 0.95V 0010 = 0.9V         0011 = 0.85V 0100 = 0.8V         0101 = 0.75V 0110 = 0.7V         0111 = 0.65V 1000 = 0.6V         1001 = 0.55V 1010 =0.5V         1011 = 0.45V 1100 = 0.4V         1101/1110/1111 = forbidden</comment>
        </bits>
        <bits access="rw" name="rg_aud_hedet_bdet_hys_sel" pos="6:5" rst="1">
          <comment>Audio headset button detect circuit hysteresis sel signal 00 = 10mV          01 = 20mV         10 =  40mV           11 =forbidden</comment>
        </bits>
        <bits access="rw" name="rg_aud_plgpd_en" pos="4" rst="0">
          <comment>Audio headset plug out detect enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_hp_driver_en" pos="3" rst="0">
          <comment>Audio headset detect signal LDRV_ENB software control signal, it should be set from 0-&gt;1 several ms (ex. 5ms) after audio driver HPL output enable signal (RG_AUD_HPL_EN) set from 1-&gt; 0</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpl_en_d2hdt_en" pos="2" rst="0">
          <comment>Audio Driver HPL output enable signal to headset detect delay function enable signal 0 = disable delay-reg(RG_AUD_HPL_EN_D2HDT_T)         1 = enable delay-reg(RG_AUD_HPL_EN_D2HDT_T)</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpl_en_d2hdt_t" pos="1:0" rst="0">
          <comment>Audio Driver HPL output enable signal (RG_AUD_HPL_EN) to headset detect delay time 00 = 8*Tclk    01 = 16*Tclk 10 = 32*Tclk   11 = 64*Tclk</comment>
        </bits>
      </reg>
      <reg name="ana_dcl0" protect="rw">
        <bits access="rw" name="rg_aud_dcl_en" pos="6" rst="0">
          <comment>Audio digital control logic enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_dcl_rst" pos="5" rst="1">
          <comment>Audio digital control logic reset enable signal 0 = disable   1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_drv_soft_t" pos="4:2" rst="1">
          <comment>Audio DRV delay timer control signal 000 = 0us            001 = 30us 010 = 60us          011 = 90us 100 = 120us        101 = 150us 110 = 180us        111 = 210us</comment>
        </bits>
        <bits access="rw" name="rg_aud_drv_soft_en" pos="1" rst="0">
          <comment>Audio DRV soft start enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_dpop_auto_rst" pos="0" rst="1">
          <comment>Soft reset dpop module . 0:disable , 1:enable</comment>
        </bits>
      </reg>
      <reg name="ana_dcl1" protect="rw">
        <bits access="rw" name="rg_aud_pacal_en" pos="10" rst="0">
          <comment>Audio PA calibration clock input enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pacal_div" pos="9:8" rst="0">
          <comment>Audio PA PWM clock divider select signal 00 = 1/128          01 = 1/64 10 = 1/256          11 = 1/1</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ovp_abmod_pd" pos="7" rst="0">
          <comment>Audio VBAT_PA over voltage protection circuit  mode change signal 0 = enable Class-AB mode         1 = keep the previous mode</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ovp_abmod_t" pos="6:4" rst="0">
          <comment>Audio PA over current protection circuit mute timer control signal 000 = 0ms    001 = 1ms 010 = 4ms    011 = 16ms 100 = 64ms   101 = 256ms 110 = 1s      111 = 4s</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ovp_deg_en" pos="3" rst="0">
          <comment>Audio VBAT_PA over voltage protection circuit  alert deglitch enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ovp_deg_t" pos="2:0" rst="0">
          <comment>Audio VBAT_PA over voltage protection circuit  alert deglitch timer control signal 000 = 0ms     001 = 0.06ms 010 = 0.24ms   011 = 1ms 100 = 4ms      101 = 16ms 110 = 64ms     111 = 256ms</comment>
        </bits>
      </reg>
      <reg name="ana_dcl2" protect="rw">
        <bits access="rw" name="rg_aud_pa_otp_deg_en" pos="12" rst="0">
          <comment>Audio PA over temperature protection circuit alert deglitch enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_otp_deg_t" pos="11:9" rst="0">
          <comment>Audio PA over temperature protection circuit  alert deglitch timer control signal 000 = 0ms   001 = 0.06ms 010 = 0.24ms    011 = 1ms 100 = 4ms    101 = 16ms 110 = 64ms     111 = 256ms</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_otp_mute_en" pos="8" rst="0">
          <comment>Audio PA over temperature protection circuit mute enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ocp_deg_en" pos="7" rst="0">
          <comment>Audio PA over temperature protection circuit alert deglitch enable signal 0 = disable          1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ocp_deg_t" pos="6:4" rst="0">
          <comment>Audio PA over temperature protection circuit  alert deglitch timer control signal 000 = 0ms     001 = 0.06ms 010 = 0.24ms  011 = 1ms 100 = 4ms      101 = 16ms 110 = 64ms     111 = 256ms</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ocp_mute_en" pos="3" rst="0">
          <comment>Audio PA over current protection circuit mute power down signal 1 = enable mute        0 = disable mute</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_ocp_mute_t" pos="2:0" rst="0">
          <comment>Audio PA over current protection circuit mute timer control signal 000 = 0ms    001 = 1ms 010 = 4ms    011 = 16ms 100 = 64ms   101 = 256ms 110 = 1s      111 = 4s</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="ana_dcl4" protect="rw">
        <bits access="rw" name="rg_hpl_depop_chg_cursel" pos="15:8" rst="255">
          <comment>HPL depop DAC current setting</comment>
        </bits>
        <bits access="rw" name="rg_hpr_depop_chg_cursel" pos="7:0" rst="255">
          <comment>HPR depop DAC current setting</comment>
        </bits>
      </reg>
      <reg name="ana_dcl5" protect="rw">
        <bits access="rw" name="rg_aud_hpl_rdac_start" pos="15" rst="1">
          <comment>Reserved, always=1</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpr_rdac_start" pos="14" rst="1">
          <comment>Reserved, always=1</comment>
        </bits>
        <bits access="rw" name="rg_aud_hp_dpop_fdin_en" pos="13" rst="1">
          <comment>Audio HP de-pop fade in function enable signal 0 = disable      1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_hp_dpop_fdout_en" pos="12" rst="1">
          <comment>Audio HP de-pop fade out function enable signal 0 = disable      1 = enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_hp_dpop_gain_n1" pos="11:9" rst="4">
          <comment>Audio HP de-pop gain step (RG_AUD_HP_DPOP_RES_PD=0) 000 = 1              001 = 2 010 = 4              011 = 8 100 = 16            101 = 32 110 = 64            111 = 128</comment>
        </bits>
        <bits access="rw" name="rg_aud_hp_dpop_gain_n2" pos="8:6" rst="0">
          <comment>Audio HP de-pop gain step (RG_AUD_HP_DPOP_RES_PD=0) 000 = 1              001 = 2 010 = 3              011 = 4 100 = 5              101 = 6 110 = 7              111 = 8</comment>
        </bits>
        <bits access="rw" name="rg_aud_hp_dpop_gain_t" pos="5:3" rst="0">
          <comment>Audio HP de-pop gain time step (RG_AUD_HP_DPOP_RES_PD=0) 000 = 30us           001 = 60us 010 = 120us         011 = 250us 100 = 500us         101 = 1ms 110 = 2ms           111 = 4ms</comment>
        </bits>
        <bits access="r" name="rg_aud_hpl_rdac_sts" pos="2" rst="0">
          <comment>Audio HPL_RDAC status signal 0 = unfinish/have never done       1 = finish</comment>
        </bits>
        <bits access="r" name="rg_aud_hpr_rdac_sts" pos="1" rst="0">
          <comment>Audio HPR_RDAC status signal 0 = unfinish/have never done       1 = finish</comment>
        </bits>
      </reg>
      <reg name="ana_dcl6" protect="rw">
        <bits access="rw" name="rg_caldc_wait_t" pos="14:12" rst="0">
          <comment>Audio dc-calibration waiting time, every data change 000 = 2Tclk    001 = 3Tclk    010 = 4Tclk    011 = 5Tclk 100 = 6Tclk    101 = 7Tclk    110 = 8Tclk    111 = 9Tclk</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpl_dpop_clkn1" pos="11:10" rst="0">
          <comment>Audio DePOP HPL DAC clock(start-up) 00 = 1Tclk    01 = 2Tclk    10 = 4Tclk    11 = 8Tclk</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpl_dpop_n1" pos="9:8" rst="0">
          <comment>Audio DePOP HPL DAC data increase step(start-up) 00 = +1    01 = +2    10 = +4    11 = +8</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpl_dpop_val1" pos="7:5" rst="6">
          <comment>Audio DePOP HPL DAC data final value(start-up) 000 = 2    001 = 4    010 = 8    011 = 16 100 = 32  101 = 64  110 = 128 111 =256</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpl_dpop_clkn2" pos="4:3" rst="0">
          <comment>Audio DePOP HPL DAC clock(rising/falling) 00 = 1Tclk    01 = 2Tclk    10 = 4Tclk    11 = 8Tclk</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpl_dpop_n2" pos="2:1" rst="0">
          <comment>Audio DePOP HPL DAC data increase step(rising/falling) 00 = +1    01 = +2    10 = +4    11 = +8</comment>
        </bits>
      </reg>
      <reg name="ana_dcl7" protect="rw">
        <bits access="rw" name="rg_depopl_pcur_opt" pos="14:13" rst="1">
          <comment>depop_hpl_current_sel 00: X2   01:X1   10:X2/3  11:X1/2</comment>
        </bits>
        <bits access="rw" name="rg_depopr_pcur_opt" pos="12:11" rst="1">
          <comment>depop_hpr_current_sel 00: X2   01:X1   10:X2/3  11:X1/2</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpr_dpop_clkn1" pos="10:9" rst="0">
          <comment>Audio DePOP HPR DAC clock(start-up) 00 = 1Tclk    01 = 2Tclk    10 = 4Tclk    11 = 8Tclk</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpr_dpop_n1" pos="8:7" rst="0">
          <comment>Audio DePOP HPR DAC data increase step(start-up) 00 = +1    01 = +2    10 = +4    11 = +8</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpr_dpop_val1" pos="6:4" rst="6">
          <comment>Audio DePOP HPR DAC data final value(start-up) 000 = 2    001 = 4    010 = 8    011 = 16 100 = 32  101 = 64  110 = 128 111 =256</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpr_dpop_clkn2" pos="3:2" rst="0">
          <comment>Audio DePOP HPR DAC clock(rising/falling) 00 = 1Tclk    01 = 2Tclk    10 = 4Tclk    11 = 8Tclk</comment>
        </bits>
        <bits access="rw" name="rg_aud_hpr_dpop_n2" pos="1:0" rst="0">
          <comment>Audio DePOP HPR DAC data increase step(rising/falling) 00 = +1    01 = +2    10 = +4    11 = +8</comment>
        </bits>
      </reg>
      <reg name="ana_sts0" protect="rw">
        <bits access="rw" name="rg_hp_depop_wait_t1" pos="15:13" rst="4">
          <comment>depop_runing time 000:  10ms   001: 20ms   010: 40ms  011: 80ms  100:160ms  101: 320ms  110: 640ms 111: 1280ms</comment>
        </bits>
        <bits access="rw" name="rg_hp_depop_wait_t2" pos="12:10" rst="4">
          <comment>depop_finish waiting time 000:  10ms   001: 20ms   010: 40ms  011: 80ms  100:160ms  101: 320ms  110: 640ms 111: 1280ms</comment>
        </bits>
        <bits access="rw" name="rg_hp_depop_wait_t3" pos="9:8" rst="2">
          <comment>CHG_EN_Delay time 00:  1Tclk   01: 2Tclk   10: 4Tclk  11: 8Tclk</comment>
        </bits>
        <bits access="rw" name="rg_hp_depop_wait_t4" pos="7:6" rst="2">
          <comment>depop path on delay time 00:  1Tclk   01: 2Tclk  10: 4Tclk  11: 8Tclk</comment>
        </bits>
        <bits access="rw" name="rg_dc_cali_idacval" pos="5:3" rst="4">
          <comment>DCCALI_IDAC_repeat_goal 000: 8  001: 9  010: 10  011:11  100:12  101:13  110:14  111:7</comment>
        </bits>
        <bits access="rw" name="dc_cali_idac_cursel" pos="2:1" rst="0">
          <comment>IDAC LSB SETTING: 00: 10nA  01:15nA  10:5nA  11:10nA</comment>
        </bits>
        <bits access="rw" name="rg_dccali_rdaci_adj" pos="0" rst="0">
          <comment>RDAC current enhancement 0 = X1       1 = X2</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="ana_sts2" protect="rw">
        <bits access="rw" name="rg_caldc_start" pos="15" rst="0">
          <comment>DC-calibraion start signal 0 ---&gt; 1 start calibration</comment>
        </bits>
        <bits access="rw" name="rg_caldc_en" pos="14" rst="0">
          <comment>DC-calibraion enable signal (digital) 0: disable      1: enable</comment>
        </bits>
        <bits access="rw" name="rg_caldc_eno" pos="13" rst="0">
          <comment>DC-calibraion enable signal (analog) 0: disable      1: enable</comment>
        </bits>
        <bits access="r" name="rg_aud_dccal_sts" pos="12" rst="0">
          <comment>Audio DC-calibration status signal 0 = unfinish/have never done       1 = finish</comment>
        </bits>
        <bits access="rw" name="rg_dccali_sts_bypass" pos="11" rst="0">
          <comment>DCCALI_STS_BYPASS=0, not bypass DCCALI_process DCCALI_STS_BYPASS=1, bypass DCCALI_process</comment>
        </bits>
        <bits access="r" name="rg_aud_hp_dpop_dvld" pos="10" rst="0">
          <comment>Audio DC-calibration finish insert signal 0 = unfinish        1 = finish</comment>
        </bits>
        <bits access="rw" name="rg_depop_chg_start" pos="9" rst="0">
          <comment>depop start signal 0 ---&gt; 1 start calibration</comment>
        </bits>
        <bits access="rw" name="rg_depop_chg_en" pos="8" rst="0">
          <comment>depop charge en 0: disable  1:enable</comment>
        </bits>
        <bits access="rw" name="rg_aud_plugin" pos="7" rst="0">
          <comment>plug_in=1, headphone has been inserted</comment>
        </bits>
        <bits access="rw" name="rg_depop_en" pos="6" rst="0">
          <comment>depop_ana_en 0: disable  1:enable</comment>
        </bits>
        <bits access="r" name="rg_depop_chg_sts" pos="5" rst="0">
          <comment>Audio plug-in depop status signal 0 = depop not finish        1 = depop finish</comment>
        </bits>
        <bits access="r" name="rg_aud_rcv_dpop_dvld" pos="4" rst="0">
          <comment>Audio plug-in depop charge finish insert signal 0 = unfinish        1 = finish</comment>
        </bits>
        <bits access="rw" name="rg_hpl_pu_enb" pos="3" rst="0">
          <comment>HPL_pull_up enable 0: pull up enable   1: pull up disable</comment>
        </bits>
        <bits access="rw" name="rg_hpr_pu_enb" pos="2" rst="0">
          <comment>HPR_pull_up enable 0: pull up enable   1: pull up disable</comment>
        </bits>
        <bits access="rw" name="rg_insbuf_en" pos="1" rst="0">
          <comment>INSBUF_EN 0: disable   1:enable</comment>
        </bits>
      </reg>
      <reg name="ana_sts3" protect="rw">
        <bits access="rw" name="rg_aud_clk3_reserve" pos="11:10" rst="0">
          <comment>Reserved</comment>
        </bits>
        <bits access="rw" name="rg_depop_bias_sel" pos="9:8" rst="0">
          <comment>AUD_DRV_DEPOP_BIAS_CURRENT SEL 00: 1.25uA   01:2.5uA   10:3.75uA   11:5uA</comment>
        </bits>
        <bits access="rw" name="rg_depop_opa_sel" pos="7:6" rst="0">
          <comment>AUD_DRV_DEPOP_OPA_CURRENT SEL 00: LS_I=5uA, LS_R=100K 01: LS_I=10uA, LS_R=100K 10: LS_I=5uA,  LS_R=50K 11: LS_I=10uA,LS_R=50K</comment>
        </bits>
        <bits access="rw" name="rg_aud_hwsw_sel" pos="5:0" rst="0">
          <comment>Hardware control/software control sel &lt;3&gt;: 0: depend on analog comp value 1: bypass analog comp value &lt;2&gt;: 0: RG_AUD_VCMI_SEL change, repeat dccali 1: change RG_AUD_VCMI_SEL, get two dccali value, choose any according RG_AUD_VCMI_SEL =0/=1 &lt;1&gt;: 0: hw control  DC_CALI_IDAC_CURSEL,  1: sw control DC_CALI_IDAC_CURSEL &lt;0&gt;: 0: hw control  RG_HPL_PU_ENB, RG_HPR_PU_ENB, RG_INSBUF_EN 1:  sw control  RG_HPL_PU_ENB, RG_HPR_PU_ENB, RG_INSBUF_EN</comment>
        </bits>
      </reg>
      <reg name="ana_sts4" protect="r">
        <bits access="r" name="hpl_dccal_rdacl" pos="15:8" rst="0">
          <comment>HPL_DCCALI_RDAC_VALUE</comment>
        </bits>
        <bits access="r" name="hpr_dccal_rdacl" pos="7:4" rst="0">
          <comment>HPR_DCCALI_RDAC_VALUE</comment>
        </bits>
        <bits access="r" name="hpl_dccal_idacl_sel" pos="3:2" rst="0">
          <comment>HPL_DCCALI_IDAC_path</comment>
        </bits>
        <bits access="r" name="hpr_dccal_idacl_sel" pos="1:0" rst="0">
          <comment>HPR_DCCALI_IDAC_path</comment>
        </bits>
      </reg>
      <reg name="ana_sts5" protect="r">
        <bits access="r" name="hpl_dccal_idacl" pos="15:11" rst="0">
          <comment>HPL_DCCALI_IDAC_VALUE</comment>
        </bits>
        <bits access="r" name="hpr_dccal_idacl" pos="10:6" rst="0">
          <comment>HPR_DCCALI_IDAC_VALUE</comment>
        </bits>
        <bits access="r" name="rg_hpl_comp_ins" pos="5:4" rst="0">
          <comment>HPL_DCCALI_IDAC_VALUE</comment>
        </bits>
        <bits access="r" name="rg_hpr_comp_ins" pos="3:2" rst="0">
          <comment>HPR_DCCALI_IDAC_VALUE</comment>
        </bits>
      </reg>
      <reg name="ana_sts6" protect="r">
        <bits access="r" name="rg_aud_pacal_do" pos="15:3" rst="0">
          <comment>Audio PA clock calibration data delta output</comment>
        </bits>
        <bits access="r" name="rg_aud_pacal_dvld" pos="2" rst="0">
          <comment>Audio PA clock calibration data valid signal 0 = not valid         1 = data valid</comment>
        </bits>
      </reg>
      <reg name="ana_sts7" protect="r">
        <bits access="r" name="rg_aud_head_insert_all" pos="12" rst="0">
          <comment>Audio headset insert alert signal (need software anti-dither) 0 = normal             1 = plug in</comment>
        </bits>
        <bits access="r" name="rg_aud_head_insert3" pos="11" rst="0">
          <comment>Audio headset-H insert alert signal (need software anti-dither) 0 = normal             1 = plug in</comment>
        </bits>
        <bits access="r" name="rg_aud_head_insert2" pos="10" rst="0">
          <comment>Audio headset-L insert alert signal (need software anti-dither) 0 = normal             1 = plug in</comment>
        </bits>
        <bits access="r" name="rg_aud_head_insert" pos="9" rst="0">
          <comment>Audio headset microphone insert alert signal (need software anti-dither) 0 = normal             1 = plug in</comment>
        </bits>
        <bits access="r" name="rg_aud_head_button" pos="8" rst="0">
          <comment>Audio headset microphone button press alert signal (need software anti-dither) 0 = normal     1 = button press</comment>
        </bits>
        <bits access="r" name="rg_aud_pa_sh_flag" pos="7" rst="0">
          <comment>Audio PA output short to VBAT detect ALERT signal 0 = normal          1 = short</comment>
        </bits>
        <bits access="r" name="rg_aud_pa_sl_flag" pos="6" rst="0">
          <comment>Audio PA output short to GND detect ALERT signal 0 = normal          1 = short</comment>
        </bits>
        <bits access="r" name="rg_aud_pa_ovp_flag" pos="5" rst="0">
          <comment>Audio PA over voltage protection circuit alert signal 0 = normal    1 = over temperature</comment>
        </bits>
        <bits access="r" name="rg_aud_pa_otp_flag" pos="4" rst="0">
          <comment>Audio PA over temperature protection circuit alert signal 0 = normal    1 = over temperature</comment>
        </bits>
        <bits access="r" name="rg_aud_drv_ocp_flag" pos="3:0" rst="0">
          <comment>Audio Driver over current protection circuit alert signal &lt;3:2&gt; for SPK      &lt;1:0&gt; for Headphone/Earpiece</comment>
        </bits>
      </reg>
      <reg name="ana_clk1" protect="rw">
        <bits access="rw" name="rg_aud_dcdcgen_clk_f" pos="15:14" rst="0">
          <comment>DCDC GEN/MEM clock frequency select (based on Fclk=6.5MHz) 00 = Fclk/4      01 = Fclk / 3 10/11 = Fclk / 2</comment>
        </bits>
        <bits access="rw" name="rg_aud_dcdccore_clk_f" pos="13:12" rst="0">
          <comment>DCDC CORE clock frequency select (based on Fclk=6.5MHz) 00 = Fclk/4       01 = Fclk / 3 10/11 = Fclk / 2</comment>
        </bits>
        <bits access="rw" name="rg_aud_dcdcchg_clk_f" pos="11:10" rst="0">
          <comment>DCDC CHG clock frequency select (based on Fclk=6.5MHz) 00 = Fclk/4      01 = Fclk / 3 10/11 = Fclk / 2</comment>
        </bits>
        <bits access="rw" name="rg_aud_pa_clk_f" pos="9:8" rst="2">
          <comment>Audio PA clock frequency select (based on ADC Clock) 00 = 1/2        01 = 1/4 10 = 1/8        11 = 1/16</comment>
        </bits>
        <bits access="rw" name="rg_aud_clk_pn_sel" pos="7:0" rst="4">
          <comment>Audio clock PN select (If RG_AUD_AD_CLK_F[1:0]=00 or 10 &amp; RG_AUD_DA_CLK_F[1:0]=00, RG_AUD_CLK_PN_SEL) &lt;0&gt; CLK_AUD_DIG_LOOP       &lt;1&gt; CLK_AUD_DIG_6P5M &lt;2&gt; CLK_AUD_DAC                 &lt;3&gt; CLK_AUD_ADC &lt;4&gt; CLK_AUD_DCDCGEN       &lt;5&gt; CLK_AUD_VAD_CLK_SEL &lt;6&gt; CLK_AUD_DCDCCORE     &lt;7&gt; RG_AUD_VB_V&lt;5&gt;</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_aud_ifa.xml">
    <module category="RDA2720M" name="RDA2720M_AUD_IFA">
      <reg name="reserved" protect="r">
      </reg>
      <reg name="adcfifostatus" protect="r">
        <bits access="r" name="adc_fifo_af" pos="8" rst="1">
          <comment>ADC FIFO almost full signal</comment>
        </bits>
        <bits access="r" name="adc_fifo_empty_r" pos="7" rst="1">
          <comment>ADC FIFO real empty.  There is no data in ADC FIFO</comment>
        </bits>
        <bits access="r" name="adc_fifo_full_w" pos="6" rst="1">
          <comment>ADC FIFO real full.</comment>
        </bits>
        <bits access="r" name="adc_fifo_addr_r" pos="5:3" rst="3">
          <comment>ADC FIFO read address</comment>
        </bits>
        <bits access="r" name="adc_fifo_addr_w" pos="2:0" rst="3">
          <comment>ADC FIFO write address</comment>
        </bits>
      </reg>
      <reg name="dac_fifo_sts" protect="r">
        <bits access="r" name="dac_fifo_empty_r" pos="7" rst="1">
          <comment>DAC FIFO real empty.  There is no data in ADC FIFO</comment>
        </bits>
        <bits access="r" name="dac_fifo_full_w" pos="6" rst="1">
          <comment>DAC FIFO real full.</comment>
        </bits>
        <bits access="r" name="dac_fifo_addr_r" pos="5:3" rst="3">
          <comment>DAC FIFO read address</comment>
        </bits>
        <bits access="r" name="dac_fifo_addr_w" pos="2:0" rst="3">
          <comment>DAC FIFO write address</comment>
        </bits>
      </reg>
      <reg name="audif_sts" protect="r">
        <bits access="r" name="cur_st" pos="7:6" rst="2">
          <comment>Internal fsm state</comment>
        </bits>
        <bits access="r" name="cnt" pos="5:3" rst="2">
          <comment>Internal counter</comment>
        </bits>
        <bits access="r" name="rx_cnt" pos="2:1" rst="2">
          <comment>Internal counter</comment>
        </bits>
        <bits access="r" name="adc_rx_data_rdy" pos="0" rst="1">
          <comment>If 1, begin to receive data from A-die</comment>
        </bits>
      </reg>
      <reg name="raw_sts" protect="w">
      </reg>
      <reg name="raw_sts_clr" protect="w">
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_bltc.xml">
    <module category="RDA2720M" name="RDA2720M_BLTC">
      <reg name="bltc_ctrl" protect="rw">
        <bits access="rw" name="wled_sw" pos="15" rst="1">
          <comment>BLTC WLED output value when by SW.</comment>
        </bits>
        <bits access="rw" name="wled_sel" pos="14" rst="1">
          <comment>BLTC WLED output selection 1: output by SW; 0: output by HW.</comment>
        </bits>
        <bits access="rw" name="wled_type" pos="13" rst="1">
          <comment>BLTC WLED output type 1: Normal PWM; 0: Breath light.</comment>
        </bits>
        <bits access="rw" name="wled_run" pos="12" rst="1">
          <comment>BLTC WLED run 1: start BLTC WLED; 0: stop BLTC WLED.</comment>
        </bits>
        <bits access="rw" name="b_sw" pos="11" rst="1">
          <comment>BLTC B output value when by SW.</comment>
        </bits>
        <bits access="rw" name="b_sel" pos="10" rst="1">
          <comment>BLTC B output selection 1: output by SW; 0: output by HW.</comment>
        </bits>
        <bits access="rw" name="b_type" pos="9" rst="1">
          <comment>BLTC B output type 1: Normal PWM; 0: Breath light.</comment>
        </bits>
        <bits access="rw" name="b_run" pos="8" rst="1">
          <comment>BLTC B run 1: start BLTC B; 0: stop BLTC B.</comment>
        </bits>
        <bits access="rw" name="g_sw" pos="7" rst="1">
          <comment>BLTC G output value when by SW.</comment>
        </bits>
        <bits access="rw" name="g_sel" pos="6" rst="1">
          <comment>BLTC G output selection 1: output by SW; 0: output by HW.</comment>
        </bits>
        <bits access="rw" name="g_type" pos="5" rst="1">
          <comment>BLTC G output type 1: Normal PWM; 0: Breath light.</comment>
        </bits>
        <bits access="rw" name="g_run" pos="4" rst="1">
          <comment>BLTC G run 1: start BLTC G; 0: stop BLTC G.</comment>
        </bits>
        <bits access="rw" name="r_sw" pos="3" rst="1">
          <comment>BLTC R output value when by SW.</comment>
        </bits>
        <bits access="rw" name="r_sel" pos="2" rst="1">
          <comment>BLTC R output selection 1: output by SW; 0: output by HW.</comment>
        </bits>
        <bits access="rw" name="r_type" pos="1" rst="1">
          <comment>BLTC R output type 1: Normal PWM; 0: Breath light.</comment>
        </bits>
        <bits access="rw" name="r_run" pos="0" rst="1">
          <comment>BLTC R run 1: start BLTC R; 0: stop BLTC R.</comment>
        </bits>
      </reg>
      <reg name="bltc_r_prescl" protect="rw">
        <bits access="rw" name="prescl" pos="7:0" rst="0">
          <comment>BLTC prescale coefficient.</comment>
        </bits>
      </reg>
      <reg name="bltc_r_duty" protect="rw">
        <bits access="rw" name="duty" pos="15:8" rst="0">
          <comment>PWM duty counter,duty cycle = duty /(mod+1)</comment>
        </bits>
        <bits access="rw" name="mod" pos="7:0" rst="0">
          <comment>PWM mod counter.</comment>
        </bits>
      </reg>
      <reg name="bltc_r_curve0" protect="rw">
        <bits access="rw" name="tfall" pos="13:8" rst="6">
          <comment>Output falling time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
        <bits access="rw" name="trise" pos="5:0" rst="6">
          <comment>Output rising time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
      </reg>
      <reg name="bltc_r_curve1" protect="rw">
        <bits access="rw" name="tlow" pos="15:8" rst="0">
          <comment>Output low time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
        <bits access="rw" name="thigh" pos="7:0" rst="0">
          <comment>Output high time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
      </reg>
      <reg name="bltc_g_prescl" protect="rw">
        <bits access="rw" name="prescl" pos="7:0" rst="0">
          <comment>BLTC prescale coefficient.</comment>
        </bits>
      </reg>
      <reg name="bltc_g_duty" protect="rw">
        <bits access="rw" name="duty" pos="15:8" rst="0">
          <comment>PWM duty counter,duty cycle = duty /(mod+1)</comment>
        </bits>
        <bits access="rw" name="mod" pos="7:0" rst="0">
          <comment>PWM mod counter.</comment>
        </bits>
      </reg>
      <reg name="bltc_g_curve0" protect="rw">
        <bits access="rw" name="tfall" pos="13:8" rst="6">
          <comment>Output falling time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
        <bits access="rw" name="trise" pos="5:0" rst="6">
          <comment>Output rising time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
      </reg>
      <reg name="bltc_g_curve1" protect="rw">
        <bits access="rw" name="tlow" pos="15:8" rst="0">
          <comment>Output low time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
        <bits access="rw" name="thigh" pos="7:0" rst="0">
          <comment>Output high time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
      </reg>
      <reg name="bltc_b_prescl" protect="rw">
        <bits access="rw" name="prescl" pos="7:0" rst="0">
          <comment>BLTC prescale coefficient.</comment>
        </bits>
      </reg>
      <reg name="bltc_b_duty" protect="rw">
        <bits access="rw" name="duty" pos="15:8" rst="0">
          <comment>PWM duty counter,duty cycle = duty /(mod+1)</comment>
        </bits>
        <bits access="rw" name="mod" pos="7:0" rst="0">
          <comment>PWM mod counter.</comment>
        </bits>
      </reg>
      <reg name="bltc_b_curve0" protect="rw">
        <bits access="rw" name="tfall" pos="13:8" rst="6">
          <comment>Output falling time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
        <bits access="rw" name="trise" pos="5:0" rst="6">
          <comment>Output rising time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
      </reg>
      <reg name="bltc_b_curve1" protect="rw">
        <bits access="rw" name="tlow" pos="15:8" rst="0">
          <comment>Output low time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
        <bits access="rw" name="thigh" pos="7:0" rst="0">
          <comment>Output high time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
      </reg>
      <reg name="bltc_sts" protect="r">
        <bits access="r" name="bltc_wled_busy" pos="3" rst="1">
          <comment>BLTC WLED busy, active high.</comment>
        </bits>
        <bits access="r" name="bltc_b_busy" pos="2" rst="1">
          <comment>BLTC B busy, active high.</comment>
        </bits>
        <bits access="r" name="bltc_g_busy" pos="1" rst="1">
          <comment>BLTC G busy, active high.</comment>
        </bits>
        <bits access="r" name="bltc_r_busy" pos="0" rst="1">
          <comment>BLTC R busy, active high.</comment>
        </bits>
      </reg>
      <reg name="rg_rgb_v0" protect="rw">
        <bits access="rw" name="rg_rgb_v0" pos="5:0" rst="6">
          <comment>Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0)</comment>
        </bits>
      </reg>
      <reg name="rg_rgb_v1" protect="rw">
        <bits access="rw" name="rg_rgb_v1" pos="5:0" rst="6">
          <comment>Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0)</comment>
        </bits>
      </reg>
      <reg name="rg_rgb_v2" protect="rw">
        <bits access="rw" name="rg_rgb_v2" pos="5:0" rst="6">
          <comment>Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0)</comment>
        </bits>
      </reg>
      <reg name="rg_rgb_v3" protect="rw">
        <bits access="rw" name="rg_rgb_v3" pos="5:0" rst="6">
          <comment>Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0)</comment>
        </bits>
      </reg>
      <reg name="bltc_wled_prescl" protect="rw">
        <bits access="rw" name="prescl" pos="7:0" rst="0">
          <comment>BLTC prescale coefficient.</comment>
        </bits>
      </reg>
      <reg name="bltc_wled_duty" protect="rw">
        <bits access="rw" name="duty" pos="15:8" rst="0">
          <comment>PWM duty counter,duty cycle = duty /(mod+1)</comment>
        </bits>
        <bits access="rw" name="mod" pos="7:0" rst="0">
          <comment>PWM mod counter.</comment>
        </bits>
      </reg>
      <reg name="bltc_wled_curve0" protect="rw">
        <bits access="rw" name="tfall" pos="13:8" rst="6">
          <comment>Output falling time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
        <bits access="rw" name="trise" pos="5:0" rst="6">
          <comment>Output rising time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
      </reg>
      <reg name="bltc_wled_curve1" protect="rw">
        <bits access="rw" name="tlow" pos="15:8" rst="0">
          <comment>Output low time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
        <bits access="rw" name="thigh" pos="7:0" rst="0">
          <comment>Output high time, its unit is 0.125s, it should be &gt;0.</comment>
        </bits>
      </reg>
      <reg name="bltc_pd_ctrl" protect="rw">
        <bits access="rw" name="hw_pd" pos="1" rst="1">
          <comment>Power down signal 0:bltc_pd depend on SW_PD  1:bltc_pd depend on bltc output</comment>
        </bits>
        <bits access="rw" name="sw_pd" pos="0" rst="1">
          <comment>Power down signal : 0: Power on the reference current source 1: Power down the reference current source</comment>
        </bits>
      </reg>
      <reg name="bltc_version" protect="r">
        <bits access="r" name="bltc_version" pos="15:0" rst="14">
          <comment>BLTC_VERSION information Default value is 16h0100  (r1p0)</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_cal.xml">
    <module category="RDA2720M" name="RDA2720M_CAL">
      <reg name="osc_cal_star" protect="rw">
        <bits access="rw" name="cal_start_busy" pos="0" rst="1">
          <comment>Write this bit 1 will start calibration process, write 0 has no effect Read this this will get the current calibration status. If 1, means the calibration is on progress. If 0, means calibration is finished, current is idle.</comment>
        </bits>
      </reg>
      <reg name="osc_cal_cycle_p0" protect="rw">
        <bits access="rw" name="cal_cycle_p0" pos="15:0" rst="14">
          <comment>Calibration cycle control, this is the low part of calibration cycle. Coupled with CAL_CYCLE_P1[7:0], the whole calibration cycles is : Calibration cycle = {CAL_CYCLE_P1[7:0],CAL_CYCLE_P0[15:0]}; The calibration cycle means using how many self-oscillator clocks to do calibration, the more cycles used, the more accuracy will be achieved. To make calculation simple, calibration cycle should be multiple of 2, that means, Calibration cycle = 2^n</comment>
        </bits>
      </reg>
      <reg name="osc_cal_cycle_p1" protect="rw">
        <bits access="rw" name="cal_cycle_p1" pos="7:0" rst="0">
          <comment>Calibration cycle control, this is the high part of calibration cycle.</comment>
        </bits>
      </reg>
      <reg name="osc_cal_result_p0" protect="r">
        <bits access="r" name="cal_result_p0" pos="15:0" rst="14">
          <comment>Calibration result, part 0. Coupled with CAL_RESULT_P1, the total calibration result is : Cal result = {CAL_RESULT_P1[15:0],CAL_RESULT_P0[15:0]}</comment>
        </bits>
      </reg>
      <reg name="osc_cal_result_p1" protect="r">
        <bits access="r" name="cal_result_p1" pos="15:0" rst="14">
          <comment>Calibration result, part 1.</comment>
        </bits>
      </reg>
      <reg name="osc_div_fac_upd" protect="rw">
        <bits access="rw" name="osc_div_fac_upd" pos="0" rst="1">
          <comment>Write this bit 1 will start 32k sigma-delta divider factor update process. write 0 has no effect Read this this will get the current update process status. If 1, means the update process is not finished. If 0, means this process is finished,current is idle.</comment>
        </bits>
      </reg>
      <reg name="osc_div_fac_frac" protect="rw">
        <bits access="rw" name="osc_div_fac_frac" pos="15:0" rst="14">
          <comment>32k sigma-delta divider factor fraction part. This field is part of the fraction bits.</comment>
        </bits>
      </reg>
      <reg name="osc_div_fac_int" protect="rw">
        <bits access="rw" name="osc_div_fac_int" pos="3:0" rst="4">
          <comment>32k sigma-delta divider integer.</comment>
        </bits>
      </reg>
      <reg name="osc_div_int_en" protect="rw">
        <bits access="rw" name="osc_fac_upd_done_int_en" pos="1" rst="1">
          <comment>Factor update done interrupt enable</comment>
        </bits>
        <bits access="rw" name="osc_cal_done_int_en" pos="0" rst="1">
          <comment>Calibration done interrupt enable..</comment>
        </bits>
      </reg>
      <reg name="osc_div_int_clr" protect="rw">
        <bits access="rw" name="osc_fac_upd_done_int_clr" pos="1" rst="1">
          <comment>Write 1 to this bit will clear OSC_FAC_UPD_DONE_INT_RAWWrite 0 has no effect</comment>
        </bits>
        <bits access="rw" name="osc_cal_done_int_clr" pos="0" rst="1">
          <comment>Write 1 to this bit will clear OSC_CAL_DONE_INT_RAWWrite 0 has no effect</comment>
        </bits>
      </reg>
      <reg name="osc_div_int_raw" protect="r">
        <bits access="r" name="osc_fac_upd_done_int_raw" pos="1" rst="1">
          <comment>Interrupt raw bits, 1 means factor update process has finished.</comment>
        </bits>
        <bits access="r" name="osc_cal_done_int_raw" pos="0" rst="1">
          <comment>Interrupt raw bits, 1 means self-oscillator calibration process has finished.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_rf_mode.xml">
    <module category="RDA2720M" name="RDA2720M_RF_MODE">
      <reg name="test_ctrl" protect="rw">
        <bits access="rw" name="ptest_amode_en" pos="8" rst="0">
          <comment>0: Function test mode
1: Analog test mode</comment>
        </bits>
        <bits access="rw" name="rf_test_mode" pos="7:0" rst="0">
          <comment>0: IOMODE
1-255: Analog Test Mode</comment>
        </bits>
      </reg>
      <reg name="test_status" protect="r">
        <bits access="r" name="ptest_analog_mode_en" pos="4" rst="0">
      </bits>
        <bits access="r" name="ptest_io_mode" pos="3" rst="0">
      </bits>
        <bits access="r" name="ptest_func_mode" pos="2" rst="0">
      </bits>
        <bits access="r" name="ptest_scan_mode" pos="1" rst="0">
      </bits>
        <bits access="r" name="ptest_mode" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="test_io_in" protect="r">
        <bits access="r" name="test_io_in" pos="12:0" rst="0">
      </bits>
      </reg>
      <reg name="test_io_out" protect="rw">
        <bits access="rw" name="test_io_out" pos="12:0" rst="0">
      </bits>
      </reg>
      <reg name="test_io_ie" protect="rw">
        <bits access="rw" name="test_io_ie" pos="12:0" rst="0">
      </bits>
      </reg>
      <reg name="test_io_oe" protect="rw">
        <bits access="rw" name="test_io_oe" pos="12:0" rst="0">
      </bits>
      </reg>
      <reg name="for_ldo_0" protect="rw">
        <bits access="rw" name="force_ldo_rf15" pos="15" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_camd" pos="14" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_lcd" pos="13" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_usb33" pos="11" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_dcxo" pos="10" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_mem" pos="9" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_spimem" pos="8" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_vio18" pos="7" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_ddr12" pos="6" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_ana" pos="5" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_sim1" pos="3" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_sim0" pos="2" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_cama" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="for_ldo_1" protect="rw">
        <bits access="rw" name="force_ldo_cp" pos="7" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_emm" pos="6" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_kpled" pos="5" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_vibr" pos="4" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_con" pos="3" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_emmc" pos="2" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_vdd28" pos="1" rst="0">
      </bits>
      </reg>
      <reg name="for_dcdc" protect="rw">
        <bits access="rw" name="force_dcdc_core_low_vol" pos="9" rst="0">
      </bits>
        <bits access="rw" name="force_osc3m" pos="8" rst="0">
      </bits>
        <bits access="rw" name="force_vpa" pos="7" rst="0">
      </bits>
        <bits access="rw" name="force_vgen" pos="5" rst="0">
      </bits>
        <bits access="rw" name="force_vcore" pos="2" rst="0">
      </bits>
      </reg>
      <reg name="for_ldo_lp_0" protect="rw">
        <bits access="rw" name="force_ldo_rf15_lp" pos="15" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_camd_lp" pos="14" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_lcd_lp" pos="13" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_usb33_lp" pos="11" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_dcxo_lp" pos="10" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_mem_lp" pos="9" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_spimem_lp" pos="8" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_vio18_lp" pos="7" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_ddr12_lp" pos="6" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_ana_lp" pos="5" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_sim1_lp" pos="3" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_sim0_lp" pos="2" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_cama_lp" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="for_ldo_lp_1" protect="rw">
        <bits access="rw" name="force_ldo_con_lp" pos="3" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_emmc_lp" pos="2" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_vdd28_lp" pos="1" rst="0">
      </bits>
        <bits access="rw" name="force_ldo_rf18b_lp" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="for_dcdc_lp" protect="rw">
        <bits access="rw" name="force_vpa_lp" pos="7" rst="0">
      </bits>
        <bits access="rw" name="force_vgen_lp" pos="5" rst="0">
      </bits>
        <bits access="rw" name="force_vcore_lp" pos="2" rst="0">
      </bits>
      </reg>
      <reg name="ldo_lp_0" protect="rw">
        <bits access="rw" name="tst_ldo_rf15_lp_en" pos="15" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_camd_lp_en" pos="14" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_lcd_lp_en" pos="13" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_usb33_lp_en" pos="11" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_dcxo_lp_en" pos="10" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_mem_lp_en" pos="9" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_spimem_lp_en" pos="8" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_vio18_lp_en" pos="7" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_ddr12_lp_en" pos="6" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_ana_lp_en" pos="5" rst="0">
      </bits>
        <bits access="rw" name="resrved" pos="4" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_sim1_lp_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_sim0_lp_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_cama_lp_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="ldo_lp_1" protect="rw">
        <bits access="rw" name="tst_ldo_con_lp_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_emmc_lp_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="tst_ldo_vdd28_lp_en" pos="1" rst="0">
      </bits>
      </reg>
      <reg name="dcdc_lp" protect="rw">
        <bits access="rw" name="tst_vpa_lp_en" pos="7" rst="0">
      </bits>
        <bits access="rw" name="tst_vgen_lp_en" pos="5" rst="0">
      </bits>
        <bits access="rw" name="tst_vcore_lp_en" pos="2" rst="0">
      </bits>
      </reg>
      <reg name="byp_dcdc" protect="rw">
        <bits access="rw" name="byp_vpa" pos="7" rst="0">
      </bits>
        <bits access="rw" name="byp_vgen" pos="5" rst="0">
      </bits>
        <bits access="rw" name="byp_vcore" pos="2" rst="0">
      </bits>
      </reg>
      <reg name="for_other_0" protect="rw">
        <bits access="rw" name="force_fgu" pos="15" rst="0">
      </bits>
        <bits access="rw" name="force_sw" pos="14" rst="0">
      </bits>
        <bits access="rw" name="force_chg_det" pos="12" rst="0">
      </bits>
        <bits access="rw" name="force_auxad" pos="11" rst="0">
      </bits>
        <bits access="rw" name="force_chg" pos="10" rst="0">
      </bits>
        <bits access="rw" name="force_stop" pos="9" rst="0">
      </bits>
        <bits access="rw" name="force_rc1m" pos="8" rst="0">
      </bits>
        <bits access="rw" name="force_rtc32k" pos="7" rst="0">
      </bits>
        <bits access="rw" name="force_rtc" pos="6" rst="0">
      </bits>
        <bits access="rw" name="force_baton" pos="4" rst="0">
      </bits>
        <bits access="rw" name="force_dbg" pos="3" rst="0">
      </bits>
        <bits access="rw" name="force_vbat_crash" pos="2" rst="0">
      </bits>
        <bits access="rw" name="force_ovlo" pos="1" rst="0">
      </bits>
        <bits access="rw" name="force_bg" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="for_other_1" protect="rw">
        <bits access="rw" name="force_osc" pos="2" rst="0">
      </bits>
        <bits access="rw" name="force_emm_pro" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="tst_auxad_0" protect="rw">
        <bits access="r" name="auxad_cs_cnt" pos="15:11" rst="0">
      </bits>
        <bits access="rw" name="tst_auxad_cs_load_en" pos="10" rst="0">
      </bits>
        <bits access="rw" name="tst_auxad_test_en" pos="9" rst="0">
      </bits>
        <bits access="rw" name="tst_auxad_rstn" pos="8" rst="1">
      </bits>
        <bits access="rw" name="tst_auxad_init" pos="7" rst="0">
      </bits>
        <bits access="rw" name="tst_auxad_scale" pos="6:5" rst="0">
      </bits>
        <bits access="rw" name="tst_auxad_cs" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="tst_auxad_1" protect="rw">
        <bits access="r" name="auxad_fsm_idle" pos="15" rst="1">
      </bits>
        <bits access="rw" name="tst_auxad_stop_req" pos="14" rst="0">
      </bits>
        <bits access="rw" name="tst_auxad_cs_add_en" pos="13" rst="0">
      </bits>
        <bits access="r" name="auxad_vld_flag" pos="12" rst="0">
      </bits>
        <bits access="r" name="ad_auxad_dat_wrap" pos="11:0" rst="0">
      </bits>
      </reg>
      <reg name="tst_chgdet" protect="rw">
        <bits access="rw" name="tst_dp_dm_bc_enb" pos="10" rst="1">
      </bits>
        <bits access="r" name="non_dcp_int_wrap" pos="9" rst="0">
      </bits>
        <bits access="r" name="chg_det_pd_wrap" pos="7" rst="0">
      </bits>
        <bits access="r" name="dp_low_wrap" pos="6" rst="0">
      </bits>
        <bits access="r" name="dcp_det_wrap" pos="5" rst="0">
      </bits>
        <bits access="r" name="chg_det_wrap" pos="4" rst="0">
      </bits>
        <bits access="r" name="cdp_int_wrap" pos="3" rst="0">
      </bits>
        <bits access="r" name="dcp_int_wrap" pos="2" rst="0">
      </bits>
        <bits access="r" name="sdp_int_wrap" pos="1" rst="0">
      </bits>
        <bits access="r" name="chg_det_done_wrap" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="reserved_reg1" protect="rw">
      </reg>
      <reg name="tst_fgu" protect="rw">
        <bits access="r" name="fgu_ocv_data_wrap" pos="15:14" rst="0">
      </bits>
        <bits access="r" name="fgu_invalid_pocv_wrap" pos="13" rst="0">
      </bits>
        <bits access="r" name="fgu_ana_sel_wrap" pos="12" rst="0">
      </bits>
        <bits access="rw" name="tst_sdb_vref_ctl" pos="11" rst="0">
      </bits>
        <bits access="rw" name="tst_sda_vref_ctl" pos="10" rst="0">
      </bits>
        <bits access="rw" name="tst_fgu_rst_rtc_n" pos="9" rst="1">
      </bits>
        <bits access="rw" name="tst_sda_iin_en" pos="8" rst="1">
      </bits>
        <bits access="rw" name="tst_sdb_vin_en" pos="7" rst="1">
      </bits>
        <bits access="rw" name="tst_sda_vin_en" pos="6" rst="0">
      </bits>
        <bits access="rw" name="tst_sd_rst" pos="5" rst="0">
      </bits>
        <bits access="rw" name="tst_sd_pd" pos="4" rst="0">
      </bits>
        <bits access="rw" name="tst_fgu_ocv_mux" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="tst_chgr" protect="rw">
        <bits access="r" name="chgr_cv_status_wrap" pos="5" rst="0">
      </bits>
        <bits access="r" name="chgr_on_wrap" pos="4" rst="0">
      </bits>
        <bits access="r" name="chgr_int_wrap" pos="3" rst="0">
      </bits>
        <bits access="r" name="vchg_ovi_wrap" pos="1" rst="0">
      </bits>
        <bits access="rw" name="tst_chgr_ptest" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="reserved_reg2" protect="r">
      </reg>
      <reg name="tst_other_0" protect="r">
        <bits access="r" name="sdb_out_wrap" pos="6" rst="0">
      </bits>
        <bits access="r" name="sda_out_wrap" pos="5" rst="0">
      </bits>
        <bits access="r" name="rtc_mode_o_wrap" pos="4" rst="0">
      </bits>
        <bits access="r" name="batdet_ok_wrap" pos="3" rst="0">
      </bits>
        <bits access="r" name="vbat_ok_wrap" pos="2" rst="0">
      </bits>
      </reg>
      <reg name="tst_other_1" protect="rw">
        <bits access="rw" name="tst_osc_pd" pos="9" rst="0">
      </bits>
        <bits access="rw" name="tst_pd_set" pos="8" rst="0">
      </bits>
        <bits access="rw" name="tst_dcdc_core_low_vol" pos="6" rst="0">
      </bits>
        <bits access="rw" name="tst_clk26m_sel" pos="5" rst="0">
      </bits>
        <bits access="rw" name="tst_bg_ts" pos="4" rst="0">
      </bits>
        <bits access="rw" name="tst_aud_loop_both_die" pos="3" rst="0">
      </bits>
        <bits access="rw" name="tst_aud_loop_a_die" pos="2" rst="0">
      </bits>
      </reg>
      <hole size="160"/>
      <reg name="tst_efs_reg1" protect="rw">
        <bits access="rw" name="tst_efs_reg1" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="tst_efs_reg2" protect="rw">
        <bits access="rw" name="tst_efs_reg2" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="tst_efs_reg3" protect="rw">
        <bits access="rw" name="tst_efs_reg3" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="tst_efs_sel0" protect="rw">
        <bits access="rw" name="efs_sel_ldo_rtc_cal" pos="11:10" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_ldo_dcxo_trim" pos="9:8" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_ldo_vibr" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_ldo_kpled" pos="5:4" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_ldo_trim_b" pos="3:2" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_ldo_trim_a" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="tst_efs_sel1" protect="r">
      </reg>
      <reg name="tst_efs_sel2" protect="r">
      </reg>
      <reg name="tst_efs_sel3" protect="rw">
        <bits access="rw" name="efs_sel_dcdc_wpa_trim" pos="11:10" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_dcdc_core_trim" pos="9:8" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_dcdc_wpa_delta" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_dcdc_gen_delta" pos="5:4" rst="0">
      </bits>
      </reg>
      <reg name="tst_efs_sel4" protect="rw">
        <bits access="rw" name="efs_sel_dcdc_core_lvl_lp" pos="11:10" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_dcdc_core_delta_lp" pos="9:8" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_dcdc_core_lvl_nor" pos="3:2" rst="0">
      </bits>
        <bits access="rw" name="efs_sel_dcdc_core_delta_nor" pos="1:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_eic.xml">
    <module category="RDA2720M" name="RDA2720M_EIC">
      <reg name="eicdata" protect="r">
        <bits access="r" name="eicdata" pos="12:0" rst="11">
          <comment>EIC bits data input.
Note:  EICDATA synchronizes the original data inputs with 2 cycles of Rtcdiv5_clk, so SW need delay 2ms to get the exact value of original data inputs when Rtcdiv5_clk is enabled.</comment>
        </bits>
      </reg>
      <reg name="eicdmsk" protect="rw">
        <bits access="rw" name="eicdmsk" pos="12:0" rst="11">
          <comment>bit type is changed from r/w to rw.
          EICDATA register can be read if EICDMSK set 1</comment>
        </bits>
      </reg>
      <reg name="reserved1" protect="r">
      </reg>
      <reg name="reserved2" protect="r">
      </reg>
      <reg name="reserved3" protect="r">
      </reg>
      <reg name="eiciev" protect="rw">
        <bits access="rw" name="eiciev" pos="12:0" rst="11">
          <comment>EIC bits interrupt status register:1 high levels trigger interrupts, 0 low levels trigger interrupts.</comment>
        </bits>
      </reg>
      <reg name="eicie" protect="rw">
        <bits access="rw" name="eicie" pos="12:0" rst="11">
          <comment>EIC bits interrupt enable register:1 corresponding bit interrupt is enabled. 0 corresponding bit interrupt isnt enabled</comment>
        </bits>
      </reg>
      <reg name="eicris" protect="r">
        <bits access="r" name="eicris" pos="12:0" rst="11">
          <comment>EIC bits raw interrupt status register:1 interrupt condition met0 condition not met</comment>
        </bits>
      </reg>
      <reg name="eicmis" protect="r">
        <bits access="r" name="eicmis" pos="12:0" rst="11">
          <comment>EIC bits masked interrupt status register:1 Interrupt active 0 interrupt not active</comment>
        </bits>
      </reg>
      <reg name="eicic" protect="w">
        <bits access="w" name="eicic" pos="12:0" rst="11">
          <comment>EIC bits interrupt clear register:1 clears detected interrupt. 0 has no effect.</comment>
        </bits>
      </reg>
      <reg name="eictrig" protect="w">
        <bits access="w" name="eictrig" pos="12:0" rst="11">
          <comment>EIC bits trig control register:1: generate the trig_start pulse0: no effect It must set EICTRIG for using de-bounce function and getting active interrupt.</comment>
        </bits>
      </reg>
      <reg name="reserved4" protect="r">
      </reg>
      <reg name="reserved5" protect="r">
      </reg>
      <reg name="reserved6" protect="r">
      </reg>
      <reg name="reserved7" protect="r">
      </reg>
      <reg name="reserved8" protect="r">
      </reg>
      <reg name="eic0ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic1ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic2ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic3ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic4ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic5ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic6ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic7ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic8ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open;</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic9ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic10ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic11ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open;</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic12ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic13ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic14ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
      <reg name="eic15ctrl" protect="rw">
        <bits access="rw" name="force_clk_dbnc" pos="15" rst="1">
          <comment>1: clock of dbnc forced open; 0: no effect</comment>
        </bits>
        <bits access="rw" name="dbnc_en" pos="14" rst="1">
          <comment>de-bounce mechanism enable or disable: 1 enable,0 disable(bypass)</comment>
        </bits>
        <bits access="rw" name="dbnc_cnt" pos="11:0" rst="10">
          <comment>de-bounce counter period value setting,  the unit is millisecond</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_efs.xml">
    <module category="RDA2720M" name="RDA2720M_EFS">
      <reg name="efuse_glb_ctrl" protect="rw">
        <bits access="rw" name="margin_mode" pos="3" rst="0">
          <comment>Reserved</comment>
        </bits>
        <bits access="rw" name="efuse_type" pos="2:1" rst="0">
          <comment>Reserved</comment>
        </bits>
        <bits access="rw" name="efuse_pgm_enable" pos="0" rst="0">
          <comment>0: Normal read mode, 1:Margin read1 mode</comment>
        </bits>
      </reg>
      <reg name="efuse_data_rd" protect="r">
        <bits access="r" name="efuse_data_rd" pos="15:0" rst="0">
          <comment>Efuse read data,
If SW  use efuse controller to send a read command to efuse memory, the return value will store here.</comment>
        </bits>
      </reg>
      <reg name="efuse_data_wr" protect="rw">
        <bits access="rw" name="efuse_data_wr" pos="15:0" rst="0">
          <comment>Efuse data to be write.
If SW want to program the efuse memory, the data to be programmed  will write to this register before SW issue a PGM command.</comment>
        </bits>
      </reg>
      <reg name="efuse_addr_index" protect="rw">
        <bits access="rw" name="efuse_addr_index" pos="4:0" rst="0">
          <comment>The efuse memory block index to be read or write.</comment>
        </bits>
      </reg>
      <reg name="efuse_mode_ctrl" protect="rw">
        <bits access="rw" name="efuse_normal_rd_flag_clr" pos="2" rst="1">
          <comment>Write 1 to this bit will clear normal read flag. This bit is self-clear, read this bit will always get 0</comment>
        </bits>
        <bits access="rw" name="efuse_rd_start" pos="1" rst="1">
          <comment>Write 1 to this bit start READ mode(read mode). This bit is self-clear, read this bit will always get 0</comment>
        </bits>
        <bits access="rw" name="efuse_pg_start" pos="0" rst="1">
          <comment>Write 1 to this bit start PGM mode(PGM mode). This bit is self-clear, read this bit will always get 0</comment>
        </bits>
      </reg>
      <reg name="efuse_status" protect="r">
        <bits access="r" name="efuse_normal_rd_done" pos="4" rst="1">
          <comment>1 indicate EFUSE normal read has been done</comment>
        </bits>
        <bits access="r" name="efuse_global_prot" pos="3" rst="1">
          <comment>If SW send a PGM command to memory and memory controller find the memory need to be protected (LSB of 64 bit is 1), this flag will be set to 1.</comment>
        </bits>
        <bits access="r" name="standby_busy" pos="2" rst="1">
          <comment>1 indicate efuse memory in standby mode</comment>
        </bits>
        <bits access="r" name="read_busy" pos="1" rst="1">
          <comment>1 indicate efuse memory in read mode</comment>
        </bits>
        <bits access="r" name="pgm_busy" pos="0" rst="1">
          <comment>1 indicate efuse memory in programming mode</comment>
        </bits>
      </reg>
      <reg name="efuse_magic_number" protect="rw">
        <bits access="rw" name="efuse_magin_magic_number" pos="15:0" rst="14">
          <comment>Magic number, only when this field is  0x2720, the Efuse programming command can be handle.
So if SW want to program efuse memory, except open clocks and power, 2 other  conditions must be met :
a) PGM_EN =1;
b) EFUSE_MAGIC_NUMBER = 0x2720</comment>
        </bits>
      </reg>
      <reg name="efuse_magin_magic_number" protect="rw">
        <bits access="rw" name="efuse_magin_magic_number" pos="15:0" rst="14">
          <comment>Magic number, only when this field is  0x6868,  the margin read is usable.</comment>
        </bits>
      </reg>
      <reg name="efuse_wr_timing_ctrl" protect="r">
        <bits access="r" name="efuse_wr_timing_ctrl" pos="13:0" rst="23953">
          <comment>Config this register to control the timing of writing operation related signals.
300us voltage rise,20usx16 program,300us voltage fall</comment>
        </bits>
      </reg>
      <reg name="efuse_rd_timing_ctrl" protect="rw">
        <bits access="rw" name="efuse_rd_timing_ctrl" pos="9:0" rst="62">
          <comment>Config this register to control the timing of writing operation related signals
2.348us Read Time</comment>
        </bits>
      </reg>
      <reg name="efuse_version" protect="rw">
        <bits access="rw" name="efuse_version" pos="15:0" rst="32768">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_fgu.xml">
    <module category="RDA2720M" name="RDA2720M_FGU">
      <reg name="fgustart1" protect="w">
        <bits access="w" name="qmax_update_en" pos="2" rst="1">
          <comment>Qmax Update enables. Write 1 to this bit will do a Qmax update processing. It is auto cleared to 0, after write 1. To check the updating status, please read QMAX_UPD_STS.</comment>
        </bits>
        <bits access="w" name="fgu_reset" pos="1" rst="1">
          <comment>FGU Reset signal. Write this bit to reset the module, it is auto cleared to 0 after reset.</comment>
        </bits>
        <bits access="w" name="write_setclb_en" pos="0" rst="1">
          <comment>When write CLBCNT_SETH &amp; CLBCNT_SETL, software should write this bit after write all of the two register to sync. It to CLK32KHz domain.</comment>
        </bits>
      </reg>
      <reg name="fgu_start2" protect="rw">
        <bits access="rw" name="sw_force_lock_high" pos="15" rst="1">
          <comment>bit type is changed from r/w to rw.
          Software force qmax low voltage area to be locked,  (Need to check WRITE_ACTIVE_STS)</comment>
        </bits>
        <bits access="rw" name="sw_force_lock_low" pos="14" rst="1">
          <comment>bit type is changed from r/w to rw.
          Software force qmax high voltage area to be locked</comment>
        </bits>
        <bits access="rw" name="sw_force_qmax_cnt" pos="13" rst="1">
          <comment>bit type is changed from r/w to rw.
          When set to 1, qmax counter will be forced to intergrate current, regardless of qmax lock conditions.</comment>
        </bits>
        <bits access="rw" name="volt_h_valid" pos="12" rst="1">
          <comment>bit type is changed from r/w to rw.
          Voltage high bit valid 0: voltage is 12 bits valid (high bit is omitted) 1: voltage is 13 bits valid</comment>
        </bits>
        <bits access="rw" name="fgu_disable_en" pos="11" rst="1">
          <comment>bit type is changed from r/w to rw.
          FGU Disable signal. It indicates if the FGU is worked or not. 0:  FGU is not disable and worked 1:  FGU is disable and not worked</comment>
        </bits>
        <bits access="rw" name="clbcnt_delta_mode" pos="10" rst="1">
          <comment>bit type is changed from r/w to rw.
          Coulomb Counter Delta Threshold Mode. This bit indicates if the coulomb counter is working when the battery is in low power condition. 0:  work when in low power condition 1:  no work when in low power condition It is working in default.</comment>
        </bits>
        <bits access="rw" name="volt_duty" pos="6:5" rst="2">
          <comment>bit type is changed from r/w to rw.
          Voltage duty ratio. 2h0: 1-7 2h1: 1-3 2h2: 1-1 2h3: 1-0 When ADC_SEL = 0, these bits are invalid. Refer to Timing Diagram for detail</comment>
        </bits>
        <bits access="rw" name="sw_dis_curt" pos="3" rst="1">
          <comment>bit type is changed from r/w to rw.
          When just use voltage of this module, this bit can disable all the current calculation logic, which will save power. 0:  not disable current 1:  disable current logic</comment>
        </bits>
        <bits access="rw" name="force_lock_en" pos="2" rst="1">
          <comment>bit type is changed from r/w to rw.
          When update the Qmax, if the battery is not in relax mode, then the voltage wont lock, write this bit will force the voltage lock to OCV either the battery is in relax mode or in active mode. 0:  not force lock 1:  force lock</comment>
        </bits>
        <bits access="rw" name="low_power_mode" pos="1" rst="1">
          <comment>bit type is changed from r/w to rw.
          There are 2 methods to judge whether the battery is in low power mode. 0:  use relax counter to judge 1:  use deep_sleep signal to judge</comment>
        </bits>
        <bits access="rw" name="auto_low_power" pos="0" rst="1">
          <comment>bit type is changed from r/w to rw.
          When the battery is in relax mode, the current can be set to sample at each 1 second instead of each 500ms, which will save power. If this bit is set 1, then the module will auto switch to low power mode. 0:  not auto low, SW should control manually 1: auto low when the battery is in relax mode.
Note: when AD1_ENABLE = 0,  the voltage and current is measured in ADC0
Note: when AD1_ENABLE = 1,  the current is measured in ADC0, and voltage is measured in ADC1.</comment>
        </bits>
      </reg>
      <reg name="adc_cfg" protect="rw">
        <bits access="rw" name="rg_sd_rsv" pos="15:14" rst="2">
          <comment>bit type is changed from r/w to rw.
          RG_SD_RSV[14]</comment>
        </bits>
        <bits access="rw" name="rg_sd_vcminavss_en" pos="13" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable Common voltage tied to ground</comment>
        </bits>
        <bits access="rw" name="rg_sd_iboot_en" pos="12" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable high current mode</comment>
        </bits>
        <bits access="rw" name="rg_sd_bgref_en" pos="11" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable reference band gap</comment>
        </bits>
        <bits access="rw" name="adc_en_sel" pos="10" rst="1">
          <comment>bit type is changed from r/w to rw.
          When ADC_EN_SEL is 0, ADC enable is always high When ADC_EN_SEL is 1, FGU takes the control of ADC enable</comment>
        </bits>
        <bits access="r" name="ad0_in_data" pos="9" rst="1">
          <comment>Ad0_in_data</comment>
        </bits>
        <bits access="r" name="ad1_in_data" pos="8" rst="1">
          <comment>Ad1_in_data</comment>
        </bits>
        <bits access="rw" name="force_ad1_vin_en" pos="7" rst="1">
          <comment>bit type is changed from r/w to rw.
          Force ADC1_VIN_EN interface to set value.</comment>
        </bits>
        <bits access="rw" name="force_ad0_vin_en" pos="6" rst="1">
          <comment>bit type is changed from r/w to rw.
          Force ADC0_VIN_EN interface to set value.</comment>
        </bits>
        <bits access="rw" name="force_ad0_iin_en" pos="5" rst="1">
          <comment>bit type is changed from r/w to rw.
          Force ADC0_IIN_EN interface to set value.</comment>
        </bits>
        <bits access="rw" name="force_ad_en" pos="4" rst="1">
          <comment>bit type is changed from r/w to rw.
          Force ADC0/ADC1 interface enable.</comment>
        </bits>
        <bits access="rw" name="ad1_volt_ref" pos="3" rst="1">
          <comment>bit type is changed from r/w to rw.
          ADC1 Voltage Reference. 0: 0.1V 1: 0.2V</comment>
        </bits>
        <bits access="rw" name="ad0_volt_ref" pos="2" rst="1">
          <comment>bit type is changed from r/w to rw.
          ADC0 Voltage Reference. 0: 0.1V 1: 0.2V</comment>
        </bits>
        <bits access="rw" name="ad01_reset" pos="1" rst="1">
          <comment>bit type is changed from r/w to rw.
          ADC0 / ADC1 Reset</comment>
        </bits>
        <bits access="rw" name="ad01_pd" pos="0" rst="1">
          <comment>bit type is changed from r/w to rw.
          ADC0 / ADC1 Power Down</comment>
        </bits>
      </reg>
      <reg name="fgu_status" protect="r">
        <bits access="r" name="battery_flag" pos="8" rst="1">
          <comment>This flag indicates whether the battery is plugged in during power on sequence.</comment>
        </bits>
        <bits access="r" name="invalid_pocv" pos="7" rst="1">
          <comment>This flag indicates the power on open circuit voltage measurement is invalid.</comment>
        </bits>
        <bits access="r" name="fgu_ana_sel" pos="6" rst="1">
          <comment>Select current and voltage enable signal between fgu_top and fgu_ana 0: select fgu_ana current and voltage enable signal 1: select fgu_top current and voltage enable signal</comment>
        </bits>
        <bits access="r" name="power_low" pos="5" rst="1">
          <comment>Indicate the power is lower 0: not lower 1: lower Note: Case LOW_POWER_MODE = 0 when CURT_LOW is 1 and the relax counter is bigger than threshold, then the power is low. Case LOW_POWER_MODE = 1; The power mode select the deepsleep, then it is equal to deepsleep signal.</comment>
        </bits>
        <bits access="r" name="curt_low" pos="4" rst="1">
          <comment>Indicate the current is lower then threshold 0: not lower 1: lower Note: when CURT_LOW is occur, the POWER_LOW may not occur other than the relax count is bigger than threshold.</comment>
        </bits>
        <bits access="r" name="ocv_lock_sts" pos="3:2" rst="2">
          <comment>To update the Qmax, there should be two OCV lock. 2b00:  OCV0 not locked OCV1 not locked. 2b01:  OCV0 locked first OCV1 locked second. 2b10:  OCV0 locked first OCV1 locked second 2b11:  Invalid When both of them are locked, the Qmax is locked.</comment>
        </bits>
        <bits access="r" name="qmax_update_sts" pos="1" rst="1">
          <comment>Qmax updating status 0:  not in updating process. 1:  in updating process.</comment>
        </bits>
        <bits access="r" name="write_active_sts" pos="0" rst="1">
          <comment>When write following register, software should check this register to know whether it has been sync. to clk32KHz domain. FGU_CONFIG, ADC_CONFIG, FGU_INT_EN, FGU_HIGH_OVER, FGU_LOW_OVER, FGU_CLBCNT_SETH, FGU_CLBCNT_SETL</comment>
        </bits>
      </reg>
      <reg name="fgu_int_en" protect="rw">
        <bits access="rw" name="clbcnt_low_int_en" pos="9" rst="1">
          <comment>bit type is changed from r/w to rw.
          When the CLBCNT is lower than wet clbcnt low threshold , then interrupt</comment>
        </bits>
        <bits access="rw" name="ocv_low_int_en" pos="8" rst="1">
          <comment>bit type is changed from r/w to rw.
          When the OCV is lower than set ocv low threshold, then interrupt</comment>
        </bits>
        <bits access="rw" name="curt_rden_int_en" pos="7" rst="1">
          <comment>bit type is changed from r/w to rw.
          When Current data is ready, an interrupt is generated. It is used when calibration.</comment>
        </bits>
        <bits access="rw" name="volt_rden_int_en" pos="6" rst="1">
          <comment>bit type is changed from r/w to rw.
          When Voltage data is ready, an interrupt is generated.</comment>
        </bits>
        <bits access="rw" name="qmax_upd_tout_en" pos="5" rst="1">
          <comment>bit type is changed from r/w to rw.
          Qmax update timeout interrupt Enable</comment>
        </bits>
        <bits access="rw" name="qmax_upd_done_en" pos="4" rst="1">
          <comment>bit type is changed from r/w to rw.
          Qmax update done interrupt Enable</comment>
        </bits>
        <bits access="rw" name="relx_cnt_int_en" pos="3" rst="1">
          <comment>bit type is changed from r/w to rw.
          Relax Counter interrupt Enable. When the relax counter reached its set threshold, an interrupt is generated.</comment>
        </bits>
        <bits access="rw" name="clbcnt_delta_int_en" pos="2" rst="1">
          <comment>bit type is changed from r/w to rw.
          Coulomb counter  threshold interrupt Enable When the Coulomb counter reached the multiply of the threshold, then an interrupt is generated. E.g. If set CLBCNT_DELTA = 5mAh, then when the Coulomb counter is 5mAh, 10mAh, 15mAh will generate interrupt.</comment>
        </bits>
        <bits access="rw" name="volt_high_int_en" pos="1" rst="1">
          <comment>bit type is changed from r/w to rw.
          Voltage High overload interrupts Enable. When the voltage is higher than the threshold, then an interrupt is generated.</comment>
        </bits>
        <bits access="rw" name="volt_low_int_en" pos="0" rst="1">
          <comment>bit type is changed from r/w to rw.
          Voltage Low overload interrupt Enable. When the voltage is lower than the threshold, then an interrupt is generated.</comment>
        </bits>
      </reg>
      <reg name="fgu_int_clear" protect="w">
        <bits access="w" name="clbcnt_low_int_clr" pos="9" rst="1">
          <comment>CLBCNT lower interrupt clear</comment>
        </bits>
        <bits access="w" name="ocv_low_int_clr" pos="8" rst="1">
          <comment>OCV lower interrupt clear</comment>
        </bits>
        <bits access="w" name="curt_rden_int_clr" pos="7" rst="1">
          <comment>Current ready interrupt clear</comment>
        </bits>
        <bits access="w" name="volt_rden_int_clr" pos="6" rst="1">
          <comment>Voltage ready interrupt clear</comment>
        </bits>
        <bits access="w" name="qmax_upd_tout_clr" pos="5" rst="1">
          <comment>Qmax update timeout interrupt clear</comment>
        </bits>
        <bits access="w" name="qmax_upd_done_clr" pos="4" rst="1">
          <comment>Qmax update done interrupt clear</comment>
        </bits>
        <bits access="w" name="relx_cnt_int_clr" pos="3" rst="1">
          <comment>Relax counter interrupt clear</comment>
        </bits>
        <bits access="w" name="clbcnt_delta_int_clr" pos="2" rst="1">
          <comment>Coulomb counter delta interrupt clear</comment>
        </bits>
        <bits access="w" name="volt_high_int_clr" pos="1" rst="1">
          <comment>Voltage High overload interrupts clear.</comment>
        </bits>
        <bits access="w" name="volt_low_int_clr" pos="0" rst="1">
          <comment>Voltage Low overload interrupts clear.</comment>
        </bits>
      </reg>
      <reg name="fgu_int_raw" protect="r">
        <bits access="r" name="clbcnt_low_int_raw" pos="9" rst="1">
          <comment>CLBCNT lower interrupt raw status</comment>
        </bits>
        <bits access="r" name="ocv_low_int_raw" pos="8" rst="1">
          <comment>OCV lower interrupt raw status</comment>
        </bits>
        <bits access="r" name="curt_rden_int_raw" pos="7" rst="1">
          <comment>Current ready interrupt raw status</comment>
        </bits>
        <bits access="r" name="volt_rden_int_raw" pos="6" rst="1">
          <comment>Voltage ready interrupt raw status</comment>
        </bits>
        <bits access="r" name="qmax_upd_tout_raw" pos="5" rst="1">
          <comment>Qmax update timeout interrupt raw status</comment>
        </bits>
        <bits access="r" name="qmax_upd_done_raw" pos="4" rst="1">
          <comment>Qmax update done interrupt raw status</comment>
        </bits>
        <bits access="r" name="relx_cnt_int_raw" pos="3" rst="1">
          <comment>Relax counter interrupt raw status</comment>
        </bits>
        <bits access="r" name="clbcnt_delta_int_raw" pos="2" rst="1">
          <comment>Coulomb counter delta interrupt raw status</comment>
        </bits>
        <bits access="r" name="volt_high_int_raw" pos="1" rst="1">
          <comment>Voltage High overload interrupts raw status.</comment>
        </bits>
        <bits access="r" name="volt_low_int_raw" pos="0" rst="1">
          <comment>Voltage Low overload interrupts raw status.</comment>
        </bits>
      </reg>
      <reg name="fgu_int_sts" protect="r">
        <bits access="r" name="clbcnt_low_int_sts" pos="9" rst="1">
          <comment>CLBCNT lower interrupt status</comment>
        </bits>
        <bits access="r" name="ocv_low_int_sts" pos="8" rst="1">
          <comment>OCV lower interrupt status</comment>
        </bits>
        <bits access="r" name="curt_rden_int_sts" pos="7" rst="1">
          <comment>Current ready interrupt status</comment>
        </bits>
        <bits access="r" name="volt_rden_int_sts" pos="6" rst="1">
          <comment>Voltage ready interrupt status</comment>
        </bits>
        <bits access="r" name="qmax_upd_tout_sts" pos="5" rst="1">
          <comment>Qmax update timeout interrupt status</comment>
        </bits>
        <bits access="r" name="qmax_upd_done_sts" pos="4" rst="1">
          <comment>Qmax update done interrupt status</comment>
        </bits>
        <bits access="r" name="relx_cnt_int_sts" pos="3" rst="1">
          <comment>Relax counter interrupt status</comment>
        </bits>
        <bits access="r" name="clbcnt_delta_int_sts" pos="2" rst="1">
          <comment>Coulomb counter delta interrupt status</comment>
        </bits>
        <bits access="r" name="volt_high_int_sts" pos="1" rst="1">
          <comment>Voltage High overload interrupts status.</comment>
        </bits>
        <bits access="r" name="volt_low_int_sts" pos="0" rst="1">
          <comment>Voltage Low overload interrupts status.</comment>
        </bits>
      </reg>
      <reg name="fgu_volt_value" protect="r">
        <bits access="r" name="volt_value" pos="12:0" rst="11">
          <comment>Voltage now It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fgu_ocv_value" protect="r">
        <bits access="r" name="ocv_value" pos="12:0" rst="11">
          <comment>Open Circuit Voltage. It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13]  is omitted, and just 12 bit is valid It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fgu_pocv_value" protect="r">
        <bits access="r" name="pocv_value" pos="12:0" rst="11">
          <comment>Open Circuit Value read at the very beginning of 250ms</comment>
        </bits>
      </reg>
      <reg name="fgucurrentvalue" protect="r">
        <bits access="r" name="curt_value" pos="13:0" rst="12">
          <comment>Current now value, It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:   represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, its current is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fgu_high_over" protect="rw">
        <bits access="rw" name="fgu_high_over" pos="12:0" rst="11">
          <comment>bit type is changed from r/w to rw.
          Voltage High overload threshold. It is forbidden that the battery voltage is higher than the voltage max threshold. If it violates that, the battery may be destroyed.  Once it reaches this value, an interrupt is generated to notify the software to do something to deal with it. It is unsigned value, the unit is equal the  A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13]  is omitted, and just 12 bit is valid</comment>
        </bits>
      </reg>
      <reg name="fguvoltagelowoverload" protect="rw">
        <bits access="rw" name="fgu_low_over" pos="12:0" rst="11">
          <comment>bit type is changed from r/w to rw.
          Voltage low overload threshold. Once the battery voltage is lower than the set threshold, the device will not Work at any moment. To avoid the lost of data, the software should save the data and shut down the device when a lower threshold interrupt is generated. It is unsigned value, the unit is equal the  A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13]  is omitted, and just 12 bit is valid</comment>
        </bits>
      </reg>
      <reg name="fguvoltagehhthreshold" protect="rw">
        <bits access="rw" name="fgu_vthre_hh" pos="12:0" rst="11">
          <comment>bit type is changed from r/w to rw.
          Voltage High-High threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the high threshod of the locked high OCV. It is unsigned value, the unit is equal the  A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13]  is omitted, and just 12 bit is valid</comment>
        </bits>
      </reg>
      <reg name="fguvoltagehlthreshold" protect="rw">
        <bits access="rw" name="fgu_vthre_hl" pos="12:0" rst="11">
          <comment>bit type is changed from r/w to rw.
          Voltage High-Low threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the low threshold of the locked high OCV. It is unsigned value, the unit is equal the  A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13]  is omitted, and just 12 bit is valid</comment>
        </bits>
      </reg>
      <reg name="fguvoltagelhthreshold" protect="rw">
        <bits access="rw" name="fgu_vthre_lh" pos="12:0" rst="11">
          <comment>bit type is changed from r/w to rw.
          Voltage Low-High threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the high threshold of the locked low OCV. It is unsigned value, the unit is equal the  A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13]  is omitted, and just 12 bit is valid</comment>
        </bits>
      </reg>
      <reg name="fguvoltagellthreshold" protect="rw">
        <bits access="rw" name="fgu_vthre_ll" pos="12:0" rst="11">
          <comment>bit type is changed from r/w to rw.
          Voltage Low-Low threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the low threshold of the locked low OCV. It is unsigned value, the unit is equal the  A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13]  is omitted, and just 12 bit is valid</comment>
        </bits>
      </reg>
      <reg name="fguqmaxocvlocklo" protect="r">
        <bits access="r" name="fgu_ocv_locklo" pos="12:0" rst="11">
          <comment>Qmax OCV record Low point The Low OCV record of Qmax updated. It is unsigned value, the unit is equal the  A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000: represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0,then the bit [13]  is omitted, and just 12 bit is valid</comment>
        </bits>
      </reg>
      <reg name="fguqmaxocvlockhi" protect="r">
        <bits access="r" name="fgu_ocv_lockhi" pos="12:0" rst="11">
          <comment>Qmax OCV record High Point The High OCV record of Qmax updated. It is unsigned value, the unit is equal the  A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000: represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0,then the bit [13]  is omitted, and just 12 bit is valid</comment>
        </bits>
      </reg>
      <reg name="fgucoulombcountersethigh" protect="rw">
        <bits access="rw" name="clbcnt_seth" pos="13:0" rst="12">
          <comment>bit type is changed from r/w to rw.
          Set Coulomb Counter Value register, bit[29:16] In Work mode 2 of Current-Integration-based algorithm. The software can initial the coulomb counter by writing the value to this register, it Once the value is write to this register (with CLBCNT_SET_IND = 2h0, then the FGU_CLBCNT_VAL will be set to the same value, and the coulomb counter will count from this value. It is 2s Complement Code value 30h1FFF_FFFF:   represent the max positive point30h0:   represent the zero point30h2000_0000:   represent the min negative point
Note: the Coulomb Counter is 28 bits, and it is distributed in two register, after both of them are set, then it can be valid. When first write CLBCNT_SETH, then CLBCNT_SET_IND[1] is high to indicate it; second write CLBCNT_SETL, then CLBCNT_SET_IND[0] is high to indicate it, and after one clock, the CLBCNT_SET_IND[1] and CLBCNT_SET_IND[0] is auto clear to 0 to indicate both the register is write and stable.When first write CLBCNT_SETL, then CLBCNT_SET_IND[0] is high to indicate it; second write CLBCNT_SETH then CLBCNT_SET_IND[1] is high to indicate it, and after one clock, the CLBCNT_SET_IND[1] and CLBCNT_SET_IND[0] is auto clear to 0 to indicate both the register is write and stable.</comment>
        </bits>
      </reg>
      <reg name="fgucoulombcountersetlow" protect="rw">
        <bits access="rw" name="clbcnt_setl" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          Set Coulomb Counter Set Value register. bit[15:0]] In Work mode 2 of Current-Integration-based algorithm. The software can initial the coulomb counter by writing the value to this register, it Once the value is write to this register (with CLBCNT_H_IND =0 &amp; CLBCNT_L_IND = 0), then the FGU_CLBCNT_VAL will be set to the same value, and the coulomb counter will count from this value. It is 2s Complement Code value 30h1FFF_FFFF:   represent the max positive point30h0:  represent the zero point30h2000_0000:   represent the min negative point</comment>
        </bits>
      </reg>
      <reg name="fgucoulombcounterdeltahigh" protect="rw">
        <bits access="rw" name="clbcnt_delth" pos="13:0" rst="12">
          <comment>bit type is changed from r/w to rw.
          Coulomb Counter Delta register, bit[29:16] Once the coulomb is changed multiply of the Coulomb counter threshold, then an interrupt is generated to notify software to deal with the resolution. It is 2s Complement Code value 30h1FFF_FFFF:   represent the max positive point30h0: represent the zero point30h2000_0000:   represent the min negative point</comment>
        </bits>
      </reg>
      <reg name="fgucoulombcounterdeltalow" protect="rw">
        <bits access="rw" name="clbcnt_deltl" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          Coulomb Counter Delta register, bit[:15:0] Once the coulomb is changed multiply of the Coulomb counter delta threshold, then an interrupt is generated to notify software to deal with the resolution. It is 2s Complement Code value 30h1FFF_FFFF:  represent the max positive point30h0:  represent the zero point30h2000_0000:   represent the min negative point</comment>
        </bits>
      </reg>
      <reg name="fgucoulombcounterlastocvhigh" protect="r">
        <bits access="r" name="clbcnt_lastocvh" pos="15:0" rst="14">
          <comment>Coulomb Counter Last OCV register, bit[31:16] This register indicated the coulomb counter value changed after the OCV is locked. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF:   max positive point32h0:  zero point 32hE000_0000:   min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value point</comment>
        </bits>
      </reg>
      <reg name="fgucoulombcounterlastocvlow" protect="r">
        <bits access="r" name="clbcnt_lastocvl" pos="15:0" rst="14">
          <comment>Coulomb Counter Last OCV register, bit[15:0] This register indicated the coulomb counter value changed after the OCV is locked. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF:   max positive point32h0: zero point32hE000_0000:   min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value</comment>
        </bits>
      </reg>
      <reg name="fgucoulombcountervaluehigh" protect="r">
        <bits access="r" name="clbcnt_valh" pos="15:0" rst="14">
          <comment>Coulomb Counter Value register, bit[31:16] This register is accumulate once every charge is coming, and it is can be set by CLBCNT_SET register at any moment. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF:   maxpositive point32h0:  zero point32hE000_0000:   min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value</comment>
        </bits>
      </reg>
      <reg name="fgu_clbcnt_vall" protect="r">
        <bits access="r" name="clbcnt_vall" pos="15:0" rst="14">
          <comment>Coulomb Counter Value register, bit[15:0] This register is accumulate once every charge is coming, and it is can be set by CLBCNT_SET register at any moment. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF:   max positive point32h0:  zero point32hE000_0000:   min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value</comment>
        </bits>
      </reg>
      <reg name="fgu_clbcnt_qmaxh" protect="r">
        <bits access="r" name="clbcnt_qmaxh" pos="15:0" rst="14">
          <comment>Coulomb Counter Qmax Value, bit[31:16] It is used to record the Qmax value when the Qmax process is used. It is read only. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF:   max positive point32h0:   zero point32hE000_0000:   min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value</comment>
        </bits>
      </reg>
      <reg name="fgu_clbcnt_qmaxl" protect="r">
        <bits access="r" name="clbcnt_qmaxl" pos="15:0" rst="14">
          <comment>Coulomb Counter Qmax Value, bit[15:0] It is used to record the Qmax value when the Qmax process is used. It is read only. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF:   max positive point32h0: zero point32hE000_0000:   min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value Note: after Power On, it saved the first sampled Curt data, unsigned, and just 250ms data.14bits. or said POCI.</comment>
        </bits>
      </reg>
      <reg name="fguqmaxtimeoutset" protect="rw">
        <bits access="rw" name="qmax_timeout_set" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          FGU Qmax timeout set counter. When the Qmax update exceed the timeout set counter, then the Qmax quit and it is failed to update. The unit of the counter is 4 seconds, so the max value is 72.8 hours. Note: when the QMAX_TIMEOUT_CNT is 0, it means it is never timeout.</comment>
        </bits>
      </reg>
      <reg name="fguqmaxtimercounter" protect="r">
        <bits access="r" name="qmax_timer_cnt" pos="15:0" rst="14">
          <comment>FGU Qmax timer counter. Once the Qmax is updating, the timer is counted from 0. After the Qmax is updated, the timer is stay on the last value until the next update process start. The unit of the counter is 4 seconds, so the max value is 72.8 hours.</comment>
        </bits>
      </reg>
      <reg name="fgurelaxcurrentthreshold" protect="rw">
        <bits access="rw" name="relax_curt_thre" pos="13:0" rst="12">
          <comment>bit type is changed from r/w to rw.
          Relax Current threshold. It is unsigned value, It is a tiny value which will add or subtract the zero value (14h1FFF) of the CURT_VALUE, to indicate a low current threshold. And it will define the conception of Relax State: When current value of CURT_VALUE bigger than (14h1FFF-CURT_THRE) and smaller than (14h1FFF + CURT_THRE), the battery will work in Relax state. And then the relax counter will work to count, else it clear to 0.</comment>
        </bits>
      </reg>
      <reg name="fgu_relx_cnt_thre" protect="rw">
        <bits access="rw" name="relx_cnt_thre" pos="12:0" rst="11">
          <comment>bit type is changed from r/w to rw.
          Relax counter threshold. When the counter reaches to this value, it stops at this value. The unit is 1 second. 13h1 means 1 second</comment>
        </bits>
      </reg>
      <reg name="fgu_relx_cnt_val" protect="r">
        <bits access="r" name="relx_cnt_val" pos="12:0" rst="11">
          <comment>Relax counter value. The relax counter register is 13 bit read-only register clocked every 1s and can go up to about 2hs. The counter is auto clearer to 0 when the current is out of the relax state. Definition of Relax State: When current value of CURT_VALUE bigger than (14h1FFF-CURT_THRE) and smaller than (14h1FFF + CURT_THRE), the battery will work in Relax state.</comment>
        </bits>
      </reg>
      <reg name="fgu_ocv_last_cnt" protect="r">
        <bits access="r" name="ocv_last_cnt" pos="12:0" rst="11">
          <comment>OCV Last count. After the OCV is locked, this counter will count how many times it keeps The unit is 1 second, and the max count is about 9 hours, if the count is bigger than 18hrs, than the count is keep its max value 16hFFFF.</comment>
        </bits>
      </reg>
      <reg name="fgu_curt_offset_value" protect="r">
        <bits access="r" name="curt_offset_value" pos="13:0" rst="12">
          <comment>Current offset value, It is signed value, and 2s complement value. Used to adjust the calibration current value.</comment>
        </bits>
      </reg>
      <reg name="reserved1" protect="rw">
      </reg>
      <reg name="reserved2" protect="rw">
      </reg>
      <reg name="reserved3" protect="rw">
      </reg>
      <reg name="fguuserareaset0" protect="rw">
        <bits access="rw" name="user_area_set0" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          For software to set this area, where the data will be kept in USER_AREA_STS0 if the RTC clock is working.</comment>
        </bits>
      </reg>
      <reg name="fguuserareaclear0" protect="rw">
        <bits access="rw" name="user_area_clr0" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          For software to clear this area, Set 1, the data kept in USER_AREA_STS0 will be cleared. Set 0, after clearing the status, the register value will be set back to 0</comment>
        </bits>
      </reg>
      <reg name="fguuserareastatus0" protect="r">
        <bits access="r" name="user_area_sts0" pos="15:0" rst="14">
          <comment>The data will be kept in if RTC clock is working</comment>
        </bits>
      </reg>
      <reg name="reserved4" protect="rw">
      </reg>
      <reg name="fguocivalue" protect="r">
        <bits access="r" name="fgu_oci" pos="15:0" rst="14">
          <comment>Open Circuit Current. Refer to the Current Value.</comment>
        </bits>
      </reg>
      <reg name="fguocvlowthreshold" protect="rw">
        <bits access="rw" name="fgu_ocv_low_thre" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          The OCV low threshold. When the real OCV lower than this register, then an interrupt is occurred.</comment>
        </bits>
      </reg>
      <reg name="fguclbcntlowthresholdhigh" protect="rw">
        <bits access="rw" name="fgu_clbcnt_lthre_h" pos="13:0" rst="12">
          <comment>bit type is changed from r/w to rw.
          The CLBCNT low threshold. When the real CLBCNT lower than this register, then an interrupt is occurred. Its higer part.</comment>
        </bits>
      </reg>
      <reg name="fguclbcntlowthresholdlow" protect="rw">
        <bits access="rw" name="fgu_clbcnt_lthre_l" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          The CLBCNT low threshold. When the real CLBCNT lower than this register, then an interrupt is occurred.</comment>
        </bits>
      </reg>
      <reg name="fguuserareaset1" protect="rw">
        <bits access="rw" name="user_area_set1" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          For software to set this area, where the data will be kept in USER_AREA_STS1 if the RTC clock is working.</comment>
        </bits>
      </reg>
      <reg name="fguuserareaclear1" protect="rw">
        <bits access="rw" name="user_area_clr1" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          For software to clear this area, Set 1, the data kept in USER_AREA_STS1 will be cleared. Set 0, after clearing the status, the register value will be set back to 0</comment>
        </bits>
      </reg>
      <reg name="fguuserareastatus1" protect="r">
        <bits access="r" name="user_area_sts1" pos="15:0" rst="14">
          <comment>The data will be kept in if RTC clock is working</comment>
        </bits>
      </reg>
      <reg name="fgulegacyocvvalue" protect="r">
        <bits access="r" name="legacy_ocv_value" pos="12:0" rst="11">
          <comment>Power On Open Circuit Voltage. If is just valid when the very time of power on . It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, it voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13]  is omitted, and just 12 bit is valid It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fguvoltvaluebuf0" protect="r">
        <bits access="r" name="volt_value_buf0" pos="12:0" rst="11">
          <comment>This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, it voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fguvoltvaluebuf1" protect="r">
        <bits access="r" name="volt_value_buf1" pos="12:0" rst="11">
          <comment>This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, it voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fguvoltvaluebuf2" protect="r">
        <bits access="r" name="volt_value_buf2" pos="12:0" rst="11">
          <comment>This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, it voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fguvoltvaluebuf3" protect="r">
        <bits access="r" name="volt_value_buf3" pos="12:0" rst="11">
          <comment>This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, it voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fguvoltvaluebuf4" protect="r">
        <bits access="r" name="volt_value_buf4" pos="12:0" rst="11">
          <comment>This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, it voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fguvoltvaluebuf5" protect="r">
        <bits access="r" name="volt_value_buf5" pos="12:0" rst="11">
          <comment>This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, it voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fguvoltvaluebuf6" protect="r">
        <bits access="r" name="volt_value_buf6" pos="12:0" rst="11">
          <comment>This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, it voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fguvoltvaluebuf7" protect="r">
        <bits access="r" name="volt_value_buf7" pos="12:0" rst="11">
          <comment>This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, it voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fgucurtvaluebuf0" protect="r">
        <bits access="r" name="curt_value_buf0" pos="13:0" rst="12">
          <comment>This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:   represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, it voltage is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fgucurtvaluebuf1" protect="r">
        <bits access="r" name="curt_value_buf1" pos="13:0" rst="12">
          <comment>This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:   represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, it voltage is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fgucurtvaluebuf2" protect="r">
        <bits access="r" name="curt_value_buf2" pos="13:0" rst="12">
          <comment>This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:   represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, it voltage is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fgucurtvaluebuf3" protect="r">
        <bits access="r" name="curt_value_buf3" pos="13:0" rst="12">
          <comment>This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:   represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, it voltage is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fgucurtvaluebuf4" protect="r">
        <bits access="r" name="curt_value_buf4" pos="13:0" rst="12">
          <comment>This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:   represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, it voltage is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fgucurtvaluebuf5" protect="r">
        <bits access="r" name="curt_value_buf5" pos="13:0" rst="12">
          <comment>This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:   represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, it voltage is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fgucurtvaluebuf6" protect="r">
        <bits access="r" name="curt_value_buf6" pos="13:0" rst="12">
          <comment>This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:   represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, it voltage is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fgucurtvaluebuf7" protect="r">
        <bits access="r" name="curt_value_buf7" pos="13:0" rst="12">
          <comment>This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:   represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, it voltage is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fguqmaxocilocklo" protect="r">
        <bits access="r" name="fgu_oci_locklo" pos="13:0" rst="12">
          <comment>Qmax Lock Low Point current value It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000: represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, its current is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fguqmaxocilockhi" protect="r">
        <bits access="r" name="fgu_oci_lockhi" pos="13:0" rst="12">
          <comment>Qmax Lock High Point current value It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, its current is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fguocvvaluedebug" protect="r">
        <bits access="r" name="ocv_debug_value" pos="12:0" rst="11">
          <comment>Legacy Open Circuit Voltage Value for Debug It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value.</comment>
        </bits>
      </reg>
      <reg name="fguatecfg" protect="rw">
        <bits access="rw" name="ate_data_sel" pos="6" rst="1">
          <comment>bit type is changed from r/w to rw.
          Select which type of data being shit out to pad 0: current value 1: voltage value</comment>
        </bits>
        <bits access="rw" name="ate_v_mode" pos="5:3" rst="3">
          <comment>bit type is changed from r/w to rw.
          ATE test voltage time mode 3b000:  15.6ms 3b001:  31.25ms 3b010:  62.5ms 3b011:  125ms 3b100:  250ms 3b101:  500ms</comment>
        </bits>
        <bits access="rw" name="ate_i_mode" pos="2:0" rst="3">
          <comment>bit type is changed from r/w to rw.
          ATE test current time mode 3b000:  15.6ms 3b001:  31.25ms 3b010:  62.5ms 3b011:  125ms 3b100:  250ms 3b101:  500ms</comment>
        </bits>
      </reg>
      <reg name="?fguatecurt" protect="r">
        <bits access="r" name="ate_curt_value" pos="13:0" rst="12">
          <comment>ATE test current value saved register It is unsigned value, but represents signed value. The unit is equal the  A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF:   represent the max point14h2000:   represent the zero point14h0:     :   represent the min point That means when the value is 14h2000, its current is 0 A.  Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value</comment>
        </bits>
      </reg>
      <reg name="fguatevolt" protect="r">
        <bits access="r" name="ate_vol_value" pos="12:0" rst="11">
          <comment>ATE test voltage value saved register It is unsigned value, the unit is equal the  A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF:  represent the max point13h1000:  represent the zero point &lt;13h1000: invalid That means when the value is 13h1000, its voltage is 0 V.  Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_global.xml">
    <module category="RDA2720M" name="RDA2720M_GLOBAL">
      <reg name="chip_id_low" protect="r">
        <bits access="r" name="chip_ip_low" pos="15:0" rst="40960">
          <comment>CHIP ID low 16 bits</comment>
        </bits>
      </reg>
      <reg name="chip_id_high" protect="r">
        <bits access="r" name="chip_id_high" pos="15:0" rst="10016">
          <comment>CHIP ID high 16 bits</comment>
        </bits>
      </reg>
      <reg name="module_en0" protect="rw">
        <bits access="rw" name="tmr_en" pos="12" rst="0">
          <comment>TMR module enable 0: Disable the PCLK  of timer 1: Enable  the PCLK  of timer</comment>
        </bits>
        <bits access="rw" name="psm_en" pos="10" rst="0">
          <comment>PSM module enable 0: Disable the PCLK  of PSM 1: Enable  the PCLK  of PSM</comment>
        </bits>
        <bits access="rw" name="bltc_en" pos="9" rst="0">
          <comment>BLTC module enable 0: Disable the PCLK  of BLTC 1: Enable  the PCLK  of BLTC</comment>
        </bits>
        <bits access="rw" name="pinreg_en" pos="8" rst="1">
          <comment>PINREG module enable 0: Disable the PCLK  of pin registers 1: Enable  the PCLK  of pin registers</comment>
        </bits>
        <bits access="rw" name="fgu_en" pos="7" rst="0">
          <comment>FGU module enable 0: Disable the PCLK  of FGU 1: Enable  the PCLK  of FGU</comment>
        </bits>
        <bits access="rw" name="efs_en" pos="6" rst="0">
          <comment>Efuse module enable 0: Disable the PCLK  of efuse ctrl 1: Enable  the PCLK  of efuse ctrl</comment>
        </bits>
        <bits access="rw" name="adc_en" pos="5" rst="0">
          <comment>AUXADC module enable 0: Disable the PCLK  of AUXADC 1: Enable  the PCLK  of AUXADC</comment>
        </bits>
        <bits access="rw" name="aud_en" pos="4" rst="0">
          <comment>Audio  module enable 0: Disable the PCLK  of Audio 1: Enable  the PCLK  of Audio</comment>
        </bits>
        <bits access="rw" name="eic_en" pos="3" rst="0">
          <comment>EIC module enable 0: Disable the PCLK  of EIC 1: Enable  the PCLK  of EIC</comment>
        </bits>
        <bits access="rw" name="wdg_en" pos="2" rst="0">
          <comment>WDG module enable 0: Disable the PCLK  of watchdog 1: Enable  the PCLK  of watchdog</comment>
        </bits>
        <bits access="rw" name="rtc_en" pos="1" rst="1">
          <comment>RTC module enable 0: Disable the PCLK  of RTC 1: Enable  the PCLK  of RTC</comment>
        </bits>
        <bits access="rw" name="cal_en" pos="0" rst="0">
          <comment>CAL module enable 0: Disable the PCLK  of CAL 1: Enable  the PCLK  of CAL</comment>
        </bits>
      </reg>
      <reg name="arm_clk_en0" protect="rw">
        <bits access="rw" name="clk_auxad_en" pos="6" rst="0">
          <comment>AUXAD clock enable, the clock is connected to AUXADC converter 0: disable AUXAD_CLK 1: enable AUXAD_CLK</comment>
        </bits>
        <bits access="rw" name="clk_auxadc_en" pos="5" rst="0">
          <comment>AUXADC module work clock enable 0: disable clk_adc 1: enable clk_adc</comment>
        </bits>
        <bits access="rw" name="clk_cal_src_sel" pos="4:3" rst="0">
          <comment>Calibration module clock source select                  2'b00: 32K-less 1MHZ clock                                       2'b01: DCDC_CLK2M_OUT                                         2'b10: DCDC_CLK3M_OUT                                         2'b11: N/A</comment>
        </bits>
        <bits access="rw" name="clk_cal_en" pos="2" rst="0">
          <comment>CLK_CAL eanble 0: disable clk_cal 1: enable clk_cal</comment>
        </bits>
        <bits access="rw" name="clk_aud_if_6p5m_en" pos="1" rst="0">
          <comment>Audio 6.5M clock enable 0: disable clk_aud_6p5m_rx  and clk_aud_6p5m_tx 1: enable clk_aud_6p5m_rx  and clk_aud_6p5m_tx</comment>
        </bits>
        <bits access="rw" name="clk_aud_if_en" pos="0" rst="0">
          <comment>Audio IF clock enable 0: disable CLK_AUDIF 1: enable CLK_AUDIF</comment>
        </bits>
      </reg>
      <reg name="rtc_clk_en0" protect="rw">
        <bits access="rw" name="rtc_tmr_en" pos="13" rst="0">
          <comment>TIMER RTC clock soft enable 0: Disable the RTC clock of timer 1: Enable RTC clock of timer</comment>
        </bits>
        <bits access="rw" name="rtc_flash_en" pos="12" rst="0">
          <comment>FLASH controller RTC clock enable 0: Disable the RTC clock of FLASH controller 1: Enable RTC clock of FLASH controller</comment>
        </bits>
        <bits access="rw" name="rtc_efs_en" pos="11" rst="1">
          <comment>EFS RTC clock soft enable 0: Disable the RTC clock of EFS 1: Enable RTC clock of EFS</comment>
        </bits>
        <bits access="rw" name="rtc_bltc_en" pos="7" rst="0">
          <comment>BLTC RTC clock soft enable 0: Disable the RTC clock of BLTC 1: Enable RTC clock of BLTC</comment>
        </bits>
        <bits access="rw" name="rtc_fgu_en" pos="6" rst="1">
          <comment>FGU RTC clock soft enable 0: Disable the RTC clock of FGU 1: Enable RTC clock of FGU</comment>
        </bits>
        <bits access="rw" name="rtc_eic_en" pos="3" rst="0">
          <comment>EIC RTC clock soft enable 0: Disable the RTC clock of EIC 1: Enable RTC clock of EIC</comment>
        </bits>
        <bits access="rw" name="rtc_wdg_en" pos="2" rst="0">
          <comment>Watchdog RTC clock soft enable 0: Disable the RTC clock of Watchdog 1: Enable RTC clock of Watchdo</comment>
        </bits>
        <bits access="rw" name="rtc_rtc_en" pos="1" rst="1">
          <comment>RTC RTC clock soft enable 0: Disable the RTC clock of RTC 1: Enable RTC clock of RTC</comment>
        </bits>
        <bits access="rw" name="rtc_arch_en" pos="0" rst="1">
          <comment>ARCH RTC clock soft enable 0: Disable the RTC clock of ARCH 1: Enable RTC clock of ARCH</comment>
        </bits>
      </reg>
      <reg name="soft_rst0" protect="rw">
        <bits access="rw" name="audrx_soft_rst" pos="13" rst="0">
          <comment>AUD RX soft reset</comment>
        </bits>
        <bits access="rw" name="audtx_soft_rst" pos="12" rst="0">
          <comment>AUD TX soft reset</comment>
        </bits>
        <bits access="rw" name="bltc_soft_rst" pos="9" rst="0">
          <comment>BLTC soft reset</comment>
        </bits>
        <bits access="rw" name="aud_if_soft_rst" pos="8" rst="0">
          <comment>Audio IF soft reset</comment>
        </bits>
        <bits access="rw" name="efs_soft_rst" pos="7" rst="0">
          <comment>Efuse soft reset</comment>
        </bits>
        <bits access="rw" name="adc_soft_rst" pos="6" rst="0">
          <comment>Auxadc soft reset</comment>
        </bits>
        <bits access="rw" name="psm_soft_rst" pos="5" rst="0">
          <comment>PSM apb soft reset</comment>
        </bits>
        <bits access="rw" name="fgu_soft_rst" pos="4" rst="0">
          <comment>FGU soft reset</comment>
        </bits>
        <bits access="rw" name="eic_soft_rst" pos="3" rst="0">
          <comment>EIC soft reset</comment>
        </bits>
        <bits access="rw" name="wdg_soft_rst" pos="2" rst="0">
          <comment>Watchdog soft reset</comment>
        </bits>
        <bits access="rw" name="rtc_soft_rst" pos="1" rst="0">
          <comment>RTC soft reset</comment>
        </bits>
        <bits access="rw" name="cal_soft_rst" pos="0" rst="0">
          <comment>CAL soft reset</comment>
        </bits>
      </reg>
      <reg name="soft_rst1" protect="rw">
        <bits access="rw" name="tmr_soft_rst" pos="1" rst="0">
          <comment>TMR soft reset</comment>
        </bits>
      </reg>
      <reg name="power_pd_sw" protect="rw">
        <bits access="rw" name="ldo_dcxo_pd" pos="10" rst="0">
          <comment>LDO_DCXO power down                                           1: power down                                                                0: power on</comment>
        </bits>
        <bits access="rw" name="ldo_emm_pd" pos="9" rst="0">
          <comment>EMM domain power down                                            1: power down                                                                0: power on</comment>
        </bits>
        <bits access="rw" name="ldo_cp_pd" pos="8" rst="0">
          <comment>LDO of charge pump power down 1: power down 0: power on</comment>
        </bits>
        <bits access="rw" name="dcdc_gen_pd" pos="7" rst="0">
          <comment>DCDC_GEN power down                                          1: power down                                                                0: power on</comment>
        </bits>
        <bits access="rw" name="dcdc_core_pd" pos="5" rst="0">
          <comment>DCDC_CORE power down                                          1: power down                                                                0: power on</comment>
        </bits>
        <bits access="rw" name="osc3m_en" pos="4" rst="1">
          <comment>internal oscillator enable 1'b0: oscillator off 1'b1: oscillator on</comment>
        </bits>
        <bits access="rw" name="ldo_mem_pd" pos="3" rst="0">
          <comment>LDO_MEM  power down                                                 1: power down                                                                0: power on</comment>
        </bits>
        <bits access="rw" name="ldo_ana_pd" pos="2" rst="0">
          <comment>LDO_ANA  power down                                                 1: power down                                                                0: power on</comment>
        </bits>
        <bits access="rw" name="ldo_vdd28_pd" pos="1" rst="0">
          <comment>LDO_VDD28 power down                                                 1: power down                                                                0: power on</comment>
        </bits>
        <bits access="rw" name="bg_pd" pos="0" rst="0">
          <comment>Bandgap power down                                                 1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="power_pd_hw" protect="rw">
        <bits access="rw" name="pwr_off_seq_en" pos="0" rst="0">
          <comment>Power off_sequence enable</comment>
        </bits>
      </reg>
      <reg name="soft_rst_hw" protect="rw">
        <bits access="rw" name="reg_soft_rst" pos="0" rst="0">
          <comment>register soft reset,write 1 can: 1 reset total system 2 power down and up</comment>
        </bits>
      </reg>
      <reg name="reserved_reg1" protect="r">
      </reg>
      <reg name="reserved_reg2" protect="r">
      </reg>
      <reg name="reserved_reg3" protect="r">
      </reg>
      <reg name="dcdc_clk_reg0" protect="rw">
        <bits access="rw" name="clk3m_out_en" pos="11" rst="0">
          <comment>clock output enable</comment>
        </bits>
        <bits access="rw" name="clkout_uniphase" pos="10" rst="0">
          <comment>phase shift option 1'b0: default, w/i 1/5 phase shift at internal mode 1'b1: uni-phase mode, all ouputs = channel 0</comment>
        </bits>
        <bits access="rw" name="clkout_sel" pos="9:7" rst="0">
          <comment>clock selection for each channel RG_CLKOUT_SEL&lt;0&gt;:  VCORE clk selection RG_CLKOUT_SEL&lt;1&gt;:  VGEN clk selection RG_CLKOUT_SEL&lt;2&gt;:  VPA clk selection 0: internal mode, default 1: external mode</comment>
        </bits>
        <bits access="rw" name="dcdc_gen_clk_rst" pos="4" rst="0">
          <comment>soft reset of all dcdc generated clk</comment>
        </bits>
        <bits access="rw" name="osc3m_freq" pos="3:0" rst="0">
          <comment>oscillator frequency tuing, (1/16)/step 4'b0000: default 3MHz 4'b0001: -1 step 4'b0111: -7 step 4'b1000: +8 step 4'b1111: +1 step</comment>
        </bits>
      </reg>
      <reg name="dcdc_core_reg0" protect="rw">
        <bits access="rw" name="curlimit_r_vcore" pos="15:14" rst="0">
          <comment>current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20%</comment>
        </bits>
        <bits access="rw" name="curses_r_vcore" pos="13:12" rst="0">
          <comment>current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20%</comment>
        </bits>
        <bits access="rw" name="pfm_vh_vcore" pos="11:10" rst="0">
          <comment>PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V</comment>
        </bits>
        <bits access="rw" name="rcomp_vcore" pos="9:8" rst="0">
          <comment>compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k</comment>
        </bits>
        <bits access="rw" name="slope_vcore" pos="7:6" rst="0">
          <comment>slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x</comment>
        </bits>
        <bits access="rw" name="sr_hs_vcore" pos="5:4" rst="0">
          <comment>high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x</comment>
        </bits>
        <bits access="rw" name="sr_ls_vcore" pos="3:2" rst="0">
          <comment>low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x</comment>
        </bits>
        <bits access="rw" name="zx_offset_vcore" pos="1:0" rst="0">
          <comment>zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset</comment>
        </bits>
      </reg>
      <reg name="dcdc_core_reg1" protect="rw">
        <bits access="rw" name="votrim_vcore" pos="5:3" rst="0">
          <comment>reference voltage trimming (base on 1.2V) 3'b000: default 3'b001: +12.5mV 3'b010: +25mV 3'b011: +37.5mV 3'b100: -50mV 3'b101: -37.5mV 3'b110: -25mV 3'b111: -12.5mV</comment>
        </bits>
        <bits access="rw" name="zx_disable_vcore" pos="2" rst="0">
          <comment>force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off</comment>
        </bits>
        <bits access="rw" name="force_pwm_vcore" pos="1" rst="0">
          <comment>force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode</comment>
        </bits>
        <bits access="rw" name="anriting_en_vcore" pos="0" rst="0">
          <comment>anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on</comment>
        </bits>
      </reg>
      <reg name="dcdc_core_reg2" protect="rw">
        <bits access="rw" name="div_clk_vcore_en" pos="12" rst="0">
          <comment>clock gating enable</comment>
        </bits>
        <bits access="rw" name="phase_sel_vcore" pos="11:6" rst="0">
          <comment>the phase difference, 26M per step</comment>
        </bits>
        <bits access="rw" name="div_base_vcore" pos="5:0" rst="15">
          <comment>the division factor from 26M for DCDCCORE, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 26'h3F: divide by 64</comment>
        </bits>
      </reg>
      <reg name="dcdc_core_vol" protect="rw">
        <bits access="rw" name="vosel_vcore" pos="8:0" rst="288">
          <comment>output voltage selection, 3.125mV/step 9'b111100000: 1.5V 9'b111000000: 1.4V 9'b110100000: 1.3V 9'b110000000: 1.2V 9'b101100000: 1.1V 9'b101000000: 1.0V 9'b100100000: 0.9V 9'b100000000: 0.8V 9'b011100000: 0.7V 9'b011000000: 0.6V</comment>
        </bits>
      </reg>
      <reg name="dcdc_gen_reg0" protect="rw">
        <bits access="rw" name="curlimit_r_vgen" pos="15:14" rst="0">
          <comment>current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20%</comment>
        </bits>
        <bits access="rw" name="curses_r_vgen" pos="13:12" rst="0">
          <comment>current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20%</comment>
        </bits>
        <bits access="rw" name="pfm_vh_vgen" pos="11:10" rst="0">
          <comment>PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V</comment>
        </bits>
        <bits access="rw" name="rcomp_vgen" pos="9:8" rst="0">
          <comment>compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k</comment>
        </bits>
        <bits access="rw" name="slope_vgen" pos="7:6" rst="0">
          <comment>slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x</comment>
        </bits>
        <bits access="rw" name="sr_hs_vgen" pos="5:4" rst="0">
          <comment>high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x</comment>
        </bits>
        <bits access="rw" name="sr_ls_vgen" pos="3:2" rst="0">
          <comment>low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x</comment>
        </bits>
        <bits access="rw" name="zx_offset_vgen" pos="1:0" rst="0">
          <comment>zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset</comment>
        </bits>
      </reg>
      <reg name="dcdc_gen_reg1" protect="rw">
        <bits access="rw" name="zx_disable_vgen" pos="3" rst="0">
          <comment>force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off</comment>
        </bits>
        <bits access="rw" name="maxduty_sel_vgen" pos="2" rst="0">
          <comment>reserved</comment>
        </bits>
        <bits access="rw" name="force_pwm_vgen" pos="1" rst="0">
          <comment>force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode</comment>
        </bits>
        <bits access="rw" name="anriting_en_vgen" pos="0" rst="0">
          <comment>anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on</comment>
        </bits>
      </reg>
      <reg name="dcdc_gen_reg2" protect="rw">
        <bits access="rw" name="div_clk_vgen_en" pos="12" rst="0">
          <comment>clock gating enable</comment>
        </bits>
        <bits access="rw" name="phase_sel_vgen" pos="11:6" rst="0">
          <comment>the phase difference, 26M per step</comment>
        </bits>
        <bits access="rw" name="div_base_vgen" pos="5:0" rst="15">
          <comment>the division factor from 26M for DCDCGEN, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 26'h3F: divide by 64</comment>
        </bits>
      </reg>
      <reg name="dcdc_gen_vol" protect="rw">
        <bits access="rw" name="vosel_vgen" pos="7:0" rst="44">
          <comment>output voltage selection, 12.5mV/step. 8'b00000000= 1.3V 8'b00001000= 1.4V 8'b00010000= 1.5V 8'b00011000= 1.6V 8'b00100000= 1.7V 8'b00101000= 1.8V 8'b00110000= 1.9V 8'b00111000= 2.0V 8'b01000000= 2.1V 8'b01001000= 2.2V 8'b01010000= 2.3V 8'b01011000= 2.4V 8'b01100000= 2.5V 8'b01101000= 2.6V 8'b01110000= 2.7V 8'b01111000= 2.8V</comment>
        </bits>
      </reg>
      <reg name="dcdc_wpa_reg0" protect="rw">
        <bits access="rw" name="curlimit_r_vpa" pos="15:14" rst="0">
          <comment>current limit threshold tuning 2'b00: default 2'b01: -0.5pF 2'b10: +1pF 2'b11: +0.5pF</comment>
        </bits>
        <bits access="rw" name="curses_m_vpa" pos="13:12" rst="0">
          <comment>current sense multiplier tuning 2'b00: default, x1 2'b01: x0.5 2'b10: x2 2'b11: x1.5</comment>
        </bits>
        <bits access="rw" name="ccomp3_vpa" pos="11:10" rst="0">
          <comment>compensation C3 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20%</comment>
        </bits>
        <bits access="rw" name="pfm_threshold_vpa" pos="9:8" rst="0">
          <comment>PFM mode threshold for upper limit 2'b00: default 2'b01: -50mV 2'b10: +50mV 2'b11: +100mV</comment>
        </bits>
        <bits access="rw" name="rcomp2_vpa" pos="7:6" rst="0">
          <comment>compensation R2 select 2'b00: default, 960k 2'b01: 880k 2'b10: 1040k 2'b11: 1120k</comment>
        </bits>
        <bits access="rw" name="rcomp3_vpa" pos="5:4" rst="0">
          <comment>compensation R3 select 2'b00: default, 5k 2'b01: 2.5k 2'b10: 10k 2'b11: 7.5k</comment>
        </bits>
        <bits access="rw" name="sawtooth_slope_vpa" pos="3:2" rst="0">
          <comment>sawtooth tuning manully 2'b00: default 2'b01: +15% 2'b10: -30% 2'b11: -15%</comment>
        </bits>
        <bits access="rw" name="sr_hs_vpa" pos="1:0" rst="0">
          <comment>high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x</comment>
        </bits>
      </reg>
      <reg name="dcdc_wpa_reg1" protect="rw">
        <bits access="rw" name="sr_ls_vpa" pos="15:14" rst="0">
          <comment>low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x</comment>
        </bits>
        <bits access="rw" name="votrim_vpa" pos="13:11" rst="0">
      </bits>
        <bits access="rw" name="zx_offset_vpa" pos="10:9" rst="0">
          <comment>zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset</comment>
        </bits>
        <bits access="rw" name="anriting_en_vpa" pos="8" rst="0">
          <comment>anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on</comment>
        </bits>
        <bits access="rw" name="apc_enable_vpa" pos="7" rst="0">
          <comment>APC mode enable 1'b0: default, RG control mode 1'b1: APC mode</comment>
        </bits>
        <bits access="rw" name="apc_ramp_sel_vpa" pos="6" rst="0">
          <comment>APC ramp selection 1'b0: default, 2.0x ramp 1'b1: 2.5x ramp</comment>
        </bits>
        <bits access="rw" name="bypass_disable_vpa" pos="5" rst="0">
          <comment>bypass mode disable 1'b0: default, auto bypass 1'b1: bypass off</comment>
        </bits>
        <bits access="rw" name="bypass_forceon_vpa" pos="4" rst="0">
          <comment>bypass force on 1'b0: default, auto bypass 1'b1: force bypass mode on</comment>
        </bits>
        <bits access="rw" name="bypass_threshold_vpa" pos="3:2" rst="0">
          <comment>bypass mode threshold 2'b00: default, ~200mV</comment>
        </bits>
        <bits access="rw" name="dvs_on_vpa" pos="1" rst="0">
          <comment>DVS control 1'b0: default, off 1'b0: on, for DCM down discharge</comment>
        </bits>
        <bits access="rw" name="maxduty_sel_vpa" pos="0" rst="0">
          <comment>100% duty selection 1'b0: default, max duty=100% 1'b1: max duty ~95%</comment>
        </bits>
      </reg>
      <reg name="dcdc_wpa_reg2" protect="rw">
        <bits access="rw" name="div_clk_vpa_en" pos="15" rst="0">
          <comment>clock gating enable</comment>
        </bits>
        <bits access="rw" name="phase_sel_vpa" pos="14:9" rst="0">
          <comment>the phase difference, 26M per step</comment>
        </bits>
        <bits access="rw" name="div_base_vpa" pos="8:3" rst="15">
          <comment>the division factor from 26M for DCDCWPA, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 26'h3F: divide by 64</comment>
        </bits>
        <bits access="rw" name="zx_disable_vpa" pos="2" rst="0">
          <comment>force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off</comment>
        </bits>
        <bits access="rw" name="sawtoothcal_rst_vpa" pos="1" rst="0">
          <comment>sawtooth calibration 1'b0: default, auto calibration before power-on 1'b1: calibration manully</comment>
        </bits>
        <bits access="rw" name="pd_buck_vpa" pos="0" rst="1">
          <comment>DCDC power down 1'b0: DCDC on 1'b1: DCDC power down</comment>
        </bits>
      </reg>
      <reg name="dcdc_wpa_vol" protect="rw">
        <bits access="rw" name="vosel_vpa" pos="6:0" rst="120">
          <comment>output voltage selection, 25mV/step. 7'b1111100= 3.5V 7'b1110000= 3.2V 7'b1100000= 2.8V 7'b1010000= 2.4V 7'b1000000= 2.0V 7'b0110000= 1.6V 7'b0100000= 1.2V 7'b0010000= 0.8V 7'b0000000= 0.4V</comment>
        </bits>
      </reg>
      <reg name="dcdc_wpa_dcm_hw" protect="rw">
        <bits access="rw" name="force_pwm_vpa" pos="0" rst="0">
          <comment>force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode</comment>
        </bits>
      </reg>
      <reg name="dcdc_ch_ctrl" protect="rw">
        <bits access="rw" name="dcdc_auxtrim_sel" pos="2:0" rst="0">
          <comment>DCDC to AUXADC trim channel selection 3'b001: select VCORE 3'b010: select VGEN (VGEN*18/37) 3'b011: select VPA (VPA*18/68) RG_DCDC_AUXTRIM_SEL&lt;2&gt;, internal test mode select: 0: default, internal test mode disable 1: internal test mode enable. Monitor internal signals by reuse CLK3M_OUT path 3'b100: enpwm_vgen 3'b101: zx_vgen 3'b110: enpwm_vcore 3'b111: zx_vcore</comment>
        </bits>
      </reg>
      <reg name="reserved_reg4" protect="r">
      </reg>
      <reg name="reserved_reg5" protect="r">
      </reg>
      <reg name="reserved_reg6" protect="r">
      </reg>
      <reg name="reserved_reg7" protect="r">
      </reg>
      <reg name="reserved_reg8" protect="r">
      </reg>
      <reg name="ldo_ana_reg0" protect="rw">
        <bits access="rw" name="ldo_ana_shpt_pd" pos="7" rst="0">
          <comment>LDO short protection power down</comment>
        </bits>
        <bits access="rw" name="ldo_ana_cap_sel" pos="6" rst="0">
          <comment>ANA LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_ana_bp" pos="5" rst="0">
          <comment>ANA LDO bypass application: default 1'b0, no bypass default 1'b1,  bypass</comment>
        </bits>
        <bits access="rw" name="ldo_ana_stb" pos="4:3" rst="0">
          <comment>ANA LDO stability compensation: default 2'b00</comment>
        </bits>
        <bits access="rw" name="ldo_ana_shpt_adj" pos="2" rst="0">
          <comment>ANA LDO foldback current threshold adjust: default 1'b0</comment>
        </bits>
        <bits access="rw" name="ldo_ana_cl_adj" pos="1" rst="0">
          <comment>ANA LDO current limit threshold adjust: default 1'b0</comment>
        </bits>
      </reg>
      <reg name="ldo_ana_reg1" protect="rw">
        <bits access="rw" name="ldo_ana_v" pos="5:0" rst="32">
          <comment>ANA LDO program bits: 12.5mV/step, 1.4V~2.1875V;   default 1.8V, 6'b100000</comment>
        </bits>
      </reg>
      <reg name="reserved_reg9" protect="r">
      </reg>
      <reg name="reserved_reg10" protect="r">
      </reg>
      <reg name="ldo_rf15_reg0" protect="rw">
        <bits access="rw" name="ldo_rf15_shpt_pd" pos="7" rst="0">
          <comment>RF15 LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_rf15_cap_sel" pos="6" rst="0">
          <comment>RF15 LDO remote cap application:default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_rf15_bp" pos="5" rst="0">
          <comment>RF15 LDO bypass application: default 1'b0, no bypass default 1'b1,  bypass</comment>
        </bits>
        <bits access="rw" name="ldo_rf15_stb" pos="4:3" rst="0">
          <comment>RF15 LDO stability compensation: default 2'b00</comment>
        </bits>
        <bits access="rw" name="ldo_rf15_shpt_adj" pos="2" rst="0">
          <comment>RF15 LDO foldback current threshold adjust: default 1'b0</comment>
        </bits>
        <bits access="rw" name="ldo_rf15_cl_adj" pos="1" rst="0">
          <comment>RF15 LDO current limit threshold adjust: default 1'b0</comment>
        </bits>
        <bits access="rw" name="ldo_rf15_pd" pos="0" rst="0">
          <comment>LDO_RF15  power down                                             1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_rf15_reg1" protect="rw">
        <bits access="rw" name="ldo_rf15_v" pos="5:0" rst="8">
          <comment>RF15 LDO program bits: 12.5mV/step, 1.4V~2.1875V;   default 1.5V, 6'b1000</comment>
        </bits>
      </reg>
      <reg name="reserved_reg11" protect="rw">
      </reg>
      <reg name="reserved_reg12" protect="rw">
      </reg>
      <reg name="ldo_camd_reg0" protect="rw">
        <bits access="rw" name="ldo_camd_shpt_pd" pos="7" rst="0">
          <comment>CAMD LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_camd_cap_sel" pos="6" rst="0">
          <comment>CAMD LDO remote cap application:default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_camd_bp" pos="5" rst="0">
          <comment>CAMD LDO bypass application: default 1'b0, no bypass default 1'b1,  bypass</comment>
        </bits>
        <bits access="rw" name="ldo_camd_stb" pos="4:3" rst="0">
          <comment>CAMD LDO stability compensation: default 2'b00</comment>
        </bits>
        <bits access="rw" name="ldo_camd_shpt_adj" pos="2" rst="0">
          <comment>CAMD LDO foldback current threshold adjust: default 1'b0</comment>
        </bits>
        <bits access="rw" name="ldo_camd_cl_adj" pos="1" rst="0">
          <comment>CAMD LDO current limit threshold adjust: default 1'b0</comment>
        </bits>
        <bits access="rw" name="ldo_camd_pd" pos="0" rst="1">
          <comment>LDO_CAMD  power down                                             1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_camd_reg1" protect="rw">
        <bits access="rw" name="ldo_camd_v" pos="5:0" rst="32">
          <comment>CAMD LDO program bits:12.5mV/step, 1.4V~2.1875V;   default 1.8V, 6'b100000</comment>
        </bits>
      </reg>
      <reg name="ldo_con_reg0" protect="rw">
        <bits access="rw" name="ldo_con_shpt_pd" pos="6" rst="0">
          <comment>CON LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_con_bp" pos="5" rst="0">
          <comment>CON LDO bypass application: default 1'b0, no bypass default 1'b1,  bypass</comment>
        </bits>
        <bits access="rw" name="ldo_con_stb" pos="4:3" rst="0">
          <comment>CON LDO stability compensation: default 2'b00</comment>
        </bits>
        <bits access="rw" name="ldo_con_shpt_adj" pos="2" rst="0">
          <comment>CON LDO foldback current threshold adjust: default 1'b0</comment>
        </bits>
        <bits access="rw" name="ldo_con_cl_adj" pos="1" rst="0">
          <comment>CON LDO current limit threshold adjust: default 1'b0</comment>
        </bits>
        <bits access="rw" name="ldo_con_pd" pos="0" rst="1">
          <comment>LDO_CON  power down                                             1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_con_reg1" protect="rw">
        <bits access="rw" name="ldo_con_v" pos="5:0" rst="32">
          <comment>CON LDO program bits: 12.5mV/step, 1.1V~1.8875V;   default 1.5V, 6'b100000</comment>
        </bits>
      </reg>
      <reg name="ldo_mem_reg0" protect="rw">
        <bits access="rw" name="ldo_mem_shpt_pd" pos="7" rst="0">
          <comment>MEM LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_mem_cap_sel" pos="6" rst="0">
          <comment>MEM LDO remote cap application:default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_mem_bp" pos="5" rst="0">
          <comment>MEM LDO bypass application: default 1'b0, no bypass default 1'b1,  bypass</comment>
        </bits>
        <bits access="rw" name="ldo_mem_stb" pos="4:3" rst="0">
          <comment>MEM LDO stability compensation: default 2'b00</comment>
        </bits>
        <bits access="rw" name="ldo_mem_shpt_adj" pos="2" rst="0">
          <comment>MEM LDO foldback current threshold adjust: default 1'b0</comment>
        </bits>
        <bits access="rw" name="ldo_mem_cl_adj" pos="1" rst="0">
          <comment>MEM LDO current limit threshold adjust: default 1'b0</comment>
        </bits>
      </reg>
      <reg name="ldo_mem_reg1" protect="rw">
        <bits access="rw" name="ldo_mem_v" pos="5:0" rst="32">
          <comment>MEM LDO program bits: 12.5mV/step, 1.4V~2.1875V;   default 6'h100000, 1.8V</comment>
        </bits>
      </reg>
      <reg name="ldo_sim0_reg0" protect="rw">
        <bits access="rw" name="ldo_sim0_shpt_pd" pos="6" rst="0">
          <comment>SIM0 LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_sim0_cap_sel" pos="5" rst="0">
          <comment>SIM0 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_sim0_stb" pos="4:3" rst="2">
          <comment>SIM0 LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_sim0_shpt_adj" pos="2" rst="1">
          <comment>SIM0 LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_sim0_cl_adj" pos="1" rst="1">
          <comment>SIM0 LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
      </reg>
      <reg name="ldo_sim0_pd_reg" protect="rw">
        <bits access="rw" name="ldo_sim0_pd" pos="0" rst="1">
          <comment>LDO_SIM0  power down                                             1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_sim0_reg1" protect="rw">
        <bits access="rw" name="ldo_sim0_v" pos="6:0" rst="15">
          <comment>SIM0 LDO program bits:12.5mV/step, 1.6125V~3.2V; default 1.8V, 7'b0001111</comment>
        </bits>
      </reg>
      <reg name="ldo_sim1_reg0" protect="rw">
        <bits access="rw" name="ldo_sim1_shpt_pd" pos="6" rst="0">
          <comment>SIM1 LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_sim1_cap_sel" pos="5" rst="0">
          <comment>SIM1 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_sim1_stb" pos="4:3" rst="2">
          <comment>SIM1 LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_sim1_shpt_adj" pos="2" rst="1">
          <comment>SIM1 LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_sim1_cl_adj" pos="1" rst="1">
          <comment>SIM1 LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
      </reg>
      <reg name="ldo_sim1_pd_reg" protect="rw">
        <bits access="rw" name="ldo_sim1_pd" pos="0" rst="1">
          <comment>LDO_SIM1  power down                                             1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_sim1_reg1" protect="rw">
        <bits access="rw" name="ldo_sim1_v" pos="6:0" rst="15">
          <comment>SIM0 LDO program bits:12.5mV/step, 1.6125V~3.2V; default 1.8V, 7'b0001111</comment>
        </bits>
      </reg>
      <reg name="reserved_reg13" protect="r">
      </reg>
      <reg name="reserved_reg14" protect="r">
      </reg>
      <reg name="reserved_reg15" protect="rw">
      </reg>
      <reg name="ldo_cama_reg0" protect="rw">
        <bits access="rw" name="ldo_cama_shpt_pd" pos="6" rst="0">
          <comment>CAMA LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_cama_cap_sel" pos="5" rst="0">
          <comment>CAMA LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_cama_stb" pos="4:3" rst="2">
          <comment>CAMA LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_cama_shpt_adj" pos="2" rst="1">
          <comment>CAMA LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_cama_cl_adj" pos="1" rst="1">
          <comment>CAMA LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_cama_pd" pos="0" rst="1">
          <comment>LDO_CAMA  power down                                             1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_cama_reg1" protect="rw">
        <bits access="rw" name="ldo_cama_v" pos="6:0" rst="95">
          <comment>CAMA LDO program bits: 12.5mV/step, 1.6125V~3.2V ; default 2.8V, 7'b1011111</comment>
        </bits>
      </reg>
      <reg name="ldo_lcd_reg0" protect="rw">
        <bits access="rw" name="ldo_lcd_shpt_pd" pos="6" rst="0">
          <comment>LCD LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_lcd_cap_sel" pos="5" rst="0">
          <comment>LCD LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_lcd_stb" pos="4:3" rst="2">
          <comment>LCD LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_lcd_shpt_adj" pos="2" rst="1">
          <comment>LCD LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_lcd_cl_adj" pos="1" rst="1">
          <comment>LCD LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_lcd_pd" pos="0" rst="1">
          <comment>LDO_LCD  power down                                             1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_lcd_reg1" protect="rw">
        <bits access="rw" name="ldo_lcd_v" pos="6:0" rst="15">
          <comment>LCD LDO program bits: 12.5mV/step, 1.6125V~3.2V; default 1.8V, 7'b0001111</comment>
        </bits>
      </reg>
      <reg name="ldo_mmc_reg0" protect="rw">
        <bits access="rw" name="ldo_mmc_shpt_pd" pos="6" rst="0">
          <comment>MMC LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_mmc_cap_sel" pos="5" rst="0">
          <comment>MMC LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_mmc_stb" pos="4:3" rst="2">
          <comment>MMC LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_mmc_shpt_adj" pos="2" rst="1">
          <comment>MMC LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_mmc_cl_adj" pos="1" rst="1">
          <comment>MMC LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
      </reg>
      <reg name="ldo_mmc_pd_reg" protect="rw">
        <bits access="rw" name="ldo_mmc_pd" pos="0" rst="0">
          <comment>LDO_MMC  power down                                               1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_mmc_reg1" protect="rw">
        <bits access="rw" name="ldo_mmc_v" pos="6:0" rst="80">
          <comment>MMC LDO program bits: 12.5mV/step, 2V~3.5875V; default 3.0V, 7'b1010000</comment>
        </bits>
      </reg>
      <reg name="ldo_sd_reg0" protect="rw">
        <bits access="rw" name="ldo_vio18_shpt_pd" pos="6" rst="0">
          <comment>SD LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_vio18_cap_sel" pos="5" rst="0">
          <comment>SD LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_vio18_stb" pos="4:3" rst="2">
          <comment>SD LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_vio18_shpt_adj" pos="2" rst="1">
          <comment>SD LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_vio18_cl_adj" pos="1" rst="1">
          <comment>SD LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
      </reg>
      <reg name="ldo_sd_pd_reg" protect="rw">
        <bits access="rw" name="ldo_vio18_pd" pos="0" rst="0">
          <comment>LDO_SD  power down                                               1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_sd_reg1" protect="rw">
        <bits access="rw" name="ldo_vio18_v" pos="6:0" rst="32">
          <comment>SD LDO program bits: 12.5mV/step, 1.4V~2.1875V; default 1.8V, 7'b100000</comment>
        </bits>
      </reg>
      <reg name="ldo_ddr12_reg0" protect="rw">
        <bits access="rw" name="ldo_ddr12_shpt_pd" pos="6" rst="0">
          <comment>DDR12 LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_ddr12_cap_sel" pos="5" rst="0">
          <comment>DDR12 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_ddr12_stb" pos="4:3" rst="2">
          <comment>DDR12 LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_ddr12_shpt_adj" pos="2" rst="1">
          <comment>DDR12 LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_ddr12_cl_adj" pos="1" rst="1">
          <comment>DDR12 LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
      </reg>
      <reg name="ldo_ddr12_pd_reg" protect="rw">
        <bits access="rw" name="ldo_ddr12_pd" pos="0" rst="0">
          <comment>LDO_DDR12  power down                                               1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_ddr12_reg1" protect="rw">
        <bits access="rw" name="ldo_ddr12_v" pos="6:0" rst="36">
          <comment>DDR12 LDO program bits: 12.5mV/step, 0.8V~1.5875V ; default 1.25V, 7'b100100</comment>
        </bits>
      </reg>
      <reg name="ldo_vdd28_reg0" protect="rw">
        <bits access="rw" name="ldo_vdd28_shpt_pd" pos="6" rst="0">
          <comment>VDD28 LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_vdd28_cap_sel" pos="5" rst="0">
          <comment>VDD28 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_vdd28_stb" pos="4:3" rst="2">
          <comment>VDD28 LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_vdd28_shpt_adj" pos="2" rst="1">
          <comment>VDD28 LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_vdd28_cl_adj" pos="1" rst="1">
          <comment>VDD28 LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
      </reg>
      <reg name="ldo_vdd28_reg1" protect="rw">
        <bits access="rw" name="ldo_vdd28_v" pos="6:0" rst="95">
          <comment>VDD28 LDO program bits: 12.5mV/step, 1.6125V~3.2V ; default 2.8V, 7'b1011111</comment>
        </bits>
      </reg>
      <reg name="ldo_spimem_reg0" protect="rw">
        <bits access="rw" name="ldo_spimem_shpt_pd" pos="6" rst="0">
          <comment>SPIMEM LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_spimem_cap_sel" pos="5" rst="0">
          <comment>SPIMEM LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_spimem_stb" pos="4:3" rst="2">
          <comment>SPIMEM LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_spimem_shpt_adj" pos="2" rst="1">
          <comment>SPIMEM LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_spimem_cl_adj" pos="1" rst="1">
          <comment>SPIMEM LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_spimem_pd" pos="0" rst="0">
          <comment>LDO_SPIMEM  power down                                               1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_spimem_reg1" protect="rw">
        <bits access="rw" name="ldo_spimem_v" pos="6:0" rst="4">
          <comment>SPIMEM LDO program bits:12.5mV/step, 1.75V~3.3375V; default is select by  V_SPIMEM pad, when V_SPIMEM ==0, spimem voltage is 1.8V, register default is 7'b100
when V_SPIMEM ==1, spimem voltage is 3.3V, register default is 7b1111100</comment>
        </bits>
      </reg>
      <reg name="ldo_dcxo_reg0" protect="rw">
        <bits access="rw" name="ldo_dcxo_trim" pos="11:7" rst="16">
          <comment>LDO DCXO trim bits: 5mV/step, 0.72V~0.875V;   default 1.2V, 5'b10000</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_shpt_pd" pos="6" rst="0">
          <comment>DCXO LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_cap_sel" pos="5" rst="0">
          <comment>DCXO LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_stb" pos="4:3" rst="2">
          <comment>DCXO LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_shpt_adj" pos="2" rst="1">
          <comment>DCXO LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_cl_adj" pos="1" rst="1">
          <comment>DCXO LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
      </reg>
      <reg name="ldo_dcxo_reg1" protect="rw">
        <bits access="rw" name="ldo_dcxo_v" pos="6:0" rst="24">
          <comment>DCXO LDO program bits: 12.5mV/step, 1.5V~3.0875V ; default 1.8V, 7'b0011000</comment>
        </bits>
      </reg>
      <reg name="ldo_usb_reg0" protect="rw">
        <bits access="rw" name="ldo_usb33_shpt_pd" pos="6" rst="0">
          <comment>USB33 LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_usb33_cap_sel" pos="5" rst="0">
          <comment>USB33 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_usb33_stb" pos="4:3" rst="2">
          <comment>USB33 LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_usb33_shpt_adj" pos="2" rst="1">
          <comment>USB33 LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_usb33_cl_adj" pos="1" rst="1">
          <comment>USB33 LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
      </reg>
      <reg name="ldo_usb_pd_reg" protect="rw">
        <bits access="rw" name="ldo_usb33_pd" pos="0" rst="0">
          <comment>LDO_USB33  power down                                             1: power down                                                                0: power on</comment>
        </bits>
      </reg>
      <reg name="ldo_usb_reg1" protect="rw">
        <bits access="rw" name="ldo_usb33_v" pos="6:0" rst="96">
          <comment>USB33 LDO program bits: 12.5mV/step, 2.1V~3.6875V; default 3.3V, 7'b1100000</comment>
        </bits>
      </reg>
      <reg name="reserved_reg17" protect="r">
      </reg>
      <reg name="reserved_reg18" protect="r">
      </reg>
      <reg name="reserved_reg19" protect="r">
      </reg>
      <reg name="reserved_reg20" protect="r">
      </reg>
      <reg name="ldo_trim_reg" protect="rw">
        <bits access="rw" name="ldo_trim_b" pos="9:5" rst="16">
          <comment>LDO trim bits: 5mV/step, 0.72V~0.875V;   default 0.8V, 5'b10000</comment>
        </bits>
        <bits access="rw" name="ldo_trim_a" pos="4:0" rst="16">
          <comment>LDO trim bits: 5mV/step, 0.72V~0.875V;   default 0.8V, 5'b10000</comment>
        </bits>
      </reg>
      <reg name="ldo_rtc_ctrl" protect="rw">
        <bits access="rw" name="ldo_rtc_cal" pos="8:4" rst="16">
          <comment>LDO VDDRTC output calibretion bit cover +/-10% step 0.625% acc +/- 0.3125%</comment>
        </bits>
        <bits access="rw" name="ldo_rtc_v" pos="3:2" rst="2">
          <comment>LDO RTC output program bits, 00:1.8, 01:1.8, 10:1.85(default),11:1.9</comment>
        </bits>
        <bits access="rw" name="vbatbk_v" pos="1:0" rst="2">
          <comment>Backup battery output program bits;00:2.6, 01:2.8, 10:3.0(default),11:3.2</comment>
        </bits>
      </reg>
      <reg name="ldo_ch_ctrl" protect="rw">
        <bits access="rw" name="ldo_cal2" pos="10:8" rst="0">
          <comment>VBAT2 LDO TRIM CONTROL BITS:
000:  cal disable (default)
001: LDO VDDSIM0 cal enable;
010: LDO VDDSIM1 cal enable;
011: LDO VDDDCXOcal enable;
100: LDO VDDUSB cal enable;
101: LDO VDDCAMA cal enable;
110: LDO VDDVIB cal enable;</comment>
        </bits>
        <bits access="rw" name="ldo_cal1" pos="7:5" rst="0">
          <comment>VBAT1 LDO TRIM CONTROL BITS:
000:  cal disable (default)
001: LDO VDDMMC cal enable;
010: LDO VDD28 cal enable;
011: LDO VDDSPIMEM cal enable;
100: LDO VDDLCD cal enable;
101: LDO VDDPLLED cal enable;</comment>
        </bits>
        <bits access="rw" name="ldo_cal" pos="2:0" rst="0">
          <comment>DCDC supplied LDO TRIM CONTROL BITS:
000:  cal disable (default)
001: LDO VDDCAMD cal enable;
010: LDO VDDCON cal enable;
011: LDO VDDANA cal enable;
100: LDO VDDVIO18 cal enable;
101: LDO VDDDDR12 cal enable;
110: LDO VDDMEM cal enable;
111: LDO VDDRF15 cal enable;</comment>
        </bits>
      </reg>
      <reg name="reserved_reg23" protect="r">
      </reg>
      <reg name="reserved_reg24" protect="r">
      </reg>
      <reg name="reserved_reg25" protect="r">
      </reg>
      <reg name="reserved_reg26" protect="r">
      </reg>
      <reg name="reserved_reg27" protect="r">
      </reg>
      <reg name="slp_ctrl" protect="rw">
        <bits access="rw" name="ldo_xtl_en" pos="2" rst="0">
          <comment>LDO and DCDC can be controlled by external device if this bit is set</comment>
        </bits>
        <bits access="rw" name="slp_io_en" pos="1" rst="0">
          <comment>IO PAD sleep enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldo_pd_en" pos="0" rst="0">
          <comment>ALL LDO and DCDC power down enable in deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="slp_dcdc_pd_ctrl" protect="rw">
        <bits access="rw" name="slp_dcdccore_pd_rstn_th" pos="15:12" rst="0">
          <comment>DCDC CORE power down  reset valid threshold @32K clock</comment>
        </bits>
        <bits access="rw" name="slp_dcdccore_pu_rstn_th" pos="11:6" rst="0">
          <comment>DCDC CORE power down  reset release threshold @32K clock</comment>
        </bits>
        <bits access="rw" name="slp_dcdccore_pd_en" pos="4" rst="0">
          <comment>DCDC CORE power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_dcdccore_drop_en" pos="3" rst="0">
          <comment>DCDC CORE power drop enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_dcdcwpa_pd_en" pos="2" rst="0">
          <comment>DCDC WPA power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_vddio1v8_pd_en" pos="1" rst="0">
          <comment>VIO1V8 power down enable in deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="slp_ldo_pd_ctrl0" protect="rw">
        <bits access="rw" name="slp_ldorf15_pd_en" pos="14" rst="0">
          <comment>LDO RFA power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldommc_pd_en" pos="12" rst="0">
          <comment>LDO MMC power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldodcxo_pd_en" pos="11" rst="0">
          <comment>LDO DCXO power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldospimem_pd_en" pos="10" rst="0">
          <comment>LDO SPIMEM power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldovdd28_pd_en" pos="9" rst="0">
          <comment>LDO VDD28 power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldovio18_pd_en" pos="8" rst="0">
          <comment>LDO VIO18 power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldoddr12_pd_en" pos="7" rst="0">
          <comment>LDO DDR12 power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldousb33_pd_en" pos="6" rst="0">
          <comment>LDO USB33 power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldolcd_pd_en" pos="5" rst="0">
          <comment>LDO LCD power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldocamio_pd_en" pos="4" rst="0">
          <comment>LDO CAMIO power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldocamd_pd_en" pos="3" rst="0">
          <comment>LDO CAMD power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldocama_pd_en" pos="2" rst="0">
          <comment>LDO CAMA power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldosim1_pd_en" pos="0" rst="0">
          <comment>LDO SIM1 power down enable in deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="slp_ldo_pd_ctrl1" protect="rw">
        <bits access="rw" name="slp_ldocp_pd_en" pos="4" rst="0">
          <comment>LDO CP power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldocon_pd_en" pos="3" rst="0">
          <comment>LDO CON power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldosim0_pd_en" pos="2" rst="0">
          <comment>LDO SIM0 power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldoana_pd_en" pos="1" rst="0">
          <comment>LDO ANA power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldomem_pd_en" pos="0" rst="0">
          <comment>LDO MEM power down enable in deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="slp_dcdc_lp_ctrl" protect="rw">
        <bits access="rw" name="slp_dcdccore_lp_en" pos="4" rst="0">
          <comment>DCDC CORE low power mode enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_dcdcgen_lp_en" pos="1" rst="0">
          <comment>DCDC GEN low power mode enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_dcdcwpa_lp_en" pos="0" rst="0">
          <comment>DCDC WPA low power mode enable in deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="slp_ldo_lp_ctrl0" protect="rw">
        <bits access="rw" name="slp_ldorf15_lp_en" pos="14" rst="0">
          <comment>LDO RFA low power mode enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldommc_lp_en" pos="12" rst="0">
          <comment>LDO MMC low power mode enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldodcxo_lp_en" pos="11" rst="0">
          <comment>LDO DCXO low power mode enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldospimem_lp_en" pos="10" rst="0">
          <comment>LDO SPIMEM low power mode enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldovdd28_lp_en" pos="9" rst="0">
          <comment>LDO VDD28 low power mode enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldovio18_lp_en" pos="8" rst="0">
          <comment>LDO VIO18 low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
        <bits access="rw" name="slp_ldoddr12_lp_en" pos="7" rst="0">
          <comment>LDO DDR12 low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
        <bits access="rw" name="slp_ldousb33_lp_en" pos="6" rst="0">
          <comment>LDO USB low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
        <bits access="rw" name="slp_ldolcd_lp_en" pos="5" rst="0">
          <comment>LDO LCD low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
        <bits access="rw" name="slp_ldocamio_lp_en" pos="4" rst="0">
          <comment>LDO CAMIO low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
        <bits access="rw" name="slp_ldocamd_lp_en" pos="3" rst="0">
          <comment>LDO CAMD low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
        <bits access="rw" name="slp_ldocama_lp_en" pos="2" rst="0">
          <comment>LDO CAMA low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
        <bits access="rw" name="slp_ldosim1_lp_en" pos="0" rst="0">
          <comment>LDO SIM1 low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
      </reg>
      <reg name="slp_ldo_lp_ctrl1" protect="rw">
        <bits access="rw" name="slp_ldocon_lp_en" pos="3" rst="0">
          <comment>LDO CON low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
        <bits access="rw" name="slp_ldosim0_lp_en" pos="2" rst="0">
          <comment>LDO SIM0 low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
        <bits access="rw" name="slp_ldoana_lp_en" pos="1" rst="0">
          <comment>LDO ANA low power mode enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="slp_ldomem_lp_en" pos="0" rst="0">
          <comment>LDO MEM low power mode enable in deep sleep mode 0: Disable 1: Enable</comment>
        </bits>
      </reg>
      <reg name="dcdc_core_slp_ctrl0" protect="rw">
        <bits access="rw" name="dcdc_core_slp_step_delay" pos="13:12" rst="0">
          <comment>delay between two steps 00:1*32k clock 01:2*32k clock 10:3*32k clock 11:4*32k clock</comment>
        </bits>
        <bits access="rw" name="dcdc_core_slp_step_num" pos="11:8" rst="0">
          <comment>step number</comment>
        </bits>
        <bits access="rw" name="dcdc_core_slp_step_vol" pos="7:3" rst="0">
          <comment>voltage per step 00000:0mv 00001:1*3.125mv 00010:2*3.125mv.. 11111:31*3.125mv</comment>
        </bits>
        <bits access="rw" name="dcdc_core_slp_step_en" pos="0" rst="0">
          <comment>DCDCCORE step tune enable in deep sleep 0: disable 1: enable</comment>
        </bits>
      </reg>
      <reg name="dcdc_core_slp_ctrl1" protect="rw">
        <bits access="rw" name="dcdc_core_vosel_ds_sw" pos="8:0" rst="4">
          <comment>DCDC CORE control bits in deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="dcdc_xtl_en0" protect="rw">
        <bits access="rw" name="dcdc_core_ext_xtl0_en" pos="15" rst="0">
          <comment>DCDC CORE can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_core_ext_xtl1_en" pos="14" rst="0">
          <comment>DCDC CORE can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_core_ext_xtl2_en" pos="13" rst="0">
          <comment>DCDC CORE can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_core_ext_xtl3_en" pos="12" rst="0">
          <comment>DCDC CORE can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_gen_ext_xtl0_en" pos="7" rst="0">
          <comment>DCDC GEN can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_gen_ext_xtl1_en" pos="6" rst="0">
          <comment>DCDC GEN can be controlled by EXT_XTL1_EN1(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_gen_ext_xtl2_en" pos="5" rst="0">
          <comment>DCDC GEN can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_gen_ext_xtl3_en" pos="4" rst="0">
          <comment>DCDC GEN can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_wpa_ext_xtl0_en" pos="3" rst="0">
          <comment>DCDC WPA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_wpa_ext_xtl1_en" pos="2" rst="0">
          <comment>DCDC WPA can be controlled by EXT_XTL1_EN1(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_wpa_ext_xtl2_en" pos="1" rst="0">
          <comment>DCDC WPA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="dcdc_wpa_ext_xtl3_en" pos="0" rst="0">
          <comment>DCDC WPA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="reseved_dcdc_xtl_en4" protect="r">
      </reg>
      <reg name="ldo_xtl_en0" protect="rw">
        <bits access="rw" name="ldo_dcxo_ext_xtl0_en" pos="15" rst="0">
          <comment>LDO DCXO can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_ext_xtl1_en" pos="14" rst="0">
          <comment>LDO DCXO can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_ext_xtl2_en" pos="13" rst="0">
          <comment>LDO DCXO can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_ext_xtl3_en" pos="12" rst="0">
          <comment>LDO DCXO can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vdd28_ext_xtl0_en" pos="3" rst="0">
          <comment>LDO VDD28 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vdd28_ext_xtl1_en" pos="2" rst="0">
          <comment>LDO VDD28 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vdd28_ext_xtl2_en" pos="1" rst="0">
          <comment>LDO VDD28 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vdd28_ext_xtl3_en" pos="0" rst="0">
          <comment>LDO VDD28 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="ldo_xtl_en1" protect="rw">
        <bits access="rw" name="ldo_rf15_ext_xtl0_en" pos="15" rst="0">
          <comment>LDO RFA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_rf15_ext_xtl1_en" pos="14" rst="0">
          <comment>LDO RFA can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_rf15_ext_xtl2_en" pos="13" rst="0">
          <comment>LDO RFA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_rf15_ext_xtl3_en" pos="12" rst="0">
          <comment>LDO RFA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="ldo_xtl_en2" protect="rw">
        <bits access="rw" name="ldo_sim0_ext_xtl0_en" pos="15" rst="0">
          <comment>LDO SIM0 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_sim0_ext_xtl1_en" pos="14" rst="0">
          <comment>LDO SIM0 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_sim0_ext_xtl2_en" pos="13" rst="0">
          <comment>LDO SIM0 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_sim0_ext_xtl3_en" pos="12" rst="0">
          <comment>LDO SIM0 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_sim1_ext_xtl0_en" pos="3" rst="0">
          <comment>LDO SIM1 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_sim1_ext_xtl1_en" pos="2" rst="0">
          <comment>LDO SIM1 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_sim1_ext_xtl2_en" pos="1" rst="0">
          <comment>LDO SIM1 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_sim1_ext_xtl3_en" pos="0" rst="0">
          <comment>LDO SIM1 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="ldo_xtl_en3" protect="rw">
        <bits access="rw" name="ldo_mem_ext_xtl0_en" pos="3" rst="0">
          <comment>LDO MEM can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_mem_ext_xtl1_en" pos="2" rst="0">
          <comment>LDO MEM can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_mem_ext_xtl2_en" pos="1" rst="0">
          <comment>LDO MEM can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_mem_ext_xtl3_en" pos="0" rst="0">
          <comment>LDO MEM can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="ldo_xtl_en4" protect="rw">
        <bits access="rw" name="ldo_lcd_ext_xtl0_en" pos="15" rst="0">
          <comment>LDO LCD can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_lcd_ext_xtl1_en" pos="14" rst="0">
          <comment>LDO LCD can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_lcd_ext_xtl2_en" pos="13" rst="0">
          <comment>LDO LCD can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_lcd_ext_xtl3_en" pos="12" rst="0">
          <comment>LDO LCD can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_camio_ext_xtl0_en" pos="3" rst="0">
          <comment>LDO CAMIO can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_camio_ext_xtl1_en" pos="2" rst="0">
          <comment>LDO CAMIO can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_camio_ext_xtl2_en" pos="1" rst="0">
          <comment>LDO CAMIO can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_camio_ext_xtl3_en" pos="0" rst="0">
          <comment>LDO CAMIO can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="ldo_xtl_en5" protect="rw">
        <bits access="rw" name="ldo_cama_ext_xtl0_en" pos="15" rst="0">
          <comment>LDO CAMA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_cama_ext_xtl1_en" pos="14" rst="0">
          <comment>LDO CAMA can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_cama_ext_xtl2_en" pos="13" rst="0">
          <comment>LDO CAMA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_cama_ext_xtl3_en" pos="12" rst="0">
          <comment>LDO CAMA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_camd_ext_xtl0_en" pos="3" rst="0">
          <comment>LDO CAMD can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_camd_ext_xtl1_en" pos="2" rst="0">
          <comment>LDO CAMD can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_camd_ext_xtl2_en" pos="1" rst="0">
          <comment>LDO CAMD can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_camd_ext_xtl3_en" pos="0" rst="0">
          <comment>LDO CAMD can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="ldo_xtl_en6" protect="rw">
        <bits access="rw" name="ldo_ddr12_ext_xtl0_en" pos="15" rst="0">
          <comment>LDO DDR12 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_ddr12_ext_xtl1_en" pos="14" rst="0">
          <comment>LDO DDR12 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_ddr12_ext_xtl2_en" pos="13" rst="0">
          <comment>LDO DDR12 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_ddr12_ext_xtl3_en" pos="12" rst="0">
          <comment>LDO DDR12 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vio18_ext_xtl0_en" pos="3" rst="0">
          <comment>LDO VIO18 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vio18_ext_xtl1_en" pos="2" rst="0">
          <comment>LDO VIO18 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vio18_ext_xtl2_en" pos="1" rst="0">
          <comment>LDO VIO18 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vio18_ext_xtl3_en" pos="0" rst="0">
          <comment>LDO VIO18 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="ldo_xtl_en7" protect="rw">
        <bits access="rw" name="ldo_mmc_ext_xtl0_en" pos="15" rst="0">
          <comment>LDO MMC can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_mmc_ext_xtl1_en" pos="14" rst="0">
          <comment>LDO MMC can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_mmc_ext_xtl2_en" pos="13" rst="0">
          <comment>LDO MMC can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_mmc_ext_xtl3_en" pos="12" rst="0">
          <comment>LDO MMC can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_usb33_ext_xtl0_en" pos="3" rst="0">
          <comment>LDO USB33 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_usb33_ext_xtl1_en" pos="2" rst="0">
          <comment>LDO USB33 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_usb33_ext_xtl2_en" pos="1" rst="0">
          <comment>LDO USB33 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_usb33_ext_xtl3_en" pos="0" rst="0">
          <comment>LDO USB33 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="ldo_xtl_en8" protect="rw">
        <bits access="rw" name="ldo_kpled_ext_xtl0_en" pos="15" rst="0">
          <comment>LDO KPLED can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_kpled_ext_xtl1_en" pos="14" rst="0">
          <comment>LDO KPLED can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_kpled_ext_xtl2_en" pos="13" rst="0">
          <comment>LDO KPLED can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_kpled_ext_xtl3_en" pos="12" rst="0">
          <comment>LDO KPLED can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_ext_xtl0_en" pos="3" rst="0">
          <comment>LDO VIBR can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_ext_xtl1_en" pos="2" rst="0">
          <comment>LDO VIBR can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_ext_xtl2_en" pos="1" rst="0">
          <comment>LDO VIBR can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_ext_xtl3_en" pos="0" rst="0">
          <comment>LDO VIBR can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="ldo_xtl_en9" protect="rw">
        <bits access="rw" name="ldo_con_ext_xtl0_en" pos="15" rst="0">
          <comment>LDO CON can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_con_ext_xtl1_en" pos="14" rst="0">
          <comment>LDO CON can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_con_ext_xtl2_en" pos="13" rst="0">
          <comment>LDO CON can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_con_ext_xtl3_en" pos="12" rst="0">
          <comment>LDO CON can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_ana_ext_xtl0_en" pos="3" rst="0">
          <comment>LDO ANA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_ana_ext_xtl1_en" pos="2" rst="0">
          <comment>LDO ANA can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_ana_ext_xtl2_en" pos="1" rst="0">
          <comment>LDO ANA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_ana_ext_xtl3_en" pos="0" rst="0">
          <comment>LDO ANA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="ldo_xtl_en10" protect="rw">
        <bits access="rw" name="ldo_cp_ext_xtl0_en" pos="15" rst="0">
          <comment>LDO CP can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_cp_ext_xtl1_en" pos="14" rst="0">
          <comment>LDO CON can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_cp_ext_xtl2_en" pos="13" rst="0">
          <comment>LDO CP can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_cp_ext_xtl3_en" pos="12" rst="0">
          <comment>LDO CP can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_spimem_ext_xtl0_en" pos="3" rst="0">
          <comment>LDO SPIMEM can be controlled by EXT_XTL0_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_spimem_ext_xtl1_en" pos="2" rst="0">
          <comment>LDO SPIMEM can be controlled by EXT_XTL1_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_spimem_ext_xtl2_en" pos="1" rst="0">
          <comment>LDO SPIMEM can be controlled by EXT_XTL2_EN(from PAD) if this bit is set</comment>
        </bits>
        <bits access="rw" name="ldo_spimem_ext_xtl3_en" pos="0" rst="0">
          <comment>LDO SPIMEM can be controlled by EXT_XTL3_EN(from PAD) if this bit is set</comment>
        </bits>
      </reg>
      <reg name="reserved_reg30" protect="r">
      </reg>
      <reg name="reserved_reg31" protect="r">
      </reg>
      <reg name="reserved_reg32" protect="r">
      </reg>
      <reg name="reserved_reg_core" protect="rw">
      </reg>
      <reg name="reserved_reg_rtc" protect="rw">
      </reg>
      <reg name="bg_ctrl" protect="rw">
        <bits access="rw" name="bg_chop_en" pos="0" rst="0">
          <comment>Band-gap chopping enable: &quot;0&quot;:chopping disable (default) &quot;1&quot;: chopping enable</comment>
        </bits>
      </reg>
      <reg name="dcdc_vlg_sel" protect="rw">
        <bits access="rw" name="dcdc_wpa_votrim_sw_sel" pos="5" rst="0">
          <comment>DCDC reference Bits selection 0: From efuse 1: From Software Register change is not recommended</comment>
        </bits>
        <bits access="rw" name="dcdc_wpa_sw_sel" pos="4" rst="0">
          <comment>DCDC Voltage calibration disable 0: enable calibration 1: disable calibration</comment>
        </bits>
        <bits access="rw" name="dcdc_gen_sw_sel" pos="3" rst="0">
          <comment>DCDC Voltage calibration disable 0: enable calibration 1: disable calibration</comment>
        </bits>
        <bits access="rw" name="dcdc_core_votrim_sw_sel" pos="2" rst="0">
          <comment>DCDC reference Bits selection 0: From efuse 1: From Software Register change is not recommended</comment>
        </bits>
        <bits access="rw" name="dcdc_core_slp_sw_sel" pos="1" rst="0">
          <comment>DCDC  sleep voltage turnning 0: From efuse,cannot voltage turnning 1: From Software Register,can be turnned if software want to control this voltage, must set this bit to 1</comment>
        </bits>
        <bits access="rw" name="dcdc_core_nor_sw_sel" pos="0" rst="0">
          <comment>DCDC normal  voltage turnning 0: From efuse,cannot voltage turnning 1: From Software Register,can be turnned if software want to control this voltage, must set this bit to 1</comment>
        </bits>
      </reg>
      <reg name="ldo_vlg_sel0" protect="rw">
        <bits access="rw" name="ldo_kpled_sw_sel" pos="5" rst="0">
          <comment>LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_sw_sel" pos="4" rst="0">
          <comment>LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended</comment>
        </bits>
        <bits access="rw" name="ldo_rtc_cal_sw_sel" pos="3" rst="0">
          <comment>LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_sw_sel" pos="2" rst="0">
          <comment>LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended</comment>
        </bits>
        <bits access="rw" name="ldo_trim_a_sw_sel" pos="1" rst="0">
          <comment>LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended</comment>
        </bits>
        <bits access="rw" name="ldo_trim_b_sw_sel" pos="0" rst="0">
          <comment>LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended</comment>
        </bits>
      </reg>
      <reg name="clk32kless_ctrl0" protect="rw">
        <bits access="r" name="rc_mode_wr_ack_flag" pos="14" rst="0">
          <comment>RC_MODE write ack flag</comment>
        </bits>
        <bits access="rc" name="rc_mode_wr_ack_flag_clr" pos="10" rst="0">
          <comment>bit type is changed from wc to rc.
          RC_MODE write ack flag clear, high effective</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_lp_en_rtcset" pos="7" rst="0">
          <comment>Low power LDO_DCXO power down set in RTC</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_lp_en_rtcclr" pos="6" rst="0">
          <comment>Low power LDO_DCXO power down clear in RTC</comment>
        </bits>
        <bits access="r" name="rtc_mode" pos="4" rst="0">
          <comment>0: there isnt 32k crystal in PMIC</comment>
        </bits>
        <bits access="rw" name="rc_32k_sel" pos="1" rst="0">
          <comment>32K clock select in 32K crystal removal option 0: From XO  1: From RC</comment>
        </bits>
        <bits access="rw" name="rc_32k_en" pos="0" rst="0">
          <comment>RC 32K oscillator enable</comment>
        </bits>
      </reg>
      <reg name="clk32kless_ctrl1" protect="rw">
        <bits access="rw" name="rc_mode" pos="15:0" rst="0">
          <comment>RC 32K mode in battery drop case:</comment>
        </bits>
      </reg>
      <reg name="xtl_wait_ctrl0" protect="rw">
        <bits access="rw" name="ext_xtl3_for_26m_en" pos="13" rst="0">
          <comment>26M wake up enable by ext_xtl3_en</comment>
        </bits>
        <bits access="rw" name="ext_xtl2_for_26m_en" pos="12" rst="0">
          <comment>26M wake up enable by ext_xtl2_en</comment>
        </bits>
        <bits access="rw" name="ext_xtl1_for_26m_en" pos="11" rst="0">
          <comment>26M wake up enable by ext_xtl1_en</comment>
        </bits>
        <bits access="rw" name="ext_xtl0_for_26m_en" pos="10" rst="0">
          <comment>26M wake up enable by ext_xtl0_en</comment>
        </bits>
        <bits access="rw" name="slp_xtlbuf_pd_en" pos="9" rst="1">
          <comment>26MHz crystal oscillator power down enable in deep sleep mode</comment>
        </bits>
        <bits access="rw" name="xtl_en" pos="8" rst="0">
          <comment>26MHz crystal oscillator output enable</comment>
        </bits>
        <bits access="rw" name="xtl_wait" pos="7:0" rst="50">
          <comment>26MHz crystal oscillator  wait cycles</comment>
        </bits>
      </reg>
      <reg name="rgb_ctrl" protect="rw">
        <bits access="rw" name="slp_rgb_pd_en" pos="2" rst="1">
          <comment>RGB driver power down enable in chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="rgb_pd_hw_en" pos="1" rst="0">
          <comment>RGB driver hardware power down enable</comment>
        </bits>
        <bits access="rw" name="rgb_pd_sw" pos="0" rst="1">
          <comment>RGB driver soft power down</comment>
        </bits>
      </reg>
      <reg name="ib_ctrl" protect="rw">
        <bits access="rw" name="batdet_cur_en" pos="13" rst="0">
          <comment>current mode enable                                                                         &quot;0&quot; disable (default)                                                                      &quot;1&quot; enable (default)</comment>
        </bits>
        <bits access="rw" name="batdet_cur_i" pos="11:9" rst="0">
          <comment>set current level in current mode 000:1.25uA;001:2.5uA;010:5uA;011:10uA;100:20uA;101:40uA;110:80uA;111:160uA; 8step</comment>
        </bits>
        <bits access="rw" name="ib_trim" pos="8:2" rst="64">
          <comment>Internal resistor for sink current calibration bit.</comment>
        </bits>
        <bits access="rw" name="ib_trim_em_sel" pos="1" rst="1">
          <comment>Internal resistor for sink current calibration bit selection 0: From Software Register 1: From Ememory</comment>
        </bits>
        <bits access="rw" name="ib_rex_en" pos="0" rst="0">
          <comment>External resisitor for sink current adjustment for test</comment>
        </bits>
      </reg>
      <reg name="flash_ctrl" protect="rw">
        <bits access="rw" name="flash_pon" pos="15" rst="0">
          <comment>Flash power on  1: power on   0: power down</comment>
        </bits>
        <bits access="rw" name="flash_v_hw_en" pos="6" rst="0">
          <comment>FLASH_V hardware control enable</comment>
        </bits>
        <bits access="rw" name="flash_v_hw_step" pos="5:4" rst="0">
          <comment>FLASH_V hardware control step                                00: 1 cycle of clock 32k                                                 01: 2 cycle of clock 32k                                                 10: 3 cycle of clock 32k                                                 11: 4 cycle of clock 32k</comment>
        </bits>
        <bits access="rw" name="flash_v_sw" pos="3:0" rst="0">
          <comment>Current control bit. 16 steps. Min current: 15mA (&quot;0000&quot;) One step is 15mA (default 4'b0)</comment>
        </bits>
      </reg>
      <reg name="kpled_ctrl0" protect="rw">
        <bits access="rw" name="kpled_v" pos="15:12" rst="0">
          <comment>Current control bit. 16 steps (default 4'b0) (0000:0.9mA 0001:1.8mA 0010:2.7mA 0011:3.6mA 0100:4.5mA 0101:5.4mA 0110:6.3mA 0111:7.2mA 1000:16.2mA 1001:22.5mA 1010:29.7mA 1011:37.8mA 1100:46.8mA 1101:56.7mA 1110:67.5mA 1111:79.2mA)</comment>
        </bits>
        <bits access="rw" name="kpled_pd" pos="11" rst="1">
          <comment>Key PAD LED driver power down &quot;1&quot; power down (default) &quot;0&quot; enable</comment>
        </bits>
        <bits access="rw" name="kpled_pulldown_en" pos="10" rst="0">
          <comment>Keypad LED pull down enable signale, high effective</comment>
        </bits>
        <bits access="rw" name="slp_ldokpled_pd_en" pos="9" rst="1">
          <comment>KPLED LDO sleep power down enable</comment>
        </bits>
        <bits access="rw" name="ldo_kpled_cap_sel" pos="4" rst="0">
          <comment>KPLED LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_kpled_stb" pos="3:2" rst="2">
          <comment>KPLED LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_kpled_shpt_adj" pos="1" rst="1">
          <comment>KPLED LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_kpled_cl_adj" pos="0" rst="1">
          <comment>VIBR LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
      </reg>
      <reg name="kpled_ctrl1" protect="rw">
        <bits access="rw" name="ldo_kpled_pd" pos="15" rst="1">
          <comment>KPLED LDO power down signal</comment>
        </bits>
        <bits access="rw" name="ldo_kpled_v" pos="9:7" rst="5">
          <comment>KPLED LDO program bits: 100mV/step, 2.8V~3.5V; default 3.3V, 3'b101</comment>
        </bits>
        <bits access="rw" name="ldo_kpled_reftrim" pos="6:2" rst="16">
          <comment>KPLED LDO TRIM program bits: 8mV/step 1.2V default</comment>
        </bits>
        <bits access="rw" name="ldo_kpled_shpt_pd" pos="0" rst="0">
          <comment>LDO short protection power down</comment>
        </bits>
      </reg>
      <reg name="vibr_ctrl0" protect="rw">
        <bits access="rw" name="ldo_vibr_cap_sel" pos="15" rst="0">
          <comment>VIBR LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_stb" pos="14:13" rst="2">
          <comment>KPLED LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_shpt_adj" pos="12" rst="1">
          <comment>VIBR LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_cl_adj" pos="11" rst="1">
          <comment>VIBR LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_shpt_pd" pos="10" rst="1">
          <comment>LDO short protection power down</comment>
        </bits>
        <bits access="rw" name="slp_ldovibr_pd_en" pos="9" rst="1">
          <comment>Vibrator LDO sleep power down enable</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_pd" pos="8" rst="1">
          <comment>VIBR LDO power down signal</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_v" pos="2:0" rst="2">
          <comment>VIBR LDO program bits: 100mV/step, 2.8V~3.5V; default 3.0V, 3'b010</comment>
        </bits>
      </reg>
      <reg name="vibr_ctrl1" protect="rw">
        <bits access="rw" name="ldo_vibr_reftrim" pos="5:1" rst="16">
          <comment>VIBR LDO TRIM program bits: 8mV/step 1.2V default</comment>
        </bits>
        <bits access="rw" name="ldo_vibr_eadbias_en" pos="0" rst="0">
          <comment>LDO EA load compensation EN  ,effective(1'b1)</comment>
        </bits>
      </reg>
      <reg name="audio_ctrl0" protect="rw">
        <bits access="rw" name="clk_aud_if_tx_inv_en" pos="3" rst="1">
          <comment>Whether Adie use inverse of clk_audif to sample Ddie tx data 0: No 1: Yes</comment>
        </bits>
        <bits access="rw" name="clk_aud_if_rx_inv_en" pos="2" rst="0">
          <comment>Whether Adie use inverse of clk_aud6m5 to send rx data to Ddie 0: No 1: Yes</comment>
        </bits>
        <bits access="rw" name="clk_aud_if_6p5m_tx_inv_en" pos="1" rst="0">
          <comment>Whether Adie audio controller use inverse of clk_aud6m5 in tx path 0: No 1: Yes</comment>
        </bits>
        <bits access="rw" name="clk_aud_if_6p5m_rx_inv_en" pos="0" rst="0">
          <comment>Whether Adie audio controller use inverse of clk_aud6m5 in rx path 0: No 1: Yes</comment>
        </bits>
      </reg>
      <reg name="chgr_ctrl0" protect="rw">
        <bits access="rw" name="chgr_dpm" pos="14:13" rst="3">
          <comment>VCHG tracking voltage level for automatic input control loop(AICL) 00: 3.8V 01: 3.95V 10: 4.3V 11: 4.5V Default value is 11</comment>
        </bits>
        <bits access="rw" name="chgr_cc_en" pos="12" rst="0">
          <comment>Charger CC mode enable, high effective</comment>
        </bits>
        <bits access="rw" name="chgr_cv_v" pos="10:5" rst="16">
          <comment>Charger battery sense DAC (CC-CV trans-point control)</comment>
        </bits>
        <bits access="rw" name="chgr_end_v" pos="4:3" rst="0">
          <comment>Charger battery charging end voltage 00: Vend=4.2V 01: Vend=4.3V 10: Vend=4.4V 11: Vend=4.5V</comment>
        </bits>
        <bits access="rw" name="chgr_iterm" pos="2:1" rst="0">
          <comment>Termination charger current programmable bits 00:cc*0.9 01:cc*0.4 10:cc*0.2 11:cc*0.1</comment>
        </bits>
        <bits access="rw" name="chgr_pd" pos="0" rst="0">
          <comment>Charger power down</comment>
        </bits>
      </reg>
      <reg name="chgr_ctrl1" protect="rw">
        <bits access="rw" name="chgr_expower_device" pos="15" rst="0">
          <comment>Choice of charger external power device 0:PNP+NMOS 1:PMOS+DIODE Default value is 0</comment>
        </bits>
        <bits access="rw" name="chgr_cc_i" pos="13:10" rst="0">
          <comment>CC mode charging current 0000:300mA        0001 : 350 0010: 400mA       0011 : 450 0100: 500mA       0101 :550 0110: 600mA       0111: 650 1000: 700mA       1001: 750 1010: 800mA       1011: 900 1100: 1000mA       1101: 1100 1110: 1200mA     1111: 1300 Default4'b0</comment>
        </bits>
        <bits access="rw" name="vchg_ovp_v" pos="1:0" rst="1">
          <comment>control bits of over voltage protection for VCHG. When VCHG is above some level set by these 2 bits, charger power down and CHGR_OVI becomes high. 00: 6.0V     01: 6.5V    10: 7.0V    11: 9.7V Default 2'b01</comment>
        </bits>
      </reg>
      <reg name="chgr_status" protect="rw">
        <bits access="rw" name="chgr_int_en" pos="13" rst="0">
          <comment>Chgr_int enable after CHG_DET_DONE</comment>
        </bits>
        <bits access="r" name="non_dcp_int" pos="12" rst="0">
          <comment>Charging port of NON-DCP status &quot;1&quot; Charging port is NON-DCP &quot;0&quot; Charging port is not NON-DCP</comment>
        </bits>
        <bits access="r" name="chg_det_done" pos="11" rst="0">
          <comment>Charging detect done after charger insert once</comment>
        </bits>
        <bits access="r" name="dp_low" pos="10" rst="0">
          <comment>The output of the comparator of DCD detection or SDP/NON-DCP detection &quot;1&quot; means DCD pass when doing DCD, or SDP if CHG_DET=0 &quot;0&quot; means DCD fail when doing DCD, or NON-DCP if CHG_DET=0</comment>
        </bits>
        <bits access="r" name="dcp_det" pos="9" rst="0">
          <comment>The output of the comparator of  DCP_DET loop &quot;1&quot;  means DCP if CHG_DET is &quot;1&quot; &quot;0&quot; means CDP if CHG_DET is &quot;1&quot;</comment>
        </bits>
        <bits access="r" name="chg_det" pos="8" rst="0">
          <comment>The output of the comparator of CHG_DET loop &quot;1&quot; DCP or CDP &quot;0&quot; SDP or NON-DCP</comment>
        </bits>
        <bits access="r" name="sdp_int" pos="7" rst="0">
          <comment>Charging port  of SDP status &quot;1&quot; Charging port is SDP &quot;0&quot; Charging port is not SDP</comment>
        </bits>
        <bits access="r" name="dcp_int" pos="6" rst="0">
          <comment>Charging port of DCP status &quot;1&quot; Charging port is DCP &quot;0&quot; Charging port is not DCP</comment>
        </bits>
        <bits access="r" name="cdp_int" pos="5" rst="0">
          <comment>Charging  port of CDP status &quot;1&quot; Charging port is CDP &quot;0&quot; Charging port is not CDP</comment>
        </bits>
        <bits access="r" name="chgr_cv_status" pos="4" rst="0">
          <comment>Flag when charging current below some level(0.5*full current) in CV mode High effective</comment>
        </bits>
        <bits access="r" name="chgr_on" pos="3" rst="0">
          <comment>Charger voltage ready indicator, high effective When VCHG&lt;4.1V: &quot;0&quot; When VCHG&gt;4.3V: &quot;1&quot;</comment>
        </bits>
        <bits access="r" name="chgr_int" pos="2" rst="0">
          <comment>Charger present indicator, high effective When VCHG&lt;3.1V: &quot;0&quot; When VCHG&gt;3.3V: &quot;1&quot;</comment>
        </bits>
        <bits access="rw" name="dcp_switch_en" pos="1" rst="1">
          <comment>0: switch DPDM to USB phy when DCP 1: keep to connect charger detector when DCP</comment>
        </bits>
        <bits access="r" name="vchg_ovi" pos="0" rst="0">
          <comment>VCHG over voltage(programmable) flag When VCHG higher than some voltage set by VCHG_OVP_V&lt;5:0&gt; and lasts 2mS, CHGR_OVI=&quot;1&quot; The hysteresis voltage is 600mV.</comment>
        </bits>
      </reg>
      <reg name="chgr_det_fgu_ctrl" protect="rw">
        <bits access="rw" name="fgua_soft_rst" pos="13" rst="0">
          <comment>FGU ANA soft reset</comment>
        </bits>
        <bits access="rw" name="ldo_fgu_pd" pos="12" rst="0">
          <comment>LDO FGU power down control 0: Normal Mode 1: Power Down Mode</comment>
        </bits>
        <bits access="rw" name="chg_int_delay" pos="11:9" rst="0">
          <comment>charger int delay time: 000:0ms 001:64ms 010:264ms.. 111:764ms</comment>
        </bits>
        <bits access="rw" name="sd_chop_cap_en" pos="8" rst="1">
          <comment>ADC chop enable</comment>
        </bits>
        <bits access="rw" name="sd_clk_p" pos="7:6" rst="0">
          <comment>ADC clock programming bits</comment>
        </bits>
        <bits access="rw" name="sd_adc0_rc_pd" pos="5" rst="0">
          <comment>input RC for ADC0 input filtering select signal: 0: ADC0 input with RC filtering 1: ADC0 input without RC filtering</comment>
        </bits>
        <bits access="rw" name="sd_chop_en" pos="4" rst="1">
          <comment>0: ADC0 input with RC filtering</comment>
        </bits>
        <bits access="rw" name="sd_dcoffset_b_en" pos="3" rst="0">
          <comment>1: ADC0 input without RC filtering</comment>
        </bits>
        <bits access="rw" name="sd_dcoffset_a_en" pos="2" rst="0">
          <comment>SD ADC_A  will be dc offset calibration Code       mode 0(default)   off 1           on</comment>
        </bits>
        <bits access="rw" name="dp_dm_aux_en" pos="1" rst="0">
          <comment>DP DM to auxADC select signal: &quot;0&quot;: switch off, no DP/DM to auxADC &quot;1&quot;: switch on, DP/DM to auxADC</comment>
        </bits>
        <bits access="rw" name="dp_dm_bc_enb" pos="0" rst="0">
          <comment>The DP DM path switch enable &quot;1&quot; switch on, BC1P2 disable &quot;0&quot; invalid</comment>
        </bits>
      </reg>
      <reg name="ovlo_ctrl" protect="rw">
        <bits access="rw" name="vbat_crash_v" pos="11:10" rst="0">
          <comment>Battery crash voltage setting: 00: 2.1V (default) 01: 2.2V 10: 2.3V 11: 2.5V</comment>
        </bits>
        <bits access="rw" name="ovlo_en" pos="9" rst="1">
          <comment>Over voltage locked-out enable (high effective) Default &quot;1&quot;</comment>
        </bits>
        <bits access="rw" name="ovlo_v" pos="3:2" rst="0">
          <comment>Over voltage locked-out detecting time 00 : 5.0V (default) 01 : 5.2V 10 : 4.8V 11 : 4.2V</comment>
        </bits>
        <bits access="rw" name="ovlo_t" pos="1:0" rst="0">
          <comment>Over voltage locked-out detecting time 00 : 1ms (default) 01 : 0.5ms 10 : 0.25ms 11 : 2ms</comment>
        </bits>
      </reg>
      <reg name="mixed_ctrl" protect="rw">
        <bits access="rw" name="xosc32k_ctl" pos="12" rst="1">
          <comment>Schmitt Trigger 0: no Schmitt trigger 1: Schmitt trigger(default)</comment>
        </bits>
        <bits access="rw" name="baton_t" pos="11:10" rst="0">
          <comment>Control bit of de-glitch time for battery remove &quot;00&quot; 32us    &quot;01&quot; 64us    &quot;10&quot; 128us    &quot;11&quot; no de-glitch         default&quot;00&quot;</comment>
        </bits>
        <bits access="rw" name="vpp_5v_sel" pos="9" rst="0">
          <comment>when VPP tie to 5V should shet VPP_5V_SEL=1</comment>
        </bits>
        <bits access="r" name="batdet_ok" pos="8" rst="0">
          <comment>Battery presence flag to SW and POCV, so need RTC domain &quot;0&quot; no battery &quot;1&quot; battery presence</comment>
        </bits>
        <bits access="r" name="vbat_ok" pos="4" rst="0">
          <comment>VBAT detect. Active &quot;0&quot; is reset, no need 32K osc.</comment>
        </bits>
        <bits access="rw" name="all_gpi_deb" pos="3" rst="0">
          <comment>ALL GPI source debug</comment>
        </bits>
        <bits access="rw" name="gpi_debug_en" pos="2" rst="0">
          <comment>GPI debug enable</comment>
        </bits>
        <bits access="rw" name="all_int_deb" pos="1" rst="0">
          <comment>ALL_INT debug, if 1, interrupt will be sent</comment>
        </bits>
        <bits access="rw" name="int_debug_en" pos="0" rst="0">
          <comment>Interupt debug enable</comment>
        </bits>
      </reg>
      <reg name="por_rst_monitor" protect="rw">
        <bits access="rw" name="por_rst_monitor" pos="15:0" rst="0">
          <comment>When POR reset active, this register is reset to 0</comment>
        </bits>
      </reg>
      <reg name="wdg_rst_monitor" protect="rw">
        <bits access="rw" name="wdg_rst_monitor" pos="15:0" rst="0">
          <comment>When WDG reset active, this register is reset to 0</comment>
        </bits>
      </reg>
      <reg name="por_pin_rst_monitor" protect="rw">
        <bits access="rw" name="pro_pin_rst_monitor" pos="15:0" rst="0">
          <comment>When POR_EXT_RST active, this register is reset to 0</comment>
        </bits>
      </reg>
      <reg name="por_src_flag" protect="rw">
        <bits access="rw" name="por_sw_force_on" pos="15" rst="0">
          <comment>Setting this bit could disable the 1S debouncing time of power key after boot.</comment>
        </bits>
        <bits access="rc" name="reg_soft_rst_flg_clr" pos="14" rst="0">
          <comment>bit type is changed from wc to rc.
          register reset flag clear</comment>
        </bits>
        <bits access="r" name="por_src_flag" pos="13:0" rst="0">
          <comment>Power on source flag:
[0]: Debounced PBINT signal, set when PBINT=0 &gt;50ms, clear when PBINT=1&gt;50ms.
[1]: PBINT initiating power-up hardware flag, set when PBINT=0&gt;1s, clear after power down.
[2]: Debounced PBINT2 signal, set when PBINT2=0 &gt;50ms, clear when PBINT2=1&gt;50ms.
[3]: PBINT2 initiating power-up hardware flag, set when PBINT2=0&gt;1s, clear after power down.
[4]: Debounced CHGR_INT signal, set when VCHG=1 &gt;50ms, clear when VCHG=0&gt;50ms.
[5]: Charger plug-in initiating power-up hardware flag, set when VCHG=1&gt;1s, clear after power down.
[6]: RTC alarm initiating power-up hardware flag
[7]: Long pressing power key reboot hardware flag, set when PBINT=0&gt;PBINT_7S_THRESHOLD, clear after power down.
[8]: PBINT initiating power-up software flag, set when PBINT=0&gt;1s, clear by pbint_flag_clr.
[9]: PBINT2 initiating power-up software flag, set when PBINT2=0&gt;1s, clear by pbint2_flag_clr.
[10]: Charger plug-in initiating power-up software flag, set when VCHG=1&gt;1s, clear by chgr_int_flag_clr.
[11: External pin reset reboot software flag, set when EXTRSTN=0&gt;30ms, clear by ext_rstn_flag_clr.
[12]: Long pressing power key reboot software flag, set when PBINT=0&gt;PBINT_7S_THRESHOLD, clear by pbint_7s_flag.
[13]: flag when register reset happened</comment>
        </bits>
      </reg>
      <reg name="por_off_flag" protect="rw">
        <bits access="r" name="por_chip_pd_flag" pos="13" rst="0">
          <comment>uvlo + ovlo chip power down flag</comment>
        </bits>
        <bits access="rc" name="por_chip_pd_flag_clr" pos="12" rst="0">
          <comment>bit type is changed from wc to rc.
          uvlo  + ovlo chip power down flag clear</comment>
        </bits>
        <bits access="r" name="uvlo_chip_pd_flag" pos="11" rst="0">
          <comment>uvlo chip power down flag</comment>
        </bits>
        <bits access="rc" name="uvlo_chip_pd_flag_clr" pos="10" rst="0">
          <comment>bit type is changed from wc to rc.
          uvlo chip power down flag clear</comment>
        </bits>
        <bits access="r" name="hard_7s_chip_pd_flag" pos="9" rst="0">
          <comment>7s hard chip power down flag</comment>
        </bits>
        <bits access="rc" name="hard_7s_chip_pd_flag_clr" pos="8" rst="0">
          <comment>bit type is changed from wc to rc.
          7s hard chip power down flag clear</comment>
        </bits>
        <bits access="r" name="sw_chip_pd_flag" pos="7" rst="0">
          <comment>OTP chip power down flag</comment>
        </bits>
        <bits access="rc" name="sw_chip_pd_flag_clr" pos="6" rst="0">
          <comment>bit type is changed from wc to rc.
          OTP chip power down flag clear</comment>
        </bits>
        <bits access="r" name="hw_chip_pd_flag" pos="5" rst="0">
          <comment>HW chip power down flag</comment>
        </bits>
        <bits access="rc" name="hw_chip_pd_flag_clr" pos="4" rst="0">
          <comment>bit type is changed from wc to rc.
          HW chip power down flag clear</comment>
        </bits>
        <bits access="r" name="otp_chip_pd_flag" pos="3" rst="0">
          <comment>OTP chip power down flag</comment>
        </bits>
        <bits access="rc" name="otp_chip_pd_flag_clr" pos="2" rst="0">
          <comment>bit type is changed from wc to rc.
          OTP chip power down flag clear</comment>
        </bits>
      </reg>
      <reg name="por_7s_ctrl" protect="rw">
        <bits access="rw" name="pbint_7s_flag_clr" pos="15" rst="0">
          <comment>Write 1'b1 to this bit will clear pbint_7s_flag.</comment>
        </bits>
        <bits access="rw" name="ext_rstn_flag_clr" pos="14" rst="0">
          <comment>Write 1'b1 to this bit will clear ext_rstn_flag.</comment>
        </bits>
        <bits access="rw" name="chgr_int_flag_clr" pos="13" rst="0">
          <comment>Write 1'b1 to this bit will clear chgr_int_flag.</comment>
        </bits>
        <bits access="rw" name="pbint2_flag_clr" pos="12" rst="0">
          <comment>Write 1'b1 to this bit will clear pbint2_flag.</comment>
        </bits>
        <bits access="rw" name="pbint_flag_clr" pos="11" rst="0">
          <comment>Write 1'b1 to this bit will clear pbint_flag.</comment>
        </bits>
        <bits access="rw" name="key2_7s_rst_en" pos="9" rst="0">
          <comment>1: One-key Reset Mode;</comment>
        </bits>
        <bits access="rw" name="pbint_7s_rst_swmode" pos="8" rst="1">
          <comment>0: long reset;</comment>
        </bits>
        <bits access="rw" name="pbint_7s_rst_threshold" pos="7:4" rst="6">
          <comment>The power key long pressing time threshold: 0~1: 2S 2: 3S 3: 4S 4: 5S 5: 6S 6: 7S 7: 8S 8: 9S 9: 10S 10:11S 11:12S 12: 13S 13:14S 14:15S 15:16S</comment>
        </bits>
        <bits access="rw" name="ext_rstn_mode" pos="3" rst="0">
          <comment>EXT_RSTN PIN function mode when 1key 7S reset 0: EXT_INT 1: RESET</comment>
        </bits>
        <bits access="rw" name="pbint_7s_auto_on_en" pos="2" rst="1">
          <comment>RTC register PBINT_7S_AUTO_ON_EN</comment>
        </bits>
        <bits access="rw" name="pbint_7s_rst_disable" pos="1" rst="0">
          <comment>0: enable 7s reset function; 1: disable 7s reset function;</comment>
        </bits>
        <bits access="rw" name="pbint_7s_rst_mode" pos="0" rst="1">
          <comment>0: software reset; 1: hardware reset;</comment>
        </bits>
      </reg>
      <reg name="hwrst_rtc" protect="rw">
        <bits access="r" name="hwrst_rtc_reg_sts" pos="15:8" rst="0">
          <comment>RTC status register, set by HWRST_RTC_SET.</comment>
        </bits>
        <bits access="rw" name="hwrst_rtc_reg_set" pos="7:0" rst="0">
          <comment>Software set this register to test VBAT and RTC power status.</comment>
        </bits>
      </reg>
      <reg name="arch_en" protect="rw">
        <bits access="rw" name="arch_en" pos="0" rst="1">
          <comment>PCLK_arch enable</comment>
        </bits>
      </reg>
      <reg name="mcu_wr_prot_value" protect="rw">
        <bits access="r" name="mcu_wr_prot" pos="15" rst="0">
          <comment>Arch_en write protect bit status. When mcu_wr_prot_value==16'h3c4d, the bit is &quot;1&quot;,else &quot;0&quot;</comment>
        </bits>
        <bits access="w" name="mcu_wr_prot_value" pos="14:0" rst="0">
          <comment>Arch_en write protect value</comment>
        </bits>
      </reg>
      <reg name="pwr_wr_prot_value" protect="rw">
        <bits access="r" name="pwr_wr_prot" pos="15" rst="0">
          <comment>All power which default on write protect bit status. When mcu_wr_prot_value==16'h6e7f, the bit is &quot;1&quot;,else &quot;0&quot;</comment>
        </bits>
        <bits access="w" name="pwr_wr_prot_value" pos="14:0" rst="0">
          <comment>Arch_en write protect value</comment>
        </bits>
      </reg>
      <reg name="smpl_ctrl0" protect="rw">
        <bits access="rw" name="smpl_mode" pos="15:0" rst="0">
          <comment>SMPL mode: [15:13]: SMPL timer threshold 0: 0.25s 1: 0.5s 2: 0.75s.. 7: 2s [12:0]: SMPL enable 13'h1935: enable Others:     disable</comment>
        </bits>
      </reg>
      <reg name="smpl_ctrl1" protect="rw">
        <bits access="r" name="smpl_pwr_on_flag" pos="15" rst="0">
          <comment>Set once SMPL timer not expired.</comment>
        </bits>
        <bits access="r" name="smpl_mode_wr_ack_flag" pos="14" rst="0">
          <comment>Set once SMPL mode write finish</comment>
        </bits>
        <bits access="rc" name="smpl_pwr_on_flag_clr" pos="13" rst="0">
          <comment>bit type is changed from wc to rc.
          Clear SMPL_PWR_ON_FLAG</comment>
        </bits>
        <bits access="rc" name="smpl_mode_wr_ack_flag_clr" pos="12" rst="0">
          <comment>bit type is changed from wc to rc.
          Clear SMPL_MODE_WR_ACK</comment>
        </bits>
        <bits access="r" name="smpl_pwr_on_set" pos="11" rst="0">
          <comment>Set once SMPL timer not expired,</comment>
        </bits>
        <bits access="r" name="smpl_en" pos="0" rst="0">
          <comment>SMPL enable indication</comment>
        </bits>
      </reg>
      <reg name="rtc_rst0" protect="rw">
        <bits access="rw" name="rtc_clk_flag_set" pos="15:0" rst="0">
          <comment>RTC register flag</comment>
        </bits>
      </reg>
      <reg name="rtc_rst1" protect="rw">
        <bits access="rw" name="rtc_clk_flag_clr" pos="15:0" rst="0">
          <comment>RTC register flag</comment>
        </bits>
      </reg>
      <reg name="rtc_rst2" protect="r">
        <bits access="r" name="rtc_clk_flag_rtc" pos="15:0" rst="42390">
          <comment>RTC register flag, reset by RTC_RST, default is 16'hA596</comment>
        </bits>
      </reg>
      <reg name="rtc_clk_stop" protect="rw">
        <bits access="r" name="rtc_clk_stop_flag" pos="7" rst="0">
          <comment>rtc time over thresthold value</comment>
        </bits>
        <bits access="rw" name="rtc_clk_stop_threshold" pos="6:0" rst="16">
          <comment>set reset rtc cnt time,default 16s</comment>
        </bits>
      </reg>
      <reg name="vbat_drop_cnt" protect="r">
        <bits access="r" name="vbat_drop_cnt" pos="11:0" rst="0">
          <comment>VBAT Drop Time Count</comment>
        </bits>
      </reg>
      <reg name="swrst_ctrl0" protect="rw">
        <bits access="rw" name="ext_rstn_pd_en" pos="10" rst="0">
          <comment>Software reset certain power enable when ext_rstn valid</comment>
        </bits>
        <bits access="rw" name="pb_7s_rst_pd_en" pos="9" rst="0">
          <comment>Software reset certain power enable when pb_7s_rst valid</comment>
        </bits>
        <bits access="rw" name="reg_rst_pd_en" pos="8" rst="0">
          <comment>Software reset certain power enable when reg_rst valid</comment>
        </bits>
        <bits access="rw" name="wdg_rst_pd_en" pos="7" rst="0">
          <comment>Software reset certain power enable when wdg_rst valid</comment>
        </bits>
        <bits access="rw" name="reg_rst_en" pos="4" rst="0">
          <comment>register reset enable:</comment>
        </bits>
        <bits access="rw" name="sw_rst_pd_threshold" pos="3:0" rst="0">
          <comment>reset LDO to normal mode threshold time</comment>
        </bits>
      </reg>
      <reg name="swrst_ctrl1" protect="rw">
        <bits access="rw" name="sw_rst_dcdcgen_pd_en" pos="10" rst="0">
          <comment>Software reset DCDC_GEN_PD enable when global reset valid</comment>
        </bits>
        <bits access="rw" name="sw_rst_dcdccore_pd_en" pos="9" rst="0">
          <comment>Software reset DCDC_CORE_PD enable when global reset valid</comment>
        </bits>
        <bits access="rw" name="sw_rst_mem_pd_en" pos="8" rst="0">
          <comment>Software reset LDO_MEM_PD enable when global reset valid</comment>
        </bits>
        <bits access="rw" name="sw_rst_dcxo_pd_en" pos="7" rst="0">
          <comment>Software reset LDO_DCXO_PD enable when global reset valid</comment>
        </bits>
        <bits access="rw" name="sw_rst_vdd28_pd_en" pos="6" rst="0">
          <comment>Software reset LDO_VDD28_PD enable when global reset valid</comment>
        </bits>
        <bits access="rw" name="sw_rst_ana_pd_en" pos="5" rst="0">
          <comment>Software reset LDO_ANA_PD enable when global reset valid</comment>
        </bits>
        <bits access="rw" name="sw_rst_rf15_pd_en" pos="4" rst="0">
          <comment>Software reset LDO_RF18_PD enable when global reset valid</comment>
        </bits>
        <bits access="rw" name="sw_rst_usb33_pd_en" pos="3" rst="0">
          <comment>Software reset LDO_USB33_PD enable when global reset valid</comment>
        </bits>
        <bits access="rw" name="sw_rst_mmc_pd_en" pos="2" rst="0">
          <comment>Software reset LDO_MMC_PD enable when global reset valid</comment>
        </bits>
        <bits access="rw" name="sw_rst_ddr12_pd_en" pos="1" rst="0">
          <comment>Software reset LDO_DDR12_PD enable when global reset valid</comment>
        </bits>
        <bits access="rw" name="sw_rst_vio18_pd_en" pos="0" rst="0">
          <comment>Software reset LDO_VIO18_PD enable when global reset valid</comment>
        </bits>
      </reg>
      <reg name="otp_ctrl" protect="rw">
        <bits access="rw" name="otp_op" pos="2:1" rst="3">
          <comment>OTP threshold option, 00 135, 01 140,  10 145, 11 150;</comment>
        </bits>
        <bits access="rw" name="otp_en" pos="0" rst="0">
          <comment>OTP function enable control bit</comment>
        </bits>
      </reg>
      <reg name="free_timer_low" protect="r">
        <bits access="r" name="timer_low" pos="15:0" rst="0">
          <comment>low 16 bit value of  free timer</comment>
        </bits>
      </reg>
      <reg name="free_timer_high" protect="r">
        <bits access="r" name="timer_high" pos="15:0" rst="0">
          <comment>high 16 bit value of free timer</comment>
        </bits>
      </reg>
      <reg name="vol_tune_ctrl_core" protect="rw">
        <bits access="rw" name="core_clk_sel" pos="14" rst="0">
          <comment>clock source for CORE DVFS 0: clock 26M 1: clock 32K</comment>
        </bits>
        <bits access="rw" name="core_step_delay" pos="13:12" rst="0">
          <comment>delay between two steps 00:1*32k clock or 2us in 26M 01:2*32k clock or 4us in 26M 10:3*32k clock or 8us in 26M 11:4*32k clock or 16us in 26M</comment>
        </bits>
        <bits access="rw" name="core_step_num" pos="11:8" rst="0">
          <comment>step number</comment>
        </bits>
        <bits access="rw" name="core_step_vol" pos="7:3" rst="0">
          <comment>DVFS voltage per step 00000:0mv 00001:1*3.125mv 00010:2*3.125mv.. 11111:31*3.125mv</comment>
        </bits>
        <bits access="rc" name="core_vol_tune_start" pos="2" rst="0">
          <comment>bit type is changed from wc to rc.
          voltage tune start bit</comment>
        </bits>
        <bits access="r" name="core_vol_tune_flag" pos="1" rst="0">
          <comment>voltage tune flag 0:done 1:on going</comment>
        </bits>
        <bits access="rw" name="core_vol_tune_en" pos="0" rst="0">
          <comment>voltage tune enable 0: disable 1: enable</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_int.xml">
    <module category="RDA2720M" name="RDA2720M_INT">
      <reg name="int_mask_status" protect="r">
        <bits access="r" name="typec_int_mask_status" pos="8" rst="1">
          <comment>This interrupt is masked from TYPEC_INT_RAW_STATUS by TYPEC_INT_EN</comment>
        </bits>
        <bits access="r" name="cal_int_mask_status" pos="7" rst="1">
          <comment>This interrupt is masked from CAL_INT_RAW_STATUS by CAL_INT_EN</comment>
        </bits>
        <bits access="r" name="tmr_int_mask_status" pos="6" rst="1">
          <comment>This interrupt is masked from TMR_INT_RAW_STATUS by TMR_INT_EN</comment>
        </bits>
        <bits access="r" name="aud_protect_int_mask_status" pos="5" rst="1">
          <comment>This interrupt is masked from AUD_PROTECT_INT_RAW_STATUS by AUD_PROTECT_INT_EN</comment>
        </bits>
        <bits access="r" name="eic_int_mask_status" pos="4" rst="1">
          <comment>This interrupt is masked from EIC_INT_RAW_STATUS by EIC_INT_EN</comment>
        </bits>
        <bits access="r" name="fgu_int_mask_status" pos="3" rst="1">
          <comment>This interrupt is masked from FGU_INT_RAW_STATUS by FGU_INT_EN</comment>
        </bits>
        <bits access="r" name="wdg_int_mask_status" pos="2" rst="1">
          <comment>This interrupt is masked from WDG_INT_RAW_STATUS by WDG_INT_EN</comment>
        </bits>
        <bits access="r" name="rtc_int_mask_status" pos="1" rst="1">
          <comment>This interrupt is masked from RTC_INT_RAW_STATUS by RTC_INT_EN</comment>
        </bits>
        <bits access="r" name="adc_int_mask_status" pos="0" rst="1">
          <comment>This interrupt is masked from ADC_INT_RAW_STATUS by ADC_INT_EN</comment>
        </bits>
      </reg>
      <reg name="int_raw_status" protect="r">
        <bits access="r" name="typec_int_raw_status" pos="8" rst="1">
          <comment>typeC raw interrupt flag</comment>
        </bits>
        <bits access="r" name="cal_int_raw_status" pos="7" rst="1">
          <comment>calibration raw interrupt flag</comment>
        </bits>
        <bits access="r" name="tmr_int_raw_status" pos="6" rst="1">
          <comment>timer raw interrupt flag</comment>
        </bits>
        <bits access="r" name="aud_protect_int_raw_status" pos="5" rst="1">
          <comment>Audio protect raw interrupt flag</comment>
        </bits>
        <bits access="r" name="eic_int_raw_status" pos="4" rst="1">
          <comment>EIC raw interrupt flag</comment>
        </bits>
        <bits access="r" name="fgu_int_raw_status" pos="3" rst="1">
          <comment>FGU raw interrupt flag</comment>
        </bits>
        <bits access="r" name="wdg_int_raw_status" pos="2" rst="1">
          <comment>WDG raw interrupt flag</comment>
        </bits>
        <bits access="r" name="rtc_int_raw_status" pos="1" rst="1">
          <comment>RTC raw interrupt flag</comment>
        </bits>
        <bits access="r" name="adc_int_raw_status" pos="0" rst="1">
          <comment>auxADC raw interrupt flag</comment>
        </bits>
      </reg>
      <reg name="int_en" protect="rw">
        <bits access="rw" name="typec_int_en" pos="8" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable TYPEC_INT_RAW_STATUS to system</comment>
        </bits>
        <bits access="rw" name="cal_int_en" pos="7" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable CAL_INT_RAW_STATUS to system</comment>
        </bits>
        <bits access="rw" name="tmr_int_en" pos="6" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable TMR_INT_RAW_STATUS to system</comment>
        </bits>
        <bits access="rw" name="aud_protect_int_en" pos="5" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable AUD_PROTECT_INT_RAW_STATUS to system</comment>
        </bits>
        <bits access="rw" name="eic_int_en" pos="4" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable EIC_INT_RAW_STATUS to system</comment>
        </bits>
        <bits access="rw" name="fgu_int_en" pos="3" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable FGU_INT_RAW_STATUS to system</comment>
        </bits>
        <bits access="rw" name="wdg_int_en" pos="2" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable WDG_INT_RAW_STATUS to system</comment>
        </bits>
        <bits access="rw" name="rtc_int_en" pos="1" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable RTC_INT_RAW_STATUS to system</comment>
        </bits>
        <bits access="rw" name="adc_int_en" pos="0" rst="1">
          <comment>bit type is changed from r/w to rw.
          Enable ADC_INT_RAW_STATUS to system</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_pin.xml">
    <module category="RDA2720M" name="RDA2720M_PIN">
      <reg name="ptest_o" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="0">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="1">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="adi_sclk" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="0">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="adi_d" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="3">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="0">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="ext_xtl_en0" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="1">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: default normal function selection 2b01: GPO 0 function selection 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="1">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="1">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="ext_xtl_en1" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="1">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: default normal function selection 2b01: GPO 1 function selection  2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="1">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="1">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="ext_xtl_en2" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="1">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select: 2b00: default normal function selection 2b01: GPO 2 function selection  2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="1">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="1">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="ext_xtl_en3" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="1">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: default normal function selection 2b01: GPO 3 function selection  2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="1">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="1">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="chip_sleep" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="1">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="clk_32k" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="0">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="1">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="ana_int" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="0">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="1">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="aud_adsync" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="0">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="1">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="aud_add0" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: default normal functon sel 2b01: VAD ADCL data function sel  2b10: VAD ADCR data function sel 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="0">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="1">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="aud_dasync" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="1">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="aud_da0" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="1">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="aud_da1" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="1">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="aud_sclk" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="1">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="0">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
      <reg name="ext_rst_b" protect="rw">
        <bits access="rw" name="pin_name_drv" pos="9:8" rst="1">
          <comment>Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpu" pos="7" rst="0">
          <comment>Weakly pull up for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_func_wpd" pos="6" rst="0">
          <comment>Weakly pull down for function mode</comment>
        </bits>
        <bits access="rw" name="pin_name_sel" pos="5:4" rst="0">
          <comment>Function select:  2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3</comment>
        </bits>
        <bits access="rw" name="pin_name_wpu" pos="3" rst="0">
          <comment>Weak pull up for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_wpd" pos="2" rst="0">
          <comment>Weak pull down for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_ie" pos="1" rst="0">
          <comment>Input enable for chip deep sleep mode</comment>
        </bits>
        <bits access="rw" name="pin_name_oe" pos="0" rst="1">
          <comment>Output enable for chip deep sleep mode</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_psm.xml">
    <module category="RDA2720M" name="RDA2720M_PSM">
      <reg name="psm_reg_wr_protect" protect="rw">
        <bits access="rw" name="psm_reg_wr" pos="15:0" rst="0">
          <comment>if write 0x454e to enable write psm reg,  readback only [15] is high</comment>
        </bits>
      </reg>
      <reg name="psm_32k_cal_th" protect="rw">
        <bits access="rw" name="rc_32k_cal_pre_th" pos="11:8" rst="8">
          <comment>psm calibration pre time. The time is from pull DCXO high to OSC 26M stable. unit is (clk_cal_64k_div_th +1)ms</comment>
        </bits>
        <bits access="rw" name="rc_32k_cal_cnt_n" pos="3:0" rst="7">
          <comment>psm calibration time 1s/(2^(16-rc_32k_cal_cnt_n))/( rc_32k_cal_cnt_p+1)</comment>
        </bits>
      </reg>
      <reg name="psm_26m_cal_dn_th" protect="rw">
        <bits access="rw" name="rc_26m_cal_cnt_dn_th" pos="15:0" rst="0">
          <comment>psm 26m calibration value update down threshold.
Value = (1/2)*26*10^6/(2^(16-rc_32k_cal_cnt_n)) /(2^9)</comment>
        </bits>
      </reg>
      <reg name="psm_26m_cal_up_th" protect="rw">
        <bits access="rw" name="rc_26m_cal_cnt_up_th" pos="15:0" rst="0">
          <comment>psm 26m calibration value update up threshold
Value = (3/2)*26*10^6/(2^(16-rc_32k_cal_cnt_n)) /(2^9)</comment>
        </bits>
      </reg>
      <reg name="psm_ctrl" protect="rw">
        <bits access="rw" name="rtc_32k_clk_sel" pos="15" rst="0">
          <comment>1'b1: rtc use psm cal 32K clock in 32K less mode,1'b0:rtc use RC 32K clock in 32K less mode</comment>
        </bits>
        <bits access="rw" name="psm_cal_en" pos="12" rst="0">
          <comment>enable psm cal</comment>
        </bits>
        <bits access="rw" name="psm_status_clr" pos="11" rst="0">
          <comment>clear psm int status</comment>
        </bits>
        <bits access="rw" name="psm_cnt_en" pos="10" rst="0">
          <comment>enble psm timer cnt</comment>
        </bits>
        <bits access="rw" name="psm_cnt_update" pos="9" rst="0">
          <comment>posedge to update psm cnt value</comment>
        </bits>
        <bits access="rw" name="psm_software_reset" pos="8" rst="0">
          <comment>software reset psm module, auto clear</comment>
        </bits>
        <bits access="rw" name="psm_cnt_alm_en" pos="7" rst="0">
          <comment>enable psm timer to wake up sys</comment>
        </bits>
        <bits access="rw" name="psm_cnt_alarm_en" pos="6" rst="0">
          <comment>enable psm alarm function</comment>
        </bits>
        <bits access="rw" name="charger_pwr_en" pos="5" rst="0">
          <comment>enable charger to power on sys</comment>
        </bits>
        <bits access="rw" name="pbint2_pwr_en" pos="4" rst="0">
          <comment>enable pbint2 to power on sys</comment>
        </bits>
        <bits access="rw" name="pbint1_pwr_en" pos="3" rst="0">
          <comment>enable pbint1 to power on sys</comment>
        </bits>
        <bits access="rw" name="ext_int_pwr_en" pos="2" rst="0">
          <comment>enable ext int to power on sys</comment>
        </bits>
        <bits access="rw" name="rtc_pwr_on_timeout_en" pos="1" rst="0">
          <comment>enable rtc power on time out detect</comment>
        </bits>
        <bits access="rw" name="psm_en" pos="0" rst="0">
          <comment>enable psm fsm</comment>
        </bits>
      </reg>
      <reg name="rtc_pwr_off_th1" protect="rw">
        <bits access="rw" name="rtc_pwr_off_hold_th" pos="15:8" rst="4">
          <comment>The time to hold rtc ISO in power off rtc state, (clk_cal_64k_div_th +1)ms</comment>
        </bits>
        <bits access="rw" name="rtc_pwr_off_clk_en_th" pos="7:0" rst="2">
          <comment>The time to disable rtc clk  in power off rtc state, unit is (clk_cal_64k_div_th +1)ms</comment>
        </bits>
      </reg>
      <reg name="rtc_pwr_off_th2" protect="rw">
        <bits access="rw" name="rtc_pwr_off_pd_th" pos="15:8" rst="8">
          <comment>The time to hold rtc ISO in power off rtc state, (clk_cal_64k_div_th +1)ms</comment>
        </bits>
        <bits access="rw" name="rtc_pwr_off_rstn_th" pos="7:0" rst="6">
          <comment>The time to reset rtc in power off rtc state, unit is (clk_cal_64k_div_th +1)ms</comment>
        </bits>
      </reg>
      <reg name="rtc_pwr_off_th3" protect="rw">
        <bits access="rw" name="rtc_pwr_off_done_th" pos="7:0" rst="16">
          <comment>The time to power off rtc done  in power off rtc state, unit is (clk_cal_64k_div_th +1)ms</comment>
        </bits>
      </reg>
      <reg name="rtc_pwr_on_th1" protect="rw">
        <bits access="rw" name="rtc_pwr_on_rstn_th" pos="15:8" rst="64">
          <comment>The time to release reset in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms</comment>
        </bits>
        <bits access="rw" name="rtc_pwr_on_pd_th" pos="7:0" rst="1">
          <comment>The time to power on rtc , unit is 4*(clk_cal_64k_div_th +1)ms</comment>
        </bits>
      </reg>
      <reg name="rtc_pwr_on_th2" protect="rw">
        <bits access="rw" name="rtc_pwr_on_clk_en_th" pos="15:8" rst="3">
          <comment>The time to clock enable in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms</comment>
        </bits>
        <bits access="rw" name="rtc_pwr_on_hold_th" pos="7:0" rst="2">
          <comment>The time to release hold ISO in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms</comment>
        </bits>
      </reg>
      <reg name="rtc_pwr_on_th3" protect="rw">
        <bits access="rw" name="rtc_pwr_on_timeout_th" pos="15:8" rst="250">
          <comment>The time to mark power on timeout in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms</comment>
        </bits>
        <bits access="rw" name="rtc_pwr_on_done_th" pos="7:0" rst="255">
          <comment>The time to power on rtc done , unit is 4*(clk_cal_64k_div_th +1)ms</comment>
        </bits>
      </reg>
      <reg name="psm_cnt_l_th" protect="rw">
        <bits access="rw" name="psm_cnt_th[15:0]" pos="15:0" rst="32320">
          <comment>The low 16 bits threshold of psm time , unit is 10*(clk_cal_64k_div_th +1)ms</comment>
        </bits>
      </reg>
      <reg name="psm_cnt_h_th" protect="rw">
        <bits access="rw" name="psm_cnt_th[31:16]" pos="15:0" rst="5">
          <comment>The high 16 bits threshold of psm time , unit is 10ms</comment>
        </bits>
      </reg>
      <reg name="psm_alarm_cnt_l_th" protect="rw">
        <bits access="rw" name="psm_alarm_cnt_th[15:0]" pos="15:0" rst="65535">
          <comment>The low 16 bits threshold of psm alarm time , unit is 10*(clk_cal_64k_div_th +1)ms</comment>
        </bits>
      </reg>
      <reg name="psm_alarm_cnt_h_th" protect="rw">
        <bits access="rw" name="psm_alarm_cnt_th[31:16]" pos="15:0" rst="0">
          <comment>The high 16 bits threshold of psm alarm time</comment>
        </bits>
      </reg>
      <reg name="psm_cnt_interval_th" protect="rw">
        <bits access="rw" name="psm_cnt_interval_th[15:0]" pos="15:0" rst="0">
          <comment>The threshold of psm calibration interval , unit is (clk_cal_64k_div_th +1)ms</comment>
        </bits>
      </reg>
      <reg name="psm_cnt_interval_phase" protect="rw">
        <bits access="rw" name="psm_cnt_interval_phase[15:0]" pos="15:0" rst="60">
          <comment>The threshold of psm calibration interval , unit is (clk_cal_64k_div_th +1)ms</comment>
        </bits>
      </reg>
      <reg name="dcxo" protect="rw">
        <bits access="rw" name="ldo_dcxo_shpt_pd" pos="13" rst="0">
          <comment>DCXO LDO short protection</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_cap_sel" pos="12" rst="0">
          <comment>DCXO LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_stb" pos="11:10" rst="16">
          <comment>DCXO LDO stability compensation: default 2'b10</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_shpt_adj" pos="9" rst="1">
          <comment>DCXO LDO foldback current threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_cl_adj" pos="8" rst="1">
          <comment>DCXO LDO current limit threshold adjust: default 1'b1</comment>
        </bits>
        <bits access="rw" name="ldo_dcxo_v" pos="6:0" rst="24">
          <comment>DCXO voltage setting, 1.5~3.0875V,12.5mv step</comment>
        </bits>
      </reg>
      <reg name="psm_rc_clk_div" protect="rw">
        <bits access="rw" name="rc_32k_cal_cnt_p" pos="11:8" rst="0">
          <comment>Psm calibration divider,it is calculated with rc_32k_cal_cnt_n C log2(clk_cal_64k_div_th+1)</comment>
        </bits>
        <bits access="rw" name="clk_cal_64k_div_th" pos="6:4" rst="0">
          <comment>Psm rc 64K divider, the input RC clock is divider to CLK_64K/( clk_cal_64k_div_th+1)</comment>
        </bits>
        <bits access="rw" name="wdg_rst_clk_sel_en" pos="0" rst="0">
          <comment>Enable watchdog power on chip by internal RC clock</comment>
        </bits>
      </reg>
      <reg name="reserved_2" protect="rw">
      </reg>
      <reg name="reserved_3" protect="rw">
      </reg>
      <reg name="reserved_4" protect="rw">
      </reg>
      <reg name="reserved_5" protect="rw">
      </reg>
      <reg name="reserved_6" protect="rw">
      </reg>
      <reg name="psm_cnt_update_l_value" protect="r">
        <bits access="r" name="psm_cnt_update_value[15:0]" pos="15:0" rst="0">
          <comment>Psm cnt updated low 16 bits value, the step of read this value is :
(1)enable psm_cnt_update,
(2)wait till psm_cnt_update_vld ==1.(psm_fsm_status[6])</comment>
        </bits>
      </reg>
      <reg name="psm_cnt_update_h_value" protect="r">
        <bits access="r" name="psm_cnt_update_value[31:16]" pos="15:0" rst="0">
          <comment>Psm cnt updated high 16 bits value</comment>
        </bits>
      </reg>
      <reg name="psm_status" protect="rw">
        <bits access="rw" name="alarm_req_int_mask" pos="13" rst="0">
      </bits>
        <bits access="rw" name="psm_req_int_mask" pos="12" rst="0">
      </bits>
        <bits access="rw" name="charger_int_mask" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pbint2_int_mask" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pbint1_int_mask" pos="9" rst="0">
      </bits>
        <bits access="rw" name="ext_int_mask" pos="8" rst="0">
      </bits>
        <bits access="r" name="psm_cnt_update_vld" pos="6" rst="0">
          <comment>psm cnt updated valid</comment>
        </bits>
        <bits access="r" name="alarm_req_int" pos="5" rst="0">
          <comment>when psm_cnt_alarm_en==1, then if alarm cnt get psm_alarm_cnt_th, this bit is high,
When psm_status_clr is high, this bit is low</comment>
        </bits>
        <bits access="r" name="psm_req_int" pos="4" rst="0">
          <comment>when psm_cnt_en==1, then if psm cnt get psm_cnt_th, this bit is high,
When psm_status_clr is high, this bit is low</comment>
        </bits>
        <bits access="r" name="charger_int" pos="3" rst="0">
          <comment>when psm_cnt_alarm_en==1, then if alarm cnt get psm_alarm_cnt_th, this bit is high,
When psm_status_clr is high, this bit is low</comment>
        </bits>
        <bits access="r" name="pbint2_int" pos="2" rst="0">
          <comment>when pbint2_pwr_en==1, then if pbint2 is low, this bit is high,
When psm_status_clr is high, this bit is low</comment>
        </bits>
        <bits access="r" name="pbint1_int" pos="1" rst="0">
          <comment>when pbint1_pwr_en==1, then if pbint1 is low, this bit is high,
When psm_status_clr is high, this bit is low</comment>
        </bits>
        <bits access="r" name="ext_int" pos="0" rst="0">
          <comment>when ext_int_en==1, then if  ext_int is high, this bit is high,
When psm_status_clr is high, this bit is low</comment>
        </bits>
      </reg>
      <reg name="psm_fsm_status" protect="r">
        <bits access="r" name="psm_fsm" pos="14:0" rst="0">
          <comment>Only debug use</comment>
        </bits>
      </reg>
      <reg name="psm_cal_cnt" protect="r">
        <bits access="r" name="psm_cal_cnt" pos="15:0" rst="0">
          <comment>We can use this value to calculate the RC 64K clock real frequency. Rc_64k=( clk_cal_64k_div_th+1)*(2^ rc_32k_cal_cnt_p)*26*10^6/ (psm_cal_cnt*2^9)</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_rtc.xml">
    <module category="RDA2720M" name="RDA2720M_RTC">
      <reg name="rtc_sec_cnt_value" protect="r">
        <bits access="r" name="rtc_sec_cnt_value" pos="5:0" rst="0">
          <comment>RTC second counter value</comment>
        </bits>
      </reg>
      <reg name="rtc_min_cnt_value" protect="r">
        <bits access="r" name="rtc_min_cnt_value" pos="5:0" rst="0">
          <comment>RTC minute counter value</comment>
        </bits>
      </reg>
      <reg name="rtc_hrs_cnt_value" protect="r">
        <bits access="r" name="rtc_hrs_cnt_value" pos="4:0" rst="0">
          <comment>RTC hour counter value</comment>
        </bits>
      </reg>
      <reg name="rtc_day_cnt_value" protect="r">
        <bits access="r" name="rtc_day_cnt_value" pos="15:0" rst="0">
          <comment>RTC day counter value</comment>
        </bits>
      </reg>
      <reg name="rtc_sec_cnt_upd" protect="rw">
        <bits access="rw" name="rtc_sec_cnt_upd" pos="5:0" rst="6">
          <comment>bit type is changed from r/w to rw.
          RTC second counter update Write new counter value to this register to start a second counter updating operation in VDDRTC domain. Reading this register can get recent updating value.</comment>
        </bits>
      </reg>
      <reg name="rtc_min_cnt_upd" protect="rw">
        <bits access="rw" name="rtc_min_cnt_upd" pos="5:0" rst="6">
          <comment>bit type is changed from r/w to rw.
          RTC minute counter update Write new counter value to this register to start a minute counter updating operation in VDDRTC domain. Reading this register can get recent updating value.</comment>
        </bits>
      </reg>
      <reg name="rtc_hrs_cnt_upd" protect="rw">
        <bits access="rw" name="rtc_hrs_cnt_upd" pos="4:0" rst="5">
          <comment>bit type is changed from r/w to rw.
          RTC hour counter update Write new counter value to this register to start an hour counter updating operation in VDDRTC domain. Reading this register can get recent updating value.</comment>
        </bits>
      </reg>
      <reg name="rtc_day_cnt_upd" protect="rw">
        <bits access="rw" name="rtc_day_cnt_upd" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          RTC day counter update Write new counter value to this register to start a day counter updating operation in VDDRTC domain. Reading this register can get recent updating value.</comment>
        </bits>
      </reg>
      <reg name="rtc_sec_alm_upd" protect="rw">
        <bits access="rw" name="rtc_sec_alm_upd" pos="5:0" rst="6">
          <comment>bit type is changed from r/w to rw.
          RTC second alarm update Write new counter value to this register to start a second alarm updating operation in VDDRTC domain. Reading this register can get recent updating value.</comment>
        </bits>
      </reg>
      <reg name="rtc_min_alm_upd" protect="rw">
        <bits access="rw" name="rtc_min_alm_upd" pos="5:0" rst="6">
          <comment>bit type is changed from r/w to rw.
          RTC minute alarm update Write new counter value to this register to start a minute alarm updating operation in VDDRTC domain. Reading this register can get recent updating value.</comment>
        </bits>
      </reg>
      <reg name="rtc_hrs_alm_upd" protect="rw">
        <bits access="rw" name="rtc_hrs_alm_upd" pos="4:0" rst="5">
          <comment>bit type is changed from r/w to rw.
          RTC hour alarm update Write new counter value to this register to start an hour alarm updating operation in VDDRTC domain. Reading this register can get recent updating value.</comment>
        </bits>
      </reg>
      <reg name="rtc_day_alm_upd" protect="rw">
        <bits access="rw" name="rtc_day_alm_upd" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          RTC day alarm update Write new counter value to this register to start a day alarm updating operation in VDDRTC domain. Reading this register can get recent updating value.</comment>
        </bits>
      </reg>
      <reg name="rtc_int_en" protect="rw">
        <bits access="rw" name="rtc_day_alm_upd_int_en" pos="15" rst="1">
          <comment>Day alarm updating complete interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_hrs_alm_upd_int_en" pos="14" rst="1">
          <comment>Hour alarm updating complete interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_min_alm_upd_int_en" pos="13" rst="1">
          <comment>Minute alarm updating complete interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_sec_alm_upd_int_en" pos="12" rst="1">
          <comment>Second alarm updating complete interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_day_cnt_upd_int_en" pos="11" rst="1">
          <comment>Day counter updating complete interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_hrs_cnt_upd_int_en" pos="10" rst="1">
          <comment>Hour counter updating complete interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_min_cnt_upd_int_en" pos="9" rst="1">
          <comment>Minute counter updating complete interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_sec_cnt_upd_int_en" pos="8" rst="1">
          <comment>Second counter updating complete interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_spg_upd_int_en" pos="7" rst="1">
          <comment>Spare register updating complete interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_auxalm_int_en" pos="6" rst="1">
          <comment>auxiliary alarm interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_hrs_format_sel" pos="5" rst="1">
          <comment>Hour format select</comment>
        </bits>
        <bits access="rw" name="rtc_alm_int_en" pos="4" rst="1">
          <comment>alarm interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_day_int_en" pos="3" rst="1">
          <comment>day interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_hrs_int_en" pos="2" rst="1">
          <comment>hour interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_min_int_en" pos="1" rst="1">
          <comment>minute interrupt enable</comment>
        </bits>
        <bits access="rw" name="rtc_sec_int_en" pos="0" rst="1">
          <comment>Second interrupt enable</comment>
        </bits>
      </reg>
      <reg name="rtc_int_raw_sts" protect="r">
        <bits access="r" name="rtc_day_alm_upd_int_raw_sts" pos="15" rst="1">
          <comment>Day alarm updating complete interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_hrs_alm_upd_int_raw_sts" pos="14" rst="1">
          <comment>Hour alarm updating complete interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_min_alm_upd_int_raw_sts" pos="13" rst="1">
          <comment>Minute alarm updating complete interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_sec_alm_upd_int_raw_sts" pos="12" rst="1">
          <comment>Second alarm updating complete interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_day_cnt_upd_int_raw_sts" pos="11" rst="1">
          <comment>Day counter updating complete interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_hrs_cnt_upd_int_raw_sts" pos="10" rst="1">
          <comment>Hour counter updating complete interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_min_cnt_upd_int_raw_sts" pos="9" rst="1">
          <comment>Minute counter updating complete interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_sec_cnt_upd_int_raw_sts" pos="8" rst="1">
          <comment>Second counter updating complete interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_spg_upd_int_raw_sts" pos="7" rst="1">
          <comment>Spare register updating complete interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_auxalm_int_raw_sts" pos="6" rst="1">
          <comment>auxiliary alarm interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_alm_int0_raw_sts" pos="5" rst="1">
          <comment>Reserved for debug</comment>
        </bits>
        <bits access="r" name="rtc_alm_int_raw_sts" pos="4" rst="1">
          <comment>alarm interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_day_int_raw_sts" pos="3" rst="1">
          <comment>day interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_hrs_int_raw_sts" pos="2" rst="1">
          <comment>hour interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_min_int_raw_sts" pos="1" rst="1">
          <comment>minute interrupt raw status</comment>
        </bits>
        <bits access="r" name="rtc_sec_int_raw_sts" pos="0" rst="1">
          <comment>Second interrupt raw status</comment>
        </bits>
      </reg>
      <reg name="rtc_int_clr" protect="rw">
        <bits access="w" name="rtc_day_alm_upd_int_clr" pos="15" rst="1">
          <comment>Day alarm updating complete interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_hour_alm_upd_int_clr" pos="14" rst="1">
          <comment>Hour alarm updating complete interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_min_alm_upd_int_clr" pos="13" rst="1">
          <comment>Minute alarm updating complete interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_sec_alm_upd_int_clr" pos="12" rst="1">
          <comment>Second alarm updating complete interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_day_cnt_upd_int_clr" pos="11" rst="1">
          <comment>Day counter updating complete interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_hour_cnt_upd_int_clr" pos="10" rst="1">
          <comment>Hour counter updating complete interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_min_cnt_upd_int_clr" pos="9" rst="1">
          <comment>Minute counter updating complete interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_sec_cnt_upd_int_clr" pos="8" rst="1">
          <comment>Second counter updating complete interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_spg_upd_int_clr" pos="7" rst="1">
          <comment>Spare register updating complete interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_auxalm_int_clr" pos="6" rst="1">
          <comment>Auxiliary alarm interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_alm_int_clr" pos="4" rst="1">
          <comment>alarm interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_day_int_clr" pos="3" rst="1">
          <comment>day interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_hrs_int_clr" pos="2" rst="1">
          <comment>hour interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_min_int_clr" pos="1" rst="1">
          <comment>minute interrupt clear</comment>
        </bits>
        <bits access="w" name="rtc_sec_int_clr" pos="0" rst="1">
          <comment>Second interrupt clear</comment>
        </bits>
      </reg>
      <reg name="rtc_int_mask_sts" protect="r">
        <bits access="r" name="rtc_day_alm_upd_int_mask_sts" pos="15" rst="1">
          <comment>Day alarm updating complete interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_hrs_alm_upd_int_mask_sts" pos="14" rst="1">
          <comment>Hour alarm updating complete interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_min_alm_upd_int_mask_sts" pos="13" rst="1">
          <comment>Minute alarm updating complete interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_sec_alm_upd_int_mask_sts" pos="12" rst="1">
          <comment>Second alarm updating complete interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_day_cnt_upd_int_mask_sts" pos="11" rst="1">
          <comment>Day counter updating complete interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_hrs_cnt_upd_int_mask_sts" pos="10" rst="1">
          <comment>Hour counter updating complete interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_min_cnt_upd_int_mask_sts" pos="9" rst="1">
          <comment>Minute counter updating complete interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_sec_cnt_upd_int_mask_sts" pos="8" rst="1">
          <comment>Second counter updating complete interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_spg_upd_int_mask_sts" pos="7" rst="1">
          <comment>Spare register updating complete interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_auxalm_int_mask_sts" pos="6" rst="1">
          <comment>auxiliary alarm interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_alm_int_mask_sts" pos="4" rst="1">
          <comment>alarm interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_day_int_mask_sts" pos="3" rst="1">
          <comment>day interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_hrs_int_mask_sts" pos="2" rst="1">
          <comment>hour interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_min_int_mask_sts" pos="1" rst="1">
          <comment>minute interrupt masked status</comment>
        </bits>
        <bits access="r" name="rtc_sec_int_mask_sts" pos="0" rst="1">
          <comment>Second interrupt masked status</comment>
        </bits>
      </reg>
      <reg name="rtc_sec_alm_value" protect="r">
        <bits access="r" name="rtc_sec_alm_value" pos="5:0" rst="0">
          <comment>RTC second alarm value</comment>
        </bits>
      </reg>
      <reg name="rtc_min_alm_value" protect="r">
        <bits access="r" name="rtc_min_alm_value" pos="5:0" rst="0">
          <comment>RTC minute alarm value</comment>
        </bits>
      </reg>
      <reg name="rtc_hrs_alm_value" protect="r">
        <bits access="r" name="rtc_hrs_alm_value" pos="4:0" rst="0">
          <comment>RTC hour alarm value</comment>
        </bits>
      </reg>
      <reg name="rtc_day_alm_value" protect="r">
        <bits access="r" name="rtc_day_alm_value" pos="15:0" rst="0">
          <comment>RTC day alarm value</comment>
        </bits>
      </reg>
      <reg name="rtc_spg_value" protect="r">
        <bits access="r" name="rtc_spg_value" pos="15:8" rst="0">
          <comment>RTC spare register value</comment>
        </bits>
        <bits access="r" name="rtc_almlock_value" pos="7:0" rst="0">
          <comment>RTC alarm lock register value</comment>
        </bits>
      </reg>
      <reg name="rtc_spg_upd" protect="rw">
        <bits access="rw" name="rtc_spg_upd" pos="15:8" rst="0">
          <comment>bit type is changed from r/w to rw.
          RTC spare register update Write new counter value to this register to start a spare register updating operation in VDDRTC domain. Reading this register can get recent updating value.</comment>
        </bits>
        <bits access="rw" name="rtc_almlock_upd" pos="7:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          RTC alarm lock register update Write new counter value to this register to start a register updating operation in VDDRTC domain. Reading this register can get recent updating value. Write 8hA5 to this register to unlock alarm function, and write other data to lock alarm function. That means, software must 8hA5 to this register to enable alarm function before using this function.</comment>
        </bits>
      </reg>
      <reg name="rtc_pwr_flag_ctrl" protect="rw">
        <bits access="rw" name="rtc_pwr_flag_set" pos="15:8" rst="0">
          <comment>bit type is changed from r/w to rw.
          RTC power flag register set</comment>
        </bits>
        <bits access="rw" name="rtc_pwr_flag_clr" pos="7:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          RTC power flag register clear</comment>
        </bits>
      </reg>
      <reg name="rtc_pwr_flag_sts" protect="r">
        <bits access="r" name="rtc_pwr_flag_sts" pos="7:0" rst="0">
          <comment>RTC power flag status register</comment>
        </bits>
      </reg>
      <reg name="rtc_sec_auxalm_upd" protect="rw">
        <bits access="rw" name="rtc_sec_auxalm_upd" pos="5:0" rst="6">
          <comment>bit type is changed from r/w to rw.
          RTC second auxiliary alarm register</comment>
        </bits>
      </reg>
      <reg name="rtc_min_auxalm_upd" protect="rw">
        <bits access="rw" name="rtc_min_auxalm_upd" pos="5:0" rst="6">
          <comment>bit type is changed from r/w to rw.
          RTC minute auxiliary alarm register</comment>
        </bits>
      </reg>
      <reg name="rtc_hrs_auxalm_upd" protect="rw">
        <bits access="rw" name="rtc_hrs_auxalm_upd" pos="4:0" rst="5">
          <comment>bit type is changed from r/w to rw.
          RTC hour auxiliary alarm register</comment>
        </bits>
      </reg>
      <reg name="rtc_day_auxalm_upd" protect="rw">
        <bits access="rw" name="rtc_day_auxalm_upd" pos="15:0" rst="14">
          <comment>bit type is changed from r/w to rw.
          RTC day auxiliary alarm register</comment>
        </bits>
      </reg>
      <reg name="rtc_sec_cnt_raw" protect="r">
        <bits access="r" name="rtc_sec_cnt_raw" pos="5:0" rst="0">
          <comment>RTC second counter raw value Only for debug</comment>
        </bits>
      </reg>
      <reg name="rtc_min_cnt_raw" protect="r">
        <bits access="r" name="rtc_min_cnt_raw" pos="5:0" rst="0">
          <comment>RTC minute counter raw value</comment>
        </bits>
      </reg>
      <reg name="rtc_hrs_cnt_raw" protect="r">
        <bits access="r" name="rtc_hrs_cnt_raw" pos="4:0" rst="0">
          <comment>RTC hour counter raw value Only for debug</comment>
        </bits>
      </reg>
      <reg name="rtc_day_cnt_raw" protect="r">
        <bits access="r" name="rtc_day_cnt_raw" pos="15:0" rst="0">
          <comment>RTC day counter raw value Only for debug</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_tmr.xml">
    <module category="RDA2720M" name="RDA2720M_TMR">
      <reg name="timer_ip_version" protect="rw">
        <bits access="r" name="the_ip_version_of_this_timer" pos="15:4" rst="16">
          <comment>the IP version of this timer</comment>
        </bits>
        <bits access="rw" name="he_ip_patch_version_of_this_timer" pos="3:0" rst="0">
          <comment>the IP patch version of this timer</comment>
        </bits>
      </reg>
      <reg name="timer_load_l" protect="rw">
        <bits access="rw" name="timer_load_lo" pos="15:0" rst="0">
          <comment>timer load value of lower 16 bit.  Write to this register will reload the timer with the new value. In one-time mode, this value is the first counting start number. In periodic mode, this value is each counting start number.</comment>
        </bits>
      </reg>
      <reg name="timer_load_h" protect="rw">
        <bits access="rw" name="timer_load_hi" pos="15:0" rst="0">
          <comment>timer load value of higher 16 bit Write to this register will reload the timer with the new value. In one-time mode, this value is the first counting start number. In periodic mode, this value is each counting start number.</comment>
        </bits>
      </reg>
      <reg name="timer_ctrl" protect="rw">
        <bits access="rw" name="timer_run" pos="1" rst="0">
          <comment>timer open bit 0: timer stops 1: timer runs</comment>
        </bits>
        <bits access="rw" name="timer_mode" pos="0" rst="0">
          <comment>timer mode select 0: one-time mode 1: period mode</comment>
        </bits>
      </reg>
      <reg name="timer_int" protect="rw">
        <bits access="w" name="timer_int_clr" pos="3" rst="0">
          <comment>timer Interrupt clear</comment>
        </bits>
        <bits access="r" name="timer_int_mask_sts" pos="2" rst="0">
          <comment>timer interrupt masked status</comment>
        </bits>
        <bits access="r" name="timer_int_raw_sts" pos="1" rst="0">
          <comment>timer interrupt raw status</comment>
        </bits>
        <bits access="rw" name="timer_int_en" pos="0" rst="0">
          <comment>timer interrupt enable</comment>
        </bits>
      </reg>
      <reg name="timer_shdw_l" protect="r">
        <bits access="r" name="timer_value_shdw_lo" pos="15:0" rst="0">
          <comment>timer counter of lower 16bit shadow value for read. When the timer in 16 bit mode, it represent the shadow value of the timer This read-only register indicates current counter value. The software can read the counter value immediately after load, without waiting for the load done. Also, software just needs to read once instead of double read.</comment>
        </bits>
      </reg>
      <reg name="timer_shdw_h" protect="r">
        <bits access="r" name="timer_value_shdw_hi" pos="15:0" rst="0">
          <comment>timer counter of 16bit higher shadow value for read. It will be valid only in 64 bit mode. This read-only register indicates current counter value.The software can read the counter value immediately after load, without waiting for the load done. Also, software just needs to read once instead of double read.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda2720m_wdg.xml">
    <module category="RDA2720M" name="RDA2720M_WDG">
      <reg name="wdg_load_low" protect="rw">
        <bits access="rw" name="wdg_load_low" pos="15:0" rst="14">
          <comment>wdg_load_low: low 16 bit of watchdog timer load value. Wdg_load_high: high 16 bit of watchdog timer load value. wdg_load_low and wdg_load_high  are used together. Software should write wdg_load_high firstly, and then write wdg_load_low, because writing wdg_load_low can trig loading both wdg_load_low and wdg_load_high to watchdog counter, and writing wdg_load_high cannot trig this event. So software must guarantee w In reset mode, software should load new value before timer decrease to 0. In interrupt mode, this value is counting start number. The default value is about 8 seconds.</comment>
        </bits>
      </reg>
      <reg name="wdg_load_high" protect="rw">
        <bits access="rw" name="wdg_load_high" pos="15:0" rst="14">
          <comment>See wdg_load_low description</comment>
        </bits>
      </reg>
      <reg name="wdg_ctrl" protect="rw">
        <bits access="rw" name="wdg_rst_en" pos="3" rst="1">
          <comment>Watchdog reset enable bit 0: reset is disabled 1: reset is enabled In reset mode and combined mode, this bit should be 1</comment>
        </bits>
        <bits access="rw" name="wdg_new" pos="2" rst="1">
          <comment>Watchdog version 0: watchdog use old behavior, this is for backward compatibility. 1: watchdog uses new behavior, such as multiple loads without checking busy bit, only need to read once to get timer counter value.</comment>
        </bits>
        <bits access="rw" name="wdg_run" pos="1" rst="1">
          <comment>Watchdog counter open: 0: counter stops. 1: counter runs.</comment>
        </bits>
        <bits access="rw" name="wdg_irq_en" pos="0" rst="1">
          <comment>Watchdog interrupt enable bit 0: interrupt is disabled 1: interrupt is enabled In interrupt mode and combined mode, this bit should be 1</comment>
        </bits>
      </reg>
      <reg name="wdg_int_clr" protect="rw">
        <bits access="w" name="wdg_rst_clr" pos="3" rst="1">
          <comment>Watchdog reset clear Write 1 to this bit to clear reset Read this bit always get 0.</comment>
        </bits>
        <bits access="w" name="wdg_int_clr" pos="0" rst="1">
          <comment>Watchdog interrupt clear Write 1 to this bit to clear interrupt Read this bit always get 0.</comment>
        </bits>
      </reg>
      <reg name="wdg_int_raw" protect="r">
        <bits access="r" name="wdg_ld_busy" pos="4" rst="1">
          <comment>Watchdog load busy status 0: Watchdog is ready for new loading 1: Last loading is not completed Software must not load new value when this bit is busy, that is, this bit should be checked before any new loading. This bit is set after a new loading, and lasts two or three RTC clock cycles, about 60us - 92us.</comment>
        </bits>
        <bits access="r" name="wdg_rst_raw" pos="3" rst="1">
          <comment>Watchdog reset  raw status. Watch dog reset cannot clear this raw status, so it can be used to judge if or not system rebooting comes from watchdog reset. Write wdg_rst_clr can clear this raw status.</comment>
        </bits>
        <bits access="r" name="wdg_int_raw" pos="0" rst="1">
          <comment>Watchdog interrupt raw status. Watch dog reset cannot clear this raw status. Write wdg_int_clr can clear this raw status.</comment>
        </bits>
      </reg>
      <reg name="wdg_int_mask" protect="r">
        <bits access="r" name="wdg_int_mask" pos="0" rst="1">
          <comment>Watchdog interrupt masked status</comment>
        </bits>
      </reg>
      <reg name="wdg_cnt_low" protect="r">
        <bits access="r" name="wdg_cnt_low" pos="15:0" rst="14">
          <comment>wdg_cnt_low: Low 16 bit of watchdog timer counter value. wdg_cnt_high: High 16 bit of watchdog timer counter value. wdg_cnt_low and wdg_cnt_high  are used together. This read-only register indicates current counter value. Its not recommended to read this register in normal usage. Because the counter is in different clock domain with APB, software needs use double-reading method to read this value, like system timer.</comment>
        </bits>
      </reg>
      <reg name="wdg_cnt_high" protect="r">
        <bits access="r" name="wdg_cnt_high" pos="15:0" rst="14">
          <comment>See wdg_cnt_low description.</comment>
        </bits>
      </reg>
      <reg name="wdg_lock" protect="rw">
        <bits access="rw" name="wdg_lock" pos="15:0" rst="14">
          <comment>Watchdog lock control Write 16hE551 to this register to unlock watchdog. Write other value to this register to lock watchdog If reading this register, bit-0 is lock status, and other bits are reserved. If watchdog is locked, all control registers cannot be written by software.</comment>
        </bits>
      </reg>
      <reg name="wdg_cnt_rd_low" protect="r">
        <bits access="r" name="wdg_cnt_rd_low" pos="15:0" rst="14">
          <comment>wdg_cnt_rd_low: Low 16 bit of watchdog timer counter value for read. wdg_cnt_rd_high: High 16 bit of watchdog timer counter value for read. wdg_cnt_rd_low and wdg_cnt_rd_high  are used together. This read-only register indicates current counter value. Read once can get watchdog counter value. No need to double read this reg. Refer to timers TIMER0_CNT_RD or TIMER1_CNT_RD</comment>
        </bits>
      </reg>
      <reg name="wdg_cnt_rd_high" protect="r">
        <bits access="r" name="wdg_cnt_rd_high" pos="15:0" rst="14">
          <comment>Refer to  wdg_cnt_rd_low</comment>
        </bits>
      </reg>
      <reg name="wdg_irqvalue_low" protect="rw">
        <bits access="rw" name="wdg_irqvalue_low" pos="15:0" rst="14">
          <comment>wdg_ irqvalue_low: Low 16 bit of watchdog irqvalue. wdg_ irqvalue_high: High 16 bit of watchdog irqvalue. wdg_ irqvalue_low and wdg_ irqvalue_high  are used together. Its useful in interrupt mode and combined mode. When  wdg_cnt equal watchdog irqvalue, an interrupt is generated. Default value of watchdog irqvalue is 32h0003_0000, corresponds to 6 seconds, which means reset will occur after irq is 1 for 6 seconds.</comment>
        </bits>
      </reg>
      <reg name="wdg_irqvalue_high" protect="rw">
        <bits access="rw" name="wdg_irqvalue_high" pos="15:0" rst="14">
          <comment>wdg_ irqvalue_low: Low 16 bit of watchdog irqvalue. wdg_ irqvalue_high: High 16 bit of watchdog irqvalue. wdg_ irqvalue_low and wdg_ irqvalue_high  are used together, which means reset will occur after irq is 1 for 6 seconds. Its useful in interrupt mode and combined mode. When  wdg_cnt equal watchdog irqvalue, an interrupt is generated. Default value of watchdog irqvalue is 32h0003_0000, corresponds to 6 seconds.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_idle.xml">
    <module category="Bb_sysctrl" name="CP_IDLE">
      <reg name="idl_ctrl_sys1" protect="rw">
        <bits access="rw" name="idct_ctrl_sys1" pos="0" rst="0">
          <comment>Enable CP sleep
0: disable
1:  enable</comment>
        </bits>
      </reg>
      <reg name="idl_ctrl_sys2" protect="rw">
        <bits access="rw" name="idct_ctrl_sys2" pos="0" rst="0">
          <comment>Enable AP sleep(Auto cleared to be 0 when the system is awaked)
0: disable
1:  enable</comment>
        </bits>
      </reg>
      <reg name="idl_en" protect="rw">
        <bits access="rw" name="idl_ap_en" pos="1" rst="0">
          <comment>Enable AP sleep
0:  disable
1:  enable</comment>
        </bits>
        <bits access="rw" name="idl_cp_en" pos="0" rst="0">
          <comment>Enable CP sleep
0:  disable
1:  enable</comment>
        </bits>
      </reg>
      <reg name="idl_m_timer" protect="rw">
        <bits access="rw" name="idct_m_sys" pos="31:0" rst="0">
          <comment>System begin to wakeup when the current ref_32k counter reach this value, the difference between warp value and current ref_32k value larger than one gsm frame is best.</comment>
        </bits>
      </reg>
      <reg name="idl_wcn_en" protect="rw">
        <bits access="rw" name="wcn_res_val" pos="4" rst="1">
          <comment>Default value when the enable bit was disabled.</comment>
        </bits>
        <bits access="rw" name="wcn_idle_cg" pos="3" rst="1">
          <comment>Enable bit of wcn idle_cg
0: disable
1:  enable</comment>
        </bits>
        <bits access="rw" name="wcn_pd_pll" pos="2" rst="1">
          <comment>Enable bit of wcn pd_pll
0: disable
1:  enable</comment>
        </bits>
        <bits access="rw" name="wcn_pd_xtal" pos="1" rst="1">
          <comment>Enable bit of wcn pd_xtal
0: disable
1:  enable</comment>
        </bits>
        <bits access="rw" name="wcn_chip_pd" pos="0" rst="1">
          <comment>Enable bit of wcn chip_pd
0: disable
1:  enable</comment>
        </bits>
      </reg>
      <reg name="idl_ctrl_timer" protect="rw">
        <bits access="rw" name="idct_ctrl_timer" pos="0" rst="0">
          <comment>Enable Timer sleep(Auto clear to be 0 when timer is awaked)
0: disable
1:  enable</comment>
        </bits>
      </reg>
      <reg name="idl_m2_sys" protect="rw">
        <bits access="rw" name="m1_sys" pos="31:16" rst="6">
          <comment>Threshold register M1:
when the signal pow_on_ack is low, both gsm and lte timer are sleeped, and the difference between current ref_32k counter
and sleep wrap value is larger than this register, system sleep state machine can shift to SLP state.</comment>
        </bits>
        <bits access="rw" name="m2_sys" pos="15:0" rst="8">
          <comment>Threshold register M2:
when idct_sys1 and idct_sys2 are set to be1, the difference between current ref_32k counter and sleep wrap value is larger than this register, system sleep state machine can shift to SLP_PRE state.</comment>
        </bits>
      </reg>
      <reg name="idl_tc_start" protect="rw">
        <bits access="rw" name="tc_start_mod" pos="1:0" rst="0">
          <comment>Enable mode(TCU suspend and this bits are clear to be 0 when take over is started)
00: disbale or already release TCU.
01:  take over TCU immediately
10: take over at gsm frame interrupt.
11:  no effect.</comment>
        </bits>
      </reg>
      <reg name="idl_tc_end" protect="rw">
        <bits access="rw" name="tc_end_framc" pos="20:4" rst="1">
          <comment>restart TCU when gsm counter reach this register</comment>
        </bits>
        <bits access="rw" name="tc_end_mod" pos="1:0" rst="0">
          <comment>restart mode(this bits clear to be 0 when TCU restarts)
00: disable
01: restart TCU immediately
10: restart TCU when gsm frame interrupt occurred.
11:  restart TCU when gsm framc equal to TC_END_FRAMC.</comment>
        </bits>
      </reg>
      <reg name="idl_awk_timer" protect="rw">
        <bits access="rw" name="wake_timer" pos="0" rst="0">
          <comment>Timer wakeup enable(software accessed only)
0: disable
1:  enable</comment>
        </bits>
      </reg>
      <reg name="gsm_lp_pu_done" protect="rw">
        <bits access="rw" name="lp_pu_done" pos="0" rst="0">
          <comment>TCU restart enable(software accessed only)
Output to the port gsm_lp_pu_done directly, wakeup TCU in low power mode when writing 1 to this bit.</comment>
        </bits>
      </reg>
      <reg name="gsm_frame_inten" protect="rw">
        <bits access="rw" name="gsm_frame_irq_en" pos="0" rst="0">
          <comment>gsm_frame_irq enable
1: enable
0: disable</comment>
        </bits>
      </reg>
      <reg name="gsm_frame_int_sta" protect="rw">
        <bits access="rw" name="gsm_frame_int_sta" pos="0" rst="0">
          <comment>cleared by writing 1 to correspond bit</comment>
        </bits>
      </reg>
      <reg name="ltem1_frame_inten" protect="rw">
        <bits access="rw" name="ltem1_frame3_irq_en" pos="2" rst="0">
          <comment>ltem1_frame3_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="ltem1_frame2_irq_en" pos="1" rst="0">
          <comment>ltem1_frame2_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="ltem1_frame1_irq_en" pos="0" rst="0">
          <comment>ltem1_frame1_irq enable
1: enable
0: disable</comment>
        </bits>
      </reg>
      <reg name="ltem1_frame_int_sta" protect="rw">
        <bits access="rc" name="ltem1_frame_int_sta" pos="2:0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          cleared by writing 1 to correspond bit</comment>
        </bits>
      </reg>
      <reg name="ltem2_frame_inten" protect="rw">
        <bits access="rw" name="ltem2_frame3_irq_en" pos="2" rst="0">
          <comment>ltem2_frame3_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="ltem2_frame2_irq_en" pos="1" rst="0">
          <comment>ltem2_frame2_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="ltem2_frame1_irq_en" pos="0" rst="0">
          <comment>ltem2_frame1_irq enable
1: enable
0: disable</comment>
        </bits>
      </reg>
      <reg name="ltem2_frame_int_sta" protect="rw">
        <bits access="rc" name="ltem2_frame_int_sta" pos="2:0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          cleared by writing 1 to correspond bit</comment>
        </bits>
      </reg>
      <reg name="idl_sta" protect="r">
        <bits access="r" name="idle_nb_timer_stat" pos="5" rst="0">
          <comment>NB timer state
0: running at 61.44M
1:  running at 32K</comment>
        </bits>
        <bits access="r" name="h_stat" pos="4" rst="0">
          <comment>H circuit state
0:  not work
1:  at wok</comment>
        </bits>
        <bits access="r" name="idle_ltem2_timer_stat" pos="3" rst="0">
          <comment>ltem2 timer state
0: running at 122.88M
1:  running at 32K</comment>
        </bits>
        <bits access="r" name="idle_ltem1_timer_stat" pos="2" rst="0">
          <comment>ltem1 timer state
0: running at 122.88M
1:  running at 32K</comment>
        </bits>
        <bits access="r" name="idle_gsm_timer_stat" pos="1" rst="0">
          <comment>GSM timer state
0: running at 26M
1:  running at 32K</comment>
        </bits>
        <bits access="r" name="idle_sys_stat" pos="0" rst="0">
          <comment>SYS state
0:  normal working
1:  low power mode</comment>
        </bits>
      </reg>
      <reg name="idl_h_ctrl" protect="rw">
        <bits access="rw" name="h_run_time" pos="6:3" rst="15">
          <comment>Runtime of H circuit, the length is 2^h_run_time(number of 32k clocks)</comment>
        </bits>
        <bits access="rw" name="h_auto_en" pos="2" rst="0">
          <comment>Automatic computing mode enable(loop computing until disabled)
0: disable
1:  enable</comment>
        </bits>
        <bits access="rw" name="h_ctrl_en" pos="1" rst="0">
          <comment>Invocation pattern(compute only one time, automatic clear to be 0 when finished.)
0: disable
1:  enable</comment>
        </bits>
      </reg>
      <reg name="idl_h_val" protect="rw">
        <bits access="rw" name="h_value" pos="26:0" rst="0">
          <comment>The length of sys clock in  2^h_run_time 32k cycles</comment>
        </bits>
      </reg>
      <reg name="idl_h_gsm" protect="rw">
        <bits access="rw" name="h_value" pos="26:0" rst="26623680">
          <comment>The cycles number of 26M in 2^h_run_time 32k cycles</comment>
        </bits>
      </reg>
      <reg name="idl_h_ltem" protect="rw">
        <bits access="rw" name="h_value" pos="26:0" rst="125829442">
          <comment>The cycles number of 122.88M in of 2^h_run_time 32k cycles</comment>
        </bits>
      </reg>
      <reg name="idl_awk_en" protect="rw">
        <bits access="rw" name="nb_lp_pu_reach_en" pos="12" rst="0">
          <comment>signal nb_lp_pu_reach wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="gsm_lp_pu_reach_en" pos="11" rst="0">
          <comment>signal gsm_lp_pu_reach wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="awk_self_en" pos="10" rst="0">
          <comment>sofware wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="awk_osw2_en" pos="9" rst="0">
          <comment>OSW2 wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="awk_osw1_en" pos="8" rst="0">
          <comment>OSW1 wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="awk7_en" pos="7" rst="0">
          <comment>wcn_osc_en wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="awk6_en" pos="6" rst="0">
          <comment>wcn2sys wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="awk5_en" pos="5" rst="0">
          <comment>pad_uart1_rxd wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="awk4_en" pos="4" rst="0">
          <comment>Uart1_irq wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="awk3_en" pos="3" rst="0">
          <comment>Gpio1_irq wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="awk2_en" pos="2" rst="0">
          <comment>Keyboard wakeup enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="awk1_en" pos="1" rst="0">
          <comment>Vad_int wakeup enable
0: disable
1:  enable</comment>
        </bits>
        <bits access="rw" name="awk0_en" pos="0" rst="0">
          <comment>Pad_gpio6 wakeup enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="idl_awk_st" protect="rw">
        <bits access="r" name="pow_dfe_sta" pos="26" rst="1">
          <comment>pow_dfe_ack state
0: pow_dfe_ack is 0 when system exit IDLE
1:  pow_dfe_ack is 1 when system exit IDLE</comment>
        </bits>
        <bits access="rc" name="thr_sta" pos="25" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Threshold M1 state
1: pow_ack not meet threshold M1 or pow_ack not feedback in sleep period
0: meet threshold M1</comment>
        </bits>
        <bits access="rc" name="pow_sta" pos="24" rst="0">
          <comment>bit type is changed from rw1c to rc.
          pow_ack state
0: pow_ack is 0 when system exit IDLE
1:  pow_ack is 1 when system exit IDLE</comment>
        </bits>
        <bits access="rc" name="idle_stat" pos="20" rst="0">
          <comment>bit type is changed from rw1c to rc.
          system exit idle state
0: sys not enter idle
1: sys enter idle state</comment>
        </bits>
        <bits access="rc" name="awk_up_stat" pos="16" rst="0">
          <comment>bit type is changed from rw1c to rc.
          IDLE sleep wakeup state
0: awaked before the sleep warp time
1: awaked at the sleep warp time</comment>
        </bits>
        <bits access="rc" name="nb_lp_pu_reach_stat" pos="12" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Signal nb_lp_pu_reach wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="gsm_lp_pu_reach_stat" pos="11" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Signal gsm_lp_pu_reach wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="awk_self_stat" pos="10" rst="0">
          <comment>bit type is changed from rw1c to rc.
          software wakeup state
0: software wakeupup signal not generated
1: software wakeupup system.</comment>
        </bits>
        <bits access="rc" name="awk_osw2_stat" pos="9" rst="0">
          <comment>bit type is changed from rw1c to rc.
          OSW2 wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="awk_osw1_stat" pos="8" rst="0">
          <comment>bit type is changed from rw1c to rc.
          OSW1 wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="awk7_awk_stat" pos="7" rst="0">
          <comment>bit type is changed from rw1c to rc.
          AWK7 wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="awk6_awk_stat" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          AWK6 wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="awk5_awk_stat" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          AWK5 wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="awk4_awk_stat" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          AWK4 wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="awk3_awk_stat" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          AWk3 wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="awk2_awk_stat" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          AWk2 wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="awk1_awk_stat" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          AWK1 wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
        <bits access="rc" name="awk0_awk_stat" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          AWK0 wakeup state
0: this signal not generated
1: this signal generated</comment>
        </bits>
      </reg>
      <reg name="idl_awk_self" protect="rw">
        <bits access="rw" name="wake_self" pos="0" rst="0">
          <comment>0: not effect
1:  wakeup system
(accessed by software only, this bit shold clear bu software when system is awaked.)</comment>
        </bits>
      </reg>
      <reg name="idl_osw1_en" protect="rw">
        <bits access="rw" name="osw1_en" pos="31" rst="0">
          <comment>1:  enable
0: disable</comment>
        </bits>
        <bits access="rw" name="osw1_time" pos="30:0" rst="2147483647">
          <comment>osw1 wrap value</comment>
        </bits>
      </reg>
      <reg name="idl_osw1_cont" protect="r">
        <bits access="r" name="osw1_count" pos="31:0" rst="4294967295">
          <comment>OSW1 Timer is based on a slow counter, which start counting from the wrap value and decreasing 1 at each 2 cycles(counter frequency is 16K), the counter suspend when disabled.</comment>
        </bits>
      </reg>
      <reg name="idl_fn_gsm" protect="r">
        <bits access="r" name="idfn_gsm" pos="31:0" rst="0">
          <comment>Number of frames gsm sleeped.</comment>
        </bits>
      </reg>
      <reg name="idl_fn_ltem1" protect="r">
        <bits access="r" name="idfn_rad_ltem" pos="31:4" rst="0">
          <comment>Number of frames ltem1 sleeped.</comment>
        </bits>
        <bits access="r" name="idfn_sub_ltem" pos="3:0" rst="0">
          <comment>Number of sub-frames ltem1 sleeped.</comment>
        </bits>
      </reg>
      <reg name="idl_fn_ltem2" protect="r">
        <bits access="r" name="idfn_rad_ltem" pos="31:4" rst="0">
          <comment>Number of frames ltem2 sleeped</comment>
        </bits>
        <bits access="r" name="idfn_sub_ltem" pos="3:0" rst="0">
          <comment>Number of sub-frames ltem2 sleeped.</comment>
        </bits>
      </reg>
      <reg name="idl_ltem_rfl" protect="rw">
        <bits access="rw" name="ltem_idle_radioframe_parameter" pos="20:0" rst="1228800">
          <comment>LTE sleep frame length, suggest keep the default value.</comment>
        </bits>
      </reg>
      <reg name="idl_ltem_sfl" protect="rw">
        <bits access="rw" name="ltem_idle_frame_parameter" pos="16:0" rst="122880">
          <comment>LTE sleep sub-frame length, suggest keep
the default value.</comment>
        </bits>
      </reg>
      <reg name="idl_sig_en" protect="rw">
        <bits access="rw" name="idle_cg_en" pos="3" rst="1">
          <comment>Idle_cg_en enable
1: enable.
0: disable.</comment>
        </bits>
        <bits access="rw" name="pd_pll_en" pos="2" rst="1">
          <comment>Pd_pll_en enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="pd_xtal_en" pos="1" rst="1">
          <comment>pd_xtal_en enable
1: enable.
0: disable.</comment>
        </bits>
        <bits access="rw" name="chip_pd_en" pos="0" rst="1">
          <comment>chip_pd_en enable
1:  enable.
0: disable.</comment>
        </bits>
      </reg>
      <reg name="idl_sig_timer" protect="rw">
        <bits access="rw" name="t4" pos="31:24" rst="1">
          <comment>The time from enable clock to obtain clock</comment>
        </bits>
        <bits access="rw" name="t3" pos="23:16" rst="10">
          <comment>The time of PLL from power saving state to output normal clock.</comment>
        </bits>
        <bits access="rw" name="t2" pos="15:8" rst="160">
          <comment>The time of OSC circuit from power saving
state to normal state.</comment>
        </bits>
        <bits access="rw" name="t1" pos="7:0" rst="1">
          <comment>The time of PMIC boost stabilization.</comment>
        </bits>
      </reg>
      <reg name="idl_32k_ref" protect="r">
        <bits access="r" name="rek_ref" pos="31:0" rst="0">
          <comment>Current 32K counter value</comment>
        </bits>
      </reg>
      <reg name="cp_inten" protect="rw">
        <bits access="rw" name="target_irq" pos="13" rst="0">
          <comment>target_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="nb_pu_reach_irq" pos="12" rst="0">
          <comment>nb_pu_reach_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="nb_tc_end_irq" pos="11" rst="0">
          <comment>nb_tc_end_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="nb_tc_start_irq" pos="10" rst="0">
          <comment>nb_tc_start_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="sys_wak_irq" pos="9" rst="0">
          <comment>sys_awk _irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="timer_awk_irq" pos="8" rst="0">
          <comment>Timer_awk_irq_enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="gsm_pu_reach_irq" pos="7" rst="0">
          <comment>gsm_pu_reach_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="gsm_tc_end_irq" pos="6" rst="0">
          <comment>gsm_tc_end_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="gsm_tc_start_irq" pos="5" rst="0">
          <comment>gsm_tc_start_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="osw1_irq" pos="4" rst="0">
          <comment>osw1_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="tstamp_irq" pos="3" rst="0">
          <comment>tstamp_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="idle_frame_irq" pos="2" rst="0">
          <comment>idle_frame_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="idle_h_irq" pos="1" rst="1">
          <comment>idle_h_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="layout_irq" pos="0" rst="0">
          <comment>layout_irq enable
1: enable
0: disable</comment>
        </bits>
      </reg>
      <reg name="cp_inten_set" protect="rw">
        <bits access="rs" name="int_en_set" pos="13:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set  cp interrupt enable register when writing 1 to correspond bits.</comment>
        </bits>
      </reg>
      <reg name="cp_inten_clr" protect="rw">
        <bits access="rc" name="int_en_clr" pos="13:0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          clear  cp interrupt enable register when writing 1 to correspond bits.</comment>
        </bits>
      </reg>
      <reg name="cp_int_sta" protect="rw">
        <bits access="rc" name="cp_int_sta" pos="13:0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          clear interrupt state register when writing 1 to correspond bits.</comment>
        </bits>
      </reg>
      <reg name="ap_inten" protect="rw">
        <bits access="rw" name="target_irq" pos="5" rst="0">
          <comment>target_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="nb_pu_reach_irq" pos="4" rst="0">
          <comment>nb_pu_reach_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="sys_wak_irq" pos="3" rst="0">
          <comment>sys_awk _irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="timer_awk_irq" pos="2" rst="0">
          <comment>Timer_awk_irq_enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="gsm_pu_reach_irq" pos="1" rst="0">
          <comment>gsm_pu_reach_irq enable
1: enable
0: disable</comment>
        </bits>
        <bits access="rw" name="osw2_irq" pos="0" rst="0">
          <comment>osw2_irq enable
1: enable
0: disable</comment>
        </bits>
      </reg>
      <reg name="ap_inten_set" protect="rw">
        <bits access="rs" name="int_en_set" pos="5:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set  ap interrupt enable register when writing 1 to correspond bits.</comment>
        </bits>
      </reg>
      <reg name="ap_inten_clr" protect="rw">
        <bits access="rc" name="int_en_clr" pos="5:0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          clear  ap interrupt enable register when writing 1 to correspond bits.</comment>
        </bits>
      </reg>
      <reg name="ap_int_sta" protect="rw">
        <bits access="rc" name="ap_int_sta" pos="5:0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          clear ap interrupt state register when writing 1 to correspond bits.</comment>
        </bits>
      </reg>
      <reg name="ltem1_cfsr_hfn" protect="rw">
        <bits access="rw" name="ltem_cfsr_hfn" pos="21:0" rst="0">
          <comment>Ltem1 high-level frame number value</comment>
        </bits>
      </reg>
      <reg name="ltem1_cfsr_fn" protect="rw">
        <bits access="rw" name="ltem_cfsr_rad" pos="13:4" rst="0">
          <comment>LTE-M1 frame number</comment>
        </bits>
        <bits access="rw" name="ltem_cfsr_sub" pos="3:0" rst="0">
          <comment>LTE-M1 sub-frame number</comment>
        </bits>
      </reg>
      <reg name="ltem1_cfsrs" protect="rw">
        <bits access="rw" name="active_time" pos="25" rst="0">
          <comment>frame adjust time
0: adjust at next frame interrupt
1: adjust frame immetiately</comment>
        </bits>
        <bits access="rw" name="adjust_direct" pos="24" rst="0">
          <comment>frame adjust direction
0: postive
1: negative</comment>
        </bits>
        <bits access="rw" name="ltem_cfsrs" pos="23:0" rst="0">
          <comment>LTE-M1 frame offest value
(Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.)</comment>
        </bits>
      </reg>
      <reg name="ltem1_cfsr_rdh" protect="r">
        <bits access="r" name="ltem_cfsr_rdh" pos="21:0" rst="0">
          <comment>LTE-M1 high-level frame value</comment>
        </bits>
      </reg>
      <reg name="ltem1_cfsr_rdl" protect="r">
        <bits access="r" name="ltem_cfsr_rdl_rad" pos="13:4" rst="0">
          <comment>LTE-M1 radio frame value</comment>
        </bits>
        <bits access="r" name="ltem_cfsr_rdl_sub" pos="3:0" rst="0">
          <comment>LTE-M1 sub-frame value</comment>
        </bits>
      </reg>
      <reg name="ltem1_framc" protect="r">
        <bits access="r" name="lframc" pos="15:0" rst="1">
          <comment>LTE-M1 counter value</comment>
        </bits>
      </reg>
      <reg name="ltem1_framl" protect="rw">
        <bits access="rw" name="lframl" pos="15:0" rst="30720">
          <comment>LTE-M1 frame length</comment>
        </bits>
      </reg>
      <reg name="ltem1_framls" protect="rw">
        <bits access="rw" name="active_time" pos="16" rst="0">
          <comment>adjust time
0: adjust immetiately
1:  adjust at next ltem frame interrupt</comment>
        </bits>
        <bits access="rw" name="lframls" pos="15:0" rst="0">
          <comment>LTE-M1 adjuste frame length.
current Ltem frame length load the register when write happens,then return the LFRAML at the time of lte frame interrupt arrivals.</comment>
        </bits>
      </reg>
      <reg name="ltem1_cfsr_tph" protect="rw">
        <bits access="rw" name="ltem_cfsr_tph" pos="21:0" rst="0">
          <comment>LTE-M1 high-level frame value time stamp register</comment>
        </bits>
      </reg>
      <reg name="ltem1_cfsr_tpl" protect="rw">
        <bits access="rw" name="ltem_cfsr_tpl" pos="13:0" rst="0">
          <comment>LTE-M1 frame stamp value</comment>
        </bits>
      </reg>
      <reg name="ltem1_framc_tp" protect="rw">
        <bits access="rw" name="ltem_framc_tp" pos="15:0" rst="1">
          <comment>LTE-M1 stamp counter</comment>
        </bits>
      </reg>
      <reg name="ltem2_cfsr_hfn" protect="rw">
        <bits access="rw" name="ltem_cfsr_hfn" pos="21:0" rst="0">
          <comment>LTE-M2 high-level frame value</comment>
        </bits>
      </reg>
      <reg name="ltem2_cfsr_fn" protect="rw">
        <bits access="rw" name="ltem_cfsr_rad" pos="13:4" rst="0">
          <comment>LTE-M2 radio frame value</comment>
        </bits>
        <bits access="rw" name="ltem_cfsr_sub" pos="3:0" rst="0">
          <comment>LTE-M2 sub-frame value</comment>
        </bits>
      </reg>
      <reg name="ltem2_cfsrs" protect="rw">
        <bits access="rw" name="active_time" pos="25" rst="0">
          <comment>adjust time.
0: adjust at next frame interrupt
1: adjust frame immetiately</comment>
        </bits>
        <bits access="rw" name="adjust_direct" pos="24" rst="0">
          <comment>adjust direction
0: postive
1: negative</comment>
        </bits>
        <bits access="rw" name="ltem_cfsrs" pos="23:0" rst="0">
          <comment>Frame offest value(Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value at the time of frame interrupt genereted. otherwise write b-1 into this register then current frame minus this value at the time of frame interrupt generated.)</comment>
        </bits>
      </reg>
      <reg name="ltem2_cfsr_rdh" protect="r">
        <bits access="r" name="ltem_cfsr_rdh" pos="21:0" rst="0">
          <comment>LTE-M2 super read frame value</comment>
        </bits>
      </reg>
      <reg name="ltem2_cfsr_rdl" protect="r">
        <bits access="r" name="ltem_cfsr_rdl_rad" pos="13:4" rst="0">
          <comment>LTE-M2 radio frame read value</comment>
        </bits>
        <bits access="r" name="ltem_cfsr_rdl_sub" pos="3:0" rst="0">
          <comment>LTE-M2 sub-frame read value</comment>
        </bits>
      </reg>
      <reg name="ltem2_framc" protect="r">
        <bits access="r" name="lframc" pos="15:0" rst="1">
          <comment>LTE-M counter</comment>
        </bits>
      </reg>
      <reg name="ltem2_framl" protect="rw">
        <bits access="rw" name="lframl" pos="15:0" rst="30720">
          <comment>LTE-M2 frame length value</comment>
        </bits>
      </reg>
      <reg name="ltem2_framls" protect="rw">
        <bits access="rw" name="active_time" pos="16" rst="0">
          <comment>adjust time
0: adjust immetiately
1:  adjust at next ltem frame interrupt</comment>
        </bits>
        <bits access="rw" name="lframls" pos="15:0" rst="0">
          <comment>LTE-M2 adjuste frame length.
current Ltem frame length load the register when write happens,then backed the LFRAML at the time of lte frame interrupt occurred.</comment>
        </bits>
      </reg>
      <reg name="ltem2_cfsr_tph" protect="rw">
        <bits access="rw" name="ltem_cfsr_tph" pos="21:0" rst="0">
          <comment>LTE-M2 high-level frame time stamp register</comment>
        </bits>
      </reg>
      <reg name="ltem2_cfsr_tpl" protect="rw">
        <bits access="rw" name="ltem_cfsr_tpl" pos="13:0" rst="0">
          <comment>LTE-M2 frame stamp value</comment>
        </bits>
      </reg>
      <reg name="ltem2_framc_tp" protect="rw">
        <bits access="rw" name="ltem_framc_tp" pos="15:0" rst="1">
          <comment>LTE-M2 stamp counter</comment>
        </bits>
      </reg>
      <reg name="gsm_cfsr" protect="rw">
        <bits access="rw" name="gsm_cfsr_gsm_cfsr" pos="23:0" rst="0">
          <comment>GSM frame value</comment>
        </bits>
      </reg>
      <reg name="gsm_cfsrs" protect="rw">
        <bits access="rw" name="adjust_direct" pos="24" rst="0">
          <comment>adjust direction
0: postive
1:  negative</comment>
        </bits>
        <bits access="rw" name="gsm_cfsrs_gsm_cfsrs" pos="23:0" rst="0">
          <comment>frame offest value
(Adjust frame offset B. there are two case: if adjust direction is 0, write b+1 into this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.)</comment>
        </bits>
      </reg>
      <reg name="gsm_cfsro" protect="rw">
        <bits access="rw" name="gsm_cfsr_overflow" pos="23:0" rst="2715648">
          <comment>GSM frame overflow value</comment>
        </bits>
      </reg>
      <reg name="ltem1_fhl" protect="r">
        <bits access="r" name="ltem_fhl" pos="21:0" rst="0">
          <comment>LTE-M high-level frame locked value,
lock the register LTEM_CFSR_HFN.</comment>
        </bits>
      </reg>
      <reg name="ltem1_fll" protect="r">
        <bits access="r" name="ltem_fll" pos="13:0" rst="0">
          <comment>LTE-M frame locked value, lock the register
LTEM_CFSR_FN</comment>
        </bits>
      </reg>
      <reg name="ltem1_fcl" protect="r">
        <bits access="r" name="ltem_fcl" pos="15:0" rst="1">
          <comment>LTE-M couner locked value</comment>
        </bits>
      </reg>
      <reg name="ltem2_fhl" protect="r">
        <bits access="r" name="ltem_fhl" pos="21:0" rst="0">
          <comment>LTE-M high-level frame locked value,
lock the register LTEM_CFSR_HFN.</comment>
        </bits>
      </reg>
      <reg name="ltem2_fll" protect="r">
        <bits access="r" name="ltem_fll" pos="13:0" rst="0">
          <comment>LTE-M frame locked value, lock the register
LTEM_CFSR_FN</comment>
        </bits>
      </reg>
      <reg name="ltem2_fcl" protect="r">
        <bits access="r" name="ltem_fcl" pos="15:0" rst="1">
          <comment>LTE-M counter locked value</comment>
        </bits>
      </reg>
      <reg name="gsm_fl" protect="r">
        <bits access="r" name="fl" pos="23:0" rst="0">
          <comment>GSM frame locked value</comment>
        </bits>
      </reg>
      <reg name="gsm_fcl" protect="r">
        <bits access="r" name="gsm_fcl_gsm_fcl" pos="16:0" rst="1">
          <comment>GSM counter locked value</comment>
        </bits>
      </reg>
      <reg name="tpctrl" protect="rw">
        <bits access="rw" name="mod_sel" pos="10:8" rst="0">
          <comment>lock signal
000: ltem1 frame interrupt.
001: ltem2 frame interrupt.
010: gsm frame interrupt.
011: negative of 32k clock.
100: nb frame interrput.
others: gsm frame interrupt.</comment>
        </bits>
        <bits access="rw" name="inner_confg" pos="5:4" rst="0">
          <comment>lock way
00: disable lock
01: bit 0 control the time stamp, bit 0 auto clear to be 0 after time stamp finsihed.
10: time stamp when lock signal comes after that bit 5 and 4 clear to be 0.
11: time stamp loop</comment>
        </bits>
        <bits access="rw" name="inner_ctrl" pos="0" rst="0">
          <comment>1: time stamp immediately.
0: not effect</comment>
        </bits>
      </reg>
      <reg name="layoutt" protect="rw">
        <bits access="rw" name="layoutt" pos="31:0" rst="0">
          <comment>The initial value of task planning, the register value decrement after a certain number of TS when started task planning, you can get the remaining time by reading this register.</comment>
        </bits>
      </reg>
      <reg name="layoutctrl" protect="rw">
        <bits access="rw" name="chip_count" pos="22:8" rst="0">
          <comment>Layoutt register descending unit.
15h0000: 1
15h0001:  2
15h0002: 3
15h7fff: 32768</comment>
        </bits>
        <bits access="rw" name="timer_select" pos="1" rst="0">
          <comment>Layout count time selection
0: ltem1 timer
1: ltem2 timer</comment>
        </bits>
        <bits access="rw" name="enable" pos="0" rst="0">
          <comment>task planning
1:  start task planing
0: end timing
(The control bit is clear automatically after the timer is finished, and the software can be clear to bestop counting.)</comment>
        </bits>
      </reg>
      <reg name="ltem1_fint_dly1" protect="rw">
        <bits access="rw" name="delay_time" pos="15:0" rst="1">
          <comment>LTE-M1 frame interrupt delay, take ltem1_framc as a reference.</comment>
        </bits>
      </reg>
      <reg name="ltem1_fint_dly2" protect="rw">
        <bits access="rw" name="delay_time" pos="15:0" rst="1">
          <comment>LTE-M1 frame interrupt delay, take ltem1_framc as a reference.</comment>
        </bits>
      </reg>
      <reg name="ltem2_fint_dly1" protect="rw">
        <bits access="rw" name="delay_time" pos="15:0" rst="1">
          <comment>LTE-M2 frame interrupt delay, take ltem2_framc as a reference.</comment>
        </bits>
      </reg>
      <reg name="ltem2_fint_dly2" protect="rw">
        <bits access="rw" name="delay_time" pos="15:0" rst="1">
          <comment>LTE-M2 frame interrupt delay, take ltem2_framc as a reference.</comment>
        </bits>
      </reg>
      <reg name="fint_en" protect="rw">
        <bits access="rw" name="lte_m2_fint_enable" pos="21:12" rst="1023">
          <comment>Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled.</comment>
        </bits>
        <bits access="rw" name="lte_m1_fint_enable" pos="9:0" rst="1023">
          <comment>Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled.</comment>
        </bits>
      </reg>
      <reg name="timer_en" protect="rw">
        <bits access="rw" name="nb_timer_enable" pos="4" rst="0">
          <comment>NB timer enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="ltem_timer_enable" pos="3" rst="0">
          <comment>LTE-M timer enable
0: disable
1: enable
(note: this timer is the reference lte timer.)</comment>
        </bits>
        <bits access="rw" name="gsm_timer_enable" pos="2" rst="0">
          <comment>GSM timer enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="lte_m2_timer_enable" pos="1" rst="0">
          <comment>LTE-M2 timer enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="lte_m1_timer_enable" pos="0" rst="1">
          <comment>LTE-M1 timer enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="idle_frame_sta" protect="rw">
        <bits access="rc" name="nb_frame_state" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          NB frame interrupt state
0: No interrupt occurred
1: interrupt occurred</comment>
        </bits>
        <bits access="rc" name="lte_m_frame_state" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          reference lte frame interrupt state
0: No interrupt occurred
1: interrupt occurred</comment>
        </bits>
        <bits access="rc" name="gsm_frame_state" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          GSM frame interrupt state
0: No interrupt occurred
1: interrupt occurred</comment>
        </bits>
        <bits access="rc" name="lte_m2_frame_state" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          LTE-M2 frame interrupt state
0: No interrupt occurred
1: interrupt occurred</comment>
        </bits>
        <bits access="rc" name="lte_m1_frame_state" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          LTE-M1 frame interrupt state
0: No interrupt occurred
1: interrupt occurred</comment>
        </bits>
      </reg>
      <reg name="idle_frame_ltem1" protect="rw">
        <bits access="rw" name="frame_conf" pos="24" rst="0">
          <comment>enable(this bit cleared automatically after the frame interrupt generated)
0: disable
1:  enable</comment>
        </bits>
        <bits access="rw" name="frame_cfsr" pos="21:0" rst="0">
          <comment>interrupt frame number
interrupt occurred when current frame reach this register.</comment>
        </bits>
      </reg>
      <reg name="idle_frame_ltem2" protect="rw">
        <bits access="rw" name="frame_conf" pos="24" rst="0">
          <comment>enable(this bit is cleared automatically after the frame interrupt generated)
0: disable
1:  enable</comment>
        </bits>
        <bits access="rw" name="frame_cfsr" pos="21:0" rst="0">
          <comment>interrupt occurred when current frame reach this register.</comment>
        </bits>
      </reg>
      <reg name="idle_frame_gsm" protect="rw">
        <bits access="rw" name="frame_conf" pos="24" rst="0">
          <comment>enable(this bit cleared automatically after the frame interrupt generated)
0: disable
1:  enable</comment>
        </bits>
        <bits access="rw" name="frame_cfsr" pos="23:0" rst="0">
          <comment>interrupt occurred when current frame reach this register and counter equal to IDLE_FRAMC_GSM</comment>
        </bits>
      </reg>
      <reg name="idle_frame_lte" protect="rw">
        <bits access="rw" name="frame_ref_cfsr" pos="31:0" rst="0">
          <comment>interrupt occurred when current frame reach this register.</comment>
        </bits>
      </reg>
      <reg name="idle_frame_lte_conf" protect="rw">
        <bits access="r" name="resrved" pos="31:1" rst="0">
      </bits>
        <bits access="rw" name="frame_ref_lte_conf" pos="0" rst="0">
          <comment>enable(this bit cleared automatically after the frame interrupt generated)
0: disable
1:  enable</comment>
        </bits>
      </reg>
      <reg name="ltem_ref_fn" protect="rw">
        <bits access="rw" name="ltem_ref_fn_ltem_ref_fn" pos="31:0" rst="0">
          <comment>reference lte frame</comment>
        </bits>
      </reg>
      <reg name="ltem_ref_fnl" protect="r">
        <bits access="r" name="ref_ltem_fnl" pos="31:0" rst="0">
          <comment>reference lte frame locked value</comment>
        </bits>
      </reg>
      <reg name="ltem_ref_fcl" protect="r">
        <bits access="r" name="ref_ltem_fcl" pos="14:0" rst="1">
          <comment>reference lte counter locked value</comment>
        </bits>
      </reg>
      <reg name="ref_32k_fnl" protect="r">
        <bits access="r" name="ref_32k_fnl_ref_32k_fnl" pos="31:0" rst="0">
          <comment>reference 32k counter locked value</comment>
        </bits>
      </reg>
      <reg name="ltem_ref_fc" protect="r">
        <bits access="r" name="ltem_ref_fc_ltem_ref_fc" pos="14:0" rst="1">
          <comment>reference lte counter</comment>
        </bits>
      </reg>
      <reg name="gsm_framl" protect="rw">
        <bits access="rw" name="gsm_framl" pos="16:0" rst="120000">
          <comment>GSM frame length value</comment>
        </bits>
      </reg>
      <reg name="idl_osw2_en" protect="rw">
        <bits access="rw" name="osw2_en" pos="31" rst="0">
          <comment>1: enable OSW2 timer
0: disable</comment>
        </bits>
        <bits access="rw" name="osw2_time" pos="30:0" rst="2147483647">
          <comment>OSW2 Timing start value</comment>
        </bits>
      </reg>
      <reg name="idl_osw2_cont" protect="r">
        <bits access="r" name="osw2_count" pos="31:0" rst="4294967295">
          <comment>OSW2 Timer is based on a slow counter, which start counting from the start value and decreasing 1 at each 2 cycles(counter frequency is 16K)</comment>
        </bits>
      </reg>
      <reg name="idle_framc_gsm" protect="rw">
        <bits access="rw" name="framc_cfsr" pos="16:0" rst="1">
          <comment>IDLE GSM frame interrupt generated when GSM frame counter reach GSM_FRAME_GSM and GSM counter equal to this register.</comment>
        </bits>
      </reg>
      <reg name="ltem1_fint_dly3" protect="rw">
        <bits access="rw" name="delay_time" pos="15:0" rst="1">
          <comment>LTE-M1 frame interrupt delay,
take ltem1_framc as a reference.</comment>
        </bits>
      </reg>
      <reg name="ltem2_fint_dly3" protect="rw">
        <bits access="rw" name="delay_time" pos="15:0" rst="1">
          <comment>LTE-M2 frame interrupt delay, take ltem2_framc as a reference.</comment>
        </bits>
      </reg>
      <reg name="idle_time_sel" protect="rw">
        <bits access="rw" name="time_sel" pos="0" rst="0">
          <comment>1: select pd_xtal, 0: select chip_pd</comment>
        </bits>
      </reg>
      <reg name="idle_time" protect="r">
        <bits access="r" name="idl_time" pos="31:0" rst="0">
          <comment>the length of pd_xtal(or chip_pd) set to be 1.</comment>
        </bits>
      </reg>
      <reg name="idl_h_gsm_lp" protect="rw">
        <bits access="rw" name="h_value" pos="26:0" rst="26623680">
          <comment>The cycles number of 26M in 2^h_run_time 32k cycles</comment>
        </bits>
      </reg>
      <reg name="idl_h_ltem_lp" protect="rw">
        <bits access="rw" name="h_value" pos="26:0" rst="125829442">
          <comment>The cycles number of 122.88M in of 2^h_run_time 32k cycles</comment>
        </bits>
      </reg>
      <reg name="idl_tc_start_nb" protect="rw">
        <bits access="rw" name="tc_start_mod" pos="1:0" rst="0">
          <comment>Enable mode(NB TCU suspend and this bits are cleared by hardware when take over started)
00: disbale or already release TCU.
01:  take over TCU immediately
10: take over at gsm frame interrupt.
11:  no effect.</comment>
        </bits>
      </reg>
      <reg name="idl_tc_end_nb" protect="rw">
        <bits access="rw" name="tc_end_framc" pos="20:4" rst="1">
          <comment>restart TCU when gsm counter reach this register</comment>
        </bits>
        <bits access="rw" name="tc_end_mod" pos="1:0" rst="0">
          <comment>restart mode(this bits cleared when TCU restarts)
00: disable
01: restart TCU immediately
10: restart TCU when gsm frame interrupt occurred.
11:  restart TCU when gsm framc equal to TC_END_FRAMC.</comment>
        </bits>
      </reg>
      <reg name="nb_lp_pu_done" protect="rw">
        <bits access="rw" name="lp_pu_done" pos="0" rst="0">
          <comment>TCU restart enable(accessed by software only.)
Output to the port nb_lp_pu_done directly, wakeup TCU in low power mode when writing 1 to this bit.</comment>
        </bits>
      </reg>
      <reg name="idl_h_nb" protect="rw">
        <bits access="rw" name="h_value" pos="26:0" rst="62914721">
          <comment>The cycles number of 61.44M in the length of 2^h_run_time 32k cycles</comment>
        </bits>
      </reg>
      <reg name="idl_h_nb_lp" protect="rw">
        <bits access="rw" name="h_value" pos="26:0" rst="62914721">
          <comment>The cycles number of 61.44M in the length of 2^h_run_time 32k cycles</comment>
        </bits>
      </reg>
      <reg name="idl_fn_nb" protect="r">
        <bits access="r" name="idfn_nb" pos="31:0" rst="0">
          <comment>Number of frames nb timer sleeped.</comment>
        </bits>
      </reg>
      <reg name="nb_frame_inten" protect="rw">
        <bits access="rw" name="nb_frame_irq_en" pos="0" rst="0">
          <comment>nb_frame_irq enable
1: enable
0: disable</comment>
        </bits>
      </reg>
      <reg name="nb_frame_int_sta" protect="rw">
        <bits access="rw" name="gsm_frame_int_sta" pos="0" rst="0">
          <comment>cleared by writing 1 to correspond bit</comment>
        </bits>
      </reg>
      <reg name="nb_cfsr" protect="rw">
        <bits access="rw" name="gsm_cfsr" pos="23:0" rst="0">
          <comment>NB frame value</comment>
        </bits>
      </reg>
      <reg name="nb_framl" protect="rw">
        <bits access="rw" name="nb_framl" pos="16:0" rst="61440">
          <comment>NB frame length value</comment>
        </bits>
      </reg>
      <reg name="nb_cfsrs" protect="rw">
        <bits access="rw" name="adjust_direct" pos="24" rst="0">
          <comment>adjust direction
0: postive
1:  negative</comment>
        </bits>
        <bits access="rw" name="nb_cfsrs_nb_cfsrs" pos="23:0" rst="0">
          <comment>frame offest value
(Adjust frame offset B. there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b- 1 to this register then current frame minus this value when frame interrupt occurred.)</comment>
        </bits>
      </reg>
      <reg name="nb_cfsro" protect="rw">
        <bits access="rw" name="nb_cfsr_overflow" pos="23:0" rst="16777215">
          <comment>NB frame overflow value</comment>
        </bits>
      </reg>
      <reg name="nb_fl" protect="r">
        <bits access="r" name="fl" pos="23:0" rst="0">
          <comment>NB frame locked value</comment>
        </bits>
      </reg>
      <reg name="nb_fcl" protect="r">
        <bits access="r" name="nb_fcl_nb_fcl" pos="16:0" rst="1">
          <comment>NB counter locked value</comment>
        </bits>
      </reg>
      <reg name="idle_frame_nb" protect="rw">
        <bits access="rw" name="frame_conf" pos="24" rst="0">
          <comment>enable(this bit cleared automatically after the frame interrupt generated)
0: disable
1:  enable</comment>
        </bits>
        <bits access="rw" name="frame_cfsr" pos="23:0" rst="0">
          <comment>interrupt occurred when current frame reach this register and counter equal to IDLE_FRAMC_NB</comment>
        </bits>
      </reg>
      <reg name="idle_framc_nb" protect="rw">
        <bits access="rw" name="framc_cfsr" pos="16:0" rst="1">
          <comment>IDLE NB frame interrupt generated when NB frame counter reach IDLE_FRAME_NB and NB counter equal to this register.</comment>
        </bits>
      </reg>
      <reg name="idl_awk_en_set" protect="rw">
        <bits access="rs" name="awk_en_set" pos="12:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set wakeup enable register  by writing 1 to correspond bits.</comment>
        </bits>
      </reg>
      <reg name="idl_awk_en_clr" protect="rw">
        <bits access="rc" name="awk_en_clear" pos="12:0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          clear wakeup enable register  by writing 1 to correspond bits.</comment>
        </bits>
      </reg>
      <reg name="gsm_framc" protect="rw">
        <bits access="rw" name="rd_enable" pos="20" rst="0">
          <comment>Read enable register.
This bit should be set first when read the value of GSM counter, then rd_enable bit cleared by hardware after locked the GSM counter.</comment>
        </bits>
        <bits access="r" name="framc" pos="16:0" rst="1">
          <comment>GSM framc</comment>
        </bits>
      </reg>
      <reg name="nb_framc" protect="rw">
        <bits access="rw" name="rd_enable" pos="20" rst="0">
          <comment>Read enable register.
This bit should be set first when read the value of NB counter, then rd_enable bit cleared by hardware after locked the NB counter.</comment>
        </bits>
        <bits access="r" name="framc" pos="16:0" rst="1">
          <comment>NB framc</comment>
        </bits>
      </reg>
      <reg name="eliminat_jitter" protect="rw">
        <bits access="rw" name="eliminat_time" pos="15:8" rst="1">
          <comment>Eliminate jitter delay register</comment>
        </bits>
        <bits access="rw" name="elimiate_en" pos="7:0" rst="0">
          <comment>Emilinate the jitter from awake signal when writing 1 to correspond bits.</comment>
        </bits>
      </reg>
      <reg name="gsm_en_sel" protect="rw">
        <bits access="rw" name="select" pos="0" rst="0">
          <comment>GGE low power Scheme selection signal
0: use RDA8909 LP  Scheme
1: use IDLE module of LP Scheme</comment>
        </bits>
      </reg>
      <reg name="nb_en_sel" protect="rw">
        <bits access="rw" name="select" pos="0" rst="0">
          <comment>NB low power Scheme selection signal
0: use RDA8909 LP  Scheme
1: use IDLE module of LP Scheme</comment>
        </bits>
      </reg>
      <reg name="pd_pll_sw" protect="rw">
        <bits access="rw" name="dsipll" pos="6" rst="0">
          <comment>1:disbale PLL
0:enable PLL</comment>
        </bits>
        <bits access="rw" name="mempll" pos="5" rst="0">
          <comment>1:disable PLL
0:enbale PLL</comment>
        </bits>
        <bits access="rw" name="usbpll" pos="4" rst="0">
          <comment>1:disable PLL
0:enable PLL</comment>
        </bits>
        <bits access="rw" name="audiopll" pos="3" rst="0">
          <comment>1:disable PLL
0:enable PLL</comment>
        </bits>
        <bits access="rw" name="apll" pos="2" rst="0">
          <comment>1:disable PLL
0:enable PLL</comment>
        </bits>
        <bits access="rw" name="bbpll2" pos="1" rst="0">
          <comment>1:disable PLL
0:enable PLL</comment>
        </bits>
        <bits access="rw" name="bbpll1" pos="0" rst="0">
          <comment>1:disable PLL
0:enable PLL</comment>
        </bits>
      </reg>
      <reg name="pd_pll_sw_set" protect="rw">
        <bits access="rs" name="pdpllswset" pos="6:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of  PD_PLL_SW
0:Invariance of corresponding bits
1:set 1 of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="pd_pll_sw_clr" protect="rw">
        <bits access="rc" name="pdpllswclr" pos="6:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of PD_PLL_SW
0:Invariance of corresponding bits
1:clean corresponding bits</comment>
        </bits>
      </reg>
      <reg name="pd_pll_sel" protect="rw">
        <bits access="rw" name="dsipll" pos="6" rst="0">
          <comment>select hardware signal or software register to control the PLL output clk switch
1:software register(bit6 of PD_PLL_SW)
0:hardware signal(IDLE module of pd_pll signal invert)</comment>
        </bits>
        <bits access="rw" name="mempll" pos="5" rst="0">
          <comment>select hardware signal or software register to control the PLL output clk switch
1:software register(bit5 of PD_PLL_SW)
0:hardware signal(IDLE module of pd_pll signal invert)</comment>
        </bits>
        <bits access="rw" name="usbpll" pos="4" rst="0">
          <comment>select hardware signal or software register to control the PLL switch
1:software register(bit4 of PD_PLL_SW)
0:hardware signal(IDLE module of pd_pll signal invert)</comment>
        </bits>
        <bits access="rw" name="audiopll" pos="3" rst="0">
          <comment>select hardware signal or software register to control the PLL switch
1:software register(bit3 of PD_PLL_SW)
0:hardware signal(IDLE module of pd_pll signal invert)</comment>
        </bits>
        <bits access="rw" name="apll" pos="2" rst="0">
          <comment>select hardware signal or software register to control the PLL switch
1:software register(bit2 of PD_PLL_SW)
0:hardware signal(IDLE module of pd_pll signal invert)</comment>
        </bits>
        <bits access="rw" name="bbpll2" pos="1" rst="0">
          <comment>select hardware signal or software register to control the PLL switch
1:software register(bit1 of PD_PLL_SW)
0:hardware signal(IDLE module of pd_pll signal invert)</comment>
        </bits>
        <bits access="rw" name="bbpll1" pos="0" rst="0">
          <comment>select hardware signal or software register to control the PLL switch
1:software register(bit0 of PD_PLL_SW)
0:hardware signal(IDLE module of pd_pll signal invert)</comment>
        </bits>
      </reg>
      <reg name="pd_pll_sel_set" protect="rw">
        <bits access="rs" name="pdpllselset" pos="6:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of PD_PLL_SEL
0:Invariance of corresponding bits
1:set 1 of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="pd_pll_sel_clr" protect="rw">
        <bits access="rc" name="pdpllselclr" pos="6:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of PD_PLL_SEL
0:Invariance of corresponding bits
1:clean corresponding bits</comment>
        </bits>
      </reg>
      <reg name="idle_cg_sw" protect="rw">
        <bits access="rw" name="dsipll" pos="6" rst="0">
          <comment>1:disable PLL output clk
0:enable PLL output clk</comment>
        </bits>
        <bits access="rw" name="mempll" pos="5" rst="0">
          <comment>1:disable PLL output clk
0:enable PLL output clk</comment>
        </bits>
        <bits access="rw" name="usbpll" pos="4" rst="0">
          <comment>1:disable PLL output clk
0:enable PLL output clk</comment>
        </bits>
        <bits access="rw" name="audiopll" pos="3" rst="0">
          <comment>1:disable PLL output clk
0:enable PLL output clk</comment>
        </bits>
        <bits access="rw" name="apll" pos="2" rst="0">
          <comment>1:disable PLL output clk
0:enable PLL output clk</comment>
        </bits>
        <bits access="rw" name="bbpll2" pos="1" rst="0">
          <comment>1:disable PLL output clk
0:enable PLL output clk</comment>
        </bits>
        <bits access="rw" name="bbpll1" pos="0" rst="0">
          <comment>1:disable PLL output clk
0:enable PLL output clk</comment>
        </bits>
      </reg>
      <reg name="idle_cg_sw_set" protect="rw">
        <bits access="rs" name="idlecgswset" pos="6:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of IDLE_CG_SW
0:Invariance of corresponding bits
1:set 1 of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="idle_cg_sw_clr" protect="rw">
        <bits access="rc" name="idlecgswclr" pos="6:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of IDLE_CG_SW
0:Invariance of corresponding bits
1:clean corresponding bits</comment>
        </bits>
      </reg>
      <reg name="idle_cg_sel" protect="rw">
        <bits access="rw" name="dsipll" pos="6" rst="0">
          <comment>select hardware signal or software register to control the PLL output clk switch
1:software register(bit6 of IDLE_CG_SW)
0:hardware signal(IDLE module of idle_cg signal invert)</comment>
        </bits>
        <bits access="rw" name="mempll" pos="5" rst="0">
          <comment>select hardware signal or software register to control the PLL output clk switch
1:software register(bit5 of IDLE_CG_SW)
0:hardware signal(IDLE module of idle_cg signal invert)</comment>
        </bits>
        <bits access="rw" name="usbpll" pos="4" rst="0">
          <comment>select hardware signal or software register to control the PLL output clk switch
1:software register(bit4 of IDLE_CG_SW)
0:hardware signal(IDLE module of idle_cg signal invert)</comment>
        </bits>
        <bits access="rw" name="audiopll" pos="3" rst="0">
          <comment>select hardware signal or software register to control the PLL output clk switch
1:software register(bit3 of IDLE_CG_SW)
0:hardware signal(IDLE module of idle_cg signal invert)</comment>
        </bits>
        <bits access="rw" name="apll" pos="2" rst="0">
          <comment>select hardware signal or software register to control the PLL output clk switch
1:software register(bit2 of IDLE_CG_SW)
0:hardware signal(IDLE module of idle_cg signal invert)</comment>
        </bits>
        <bits access="rw" name="bbpll2" pos="1" rst="0">
          <comment>select hardware signal or software register to control the PLL output clk switch
1:software register(bit1 of IDLE_CG_SW)
0:hardware signal(IDLE module of idle_cg signal invert)</comment>
        </bits>
        <bits access="rw" name="bbpll1" pos="0" rst="0">
          <comment>select hardware signal or software register to control the PLL output clk switch
1:software register(bit0 of IDLE_CG_SW)
0:hardware signal(IDLE module of idle_cg signal invert)</comment>
        </bits>
      </reg>
      <reg name="idle_cg_sel_set" protect="rw">
        <bits access="rs" name="idlecgselset" pos="6:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of IDLE_CG_SEL
0:Invariance of corresponding bits
1:set 1 of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="idle_cg_sel_clr" protect="rw">
        <bits access="rc" name="idlecgselclr" pos="6:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of IDLE_CG_SEL
0:Invariance of corresponding bits
1:clean corresponding bits</comment>
        </bits>
      </reg>
      <reg name="rf_idle_enable_sw" protect="rw">
        <bits access="rw" name="rfidleenablesw" pos="0" rst="0">
          <comment>1:control the RF_DIG enter in IDLE
0:control the RF_DIG exit to the IDLE</comment>
        </bits>
      </reg>
      <reg name="rf_idle_enable_sel" protect="rw">
        <bits access="rw" name="rfidleenablesel" pos="0" rst="1">
          <comment>select the hardware signal or software register to control the RF_DIG enter in or extit to IDLE model.
1:software register(RF_IDLE_ENABLE_SW)
0:hardware signal( pow_on signal invert of IDLE module)</comment>
        </bits>
      </reg>
      <hole size="256"/>
      <reg name="mem_ema_cfg" protect="rw">
        <bits access="rw" name="rftpd_rmb" pos="9:6" rst="2">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rmeb" pos="5" rst="0">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rma" pos="4:1" rst="2">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rmea" pos="0" rst="0">
          <comment>RFTPD type EMA signal</comment>
        </bits>
      </reg>
      <reg name="uart_ctrl" protect="rw">
        <bits access="rw" name="rst_ctrl_uart" pos="1" rst="1">
          <comment>UART module reset control:
0: reset
1: reset release</comment>
        </bits>
        <bits access="rw" name="enable_clk_uart" pos="0" rst="1">
          <comment>UART module clock control:
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="ddr_latch" protect="rw">
        <bits access="rw" name="psram_latch" pos="1" rst="0">
          <comment>PSRAM IO LATCH:
0: release PSRAM PAD
1: no release PSRAM PAD.This bit will be set &quot;1&quot; by hardware when AP power domain was shut-down.Software should write this bit to &quot;0&quot; after PSRAM initialization when AP wake-up from deep sleep.</comment>
        </bits>
        <bits access="rw" name="lpddr_latch" pos="0" rst="0">
          <comment>LPDDR IO LATCH:
0: release LPDDR PAD
1: no release LPDDR PAD.This bit will be set &quot;1&quot; by hardware when AP power domain was shut-down.Software should write this bit to &quot;0&quot; after LPDDR initialization when AP wake-up from deep sleep.</comment>
        </bits>
      </reg>
      <reg name="pad_ctrl" protect="rw">
        <bits access="rw" name="pad_misc_idle_wpdi" pos="27" rst="0">
      </bits>
        <bits access="rw" name="pad_osc_32k_drv" pos="26:25" rst="2">
      </bits>
        <bits access="rw" name="pad_osc_32k_se" pos="24" rst="0">
      </bits>
        <bits access="rw" name="pad_osc_32k_wpus" pos="23" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_6_pull_frc" pos="22" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_6_drv" pos="21:20" rst="2">
      </bits>
        <bits access="rw" name="pad_gpio_6_pull_dowe" pos="19" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_6_pull_up" pos="18" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_6_se" pos="17" rst="0">
      </bits>
        <bits access="rw" name="pad_gpio_6_wpus" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pad_chip_pd_out" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pad_chip_pd_out_frc" pos="14" rst="0">
      </bits>
        <bits access="rw" name="pad_chip_pd_pull_frc" pos="13" rst="0">
      </bits>
        <bits access="rw" name="pad_chip_pd_drv" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="pad_chip_pd_pull_dowe" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pad_chip_pd_pull_up" pos="9" rst="0">
      </bits>
        <bits access="rw" name="pad_chip_pd_se" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_chip_pd_wpus" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_rxd_pull_frc" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_rxd_drv" pos="5:4" rst="2">
      </bits>
        <bits access="rw" name="pad_uart_1_rxd_pull_dowe" pos="3" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_rxd_pull_up" pos="2" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_rxd_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_rxd_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <hole size="128"/>
      <reg name="pad_ctrl_uart_txd" protect="rw">
        <bits access="rw" name="pad_uart_1_txd_out" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_txd_out_frc" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_txd_pull_frc" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_txd_drv" pos="5:4" rst="2">
      </bits>
        <bits access="rw" name="pad_uart_1_txd_pull_dowe" pos="3" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_txd_pull_up" pos="2" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_txd_se" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pad_uart_1_txd_wpus" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="mon_sel" protect="rw">
        <bits access="rw" name="mon15_sel" pos="31:30" rst="0">
          <comment>mon15_sel:
00: select nb_en.
01: select awk_sys_valid.
10: select awake[7].
11: select target_timer_stat[1].</comment>
        </bits>
        <bits access="rw" name="mon14_sel" pos="29:28" rst="0">
          <comment>mon14_sel:
00: select gsm_en.
01: select wcn_chip_pd.
10: select awake[6].
11: select target_timer_stat[0].</comment>
        </bits>
        <bits access="rw" name="mon13_sel" pos="27:26" rst="0">
          <comment>mon13_sel:
00: select wake_timer.
01: select wcn_pd_xtal.
10: select awake[5].
11: select target_timer_enable.</comment>
        </bits>
        <bits access="rw" name="mon12_sel" pos="25:24" rst="0">
          <comment>mon12_sel:
00: select timer_en_nb.
01: select wcn_pd_pll.
10: select awake[4].
11: select nb_frame_int.</comment>
        </bits>
        <bits access="rw" name="mon11_sel" pos="23:22" rst="0">
          <comment>mon11_sel:
00: select timer_en_gsm.
01: select wcn_idle_cg.
10: select awake[3].
11: nb_lp_pu_done.</comment>
        </bits>
        <bits access="rw" name="mon10_sel" pos="21:20" rst="0">
          <comment>mon10_sel:
00: select timer_en_ltem2.
01: select nb_en_sel.
10: select awake[2].
11: select nb_lp_sf_slowrunning.</comment>
        </bits>
        <bits access="rw" name="mon9_sel" pos="19:18" rst="0">
          <comment>mon9_sel:
00: select timer_en_ltem1.
01: select gsm_en_sel.
10: select awake[1].
11: select nb_fint.</comment>
        </bits>
        <bits access="rw" name="mon8_sel" pos="17:16" rst="0">
          <comment>mon8_sel:
00: select idst_nb_timer.
01: select idle_chip_pd.
10: select awake[0].
11: select gsm_frame_int.</comment>
        </bits>
        <bits access="rw" name="mon7_sel" pos="15:14" rst="0">
          <comment>mon7_sel:
00: select idst_gsm_timer
01: select idle_pd_xtal.
10: select awk_self.
11: gsm_lp_pu_done.</comment>
        </bits>
        <bits access="rw" name="mon6_sel" pos="13:12" rst="0">
          <comment>mon6_sel:
00: select idst_ltem2_timer.
01: select idle_pd_pll.
10: select idst_gsm_ltem_timer.
11: select gsm_lp_sf_slowrunning.</comment>
        </bits>
        <bits access="rw" name="mon5_sel" pos="11:10" rst="0">
          <comment>mon5_sel:
00: select idst_ltem1_timer.
01: select idle_idle_cg.
10: select awk_gsm_ltem_timner.
11: select gsm_fint.</comment>
        </bits>
        <bits access="rw" name="mon4_sel" pos="9:8" rst="0">
          <comment>mon4_sel:
00: select idct_nb_timer.
01: select pow_on.
10: select idst_sys.
11: select rstctrl_uart.</comment>
        </bits>
        <bits access="rw" name="mon3_sel" pos="7:6" rst="0">
          <comment>mon3_sel:
00: select idct_gsm_timer.
01: select idct_sys_valid.
10: select nb_lp_pu_reach.
11: select clken_uart.</comment>
        </bits>
        <bits access="rw" name="mon2_sel" pos="5:4" rst="0">
          <comment>mon2_sel:
00: select idct_ltem2_timer.
01: select idct_ap.
10: select gsm_lp_pu_reach.
11: select psram_latch_reg.</comment>
        </bits>
        <bits access="rw" name="mon1_sel" pos="3:2" rst="0">
          <comment>mon1_sel:
00: select idct_ltem1_timer
01: select idct_cp.
10: select osw2_awk
11: select lpddr_latch_reg</comment>
        </bits>
        <bits access="rw" name="mon0_sel" pos="1:0" rst="1">
          <comment>mon0_sel:
00: select idct_timer.
01: select ltem1_fint.
10: select osw1_awk.
11: select ltem2_fint</comment>
        </bits>
      </reg>
      <reg name="mon_sel_set" protect="rw">
        <bits access="rw" name="mon_sel_set" pos="31:0" rst="0">
          <comment>set corresponding bits of MON_SEL
0:Invariance of corresponding bits
1:set corresponding bits</comment>
        </bits>
      </reg>
      <reg name="mon_sel_clr" protect="rw">
        <bits access="rw" name="mon_sel_clr" pos="31:0" rst="0">
          <comment>clear corresponding bits of MON_SEL
0:Invariance of corresponding bits
1:clear corresponding bits</comment>
        </bits>
      </reg>
      <reg name="target_timer" protect="rw">
        <bits access="rw" name="target_time" pos="31:0" rst="0">
          <comment>Interrupt generated when the reference 32K counter reach to this register value.</comment>
        </bits>
      </reg>
      <reg name="target_timer_en" protect="rw">
        <bits access="rw" name="disable_target_timer" pos="0" rst="0">
          <comment>1: disable target timer.
0: enable</comment>
        </bits>
      </reg>
      <reg name="target_value_lock" protect="rw">
        <bits access="rw" name="lock_value" pos="31:0" rst="0">
          <comment>The locked value of reference 32K when interrupt generated.</comment>
        </bits>
      </reg>
      <reg name="target_timer_stat" protect="r">
        <bits access="r" name="timer_stat_32k" pos="1" rst="0">
          <comment>Indicat the state of target timer in 32K clock domain</comment>
        </bits>
        <bits access="r" name="timer_stat_122m" pos="0" rst="0">
          <comment>Indicate the state of target timer in 122.88M clock domain</comment>
        </bits>
      </reg>
      <reg name="slow_sys_clk_sel_hwen" protect="rw">
        <bits access="rw" name="hwen" pos="0" rst="0">
          <comment>0:SLOW_CLK and system clk selected by software bit conrtol
1:SLOW_CLK and system clk select by hareware signal control</comment>
        </bits>
      </reg>
      <reg name="slow_clk_sel_hwen" protect="rw">
        <bits access="rw" name="hwen" pos="0" rst="0">
          <comment>0:SLOW_CLK selected(between 26M and 32k) by software bit control
1:SLOW_CLK selected(between 26M and 32k) by hareware signal control</comment>
        </bits>
      </reg>
      <reg name="sleep_prot_time" protect="rw">
        <bits access="rw" name="prot_time" pos="7:0" rst="9">
          <comment>The minimum threshold of deep sleep, to ensure PMIC have complete deep sleep in and deep sleep out.</comment>
        </bits>
      </reg>
      <hole size="125632"/>
      <reg name="idle_res0" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res1" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res2" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res3" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res4" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res5" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res6" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res7" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res8" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res9" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res10" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="idle_res11" protect="r">
        <bits access="r" name="reservedvalue_0" pos="31:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_mailbox.xml">
    <module category="Bb_sysctrl" name="CP_MAILBOX">
      <reg name="intgr0" protect="rw">
        <bits access="rw" name="interrupt0generate" pos="31:0" rst="0">
          <comment>sysmail0 Interrupt generate register</comment>
        </bits>
      </reg>
      <reg name="intstr0" protect="rw">
        <bits access="rs" name="interrupt0bitset" pos="31:0" rst="0">
          <comment>bit type is changed from ws to rs.
          sysmail0 interrupt bit set register</comment>
        </bits>
      </reg>
      <reg name="intcr0" protect="rw">
        <bits access="rc" name="interrupt0bitclean" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          sysmail0 interrupt clean register</comment>
        </bits>
      </reg>
      <reg name="intmr0" protect="rw">
        <bits access="rw" name="interrupt0mask" pos="31:0" rst="0">
          <comment>sysmail0 interrupt mask register</comment>
        </bits>
      </reg>
      <reg name="intsr0" protect="r">
        <bits access="r" name="interrupt0status" pos="31:0" rst="0">
          <comment>sysmail0 interrupt status register</comment>
        </bits>
      </reg>
      <reg name="intmsr0" protect="r">
        <bits access="r" name="interrupt0maskstatus" pos="31:0" rst="0">
          <comment>sysmail0 interrupt mask status register</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="intgr1" protect="rw">
        <bits access="rw" name="interrupt1generate" pos="31:0" rst="0">
          <comment>sysmail1 Interrupt generate register</comment>
        </bits>
      </reg>
      <reg name="intstr1" protect="rw">
        <bits access="rs" name="interrupt1bitset" pos="31:0" rst="0">
          <comment>bit type is changed from ws to rs.
          sysmail1 interrupt bit set register</comment>
        </bits>
      </reg>
      <reg name="intcr1" protect="rw">
        <bits access="rc" name="interrupt1bitclean" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          sysmail1 interrupt clean register</comment>
        </bits>
      </reg>
      <reg name="intmr1" protect="rw">
        <bits access="rw" name="interrupt1mask" pos="31:0" rst="0">
          <comment>sysmail1 interrupt mask register</comment>
        </bits>
      </reg>
      <reg name="intsr1" protect="r">
        <bits access="r" name="interrupt1status" pos="31:0" rst="0">
          <comment>sysmail1 interrupt status register</comment>
        </bits>
      </reg>
      <reg name="intmsr1" protect="r">
        <bits access="r" name="interrupt1maskstatus" pos="31:0" rst="0">
          <comment>sysmail1 interrupt mask  status register</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="intgr2" protect="rw">
        <bits access="rw" name="interrupt2generate" pos="31:0" rst="0">
          <comment>sysmail2 Interrupt generate register</comment>
        </bits>
      </reg>
      <reg name="intstr2" protect="rw">
        <bits access="rs" name="interrupt2bitset" pos="31:0" rst="0">
          <comment>bit type is changed from ws to rs.
          sysmail2 interrupt bit set register</comment>
        </bits>
      </reg>
      <reg name="intcr2" protect="rw">
        <bits access="rc" name="interrupt2bitclean" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          sysmail2 interrupt clean register</comment>
        </bits>
      </reg>
      <reg name="intmr2" protect="rw">
        <bits access="rw" name="interrupt2mask" pos="31:0" rst="0">
          <comment>sysmail2 interrupt mask register</comment>
        </bits>
      </reg>
      <reg name="intsr2" protect="r">
        <bits access="r" name="interrupt2status" pos="31:0" rst="0">
          <comment>sysmail2 interrupt status register</comment>
        </bits>
      </reg>
      <reg name="intmsr2" protect="r">
        <bits access="r" name="interrupt2maskstatus" pos="31:0" rst="0">
          <comment>sysmail2 interrupt mask  status register</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="intgr3" protect="rw">
        <bits access="rw" name="interrupt3generate" pos="31:0" rst="0">
          <comment>sysmail3 Interrupt generate register</comment>
        </bits>
      </reg>
      <reg name="intstr3" protect="rw">
        <bits access="rs" name="interrupt3bitset" pos="31:0" rst="0">
          <comment>bit type is changed from ws to rs.
          sysmail3 interrupt bit set register</comment>
        </bits>
      </reg>
      <reg name="intcr3" protect="rw">
        <bits access="rc" name="interrupt3bitclean" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          sysmail3 interrupt clean register</comment>
        </bits>
      </reg>
      <reg name="intmr3" protect="rw">
        <bits access="rw" name="interrupt3mask" pos="31:0" rst="0">
          <comment>sysmail3 interrupt mask register</comment>
        </bits>
      </reg>
      <reg name="intsr3" protect="r">
        <bits access="r" name="interrupt3status" pos="31:0" rst="0">
          <comment>sysmail3 interrupt status register</comment>
        </bits>
      </reg>
      <reg name="intmsr3" protect="r">
        <bits access="r" name="interrupt3maskstatus" pos="31:0" rst="0">
          <comment>sysmail3 interrupt mask  status register</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="intgr4" protect="rw">
        <bits access="rw" name="interrupt4generate" pos="31:0" rst="0">
          <comment>sysmail4 Interrupt generate register</comment>
        </bits>
      </reg>
      <reg name="intstr4" protect="rw">
        <bits access="rs" name="interrupt4bitset" pos="31:0" rst="0">
          <comment>bit type is changed from ws to rs.
          sysmail4 interrupt bit set register</comment>
        </bits>
      </reg>
      <reg name="intcr4" protect="rw">
        <bits access="rc" name="interrupt4bitclean" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          sysmail4 interrupt clean register</comment>
        </bits>
      </reg>
      <reg name="intmr4" protect="rw">
        <bits access="rw" name="interrupt4mask" pos="31:0" rst="0">
          <comment>sysmail4 interrupt mask register</comment>
        </bits>
      </reg>
      <reg name="intsr4" protect="r">
        <bits access="r" name="interrupt4status" pos="31:0" rst="0">
          <comment>sysmail4 interrupt status register</comment>
        </bits>
      </reg>
      <reg name="intmsr4" protect="r">
        <bits access="r" name="interrupt4maskstatus" pos="31:0" rst="0">
          <comment>sysmail4 interrupt mask  status register</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="intgr5" protect="rw">
        <bits access="rw" name="interrupt5generate" pos="31:0" rst="0">
          <comment>sysmail5 Interrupt generate register</comment>
        </bits>
      </reg>
      <reg name="intstr5" protect="rw">
        <bits access="rs" name="interrupt5bitset" pos="31:0" rst="0">
          <comment>bit type is changed from ws to rs.
          sysmail5 interrupt bit set register</comment>
        </bits>
      </reg>
      <reg name="intcr5" protect="rw">
        <bits access="rc" name="interrupt5bitclean" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          sysmail5 interrupt clean register</comment>
        </bits>
      </reg>
      <reg name="intmr5" protect="rw">
        <bits access="rw" name="interrupt5mask" pos="31:0" rst="0">
          <comment>sysmail5 interrupt mask register</comment>
        </bits>
      </reg>
      <reg name="intsr5" protect="r">
        <bits access="r" name="interrupt5status" pos="31:0" rst="0">
          <comment>sysmail5 interrupt status register</comment>
        </bits>
      </reg>
      <reg name="intmsr5" protect="r">
        <bits access="r" name="interrupt5maskstatus" pos="31:0" rst="0">
          <comment>sysmail5 interrupt mask  status register</comment>
        </bits>
      </reg>
      <hole size="576"/>
      <reg name="sysmail0" protect="rw">
        <bits access="rw" name="sysmail0" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail1" protect="rw">
        <bits access="rw" name="sysmail1" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail2" protect="rw">
        <bits access="rw" name="sysmail2" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail3" protect="rw">
        <bits access="rw" name="sysmail3" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail4" protect="rw">
        <bits access="rw" name="sysmail4" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail5" protect="rw">
        <bits access="rw" name="sysmail5" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail6" protect="rw">
        <bits access="rw" name="sysmail6" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail7" protect="rw">
        <bits access="rw" name="sysmail7" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail8" protect="rw">
        <bits access="rw" name="sysmail8" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail9" protect="rw">
        <bits access="rw" name="sysmail9" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail10" protect="rw">
        <bits access="rw" name="sysmail10" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail11" protect="rw">
        <bits access="rw" name="sysmail11" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail12" protect="rw">
        <bits access="rw" name="sysmail12" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail13" protect="rw">
        <bits access="rw" name="sysmail13" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail14" protect="rw">
        <bits access="rw" name="sysmail14" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail15" protect="rw">
        <bits access="rw" name="sysmail15" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail16" protect="rw">
        <bits access="rw" name="sysmail16" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail17" protect="rw">
        <bits access="rw" name="sysmail17" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail18" protect="rw">
        <bits access="rw" name="sysmail18" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail19" protect="rw">
        <bits access="rw" name="sysmail19" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail20" protect="rw">
        <bits access="rw" name="sysmail20" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail21" protect="rw">
        <bits access="rw" name="sysmail21" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail22" protect="rw">
        <bits access="rw" name="sysmail22" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail23" protect="rw">
        <bits access="rw" name="sysmail23" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail24" protect="rw">
        <bits access="rw" name="sysmail24" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail25" protect="rw">
        <bits access="rw" name="sysmail25" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail26" protect="rw">
        <bits access="rw" name="sysmail26" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail27" protect="rw">
        <bits access="rw" name="sysmail27" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail28" protect="rw">
        <bits access="rw" name="sysmail28" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail29" protect="rw">
        <bits access="rw" name="sysmail29" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail30" protect="rw">
        <bits access="rw" name="sysmail30" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail31" protect="rw">
        <bits access="rw" name="sysmail31" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="1024"/>
      <reg name="sysmail32" protect="rw">
        <bits access="rw" name="sysmail32" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail33" protect="rw">
        <bits access="rw" name="sysmail33" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail34" protect="rw">
        <bits access="rw" name="sysmail34" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail35" protect="rw">
        <bits access="rw" name="sysmail35" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail36" protect="rw">
        <bits access="rw" name="sysmail36" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail37" protect="rw">
        <bits access="rw" name="sysmail37" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail38" protect="rw">
        <bits access="rw" name="sysmail38" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail39" protect="rw">
        <bits access="rw" name="sysmail39" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail40" protect="rw">
        <bits access="rw" name="sysmail40" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail41" protect="rw">
        <bits access="rw" name="sysmail41" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail42" protect="rw">
        <bits access="rw" name="sysmail42" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail43" protect="rw">
        <bits access="rw" name="sysmail43" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail44" protect="rw">
        <bits access="rw" name="sysmail44" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail45" protect="rw">
        <bits access="rw" name="sysmail45" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail46" protect="rw">
        <bits access="rw" name="sysmail46" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail47" protect="rw">
        <bits access="rw" name="sysmail47" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail48" protect="rw">
        <bits access="rw" name="sysmail48" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail49" protect="rw">
        <bits access="rw" name="sysmail49" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail50" protect="rw">
        <bits access="rw" name="sysmail50" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail51" protect="rw">
        <bits access="rw" name="sysmail51" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail52" protect="rw">
        <bits access="rw" name="sysmail52" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail53" protect="rw">
        <bits access="rw" name="sysmail53" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail54" protect="rw">
        <bits access="rw" name="sysmail54" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail55" protect="rw">
        <bits access="rw" name="sysmail55" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail56" protect="rw">
        <bits access="rw" name="sysmail56" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail57" protect="rw">
        <bits access="rw" name="sysmail57" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail58" protect="rw">
        <bits access="rw" name="sysmail58" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail59" protect="rw">
        <bits access="rw" name="sysmail59" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail60" protect="rw">
        <bits access="rw" name="sysmail60" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail61" protect="rw">
        <bits access="rw" name="sysmail61" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail62" protect="rw">
        <bits access="rw" name="sysmail62" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail63" protect="rw">
        <bits access="rw" name="sysmail63" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="1024"/>
      <reg name="sysmail64" protect="rw">
        <bits access="rw" name="sysmail64" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail65" protect="rw">
        <bits access="rw" name="sysmail65" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail66" protect="rw">
        <bits access="rw" name="sysmail66" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail67" protect="rw">
        <bits access="rw" name="sysmail67" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail68" protect="rw">
        <bits access="rw" name="sysmail68" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail69" protect="rw">
        <bits access="rw" name="sysmail69" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail70" protect="rw">
        <bits access="rw" name="sysmail70" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail71" protect="rw">
        <bits access="rw" name="sysmail71" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail72" protect="rw">
        <bits access="rw" name="sysmail72" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail73" protect="rw">
        <bits access="rw" name="sysmail73" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail74" protect="rw">
        <bits access="rw" name="sysmail74" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail75" protect="rw">
        <bits access="rw" name="sysmail75" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail76" protect="rw">
        <bits access="rw" name="sysmail76" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail77" protect="rw">
        <bits access="rw" name="sysmail77" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail78" protect="rw">
        <bits access="rw" name="sysmail78" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail79" protect="rw">
        <bits access="rw" name="sysmail79" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail80" protect="rw">
        <bits access="rw" name="sysmail80" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail81" protect="rw">
        <bits access="rw" name="sysmail81" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail82" protect="rw">
        <bits access="rw" name="sysmail82" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail83" protect="rw">
        <bits access="rw" name="sysmail83" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail84" protect="rw">
        <bits access="rw" name="sysmail84" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail85" protect="rw">
        <bits access="rw" name="sysmail85" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail86" protect="rw">
        <bits access="rw" name="sysmail86" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail87" protect="rw">
        <bits access="rw" name="sysmail87" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail88" protect="rw">
        <bits access="rw" name="sysmail88" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail89" protect="rw">
        <bits access="rw" name="sysmail89" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail90" protect="rw">
        <bits access="rw" name="sysmail90" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail91" protect="rw">
        <bits access="rw" name="sysmail91" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail92" protect="rw">
        <bits access="rw" name="sysmail92" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail93" protect="rw">
        <bits access="rw" name="sysmail93" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail94" protect="rw">
        <bits access="rw" name="sysmail94" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail95" protect="rw">
        <bits access="rw" name="sysmail95" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="1024"/>
      <reg name="sysmail96" protect="rw">
        <bits access="rw" name="sysmail96" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail97" protect="rw">
        <bits access="rw" name="sysmail97" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail98" protect="rw">
        <bits access="rw" name="sysmail98" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail99" protect="rw">
        <bits access="rw" name="sysmail99" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail100" protect="rw">
        <bits access="rw" name="sysmail100" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail101" protect="rw">
        <bits access="rw" name="sysmail101" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail102" protect="rw">
        <bits access="rw" name="sysmail102" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail103" protect="rw">
        <bits access="rw" name="sysmail103" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail104" protect="rw">
        <bits access="rw" name="sysmail104" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail105" protect="rw">
        <bits access="rw" name="sysmail105" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail106" protect="rw">
        <bits access="rw" name="sysmail106" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail107" protect="rw">
        <bits access="rw" name="sysmail107" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail108" protect="rw">
        <bits access="rw" name="sysmail108" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail109" protect="rw">
        <bits access="rw" name="sysmail109" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail110" protect="rw">
        <bits access="rw" name="sysmail110" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail111" protect="rw">
        <bits access="rw" name="sysmail111" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail112" protect="rw">
        <bits access="rw" name="sysmail112" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail113" protect="rw">
        <bits access="rw" name="sysmail113" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail114" protect="rw">
        <bits access="rw" name="sysmail114" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail115" protect="rw">
        <bits access="rw" name="sysmail115" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail116" protect="rw">
        <bits access="rw" name="sysmail116" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail117" protect="rw">
        <bits access="rw" name="sysmail117" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail118" protect="rw">
        <bits access="rw" name="sysmail118" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail119" protect="rw">
        <bits access="rw" name="sysmail119" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail120" protect="rw">
        <bits access="rw" name="sysmail120" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail121" protect="rw">
        <bits access="rw" name="sysmail121" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail122" protect="rw">
        <bits access="rw" name="sysmail122" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail123" protect="rw">
        <bits access="rw" name="sysmail123" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail124" protect="rw">
        <bits access="rw" name="sysmail124" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail125" protect="rw">
        <bits access="rw" name="sysmail125" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail126" protect="rw">
        <bits access="rw" name="sysmail126" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail127" protect="rw">
        <bits access="rw" name="sysmail127" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="1024"/>
      <reg name="sysmail128" protect="rw">
        <bits access="rw" name="sysmail128" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail129" protect="rw">
        <bits access="rw" name="sysmail129" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail130" protect="rw">
        <bits access="rw" name="sysmail130" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail131" protect="rw">
        <bits access="rw" name="sysmail131" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail132" protect="rw">
        <bits access="rw" name="sysmail132" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail133" protect="rw">
        <bits access="rw" name="sysmail133" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail134" protect="rw">
        <bits access="rw" name="sysmail134" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail135" protect="rw">
        <bits access="rw" name="sysmail135" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail136" protect="rw">
        <bits access="rw" name="sysmail136" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail137" protect="rw">
        <bits access="rw" name="sysmail137" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail138" protect="rw">
        <bits access="rw" name="sysmail138" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail139" protect="rw">
        <bits access="rw" name="sysmail139" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail140" protect="rw">
        <bits access="rw" name="sysmail140" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail141" protect="rw">
        <bits access="rw" name="sysmail141" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail142" protect="rw">
        <bits access="rw" name="sysmail142" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail143" protect="rw">
        <bits access="rw" name="sysmail143" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail144" protect="rw">
        <bits access="rw" name="sysmail144" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail145" protect="rw">
        <bits access="rw" name="sysmail145" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail146" protect="rw">
        <bits access="rw" name="sysmail146" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail147" protect="rw">
        <bits access="rw" name="sysmail147" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail148" protect="rw">
        <bits access="rw" name="sysmail148" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail149" protect="rw">
        <bits access="rw" name="sysmail149" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail150" protect="rw">
        <bits access="rw" name="sysmail150" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail151" protect="rw">
        <bits access="rw" name="sysmail151" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail152" protect="rw">
        <bits access="rw" name="sysmail152" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail153" protect="rw">
        <bits access="rw" name="sysmail153" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail154" protect="rw">
        <bits access="rw" name="sysmail154" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail155" protect="rw">
        <bits access="rw" name="sysmail155" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail156" protect="rw">
        <bits access="rw" name="sysmail156" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail157" protect="rw">
        <bits access="rw" name="sysmail157" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail158" protect="rw">
        <bits access="rw" name="sysmail158" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail159" protect="rw">
        <bits access="rw" name="sysmail159" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="1024"/>
      <reg name="sysmail160" protect="rw">
        <bits access="rw" name="sysmail160" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail161" protect="rw">
        <bits access="rw" name="sysmail161" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail162" protect="rw">
        <bits access="rw" name="sysmail162" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail163" protect="rw">
        <bits access="rw" name="sysmail163" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail164" protect="rw">
        <bits access="rw" name="sysmail164" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail165" protect="rw">
        <bits access="rw" name="sysmail165" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail166" protect="rw">
        <bits access="rw" name="sysmail166" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail167" protect="rw">
        <bits access="rw" name="sysmail167" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail168" protect="rw">
        <bits access="rw" name="sysmail168" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail169" protect="rw">
        <bits access="rw" name="sysmail169" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail170" protect="rw">
        <bits access="rw" name="sysmail170" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail171" protect="rw">
        <bits access="rw" name="sysmail171" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail172" protect="rw">
        <bits access="rw" name="sysmail172" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail173" protect="rw">
        <bits access="rw" name="sysmail173" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail174" protect="rw">
        <bits access="rw" name="sysmail174" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail175" protect="rw">
        <bits access="rw" name="sysmail175" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail176" protect="rw">
        <bits access="rw" name="sysmail176" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail177" protect="rw">
        <bits access="rw" name="sysmail177" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail178" protect="rw">
        <bits access="rw" name="sysmail178" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail179" protect="rw">
        <bits access="rw" name="sysmail179" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail180" protect="rw">
        <bits access="rw" name="sysmail180" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail181" protect="rw">
        <bits access="rw" name="sysmail181" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail182" protect="rw">
        <bits access="rw" name="sysmail182" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail183" protect="rw">
        <bits access="rw" name="sysmail183" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail184" protect="rw">
        <bits access="rw" name="sysmail184" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail185" protect="rw">
        <bits access="rw" name="sysmail185" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail186" protect="rw">
        <bits access="rw" name="sysmail186" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail187" protect="rw">
        <bits access="rw" name="sysmail187" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail188" protect="rw">
        <bits access="rw" name="sysmail188" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail189" protect="rw">
        <bits access="rw" name="sysmail189" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail190" protect="rw">
        <bits access="rw" name="sysmail190" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="sysmail191" protect="rw">
        <bits access="rw" name="sysmail191" pos="31:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_clkrst.xml">
    <module category="Bb_sysctrl" name="CP_CLKRST">
      <reg name="clksel" protect="rw">
        <bits access="rw" name="idle_h_sel" pos="5:4" rst="0">
          <comment>clock select for module of IDLE_H:
00: 122.88M clock
01: 26M clock
10: 61.44M clock
11: 122.88M clock</comment>
        </bits>
        <bits access="rw" name="zsp_wd_sel" pos="3" rst="0">
          <comment>clock select for module of ZSP_WD:
0: 32K clock
1: 26M clock</comment>
        </bits>
        <bits access="rw" name="bb_sysctrl_wd_sel" pos="2" rst="0">
          <comment>clock select for module of BB_SYSCTRL_WD:
0: 32K clock
1: 26M clock</comment>
        </bits>
        <bits access="rw" name="slow_sel_480m" pos="1" rst="1">
          <comment>clock select of 480M and SLOW:
0: SLOW clock
1: 480M clock</comment>
        </bits>
        <bits access="rw" name="slow_sel_122m" pos="0" rst="1">
          <comment>clock select of 122M and SLOW:
0: SLOW clock
1: 122.88M clock</comment>
        </bits>
      </reg>
      <reg name="clksel_set" protect="rw">
        <bits access="rs" name="clkselset" pos="4:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of CLKSEL register:
0: Invariance of corresponding bits
1: set 1 of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="clksel_clr" protect="rw">
        <bits access="rc" name="clkselclear" pos="4:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of CLKSEL register:
0: Invariance of corresponding bits
1: clean of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="clkdiv_zsp" protect="rw">
        <bits access="rw" name="zsp_cd" pos="3:0" rst="0">
          <comment>ZSP and bus clock division:
0: no clock division
1: 1/16 clock division
2: 2/16 clock division
F: 15/16 clock division</comment>
        </bits>
      </reg>
      <reg name="clkdiv_lte" protect="rw">
        <bits access="rw" name="lte_cd" pos="3:0" rst="0">
          <comment>LTE accelerator function clock division:
0: no clock division
1: 1/16 clock division
2: 2/16 clock division
F: 15/16 clock division</comment>
        </bits>
      </reg>
      <reg name="clken_bb_sysctrl" protect="rw">
        <bits access="rw" name="clken_cp_wd" pos="4" rst="0">
          <comment>0: close
1: open</comment>
        </bits>
        <bits access="rw" name="clken_idle" pos="3" rst="1">
          <comment>0: close
1: open</comment>
        </bits>
        <bits access="rw" name="clken_mailbox" pos="2" rst="0">
          <comment>0: close
1: open</comment>
        </bits>
        <bits access="rw" name="clken_pwrctrl" pos="1" rst="1">
          <comment>0: close
1: open</comment>
        </bits>
        <bits access="rw" name="clken_sysreg" pos="0" rst="0">
          <comment>0: close
1: open</comment>
        </bits>
      </reg>
      <reg name="clken_bb_sysctrl_set" protect="rw">
        <bits access="rs" name="clken_bb_sysctrlset" pos="4:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of CLKEN_BB_SYSCTRL regsiter:
0: Invariance of corresponding bits
1: set 1 of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="clken_bb_sysctrl_clr" protect="rw">
        <bits access="rc" name="clken_bb_sysctrlclear" pos="4:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of CLKSEL register
0: Invariance of corresponding bits
1: clean of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="clken_zsp" protect="rw">
        <bits access="rw" name="clken_aud_dft" pos="5" rst="0">
          <comment>0: close
1: open</comment>
        </bits>
        <bits access="rw" name="clken_wd" pos="4" rst="0">
          <comment>0: close
1: open</comment>
        </bits>
        <bits access="rw" name="clken_busmon" pos="3" rst="0">
          <comment>0: close
1: open</comment>
        </bits>
        <bits access="rw" name="clken_zirq" pos="2" rst="0">
          <comment>0: close
1: open</comment>
        </bits>
        <bits access="rw" name="clken_axidma" pos="1" rst="0">
          <comment>0: close
1: open</comment>
        </bits>
        <bits access="rw" name="clken_zspcore" pos="0" rst="0">
          <comment>0: close
1: open</comment>
        </bits>
      </reg>
      <reg name="clken_zsp_set" protect="rw">
        <bits access="rs" name="clken_zspset" pos="5:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of CLKEN_ZSP regsiter:
0: Invariance of corresponding bits
1: set &quot;1&quot; of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="clken_zsp_clr" protect="rw">
        <bits access="rc" name="clken_zspclear" pos="5:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of CLKEN_ZSP register:
0: Invariance of corresponding bits
1: clean of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="clken_lte" protect="rw">
        <bits access="rw" name="clken_rxcapt" pos="12" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_rfad" pos="11" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_dlfft" pos="10" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_csirs" pos="9" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_pusch" pos="8" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_uldft" pos="7" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_otdoa" pos="6" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_iddet" pos="5" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_measpwr" pos="4" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_ldtc1" pos="3" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_ldtc" pos="2" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_coeff" pos="1" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_txrx" pos="0" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="clken_lte_set" protect="rw">
        <bits access="rs" name="clken_lteset" pos="12:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of CLKEN_LTE register
0: Invariance of corresponding bits
1: set &quot;1&quot; of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="clken_lte_clr" protect="rw">
        <bits access="rc" name="clken_lteclear" pos="12:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of CLKEN_LTE:
0: Invariance of corresponding bits
1: clean of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="clken_zspcore_mode" protect="rw">
        <bits access="rw" name="mode" pos="0" rst="0">
          <comment>0: ZSPCORE clock switch controlled by hardware
1: ZSPCORE clock switch controlled by register</comment>
        </bits>
      </reg>
      <reg name="clken_zsp_axidma_mode" protect="rw">
        <bits access="rw" name="mode" pos="0" rst="0">
          <comment>0: ZSP_AXIDMA clock switch controlled by hardware
1: ZSP_AXIDMA clock switch controlled by register</comment>
        </bits>
      </reg>
      <reg name="rstctrl_bb_sysctrl" protect="rw">
        <bits access="rw" name="rstctrl_monitor" pos="5" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_cp_wd" pos="4" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_idle" pos="3" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_mailbox" pos="2" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_pwrctrl" pos="1" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_sysreg" pos="0" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
      </reg>
      <reg name="rstctrl_bb_sysctrl_set" protect="rw">
        <bits access="rs" name="rstctrl_bb_sysctrlset" pos="5:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of RSTCTRL_BB_SYSCTRL register:
0: Invariance of corresponding bits
1: set &quot;1&quot; of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="rstctrl_bb_sysctrl_clr" protect="rw">
        <bits access="rc" name="rstctrl_bb_sysctrlclear" pos="5:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of RSTCTRL_BB_SYSCTRL:
0: Invariance of corresponding bits
1: set 1 of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="rstctrl_zsp" protect="rw">
        <bits access="rw" name="rstctrl_aud_dft" pos="5" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_wd" pos="4" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_busmon" pos="3" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_zirq" pos="2" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_axidma" pos="1" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_zspcore" pos="0" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
      </reg>
      <reg name="rstctrl_zsp_set" protect="rw">
        <bits access="rs" name="rstctrl_zspset" pos="5:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of RSTCTRL_ZSP register:
0: Invariance of corresponding bits
1: set &quot;1&quot; of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="rstctrl_zsp_clr" protect="rw">
        <bits access="rc" name="rstctrl_zspclear" pos="5:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of RSTCTRL_ZSP:
0: Invariance of corresponding bits
1: set &quot;1&quot; of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="rstctrl_lte" protect="rw">
        <bits access="rw" name="rstctrl_rxcapt" pos="13" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_rfad" pos="12" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_dlfft" pos="11" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_csirs" pos="10" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_pusch" pos="9" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_uldft" pos="8" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_otdoa" pos="7" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_iddet" pos="6" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_measpwr" pos="5" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_ldtc1" pos="4" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_ldtc" pos="3" rst="1">
          <comment>0: reset)
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_coeff" pos="2" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_txrx_rx" pos="1" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
        <bits access="rw" name="rstctrl_txrx_tx" pos="0" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
      </reg>
      <reg name="rstctrl_lte_set" protect="rw">
        <bits access="rs" name="rstctrl_lteset" pos="13:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of RSTCTRL_LTE register:
0: Invariance of corresponding bits
1: set &quot;1&quot; of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="rstctrl_lte_clr" protect="rw">
        <bits access="rc" name="rstctrl_lteclear" pos="13:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of RSTCTRL_LTE:
0: Invariance of corresponding bits
1: clean corresponding bits</comment>
        </bits>
      </reg>
      <reg name="zsp_soft_rst" protect="rw">
        <bits access="rw" name="zsp_soft_rst_ctrl" pos="0" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
      </reg>
      <reg name="lte_soft_rst" protect="rw">
        <bits access="rw" name="lte_soft_rst_ctrl" pos="0" rst="1">
          <comment>0: reset
1: no reset</comment>
        </bits>
      </reg>
      <reg name="zsp_axilpcnt" protect="rw">
        <bits access="rw" name="cnt" pos="15:0" rst="0">
          <comment>waiting time of bus entered low power model,calculated by bus clock</comment>
        </bits>
      </reg>
      <reg name="zsp_buslpmc" protect="rw">
        <bits access="rw" name="buslpmc_zspcore" pos="3" rst="0">
          <comment>Control bit of ZSP_CORE DOMAIN low power model
0: enable
1: disable</comment>
        </bits>
        <bits access="rw" name="buslpmc_phy" pos="2" rst="0">
          <comment>Control bit of PHY DOMAIN low power model
0: enable
1: disable</comment>
        </bits>
        <bits access="rw" name="buslpmc_sw2" pos="1" rst="0">
          <comment>control bit of SWITCH2 DOMAIN low power model
0: enable
1: disable</comment>
        </bits>
        <bits access="rw" name="buslpmc_sw1" pos="0" rst="0">
          <comment>control bit of SWITCH1 DOMAIN low power model:
0: enable
1: disable</comment>
        </bits>
      </reg>
      <reg name="zsp_buslpmc_set" protect="rw">
        <bits access="rs" name="zsp_buslpmcset" pos="3:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of ZSP_BUSLPMC register
0: Invariance of corresponding bits
1: set &quot;1&quot; of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="zsp_buslpmc_clr" protect="rw">
        <bits access="rc" name="zsp_buslpmcclear" pos="3:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of ZSP_BUSLPMC
0: Invariance of corresponding bits
1: clean corresponding bits</comment>
        </bits>
      </reg>
      <reg name="zsp_busforcelpmc" protect="rw">
        <bits access="rw" name="busforcelpmc_zspcore" pos="3" rst="0">
          <comment>control bit of ZSPCORE force entering in low power model:
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="busforcelpmc_phy" pos="2" rst="0">
          <comment>control bit of PHY DOMAIN force entering in low power model:
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="busforcelpmc_sw2" pos="1" rst="0">
          <comment>control bit of SWITCH2 DOMAIN force entering in low power model:
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="busforcelpmc_sw1" pos="0" rst="0">
          <comment>control bit of SWITCH1 DOMAIN force entering in low power model:
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="zsp_busforcelpmc_set" protect="rw">
        <bits access="rs" name="zsp_busforcelpmcset" pos="3:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of ZSP_BUSFORCELPMC:
0: Invariance of corresponding bits
1: clean corresponding bits</comment>
        </bits>
      </reg>
      <reg name="zsp_busforcelpmc_clr" protect="rw">
        <bits access="rc" name="zsp_busforcelpmcclear" pos="3:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of ZSP_BUSFORCELPMC:
0: Invariance of corresponding bits
1: clean corresponding bits</comment>
        </bits>
      </reg>
      <reg name="clken_mailbox_mode" protect="rw">
        <bits access="rw" name="mode" pos="0" rst="0">
          <comment>0: MAILBOX clock switch controlled by hardware
1: MAILBOX clock switch controlled by register</comment>
        </bits>
      </reg>
      <reg name="clken_lte_intf" protect="rw">
        <bits access="rw" name="clken_rxcapt_intf" pos="12" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_rfad_intf" pos="11" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_dlfft_intf" pos="10" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_csirs_intf" pos="9" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_pusch_intf" pos="8" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_uldft_intf" pos="7" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_otdoa_intf" pos="6" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_iddet_intf" pos="5" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_measpwr_intf" pos="4" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_ldtc1_intf" pos="3" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_ldtc_intf" pos="2" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_coeff_intf" pos="1" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="clken_txrx_intf" pos="0" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="clken_lte_intf_set" protect="rw">
        <bits access="rs" name="clken_lte_intfset" pos="12:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of CLKEN_LTE_INTF register
0: Invariance of corresponding bits
1: set &quot;1&quot; of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="clken_lte_intf_clr" protect="rw">
        <bits access="rc" name="clken_lte_intfclear" pos="12:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of CLKEN_LTE_INTF register
0: Invariance of corresponding bits
1: clean of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="lte_autogate_mode" protect="rw">
        <bits access="rw" name="mode" pos="0" rst="0">
          <comment>0: LTE module clock auto gating individual
1: LTE modules invide into two parties : &quot;uplink&quot; and &quot;downlink&quot;, and auto gating individual</comment>
        </bits>
      </reg>
      <reg name="lte_autogate_en" protect="rw">
        <bits access="rw" name="uplink_intf_autogate_en" pos="27" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="downlink_intf_autogate_en" pos="26" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="uplink_func_autogate_en" pos="25" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="downlink_func_autogate_en" pos="24" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="dlfft_intf_autogate_en" pos="21" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="csirs_intf_autogate_en" pos="20" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="pusch_intf_autogate_en" pos="19" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="uldft_intf_autogate_en" pos="18" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="otdoa_intf_autogate_en" pos="17" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="iddet_intf_autogate_en" pos="16" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="measpwr_intf_autogate_en" pos="15" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="ldtc1_intf_autogate_en" pos="14" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="ldtc_intf_autogate_en" pos="13" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="coeff_intf_autogate_en" pos="12" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="txrx_intf_autogate_en" pos="11" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="dlfft_func_autogate_en" pos="10" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="csirs_func_autogate_en" pos="9" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="pusch_func_autogate_en" pos="8" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="uldft_func_autogate_en" pos="7" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="otdoa_func_autogate_en" pos="6" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="iddet_func_autogate_en" pos="5" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="measpwr_func_autogate_en" pos="4" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="ldtc1_func_autogate_en" pos="3" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="ldtc_func_autogate_en" pos="2" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="coeff_func_autogate_en" pos="1" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="txrx_func_autogate_en" pos="0" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="lte_autogate_en_set" protect="rw">
        <bits access="rs" name="clken_lte_intfset" pos="27:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of LTE_AUTOGATE_EN register
0: Invariance of corresponding bits
1: set &quot;1&quot; of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="lte_autogate_en_clr" protect="rw">
        <bits access="rc" name="clken_lte_intfclear" pos="27:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of LTE_AUTOGATE_EN register
0: Invariance of corresponding bits
1: clean of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="lte_autogate_delay_num" protect="rw">
        <bits access="rw" name="delaycounternumber" pos="7:0" rst="16">
          <comment>When LTE autogating function enable, After module &quot;running&quot; signal was pull down, a counter begin to count from zero.LTE modules clock will be gated when the counter counts to this number value.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_pwrctrl.xml">
    <module category="Bb_sysctrl" name="CP_PWRCTRL">
      <reg name="pwr_hwen" protect="rw">
        <bits access="rw" name="aon_lp_pon_en" pos="6" rst="0">
          <comment>AON_LP hardware power domain switch:
1:AON_LP power domain switch controlled by hardware signal.
0:AON_LP power domain switch controlled by regiser.</comment>
        </bits>
        <bits access="rw" name="btfm_pon_en" pos="5" rst="0">
          <comment>BTFM hardware power domain switch:
1:BTFM power domain switch controlled by hardware signal.
0:BTFM power domain switch controlled by regiser.</comment>
        </bits>
        <bits access="rw" name="rf_pon_en" pos="4" rst="0">
          <comment>RF hardware power domain switch:
1:RF power domain switch controlled by hardware signal.
0:RF power domain switch controlled by register.</comment>
        </bits>
        <bits access="rw" name="gge_pon_en" pos="3" rst="0">
          <comment>GGE hardware power domian switch:
1:GGE power domain switch controlled by hardware signal.
0:GGEpower domain switch controlled by register.</comment>
        </bits>
        <bits access="rw" name="lte_pon_en" pos="2" rst="0">
          <comment>LTE hardware power domain switch:
1:LTE power domain switch controlled by hardware signal.
0:LTE power domain switch controlled by register.</comment>
        </bits>
        <bits access="rw" name="zsp_pon_en" pos="1" rst="0">
          <comment>ZSP hardware power domain switch:
1:ZSP power domain switch controlled by hardware signal .
0:ZSP power domain switch controlled by register.</comment>
        </bits>
        <bits access="rw" name="ap_pwr_en" pos="0" rst="1">
          <comment>AP hardware power domain switch:
1:AP power domain switch controlled by hardware signal.
0:AP power domain switch controlled by register.</comment>
        </bits>
      </reg>
      <reg name="ap_pwr_ctrl" protect="rw">
        <bits access="rw" name="ap_pon" pos="1" rst="1">
          <comment>AP power domain on:
1:AP power domain on.
0:after AP power domain on,hardware cleared.</comment>
        </bits>
        <bits access="rw" name="ap_poff" pos="0" rst="0">
          <comment>AP power domain off:
1:AP power domian off.
0:after AP power domain off,hareware cleared.</comment>
        </bits>
      </reg>
      <reg name="zsp_pwr_ctrl" protect="rw">
        <bits access="rw" name="zsp_pon" pos="1" rst="0">
          <comment>ZSP power domain on:
1:ZSP power domain on.
0:after ZSP power domain on,hardware cleared.</comment>
        </bits>
        <bits access="rw" name="zsp_poff" pos="0" rst="1">
          <comment>ZSP power domain off:
1:ZSP power domain off.
0:after ZSP power domain off,hardware cleared.</comment>
        </bits>
      </reg>
      <reg name="lte_pwr_ctrl" protect="rw">
        <bits access="rw" name="lte_pon" pos="1" rst="0">
          <comment>LTE power domain on:
1:LTE power domain on.
0:after LTE power domain on,hardware cleared.</comment>
        </bits>
        <bits access="rw" name="lte_poff" pos="0" rst="1">
          <comment>LTE power domain off:
1:LTE power domain off.
0:after LTE power domain off,hardware cleared.</comment>
        </bits>
      </reg>
      <reg name="gge_pwr_ctrl" protect="rw">
        <bits access="rw" name="gge_pon" pos="1" rst="0">
          <comment>GGE power domain on:
1:GGE power domain on.
0:after GGE power domain on,hardware cleared.</comment>
        </bits>
        <bits access="rw" name="gge_poff" pos="0" rst="1">
          <comment>GGE power domain off:
1:GGE power domain off.
0:after GGE power domain off,hardware cleared.</comment>
        </bits>
      </reg>
      <reg name="rf_pwr_ctrl" protect="rw">
        <bits access="rw" name="rf_pon" pos="1" rst="1">
          <comment>RF power domain on:
1:RF power domain on.
0:after RF power domain on,hardware cleared.</comment>
        </bits>
        <bits access="rw" name="rf_poff" pos="0" rst="0">
          <comment>RF power domain off:
1:RF power domain off.
0:after RF power domain off,hardware cleared.</comment>
        </bits>
      </reg>
      <reg name="btfm_pwr_ctrl" protect="rw">
        <bits access="rw" name="btfm_pon" pos="1" rst="0">
          <comment>BTFM power domain on:
1:BTFM power domain on.
0:after BTFM power domain on,hardware cleared.</comment>
        </bits>
        <bits access="rw" name="btfm_poff" pos="0" rst="1">
          <comment>BTFM power domain off:
1:BTFM power domain off.
0:after BTFM power domain off,hardware cleared.</comment>
        </bits>
      </reg>
      <reg name="aon_lp_pwr_ctrl" protect="rw">
        <bits access="rw" name="aon_lp_pon" pos="1" rst="0">
          <comment>AON_LP power domain on:
1:AON_LP power domain on.
0:after AON_LP power domain on,hardware cleared.</comment>
        </bits>
        <bits access="rw" name="aon_lp_poff" pos="0" rst="1">
          <comment>AON_LP power domain off:
1:AON_LP power domain off.
0:after AON_LP power domain off,hardware cleared.</comment>
        </bits>
      </reg>
      <reg name="ap_pwr_stat" protect="r">
        <bits access="r" name="ap_stable" pos="1" rst="0">
          <comment>AP power domain stable state:
1:power domain stable.
0:power domain unstable,in the power on/off of the middle state.</comment>
        </bits>
        <bits access="r" name="ap_pstat" pos="0" rst="0">
          <comment>AP power domain current state:
1:on
0:off</comment>
        </bits>
      </reg>
      <reg name="zsp_pwr_stat" protect="r">
        <bits access="r" name="zsp_stable" pos="1" rst="0">
          <comment>ZSP power domain stable state:
1:power domain stable.
0:power domain unstable,in the power on/off of the middle state.</comment>
        </bits>
        <bits access="r" name="zsp_pstat" pos="0" rst="0">
          <comment>ZSP power domain current state:
1:on
0:off</comment>
        </bits>
      </reg>
      <reg name="lte_pwr_stat" protect="r">
        <bits access="r" name="lte_stable" pos="1" rst="0">
          <comment>LTE power domain stable state:
1:power domain stable.
0:power domain unstable,in the power on/off of the middle state.</comment>
        </bits>
        <bits access="r" name="lte_pstat" pos="0" rst="0">
          <comment>LTE power domain current state:
1:on
0:off</comment>
        </bits>
      </reg>
      <reg name="gge_pwr_stat" protect="r">
        <bits access="r" name="gge_stable" pos="1" rst="0">
          <comment>GGE power domain stable state:
1:power domain stable.
0:power domain unstable,in the power on/off the middle state.</comment>
        </bits>
        <bits access="r" name="gge_pstat" pos="0" rst="0">
          <comment>GGE power domain current state:
1:on
0:off</comment>
        </bits>
      </reg>
      <reg name="rf_pwr_stat" protect="r">
        <bits access="r" name="rf_stable" pos="1" rst="0">
          <comment>RF power domain stable state:
1:power domain stable.
0:power domain unstable,in the power on/off the middle state.</comment>
        </bits>
        <bits access="r" name="rf_pstat" pos="0" rst="0">
          <comment>RF power domain current state:
1:on
0:off</comment>
        </bits>
      </reg>
      <reg name="btfm_pwr_stat" protect="r">
        <bits access="r" name="btfm_stable" pos="1" rst="0">
          <comment>BTFM power domain stable state:
1:power domain stable.
0:power domain unstable,in the power on/off the middle state.</comment>
        </bits>
        <bits access="r" name="btfm_pstat" pos="0" rst="0">
          <comment>BTFM power domain current state:
1:on
0:off</comment>
        </bits>
      </reg>
      <reg name="aon_lp_pwr_stat" protect="r">
        <bits access="r" name="aon_lp_stable" pos="1" rst="0">
          <comment>AON_LP power domain stable state:
1:power domain stable.
0:power domain unstable,in the power on/off the middle state.</comment>
        </bits>
        <bits access="r" name="aon_lp_pstat" pos="0" rst="0">
          <comment>AON_LP power domain current state:
1:on
0:off</comment>
        </bits>
      </reg>
      <reg name="state_delay" protect="rw">
        <bits access="rw" name="delay" pos="7:0" rst="255">
          <comment>power control state machine for Intermediate state delay value,use function clk count</comment>
        </bits>
      </reg>
      <reg name="prepgc_delay" protect="rw">
        <bits access="rw" name="delay" pos="15:0" rst="208">
          <comment>power gating cell domain power-on of waiting time value,use function clk count.</comment>
        </bits>
      </reg>
      <reg name="allpgc_delay" protect="rw">
        <bits access="rw" name="delay" pos="15:0" rst="1280">
          <comment>All of power gating cell power-on of waiting time value,use function clk count.</comment>
        </bits>
      </reg>
      <reg name="ddr_hold_ctrl" protect="rw">
        <bits access="rw" name="hold_ctrl" pos="0" rst="0">
          <comment>0:release DDR port signals
1:no release DDR port signals.This bit will be set &quot;1&quot; by hardware when AP power domain was shut-down.Software should write this bit to &quot;0&quot; after ddr initialization when AP wake-up from deep sleep.</comment>
        </bits>
      </reg>
      <reg name="zsp_pd_poll" protect="rw">
        <bits access="rw" name="zsp_poll" pos="2" rst="0">
          <comment>1:vote for off ZSP power domain
0:vote for on ZSP power domain</comment>
        </bits>
        <bits access="rw" name="cp_poll" pos="1" rst="0">
          <comment>1:vote for off ZSP power domain
0:vote for on ZSP power domain</comment>
        </bits>
        <bits access="rw" name="ap_poll" pos="0" rst="0">
          <comment>1:vote for off ZSP power domain
0:vote for on ZSP power domain</comment>
        </bits>
      </reg>
      <reg name="zsp_pd_poll_set" protect="rw">
        <bits access="rs" name="zsppollset" pos="2:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of ZSP_PD_POLL
0:Invariance of corresponding bits
1:set 1 of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="zsp_pd_poll_clr" protect="rw">
        <bits access="rc" name="zsppollclr" pos="2:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of ZSP_PD_POLL
0:Invariance of corresponding bits
1:clean corresponding bits</comment>
        </bits>
      </reg>
      <hole size="448"/>
      <reg name="wcn_lps" protect="rw">
        <bits access="r" name="wcn2sys_sleep" pos="3" rst="0">
          <comment>wcn2sys_sleep signal state</comment>
        </bits>
        <bits access="r" name="wcn2sys_osc_en" pos="2" rst="0">
          <comment>wcn2sys_osc_en signal state</comment>
        </bits>
        <bits access="r" name="wcn2sys_wakeup" pos="1" rst="0">
          <comment>wcn2sys_wakeup signal state</comment>
        </bits>
        <bits access="rw" name="sys2wcn_wakeup" pos="0" rst="0">
          <comment>control WCN sub_system of awake siganl:sys2wcn_awake</comment>
        </bits>
      </reg>
      <reg name="arm_slp_req_sw" protect="rw">
        <bits access="rw" name="armslpreq" pos="0" rst="0">
          <comment>when this bit set &quot;1&quot;,the hardware signal arm_slp_req will enter in ARM sub_system ,force ARM's AXI bus enter LP model.
0:normal work
1:SLEEP request</comment>
        </bits>
      </reg>
      <reg name="arm_slp_ack" protect="r">
        <bits access="r" name="armslpack" pos="0" rst="1">
          <comment>the work status of  AXI bus in  ARM sub_system .
0:normal work
1:low_power state</comment>
        </bits>
      </reg>
      <reg name="arm_slp_req_hwen" protect="rw">
        <bits access="rw" name="armslpreq_hwen" pos="0" rst="1">
          <comment>0:the hardware signal arm_slp_req controlled by ARM_SLP_REQ_SW register,and pwrctrl status is bypass.
1:pwrctrl status controlled by the hardware signal of arm_slp_req.</comment>
        </bits>
      </reg>
      <reg name="zsp_slp_req_sw" protect="rw">
        <bits access="rw" name="zspslpreq" pos="0" rst="0">
          <comment>when this bit set &quot;1&quot;,zsp_slp_req signal will enter in ZSP sub_system ,force ZSP's AXI bus enter in LP model. Before ZSP sub_system software reset,need this bit set &quot;1&quot;,and wait ZSP_SLP_ACK register to be &quot;1&quot;.after ZSP sub_system reset,should set this bit &quot;0&quot;,so that ZSP bus can normal work.
0:normal work
1:SLEEP request</comment>
        </bits>
      </reg>
      <reg name="zsp_slp_ack" protect="r">
        <bits access="r" name="zspslpack" pos="0" rst="0">
          <comment>the status of AXI bus in ZSP sub_system.
0:normal work
1:low_power state</comment>
        </bits>
      </reg>
      <reg name="zsp_slp_req_hwen" protect="rw">
        <bits access="rw" name="zspslpreq_hwen" pos="0" rst="1">
          <comment>0:zsp_slp_req signal controlled by ZSP_SLP_REQ_SW register,and pwrctrl status is bypass.
1: pwrctrl status controlled by the hareware signal of zsp_slp_req</comment>
        </bits>
      </reg>
      <reg name="ddr_slp_req_sw" protect="rw">
        <bits access="rw" name="ddrslpreq" pos="0" rst="0">
          <comment>when this bit set &quot;1&quot;,ddr_slp_req hardware signal will enter in ARM sub_system,force DDR enter in self refresh.
0:normal work
1:SLEEP request</comment>
        </bits>
      </reg>
      <reg name="ddr_slp_ack" protect="r">
        <bits access="r" name="ddrslpack" pos="0" rst="0">
          <comment>DDR work status
0:normal work status
1:low_power(self_refresh)state</comment>
        </bits>
      </reg>
      <reg name="ddr_slp_req_hwen" protect="rw">
        <bits access="rw" name="ddrslpreq_hwen" pos="0" rst="1">
          <comment>0:ddr_slp_req is the hardware signal controlled by DDR_SLP_REQ_SW register,and pwrctrl corresponding status is bypass.
1:pwrctrl status controlled by the hareware signal of ddr_slp_req</comment>
        </bits>
      </reg>
      <reg name="timeout_flag" protect="rw">
        <bits access="rw" name="ddrslptimeout" pos="2" rst="0">
          <comment>0:normal work
1:DDR sleep request time out</comment>
        </bits>
        <bits access="rw" name="zspbusslptimeout" pos="1" rst="0">
          <comment>0:normal work
1:ZSP bus sleep request time out</comment>
        </bits>
        <bits access="rw" name="armbusslptimeout" pos="0" rst="0">
          <comment>0:normal work
1:ARM bus sleep request time out</comment>
        </bits>
      </reg>
      <reg name="power_state" protect="r">
        <bits access="r" name="corepowerstate" pos="31:28" rst="0">
          <comment>power domain auto control state machine status</comment>
        </bits>
        <bits access="r" name="aonlppowerstate" pos="27:24" rst="0">
          <comment>AON_LP power domain state of machine status</comment>
        </bits>
        <bits access="r" name="btfmpowerstate" pos="23:20" rst="0">
          <comment>BTFM power domain state of machine status</comment>
        </bits>
        <bits access="r" name="rfpowerstate" pos="19:16" rst="0">
          <comment>RF power domain state of  machine status</comment>
        </bits>
        <bits access="r" name="ggepowerstate" pos="15:12" rst="0">
          <comment>GGE power domain state of machine status</comment>
        </bits>
        <bits access="r" name="ltepowerstate" pos="11:8" rst="0">
          <comment>LTE power domain state of machine status</comment>
        </bits>
        <bits access="r" name="zsppowerstate" pos="7:4" rst="0">
          <comment>ZSP power domain state of  machine status</comment>
        </bits>
        <bits access="r" name="armpowerstate" pos="3:0" rst="0">
          <comment>ARM power domain state of machine status</comment>
        </bits>
      </reg>
      <reg name="pwrctrl_mode" protect="rw">
        <bits access="rw" name="pwr_mode" pos="0" rst="1">
          <comment>0:power domain control siganl conrtolled by related bit of PWRCTRL_SW register
1:power domain conrtol signal conrtolled by hardware signal of PWRCTRL</comment>
        </bits>
      </reg>
      <reg name="pwrctrl_sw" protect="rw">
        <bits access="rw" name="btfm_pwr_ctrl" pos="29" rst="0">
          <comment>btfm_pwr_ctrl</comment>
        </bits>
        <bits access="rw" name="btfm_pwr_ctrl_pre" pos="28" rst="0">
          <comment>btfm_pwr_ctrl_pre</comment>
        </bits>
        <bits access="rw" name="btfm_hold" pos="27" rst="1">
          <comment>btfm_hold</comment>
        </bits>
        <bits access="rw" name="btfm_rst_ctrl" pos="26" rst="0">
          <comment>btfm_rst_ctrl</comment>
        </bits>
        <bits access="rw" name="btfm_clk_ctrl" pos="25" rst="0">
          <comment>btfm_clk_ctrl</comment>
        </bits>
        <bits access="rw" name="rf_pwr_ctrl" pos="24" rst="1">
          <comment>rf_pwr_ctrl</comment>
        </bits>
        <bits access="rw" name="rf_pwr_ctrl_pre" pos="23" rst="1">
          <comment>rf_pwr_ctrl_pre</comment>
        </bits>
        <bits access="rw" name="rf_hold" pos="22" rst="1">
          <comment>rf_hold</comment>
        </bits>
        <bits access="rw" name="rf_rst_ctrl" pos="21" rst="0">
          <comment>rf_rst_ctrl</comment>
        </bits>
        <bits access="rw" name="rf_clk_ctrl" pos="20" rst="0">
          <comment>rf_clk_ctrl</comment>
        </bits>
        <bits access="rw" name="gge_pwr_ctrl" pos="19" rst="0">
          <comment>gge_pwr_ctrl</comment>
        </bits>
        <bits access="rw" name="gge_pwr_ctrl_pre" pos="18" rst="0">
          <comment>gge_pwr_ctrl_pre</comment>
        </bits>
        <bits access="rw" name="gge_hold" pos="17" rst="1">
          <comment>gge_hold</comment>
        </bits>
        <bits access="rw" name="gge_rst_ctrl" pos="16" rst="0">
          <comment>gge_rst_ctrl</comment>
        </bits>
        <bits access="rw" name="gge_clk_ctrl" pos="15" rst="0">
          <comment>gge_clk_ctrl</comment>
        </bits>
        <bits access="rw" name="lte_pwr_ctrl" pos="14" rst="0">
          <comment>lte_pwr_ctrl</comment>
        </bits>
        <bits access="rw" name="lte_pwr_ctrl_pre" pos="13" rst="0">
          <comment>lte_pwr_ctrl_pre</comment>
        </bits>
        <bits access="rw" name="lte_hold" pos="12" rst="1">
          <comment>lte_hold</comment>
        </bits>
        <bits access="rw" name="lte_rst_ctrl" pos="11" rst="0">
          <comment>lte_rst_ctrl</comment>
        </bits>
        <bits access="rw" name="lte_clk_ctrl" pos="10" rst="0">
          <comment>lte_clk_ctrl</comment>
        </bits>
        <bits access="rw" name="zsp_pwr_ctrl" pos="9" rst="0">
          <comment>zsp_pwr_ctrl</comment>
        </bits>
        <bits access="rw" name="zsp_pwr_ctrl_pre" pos="8" rst="0">
          <comment>zsp_pwr_ctrl_pre</comment>
        </bits>
        <bits access="rw" name="zsp_hold" pos="7" rst="1">
          <comment>zsp_hold</comment>
        </bits>
        <bits access="rw" name="zsp_rst_ctrl" pos="6" rst="0">
          <comment>zsp_rst_ctrl</comment>
        </bits>
        <bits access="rw" name="zsp_clk_ctrl" pos="5" rst="0">
          <comment>zsp_clk_ctrl</comment>
        </bits>
        <bits access="rw" name="ap_pwr_ctrl" pos="4" rst="1">
          <comment>ap_pwr_ctrl</comment>
        </bits>
        <bits access="rw" name="ap_pwr_ctrl_pre" pos="3" rst="1">
          <comment>ap_pwr_ctrl_pre</comment>
        </bits>
        <bits access="rw" name="ap_hold" pos="2" rst="1">
          <comment>ap_hold</comment>
        </bits>
        <bits access="rw" name="ap_rst_ctrl" pos="1" rst="0">
          <comment>ap_rst_ctrl</comment>
        </bits>
        <bits access="rw" name="ap_clk_ctrl" pos="0" rst="0">
          <comment>ap_clk_ctrl</comment>
        </bits>
      </reg>
      <reg name="pwrctrl_sw_set" protect="rw">
        <bits access="rs" name="set" pos="29:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of PWRCTRL_SW
0:Invariance of corresponding bits
1:set 1 of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="pwrctrl_sw_clr" protect="rw">
        <bits access="rc" name="clear" pos="29:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of PWRCTRL_SW
0:Invariance of corresponding bits
1:clean corresponding bits</comment>
        </bits>
      </reg>
      <reg name="pwrctrl_sw1" protect="rw">
        <bits access="rw" name="aon_lp_pwr_ctrl" pos="4" rst="1">
          <comment>aon_lp_pwr_ctrl</comment>
        </bits>
        <bits access="rw" name="aon_lp_pwr_ctrl_pre" pos="3" rst="1">
          <comment>aon_lp_pwr_ctrl_pre</comment>
        </bits>
        <bits access="rw" name="aon_lp_hold" pos="2" rst="1">
          <comment>aon_lp_hold</comment>
        </bits>
        <bits access="rw" name="aon_lp_rst_ctrl" pos="1" rst="0">
          <comment>aon_lp_rst_ctrl</comment>
        </bits>
        <bits access="rw" name="aon_lp_clk_ctrl" pos="0" rst="0">
          <comment>aon_lp_clk_ctrl</comment>
        </bits>
      </reg>
      <reg name="pwrctrl_sw1_set" protect="rw">
        <bits access="rs" name="set" pos="4:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of PWRCTRL_SW
0:Invariance of corresponding bits
1:set 1 of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="pwrctrl_sw1_clr" protect="rw">
        <bits access="rc" name="clear" pos="4:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of PWRCTRL_SW1
0:Invariance of corresponding bits
1:clean corresponding bits</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_sysreg.xml">
    <module category="Bb_sysctrl" name="CP_SYSREG">
      <reg name="zsp_svtaddr" protect="rw">
        <bits access="rw" name="svtaddr" pos="31:8" rst="1048576">
          <comment>Interrupt vector entry address</comment>
        </bits>
      </reg>
      <reg name="mem_ema_cfg_zsp" protect="rw">
        <bits access="rw" name="rftpd_rmb" pos="29:26" rst="2">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rmeb" pos="25" rst="0">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rma" pos="24:21" rst="2">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rmea" pos="20" rst="0">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rfspd_rm" pos="19:16" rst="2">
          <comment>RASPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rfspd_rme" pos="15" rst="0">
          <comment>RASPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="raspu_rm" pos="14:11" rst="2">
          <comment>RASPU type EMA signal</comment>
        </bits>
        <bits access="rw" name="raspu_rme" pos="10" rst="0">
          <comment>RASPU type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rmb" pos="9:6" rst="2">
          <comment>RADPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rmeb" pos="5" rst="0">
          <comment>RADPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rma" pos="4:1" rst="2">
          <comment>RADPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rmea" pos="0" rst="0">
          <comment>RADPD type EMA signal</comment>
        </bits>
      </reg>
      <reg name="mem_ema_cfg_lte" protect="rw">
        <bits access="rw" name="rftpd_rmb" pos="29:26" rst="2">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rmeb" pos="25" rst="0">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rma" pos="24:21" rst="2">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rmea" pos="20" rst="0">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rfspd_rm" pos="19:16" rst="2">
          <comment>RASPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rfspd_rme" pos="15" rst="0">
          <comment>RASPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="raspu_rm" pos="14:11" rst="2">
          <comment>RASPU type EMA signal</comment>
        </bits>
        <bits access="rw" name="raspu_rme" pos="10" rst="0">
          <comment>RASPU type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rmb" pos="9:6" rst="2">
          <comment>RADPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rmeb" pos="5" rst="0">
          <comment>RADPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rma" pos="4:1" rst="2">
          <comment>RADPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rmea" pos="0" rst="0">
          <comment>RADPD type EMA signal</comment>
        </bits>
      </reg>
      <reg name="rom_ema_cfg_lte" protect="rw">
        <bits access="rw" name="rom_rma" pos="4:1" rst="2">
          <comment>ROM type EMA signal</comment>
        </bits>
        <bits access="rw" name="rom_rmea" pos="0" rst="0">
          <comment>ROM type EMA signal</comment>
        </bits>
      </reg>
      <reg name="mem_ema_cfg_bbsys" protect="rw">
        <bits access="rw" name="rftpd_rmb" pos="29:26" rst="2">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rmeb" pos="25" rst="0">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rma" pos="24:21" rst="2">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rftpd_rmea" pos="20" rst="0">
          <comment>RFTPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rfspd_rm" pos="19:16" rst="2">
          <comment>RASPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="rfspd_rme" pos="15" rst="0">
          <comment>RASPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="raspu_rm" pos="14:11" rst="2">
          <comment>RASPU type EMA signal</comment>
        </bits>
        <bits access="rw" name="raspu_rme" pos="10" rst="0">
          <comment>RASPU type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rmb" pos="9:6" rst="2">
          <comment>RADPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rmeb" pos="5" rst="0">
          <comment>RADPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rma" pos="4:1" rst="2">
          <comment>RADPD type EMA signal</comment>
        </bits>
        <bits access="rw" name="radpd_rmea" pos="0" rst="0">
          <comment>RADPD type EMA signal</comment>
        </bits>
      </reg>
      <reg name="zsp_qos" protect="rw">
        <bits access="rw" name="awqos_zsp_axidma" pos="23:20" rst="0">
          <comment>awqos_zsp_axidma</comment>
        </bits>
        <bits access="rw" name="arqos_zsp_axidma" pos="19:16" rst="0">
          <comment>arqos_zsp_axidma</comment>
        </bits>
        <bits access="rw" name="awqos_zsp_ibus" pos="15:12" rst="0">
          <comment>awqos_zsp_ibus</comment>
        </bits>
        <bits access="rw" name="arqos_zsp_ibus" pos="11:8" rst="0">
          <comment>arqos_zsp_ibus</comment>
        </bits>
        <bits access="rw" name="awqos_zsp_dbus" pos="7:4" rst="0">
          <comment>awqos_zsp_dbus</comment>
        </bits>
        <bits access="rw" name="arqos_zsp_dbus" pos="3:0" rst="0">
          <comment>arqos_zsp_dbus</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="flow_para" protect="rw">
        <bits access="rw" name="flowpara" pos="31:0" rst="0">
          <comment>Used to store and determine whether the pow on and Other relevant information is in a calibrated version</comment>
        </bits>
      </reg>
      <reg name="rf_sel" protect="rw">
        <bits access="rw" name="rfsel" pos="0" rst="0">
          <comment>RF scheme selection signal
0: use SOC RF scheme signal
1: use chip RF scheme</comment>
        </bits>
      </reg>
      <reg name="nb_lte_sel" protect="rw">
        <bits access="rw" name="nblte_sel" pos="0" rst="1">
          <comment>AD/DA data path select signal
1: LTE
0: NBIOT</comment>
        </bits>
      </reg>
      <reg name="ggenb_sel" protect="rw">
        <bits access="rw" name="gge_nb_sel" pos="0" rst="1">
          <comment>AD/DA data path select signal
0: NBIOT
1: GGE</comment>
        </bits>
      </reg>
      <reg name="rf_ana_26m_ctrl" protect="rw">
        <bits access="rw" name="enable_clk_26m_wcn" pos="8" rst="0">
          <comment>WCN 26M clock control:
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="enable_clk_26m_adi" pos="7" rst="1">
          <comment>ADI module 26M clock control:
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="enable_clk_26m_vad" pos="6" rst="0">
          <comment>VAD module 26M clock control:
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="muxsel_clk26m_aud2ad" pos="5" rst="0">
          <comment>AUD2AD module of 26M clock select:
0: AP_26M
1: after 17/16 clock operation</comment>
        </bits>
        <bits access="rw" name="enable_clk_26m_aud2ad" pos="4" rst="0">
          <comment>AUD2AD module of 26M clock switch:
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="muxsel_clk26m_audio" pos="3" rst="0">
          <comment>audio pll input Reference clock select:
0: AP_26M
1: after 17/16 clock operation</comment>
        </bits>
        <bits access="rw" name="enable_clk_26m_audio" pos="2" rst="0">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="enable_clk_26m_dsi" pos="1" rst="1">
          <comment>0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="enable_clk_26m_usb" pos="0" rst="1">
          <comment>0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="rf_ana_26m_ctrl_set" protect="rw">
        <bits access="rs" name="set" pos="8:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set corresponding bits of RF_ANA_26M_CTRL register:
0: Invariance of corresponding bits
1: set &quot;1&quot; of corresponding bits</comment>
        </bits>
      </reg>
      <reg name="rf_ana_26m_ctrl_clr" protect="rw">
        <bits access="rc" name="clear" pos="8:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clean corresponding bits of RF_ANA_26M_CTRL register:
0: Invariance of corresponding bits
1: clean corresponding bits</comment>
        </bits>
      </reg>
      <reg name="ddr_slp_ctrl_enable" protect="rw">
        <bits access="rw" name="enable" pos="0" rst="0">
          <comment>0: DISABLE
1: ENABLE
When AP power domain shut-down, this bit will be clear to &quot;0&quot;. Need software re-enable.</comment>
        </bits>
      </reg>
      <reg name="ddr_wakeup_force_en" protect="rw">
        <bits access="rw" name="enable" pos="0" rst="0">
          <comment>0: do not force ddr_slp_ctrl wakeup
1: force ddr_slp_ctrl wakeup</comment>
        </bits>
      </reg>
      <reg name="ddr_wakeup_force_ack" protect="r">
        <bits access="r" name="ack" pos="0" rst="0">
          <comment>force ddr_slp_ctrl wakeup done when &quot;1&quot;</comment>
        </bits>
      </reg>
      <reg name="ddr_slp_wait_number" protect="rw">
        <bits access="rw" name="n" pos="15:0" rst="0">
          <comment>after count N cycles,ddr_slp_ctrl begin sleep sequence when sleep condition meet.</comment>
        </bits>
      </reg>
      <reg name="lvds_spi_sel" protect="rw">
        <bits access="rw" name="sel" pos="0" rst="0">
          <comment>LVDS_SPI_SEL</comment>
        </bits>
      </reg>
      <reg name="monitor_lte_fint_sel" protect="rw">
        <bits access="rw" name="sel" pos="0" rst="0">
          <comment>0:  select idle_test[16] (LTE frame irq signal.)
1:  select lte_rbdp_tx[11];</comment>
        </bits>
      </reg>
      <reg name="rfmux_irq_sta" protect="rw">
        <bits access="rc" name="rfspi_conflict_irq" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Indicate RFSPI_CONFILICT_IRQ happened when &quot;1&quot;. Can be cleared by software writing &quot;1&quot;.</comment>
        </bits>
        <bits access="rc" name="txfifo_full_irq" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Indicate TXFIFO_FULL_IRQ happened when &quot;1&quot;. Can be cleared by software writing &quot;1&quot;.</comment>
        </bits>
      </reg>
      <reg name="apt_sel" protect="rw">
        <bits access="rw" name="sel" pos="0" rst="0">
          <comment>0:  select lte_up_rfctrl;
1:  select rf_gpio_o[9];</comment>
        </bits>
      </reg>
      <reg name="rfspi_mode_sel" protect="rw">
        <bits access="rw" name="sel" pos="0" rst="0">
          <comment>0:  3-wire mode;
1:  4-wire mode;</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="ggenb_sys_ctrl" protect="rw">
        <bits access="rw" name="ggenb_ctrl" pos="15:0" rst="0">
          <comment>General ctrl signal for GGENB.</comment>
        </bits>
      </reg>
      <reg name="a5_standbywfi_en" protect="rw">
        <bits access="rw" name="cp_a5_standby_en" pos="1" rst="0">
          <comment>1:enable
0:disable</comment>
        </bits>
        <bits access="rw" name="ap_a5_standby_en" pos="0" rst="0">
          <comment>1:enable
0:disable</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_monitor.xml">
    <module category="Bb_sysctrl" name="CP_MONITOR">
      <reg name="mon_sel0" protect="rw">
        <bits access="rw" name="mon_sel0" pos="10:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="mon_sel1" protect="rw">
        <bits access="rw" name="mon_sel1" pos="10:0" rst="1">
          <comment>1</comment>
        </bits>
      </reg>
      <reg name="mon_sel2" protect="rw">
        <bits access="rw" name="mon_sel2" pos="10:0" rst="2">
          <comment>2</comment>
        </bits>
      </reg>
      <reg name="mon_sel3" protect="rw">
        <bits access="rw" name="mon_sel3" pos="10:0" rst="3">
          <comment>3</comment>
        </bits>
      </reg>
      <reg name="mon_sel4" protect="rw">
        <bits access="rw" name="mon_sel4" pos="10:0" rst="4">
          <comment>4</comment>
        </bits>
      </reg>
      <reg name="mon_sel5" protect="rw">
        <bits access="rw" name="mon_sel5" pos="10:0" rst="5">
          <comment>5</comment>
        </bits>
      </reg>
      <reg name="mon_sel6" protect="rw">
        <bits access="rw" name="mon_sel6" pos="10:0" rst="6">
          <comment>6</comment>
        </bits>
      </reg>
      <reg name="mon_sel7" protect="rw">
        <bits access="rw" name="mon_sel7" pos="10:0" rst="7">
          <comment>7</comment>
        </bits>
      </reg>
      <reg name="mon_con0" protect="rw">
        <bits access="rw" name="mon_con0" pos="2:0" rst="0">
          <comment>monitor_o[0]
3'h0: 0
3'h1: 1
3'h2: 2
3'h3: 3
3'h4: 4
3'h5: 5
3'h6: 6
3'h7: 7</comment>
        </bits>
      </reg>
      <reg name="mon_con1" protect="rw">
        <bits access="rw" name="mon_con1" pos="2:0" rst="0">
          <comment>monitor_o[1]
3'h0: 0
3'h1: 1
3'h2: 2
3'h3: 3
3'h4: 4
3'h5: 5
3'h6: 6
3'h7: 7</comment>
        </bits>
      </reg>
      <reg name="mon_con2" protect="rw">
        <bits access="rw" name="mon_con2" pos="2:0" rst="0">
          <comment>monitor_o[2]
3'h0: 0
3'h1: 1
3'h2: 2
3'h3: 3
3'h4: 4
3'h5: 5
3'h6: 6
3'h7: 7</comment>
        </bits>
      </reg>
      <reg name="mon_con3" protect="rw">
        <bits access="rw" name="mon_con3" pos="2:0" rst="0">
          <comment>monitor_o[3]
3'h0: 0
3'h1: 1
3'h2: 2
3'h3: 3
3'h4: 4
3'h5: 5
3'h6: 6
3'h7: 7</comment>
        </bits>
      </reg>
      <reg name="mon_con4" protect="rw">
        <bits access="rw" name="mon_con4" pos="2:0" rst="0">
          <comment>monitor_o[4]
3'h0: 0
3'h1: 1
3'h2: 2
3'h3: 3
3'h4: 4
3'h5: 5
3'h6: 6
3'h7: 7</comment>
        </bits>
      </reg>
      <reg name="mon_con5" protect="rw">
        <bits access="rw" name="mon_con5" pos="2:0" rst="0">
          <comment>monitor_o[5]
3'h0: 0
3'h1: 1
3'h2: 2
3'h3: 3
3'h4: 4
3'h5: 5
3'h6: 6
3'h7: 7</comment>
        </bits>
      </reg>
      <reg name="mon_con6" protect="rw">
        <bits access="rw" name="mon_con6" pos="2:0" rst="0">
          <comment>monitor_o[6]
3'h0: 0
3'h1: 1
3'h2: 2
3'h3: 3
3'h4: 4
3'h5: 5
3'h6: 6
3'h7: 7</comment>
        </bits>
      </reg>
      <reg name="mon_con7" protect="rw">
        <bits access="rw" name="mon_con7" pos="2:0" rst="0">
          <comment>monitor_o[7]
3'h0: 0
3'h1: 1
3'h2: 2
3'h3: 3
3'h4: 4
3'h5: 5
3'h6: 6
3'h7: 7</comment>
        </bits>
      </reg>
      <reg name="mon_enable" protect="rw">
        <bits access="rw" name="monenable" pos="0" rst="0">
          <comment>1
0</comment>
        </bits>
      </reg>
      <reg name="monitor_o" protect="r">
        <bits access="r" name="monitorsignal" pos="7:0" rst="0">
          <comment>monitor output signal value.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_bb_wd.xml">
    <module category="Bb_sysctrl" name="CP_BB_WD">
      <reg name="wd_conf" protect="rw">
        <bits access="rw" name="prot_en" pos="9" rst="1">
          <comment>WD_PROT function enable
0: WD_PROT register function invalid
1: WD_PROT register function valid</comment>
        </bits>
        <bits access="rw" name="wd" pos="8" rst="1">
          <comment>0: timer mode
1: watchdog mode</comment>
        </bits>
        <bits access="rw" name="pvt" pos="7:4" rst="0">
          <comment>0000: no pre-div
0001: 1/2 pre-div
0010: 1/4 pre-div
0011: 1/8 pre-div
0100: 1/16 pre-div
0101: 1/32 pre-div
0110: 1/64 pre-div
0111: 1/128 pre-div
1000: 1/256 pre-div
others: no pre-div</comment>
        </bits>
        <bits access="rw" name="tr" pos="3" rst="0">
          <comment>0:  no influence to current timer value
1:  clear current timer value to zero</comment>
        </bits>
        <bits access="rw" name="ie" pos="2" rst="0">
          <comment>0:  interrupt disable
1:  interrupt enable</comment>
        </bits>
        <bits access="rw" name="ar" pos="1" rst="0">
          <comment>0:  keep the timer value when it reach the loaded value
1:  clear the timer value to zero when it reach the loaded value</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>0:  stop
1:  run
Note:  WD_LOAD1/2 register can not be writen when this bit is '1'.
This bit will be clear by hardware when reset signal generated in watchdog mode; and in timer mode, this bit will be clear by hardware when timer value reach the loaded value and 'AR' is set to '0'.</comment>
        </bits>
      </reg>
      <reg name="wd_prot" protect="rw">
        <bits access="rw" name="prot" pos="15:0" rst="0">
          <comment>WD_CONF and WD_LOAD1/2 register can be writen when this register value is 0xCCCC.</comment>
        </bits>
      </reg>
      <reg name="wd_load1" protect="rw">
        <bits access="rw" name="load_low" pos="31:0" rst="130000000">
          <comment>The low 32-bits of the load value.</comment>
        </bits>
      </reg>
      <reg name="wd_load2" protect="rw">
        <bits access="rw" name="load_high" pos="31:0" rst="0">
          <comment>The high 32-bits of the load value.</comment>
        </bits>
      </reg>
      <reg name="wd_value1" protect="r">
        <bits access="r" name="value_low" pos="31:0" rst="0">
          <comment>The low 32-bits of the timer value.</comment>
        </bits>
      </reg>
      <reg name="wd_value2" protect="r">
        <bits access="r" name="value_high" pos="31:0" rst="0">
          <comment>The high 32-bits of the timer value.</comment>
        </bits>
      </reg>
      <reg name="wd_cmd" protect="w">
        <bits access="w" name="cmd" pos="15:0" rst="0">
          <comment>Write orderly 0xAAAA and 0x5555 to convert to timer mode from watchdog mode.
Write orderly 0xAAAA and 0x4444 to convert to watchdog mode from timer mode.
Write 0xBBBB to &quot;feed dog&quot; in watchdog mode.</comment>
        </bits>
      </reg>
      <reg name="wd_div_conf" protect="rw">
        <bits access="rw" name="en" pos="16" rst="0">
          <comment>0:  disable timer divider
1:  enable timer divider</comment>
        </bits>
        <bits access="rw" name="div" pos="15:0" rst="25">
          <comment>f= FuncClk/(DIV+1)</comment>
        </bits>
      </reg>
      <reg name="wd_div_count" protect="rw">
        <bits access="rc" name="count" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          The counter value of timer divider.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_zsp_irqh.xml">
    <module category="ZSP_SYS" name="CP_ZSP_IRQH">
      <reg name="inth_itr0" protect="rw">
        <bits access="rc" name="it" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          Interrupt source flag(0-31)
0:  no interrupt
1:  capture interrupt</comment>
        </bits>
      </reg>
      <reg name="inth_itr1" protect="rw">
        <bits access="rc" name="it" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          Interrupt source flag(32-63)
0:  no interrupt
1:  capture interrupt</comment>
        </bits>
      </reg>
      <reg name="inth_mir0" protect="rw">
        <bits access="rw" name="im" pos="31:0" rst="4294967295">
          <comment>Interrupt mask bit (0-30)
0:  open interrupt
1:  mask interrupt</comment>
        </bits>
      </reg>
      <reg name="inth_mir1" protect="rw">
        <bits access="rw" name="im" pos="31:0" rst="4294967295">
          <comment>Interrupt mask bit (32-63)
0:  open interrupt
1:  mask interrupt</comment>
        </bits>
      </reg>
      <reg name="inth_mirs0" protect="rw">
        <bits access="rs" name="ims" pos="31:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          sets the corresponding bit in the mask register (0-31)
0:  the corresponding bit in the mask register do not change.
1:  sets the corresponding bit in the mask register to '1'.</comment>
        </bits>
      </reg>
      <reg name="inth_mirs1" protect="rw">
        <bits access="rs" name="ims" pos="31:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          sets the corresponding bit in the mask register(32-64)
0:  the corresponding bit in the mask register do not change.
1:  sets the corresponding bit in the mask register to '1'.</comment>
        </bits>
      </reg>
      <reg name="inth_mirc0" protect="rw">
        <bits access="rc" name="ims" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clears the corresponding bit in the mask register(0-31)
0:  the corresponding bit in the mask register do not change
1:  Writing '1' clears the corresponding bit in the mask register to '0'.</comment>
        </bits>
      </reg>
      <reg name="inth_mirc1" protect="rw">
        <bits access="rc" name="ims" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clears the corresponding bit in the mask register(32-64)
0:  the corresponding bit in the mask register do not change
1:  Writing '1' clears the corresponding bit in the mask register to '0'.</comment>
        </bits>
      </reg>
      <reg name="inth_gmir" protect="rw">
        <bits access="rw" name="gim" pos="0" rst="0">
          <comment>Global interrupt enable BIT
0:  Interrupt is decided by corresponding mask bit
1:  Maks all Interrupt</comment>
        </bits>
      </reg>
      <reg name="inth_sel0" protect="rw">
        <bits access="rw" name="fiq_sel" pos="31:0" rst="0">
          <comment>FIQ OR IRQ Select (0-31)
0:  corresponding interrupt send to arm through IRQ
1:  corresponding interrupt send to arm through FIR</comment>
        </bits>
      </reg>
      <reg name="inth_sel1" protect="rw">
        <bits access="rw" name="fiq_sel" pos="31:0" rst="0">
          <comment>FIQ OR IRQ Select (32-63)
0:  corresponding interrupt send to arm through IRQ
1:  corresponding interrupt send to arm through FIR</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="irq_sta0" protect="r">
        <bits access="r" name="irq_s" pos="31:0" rst="0">
          <comment>IRQ status bit(0-31)
0:  corresponding interrupt source no interrupt
1:   corresponding interrupt source no interrupt send interrupt to arm through IRQ</comment>
        </bits>
      </reg>
      <reg name="irq_sta1" protect="r">
        <bits access="r" name="irq_s" pos="31:0" rst="0">
          <comment>IRQ status bit(32-63)
0:  corresponding interrupt source no interrupt
1:   corresponding interrupt source no interrupt send interrupt to arm through IRQ</comment>
        </bits>
      </reg>
      <reg name="irq_sir" protect="r">
        <bits access="r" name="is" pos="6:0" rst="127">
          <comment>IRQ interrupt source code
0000000:  IRQ0
0000001:  IRQ1
0000010:  IRQ2
......
0111111:  IRQ63</comment>
        </bits>
      </reg>
      <reg name="irq_ctrl" protect="w">
        <bits access="w" name="clr" pos="0" rst="0">
          <comment>Clear interrupt status bit
0:  no operation
1:  clear corresponding bit of IRQ_STA and ITR,at the same time change irq from high to low</comment>
        </bits>
      </reg>
      <reg name="fiq_sta0" protect="r">
        <bits access="r" name="fiq_s" pos="31:0" rst="0">
          <comment>FIQ status bit(0-31)
0:  corresponding interrupt source no interrupt
1:   corresponding interrupt source no interrupt send interrupt to arm through Fiq</comment>
        </bits>
      </reg>
      <reg name="fiq_sta1" protect="r">
        <bits access="r" name="fiq_s" pos="31:0" rst="0">
          <comment>FIQ status bit(32-63)
0:  corresponding interrupt source no interrupt
1:   corresponding interrupt source no interrupt send interrupt to arm through Fiq</comment>
        </bits>
      </reg>
      <reg name="fiq_sir" protect="r">
        <bits access="r" name="fs" pos="6:0" rst="127">
          <comment>fiq interrupt source code
0000000:  FIQ0
0000001:  FIQ1
0000010:  FIQ2
......
0111111:  FIQ63</comment>
        </bits>
      </reg>
      <reg name="fiq_ctrl" protect="rw">
        <bits access="rw" name="clr" pos="0" rst="0">
          <comment>Clear interrupt status bit
0:  no operation
1:  clear corresponding bit of IRQ_STA and ITR,at the same time change irq from high to low</comment>
        </bits>
      </reg>
      <reg name="vicprio0" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio1" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio2" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio3" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio4" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio5" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio6" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio7" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio8" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio9" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio10" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio11" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio12" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio13" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio14" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio15" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio16" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio17" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio18" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio19" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio20" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio21" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio22" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio23" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio24" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio25" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio26" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio27" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio28" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio29" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio30" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio31" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio32" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio33" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio34" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio35" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio36" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio37" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio38" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio39" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0: Interrupt prio 0
1: Interrupt prio 1
......
7: Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio40" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio41" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio42" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio43" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio44" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio45" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio46" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio47" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio48" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio49" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio50" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio51" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio52" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio53" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio54" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio55" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio56" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio57" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio58" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio59" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio60" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio61" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio62" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
      <reg name="vicprio63" protect="rw">
        <bits access="rw" name="vic_pri" pos="2:0" rst="7">
          <comment>Interrupt prio
0:  Interrupt prio 0
1:  Interrupt prio 1
......
7:  Interrupt prio 7
Prio 0 is corrosponed to the highist prio</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_zsp_axidma.xml">
    <module category="ZSP_SYS" name="CP_ZSP_AXIDMA">
      <reg name="axidma_conf" protect="rw">
        <bits access="rw" name="gen_reg_secuirty_en" pos="6" rst="1">
          <comment>general used register security visit enable
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="resp_err_stop_en" pos="5" rst="0">
          <comment>response error stop function enable
0enable
1disable</comment>
        </bits>
        <bits access="rw" name="outstand" pos="4:3" rst="2">
          <comment>the number of outstanding that can be send out
0: 2
1: 3
2: 4</comment>
        </bits>
        <bits access="rw" name="priority" pos="2" rst="0">
          <comment>multe-channel transport priority mode control
0: there is no priority in the channels, using polling to DMA data
1: smaller channel number has high-priority.high-priority move data before low-priority channels</comment>
        </bits>
        <bits access="rw" name="stop_ie" pos="1" rst="0">
          <comment>interrupt control bit
0: no interruption occurs when all logical channels finish
1: interruption occurs when all logical channels finish</comment>
        </bits>
        <bits access="rw" name="stop" pos="0" rst="0">
          <comment>the control bit of logical channel transport finish
0: don't stop all the channel,or automatically clear after setting
1: stop all channel.the current transmission is stopped.the start bits of all channels are cleared</comment>
        </bits>
      </reg>
      <reg name="axidma_delay" protect="rw">
        <bits access="rw" name="delay" pos="15:0" rst="0">
          <comment>in the non-priority mode, the time interval between two COUNTP transmission. Take the system clock as the criterion to avoid AXIDMA long-term use of the bus.</comment>
        </bits>
      </reg>
      <reg name="axidma_status" protect="r">
        <bits access="r" name="stop_status" pos="4" rst="0">
          <comment>stop status
0: not finish
1: finish</comment>
        </bits>
        <bits access="r" name="ch_num" pos="3:0" rst="15">
          <comment>the channel number of the final transmission
0000: channel 0 just finished the transmission
0001: channel 1 just finished the transmission
0010: channel 2 just finished the transmission
1011: channel 11 just finished the transmission
others: nonentity</comment>
        </bits>
      </reg>
      <reg name="axidma_irq_stat" protect="r">
        <bits access="r" name="rst_fin_irq" pos="12" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="r" name="ch11_irq" pos="11" rst="0">
          <comment>channel 11 interrupts state
0: the channel 11 has not been interrupted, or the interrupt bit has been cleared
1: channel 11 is interrupted</comment>
        </bits>
        <bits access="r" name="ch10_irq" pos="10" rst="0">
          <comment>channel 10 interrupts state
0: the channel 10 has not been interrupted, or the interrupt bit has been cleared
1: channel 10 is interrupted</comment>
        </bits>
        <bits access="r" name="ch9_irq" pos="9" rst="0">
          <comment>channel 9 interrupts state
0: the channel 9 has not been interrupted, or the interrupt bit has been cleared
1: channel 9 is interrupted</comment>
        </bits>
        <bits access="r" name="ch8_irq" pos="8" rst="0">
          <comment>channel 8 interrupts state
0: the channel 8 has not been interrupted, or the interrupt bit has been cleared
1: channel 8 is interrupted</comment>
        </bits>
        <bits access="r" name="ch7_irq" pos="7" rst="0">
          <comment>channel 7 interrupts state
0: the channel 7 has not been interrupted, or the interrupt bit has been cleared
1: channel 7 is interrupted</comment>
        </bits>
        <bits access="r" name="ch6_irq" pos="6" rst="0">
          <comment>channel 6 interrupts state
0: the channel 6 has not been interrupted, or the interrupt bit has been cleared
1: channel 6 is interrupted</comment>
        </bits>
        <bits access="r" name="ch5_irq" pos="5" rst="0">
          <comment>channel 5 interrupts state
0: the channel 5 has not been interrupted, or the interrupt bit has been cleared
1: channel 5 is interrupted</comment>
        </bits>
        <bits access="r" name="ch4_irq" pos="4" rst="0">
          <comment>channel 4 interrupts state
0: the channel 4 has not been interrupted, or the interrupt bit has been cleared
1: channel 4 is interrupted</comment>
        </bits>
        <bits access="r" name="ch3_irq" pos="3" rst="0">
          <comment>channel 3 interrupts state
0: the channel 3 has not been interrupted, or the interrupt bit has been cleared
1: channel 3 is interrupted</comment>
        </bits>
        <bits access="r" name="ch2_irq" pos="2" rst="0">
          <comment>channel 2 interrupts state
0: the channel 2 has not been interrupted, or the interrupt bit has been cleared
1: channel 2 is interrupted</comment>
        </bits>
        <bits access="r" name="ch1_irq" pos="1" rst="0">
          <comment>channel 1 interrupts state
0: the channel 1 has not been interrupted, or the interrupt bit has been cleared
1: channel 1 is interrupted</comment>
        </bits>
        <bits access="r" name="ch0_irq" pos="0" rst="0">
          <comment>channel 0 interrupts state
0: the channel 0 has not been interrupted, or the interrupt bit has been cleared
1: channel 0 is interrupted</comment>
        </bits>
      </reg>
      <reg name="axidma_arm_req_stat" protect="r">
        <bits access="r" name="irq23" pos="23" rst="0">
          <comment>state of IRQ 23 generate requests of moving data
0: IRQ 23 does not generate requests of moving data
1: IRQ 23 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq22" pos="22" rst="0">
          <comment>state of IRQ 22 generate requests of moving data
0: IRQ 22 does not generate requests of moving data
1: IRQ 22 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq21" pos="21" rst="0">
          <comment>state of IRQ 21 generate requests of moving data
0: IRQ 21 does not generate requests of moving data
1: IRQ 21 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq20" pos="20" rst="0">
          <comment>state of IRQ 20 generate requests of moving data
0: IRQ 20 does not generate requests of moving data
1: IRQ 20 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq19" pos="19" rst="0">
          <comment>state of IRQ 19 generate requests of moving data
0: IRQ 19 does not generate requests of moving data
1: IRQ 19 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq18" pos="18" rst="0">
          <comment>state of IRQ 18 generate requests of moving data
0: IRQ 18 does not generate requests of moving data
1: IRQ 18 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq17" pos="17" rst="0">
          <comment>state of IRQ 17 generate requests of moving data
0: IRQ 17 does not generate requests of moving data
1: IRQ 17 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq16" pos="16" rst="0">
          <comment>state of IRQ 16 generate requests of moving data
0: IRQ 16 does not generate requests of moving data
1: IRQ 16 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq15" pos="15" rst="0">
          <comment>state of IRQ 15 generate requests of moving data
0: IRQ 15 does not generate requests of moving data
1: IRQ 15 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq14" pos="14" rst="0">
          <comment>state of IRQ 14 generate requests of moving data
0: IRQ 14 does not generate requests of moving data
1: IRQ 14 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq13" pos="13" rst="0">
          <comment>state of IRQ 13 generate requests of moving data
0: IRQ 13 does not generate requests of moving data
1: IRQ 13 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq12" pos="12" rst="0">
          <comment>state of IRQ 12 generate requests of moving data
0: IRQ 12 does not generate requests of moving data
1: IRQ 12 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq11" pos="11" rst="0">
          <comment>state of IRQ 11 generate requests of moving data
0: IRQ 11 does not generate requests of moving data
1: IRQ 11 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq10" pos="10" rst="0">
          <comment>state of IRQ 10 generate requests of moving data
0: IRQ 10 does not generate requests of moving data
1: IRQ 10 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq9" pos="9" rst="0">
          <comment>state of IRQ 9 generate requests of moving data
0: IRQ 9 does not generate requests of moving data
1: IRQ 7 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq8" pos="8" rst="0">
          <comment>state of IRQ 8 generate requests of moving data
0: IRQ 8 does not generate requests of moving data
1: IRQ 8 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq7" pos="7" rst="0">
          <comment>state of IRQ 7 generate requests of moving data
0: IRQ 7 does not generate requests of moving data
1: IRQ 7 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq6" pos="6" rst="0">
          <comment>state of IRQ 6 generate requests of moving data
0: IRQ 6 does not generate requests of moving data
1: IRQ 6 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq5" pos="5" rst="0">
          <comment>state of IRQ 5 generate requests of moving data
0: IRQ 5 does not generate requests of moving data
1: IRQ 5 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq4" pos="4" rst="0">
          <comment>state of IRQ 4 generate requests of moving data
0: IRQ 4 does not generate requests of moving data
1: IRQ 4 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq3" pos="3" rst="0">
          <comment>state of IRQ 3 generate requests of moving data
0: IRQ 3 does not generate requests of moving data
1: IRQ 3 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq2" pos="2" rst="0">
          <comment>state of IRQ 2 generate requests of moving data
0: IRQ 2 does not generate requests of moving data
1: IRQ 2 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq1" pos="1" rst="0">
          <comment>state of IRQ 1 generate requests of moving data
0: IRQ 1 does not generate requests of moving data
1: IRQ 1 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="irq0" pos="0" rst="0">
          <comment>state of IRQ 0 generate requests of moving data
0: IRQ 0 does not generate requests of moving data
1: IRQ 0 generate requests of moving data</comment>
        </bits>
      </reg>
      <reg name="axidma_arm_ack_stat" protect="r">
        <bits access="r" name="ack23" pos="23" rst="0">
          <comment>state of ACK 23 generate requests of moving data
0: ACK 23 does not generate requests of moving data
1: ACK 23 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack22" pos="22" rst="0">
          <comment>state of ACK 22 generate requests of moving data
0: ACK 22 does not generate requests of moving data
1: ACK 22 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack21" pos="21" rst="0">
          <comment>state of ACK 21 generate requests of moving data
0: ACK 21 does not generate requests of moving data
1: ACK 21 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack20" pos="20" rst="0">
          <comment>state of ACK 20 generate requests of moving data
0: ACK 20 does not generate requests of moving data
1: ACK 20 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack19" pos="19" rst="0">
          <comment>state of ACK 19 generate requests of moving data
0: ACK 19 does not generate requests of moving data
1: ACK 19 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack18" pos="18" rst="0">
          <comment>state of ACK 18 generate requests of moving data
0: ACK 18 does not generate requests of moving data
1: ACK 18 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack17" pos="17" rst="0">
          <comment>state of ACK 17 generate requests of moving data
0: ACK 17 does not generate requests of moving data
1: ACK 17 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack16" pos="16" rst="0">
          <comment>state of ACK 16 generate requests of moving data
0: ACK 16 does not generate requests of moving data
1: ACK 16 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack15" pos="15" rst="0">
          <comment>state of ACK 15 generate requests of moving data
0: ACK 15 does not generate requests of moving data
1: ACK 15 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack14" pos="14" rst="0">
          <comment>state of ACK 14 generate requests of moving data
0: ACK 14 does not generate requests of moving data
1: ACK 14 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack13" pos="13" rst="0">
          <comment>state of ACK 13 generate requests of moving data
0: ACK 13 does not generate requests of moving data
1: ACK 13 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack12" pos="12" rst="0">
          <comment>state of ACK 12 generate requests of moving data
0: ACK 12 does not generate requests of moving data
1: ACK 12 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack11" pos="11" rst="0">
          <comment>state of ACK 11 generate requests of moving data
0: ACK 11 does not generate requests of moving data
1: ACK 11 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack10" pos="10" rst="0">
          <comment>state of ACK 10 generate requests of moving data
0: ACK 10 does not generate requests of moving data
1: ACK 10 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack9" pos="9" rst="0">
          <comment>state of ACK 9 generate requests of moving data
0: ACK 9 does not generate requests of moving data
1: ACK 7 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack8" pos="8" rst="0">
          <comment>state of ACK 8 generate requests of moving data
0: ACK 8 does not generate requests of moving data
1: ACK 8 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack7" pos="7" rst="0">
          <comment>state of ACK 7 generate requests of moving data
0: ACK 7 does not generate requests of moving data
1: ACK 7 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack6" pos="6" rst="0">
          <comment>state of ACK 6 generate requests of moving data
0: ACK 6 does not generate requests of moving data
1: ACK 6 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack5" pos="5" rst="0">
          <comment>state of ACK 5 generate requests of moving data
0: ACK 5 does not generate requests of moving data
1: ACK 5 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack4" pos="4" rst="0">
          <comment>state of ACK 4 generate requests of moving data
0: ACK 4 does not generate requests of moving data
1: ACK 4 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack3" pos="3" rst="0">
          <comment>state of ACK 3 generate requests of moving data
0: ACK 3 does not generate requests of moving data
1: ACK 3 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack2" pos="2" rst="0">
          <comment>state of ACK 2 generate requests of moving data
0: ACK 2 does not generate requests of moving data
1: ACK 2 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack1" pos="1" rst="0">
          <comment>state of ACK 1 generate requests of moving data
0: ACK 1 does not generate requests of moving data
1: ACK 1 generate requests of moving data</comment>
        </bits>
        <bits access="r" name="ack0" pos="0" rst="0">
          <comment>state of ACK 0 generate requests of moving data
0: ACK 0 does not generate requests of moving data
1: ACK 0 generate requests of moving data</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="axidma_ch_irq_distr" protect="rw">
        <bits access="rw" name="ch11_irq_en0" pos="11" rst="0">
          <comment>channel 11 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch10_irq_en0" pos="10" rst="0">
          <comment>channel 10 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch9_irq_en0" pos="9" rst="0">
          <comment>channel 9 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch8_irq_en0" pos="8" rst="0">
          <comment>channel 8 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch7_irq_en0" pos="7" rst="0">
          <comment>channel 7 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch6_irq_en0" pos="6" rst="0">
          <comment>channel 6 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch5_irq_en0" pos="5" rst="0">
          <comment>channel 5 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch4_irq_en0" pos="4" rst="0">
          <comment>channel 4 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch3_irq_en0" pos="3" rst="0">
          <comment>channel 3 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch2_irq_en0" pos="2" rst="0">
          <comment>channel 2 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch1_irq_en0" pos="1" rst="0">
          <comment>channel 1 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
        <bits access="rw" name="ch0_irq_en0" pos="0" rst="0">
          <comment>channel 0 interrupt allocation bit
0: the interrupt of the channel is output to the dma_irq interruption
1: the interrupt of the channel is output to the dma_irq1 interruption</comment>
        </bits>
      </reg>
      <hole size="224"/>
      <reg name="axidma_c0_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="0">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="0">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c0_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c1_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="1">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="1">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c1_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c2_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="2">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="2">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c2_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c3_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="3">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="3">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c3_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c4_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="4">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="4">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c4_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c5_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="5">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="5">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c5_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c6_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="6">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="6">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c6_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c7_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="7">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="7">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c7_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c8_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="8">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="8">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c8_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c9_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="9">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="9">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c9_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c10_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="10">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="10">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c10_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="axidma_c11_conf" protect="rw">
        <bits access="rw" name="err_int_en" pos="15" rst="0">
          <comment>response error interrupt enable
0disable
1enable</comment>
        </bits>
        <bits access="rw" name="security_en" pos="14" rst="1">
          <comment>security visit
0security
1unsecurity</comment>
        </bits>
        <bits access="rw" name="daddr_turnaround" pos="13" rst="0">
          <comment>after moving a COUNTP,the DADDR is automatically returned to the original destination addr
0: the destination addr does not automatically ring back
1: the destination addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="saddr_turnaround" pos="12" rst="0">
          <comment>after moving a COUNTP,the SADDR is automatically returned to initial source addr
0: the source addr does not automatically ring back
1: the source addr automatically ring back</comment>
        </bits>
        <bits access="rw" name="count_sel" pos="10" rst="0">
          <comment>the length of moving data in one interrupt in interrupted mode
0:  move a countp
1: move all count</comment>
        </bits>
        <bits access="rw" name="force_trans" pos="8" rst="0">
          <comment>mandatory transmission control bit
0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared.
1: force a transmission without interruption in interrupted mode.</comment>
        </bits>
        <bits access="rw" name="daddr_fix" pos="7" rst="0">
          <comment>fixed destination addr control bit
0: destination addr can be incremented by different data types during transmission
1: the destination addr is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="saddr_fix" pos="6" rst="0">
          <comment>fixed source addr control bit
0: source addr can be incremented by different data types during transmission
1: the source add is fixed during transmission</comment>
        </bits>
        <bits access="rw" name="irq_t" pos="5" rst="0">
          <comment>control bit of each transmission interruption
0: each transmission does not produce an interrupt signal
1: each transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="irq_f" pos="4" rst="1">
          <comment>control bit of whole transmission interruption
0: whole transmission does not produce an interrupt signal
1: whole transmission prodece an interrupt signal</comment>
        </bits>
        <bits access="rw" name="syn_irq" pos="3" rst="0">
          <comment>control bit of synchronous interrupt trigger mode
0: this channel is in normal transmission mode
1: this channel is in sync interrupt trigger mode</comment>
        </bits>
        <bits access="rw" name="data_type" pos="2:1" rst="0">
          <comment>data types
00: Byte (8 bits)
01: Half Word (16 bits)
10: Word (32 bits)
11: DWord (64 bits)</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>start control bit
0: stop the transmission of this channel
1: start the transmission of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_map" protect="rw">
        <bits access="rw" name="ack_map" pos="12:8" rst="11">
          <comment>this channel corresponds to the ACK signal that is triggered
00000: ACK0
00001: ACK1
00010: ACK2
10111: ACK23</comment>
        </bits>
        <bits access="rw" name="req_source" pos="4:0" rst="11">
          <comment>the source of interrupt trigger for this channel
00000: IRQ0 trigger transmission
00001: IRQ1 trigger transmission
00010: IRQ2 trigger transmission
01111: IRQ15 trigger transmission
10111: IRQ23trigger transmission</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_saddr" protect="rw">
        <bits access="rw" name="s_addr" pos="31:0" rst="0">
          <comment>the source addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_daddr" protect="rw">
        <bits access="rw" name="d_addr" pos="31:0" rst="0">
          <comment>the destination addr of this channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_count" protect="rw">
        <bits access="rw" name="count" pos="23:0" rst="0">
          <comment>The total length of the transmitted data is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_countp" protect="rw">
        <bits access="rw" name="countp" pos="15:0" rst="0">
          <comment>the data length per transmission is measured in byte</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_status" protect="rw">
        <bits access="rc" name="resp_err_int" pos="26" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error interrupt flag
0unset
1set</comment>
        </bits>
        <bits access="rc" name="resp_err" pos="25" rst="0">
          <comment>bit type is changed from w1c to rc.
          response error status
0unset
1set</comment>
        </bits>
        <bits access="rc" name="sg_suspend_sta" pos="24" rst="0">
          <comment>bit type is changed from w1c to rc.
          data linked list is paused
0: not paused
1:  paused</comment>
        </bits>
        <bits access="rc" name="sg_finish_sta" pos="23" rst="0">
          <comment>bit type is changed from w1c to rc.
          the linked list is completed
0: not completed
1: completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_sta" pos="22" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_sta" pos="21" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNT transmission completion indication
0: COUNT is not completed
1: COUNT is completed</comment>
        </bits>
        <bits access="rc" name="sg_suspend_int" pos="20" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather pause</comment>
        </bits>
        <bits access="rc" name="sg_count" pos="19:4" rst="0">
          <comment>bit type is changed from w1c to rc.
          the number of scatter-gather transfers completed
0x0000: 0
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rc" name="sg_finish_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather transmission completion
0: scatter-gather is not completed
1: scatter-gather is completed</comment>
        </bits>
        <bits access="rc" name="countp_finish_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          COUNTP transmission completion indication
0: COUNTP is not completed
1: COUNTP is completed</comment>
        </bits>
        <bits access="rc" name="count_finish_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          the whole transmission completion indication
0: the whole transmission is not completed
1: the whole transmission is completed</comment>
        </bits>
        <bits access="rc" name="run" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          the channel runs state
0: IDLE
1: TRANS</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_sgaddr" protect="rw">
        <bits access="rw" name="sg_addr" pos="31:0" rst="0">
          <comment>first addr of the structural body</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_sgconf" protect="rw">
        <bits access="rw" name="sg_num" pos="19:4" rst="0">
          <comment>scatter-gather transmission frequency
0x0: unlimited limit
0xFFFF: 65535 times</comment>
        </bits>
        <bits access="rw" name="desc_rd_ctrl" pos="3" rst="0">
          <comment>linked table read control
0: after the data is moved,the linked list isread and no descriptor_req are required
1: descriptor_req is needed to read the linked list</comment>
        </bits>
        <bits access="rw" name="sg_suspend_ie" pos="2" rst="0">
          <comment>scatter-gather pause interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sg_finish_ie" pos="1" rst="0">
          <comment>scatter-gather complete interrupt enable
0: disable
1: enable</comment>
        </bits>
        <bits access="rc" name="sg_en" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          scatter-gather function enable
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_set" protect="rw">
        <bits access="rw" name="run_set" pos="0" rst="0">
          <comment>channel runs position
0: the running bit of the channel does not change
1: set the running bit of the channel</comment>
        </bits>
      </reg>
      <reg name="axidma_c11_clr" protect="rw">
        <bits access="rw" name="run_clr" pos="0" rst="0">
          <comment>clear the running bit of channel
0: the running bit of the channel does not change
1: clear the running bit of the channel</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_zsp_aud_dft.xml">
    <module category="ZSP_SYS" name="CP_ZSP_AUD_DFT">
      <reg name="dft_params" protect="rw">
        <bits access="rw" name="rsv_registers" pos="31:21" rst="0">
          <comment>reserved fields of DFT</comment>
        </bits>
        <bits access="rw" name="dft_zero_insert" pos="20" rst="0">
          <comment>1: HW insert zeros for imag part, 0: SW provide zeros</comment>
        </bits>
        <bits access="rw" name="dft_dma_out_intr_mask" pos="19" rst="0">
          <comment>1: mask DMA out intr; 0:not mask DMA out intr</comment>
        </bits>
        <bits access="rw" name="dft_calc_intr_mask" pos="18" rst="0">
          <comment>1: mask Calc intr; 0:not mask Calc intr</comment>
        </bits>
        <bits access="rw" name="dft_dma_in_intr_mask" pos="17" rst="0">
          <comment>1: mask DMA in intr; 0:not mask DMA in intr</comment>
        </bits>
        <bits access="rw" name="dft_iq_swap" pos="16" rst="0">
          <comment>1:iq swap; 0:iq not swap</comment>
        </bits>
        <bits access="rw" name="dft_fft_ifft" pos="15" rst="1">
          <comment>1:fft; 0:ifft</comment>
        </bits>
        <bits access="rw" name="dft_force_clken_enable" pos="14" rst="0">
          <comment>force clock gating enable</comment>
        </bits>
        <bits access="rw" name="dft_ram_base_addr" pos="13:4" rst="1023">
          <comment>base address of ram in dft</comment>
        </bits>
        <bits access="rw" name="n_index" pos="3:0" rst="0">
          <comment>index of DFT  N length</comment>
        </bits>
      </reg>
      <reg name="dft_general" protect="rw">
        <bits access="rs" name="dft_err_stat_clr" pos="4" rst="0">
          <comment>bit type is changed from w1s to rs.
          write clear pulse for DFT error status, read in err status</comment>
        </bits>
        <bits access="rs" name="dft_dma_out_intr_clr" pos="3" rst="0">
          <comment>bit type is changed from w1s to rs.
          write clear pulse for DFT dma out interrupts, read in dma out interrupt source before mask</comment>
        </bits>
        <bits access="rs" name="dft_calc_intr_clr" pos="2" rst="0">
          <comment>bit type is changed from w1s to rs.
          write clear pulse for DFT calc interrupts, read in calc interrupt source before mask</comment>
        </bits>
        <bits access="rs" name="dft_dma_in_intr_clr" pos="1" rst="0">
          <comment>bit type is changed from w1s to rs.
          write clear pulse for DFT dma in interrupts,  read in dma in interrupt source before mask</comment>
        </bits>
        <bits access="rs" name="dft_start" pos="0" rst="0">
          <comment>bit type is changed from w1s to rs.
          write start trigger pulse of DFT, which will do dma rx, and read in dma rx request status</comment>
        </bits>
      </reg>
      <reg name="dft_report" protect="r">
        <bits access="r" name="dft_dma_out_intr_source" pos="13" rst="0">
          <comment>1: interrupt source in dma out; 0 : no interrupt, read interrupt after mask</comment>
        </bits>
        <bits access="r" name="dft_calc_intr_source" pos="12" rst="0">
          <comment>1: interrupt source in calc; 0 : no interrupt, read interrupt after mask</comment>
        </bits>
        <bits access="r" name="dft_dma_in_intr_source" pos="11" rst="0">
          <comment>1: interrupt source in dma in; 0 : no interrupt, read interrupt after mask</comment>
        </bits>
        <bits access="r" name="dft_err_stat" pos="10" rst="0">
          <comment>DFT error status report upon interrupt gen, cleared via DFT_err_stat_clr set</comment>
        </bits>
        <bits access="r" name="dft_sm_stat" pos="9:0" rst="0">
          <comment>DFT state machine status report</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_zsp_busmon.xml">
    <module category="ZSP_SYS" name="CP_ZSP_BUSMON">
      <reg name="mon_ctrl" protect="rw">
        <bits access="rw" name="busmon_ctrl" pos="0" rst="0">
          <comment>Monitor
0
1
:BUS Monitor</comment>
        </bits>
      </reg>
      <reg name="mon_conf" protect="rw">
        <bits access="rw" name="mon_ext_addr_en" pos="9" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="busy_en" pos="8" rst="0">
          <comment>BUSY
1
0</comment>
        </bits>
        <bits access="rw" name="rbusy_en" pos="7" rst="0">
          <comment>RBUSY
1
0</comment>
        </bits>
        <bits access="rw" name="wbusy_en" pos="6" rst="0">
          <comment>WBUSY
1
0</comment>
        </bits>
        <bits access="rw" name="mon_in_addr_en" pos="5" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="mon_num_en" pos="4" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="mon_cont_en" pos="3" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="mon_time_en" pos="2" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="mon_lock_en" pos="1" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="gint_en" pos="0" rst="0">
          <comment>0
1
MON_M0_ADDR_WIDIDDDR0x0-0x1fff_ffffDDR</comment>
        </bits>
      </reg>
      <reg name="mon_time" protect="rw">
        <bits access="rw" name="busmon_time" pos="31:0" rst="4294967295">
          <comment>,
PCLK</comment>
        </bits>
      </reg>
      <reg name="mon_cont" protect="rw">
        <bits access="rw" name="busmon_cnt" pos="31:0" rst="4294967295">
          <comment>MON_NUM_EN,MASTER</comment>
        </bits>
      </reg>
      <reg name="mon_int_en" protect="rw">
        <bits access="rw" name="addr_int_en" pos="3" rst="0">
          <comment>MASTER0
0
1</comment>
        </bits>
        <bits access="rw" name="num_int_en" pos="2" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="timer_int_en" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="lock_int_en" pos="0" rst="0">
          <comment>LOCK
0
1</comment>
        </bits>
      </reg>
      <reg name="mon_int_flag" protect="rw">
        <bits access="rc" name="timer_int" pos="17" rst="0">
          <comment>bit type is changed from w1c to rc.
0
1</comment>
        </bits>
        <bits access="rc" name="addr_int" pos="16" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER0
0
1</comment>
        </bits>
        <bits access="rc" name="m4_rnum_int" pos="15" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER4
0
1</comment>
        </bits>
        <bits access="rc" name="m4_wnum_int" pos="14" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER4
0
1</comment>
        </bits>
        <bits access="rc" name="m3_rnum_int" pos="13" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER3
0
1</comment>
        </bits>
        <bits access="rc" name="m3_wnum_int" pos="12" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER3
0
1</comment>
        </bits>
        <bits access="rc" name="m2_rnum_int" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER2
0
1</comment>
        </bits>
        <bits access="rc" name="m2_wnum_int" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER2
0
1</comment>
        </bits>
        <bits access="rc" name="m1_rnum_int" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER1
0
1</comment>
        </bits>
        <bits access="rc" name="m1_wnum_int" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER1
0
1</comment>
        </bits>
        <bits access="rc" name="m0_rnum_int" pos="7" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER0
0
1</comment>
        </bits>
        <bits access="rc" name="m0_wnum_int" pos="6" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER0
0
1</comment>
        </bits>
        <bits access="rc" name="timer_cint" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.
0
1</comment>
        </bits>
        <bits access="rc" name="m4_lcok_int" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER4
0
1</comment>
        </bits>
        <bits access="rc" name="m3_lcok_int" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER3
0
1</comment>
        </bits>
        <bits access="rc" name="m2_lcok_int" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER2
0
1</comment>
        </bits>
        <bits access="rc" name="m1_lcok_int" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER1
0
1</comment>
        </bits>
        <bits access="rc" name="m0_lcok_int" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          MASTER0
0
1</comment>
        </bits>
      </reg>
      <reg name="mon_m0_start_addr0" protect="rw">
        <bits access="rw" name="first_addr" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="mon_m0_end_addr0" protect="rw">
        <bits access="rw" name="end_addr" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="mon_m0_addr_wid" protect="r">
        <bits access="r" name="wa_id" pos="7:0" rst="0">
          <comment>ID
: MON_START_ADDR, MON_END_ADDRMASTER0;MASTER0,ADDR_INT,</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="mon_lock_time" protect="rw">
        <bits access="rw" name="lock_value" pos="15:0" rst="65535">
          <comment/>
        </bits>
      </reg>
      <reg name="mon_rcommand0" protect="r">
        <bits access="r" name="rc_cnt" pos="31:0" rst="0">
          <comment>0
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_rdata0" protect="r">
        <bits access="r" name="rd_cnt" pos="31:0" rst="0">
          <comment>0
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_wcommand0" protect="r">
        <bits access="r" name="wc_cnt" pos="31:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="mon_wdata0" protect="r">
        <bits access="r" name="wd_cnt" pos="31:0" rst="0">
          <comment>0
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_rcommand1" protect="r">
        <bits access="r" name="rc_cnt" pos="31:0" rst="0">
          <comment>1
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_rdata1" protect="r">
        <bits access="r" name="rd_cnt" pos="31:0" rst="0">
          <comment>1
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_wcommand1" protect="r">
        <bits access="r" name="wc_cnt" pos="31:0" rst="0">
          <comment>1</comment>
        </bits>
      </reg>
      <reg name="mon_wdata1" protect="r">
        <bits access="r" name="wd_cnt" pos="31:0" rst="0">
          <comment>1
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_rcommand2" protect="r">
        <bits access="r" name="rc_cnt" pos="31:0" rst="0">
          <comment>2
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_rdata2" protect="r">
        <bits access="r" name="rd_cnt" pos="31:0" rst="0">
          <comment>2
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_wcommand2" protect="r">
        <bits access="r" name="wc_cnt" pos="31:0" rst="0">
          <comment>2</comment>
        </bits>
      </reg>
      <reg name="mon_wdata2" protect="r">
        <bits access="r" name="wd_cnt" pos="31:0" rst="0">
          <comment>2
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_rcommand3" protect="r">
        <bits access="r" name="rc_cnt" pos="31:0" rst="0">
          <comment>3
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_rdata3" protect="r">
        <bits access="r" name="rd_cnt" pos="31:0" rst="0">
          <comment>3
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_wcommand3" protect="r">
        <bits access="r" name="wc_cnt" pos="31:0" rst="0">
          <comment>3</comment>
        </bits>
      </reg>
      <reg name="mon_wdata3" protect="r">
        <bits access="r" name="wd_cnt" pos="31:0" rst="0">
          <comment>3
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_rcommand4" protect="r">
        <bits access="r" name="rc_cnt" pos="31:0" rst="0">
          <comment>4
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_rdata4" protect="r">
        <bits access="r" name="rd_cnt" pos="31:0" rst="0">
          <comment>4
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_wcommand4" protect="r">
        <bits access="r" name="wc_cnt" pos="31:0" rst="0">
          <comment>4</comment>
        </bits>
      </reg>
      <reg name="mon_wdata4" protect="r">
        <bits access="r" name="wd_cnt" pos="31:0" rst="0">
          <comment>4
-10xFF0x100</comment>
        </bits>
      </reg>
      <reg name="mon_m0_start_addr1" protect="rw">
        <bits access="rw" name="first_addr" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="mon_m0_end_addr1" protect="rw">
        <bits access="rw" name="end_addr" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="mon_m0_start_addr2" protect="rw">
        <bits access="rw" name="first_addr" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="mon_m0_end_addr2" protect="rw">
        <bits access="rw" name="end_addr" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="mon_m0_start_addr3" protect="rw">
        <bits access="rw" name="first_addr" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="mon_m0_end_addr3" protect="rw">
        <bits access="rw" name="end_addr" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="mon_m0_addr" protect="r">
        <bits access="r" name="addr" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_zsp_wd.xml">
    <module category="ZSP_SYS" name="CP_ZSP_WD">
      <reg name="wd_conf" protect="rw">
        <bits access="rw" name="prot_en" pos="9" rst="1">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="wd" pos="8" rst="1">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="pvt" pos="7:4" rst="0">
          <comment>0000
00011/2
00101/4
00111/8
01001/16
01011/32
01101/64
01111/128
10001/256</comment>
        </bits>
        <bits access="rw" name="tr" pos="3" rst="0">
          <comment>0
00
10</comment>
        </bits>
        <bits access="rw" name="ie" pos="2" rst="0">
          <comment>0
1Load</comment>
        </bits>
        <bits access="rw" name="ar" pos="1" rst="0">
          <comment>0Load
1Load0</comment>
        </bits>
        <bits access="rw" name="start" pos="0" rst="0">
          <comment>0
1
1STARTTR0
20xCCCCSTARTPROT_EN
3STARTARSTART</comment>
        </bits>
      </reg>
      <reg name="wd_prot" protect="rw">
        <bits access="rw" name="prot" pos="15:0" rst="0">
          <comment>0xCCCCWD_CONFWD_LOAD12
WD_CONF[9]1</comment>
        </bits>
      </reg>
      <reg name="wd_load1" protect="rw">
        <bits access="rw" name="load" pos="31:0" rst="130000000">
          <comment>32bit
1</comment>
        </bits>
      </reg>
      <reg name="wd_load2" protect="rw">
        <bits access="rw" name="load" pos="31:0" rst="0">
          <comment>32bit
1</comment>
        </bits>
      </reg>
      <reg name="wd_value1" protect="r">
        <bits access="r" name="value" pos="31:0" rst="0">
          <comment>32bit</comment>
        </bits>
      </reg>
      <reg name="wd_value2" protect="r">
        <bits access="r" name="value" pos="31:0" rst="0">
          <comment>32bit</comment>
        </bits>
      </reg>
      <reg name="wd_cmd" protect="w">
        <bits access="w" name="cmd" pos="15:0" rst="0">
          <comment>0xAAAA0x5555
0xAAAA0x4444
0xBBBB</comment>
        </bits>
      </reg>
      <reg name="wd_div_conf" protect="rw">
        <bits access="rw" name="en" pos="16" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="div" pos="15:0" rst="25">
          <comment>f= FuncClk/(DIV+1)
WATCHDOG26MhzDIVWD_DIV_COUNT</comment>
        </bits>
      </reg>
      <reg name="wd_div_count" protect="rw">
        <bits access="rc" name="count" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_pusch.xml">
    <module category="LTE_SYS" name="CP_LTE_PUSCH">
      <reg name="ack_offset" protect="rw">
        <bits access="rw" name="ack_offset_ack_offset" pos="3:0" rst="0">
          <comment>ACK</comment>
        </bits>
      </reg>
      <reg name="ri_offset" protect="rw">
        <bits access="rw" name="ri_offset_ri_offset" pos="3:0" rst="0">
          <comment>RIMCS</comment>
        </bits>
      </reg>
      <reg name="cqi_offset" protect="rw">
        <bits access="rw" name="cqi_offset_cqi_offset" pos="3:0" rst="0">
          <comment>CQIMCS</comment>
        </bits>
      </reg>
      <reg name="tbsize_init" protect="rw">
        <bits access="rw" name="tbsize_init_tbsize_init" pos="13:0" rst="0">
          <comment>PUSCHPUSCHCRCbit</comment>
        </bits>
      </reg>
      <reg name="tbsize" protect="rw">
        <bits access="rw" name="tbsize_tbsize" pos="13:0" rst="0">
          <comment>PUSCHPUSCHCRCbit</comment>
        </bits>
      </reg>
      <reg name="modulate" protect="rw">
        <bits access="rw" name="modulate_modulate" pos="1:0" rst="0">
          <comment>00BPSK
01QPSK
1016QAM
1164QAM</comment>
        </bits>
      </reg>
      <reg name="redun_ver" protect="rw">
        <bits access="rw" name="redun_ver_redun_ver" pos="1:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="lcrb" protect="rw">
        <bits access="rw" name="ini_sub_num" pos="26:16" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="sub_num" pos="10:0" rst="0">
          <comment>PUSCH</comment>
        </bits>
      </reg>
      <reg name="symbol_num" protect="rw">
        <bits access="rw" name="ru_num" pos="11:8" rst="0">
          <comment>RU</comment>
        </bits>
        <bits access="rw" name="ini_sym_num" pos="7:4" rst="0">
          <comment>PUSCHCAT1/CATM
1PUSCH DATA
CAT-NB1RU</comment>
        </bits>
        <bits access="rw" name="sym_num" pos="3:0" rst="0">
          <comment>PUSCHCAT1/CATM1
PUSCH DATACAT-NB
1RU</comment>
        </bits>
      </reg>
      <reg name="cqi_bit1" protect="rw">
        <bits access="rw" name="cqi_bit1_cqi_bit1" pos="31:0" rst="0">
          <comment>CQI31~0</comment>
        </bits>
      </reg>
      <reg name="cqi_bit2" protect="rw">
        <bits access="rw" name="cqi_bit2_cqi_bit2" pos="31:0" rst="0">
          <comment>CQI31~0</comment>
        </bits>
      </reg>
      <reg name="cqi_bit8_bitlen" protect="rw">
        <bits access="rw" name="o_cqi_bitlen_min" pos="22:16" rst="0">
          <comment>CQI</comment>
        </bits>
        <bits access="rw" name="o_cqi_bitlen" pos="14:8" rst="0">
          <comment>CQI65</comment>
        </bits>
        <bits access="rw" name="cqi_bit8" pos="0" rst="0">
          <comment>CQI64</comment>
        </bits>
      </reg>
      <reg name="ri_bit_bitlen" protect="rw">
        <bits access="rw" name="o_ri_bitlen" pos="16" rst="0">
          <comment>RI</comment>
        </bits>
        <bits access="rw" name="ri_bit" pos="0" rst="0">
          <comment>RI</comment>
        </bits>
      </reg>
      <reg name="ack_bit_bitlen" protect="rw">
        <bits access="rw" name="o_ack_bitlen" pos="26:24" rst="0">
          <comment>ACK4</comment>
        </bits>
        <bits access="rw" name="ack_bit" pos="3:0" rst="0">
          <comment>ACK</comment>
        </bits>
      </reg>
      <reg name="ack_mux_bundling" protect="rw">
        <bits access="rw" name="bundling_flag" pos="2" rst="0">
          <comment>0FDDTDDHARQ-ACK
1TDDHARQ-ACK</comment>
        </bits>
        <bits access="rw" name="bundling_idx" pos="1:0" rst="0">
          <comment>TDD HARQ-ACK</comment>
        </bits>
      </reg>
      <reg name="pucch_format" protect="rw">
        <bits access="rw" name="format" pos="2:0" rst="0">
          <comment>PUCCH
000~010RESERVED
0112
1002a
1012b
110~111RESERVED</comment>
        </bits>
      </reg>
      <reg name="prach_u" protect="rw">
        <bits access="rw" name="u_inv_value" pos="25:16" rst="0">
          <comment>U</comment>
        </bits>
        <bits access="rw" name="u_value" pos="9:0" rst="0">
          <comment>U</comment>
        </bits>
      </reg>
      <reg name="prach_cv" protect="rw">
        <bits access="rw" name="cv_value" pos="9:0" rst="0">
          <comment>CV</comment>
        </bits>
      </reg>
      <reg name="gold_init" protect="rw">
        <bits access="rw" name="gold_init_gold_init" pos="30:0" rst="0">
          <comment>GOLD</comment>
        </bits>
      </reg>
      <reg name="pusch_ctrl" protect="rw">
        <bits access="rw" name="pusch2dft_trig_en" pos="17" rst="0">
          <comment>1PUSCHULDFT
0PUSCHULDFT</comment>
        </bits>
        <bits access="rw" name="func_sel" pos="16:15" rst="0">
          <comment>00PUSCH
01PUCCH UCI
10PRACH
11NPUSCH1NPUSCH2PUSCH IP</comment>
        </bits>
        <bits access="rw" name="uci_en" pos="14" rst="0">
          <comment>FUNC_SELPUSCH UCIPUCCH UCIFUNC_SEL00PUSCH UCIFUNC_SEL01PUCCH UCI
0UCI
1UCI</comment>
        </bits>
        <bits access="rw" name="buf_index" pos="13:12" rst="0">
          <comment>PUSCH_BUFFERMEM
00PUSCH_BUF1
01PUSCH_BUF2
10PUSCH_BUF3
11PRACH_BUF</comment>
        </bits>
        <bits access="rw" name="pusch_buf_en" pos="11" rst="0">
          <comment>0PUSCH_BUFFER
1PUSCH_BUFFER</comment>
        </bits>
        <bits access="rw" name="zc_index" pos="9" rst="0">
          <comment>PRACHZC
0ZC139
1ZC839</comment>
        </bits>
        <bits access="rw" name="inver_en" pos="7" rst="0">
          <comment>0PUSCHCRCByte
1PUSCHCRCByte</comment>
        </bits>
        <bits access="rw" name="pusch_irqen" pos="5" rst="0">
          <comment>0LTE
1LTE</comment>
        </bits>
        <bits access="rw" name="scr_en" pos="4" rst="0">
          <comment>0PUSCH
1PUSCH</comment>
        </bits>
        <bits access="rw" name="int_en" pos="3" rst="0">
          <comment>0PUSCH
1PUSCH</comment>
        </bits>
        <bits access="rw" name="tb_rm_en" pos="2" rst="0">
          <comment>0PUSCHTurbo
1PUSCHTurbo</comment>
        </bits>
        <bits access="rw" name="crc_en" pos="1" rst="0">
          <comment>0PUSCHCRC
1PUSCHCRC</comment>
        </bits>
        <bits access="rw" name="fun_en" pos="0" rst="0">
          <comment>0LTE
1LTE</comment>
        </bits>
      </reg>
      <reg name="pusch_irq_flag" protect="rw">
        <bits access="rc" name="irq_flag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
      </reg>
      <reg name="pucch_res" protect="r">
        <bits access="r" name="res_uci" pos="21:0" rst="0">
          <comment>PUCCH format2/2a/2b UCI</comment>
        </bits>
      </reg>
      <hole size="523584"/>
      <reg name="mem1" protect="rw">
        <bits access="rw" name="mem1_mem1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="mem2" protect="rw">
        <bits access="rw" name="mem2_mem2" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="mem3" protect="rw">
        <bits access="rw" name="mem3_mem3" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="pusch_buf1" protect="rw">
        <bits access="rw" name="pusch_buf1_pusch_buf1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="pusch_buf2" protect="rw">
        <bits access="rw" name="pusch_buf2_pusch_buf2" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="pusch_buf3" protect="rw">
        <bits access="rw" name="pusch_buf3_pusch_buf3" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="prach_buf" protect="rw">
        <bits access="rw" name="prach_buf_prach_buf" pos="31:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_ldtc1.xml">
    <module category="LTE_SYS" name="CP_LTE_LDTC1">
      <reg name="csys_para_nxt" protect="rw">
        <bits access="rw" name="schd_sib1" pos="30:26" rst="0">
          <comment>Schedule SIB1 BR R13PBML</comment>
        </bits>
        <bits access="rw" name="phi_res" pos="25:24" rst="0">
          <comment>PHICH resourcePBML</comment>
        </bits>
        <bits access="rw" name="phi_dur" pos="23" rst="0">
          <comment>PHICH durationPBML</comment>
        </bits>
        <bits access="rw" name="bw_ind_ul" pos="22:20" rst="0">
          <comment>01.4Mhz
13Mhz
25Mhz
310Mhz
415Mhz
520Mhz
6~75</comment>
        </bits>
        <bits access="rw" name="ng_ind" pos="19:18" rst="0">
          <comment>Ng
01/6
11/2
21
32</comment>
        </bits>
        <bits access="rw" name="tm_mode" pos="17:14" rst="0">
          <comment>1~:9tm1,tm2,,tm9</comment>
        </bits>
        <bits access="rw" name="ss_conf" pos="13:10" rst="0">
          <comment>TDD0~9
9</comment>
        </bits>
        <bits access="rw" name="uldl_conf" pos="9:7" rst="0">
          <comment>0~66</comment>
        </bits>
        <bits access="rw" name="bw_ind" pos="6:4" rst="0">
          <comment>01.4Mhz
13Mhz
25Mhz
310Mhz
415Mhz
520Mhz
6~75</comment>
        </bits>
        <bits access="rw" name="ant_tx" pos="3:2" rst="0">
          <comment>01
12
24
32</comment>
        </bits>
        <bits access="rw" name="cp_ind" pos="1" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="rw" name="fdd_tdd" pos="0" rst="0">
          <comment>FDDTDD
0TDD
1FDD</comment>
        </bits>
      </reg>
      <reg name="cnid_cell_nxt" protect="rw">
        <bits access="rw" name="nid_cell" pos="8:0" rst="0">
          <comment>ID0~503</comment>
        </bits>
      </reg>
      <reg name="dsys_para_nxt" protect="rw">
        <bits access="rw" name="bw_ind_ul" pos="22:20" rst="0">
          <comment>01.4Mhz
13Mhz
25Mhz
310Mhz
415Mhz
520Mhz
6~75</comment>
        </bits>
        <bits access="rw" name="ng_ind" pos="19:18" rst="0">
          <comment>Ng
01/6
11/2
21
32</comment>
        </bits>
        <bits access="rw" name="tm_mode" pos="17:14" rst="0">
          <comment>1~:9tm1,tm2,,tm9</comment>
        </bits>
        <bits access="rw" name="ss_conf" pos="13:10" rst="0">
          <comment>TDD0~99</comment>
        </bits>
        <bits access="rw" name="uldl_conf" pos="9:7" rst="0">
          <comment>0~66</comment>
        </bits>
        <bits access="rw" name="bw_ind" pos="6:4" rst="0">
          <comment>01.4Mhz
13Mhz
25Mhz
310Mhz
415Mhz
520Mhz
6~75</comment>
        </bits>
        <bits access="rw" name="ant_tx" pos="3:2" rst="0">
          <comment>01
12
24
32</comment>
        </bits>
        <bits access="rw" name="cp_ind" pos="1" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="rw" name="fdd_tdd" pos="0" rst="0">
          <comment>FDDTDD
0TDD
1FDD</comment>
        </bits>
      </reg>
      <reg name="dnid_cell_nxt" protect="rw">
        <bits access="rw" name="nid_cell" pos="8:0" rst="0">
          <comment>MBSFN ID0~255
ID0~503</comment>
        </bits>
      </reg>
      <reg name="ra_t_rnti" protect="rw">
        <bits access="rw" name="t_rnti" pos="31:16" rst="0">
          <comment>Temp-C-RNTI</comment>
        </bits>
        <bits access="rw" name="ra_rnti" pos="15:0" rst="0">
          <comment>RA_RNTI</comment>
        </bits>
      </reg>
      <reg name="c_sps_rnti" protect="rw">
        <bits access="rw" name="sps_rnti" pos="31:16" rst="0">
          <comment>SPS_RNTI</comment>
        </bits>
        <bits access="rw" name="c_rnti" pos="15:0" rst="0">
          <comment>C_RNTI</comment>
        </bits>
      </reg>
      <reg name="tpc_rnti" protect="rw">
        <bits access="rw" name="tpcs_rnti" pos="31:16" rst="0">
          <comment>TPC-PUCSH-RNTI</comment>
        </bits>
        <bits access="rw" name="tpcc_rnti" pos="15:0" rst="0">
          <comment>TPC-PUCCH-RNTI</comment>
        </bits>
      </reg>
      <reg name="g_rnti" protect="rw">
        <bits access="rw" name="g_rnti_g_rnti" pos="15:0" rst="0">
          <comment>G_RNTI</comment>
        </bits>
      </reg>
      <reg name="csi_rsmap0_nxt" protect="rw">
        <bits access="rw" name="csirs_group2" pos="23:12" rst="0">
          <comment>2PRBCSI-RS
CSIRS_GROUP1</comment>
        </bits>
        <bits access="rw" name="csirs_group1" pos="11:0" rst="0">
          <comment>1PRBCSI-RS
011PRBRE#0
RE#1101RE#0
CSI-RS</comment>
        </bits>
      </reg>
      <reg name="csi_rsmap1_nxt" protect="rw">
        <bits access="rw" name="csirs_jump" pos="30:24" rst="0">
          <comment>CSI-RSOFDM1PDSCHNorm-CP2430OFDM#5689101213Ext-CP2429OFDM#45781011Norm-CP241OFDM#510OFDM#51CSI-RS</comment>
        </bits>
        <bits access="rw" name="csirs_group4" pos="23:12" rst="0">
          <comment>4PRBCSI-RSCSIRS_GROUP1</comment>
        </bits>
        <bits access="rw" name="csirs_group3" pos="11:0" rst="0">
          <comment>3PRBCSI-RSCSIRS_GROUP1</comment>
        </bits>
      </reg>
      <reg name="pmi_cfg" protect="rw">
        <bits access="rw" name="pmi_cbsr" pos="15:0" rst="0">
          <comment>PMI (codebookSubsetRestriction)
0PMIbit
1PMIbit</comment>
        </bits>
      </reg>
      <reg name="pcfi_cfg_nxt" protect="rw">
        <bits access="rw" name="cfi_val" pos="3:0" rst="7">
          <comment>BIT
Bit0:1OFDMCFI
Bit1:2OFDMCFI
Bit2:3OFDMCFI
Bit3:4OFDMCFI
0
1</comment>
        </bits>
      </reg>
      <reg name="phi_cfg_nxt" protect="rw">
        <bits access="rw" name="hi_cond" pos="23:22" rst="0">
          <comment>HIOFDM0~3</comment>
        </bits>
        <bits access="rw" name="phi1_en" pos="21" rst="0">
          <comment>PHICH1
0
1</comment>
        </bits>
        <bits access="rw" name="phi1_seqnum" pos="20:18" rst="0">
          <comment>PHICH10~7</comment>
        </bits>
        <bits access="rw" name="phi1_grpnum" pos="17:11" rst="0">
          <comment>PHICH10~99</comment>
        </bits>
        <bits access="rw" name="phi0_en" pos="10" rst="0">
          <comment>PHICH0
0
1</comment>
        </bits>
        <bits access="rw" name="phi0_seqnum" pos="9:7" rst="0">
          <comment>PHICH00~7</comment>
        </bits>
        <bits access="rw" name="phi0_grpnum" pos="6:0" rst="0">
          <comment>PHICH00~99</comment>
        </bits>
      </reg>
      <reg name="pdcch_cfg_nxt" protect="rw">
        <bits access="rw" name="dcilen_ue1" pos="31:26" rst="0">
          <comment>UEDCImax57</comment>
        </bits>
        <bits access="rw" name="dcilen_ue0" pos="25:20" rst="0">
          <comment>UEDCImax57</comment>
        </bits>
        <bits access="rw" name="dcilen_comm1" pos="19:14" rst="0">
          <comment>COMMDCImax57</comment>
        </bits>
        <bits access="rw" name="dcilen_comm0" pos="13:8" rst="0">
          <comment>COMMDCImax57</comment>
        </bits>
        <bits access="rw" name="dcilen_sel" pos="7" rst="0">
          <comment>DCILEN
0
1</comment>
        </bits>
        <bits access="rw" name="pus_enh" pos="6" rst="0">
          <comment>PUSCH
0DCI0
1DCI0C</comment>
        </bits>
        <bits access="rw" name="csi_sel" pos="5" rst="0">
          <comment>CSI
01
12</comment>
        </bits>
        <bits access="rw" name="antsel_en" pos="4" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="srs_act" pos="3" rst="0">
          <comment>SRS
0DCISRS_REQ
1DCISRS_REQ</comment>
        </bits>
        <bits access="rw" name="pdcch_det_num" pos="2:0" rst="4">
          <comment>PDCCH
0:1
1:2
2:3
3:4
78</comment>
        </bits>
      </reg>
      <reg name="pdsch0_cfg_nxt" protect="rw">
        <bits access="rw" name="pmi_confm" pos="31" rst="0">
          <comment>PMIDCIPMI
0DCIPMI
1PMI</comment>
        </bits>
        <bits access="rw" name="hq_proc" pos="30:27" rst="0">
          <comment>HARQ:0~15</comment>
        </bits>
        <bits access="rw" name="pmi_indx" pos="26:23" rst="0">
          <comment>tx2:0~3tx4:0~15</comment>
        </bits>
        <bits access="rw" name="trans_scheme" pos="22:20" rst="0">
          <comment>0
1
2
3PORT7
4PORT8
5PORT5</comment>
        </bits>
        <bits access="rw" name="ra_type" pos="19" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="n_scid" pos="18" rst="0">
          <comment>Nscid(UE)0~1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="17:16" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="modu" pos="15:14" rst="0">
          <comment>0:QPSK
1:16QAM
2:64QAM</comment>
        </bits>
        <bits access="rw" name="tbsize" pos="13:0" rst="0">
          <comment>max10296</comment>
        </bits>
      </reg>
      <reg name="pdsch1_cfg_nxt" protect="rw">
        <bits access="rw" name="ra_type" pos="16" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="15:14" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="tbsize" pos="13:0" rst="0">
          <comment>max2216</comment>
        </bits>
      </reg>
      <reg name="pdsch2_cfg_nxt" protect="rw">
        <bits access="rw" name="ra_type" pos="16" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="15:14" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="tbsize" pos="13:0" rst="0">
          <comment>max2216</comment>
        </bits>
      </reg>
      <reg name="frame_ccnt_nxt" protect="rw">
        <bits access="rw" name="ssfn_cnt" pos="31:16" rst="0">
          <comment>0~65535</comment>
        </bits>
        <bits access="rw" name="rf_cnt" pos="13:4" rst="0">
          <comment>:0~1023</comment>
        </bits>
        <bits access="rw" name="sf_cnt" pos="3:0" rst="0">
          <comment>:0~9</comment>
        </bits>
      </reg>
      <reg name="frame_dcnt_nxt" protect="rw">
        <bits access="rw" name="ssfn_cnt" pos="31:16" rst="0">
          <comment>0~65535</comment>
        </bits>
        <bits access="rw" name="rf_cnt" pos="13:4" rst="0">
          <comment>:0~1023</comment>
        </bits>
        <bits access="rw" name="sf_cnt" pos="3:0" rst="0">
          <comment>:0~9</comment>
        </bits>
      </reg>
      <reg name="ldtc1_cserv_nxt" protect="rw">
        <bits access="rw" name="sc_n_rnti_en" pos="10" rst="0">
          <comment>SC-N-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="sc_rnti_en" pos="9" rst="0">
          <comment>SC-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="g_rnti_en" pos="8" rst="0">
          <comment>G-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="tpcc_rnti_en" pos="7" rst="0">
          <comment>TPC-PUCCH-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="tpcs_rnti_en" pos="6" rst="0">
          <comment>TPC-PUSCH-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="t_rnti_en" pos="5" rst="0">
          <comment>Temp-C-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="sps_rnti_en" pos="4" rst="0">
          <comment>SPS-C-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="c_rnti_en" pos="3" rst="0">
          <comment>C-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="ra_rnti_en" pos="2" rst="0">
          <comment>RA-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="p_rnti_en" pos="1" rst="0">
          <comment>P-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="si_rnti_en" pos="0" rst="0">
          <comment>SI-RNTI
0
1</comment>
        </bits>
      </reg>
      <reg name="ldtc1_dserv_nxt" protect="rw">
        <bits access="rw" name="sc_rnti_en" pos="7" rst="0">
          <comment>SC-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="g_rnti_en" pos="6" rst="0">
          <comment>G-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="t_rnti_en" pos="5" rst="0">
          <comment>Temp-C-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="sps_rnti_en" pos="4" rst="0">
          <comment>SPS-C-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="c_rnti_en" pos="3" rst="0">
          <comment>C-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="ra_rnti_en" pos="2" rst="0">
          <comment>RA-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="p_rnti_en" pos="1" rst="0">
          <comment>P-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="si_rnti_en" pos="0" rst="0">
          <comment>SI-RNTI
0
1</comment>
        </bits>
      </reg>
      <reg name="ldtc1_cctrl_nxt" protect="rw">
        <bits access="rw" name="dma_s_en" pos="14" rst="0">
          <comment>SINR DMA
0
1</comment>
        </bits>
        <bits access="rw" name="dma_m_en" pos="13" rst="0">
          <comment>PMI DMA
0
1</comment>
        </bits>
        <bits access="rw" name="int_s_en" pos="12" rst="0">
          <comment>SINR
0
1</comment>
        </bits>
        <bits access="rw" name="int_m_en" pos="11" rst="0">
          <comment>PMI
0
1</comment>
        </bits>
        <bits access="rw" name="int_c_en" pos="10" rst="0">
          <comment>PDCCH
0
1</comment>
        </bits>
        <bits access="rw" name="int_b_en" pos="9" rst="0">
          <comment>PBCH
0
1</comment>
        </bits>
        <bits access="rw" name="mbms_sf" pos="8" rst="0">
          <comment>MBMS
0MBMS
1MBMS</comment>
        </bits>
        <bits access="rw" name="cqfqt_ppsel" pos="7:6" rst="0">
          <comment>CTRL QFQT
01
12
23</comment>
        </bits>
        <bits access="rw" name="pbch_first" pos="5" rst="0">
          <comment>PBCH
0
1</comment>
        </bits>
        <bits access="rw" name="sinr_en" pos="4" rst="0">
          <comment>SINR
0
1</comment>
        </bits>
        <bits access="rw" name="pmi_en" pos="3" rst="0">
          <comment>PMI
0
1</comment>
        </bits>
        <bits access="rw" name="hi_en" pos="2" rst="0">
          <comment>HI
0
1</comment>
        </bits>
        <bits access="rw" name="pdcch_en" pos="1" rst="0">
          <comment>PDCCH
0
1</comment>
        </bits>
        <bits access="rw" name="pbch_en" pos="0" rst="0">
          <comment>PBCH
0
1</comment>
        </bits>
      </reg>
      <reg name="ldtc1_dctrl_nxt" protect="rw">
        <bits access="rw" name="dma_d_en" pos="8" rst="0">
          <comment>PDSCH DMA
0
1</comment>
        </bits>
        <bits access="rw" name="int_d_en" pos="7" rst="0">
          <comment>PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="dqfqt_ppsel" pos="6:5" rst="0">
          <comment>DATA QFQT
01
12
23</comment>
        </bits>
        <bits access="rw" name="csirs_en" pos="4" rst="0">
          <comment>CSIRS
0
1</comment>
        </bits>
        <bits access="rw" name="sihqbuf_sel" pos="3" rst="0">
          <comment>SIHQBUF
0HQBUF0
1HQBUF1</comment>
        </bits>
        <bits access="rw" name="si_first" pos="2" rst="0">
          <comment>PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="pds_first" pos="1" rst="0">
          <comment>PDS
0
1</comment>
        </bits>
        <bits access="rw" name="pdsch_en" pos="0" rst="0">
          <comment>PDSCH
0
1</comment>
        </bits>
      </reg>
      <reg name="ldtc1_cstart" protect="rw">
        <bits access="rw" name="ldtc_cstart" pos="0" rst="0">
          <comment>LDTC
0
1</comment>
        </bits>
      </reg>
      <reg name="ldtc1_dstart" protect="rw">
        <bits access="rw" name="ldtc_dstart" pos="0" rst="0">
          <comment>LDTC
0
1</comment>
        </bits>
      </reg>
      <reg name="ctrl_flag" protect="rw">
        <bits access="rc" name="dci_valid" pos="15:8" rst="0">
          <comment>bit type is changed from rw1c to rc.
          DCI
0DCI
1DCI</comment>
        </bits>
        <bits access="rc" name="mib_valid" pos="7:4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          MIB
0MIB
1MIB</comment>
        </bits>
        <bits access="rc" name="int_sflag" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          SINR
0
1</comment>
        </bits>
        <bits access="rc" name="int_mflag" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PMI
0
1</comment>
        </bits>
        <bits access="rc" name="int_cflag" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PDCCH
0
1</comment>
        </bits>
        <bits access="rc" name="int_bflag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PBCH
0
1</comment>
        </bits>
      </reg>
      <reg name="data_flag" protect="rw">
        <bits access="rc" name="paging_zero_flag" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PAGINGCRC
0
1</comment>
        </bits>
        <bits access="rc" name="paging_crc_flag" pos="5" rst="1">
          <comment>bit type is changed from rw1c to rc.
          PAGINGCRC
0CRC
1CRC</comment>
        </bits>
        <bits access="rc" name="si_zero_flag" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          SICRC
0
1</comment>
        </bits>
        <bits access="rc" name="si_crc_flag" pos="3" rst="1">
          <comment>bit type is changed from rw1c to rc.
          SICRC
0CRC
1CRC</comment>
        </bits>
        <bits access="rc" name="pdsch_zero_flag" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PDSCH CRC
0
1</comment>
        </bits>
        <bits access="rc" name="pdsch_crc_flag" pos="1" rst="1">
          <comment>bit type is changed from rw1c to rc.
          PDSCH CRC
0CRC
1CRC</comment>
        </bits>
        <bits access="rc" name="int_dflag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PDSCH
0
1</comment>
        </bits>
      </reg>
      <reg name="buf_flag" protect="r">
        <bits access="r" name="dfh_ind" pos="3" rst="0">
          <comment>FHdata
0FH0
1FH1</comment>
        </bits>
        <bits access="r" name="cfh_ind" pos="2" rst="0">
          <comment>FHctrl
0FH0
1FH1</comment>
        </bits>
        <bits access="r" name="dschout_ind" pos="1" rst="0">
          <comment>DSCHOUT
0DSCHOUT0
1DSCHOUT1</comment>
        </bits>
        <bits access="r" name="fftbuf_ind" pos="0" rst="0">
          <comment>FFTBUF
0FFTBUF0
1FFTBUF1</comment>
        </bits>
      </reg>
      <reg name="alg_comm_para" protect="rw">
        <bits access="rw" name="pdc_th" pos="16:11" rst="0">
          <comment>PDCCH</comment>
        </bits>
        <bits access="rw" name="g_scale" pos="10:8" rst="4">
          <comment>GQ
0Q15
1Q16
7Q22</comment>
        </bits>
        <bits access="rw" name="cc_ir" pos="7" rst="0">
          <comment>HQ
0CC
1IR</comment>
        </bits>
        <bits access="rw" name="hqbit_sel" pos="6" rst="0">
          <comment>HQ BUF
04bit
16bit</comment>
        </bits>
        <bits access="rw" name="sdgn_sel" pos="5" rst="0">
          <comment>SDGnoise
0noise
1GM</comment>
        </bits>
        <bits access="rw" name="subbw_sel" pos="4" rst="0">
          <comment>PMI/PWR
0
1</comment>
        </bits>
        <bits access="rw" name="ctcg_sel" pos="3" rst="0">
          <comment>CTCG
0OFDM4(OFDM4)CRS
1OFDM8(OFDM8)CRS</comment>
        </bits>
        <bits access="rw" name="crs_g_len" pos="2" rst="0">
          <comment>CRS G
01PRB
12PRB</comment>
        </bits>
        <bits access="rw" name="crs_fh_len" pos="1" rst="0">
          <comment>CRS36 PRB
03PRB
16PRB</comment>
        </bits>
        <bits access="rw" name="ue_bund" pos="0" rst="0">
          <comment>UE RSPRB1,3
0
1</comment>
        </bits>
      </reg>
      <reg name="che_fh_para" protect="rw">
        <bits access="rw" name="fh10_bitsel_type" pos="7" rst="1">
          <comment>16bit10bit
0
1</comment>
        </bits>
        <bits access="rw" name="fh10_bitsel" pos="6:4" rst="0">
          <comment>16bit10bit
0x015~6
0x114~5
0x213~4
0x312~3
0x411~2
0x510~1
0x69~0
reserved</comment>
        </bits>
        <bits access="rw" name="fh16_bitsel" pos="3:0" rst="6">
          <comment>16bit
0x028~13
0x127~12
0x226~11
0x325~10
0x424~9
0x523~8
0x622~7
0x721~6
0x820~5
0x919~4
0xa18~3
0xb17~2
0xc16~1
0xd15~0
Reserved</comment>
        </bits>
      </reg>
      <reg name="che_th_para" protect="rw">
        <bits access="rw" name="th16_bitsel" pos="3:0" rst="5">
          <comment>0x025~10
0x124~9
0x223~8
0x322~7
0x421~6
0x520~5
0x619~4
0x718~3
0x817~2
0x916~1
0xa15~0</comment>
        </bits>
      </reg>
      <reg name="rbbm_pds00_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pds01_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pds02_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[95:64]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pds03_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbit[99:96]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pds10_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[31:0]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pds11_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pds12_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[95:64]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pds13_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbit[99:96]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_si00_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[31:0]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_si01_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[64:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_si02_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[95:64]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_si03_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_si10_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[31:0]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_si11_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_si12_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[95:64]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_si13_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbit[99:96]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pag00_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[31:0]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pag01_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pag02_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[95:64]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pag03_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbit[99:96]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pag10_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[31:0]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pag11_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pag12_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[95:64]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="rbbm_pag13_nxt" protect="rw">
        <bits access="rw" name="rbbm_nxt_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbit[99:96]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="pmi_pds0_nxt" protect="rw">
        <bits access="rw" name="pmi_8" pos="31:28" rst="0">
          <comment>8</comment>
        </bits>
        <bits access="rw" name="pmi_7" pos="27:24" rst="0">
          <comment>7</comment>
        </bits>
        <bits access="rw" name="pmi_6" pos="23:20" rst="0">
          <comment>6</comment>
        </bits>
        <bits access="rw" name="pmi_5" pos="19:16" rst="0">
          <comment>5</comment>
        </bits>
        <bits access="rw" name="pmi_4" pos="15:12" rst="0">
          <comment>4</comment>
        </bits>
        <bits access="rw" name="pmi_3" pos="11:8" rst="0">
          <comment>3</comment>
        </bits>
        <bits access="rw" name="pmi_2" pos="7:4" rst="0">
          <comment>2</comment>
        </bits>
        <bits access="rw" name="pmi_1" pos="3:0" rst="0">
          <comment>1</comment>
        </bits>
      </reg>
      <reg name="pmi_pds1_nxt" protect="rw">
        <bits access="rw" name="pmi_16" pos="31:28" rst="0">
          <comment>16</comment>
        </bits>
        <bits access="rw" name="pmi_15" pos="27:24" rst="0">
          <comment>15</comment>
        </bits>
        <bits access="rw" name="pmi_14" pos="23:20" rst="0">
          <comment>14</comment>
        </bits>
        <bits access="rw" name="pmi_13" pos="19:16" rst="0">
          <comment>13</comment>
        </bits>
        <bits access="rw" name="pmi_12" pos="15:12" rst="0">
          <comment>12</comment>
        </bits>
        <bits access="rw" name="pmi_11" pos="11:8" rst="0">
          <comment>11</comment>
        </bits>
        <bits access="rw" name="pmi_10" pos="7:4" rst="0">
          <comment>10</comment>
        </bits>
        <bits access="rw" name="pmi_9" pos="3:0" rst="0">
          <comment>9</comment>
        </bits>
      </reg>
      <reg name="pmi_pds2_nxt" protect="rw">
        <bits access="rw" name="pmi_24" pos="31:28" rst="0">
          <comment>24</comment>
        </bits>
        <bits access="rw" name="pmi_23" pos="27:24" rst="0">
          <comment>23</comment>
        </bits>
        <bits access="rw" name="pmi_22" pos="23:20" rst="0">
          <comment>22</comment>
        </bits>
        <bits access="rw" name="pmi_21" pos="19:16" rst="0">
          <comment>21</comment>
        </bits>
        <bits access="rw" name="pmi_20" pos="15:12" rst="0">
          <comment>20</comment>
        </bits>
        <bits access="rw" name="pmi_19" pos="11:8" rst="0">
          <comment>19</comment>
        </bits>
        <bits access="rw" name="pmi_18" pos="7:4" rst="0">
          <comment>18</comment>
        </bits>
        <bits access="rw" name="pmi_17" pos="3:0" rst="0">
          <comment>17</comment>
        </bits>
      </reg>
      <reg name="pmi_pds3_nxt" protect="rw">
        <bits access="rw" name="pmi_25" pos="3:0" rst="0">
          <comment>25</comment>
        </bits>
      </reg>
      <reg name="spwr_wb" protect="r">
        <bits access="r" name="spwr_wb_spwr_wb" pos="31:0" rst="0">
          <comment>1CRS</comment>
        </bits>
      </reg>
      <reg name="npwr_wb" protect="r">
        <bits access="r" name="npwr_wb_npwr_wb" pos="31:0" rst="0">
          <comment>1CRS</comment>
        </bits>
      </reg>
      <reg name="spwr_wb_agc" protect="r">
        <bits access="r" name="spwr_wb_agc_spwr_wb_agc" pos="9:0" rst="0">
          <comment>1CRSAGC</comment>
        </bits>
      </reg>
      <reg name="npwr_wb_agc" protect="r">
        <bits access="r" name="npwr_wb_agc_npwr_wb_agc" pos="9:0" rst="0">
          <comment>1CRSAGC</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_factor0" protect="rw">
        <bits access="rw" name="pdcch_scale_sel" pos="19" rst="0">
          <comment>PDCCH
0
1</comment>
        </bits>
        <bits access="rw" name="pbch_scale_sel" pos="18" rst="0">
          <comment>PBCH
0
1</comment>
        </bits>
        <bits access="rw" name="pbch_scale1" pos="17:9" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="pbch_scale0" pos="8:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_factor1" protect="rw">
        <bits access="rw" name="pdsch_scale_sel" pos="12" rst="0">
          <comment>PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="pdsch_scale0" pos="11:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_factor2" protect="rw">
        <bits access="rw" name="pdsch_scale2" pos="23:12" rst="0">
          <comment>2</comment>
        </bits>
        <bits access="rw" name="pdsch_scale1" pos="11:0" rst="0">
          <comment>1</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_factor3" protect="rw">
        <bits access="rw" name="pdsch_scale4" pos="23:12" rst="0">
          <comment>4</comment>
        </bits>
        <bits access="rw" name="pdsch_scale3" pos="11:0" rst="0">
          <comment>3</comment>
        </bits>
      </reg>
      <reg name="sd_data_factor0" protect="rw">
        <bits access="rw" name="cr_data_factor" pos="31:16" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
        <bits access="rw" name="ucr_data_factor" pos="15:0" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
      </reg>
      <reg name="sd_data_factor1" protect="rw">
        <bits access="rw" name="cr_data_factor" pos="31:16" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
        <bits access="rw" name="ucr_data_factor" pos="15:0" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
      </reg>
      <reg name="sd_data_factor2" protect="rw">
        <bits access="rw" name="cr_data_factor" pos="31:16" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
        <bits access="rw" name="ucr_data_factor" pos="15:0" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
      </reg>
      <reg name="cnoise_nxt" protect="rw">
        <bits access="rw" name="noise" pos="31:0" rst="0">
          <comment>32Q300~7fff_ffff</comment>
        </bits>
      </reg>
      <reg name="cnoise_agc_nxt" protect="rw">
        <bits access="rw" name="noise_agc" pos="9:0" rst="0">
          <comment>AGC</comment>
        </bits>
      </reg>
      <reg name="cnoise_th" protect="rw">
        <bits access="rw" name="noise_th" pos="15:0" rst="0">
          <comment>PDCCHPBCH</comment>
        </bits>
      </reg>
      <reg name="dnoise_nxt" protect="rw">
        <bits access="rw" name="noise" pos="31:0" rst="0">
          <comment>32Q300~7fff_ffff</comment>
        </bits>
      </reg>
      <reg name="dnoise_agc_nxt" protect="rw">
        <bits access="rw" name="noise_agc" pos="9:0" rst="0">
          <comment>AGC</comment>
        </bits>
      </reg>
      <reg name="dnoise_th" protect="rw">
        <bits access="rw" name="noise_th2" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="noise_th1" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="sd_scaling_bcout0" protect="r">
        <bits access="r" name="cscale_out" pos="11:8" rst="0">
          <comment>PDCCHINDX</comment>
        </bits>
        <bits access="r" name="bscale_out3" pos="7:6" rst="0">
          <comment>PBCHINDX3</comment>
        </bits>
        <bits access="r" name="bscale_out2" pos="5:4" rst="0">
          <comment>PBCHINDX2</comment>
        </bits>
        <bits access="r" name="bscale_out1" pos="3:2" rst="0">
          <comment>PBCHINDX1</comment>
        </bits>
        <bits access="r" name="bscale_out0" pos="1:0" rst="0">
          <comment>PBCHINDX0</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_dout0" protect="r">
        <bits access="r" name="dscale_out7" pos="23:21" rst="0">
          <comment>INDX7</comment>
        </bits>
        <bits access="r" name="dscale_out6" pos="20:18" rst="0">
          <comment>INDX6</comment>
        </bits>
        <bits access="r" name="dscale_out5" pos="17:15" rst="0">
          <comment>INDX5</comment>
        </bits>
        <bits access="r" name="dscale_out4" pos="14:12" rst="0">
          <comment>INDX4</comment>
        </bits>
        <bits access="r" name="dscale_out3" pos="11:9" rst="0">
          <comment>INDX3</comment>
        </bits>
        <bits access="r" name="dscale_out2" pos="8:6" rst="0">
          <comment>INDX2</comment>
        </bits>
        <bits access="r" name="dscale_out1" pos="5:3" rst="0">
          <comment>INDX1</comment>
        </bits>
        <bits access="r" name="dscale_out0" pos="2:0" rst="0">
          <comment>INDX0</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_dout1" protect="r">
        <bits access="r" name="dscale_out15" pos="23:21" rst="0">
          <comment>INDX15</comment>
        </bits>
        <bits access="r" name="dscale_out14" pos="20:18" rst="0">
          <comment>INDX14</comment>
        </bits>
        <bits access="r" name="dscale_out13" pos="17:15" rst="0">
          <comment>INDX13</comment>
        </bits>
        <bits access="r" name="dscale_out12" pos="14:12" rst="0">
          <comment>INDX12</comment>
        </bits>
        <bits access="r" name="dscale_out11" pos="11:9" rst="0">
          <comment>INDX11</comment>
        </bits>
        <bits access="r" name="dscale_out10" pos="8:6" rst="0">
          <comment>INDX10</comment>
        </bits>
        <bits access="r" name="dscale_out9" pos="5:3" rst="0">
          <comment>INDX9</comment>
        </bits>
        <bits access="r" name="dscale_out8" pos="2:0" rst="0">
          <comment>INDX8</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_dout2" protect="r">
        <bits access="r" name="dscale_out23" pos="23:21" rst="0">
          <comment>INDX23</comment>
        </bits>
        <bits access="r" name="dscale_out22" pos="20:18" rst="0">
          <comment>INDX22</comment>
        </bits>
        <bits access="r" name="dscale_out21" pos="17:15" rst="0">
          <comment>INDX21</comment>
        </bits>
        <bits access="r" name="dscale_out20" pos="14:12" rst="0">
          <comment>INDX20</comment>
        </bits>
        <bits access="r" name="dscale_out19" pos="11:9" rst="0">
          <comment>INDX19</comment>
        </bits>
        <bits access="r" name="dscale_out18" pos="8:6" rst="0">
          <comment>INDX18</comment>
        </bits>
        <bits access="r" name="dscale_out17" pos="5:3" rst="0">
          <comment>INDX17</comment>
        </bits>
        <bits access="r" name="dscale_out16" pos="2:0" rst="0">
          <comment>INDX16</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_dout3" protect="r">
        <bits access="r" name="dscale_out31" pos="23:21" rst="0">
          <comment>INDX31</comment>
        </bits>
        <bits access="r" name="dscale_out30" pos="20:18" rst="0">
          <comment>INDX30</comment>
        </bits>
        <bits access="r" name="dscale_out29" pos="17:15" rst="0">
          <comment>INDX29</comment>
        </bits>
        <bits access="r" name="dscale_out28" pos="14:12" rst="0">
          <comment>INDX28</comment>
        </bits>
        <bits access="r" name="dscale_out27" pos="11:9" rst="0">
          <comment>INDX27</comment>
        </bits>
        <bits access="r" name="dscale_out26" pos="8:6" rst="0">
          <comment>INDX26</comment>
        </bits>
        <bits access="r" name="dscale_out25" pos="5:3" rst="0">
          <comment>INDX25</comment>
        </bits>
        <bits access="r" name="dscale_out24" pos="2:0" rst="0">
          <comment>INDX24</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_dout4" protect="r">
        <bits access="r" name="dscale_out34" pos="8:6" rst="0">
          <comment>INDX34</comment>
        </bits>
        <bits access="r" name="dscale_out33" pos="5:3" rst="0">
          <comment>INDX33</comment>
        </bits>
        <bits access="r" name="dscale_out32" pos="2:0" rst="0">
          <comment>INDX32</comment>
        </bits>
      </reg>
      <reg name="hq_hb_sta" protect="rw">
        <bits access="rc" name="hb15_sta" pos="15" rst="0">
          <comment>bit type is changed from rw1c to rc.
          15HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb14_sta" pos="14" rst="0">
          <comment>bit type is changed from rw1c to rc.
          14HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb13_sta" pos="13" rst="0">
          <comment>bit type is changed from rw1c to rc.
          13HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb12_sta" pos="12" rst="0">
          <comment>bit type is changed from rw1c to rc.
          12HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb11_sta" pos="11" rst="0">
          <comment>bit type is changed from rw1c to rc.
          11HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb10_sta" pos="10" rst="0">
          <comment>bit type is changed from rw1c to rc.
          10HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb9_sta" pos="9" rst="0">
          <comment>bit type is changed from rw1c to rc.
          9HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb8_sta" pos="8" rst="0">
          <comment>bit type is changed from rw1c to rc.
          8HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb7_sta" pos="7" rst="0">
          <comment>bit type is changed from rw1c to rc.
          7HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb6_sta" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          6HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb5_sta" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          5HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb4_sta" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          4HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb3_sta" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          3HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb2_sta" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          2HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb1_sta" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb0_sta" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0HARQBUFFER
0:
1:</comment>
        </bits>
      </reg>
      <reg name="hq_hb_proc0" protect="r">
        <bits access="r" name="hb7_proc" pos="31:28" rst="0">
          <comment>7HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb6_proc" pos="27:24" rst="0">
          <comment>6HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb5_proc" pos="23:20" rst="0">
          <comment>5HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb4_proc" pos="19:16" rst="0">
          <comment>4HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb3_proc" pos="15:12" rst="0">
          <comment>3HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb2_proc" pos="11:8" rst="0">
          <comment>2HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb1_proc" pos="7:4" rst="0">
          <comment>1HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb0_proc" pos="3:0" rst="0">
          <comment>0HARQBUFFER:0~15</comment>
        </bits>
      </reg>
      <reg name="hq_hb_proc1" protect="r">
        <bits access="r" name="hb15_proc" pos="31:28" rst="0">
          <comment>15HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb14_proc" pos="27:24" rst="0">
          <comment>14HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb13_proc" pos="23:20" rst="0">
          <comment>13HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb12_proc" pos="19:16" rst="0">
          <comment>12HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb11_proc" pos="15:12" rst="0">
          <comment>11HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb10_proc" pos="11:8" rst="0">
          <comment>10HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb9_proc" pos="7:4" rst="0">
          <comment>9HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb8_proc" pos="3:0" rst="0">
          <comment>8HARQBUFFER:0~15</comment>
        </bits>
      </reg>
      <reg name="turbo_para" protect="rw">
        <bits access="rw" name="norm_en2" pos="17" rst="0">
          <comment>64QAM
02
1</comment>
        </bits>
        <bits access="rw" name="norm_en1" pos="16" rst="0">
          <comment>16QAM
02
1</comment>
        </bits>
        <bits access="rw" name="norm_en0" pos="15" rst="0">
          <comment>QPSK
02
1</comment>
        </bits>
        <bits access="rw" name="shift_en2" pos="14" rst="0">
          <comment>64QAM
0
1</comment>
        </bits>
        <bits access="rw" name="shift_en1" pos="13" rst="1">
          <comment>16QAM
0
1</comment>
        </bits>
        <bits access="rw" name="shift_en0" pos="12" rst="1">
          <comment>QPSK
0
1</comment>
        </bits>
        <bits access="rw" name="shift_iternum2" pos="11:8" rst="5">
          <comment>2</comment>
        </bits>
        <bits access="rw" name="shift_iternum1" pos="7:4" rst="2">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="iter_num_max" pos="3:0" rst="8">
          <comment>1
90~8</comment>
        </bits>
      </reg>
      <reg name="turbo_iter" protect="r">
        <bits access="r" name="real_iter3" pos="15:12" rst="0">
          <comment>PAG-1</comment>
        </bits>
        <bits access="r" name="real_iter2" pos="11:8" rst="0">
          <comment>SI-1</comment>
        </bits>
        <bits access="r" name="real_iter1" pos="7:4" rst="0">
          <comment>PDS-1</comment>
        </bits>
        <bits access="r" name="real_iter0" pos="3:0" rst="0">
          <comment>PDS-1</comment>
        </bits>
      </reg>
      <reg name="vit_par" protect="rw">
        <bits access="rw" name="mask_en" pos="5" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="crc_type" pos="4" rst="0">
          <comment>CRC
0CRC16
1CRC24A</comment>
        </bits>
        <bits access="rw" name="dmav_en" pos="3" rst="0">
          <comment>DMA
0
1</comment>
        </bits>
        <bits access="rw" name="intv_en" pos="2" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="vit_itnum" pos="1:0" rst="1">
          <comment>VIT
0:1
1:2
2:3
3:4</comment>
        </bits>
      </reg>
      <reg name="vit_faconf" protect="rw">
        <bits access="rw" name="crc_mask" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="fa_en" pos="8" rst="0">
          <comment>PDCCHfalse alarm</comment>
        </bits>
        <bits access="rw" name="fa_th" pos="7:0" rst="128">
          <comment>PDCCHfalse alarm(U8Q7)</comment>
        </bits>
      </reg>
      <reg name="vit_len" protect="rw">
        <bits access="rw" name="vit_len_vit_len" pos="9:0" rst="0">
          <comment>VIT</comment>
        </bits>
      </reg>
      <reg name="vit_start" protect="rw">
        <bits access="rw" name="vit_start_vit_start" pos="0" rst="0">
          <comment>VIT
0
1</comment>
        </bits>
      </reg>
      <reg name="vit_flag" protect="rw">
        <bits access="rc" name="pdsch_zero_flag" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          VIT CRCCRC
0
1</comment>
        </bits>
        <bits access="rc" name="vit_crc_flag" pos="1" rst="1">
          <comment>bit type is changed from rw1c to rc.
          VIT CRC
0
1</comment>
        </bits>
        <bits access="rc" name="int_vflag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PBCH
0
1</comment>
        </bits>
      </reg>
      <reg name="vit_faout" protect="rw">
        <bits access="rw" name="dci_fa_zero" pos="15:8" rst="0">
          <comment>DCI false alarm0</comment>
        </bits>
        <bits access="r" name="dci_fa" pos="7:0" rst="0">
          <comment>DCI false alarm</comment>
        </bits>
      </reg>
      <reg name="cfi_out" protect="r">
        <bits access="r" name="cfi_out_cfi_out" pos="2:0" rst="0">
          <comment>CFI
1~41.4M1</comment>
        </bits>
      </reg>
      <reg name="hi_out" protect="r">
        <bits access="r" name="hi1_out" pos="1" rst="0">
          <comment>HI1</comment>
        </bits>
        <bits access="r" name="hi0_out" pos="0" rst="0">
          <comment>HI0</comment>
        </bits>
      </reg>
      <reg name="sw_cin_nxt" protect="rw">
        <bits access="rw" name="sw_cin" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="sw_din_nxt" protect="rw">
        <bits access="rw" name="sw_din" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="sw_cout" protect="r">
        <bits access="r" name="sw_cout_sw_cout" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="sw_dout" protect="r">
        <bits access="r" name="sw_dout_sw_dout" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="pds_rep_num" protect="r">
        <bits access="r" name="pds15_rep_num" pos="31:30" rst="0">
          <comment>PDSCH 15</comment>
        </bits>
        <bits access="r" name="pds14_rep_num" pos="29:28" rst="0">
          <comment>PDSCH 14</comment>
        </bits>
        <bits access="r" name="pds13_rep_num" pos="27:26" rst="0">
          <comment>PDSCH 13</comment>
        </bits>
        <bits access="r" name="pds12_rep_num" pos="25:24" rst="0">
          <comment>PDSCH 12</comment>
        </bits>
        <bits access="r" name="pds11_rep_num" pos="23:22" rst="0">
          <comment>PDSCH 11</comment>
        </bits>
        <bits access="r" name="pds10_rep_num" pos="21:20" rst="0">
          <comment>PDSCH 10</comment>
        </bits>
        <bits access="r" name="pds9_rep_num" pos="19:18" rst="0">
          <comment>PDSCH 9</comment>
        </bits>
        <bits access="r" name="pds8_rep_num" pos="17:16" rst="0">
          <comment>PDSCH 8</comment>
        </bits>
        <bits access="r" name="pds7_rep_num" pos="15:14" rst="0">
          <comment>PDSCH 7</comment>
        </bits>
        <bits access="r" name="pds6_rep_num" pos="13:12" rst="0">
          <comment>PDSCH 6</comment>
        </bits>
        <bits access="r" name="pds5_rep_num" pos="11:10" rst="0">
          <comment>PDSCH 5</comment>
        </bits>
        <bits access="r" name="pds4_rep_num" pos="9:8" rst="0">
          <comment>PDSCH 4</comment>
        </bits>
        <bits access="r" name="pds3_rep_num" pos="7:6" rst="0">
          <comment>PDSCH 3</comment>
        </bits>
        <bits access="r" name="pds2_rep_num" pos="5:4" rst="0">
          <comment>PDSCH 2</comment>
        </bits>
        <bits access="r" name="pds1_rep_num" pos="3:2" rst="0">
          <comment>PDSCH 1</comment>
        </bits>
        <bits access="r" name="pds0_rep_num" pos="1:0" rst="0">
          <comment>PDSCH 0</comment>
        </bits>
      </reg>
      <reg name="si_rep_num" protect="r">
        <bits access="r" name="si1_rep_num" pos="3:2" rst="0">
          <comment>SI1</comment>
        </bits>
        <bits access="r" name="si0_rep_num" pos="1:0" rst="0">
          <comment>SI0</comment>
        </bits>
      </reg>
      <reg name="pbch_rep_num" protect="r">
        <bits access="r" name="pbch_rep_num_pbch_rep_num" pos="1:0" rst="0">
          <comment>PBCH</comment>
        </bits>
      </reg>
      <reg name="rtctrl_cfg" protect="rw">
        <bits access="rw" name="rtctrl_cfg_rtctrl_cfg" pos="17:0" rst="50000">
          <comment/>
        </bits>
      </reg>
      <reg name="cabis_enbl_nxt" protect="rw">
        <bits access="rw" name="abis_portsel2" pos="11:10" rst="0">
          <comment>2
02port0port14port0port1port2port3
12port04port0port2port3
22port14port1port2port3</comment>
        </bits>
        <bits access="rw" name="abis_portsel1" pos="9:8" rst="0">
          <comment>1
02port0port14port0port1port2port3
12port04port0port2port3
22port14port1port2port3</comment>
        </bits>
        <bits access="rw" name="abis_portsel0" pos="7:6" rst="0">
          <comment>02port0port14port0port1port2port3
12port04port0port2port3
22port14port1port2port3</comment>
        </bits>
        <bits access="rw" name="cmc_en" pos="5" rst="0">
          <comment>MultiCell
0SingalCell
1MultiCell</comment>
        </bits>
        <bits access="rw" name="cabis_sel" pos="4" rst="0">
          <comment>ABIS
0
1DLFFT</comment>
        </bits>
        <bits access="rw" name="cabis_en" pos="3" rst="0">
          <comment>ABIS
0
1</comment>
        </bits>
        <bits access="rw" name="cabis_sdden" pos="2" rst="0">
          <comment>ABISSD PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="cabis_sdcen" pos="1" rst="0">
          <comment>ABISSD MPDCCH
0
1</comment>
        </bits>
        <bits access="rw" name="cabis_sdben" pos="0" rst="0">
          <comment>ABISSD PBCH
0
1</comment>
        </bits>
      </reg>
      <reg name="cabis_cfg_nxt" protect="rw">
        <bits access="rw" name="cabis_num" pos="29:28" rst="0">
          <comment>000
011
102
0</comment>
        </bits>
        <bits access="rw" name="cabis_txnum_next2" pos="27:26" rst="0">
          <comment>2
001port
012port
104port
1port</comment>
        </bits>
        <bits access="rw" name="cabis_txnum_next1" pos="25:24" rst="0">
          <comment>1
001port
012port
104port
1port</comment>
        </bits>
        <bits access="rw" name="cabis_nrb_next2" pos="23:21" rst="0">
          <comment>2
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
6prb</comment>
        </bits>
        <bits access="rw" name="cabis_nrb_next1" pos="20:18" rst="0">
          <comment>1
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
6prb</comment>
        </bits>
        <bits access="rw" name="cabis_cellid_next2" pos="17:9" rst="0">
          <comment>2 CELL ID</comment>
        </bits>
        <bits access="rw" name="cabis_cellid_next1" pos="8:0" rst="0">
          <comment>1 CELL ID</comment>
        </bits>
      </reg>
      <reg name="cabis_dly1_nxt" protect="rw">
        <bits access="rw" name="cabis_dly_next1" pos="18:0" rst="0">
          <comment>1TS</comment>
        </bits>
      </reg>
      <reg name="cabis_dly2_nxt" protect="rw">
        <bits access="rw" name="cabis_dly_next2" pos="18:0" rst="0">
          <comment>2TS</comment>
        </bits>
      </reg>
      <reg name="cabis_shft_nxt" protect="r">
        <bits access="r" name="cabis_shft_next3" pos="11:8" rst="0">
          <comment>ABIS31+2</comment>
        </bits>
        <bits access="r" name="cabis_shft_next2" pos="7:4" rst="0">
          <comment>ABIS22</comment>
        </bits>
        <bits access="r" name="cabis_shft_next1" pos="3:0" rst="0">
          <comment>ABIS11</comment>
        </bits>
      </reg>
      <reg name="dabis_enbl_nxt" protect="rw">
        <bits access="rw" name="abis_portsel2" pos="10:9" rst="0">
          <comment>2
02port0port14port0port1port2port3
12port04port0port2port3
22port14port1port2port3</comment>
        </bits>
        <bits access="rw" name="abis_portsel1" pos="8:7" rst="0">
          <comment>1
02port0port14port0port1port2port3
12port04port0port2port3
22port14port1port2port3</comment>
        </bits>
        <bits access="rw" name="abis_portsel0" pos="6:5" rst="0">
          <comment>02port0port14port0port1port2port3
12port04port0port2port3
22port14port1port2port3</comment>
        </bits>
        <bits access="rw" name="dabis_sel" pos="4" rst="0">
          <comment>ABIS
0
1DLFFT</comment>
        </bits>
        <bits access="rw" name="dabis_en" pos="3" rst="0">
          <comment>ABIS
0
1</comment>
        </bits>
        <bits access="rw" name="dabis_sdden" pos="2" rst="0">
          <comment>ABISSD PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="dabis_sdcen" pos="1" rst="0">
          <comment>ABISSD MPDCCH
0
1</comment>
        </bits>
        <bits access="rw" name="dabis_sdben" pos="0" rst="0">
          <comment>ABISSD PBCH
0
1</comment>
        </bits>
      </reg>
      <reg name="dabis_cfg_nxt" protect="rw">
        <bits access="rw" name="dabis_num" pos="29:28" rst="0">
          <comment>000
011
102
0</comment>
        </bits>
        <bits access="rw" name="dabis_txnum_next2" pos="27:26" rst="0">
          <comment>2
001port
012port
104port
1port</comment>
        </bits>
        <bits access="rw" name="dabis_txnum_next1" pos="25:24" rst="0">
          <comment>2
001port
012port
104port
1port</comment>
        </bits>
        <bits access="rw" name="dabis_nrb_next2" pos="23:21" rst="0">
          <comment>2
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
6prb</comment>
        </bits>
        <bits access="rw" name="dabis_nrb_next1" pos="20:18" rst="0">
          <comment>1
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
6prb</comment>
        </bits>
        <bits access="rw" name="dabis_cellid_next2" pos="17:9" rst="0">
          <comment>2 CELL ID</comment>
        </bits>
        <bits access="rw" name="dabis_cellid_next1" pos="8:0" rst="0">
          <comment>1 CELL ID</comment>
        </bits>
      </reg>
      <reg name="dabis_dly1_nxt" protect="rw">
        <bits access="rw" name="dabis_dly_next1" pos="18:0" rst="0">
          <comment>1TS</comment>
        </bits>
      </reg>
      <reg name="dabis_dly2_nxt" protect="rw">
        <bits access="rw" name="dabis_dly_next2" pos="18:0" rst="0">
          <comment>2TS</comment>
        </bits>
      </reg>
      <reg name="dabis_shft_nxt" protect="r">
        <bits access="r" name="dabis_shft_next3" pos="11:8" rst="0">
          <comment>ABIS31+2</comment>
        </bits>
        <bits access="r" name="dabis_shft_next2" pos="7:4" rst="0">
          <comment>ABIS22</comment>
        </bits>
        <bits access="r" name="dabis_shft_next1" pos="3:0" rst="0">
          <comment>ABIS11</comment>
        </bits>
      </reg>
      <reg name="reis_conf" protect="rw">
        <bits access="rw" name="reis_en" pos="4" rst="0">
          <comment>REIS
0
1</comment>
        </bits>
        <bits access="rw" name="reis_num" pos="3:0" rst="0">
          <comment>REISNUM</comment>
        </bits>
      </reg>
      <reg name="reis_pos0" protect="rw">
        <bits access="rw" name="reis_shift1" pos="31:28" rst="0">
          <comment>REIS1</comment>
        </bits>
        <bits access="rw" name="reis_re1" pos="26:16" rst="0">
          <comment>REIS1RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_shift0" pos="15:12" rst="0">
          <comment>REIS0</comment>
        </bits>
        <bits access="rw" name="reis_re0" pos="10:0" rst="0">
          <comment>REIS0RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="reis_pos1" protect="rw">
        <bits access="rw" name="reis_shift3" pos="31:28" rst="0">
          <comment>REIS3</comment>
        </bits>
        <bits access="rw" name="reis_re3" pos="26:16" rst="0">
          <comment>REIS3RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_shift2" pos="15:12" rst="0">
          <comment>REIS2</comment>
        </bits>
        <bits access="rw" name="reis_re2" pos="10:0" rst="0">
          <comment>REIS2RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="reis_pos2" protect="rw">
        <bits access="rw" name="reis_shift5" pos="31:28" rst="0">
          <comment>REIS5</comment>
        </bits>
        <bits access="rw" name="reis_re5" pos="26:16" rst="0">
          <comment>REIS5RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_shift4" pos="15:12" rst="0">
          <comment>REIS4</comment>
        </bits>
        <bits access="rw" name="reis_re4" pos="10:0" rst="0">
          <comment>REIS4RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="reis_pos3" protect="rw">
        <bits access="rw" name="reis_shift7" pos="31:28" rst="0">
          <comment>REIS7</comment>
        </bits>
        <bits access="rw" name="reis_re7" pos="26:16" rst="0">
          <comment>REIS7RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_shift6" pos="15:12" rst="0">
          <comment>REIS6</comment>
        </bits>
        <bits access="rw" name="reis_re6" pos="10:0" rst="0">
          <comment>REIS6RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="rbis_par" protect="rw">
        <bits access="rw" name="rbis_portsel" pos="31" rst="0">
          <comment>2ABISPORT
0port0
1port1</comment>
        </bits>
        <bits access="rw" name="rbis_en" pos="30" rst="0">
          <comment>RBIS
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_sdden" pos="29" rst="0">
          <comment>RBISSD PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_sdcen" pos="28" rst="0">
          <comment>RBISSD MPDCCH
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_sdben" pos="27" rst="0">
          <comment>RBISSD PBCH
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_posen" pos="26" rst="0">
          <comment>RBIS
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_num" pos="25:23" rst="0">
          <comment>RBIS
01
12
23
34
45</comment>
        </bits>
        <bits access="rw" name="rbis_dipos" pos="22:16" rst="0">
          <comment>RBIS</comment>
        </bits>
        <bits access="rw" name="rbis_factor" pos="15:0" rst="0">
          <comment>RBIS</comment>
        </bits>
      </reg>
      <reg name="rbis_posout0" protect="r">
        <bits access="r" name="rbis_posout3" pos="27:21" rst="0">
          <comment>RBIS0~99</comment>
        </bits>
        <bits access="r" name="rbis_posout2" pos="20:14" rst="0">
          <comment>RBIS0~99</comment>
        </bits>
        <bits access="r" name="rbis_posout1" pos="13:7" rst="0">
          <comment>RBIS0~99</comment>
        </bits>
        <bits access="r" name="rbis_posout0_rbis_posout0" pos="6:0" rst="0">
          <comment>RBIS0~99</comment>
        </bits>
      </reg>
      <reg name="rbis_posout1" protect="r">
        <bits access="r" name="rbis_posout4" pos="6:0" rst="0">
          <comment>RBIS0~99</comment>
        </bits>
      </reg>
      <reg name="rbis_ave" protect="r">
        <bits access="r" name="rbis_ave_rbis_ave" pos="31:0" rst="0">
          <comment>RBIS</comment>
        </bits>
      </reg>
      <reg name="rbis_max" protect="r">
        <bits access="r" name="rbis_max_rbis_max" pos="24:0" rst="0">
          <comment>RBIS</comment>
        </bits>
      </reg>
      <reg name="pbml_cfg_nxt" protect="rw">
        <bits access="rw" name="pbml_en" pos="20" rst="0">
          <comment>PBML
0
1</comment>
        </bits>
        <bits access="rw" name="llr_cal_len" pos="19:14" rst="0">
          <comment>LLR</comment>
        </bits>
        <bits access="rw" name="llr_pos_sta" pos="13:8" rst="0">
          <comment>LLR</comment>
        </bits>
        <bits access="rw" name="llr_alpha" pos="7:0" rst="0">
          <comment>LLR
0~255</comment>
        </bits>
      </reg>
      <reg name="ctrl_state" protect="r">
        <bits access="r" name="ctrl_state_ctrl_state" pos="25:0" rst="1">
          <comment/>
        </bits>
      </reg>
      <reg name="data_state" protect="r">
        <bits access="r" name="data_state_data_state" pos="25:0" rst="1">
          <comment/>
        </bits>
      </reg>
      <reg name="frame_ccnt_out" protect="r">
        <bits access="r" name="ssfn_cnt" pos="31:16" rst="0">
          <comment>0~65535</comment>
        </bits>
        <bits access="r" name="rf_cnt" pos="13:4" rst="0">
          <comment>0~1023</comment>
        </bits>
        <bits access="r" name="sf_cnt" pos="3:0" rst="0">
          <comment>0~9</comment>
        </bits>
      </reg>
      <reg name="frame_dcnt_out" protect="r">
        <bits access="r" name="ssfn_cnt" pos="31:16" rst="0">
          <comment>0~65535</comment>
        </bits>
        <bits access="r" name="rf_cnt" pos="13:4" rst="0">
          <comment>0~1023</comment>
        </bits>
        <bits access="r" name="sf_cnt" pos="3:0" rst="0">
          <comment>0~9</comment>
        </bits>
      </reg>
      <reg name="pds0_harqin0_info" protect="r">
        <bits access="r" name="pds_len0" pos="25:16" rst="0">
          <comment>CB0HARQIN MEM0</comment>
        </bits>
        <bits access="r" name="pds_ini0" pos="9:0" rst="0">
          <comment>CB0HARQIN MEM0</comment>
        </bits>
      </reg>
      <reg name="pds0_harqin1_info" protect="r">
        <bits access="r" name="pds_e0" pos="31:16" rst="0">
          <comment>CB0</comment>
        </bits>
        <bits access="r" name="pds_ini1" pos="12:0" rst="0">
          <comment>CB0HARQIN MEM1</comment>
        </bits>
      </reg>
      <reg name="pds1_harqin0_info" protect="r">
        <bits access="r" name="pds_len0" pos="25:16" rst="0">
          <comment>CB1HARQIN MEM0</comment>
        </bits>
        <bits access="r" name="pds_ini0" pos="9:0" rst="0">
          <comment>CB1HARQIN MEM0</comment>
        </bits>
      </reg>
      <reg name="pds1_harqin1_info" protect="r">
        <bits access="r" name="pds_e0" pos="31:16" rst="0">
          <comment>CB1</comment>
        </bits>
        <bits access="r" name="pds_ini1" pos="12:0" rst="0">
          <comment>CB1HARQIN MEM1</comment>
        </bits>
      </reg>
      <reg name="si_harqin0_info" protect="r">
        <bits access="r" name="si_len0" pos="25:16" rst="0">
          <comment>SICB1HARQIN MEM0</comment>
        </bits>
        <bits access="r" name="si_ini0" pos="9:0" rst="0">
          <comment>SICB1HARQIN MEM0</comment>
        </bits>
      </reg>
      <reg name="si_harqin1_info" protect="r">
        <bits access="r" name="si_e0" pos="31:16" rst="0">
          <comment>SICB1</comment>
        </bits>
        <bits access="r" name="si_ini1" pos="12:0" rst="0">
          <comment>SICB1HARQIN MEM1</comment>
        </bits>
      </reg>
      <reg name="pag_harqin0_info" protect="r">
        <bits access="r" name="pag_len0" pos="25:16" rst="0">
          <comment>PAGINGCB1HARQIN MEM0</comment>
        </bits>
        <bits access="r" name="pag_ini0" pos="9:0" rst="0">
          <comment>PAGINGCB1HARQIN MEM0</comment>
        </bits>
      </reg>
      <reg name="pag_harqin1_info" protect="r">
        <bits access="r" name="pag_e0" pos="31:16" rst="0">
          <comment>PAGINGCB1</comment>
        </bits>
        <bits access="r" name="pag_ini1" pos="12:0" rst="0">
          <comment>PAGINGCB1HARQIN MEM1</comment>
        </bits>
      </reg>
      <reg name="cabis_shft_out" protect="r">
        <bits access="r" name="cabis_shft3" pos="11:8" rst="0">
          <comment>ABIS31+2</comment>
        </bits>
        <bits access="r" name="cabis_shft2" pos="7:4" rst="0">
          <comment>ABIS22</comment>
        </bits>
        <bits access="r" name="cabis_shft1" pos="3:0" rst="0">
          <comment>ABIS11</comment>
        </bits>
      </reg>
      <reg name="dabis_shft_out" protect="r">
        <bits access="r" name="dabis_shft3" pos="11:8" rst="0">
          <comment>ABIS31+2</comment>
        </bits>
        <bits access="r" name="dabis_shft2" pos="7:4" rst="0">
          <comment>ABIS22</comment>
        </bits>
        <bits access="r" name="dabis_shft1" pos="3:0" rst="0">
          <comment>ABIS11</comment>
        </bits>
      </reg>
      <reg name="mc_dly1_nxt" protect="rw">
        <bits access="rw" name="mc_dly1" pos="18:0" rst="0">
          <comment>1TS</comment>
        </bits>
      </reg>
      <reg name="mc_dly2_nxt" protect="rw">
        <bits access="rw" name="mc_dly2" pos="18:0" rst="0">
          <comment>2TS</comment>
        </bits>
      </reg>
      <reg name="mc_dlyth_nxt" protect="rw">
        <bits access="rw" name="mc_dlyth" pos="9:0" rst="0">
          <comment>TS</comment>
        </bits>
      </reg>
      <hole size="8384096"/>
      <reg name="cfhmem1" protect="rw">
        <bits access="rw" name="cfhmem1_cfhmem1" pos="29:0" rst="0">
      </bits>
      </reg>
      <hole size="524256"/>
      <reg name="cfhmem2" protect="rw">
        <bits access="rw" name="cfhmem2_cfhmem2" pos="29:0" rst="0">
      </bits>
      </reg>
      <hole size="524256"/>
      <reg name="crsmem1" protect="rw">
        <bits access="rw" name="crsmem1_re" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="crsmem1_im" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="crsmem2" protect="rw">
        <bits access="rw" name="crsmem2_re" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="crsmem2_im" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="clsmem" protect="rw">
        <bits access="rw" name="clsmem_re" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="clsmem_im" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="458720"/>
      <reg name="ursmem" protect="rw">
        <bits access="rw" name="ursmem_re" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="ursmem_im" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="ulsmem" protect="rw">
        <bits access="rw" name="ulsmem_re" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="ulsmem_im" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="pwr_mem1" protect="rw">
        <bits access="rw" name="pwr_mem1_pwr_mem1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="pwr_mem2" protect="rw">
        <bits access="rw" name="pwr_mem2_pwr_mem2" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="cell_qfmem1" protect="rw">
        <bits access="rw" name="cell_qfmem1_re" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="cell_qfmem1_im" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="98272"/>
      <reg name="cell_qfmem2" protect="rw">
        <bits access="rw" name="cell_qfmem2_re" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="cell_qfmem2_im" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="98272"/>
      <reg name="ue_qfmem1" protect="rw">
        <bits access="rw" name="ue_qfmem1_re" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="ue_qfmem1_im" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="ue_qfmem2" protect="rw">
        <bits access="rw" name="ue_qfmem2_re" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="ue_qfmem2_im" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="cg_qtmem1" protect="rw">
        <bits access="rw" name="cg_qtmem1_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="cg_qtmem1_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="16352"/>
      <reg name="cg_qtmem2" protect="rw">
        <bits access="rw" name="cg_qtmem2_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="cg_qtmem2_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="16352"/>
      <reg name="ct_qtmem1" protect="rw">
        <bits access="rw" name="ct_qtmem1_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="ct_qtmem1_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="16352"/>
      <reg name="ct_qtmem2" protect="rw">
        <bits access="rw" name="ct_qtmem2_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="ct_qtmem2_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="16352"/>
      <reg name="dt_qtmem1" protect="rw">
        <bits access="rw" name="dt_qtmem1_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="dt_qtmem1_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="dt_qtmem2" protect="rw">
        <bits access="rw" name="dt_qtmem2_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="dt_qtmem2_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="dcg_qtmem1" protect="rw">
        <bits access="rw" name="dcg_qtmem1_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="dcg_qtmem1_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="dcg_qtmem2" protect="rw">
        <bits access="rw" name="dcg_qtmem2_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="dcg_qtmem2_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="agc_cls_mem" protect="rw">
        <bits access="rw" name="agc_cls_mem_2" pos="31:22" rst="0">
      </bits>
        <bits access="rw" name="agc_cls_mem_1" pos="15:6" rst="0">
      </bits>
      </reg>
      <hole size="2016"/>
      <reg name="agc_uls_mem" protect="rw">
        <bits access="rw" name="agc_uls_mem_2" pos="31:22" rst="0">
      </bits>
        <bits access="rw" name="agc_uls_mem_1" pos="15:6" rst="0">
      </bits>
      </reg>
      <hole size="2016"/>
      <reg name="agc_cfh_mem1" protect="rw">
        <bits access="rw" name="agc_cfh_mem1_2" pos="31:22" rst="0">
      </bits>
        <bits access="rw" name="agc_cfh_mem1_1" pos="15:6" rst="0">
      </bits>
      </reg>
      <hole size="2016"/>
      <reg name="agc_cfh_mem2" protect="rw">
        <bits access="rw" name="agc_cfh_mem2_2" pos="31:22" rst="0">
      </bits>
        <bits access="rw" name="agc_cfh_mem2_1" pos="15:6" rst="0">
      </bits>
      </reg>
      <hole size="2016"/>
      <reg name="agc_ufh_mem1" protect="rw">
        <bits access="rw" name="agc_ufh_mem1_2" pos="31:22" rst="0">
      </bits>
        <bits access="rw" name="agc_ufh_mem1_1" pos="15:6" rst="0">
      </bits>
      </reg>
      <hole size="2016"/>
      <reg name="agc_ufh_mem2" protect="rw">
        <bits access="rw" name="agc_ufh_mem2_2" pos="31:22" rst="0">
      </bits>
        <bits access="rw" name="agc_ufh_mem2_1" pos="15:6" rst="0">
      </bits>
      </reg>
      <hole size="2016"/>
      <reg name="gold_mem1" protect="rw">
        <bits access="rw" name="gold_mem1_gold_mem1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="2016"/>
      <reg name="gold_mem2" protect="rw">
        <bits access="rw" name="gold_mem2_gold_mem2" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="18400"/>
      <reg name="ufhmem" protect="rw">
        <bits access="rw" name="ufhmem_ufhmem" pos="29:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="pbch_t_qtmem1" protect="rw">
        <bits access="rw" name="pbch_t_qtmem1_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="pbch_t_qtmem1_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="16352"/>
      <reg name="pbch_t_qtmem2" protect="rw">
        <bits access="rw" name="pbch_t_qtmem2_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="pbch_t_qtmem2_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="16352"/>
      <reg name="csi_in_mem" protect="rw">
        <bits access="rw" name="csimem_re" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="csimem_im" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="pmi_mem" protect="rw">
        <bits access="rw" name="pmi_mem_pmi_mem" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="229344"/>
      <reg name="cell_qfmem3" protect="rw">
        <bits access="rw" name="cell_qfmem3_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="cell_qfmem3_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="cg_qtmem3" protect="rw">
        <bits access="rw" name="cg_qtmem3_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="cg_qtmem3_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="ct_qtmem3" protect="rw">
        <bits access="rw" name="ct_qtmem3_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="ct_qtmem3_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="dt_qtmem3" protect="rw">
        <bits access="rw" name="dt_qtmem3_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="dt_qtmem3_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="dcg_qtmem3" protect="rw">
        <bits access="rw" name="dcg_qtmem3_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="dcg_qtmem3_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="360416"/>
      <reg name="pbch_t_qtmem3" protect="rw">
        <bits access="rw" name="pbch_t_qtmem3_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="pbch_t_qtmem3_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="4423648"/>
      <reg name="sdmemch0" protect="rw">
        <bits access="rw" name="sdmemch0_sdmemch0" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="sdmemch1" protect="rw">
        <bits access="rw" name="sdmemch1_sdmemch1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="sdmemcg0" protect="rw">
        <bits access="rw" name="sdmemcg0_sdmemcg0" pos="31:11" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="sdmemcg1" protect="rw">
        <bits access="rw" name="sdmemcg1_sdmemcg1" pos="31:11" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="sdmemdh0" protect="rw">
        <bits access="rw" name="sdmemdh0_sdmemdh0" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="sdmemdh1" protect="rw">
        <bits access="rw" name="sdmemdh1_sdmemdh1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="sdmemdg0" protect="rw">
        <bits access="rw" name="sdmemdg0_sdmemdg0" pos="31:11" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="sdmemdg1" protect="rw">
        <bits access="rw" name="sdmemdg1_sdmemdg1" pos="31:11" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="sdmemdg2" protect="r">
        <bits access="r" name="sdmemdg2_sdmemdg2" pos="31:11" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="sdmemdg3" protect="r">
        <bits access="r" name="sdmemdg3_sdmemdg3" pos="31:11" rst="0">
      </bits>
      </reg>
      <hole size="6717408"/>
      <reg name="pdcch_memin" protect="rw">
        <bits access="rw" name="pdcch_memin_2" pos="31:21" rst="0">
      </bits>
        <bits access="rw" name="pdcch_memin_1" pos="15:5" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="pdcch_memgold" protect="rw">
        <bits access="rw" name="pdcch_memgold_pdcch_memgold" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="16352"/>
      <reg name="pdcch_mempbch0" protect="rw">
        <bits access="rw" name="pdcch_mempbch0_pdcch_mempbch0" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="pdcch_mempbch1" protect="rw">
        <bits access="rw" name="pdcch_mempbch1_pdcch_mempbch1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="pdcch_mempbch2" protect="rw">
        <bits access="rw" name="pdcch_mempbch2_pdcch_mempbch2" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="dci0_out1" protect="rw">
        <bits access="rw" name="dci0_out1_dci0_out1" pos="31:0" rst="0">
          <comment>DCI032</comment>
        </bits>
      </reg>
      <reg name="dci0_out2" protect="rw">
        <bits access="rw" name="dci0_out2_dci0_out2" pos="31:0" rst="0">
          <comment>DCI032</comment>
        </bits>
      </reg>
      <reg name="dci0_pwr" protect="rw">
        <bits access="rw" name="dci_pwr" pos="25:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci0_fa" protect="rw">
        <bits access="rw" name="dci_fa_zero" pos="15:8" rst="0">
          <comment>DCI false alarm0</comment>
        </bits>
        <bits access="rw" name="dci_fa" pos="7:0" rst="0">
          <comment>DCI false alarm</comment>
        </bits>
      </reg>
      <reg name="dci0_info1" protect="rw">
        <bits access="rw" name="ant_sel" pos="28" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="rw" name="order_flag" pos="27" rst="0">
          <comment>DCI1A
0ORDER
1ORDER</comment>
        </bits>
        <bits access="rw" name="sps_ind" pos="26:25" rst="0">
          <comment>SPS-C-RNTI
0
1
2
3</comment>
        </bits>
        <bits access="rw" name="dci_type" pos="24:21" rst="0">
          <comment>DCI
0:DCI0
1:DCI1
2:DCI1A
3:DCI1B
4:DCI1C
5:DCI1D
6:DCI2
7:DCI2A
8:DCI2B
9:DCI2C
10:DCI3/3A</comment>
        </bits>
        <bits access="rw" name="rnti_ind" pos="20:17" rst="0">
          <comment>DCI RNTI
0RNTI0SI-RNTI
1RNTI1P-RNTI
2RNTI2RA-RNTI
3RNTI3C-RNTI
4RNTI4SPS-RNTI
5RNTI5T-RNTI
6RNTI6TPCS-RNTI
7RNTI7TPCC-RNTI
8RNTI8G-RNTI
9RNTI9SC-RNTI
10RNTI10SC-N-RNTI</comment>
        </bits>
        <bits access="rw" name="comm_ue" pos="16" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="rw" name="dci_stapos" pos="15:9" rst="0">
          <comment>DCI(index:0~23)</comment>
        </bits>
        <bits access="rw" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="rw" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci0_info2" protect="rw">
        <bits access="rw" name="pmi_confm" pos="31" rst="0">
          <comment>PMIDCIPMI
0DCIPMI
1PMI</comment>
        </bits>
        <bits access="rw" name="hq_proc" pos="30:27" rst="0">
          <comment>HARQ:0~15</comment>
        </bits>
        <bits access="rw" name="pmi_indx" pos="26:23" rst="0">
          <comment>tx2:0~3tx4:0~15</comment>
        </bits>
        <bits access="rw" name="trans_scheme" pos="22:20" rst="0">
          <comment>0
1
2
3PORT7
4PORT8
5PORT5</comment>
        </bits>
        <bits access="rw" name="ra_type" pos="19" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="n_scid" pos="18" rst="0">
          <comment>Nscid(UE)0~1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="17:16" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="modu_type" pos="15:14" rst="0">
          <comment>0:QPSK
1:16QAM
2:64QAM</comment>
        </bits>
        <bits access="rw" name="tb_size" pos="13:0" rst="0">
          <comment>max10296</comment>
        </bits>
      </reg>
      <reg name="dci0_info3" protect="rw">
        <bits access="rw" name="rep" pos="21:19" rst="0">
          <comment>DCI0C</comment>
        </bits>
        <bits access="rw" name="mcs" pos="18:14" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="cw2_flag" pos="13" rst="0">
          <comment>DCI2/DCI2A/DCI2B/DCI2C2
01
12</comment>
        </bits>
        <bits access="rw" name="cs_dmrs" pos="12:10" rst="0">
          <comment>DCI0</comment>
        </bits>
        <bits access="rw" name="cqi_indx" pos="9:8" rst="0">
          <comment>DCI0CQI</comment>
        </bits>
        <bits access="rw" name="tb_cw" pos="7" rst="0">
          <comment>DCI2/DCI2ATBCW
0
1</comment>
        </bits>
        <bits access="rw" name="srs_req" pos="6" rst="0">
          <comment>SRS
SRQDCI0DCI1ADCI2B TDDDCI2C TDD</comment>
        </bits>
        <bits access="rw" name="ndi_ind" pos="5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="pwr_ofst" pos="4" rst="0">
          <comment>DCI1D POWER OFFSET</comment>
        </bits>
        <bits access="rw" name="dai" pos="3:2" rst="0">
          <comment>DAI</comment>
        </bits>
        <bits access="rw" name="tpc_step" pos="1:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="dci0_info4" protect="rw">
        <bits access="rw" name="nul_fd" pos="31:15" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="ra_type" pos="14" rst="0">
          <comment>0TYPE0
1TYPE1</comment>
        </bits>
        <bits access="rw" name="rb_hop_flag" pos="13" rst="0">
          <comment>Type0</comment>
        </bits>
        <bits access="rw" name="rba" pos="12:0" rst="0">
          <comment>Type0/Type1RBA</comment>
        </bits>
      </reg>
      <reg name="dci0_info5" protect="rw">
        <bits access="rw" name="rb_bm_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci0_info6" protect="rw">
        <bits access="rw" name="rb_bm_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci0_info7" protect="rw">
        <bits access="rw" name="rb_bm_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci0_info8" protect="rw">
        <bits access="rw" name="rb_bm_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci0_info9" protect="rw">
        <bits access="rw" name="rb_bm_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci0_info10" protect="rw">
        <bits access="rw" name="rb_bm_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci0_info11" protect="rw">
        <bits access="rw" name="rb_bm_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci0_info12" protect="rw">
        <bits access="rw" name="rb_bm_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci1_out1" protect="rw">
        <bits access="rw" name="dci1_out1_dci1_out1" pos="31:0" rst="0">
          <comment>DCI132</comment>
        </bits>
      </reg>
      <reg name="dci1_out2" protect="rw">
        <bits access="rw" name="dci1_out2_dci1_out2" pos="31:0" rst="0">
          <comment>DCI132</comment>
        </bits>
      </reg>
      <reg name="dci1_pwr" protect="rw">
        <bits access="rw" name="dci_pwr" pos="25:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci1_fa" protect="rw">
        <bits access="rw" name="dci_fa_zero" pos="15:8" rst="0">
          <comment>DCI false alarm0</comment>
        </bits>
        <bits access="rw" name="dci_fa" pos="7:0" rst="0">
          <comment>DCI false alarm</comment>
        </bits>
      </reg>
      <reg name="dci1_info1" protect="rw">
        <bits access="rw" name="ant_sel" pos="28" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="rw" name="order_flag" pos="27" rst="0">
          <comment>DCI1A
0ORDER
1ORDER</comment>
        </bits>
        <bits access="rw" name="sps_ind" pos="26:25" rst="0">
          <comment>SPS-C-RNTI
0
1
2
3</comment>
        </bits>
        <bits access="rw" name="dci_type" pos="24:21" rst="0">
          <comment>DCI
0:DCI1
1:DCI1
2:DCI1A
3:DCI1B
4:DCI1C
5:DCI1D
6:DCI2
7:DCI2A
8:DCI2B
9:DCI2C
10:DCI3/3A</comment>
        </bits>
        <bits access="rw" name="rnti_ind" pos="20:17" rst="0">
          <comment>DCI RNTI
0RNTI0SI-RNTI
1RNTI1P-RNTI
2RNTI2RA-RNTI
3RNTI3C-RNTI
4RNTI4SPS-RNTI
5RNTI5T-RNTI
6RNTI6TPCS-RNTI
7RNTI7TPCC-RNTI
8RNTI8G-RNTI
9RNTI9SC-RNTI
10RNTI10SC-N-RNTI</comment>
        </bits>
        <bits access="rw" name="comm_ue" pos="16" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="rw" name="dci_stapos" pos="15:9" rst="0">
          <comment>DCI(index:0~23)</comment>
        </bits>
        <bits access="rw" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="rw" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci1_info2" protect="rw">
        <bits access="rw" name="pmi_confm" pos="31" rst="0">
          <comment>PMIDCIPMI
0DCIPMI
1PMI</comment>
        </bits>
        <bits access="rw" name="hq_proc" pos="30:27" rst="0">
          <comment>HARQ:0~15</comment>
        </bits>
        <bits access="rw" name="pmi_indx" pos="26:23" rst="0">
          <comment>tx2:0~3tx4:0~15</comment>
        </bits>
        <bits access="rw" name="trans_scheme" pos="22:20" rst="0">
          <comment>0
1
2
3PORT7
4PORT8
5PORT5</comment>
        </bits>
        <bits access="rw" name="ra_type" pos="19" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="n_scid" pos="18" rst="0">
          <comment>Nscid(UE)0~1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="17:16" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="modu_type" pos="15:14" rst="0">
          <comment>0:QPSK
1:16QAM
2:64QAM</comment>
        </bits>
        <bits access="rw" name="tb_size" pos="13:0" rst="0">
          <comment>max10296</comment>
        </bits>
      </reg>
      <reg name="dci1_info3" protect="rw">
        <bits access="rw" name="rep" pos="21:19" rst="0">
          <comment>DCI1C</comment>
        </bits>
        <bits access="rw" name="mcs" pos="18:14" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="cw2_flag" pos="13" rst="0">
          <comment>DCI2/DCI2A/DCI2B/DCI2C2
01
12</comment>
        </bits>
        <bits access="rw" name="cs_dmrs" pos="12:10" rst="0">
          <comment>DCI1</comment>
        </bits>
        <bits access="rw" name="cqi_indx" pos="9:8" rst="0">
          <comment>DCI1CQI</comment>
        </bits>
        <bits access="rw" name="tb_cw" pos="7" rst="0">
          <comment>DCI2/DCI2ATBCW
0
1</comment>
        </bits>
        <bits access="rw" name="srs_req" pos="6" rst="0">
          <comment>SRS
SRQDCI1DCI1ADCI2B TDDDCI2C TDD</comment>
        </bits>
        <bits access="rw" name="ndi_ind" pos="5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="pwr_ofst" pos="4" rst="0">
          <comment>DCI1D POWER OFFSET</comment>
        </bits>
        <bits access="rw" name="dai" pos="3:2" rst="0">
          <comment>DAI</comment>
        </bits>
        <bits access="rw" name="tpc_step" pos="1:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="dci1_info4" protect="rw">
        <bits access="rw" name="nul_fd" pos="31:15" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="ra_type" pos="14" rst="0">
          <comment>0TYPE0
1TYPE1</comment>
        </bits>
        <bits access="rw" name="rb_hop_flag" pos="13" rst="0">
          <comment>Type0</comment>
        </bits>
        <bits access="rw" name="rba" pos="12:0" rst="0">
          <comment>Type0/Type1RBA</comment>
        </bits>
      </reg>
      <reg name="dci1_info5" protect="rw">
        <bits access="rw" name="rb_bm_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci1_info6" protect="rw">
        <bits access="rw" name="rb_bm_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci1_info7" protect="rw">
        <bits access="rw" name="rb_bm_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci1_info8" protect="rw">
        <bits access="rw" name="rb_bm_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci1_info9" protect="rw">
        <bits access="rw" name="rb_bm_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci1_info10" protect="rw">
        <bits access="rw" name="rb_bm_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci1_info11" protect="rw">
        <bits access="rw" name="rb_bm_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci1_info12" protect="rw">
        <bits access="rw" name="rb_bm_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci2_out1" protect="rw">
        <bits access="rw" name="dci2_out1_dci2_out1" pos="31:0" rst="0">
          <comment>DCI232</comment>
        </bits>
      </reg>
      <reg name="dci2_out2" protect="rw">
        <bits access="rw" name="dci2_out2_dci2_out2" pos="31:0" rst="0">
          <comment>DCI232</comment>
        </bits>
      </reg>
      <reg name="dci2_pwr" protect="rw">
        <bits access="rw" name="dci_pwr" pos="25:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci2_fa" protect="rw">
        <bits access="rw" name="dci_fa_zero" pos="15:8" rst="0">
          <comment>DCI false alarm0</comment>
        </bits>
        <bits access="rw" name="dci_fa" pos="7:0" rst="0">
          <comment>DCI false alarm</comment>
        </bits>
      </reg>
      <reg name="dci2_info1" protect="rw">
        <bits access="rw" name="ant_sel" pos="28" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="rw" name="order_flag" pos="27" rst="0">
          <comment>DCI2A
0ORDER
1ORDER</comment>
        </bits>
        <bits access="rw" name="sps_ind" pos="26:25" rst="0">
          <comment>SPS-C-RNTI
0
1
2
3</comment>
        </bits>
        <bits access="rw" name="dci_type" pos="24:21" rst="0">
          <comment>DCI
0:DCI2
1:DCI2
2:DCI2A
3:DCI2B
4:DCI2C
5:DCI2D
6:DCI2
7:DCI2A
8:DCI2B
9:DCI2C
10:DCI3/3A</comment>
        </bits>
        <bits access="rw" name="rnti_ind" pos="20:17" rst="0">
          <comment>DCI RNTI
0RNTI0SI-RNTI
1RNTI1P-RNTI
2RNTI2RA-RNTI
3RNTI3C-RNTI
4RNTI4SPS-RNTI
5RNTI5T-RNTI
6RNTI6TPCS-RNTI
7RNTI7TPCC-RNTI
8RNTI8G-RNTI
9RNTI9SC-RNTI
10RNTI10SC-N-RNTI</comment>
        </bits>
        <bits access="rw" name="comm_ue" pos="16" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="rw" name="dci_stapos" pos="15:9" rst="0">
          <comment>DCI(index:0~23)</comment>
        </bits>
        <bits access="rw" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="rw" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci2_info2" protect="rw">
        <bits access="rw" name="pmi_confm" pos="31" rst="0">
          <comment>PMIDCIPMI
0DCIPMI
1PMI</comment>
        </bits>
        <bits access="rw" name="hq_proc" pos="30:27" rst="0">
          <comment>HARQ:0~15</comment>
        </bits>
        <bits access="rw" name="pmi_indx" pos="26:23" rst="0">
          <comment>tx2:0~3tx4:0~15</comment>
        </bits>
        <bits access="rw" name="trans_scheme" pos="22:20" rst="0">
          <comment>0
1
2
3PORT7
4PORT8
5PORT5</comment>
        </bits>
        <bits access="rw" name="ra_type" pos="19" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="n_scid" pos="18" rst="0">
          <comment>Nscid(UE)0~1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="17:16" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="modu_type" pos="15:14" rst="0">
          <comment>0:QPSK
1:16QAM
2:64QAM</comment>
        </bits>
        <bits access="rw" name="tb_size" pos="13:0" rst="0">
          <comment>max10296</comment>
        </bits>
      </reg>
      <reg name="dci2_info3" protect="rw">
        <bits access="rw" name="rep" pos="21:19" rst="0">
          <comment>DCI2C</comment>
        </bits>
        <bits access="rw" name="mcs" pos="18:14" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="cw2_flag" pos="13" rst="0">
          <comment>DCI2/DCI2A/DCI2B/DCI2C2
01
12</comment>
        </bits>
        <bits access="rw" name="cs_dmrs" pos="12:10" rst="0">
          <comment>DCI2</comment>
        </bits>
        <bits access="rw" name="cqi_indx" pos="9:8" rst="0">
          <comment>DCI2CQI</comment>
        </bits>
        <bits access="rw" name="tb_cw" pos="7" rst="0">
          <comment>DCI2/DCI2ATBCW
0
1</comment>
        </bits>
        <bits access="rw" name="srs_req" pos="6" rst="0">
          <comment>SRS
SRQDCI2DCI2ADCI2B TDDDCI2C TDD</comment>
        </bits>
        <bits access="rw" name="ndi_ind" pos="5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="pwr_ofst" pos="4" rst="0">
          <comment>DCI2D POWER OFFSET</comment>
        </bits>
        <bits access="rw" name="dai" pos="3:2" rst="0">
          <comment>DAI</comment>
        </bits>
        <bits access="rw" name="tpc_step" pos="1:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="dci2_info4" protect="rw">
        <bits access="rw" name="nul_fd" pos="31:15" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="ra_type" pos="14" rst="0">
          <comment>0TYPE0
1TYPE1</comment>
        </bits>
        <bits access="rw" name="rb_hop_flag" pos="13" rst="0">
          <comment>Type0</comment>
        </bits>
        <bits access="rw" name="rba" pos="12:0" rst="0">
          <comment>Type0/Type1RBA</comment>
        </bits>
      </reg>
      <reg name="dci2_info5" protect="rw">
        <bits access="rw" name="rb_bm_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci2_info6" protect="rw">
        <bits access="rw" name="rb_bm_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci2_info7" protect="rw">
        <bits access="rw" name="rb_bm_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci2_info8" protect="rw">
        <bits access="rw" name="rb_bm_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci2_info9" protect="rw">
        <bits access="rw" name="rb_bm_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci2_info10" protect="rw">
        <bits access="rw" name="rb_bm_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci2_info11" protect="rw">
        <bits access="rw" name="rb_bm_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci2_info12" protect="rw">
        <bits access="rw" name="rb_bm_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci3_out1" protect="rw">
        <bits access="rw" name="dci3_out1_dci3_out1" pos="31:0" rst="0">
          <comment>DCI332</comment>
        </bits>
      </reg>
      <reg name="dci3_out2" protect="rw">
        <bits access="rw" name="dci3_out2_dci3_out2" pos="31:0" rst="0">
          <comment>DCI332</comment>
        </bits>
      </reg>
      <reg name="dci3_pwr" protect="rw">
        <bits access="rw" name="dci_pwr" pos="25:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci3_fa" protect="rw">
        <bits access="rw" name="dci_fa_zero" pos="15:8" rst="0">
          <comment>DCI false alarm0</comment>
        </bits>
        <bits access="rw" name="dci_fa" pos="7:0" rst="0">
          <comment>DCI false alarm</comment>
        </bits>
      </reg>
      <reg name="dci3_info1" protect="rw">
        <bits access="rw" name="ant_sel" pos="28" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="rw" name="order_flag" pos="27" rst="0">
          <comment>DCI3A
0ORDER
1ORDER</comment>
        </bits>
        <bits access="rw" name="sps_ind" pos="26:25" rst="0">
          <comment>SPS-C-RNTI
0
1
2
3</comment>
        </bits>
        <bits access="rw" name="dci_type" pos="24:21" rst="0">
          <comment>DCI
0:DCI3
1:DCI3
2:DCI3A
3:DCI3B
4:DCI3C
5:DCI3D
6:DCI3
7:DCI3A
8:DCI3B
9:DCI3C
10:DCI3/3A</comment>
        </bits>
        <bits access="rw" name="rnti_ind" pos="20:17" rst="0">
          <comment>DCI RNTI
0RNTI0SI-RNTI
1RNTI1P-RNTI
2RNTI2RA-RNTI
3RNTI3C-RNTI
4RNTI4SPS-RNTI
5RNTI5T-RNTI
6RNTI6TPCS-RNTI
7RNTI7TPCC-RNTI
8RNTI8G-RNTI
9RNTI9SC-RNTI
10RNTI10SC-N-RNTI</comment>
        </bits>
        <bits access="rw" name="comm_ue" pos="16" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="rw" name="dci_stapos" pos="15:9" rst="0">
          <comment>DCI(index:0~23)</comment>
        </bits>
        <bits access="rw" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="rw" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci3_info2" protect="rw">
        <bits access="rw" name="pmi_confm" pos="31" rst="0">
          <comment>PMIDCIPMI
0DCIPMI
1PMI</comment>
        </bits>
        <bits access="rw" name="hq_proc" pos="30:27" rst="0">
          <comment>HARQ:0~15</comment>
        </bits>
        <bits access="rw" name="pmi_indx" pos="26:23" rst="0">
          <comment>tx2:0~3tx4:0~15</comment>
        </bits>
        <bits access="rw" name="trans_scheme" pos="22:20" rst="0">
          <comment>0
1
2
3PORT7
4PORT8
5PORT5</comment>
        </bits>
        <bits access="rw" name="ra_type" pos="19" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="n_scid" pos="18" rst="0">
          <comment>Nscid(UE)0~1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="17:16" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="modu_type" pos="15:14" rst="0">
          <comment>0:QPSK
1:16QAM
2:64QAM</comment>
        </bits>
        <bits access="rw" name="tb_size" pos="13:0" rst="0">
          <comment>max10296</comment>
        </bits>
      </reg>
      <reg name="dci3_info3" protect="rw">
        <bits access="rw" name="rep" pos="21:19" rst="0">
          <comment>DCI3C</comment>
        </bits>
        <bits access="rw" name="mcs" pos="18:14" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="cw2_flag" pos="13" rst="0">
          <comment>DCI3/DCI3A/DCI3B/DCI3C2
01
12</comment>
        </bits>
        <bits access="rw" name="cs_dmrs" pos="12:10" rst="0">
          <comment>DCI3</comment>
        </bits>
        <bits access="rw" name="cqi_indx" pos="9:8" rst="0">
          <comment>DCI3CQI</comment>
        </bits>
        <bits access="rw" name="tb_cw" pos="7" rst="0">
          <comment>DCI3/DCI3ATBCW
0
1</comment>
        </bits>
        <bits access="rw" name="srs_req" pos="6" rst="0">
          <comment>SRS
SRQDCI3DCI3ADCI3B TDDDCI3C TDD</comment>
        </bits>
        <bits access="rw" name="ndi_ind" pos="5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="pwr_ofst" pos="4" rst="0">
          <comment>DCI3D POWER OFFSET</comment>
        </bits>
        <bits access="rw" name="dai" pos="3:2" rst="0">
          <comment>DAI</comment>
        </bits>
        <bits access="rw" name="tpc_step" pos="1:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="dci3_info4" protect="rw">
        <bits access="rw" name="nul_fd" pos="31:15" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="ra_type" pos="14" rst="0">
          <comment>0TYPE0
1TYPE1</comment>
        </bits>
        <bits access="rw" name="rb_hop_flag" pos="13" rst="0">
          <comment>Type0</comment>
        </bits>
        <bits access="rw" name="rba" pos="12:0" rst="0">
          <comment>Type0/Type1RBA</comment>
        </bits>
      </reg>
      <reg name="dci3_info5" protect="rw">
        <bits access="rw" name="rb_bm_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci3_info6" protect="rw">
        <bits access="rw" name="rb_bm_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci3_info7" protect="rw">
        <bits access="rw" name="rb_bm_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci3_info8" protect="rw">
        <bits access="rw" name="rb_bm_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci3_info9" protect="rw">
        <bits access="rw" name="rb_bm_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci3_info10" protect="rw">
        <bits access="rw" name="rb_bm_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci3_info11" protect="rw">
        <bits access="rw" name="rb_bm_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci3_info12" protect="rw">
        <bits access="rw" name="rb_bm_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci4_out1" protect="rw">
        <bits access="rw" name="dci4_out1_dci4_out1" pos="31:0" rst="0">
          <comment>DCI432</comment>
        </bits>
      </reg>
      <reg name="dci4_out2" protect="rw">
        <bits access="rw" name="dci4_out2_dci4_out2" pos="31:0" rst="0">
          <comment>DCI432</comment>
        </bits>
      </reg>
      <reg name="dci4_pwr" protect="rw">
        <bits access="rw" name="dci_pwr" pos="25:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci4_fa" protect="rw">
        <bits access="rw" name="dci_fa_zero" pos="15:8" rst="0">
          <comment>DCI false alarm0</comment>
        </bits>
        <bits access="rw" name="dci_fa" pos="7:0" rst="0">
          <comment>DCI false alarm</comment>
        </bits>
      </reg>
      <reg name="dci4_info1" protect="rw">
        <bits access="rw" name="ant_sel" pos="28" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="rw" name="order_flag" pos="27" rst="0">
          <comment>DCI4A
0ORDER
1ORDER</comment>
        </bits>
        <bits access="rw" name="sps_ind" pos="26:25" rst="0">
          <comment>SPS-C-RNTI
0
1
2
3</comment>
        </bits>
        <bits access="rw" name="dci_type" pos="24:21" rst="0">
          <comment>DCI
0:DCI4
1:DCI4
2:DCI4A
3:DCI4B
4:DCI4C
5:DCI4D
6:DCI4
7:DCI4A
8:DCI4B
9:DCI4C
10:DCI4/3A</comment>
        </bits>
        <bits access="rw" name="rnti_ind" pos="20:17" rst="0">
          <comment>DCI RNTI
0RNTI0SI-RNTI
1RNTI1P-RNTI
2RNTI2RA-RNTI
3RNTI3C-RNTI
4RNTI4SPS-RNTI
5RNTI5T-RNTI
6RNTI6TPCS-RNTI
7RNTI7TPCC-RNTI
8RNTI8G-RNTI
9RNTI9SC-RNTI
10RNTI10SC-N-RNTI</comment>
        </bits>
        <bits access="rw" name="comm_ue" pos="16" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="rw" name="dci_stapos" pos="15:9" rst="0">
          <comment>DCI(index:0~23)</comment>
        </bits>
        <bits access="rw" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="rw" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci4_info2" protect="rw">
        <bits access="rw" name="pmi_confm" pos="31" rst="0">
          <comment>PMIDCIPMI
0DCIPMI
1PMI</comment>
        </bits>
        <bits access="rw" name="hq_proc" pos="30:27" rst="0">
          <comment>HARQ:0~15</comment>
        </bits>
        <bits access="rw" name="pmi_indx" pos="26:23" rst="0">
          <comment>tx2:0~3tx4:0~15</comment>
        </bits>
        <bits access="rw" name="trans_scheme" pos="22:20" rst="0">
          <comment>0
1
2
3PORT7
4PORT8
5PORT5</comment>
        </bits>
        <bits access="rw" name="ra_type" pos="19" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="n_scid" pos="18" rst="0">
          <comment>Nscid(UE)0~1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="17:16" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="modu_type" pos="15:14" rst="0">
          <comment>0:QPSK
1:16QAM
2:64QAM</comment>
        </bits>
        <bits access="rw" name="tb_size" pos="13:0" rst="0">
          <comment>max10296</comment>
        </bits>
      </reg>
      <reg name="dci4_info3" protect="rw">
        <bits access="rw" name="rep" pos="21:19" rst="0">
          <comment>DCI4C</comment>
        </bits>
        <bits access="rw" name="mcs" pos="18:14" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="cw2_flag" pos="13" rst="0">
          <comment>DCI4/DCI4A/DCI4B/DCI4C2
01
12</comment>
        </bits>
        <bits access="rw" name="cs_dmrs" pos="12:10" rst="0">
          <comment>DCI4</comment>
        </bits>
        <bits access="rw" name="cqi_indx" pos="9:8" rst="0">
          <comment>DCI4CQI</comment>
        </bits>
        <bits access="rw" name="tb_cw" pos="7" rst="0">
          <comment>DCI4/DCI4ATBCW
0
1</comment>
        </bits>
        <bits access="rw" name="srs_req" pos="6" rst="0">
          <comment>SRS
SRQDCI4DCI4ADCI4B TDDDCI4C TDD</comment>
        </bits>
        <bits access="rw" name="ndi_ind" pos="5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="pwr_ofst" pos="4" rst="0">
          <comment>DCI4D POWER OFFSET</comment>
        </bits>
        <bits access="rw" name="dai" pos="3:2" rst="0">
          <comment>DAI</comment>
        </bits>
        <bits access="rw" name="tpc_step" pos="1:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="dci4_info4" protect="rw">
        <bits access="rw" name="nul_fd" pos="31:15" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="ra_type" pos="14" rst="0">
          <comment>0TYPE0
1TYPE1</comment>
        </bits>
        <bits access="rw" name="rb_hop_flag" pos="13" rst="0">
          <comment>Type0</comment>
        </bits>
        <bits access="rw" name="rba" pos="12:0" rst="0">
          <comment>Type0/Type1RBA</comment>
        </bits>
      </reg>
      <reg name="dci4_info5" protect="rw">
        <bits access="rw" name="rb_bm_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci4_info6" protect="rw">
        <bits access="rw" name="rb_bm_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci4_info7" protect="rw">
        <bits access="rw" name="rb_bm_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci4_info8" protect="rw">
        <bits access="rw" name="rb_bm_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci4_info9" protect="rw">
        <bits access="rw" name="rb_bm_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci4_info10" protect="rw">
        <bits access="rw" name="rb_bm_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci4_info11" protect="rw">
        <bits access="rw" name="rb_bm_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci4_info12" protect="rw">
        <bits access="rw" name="rb_bm_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci5_out1" protect="rw">
        <bits access="rw" name="dci5_out1_dci5_out1" pos="31:0" rst="0">
          <comment>DCI532</comment>
        </bits>
      </reg>
      <reg name="dci5_out2" protect="rw">
        <bits access="rw" name="dci5_out2_dci5_out2" pos="31:0" rst="0">
          <comment>DCI532</comment>
        </bits>
      </reg>
      <reg name="dci5_pwr" protect="rw">
        <bits access="rw" name="dci_pwr" pos="25:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci5_fa" protect="rw">
        <bits access="rw" name="dci_fa_zero" pos="15:8" rst="0">
          <comment>DCI false alarm0</comment>
        </bits>
        <bits access="rw" name="dci_fa" pos="7:0" rst="0">
          <comment>DCI false alarm</comment>
        </bits>
      </reg>
      <reg name="dci5_info1" protect="rw">
        <bits access="rw" name="ant_sel" pos="28" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="rw" name="order_flag" pos="27" rst="0">
          <comment>DCI5A
0ORDER
1ORDER</comment>
        </bits>
        <bits access="rw" name="sps_ind" pos="26:25" rst="0">
          <comment>SPS-C-RNTI
0
1
2
3</comment>
        </bits>
        <bits access="rw" name="dci_type" pos="24:21" rst="0">
          <comment>DCI
0:DCI5
1:DCI5
2:DCI5A
3:DCI5B
4:DCI5C
5:DCI5D
6:DCI5
7:DCI5A
8:DCI5B
9:DCI5C
10:DCI5/3A</comment>
        </bits>
        <bits access="rw" name="rnti_ind" pos="20:17" rst="0">
          <comment>DCI RNTI
0RNTI0SI-RNTI
1RNTI1P-RNTI
2RNTI2RA-RNTI
3RNTI3C-RNTI
4RNTI4SPS-RNTI
5RNTI5T-RNTI
6RNTI6TPCS-RNTI
7RNTI7TPCC-RNTI
8RNTI8G-RNTI
9RNTI9SC-RNTI
10RNTI10SC-N-RNTI</comment>
        </bits>
        <bits access="rw" name="comm_ue" pos="16" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="rw" name="dci_stapos" pos="15:9" rst="0">
          <comment>DCI(index:0~23)</comment>
        </bits>
        <bits access="rw" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="rw" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci5_info2" protect="rw">
        <bits access="rw" name="pmi_confm" pos="31" rst="0">
          <comment>PMIDCIPMI
0DCIPMI
1PMI</comment>
        </bits>
        <bits access="rw" name="hq_proc" pos="30:27" rst="0">
          <comment>HARQ:0~15</comment>
        </bits>
        <bits access="rw" name="pmi_indx" pos="26:23" rst="0">
          <comment>tx2:0~3tx4:0~15</comment>
        </bits>
        <bits access="rw" name="trans_scheme" pos="22:20" rst="0">
          <comment>0
1
2
3PORT7
4PORT8
5PORT5</comment>
        </bits>
        <bits access="rw" name="ra_type" pos="19" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="n_scid" pos="18" rst="0">
          <comment>Nscid(UE)0~1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="17:16" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="modu_type" pos="15:14" rst="0">
          <comment>0:QPSK
1:16QAM
2:64QAM</comment>
        </bits>
        <bits access="rw" name="tb_size" pos="13:0" rst="0">
          <comment>max10296</comment>
        </bits>
      </reg>
      <reg name="dci5_info3" protect="rw">
        <bits access="rw" name="rep" pos="21:19" rst="0">
          <comment>DCI5C</comment>
        </bits>
        <bits access="rw" name="mcs" pos="18:14" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="cw2_flag" pos="13" rst="0">
          <comment>DCI5/DCI5A/DCI5B/DCI5C2
01
12</comment>
        </bits>
        <bits access="rw" name="cs_dmrs" pos="12:10" rst="0">
          <comment>DCI5</comment>
        </bits>
        <bits access="rw" name="cqi_indx" pos="9:8" rst="0">
          <comment>DCI5CQI</comment>
        </bits>
        <bits access="rw" name="tb_cw" pos="7" rst="0">
          <comment>DCI5/DCI5ATBCW
0
1</comment>
        </bits>
        <bits access="rw" name="srs_req" pos="6" rst="0">
          <comment>SRS
SRQDCI5DCI5ADCI5B TDDDCI5C TDD</comment>
        </bits>
        <bits access="rw" name="ndi_ind" pos="5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="pwr_ofst" pos="4" rst="0">
          <comment>DCI5D POWER OFFSET</comment>
        </bits>
        <bits access="rw" name="dai" pos="3:2" rst="0">
          <comment>DAI</comment>
        </bits>
        <bits access="rw" name="tpc_step" pos="1:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="dci5_info4" protect="rw">
        <bits access="rw" name="nul_fd" pos="31:15" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="ra_type" pos="14" rst="0">
          <comment>0TYPE0
1TYPE1</comment>
        </bits>
        <bits access="rw" name="rb_hop_flag" pos="13" rst="0">
          <comment>Type0</comment>
        </bits>
        <bits access="rw" name="rba" pos="12:0" rst="0">
          <comment>Type0/Type1RBA</comment>
        </bits>
      </reg>
      <reg name="dci5_info5" protect="rw">
        <bits access="rw" name="rb_bm_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci5_info6" protect="rw">
        <bits access="rw" name="rb_bm_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci5_info7" protect="rw">
        <bits access="rw" name="rb_bm_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci5_info8" protect="rw">
        <bits access="rw" name="rb_bm_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci5_info9" protect="rw">
        <bits access="rw" name="rb_bm_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci5_info10" protect="rw">
        <bits access="rw" name="rb_bm_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci5_info11" protect="rw">
        <bits access="rw" name="rb_bm_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci5_info12" protect="rw">
        <bits access="rw" name="rb_bm_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci6_out1" protect="rw">
        <bits access="rw" name="dci6_out1_dci6_out1" pos="31:0" rst="0">
          <comment>DCI632</comment>
        </bits>
      </reg>
      <reg name="dci6_out2" protect="rw">
        <bits access="rw" name="dci6_out2_dci6_out2" pos="31:0" rst="0">
          <comment>DCI632</comment>
        </bits>
      </reg>
      <reg name="dci6_pwr" protect="rw">
        <bits access="rw" name="dci_pwr" pos="25:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci6_fa" protect="rw">
        <bits access="rw" name="dci_fa_zero" pos="15:8" rst="0">
          <comment>DCI false alarm0</comment>
        </bits>
        <bits access="rw" name="dci_fa" pos="7:0" rst="0">
          <comment>DCI false alarm</comment>
        </bits>
      </reg>
      <reg name="dci6_info1" protect="rw">
        <bits access="rw" name="ant_sel" pos="28" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="rw" name="order_flag" pos="27" rst="0">
          <comment>DCI6A
0ORDER
1ORDER</comment>
        </bits>
        <bits access="rw" name="sps_ind" pos="26:25" rst="0">
          <comment>SPS-C-RNTI
0
1
2
3</comment>
        </bits>
        <bits access="rw" name="dci_type" pos="24:21" rst="0">
          <comment>DCI
0:DCI6
1:DCI6
2:DCI6A
3:DCI6B
4:DCI6C
5:DCI6D
6:DCI6
7:DCI6A
8:DCI6B
9:DCI6C
10:DCI6/3A</comment>
        </bits>
        <bits access="rw" name="rnti_ind" pos="20:17" rst="0">
          <comment>DCI RNTI
0RNTI0SI-RNTI
1RNTI1P-RNTI
2RNTI2RA-RNTI
3RNTI3C-RNTI
4RNTI4SPS-RNTI
5RNTI5T-RNTI
6RNTI6TPCS-RNTI
7RNTI7TPCC-RNTI
8RNTI8G-RNTI
9RNTI9SC-RNTI
10RNTI10SC-N-RNTI</comment>
        </bits>
        <bits access="rw" name="comm_ue" pos="16" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="rw" name="dci_stapos" pos="15:9" rst="0">
          <comment>DCI(index:0~23)</comment>
        </bits>
        <bits access="rw" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="rw" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci6_info2" protect="rw">
        <bits access="rw" name="pmi_confm" pos="31" rst="0">
          <comment>PMIDCIPMI
0DCIPMI
1PMI</comment>
        </bits>
        <bits access="rw" name="hq_proc" pos="30:27" rst="0">
          <comment>HARQ:0~15</comment>
        </bits>
        <bits access="rw" name="pmi_indx" pos="26:23" rst="0">
          <comment>tx2:0~3tx4:0~15</comment>
        </bits>
        <bits access="rw" name="trans_scheme" pos="22:20" rst="0">
          <comment>0
1
2
3PORT7
4PORT8
5PORT5</comment>
        </bits>
        <bits access="rw" name="ra_type" pos="19" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="n_scid" pos="18" rst="0">
          <comment>Nscid(UE)0~1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="17:16" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="modu_type" pos="15:14" rst="0">
          <comment>0:QPSK
1:16QAM
2:64QAM</comment>
        </bits>
        <bits access="rw" name="tb_size" pos="13:0" rst="0">
          <comment>max10296</comment>
        </bits>
      </reg>
      <reg name="dci6_info3" protect="rw">
        <bits access="rw" name="rep" pos="21:19" rst="0">
          <comment>DCI6C</comment>
        </bits>
        <bits access="rw" name="mcs" pos="18:14" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="cw2_flag" pos="13" rst="0">
          <comment>DCI6/DCI6A/DCI6B/DCI6C2
01
12</comment>
        </bits>
        <bits access="rw" name="cs_dmrs" pos="12:10" rst="0">
          <comment>DCI6</comment>
        </bits>
        <bits access="rw" name="cqi_indx" pos="9:8" rst="0">
          <comment>DCI6CQI</comment>
        </bits>
        <bits access="rw" name="tb_cw" pos="7" rst="0">
          <comment>DCI6/DCI6ATBCW
0
1</comment>
        </bits>
        <bits access="rw" name="srs_req" pos="6" rst="0">
          <comment>SRS
SRQDCI6DCI6ADCI6B TDDDCI6C TDD</comment>
        </bits>
        <bits access="rw" name="ndi_ind" pos="5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="pwr_ofst" pos="4" rst="0">
          <comment>DCI6D POWER OFFSET</comment>
        </bits>
        <bits access="rw" name="dai" pos="3:2" rst="0">
          <comment>DAI</comment>
        </bits>
        <bits access="rw" name="tpc_step" pos="1:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="dci6_info4" protect="rw">
        <bits access="rw" name="nul_fd" pos="31:15" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="ra_type" pos="14" rst="0">
          <comment>0TYPE0
1TYPE1</comment>
        </bits>
        <bits access="rw" name="rb_hop_flag" pos="13" rst="0">
          <comment>Type0</comment>
        </bits>
        <bits access="rw" name="rba" pos="12:0" rst="0">
          <comment>Type0/Type1RBA</comment>
        </bits>
      </reg>
      <reg name="dci6_info5" protect="rw">
        <bits access="rw" name="rb_bm_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci6_info6" protect="rw">
        <bits access="rw" name="rb_bm_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci6_info7" protect="rw">
        <bits access="rw" name="rb_bm_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci6_info8" protect="rw">
        <bits access="rw" name="rb_bm_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci6_info9" protect="rw">
        <bits access="rw" name="rb_bm_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci6_info10" protect="rw">
        <bits access="rw" name="rb_bm_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci6_info11" protect="rw">
        <bits access="rw" name="rb_bm_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci6_info12" protect="rw">
        <bits access="rw" name="rb_bm_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci7_out1" protect="rw">
        <bits access="rw" name="dci7_out1_dci7_out1" pos="31:0" rst="0">
          <comment>DCI732</comment>
        </bits>
      </reg>
      <reg name="dci7_out2" protect="rw">
        <bits access="rw" name="dci7_out2_dci7_out2" pos="31:0" rst="0">
          <comment>DCI732</comment>
        </bits>
      </reg>
      <reg name="dci7_pwr" protect="rw">
        <bits access="rw" name="dci_pwr" pos="25:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci7_fa" protect="rw">
        <bits access="rw" name="dci_fa_zero" pos="15:8" rst="0">
          <comment>DCI false alarm0</comment>
        </bits>
        <bits access="rw" name="dci_fa" pos="7:0" rst="0">
          <comment>DCI false alarm</comment>
        </bits>
      </reg>
      <reg name="dci7_info1" protect="rw">
        <bits access="rw" name="ant_sel" pos="28" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="rw" name="order_flag" pos="27" rst="0">
          <comment>DCI7A
0ORDER
1ORDER</comment>
        </bits>
        <bits access="rw" name="sps_ind" pos="26:25" rst="0">
          <comment>SPS-C-RNTI
0
1
2
3</comment>
        </bits>
        <bits access="rw" name="dci_type" pos="24:21" rst="0">
          <comment>DCI
0:DCI7
1:DCI7
2:DCI7A
3:DCI7B
4:DCI7C
5:DCI7D
6:DCI7
7:DCI7A
8:DCI7B
9:DCI7C
10:DCI7/3A</comment>
        </bits>
        <bits access="rw" name="rnti_ind" pos="20:17" rst="0">
          <comment>DCI RNTI
0RNTI0SI-RNTI
1RNTI1P-RNTI
2RNTI2RA-RNTI
3RNTI3C-RNTI
4RNTI4SPS-RNTI
5RNTI5T-RNTI
6RNTI6TPCS-RNTI
7RNTI7TPCC-RNTI
8RNTI8G-RNTI
9RNTI9SC-RNTI
10RNTI10SC-N-RNTI</comment>
        </bits>
        <bits access="rw" name="comm_ue" pos="16" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="rw" name="dci_stapos" pos="15:9" rst="0">
          <comment>DCI(index:0~23)</comment>
        </bits>
        <bits access="rw" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="rw" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci7_info2" protect="rw">
        <bits access="rw" name="pmi_confm" pos="31" rst="0">
          <comment>PMIDCIPMI
0DCIPMI
1PMI</comment>
        </bits>
        <bits access="rw" name="hq_proc" pos="30:27" rst="0">
          <comment>HARQ:0~15</comment>
        </bits>
        <bits access="rw" name="pmi_indx" pos="26:23" rst="0">
          <comment>tx2:0~3tx4:0~15</comment>
        </bits>
        <bits access="rw" name="trans_scheme" pos="22:20" rst="0">
          <comment>0
1
2
3PORT7
4PORT8
5PORT5</comment>
        </bits>
        <bits access="rw" name="ra_type" pos="19" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="n_scid" pos="18" rst="0">
          <comment>Nscid(UE)0~1</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="17:16" rst="0">
          <comment>0~3</comment>
        </bits>
        <bits access="rw" name="modu_type" pos="15:14" rst="0">
          <comment>0:QPSK
1:16QAM
2:64QAM</comment>
        </bits>
        <bits access="rw" name="tb_size" pos="13:0" rst="0">
          <comment>max10296</comment>
        </bits>
      </reg>
      <reg name="dci7_info3" protect="rw">
        <bits access="rw" name="rep" pos="21:19" rst="0">
          <comment>DCI7C</comment>
        </bits>
        <bits access="rw" name="mcs" pos="18:14" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="cw2_flag" pos="13" rst="0">
          <comment>DCI7/DCI7A/DCI7B/DCI7C2
01
12</comment>
        </bits>
        <bits access="rw" name="cs_dmrs" pos="12:10" rst="0">
          <comment>DCI7</comment>
        </bits>
        <bits access="rw" name="cqi_indx" pos="9:8" rst="0">
          <comment>DCI7CQI</comment>
        </bits>
        <bits access="rw" name="tb_cw" pos="7" rst="0">
          <comment>DCI7/DCI7ATBCW
0
1</comment>
        </bits>
        <bits access="rw" name="srs_req" pos="6" rst="0">
          <comment>SRS
SRQDCI7DCI7ADCI7B TDDDCI7C TDD</comment>
        </bits>
        <bits access="rw" name="ndi_ind" pos="5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="pwr_ofst" pos="4" rst="0">
          <comment>DCI7D POWER OFFSET</comment>
        </bits>
        <bits access="rw" name="dai" pos="3:2" rst="0">
          <comment>DAI</comment>
        </bits>
        <bits access="rw" name="tpc_step" pos="1:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="dci7_info4" protect="rw">
        <bits access="rw" name="nul_fd" pos="31:15" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="ra_type" pos="14" rst="0">
          <comment>0TYPE0
1TYPE1</comment>
        </bits>
        <bits access="rw" name="rb_hop_flag" pos="13" rst="0">
          <comment>Type0</comment>
        </bits>
        <bits access="rw" name="rba" pos="12:0" rst="0">
          <comment>Type0/Type1RBA</comment>
        </bits>
      </reg>
      <reg name="dci7_info5" protect="rw">
        <bits access="rw" name="rb_bm_00" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci7_info6" protect="rw">
        <bits access="rw" name="rb_bm_01" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci7_info7" protect="rw">
        <bits access="rw" name="rb_bm_02" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci7_info8" protect="rw">
        <bits access="rw" name="rb_bm_03" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci7_info9" protect="rw">
        <bits access="rw" name="rb_bm_10" pos="31:0" rst="0">
          <comment>0.5msbitmapbit[63:32]prbbit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci7_info10" protect="rw">
        <bits access="rw" name="rb_bm_11" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[63:32]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci7_info11" protect="rw">
        <bits access="rw" name="rb_bm_12" pos="31:0" rst="0">
          <comment>0.5msbitmapbitprb[95:64]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <reg name="dci7_info12" protect="rw">
        <bits access="rw" name="rb_bm_13" pos="3:0" rst="0">
          <comment>0.5msbitmapbitprb[99:96]bit
0prb
1prb</comment>
        </bits>
      </reg>
      <hole size="86016"/>
      <reg name="pdcch_memdem" protect="rw">
        <bits access="rw" name="pdcch_memdem_2" pos="31:21" rst="0">
      </bits>
        <bits access="rw" name="pdcch_memdem_1" pos="15:5" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="pdcch_memreg" protect="r">
        <bits access="r" name="pdcch_memreg_pdcch_memreg" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="pdcch_mempbchin" protect="rw">
        <bits access="rw" name="pbch_memin_2" pos="31:22" rst="0">
      </bits>
        <bits access="rw" name="pbch_memin_1" pos="15:6" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="mib0_out" protect="r">
        <bits access="r" name="mib0_out_mib0_out" pos="23:0" rst="0">
          <comment>MIB0</comment>
        </bits>
      </reg>
      <reg name="mib0_info" protect="r">
        <bits access="r" name="mib0_info_mib0_info" pos="1:0" rst="0">
          <comment>MIB</comment>
        </bits>
      </reg>
      <reg name="mib1_out" protect="r">
        <bits access="r" name="mib1_out_mib1_out" pos="23:0" rst="0">
          <comment>MIB1</comment>
        </bits>
      </reg>
      <reg name="mib1_info" protect="r">
        <bits access="r" name="mib1_info_mib1_info" pos="1:0" rst="0">
          <comment>MIB</comment>
        </bits>
      </reg>
      <reg name="mib2_out" protect="r">
        <bits access="r" name="mib2_out_mib2_out" pos="23:0" rst="0">
          <comment>MIB2</comment>
        </bits>
      </reg>
      <reg name="mib2_info" protect="r">
        <bits access="r" name="mib2_info_mib2_info" pos="1:0" rst="0">
          <comment>MIB</comment>
        </bits>
      </reg>
      <reg name="mib3_out" protect="r">
        <bits access="r" name="mib3_out_mib3_out" pos="23:0" rst="0">
          <comment>MIB3</comment>
        </bits>
      </reg>
      <reg name="mib3_info" protect="r">
        <bits access="r" name="mib3_info_mib3_info" pos="1:0" rst="0">
          <comment>MIB</comment>
        </bits>
      </reg>
      <hole size="7921408"/>
      <reg name="hqmem11" protect="rw">
        <bits access="rw" name="hqmem11_2" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="hqmem11_1" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="98272"/>
      <reg name="hqmem12" protect="rw">
        <bits access="rw" name="hqmem12_hqmem12" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="950240"/>
      <reg name="hqmem21" protect="rw">
        <bits access="rw" name="hqmem21_hqmem21" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="hqmem22" protect="rw">
        <bits access="rw" name="hqmem22_hqmem22" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="hqmem23" protect="rw">
        <bits access="rw" name="hqmem23_hqmem23" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="hqmem24" protect="rw">
        <bits access="rw" name="hqmem24_hqmem24" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="6553568"/>
      <reg name="tbmemin0" protect="rw">
        <bits access="rw" name="tbmemin0_tbmemin0" pos="23:0" rst="0">
      </bits>
      </reg>
      <hole size="229344"/>
      <reg name="tbmemout0" protect="rw">
        <bits access="rw" name="tbmemout0_tbmemout0" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="294880"/>
      <reg name="tbmemin1" protect="rw">
        <bits access="rw" name="tbmemin1_tbmemin1" pos="23:0" rst="0">
      </bits>
      </reg>
      <hole size="229344"/>
      <reg name="tbmemout1" protect="rw">
        <bits access="rw" name="tbmemout1_tbmemout1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="294880"/>
      <reg name="pdsmemout0" protect="rw">
        <bits access="rw" name="pdsmemout0_pdsmemout0" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="pdsmemout1" protect="rw">
        <bits access="rw" name="pdsmemout1_pdsmemout1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="7307232"/>
      <reg name="fftbuf0" protect="rw">
        <bits access="rw" name="fftbuf0_fftbuf0" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="524256"/>
      <reg name="fftbuf1" protect="rw">
        <bits access="rw" name="fftbuf1_fftbuf1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="7864288"/>
      <reg name="hqbuf" protect="rw">
        <bits access="rw" name="hqbuf_hqbuf" pos="31:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_ldtc.xml">
    <module category="LTE_SYS" name="CP_LTE_LDTC">
      <reg name="sys_para_nxt" protect="rw">
        <bits access="rw" name="schd_sib1" pos="26:22" rst="0">
          <comment>Schedule SIB1 BR R13PBML</comment>
        </bits>
        <bits access="rw" name="phi_res" pos="21:20" rst="0">
          <comment>PHICH resourcePBML</comment>
        </bits>
        <bits access="rw" name="phi_dur" pos="19" rst="0">
          <comment>PHICH durationPBML</comment>
        </bits>
        <bits access="rw" name="pbch_rep" pos="18" rst="0">
          <comment>PBCH
0PBCH
1PBCH</comment>
        </bits>
        <bits access="rw" name="tm_mode" pos="17:14" rst="0">
          <comment>CATM1,2,6,9</comment>
        </bits>
        <bits access="rw" name="ss_conf" pos="13:10" rst="0">
          <comment>TDD
099</comment>
        </bits>
        <bits access="rw" name="uldl_conf" pos="9:7" rst="0">
          <comment>066</comment>
        </bits>
        <bits access="rw" name="bw_ind" pos="6:4" rst="0">
          <comment>0: 1.4MHZ
1: 3MHZ
2: 5MHZ
310MHZ
4: 15MHZ
5: 20MHZ
6~75</comment>
        </bits>
        <bits access="rw" name="ant_tx" pos="3:2" rst="0">
          <comment>0 1
1 2
2 4
3 2</comment>
        </bits>
        <bits access="rw" name="cp_ind" pos="1" rst="0">
          <comment>CP
0 CP
1 CP</comment>
        </bits>
        <bits access="rw" name="fdd_tdd" pos="0" rst="0">
          <comment>FDDTDD
0 TDD
1 FDD</comment>
        </bits>
      </reg>
      <reg name="nid_cell_nxt" protect="rw">
        <bits access="rw" name="nid_cell" pos="8:0" rst="0">
          <comment>ID0503</comment>
        </bits>
      </reg>
      <reg name="g_rnti" protect="rw">
        <bits access="rw" name="g_rnti_g_rnti" pos="15:0" rst="0">
          <comment>G_RNTI</comment>
        </bits>
      </reg>
      <reg name="ra_t_rnti" protect="rw">
        <bits access="rw" name="t_rnti" pos="31:16" rst="0">
          <comment>Temp-C-RNTI</comment>
        </bits>
        <bits access="rw" name="ra_rnti" pos="15:0" rst="0">
          <comment>RA-RNTI</comment>
        </bits>
      </reg>
      <reg name="c_sps_rnti" protect="rw">
        <bits access="rw" name="sps_rnti" pos="31:16" rst="0">
          <comment>SPS-C-RNTI</comment>
        </bits>
        <bits access="rw" name="c_rnti" pos="15:0" rst="0">
          <comment>C-RNTI</comment>
        </bits>
      </reg>
      <reg name="tpc_rnti" protect="rw">
        <bits access="rw" name="tpcs_rnti" pos="31:16" rst="0">
          <comment>TPC-PUCSH-RNTI</comment>
        </bits>
        <bits access="rw" name="tpcc_rnti" pos="15:0" rst="0">
          <comment>TPC-PUCCH-RNTI</comment>
        </bits>
      </reg>
      <reg name="mpdcch_set1_nxt" protect="rw">
        <bits access="rw" name="nprb_set1" pos="15:14" rst="0">
          <comment>MPDCCH1PRB
0 2
1 4
2 6</comment>
        </bits>
        <bits access="rw" name="rba_set1" pos="13:10" rst="0">
          <comment>MPDCCH1RBA</comment>
        </bits>
        <bits access="rw" name="dmrs_sid_set1" pos="9:1" rst="0">
          <comment>MPDCCH1ID
0503</comment>
        </bits>
        <bits access="rw" name="loc_dis_set1" pos="0" rst="0">
          <comment>MPDCCH1
0(LOC)
1(DIS)</comment>
        </bits>
      </reg>
      <reg name="csi_rsmap1_nxt" protect="rw">
        <bits access="rw" name="csirs_group2" pos="23:12" rst="0">
          <comment>2PRBCSI-RSCSIRS_GROUP1</comment>
        </bits>
        <bits access="rw" name="csirs_group1" pos="11:0" rst="0">
          <comment>1PRBCSI-RS011PRBRE#0RE#1101RE#0CSI-RS</comment>
        </bits>
      </reg>
      <reg name="csi_rsmap2_nxt" protect="rw">
        <bits access="rw" name="csirs_group4" pos="23:12" rst="0">
          <comment>4PRBCSI-RSCSIRS_GROUP1</comment>
        </bits>
        <bits access="rw" name="csirs_group3" pos="11:0" rst="0">
          <comment>3PRBCSI-RSCSIRS_GROUP1</comment>
        </bits>
      </reg>
      <reg name="pmi_cfg_nxt" protect="rw">
        <bits access="rw" name="pmi_nrce" pos="18:16" rst="0">
          <comment>PMIcsi-NumrepetitionCE-R13:
0: 1
1: 2
2: 4
3: 8
4: 16
5: 32</comment>
        </bits>
        <bits access="rw" name="pmi_cbsr" pos="15:0" rst="0">
          <comment>PMI
0 PMIbit
1 PMIbit</comment>
        </bits>
      </reg>
      <reg name="pbch_cfg_nxt" protect="rw">
        <bits access="rw" name="pbch_val_bypass" pos="8" rst="0">
          <comment>PBCH
0
1</comment>
        </bits>
        <bits access="rw" name="pbch_det_sel" pos="7" rst="0">
          <comment>PBCH
0FDD90TDD05
10PBCH</comment>
        </bits>
        <bits access="rw" name="pbch_det_num" pos="6" rst="0">
          <comment>PBCH
0 1
1 2</comment>
        </bits>
        <bits access="rw" name="rep2_prior" pos="5:4" rst="0">
          <comment>PBCH2TDD03
0
1
2
3</comment>
        </bits>
        <bits access="rw" name="rep1_prior" pos="3:2" rst="0">
          <comment>PBCH1(TDD,FDD)03
0
1
2
3</comment>
        </bits>
        <bits access="rw" name="rep0_prior" pos="1:0" rst="0">
          <comment>PBCH(TDD/FDD)03
0
1
2
3</comment>
        </bits>
      </reg>
      <reg name="mpdcch_cfg_nxt" protect="rw">
        <bits access="rw" name="mpdcch_ue_bund" pos="21:20" rst="0">
          <comment>MPDCCHFHBUNDbit3PRB3PRB
Bit2013PRBBUND03PRBBUND
Bit2113PRBBUND03PRBBUND</comment>
        </bits>
        <bits access="rw" name="antdet_en" pos="19" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="maxtbs_flag" pos="18" rst="0">
          <comment>UL TBSIZE
0max1000
1max2984</comment>
        </bits>
        <bits access="rw" name="pdspusenh_flag" pos="17" rst="0">
          <comment>PDSCH_PUSCH
0
1</comment>
        </bits>
        <bits access="rw" name="tenhq_flag" pos="16" rst="0">
          <comment>FDD HARQ
08
110</comment>
        </bits>
        <bits access="rw" name="bund_flag" pos="15" rst="0">
          <comment>HARQ ACK
0
1</comment>
        </bits>
        <bits access="rw" name="schdenh_flag" pos="14" rst="0">
          <comment>0harq
1harq</comment>
        </bits>
        <bits access="rw" name="mpdcch_val_bypass" pos="13" rst="0">
          <comment>MPDCCH DCI
0
1</comment>
        </bits>
        <bits access="rw" name="mpdcch_srsreq_flag" pos="12" rst="1">
          <comment>MPDCCH SRSRREQ
0SRSRREQ
1SRSRREQ</comment>
        </bits>
        <bits access="rw" name="mpdcch_det_num_comm" pos="11:10" rst="0">
          <comment>MPDCCH COMM
0:1
1:2
2:3
3:4</comment>
        </bits>
        <bits access="rw" name="mpdcch_det_num_set" pos="9:8" rst="0">
          <comment>MPDCCH SET
0:1
1:2
2:3
3:4</comment>
        </bits>
        <bits access="rw" name="mpdcch_maxrep_ind_comm" pos="7:4" rst="0">
          <comment>MPDCCH COMM(1256)
0:1
1:2
2:4
3:8
4:16
8:256</comment>
        </bits>
        <bits access="rw" name="mpdcch_maxrep_ind_set1" pos="3:0" rst="0">
          <comment>MPDCCH SET1(1~256)
0:1
1:2
2:4
3:8
4:16
8:256</comment>
        </bits>
      </reg>
      <reg name="mpdcch_dcilen_nxt" protect="rw">
        <bits access="rw" name="dcilen_comm" pos="17:12" rst="0">
          <comment>MPDCCH COMM DCImax38</comment>
        </bits>
        <bits access="rw" name="dcilen_comm_set1" pos="11:6" rst="0">
          <comment>MPDCCH SET1 COMM DCImax38</comment>
        </bits>
        <bits access="rw" name="dcilen_uespec_set1" pos="5:0" rst="0">
          <comment>MPDCCH SET1 UESPEC DCImax38</comment>
        </bits>
      </reg>
      <reg name="mpdcch_repcnt_nxt" protect="rw">
        <bits access="rw" name="mpdcch_repcnt_set1" pos="7:0" rst="0">
          <comment>MPDCCH SET10255</comment>
        </bits>
      </reg>
      <reg name="pdsch_dciinfo_nxt" protect="rw">
        <bits access="rw" name="pmi_ind" pos="30:27" rst="0">
          <comment>tx2:03
tx4:015</comment>
        </bits>
        <bits access="rw" name="trans_scheme" pos="26:24" rst="0">
          <comment>0
1
2
3PORT7
4PORT8</comment>
        </bits>
        <bits access="rw" name="hq_proc_ind" pos="23:20" rst="0">
          <comment>HARQ015</comment>
        </bits>
        <bits access="rw" name="n_scid" pos="19" rst="0">
          <comment>NscidUE01</comment>
        </bits>
        <bits access="rw" name="rv_sel" pos="18:17" rst="0">
          <comment>03</comment>
        </bits>
        <bits access="rw" name="modu" pos="16" rst="0">
          <comment>0:QPSK
1:16QAM</comment>
        </bits>
        <bits access="rw" name="tbsize" pos="15:6" rst="0">
          <comment>max1000</comment>
        </bits>
        <bits access="rw" name="lcrb" pos="5:3" rst="0">
          <comment>RB16</comment>
        </bits>
        <bits access="rw" name="rb_start" pos="2:0" rst="0">
          <comment>RB05</comment>
        </bits>
      </reg>
      <reg name="agc_in_nxt" protect="rw">
        <bits access="rw" name="agc_in" pos="9:0" rst="0">
          <comment>AGC</comment>
        </bits>
      </reg>
      <reg name="fram_cnt_nxt" protect="rw">
        <bits access="rw" name="ssfn_cnt" pos="31:16" rst="0">
          <comment>065535</comment>
        </bits>
        <bits access="rw" name="rf_cnt" pos="13:4" rst="0">
          <comment>01023</comment>
        </bits>
        <bits access="rw" name="sf_cnt" pos="3:0" rst="0">
          <comment>09</comment>
        </bits>
      </reg>
      <reg name="ldtc_serv_nxt" protect="rw">
        <bits access="rw" name="cnnt_ra_proc" pos="12" rst="0">
          <comment>C-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="sib1_sel" pos="11" rst="0">
          <comment>SI-RNTISIB1SIB
0SIB1SIB
1SIB1</comment>
        </bits>
        <bits access="rw" name="c_sps_sel" pos="10" rst="0">
          <comment>PDSCHC-RNTSPS-C-RNTI
0C-RNTI
1SPS-RNTI</comment>
        </bits>
        <bits access="rw" name="si_rnti_en" pos="9" rst="0">
          <comment>SI-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="g_rnti_en" pos="8" rst="0">
          <comment>G-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="sc_rnti_en" pos="7" rst="0">
          <comment>SC-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="t_rnti_en" pos="6" rst="0">
          <comment>Temp-C-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="ra_rnti_en" pos="5" rst="0">
          <comment>RA-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="p_rnti_en" pos="4" rst="0">
          <comment>P-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="tpcs_rnti_en" pos="3" rst="0">
          <comment>TPC-PUSCH-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="tpcc_rnti_en" pos="2" rst="0">
          <comment>TPC-PUCCH-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="sps_rnti_en" pos="1" rst="0">
          <comment>SPS-C-RNTI
0
1</comment>
        </bits>
        <bits access="rw" name="c_rnti_en" pos="0" rst="0">
          <comment>C-RNTI
0
1</comment>
        </bits>
      </reg>
      <reg name="ldtc_ctrl_nxt" protect="rw">
        <bits access="rw" name="int_sel_dm" pos="30" rst="0">
          <comment>PDSCH/PBCH
0
1PDSCH /PBCH</comment>
        </bits>
        <bits access="rw" name="int_sel_c" pos="29" rst="0">
          <comment>MPDCCH
0
1MPDCCH</comment>
        </bits>
        <bits access="rw" name="int_en_dm" pos="28" rst="0">
          <comment>PDSCH/PBCHPMI
0
1</comment>
        </bits>
        <bits access="rw" name="int_en_c" pos="27" rst="0">
          <comment>MPDCCH(PMI)
0
1</comment>
        </bits>
        <bits access="rw" name="cfi_num" pos="26:25" rst="0">
          <comment>CFI
0:1
1:2
2:3
3:4</comment>
        </bits>
        <bits access="rw" name="drop_en" pos="24" rst="0">
          <comment>MPDCCH/PDSCHSIB
0
1</comment>
        </bits>
        <bits access="rw" name="pdsch_zero_en" pos="23" rst="0">
          <comment>PDSCH0
000
100</comment>
        </bits>
        <bits access="rw" name="csi_en" pos="22" rst="0">
          <comment>CSI RS
0
1</comment>
        </bits>
        <bits access="rw" name="int_sel" pos="21" rst="0">
          <comment>0
1PDSCH/MPDCCH/PBCH</comment>
        </bits>
        <bits access="rw" name="int_en" pos="20" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="qfqt_ppsel" pos="19:18" rst="0">
          <comment>QFQT
0Qtable0
1Qtable1
2Qtable2</comment>
        </bits>
        <bits access="rw" name="cemode" pos="17" rst="0">
          <comment>0CEA
1CEB</comment>
        </bits>
        <bits access="rw" name="nb_ind" pos="16:13" rst="0">
          <comment>:015</comment>
        </bits>
        <bits access="rw" name="mpdcch_set1_new_win" pos="12" rst="0">
          <comment>MPDCCH SET1
0
1</comment>
        </bits>
        <bits access="rw" name="pdsch_urs_new_win" pos="11" rst="0">
          <comment>PDSCH URS
0
1</comment>
        </bits>
        <bits access="rw" name="pdsch_crs_new_win" pos="10" rst="0">
          <comment>PDSCH CRS/PMI
0
1</comment>
        </bits>
        <bits access="rw" name="freq_hop" pos="9" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="mpdcch_set1_last" pos="8" rst="0">
          <comment>MPDCCH SET1
0
1</comment>
        </bits>
        <bits access="rw" name="pmi_first" pos="7" rst="0">
          <comment>PMI
0
1</comment>
        </bits>
        <bits access="rw" name="pdsch_first" pos="6" rst="0">
          <comment>PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="mpdcch_set1_first" pos="5" rst="0">
          <comment>MPDCCH SET1
0
1</comment>
        </bits>
        <bits access="rw" name="pbch_first" pos="4" rst="0">
          <comment>PBCH
0
1</comment>
        </bits>
        <bits access="rw" name="pmi_en" pos="3" rst="0">
          <comment>PMI
0
1</comment>
        </bits>
        <bits access="rw" name="pdsch_en" pos="2" rst="0">
          <comment>PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="mpdcch_en" pos="1" rst="0">
          <comment>MPDCCH
0
1</comment>
        </bits>
        <bits access="rw" name="pbch_en" pos="0" rst="0">
          <comment>PBCH
0
1</comment>
        </bits>
      </reg>
      <reg name="ldtc_start" protect="rw">
        <bits access="rw" name="ldtc_start_ldtc_start" pos="0" rst="0">
          <comment>LDTC
0
1</comment>
        </bits>
      </reg>
      <reg name="ldtc_flag" protect="rw">
        <bits access="rc" name="fin_flag" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
0LDTC
1LDTC</comment>
        </bits>
        <bits access="rc" name="pmi_flag" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PMI
0PMI
1PMI</comment>
        </bits>
        <bits access="rc" name="pdsch_flag" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PDSCH
0PDSCH
1PDSCH</comment>
        </bits>
        <bits access="rc" name="mpdcch_flag" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          MPDCCH
0MPDCCH
1PBCH</comment>
        </bits>
        <bits access="rc" name="pbch_flag" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PBCH
0PBCH
1PBCH</comment>
        </bits>
        <bits access="rc" name="int_flag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
      </reg>
      <reg name="ldtc_out" protect="r">
        <bits access="r" name="coeff_ping_pang" pos="22:21" rst="0">
          <comment>COEFF</comment>
        </bits>
        <bits access="r" name="dlfft_datmem_sel" pos="20" rst="0">
          <comment>DATMEM</comment>
        </bits>
        <bits access="r" name="dlfft_rsmem_sel" pos="19:17" rst="0">
          <comment>RSMEM0~4</comment>
        </bits>
        <bits access="r" name="dci_det_full" pos="16" rst="0">
          <comment>DCI
0
1</comment>
        </bits>
        <bits access="r" name="dci_rlastval" pos="15:12" rst="0">
          <comment>DCI Ri
0DCI
1DCIRi</comment>
        </bits>
        <bits access="r" name="dci_reconfmval" pos="11:8" rst="0">
          <comment>DCI2
0DCI
1DCI2</comment>
        </bits>
        <bits access="r" name="dci_nowvalid" pos="7:4" rst="0">
          <comment>DCI
0DCI
1DCI</comment>
        </bits>
        <bits access="r" name="mib_valid" pos="3:2" rst="0">
          <comment>MIB
0MIB
1MIB</comment>
        </bits>
        <bits access="r" name="pdsch_zero_flag" pos="1" rst="0">
          <comment>PDSCH CRC
0
1</comment>
        </bits>
        <bits access="r" name="pdsch_crc_flag" pos="0" rst="1">
          <comment>PDSCH CRC
0CRC
1CRC</comment>
        </bits>
      </reg>
      <reg name="ldtc_fram_out" protect="r">
        <bits access="r" name="ssfn_cnt" pos="31:16" rst="0">
          <comment>065535</comment>
        </bits>
        <bits access="r" name="rf_cnt" pos="13:4" rst="0">
          <comment>01023</comment>
        </bits>
        <bits access="r" name="sf_cnt" pos="3:0" rst="0">
          <comment>09</comment>
        </bits>
      </reg>
      <reg name="ldtc_par_out" protect="r">
        <bits access="r" name="mpdcch_cnt" pos="27:20" rst="0">
          <comment>MPDCCH CNT</comment>
        </bits>
        <bits access="r" name="hq_proc_ind" pos="19:16" rst="0">
          <comment>HARQ:0~15</comment>
        </bits>
        <bits access="r" name="dci_rnti_ind" pos="15:12" rst="0">
          <comment>RNTI
0RNTI0C-RNTI
1RNTI1SPS-C-RNTI
2RNTI2TPC-PDCCH-RNTI
3RNTI3TPC-PDSCH-RNTI
4RNTI4P-RNTI
5RNTI5RA-RNTI
6RNTI6Temp-C-RNTI
7RNTI7SC-RNTI
8RNTI7G-RNTI
9RNTI7SI-RNTI</comment>
        </bits>
        <bits access="r" name="cnnt_ra_proc" pos="11" rst="0">
          <comment>C-RNTI
0
1</comment>
        </bits>
        <bits access="r" name="sib1_sel" pos="10" rst="0">
          <comment>SI-RNTISIB1SIB
0SIB1SIB
1SIB1</comment>
        </bits>
        <bits access="r" name="ant_tx" pos="9:8" rst="0">
          <comment>MIB
0
12
24</comment>
        </bits>
        <bits access="r" name="mpdcch_repcnt_set1" pos="7:0" rst="0">
          <comment>MPDCCH SET10255</comment>
        </bits>
      </reg>
      <reg name="che_ir_para_nxt" protect="rw">
        <bits access="rw" name="pdsch_layer_num" pos="4" rst="1">
          <comment>PDSCH UE
0
1</comment>
        </bits>
        <bits access="rw" name="mpdcch_layer_num" pos="3" rst="0">
          <comment>MPDCCH
0MPDCCHextendCPMPDCCH
1MPDCCHnormalCP</comment>
        </bits>
        <bits access="rw" name="fir_iir_sel" pos="2" rst="0">
          <comment>FIR/IIR
0FIR
1IIR</comment>
        </bits>
        <bits access="rw" name="fir_win" pos="1:0" rst="0">
          <comment>FIR
0:1
1:2
2:3
3:4</comment>
        </bits>
      </reg>
      <reg name="che_iir_coef" protect="rw">
        <bits access="rw" name="coef1" pos="15:8" rst="63">
          <comment>IIRHLS</comment>
        </bits>
        <bits access="rw" name="coef0" pos="7:0" rst="64">
          <comment>FIRHLS</comment>
        </bits>
      </reg>
      <reg name="che_fir2_coef" protect="rw">
        <bits access="rw" name="coef2_1" pos="15:8" rst="63">
          <comment>FIR1HLS</comment>
        </bits>
        <bits access="rw" name="coef2_0" pos="7:0" rst="64">
          <comment>IIR/FIR0HLS</comment>
        </bits>
      </reg>
      <reg name="che_fir3_coef" protect="rw">
        <bits access="rw" name="coef3_2" pos="23:16" rst="42">
          <comment>FIR2HLS</comment>
        </bits>
        <bits access="rw" name="coef3_1" pos="15:8" rst="42">
          <comment>FIR1HLS</comment>
        </bits>
        <bits access="rw" name="coef3_0" pos="7:0" rst="43">
          <comment>FIR0HLS</comment>
        </bits>
      </reg>
      <reg name="che_fir4_coef" protect="rw">
        <bits access="rw" name="coef4_3" pos="31:24" rst="31">
          <comment>FIR3HLS</comment>
        </bits>
        <bits access="rw" name="coef4_2" pos="23:16" rst="32">
          <comment>FIR2HLS</comment>
        </bits>
        <bits access="rw" name="coef4_1" pos="15:8" rst="32">
          <comment>FIR1HLS</comment>
        </bits>
        <bits access="rw" name="coef4_0" pos="7:0" rst="32">
          <comment>FIR0HLS</comment>
        </bits>
      </reg>
      <reg name="che_fh_para" protect="rw">
        <bits access="rw" name="ue_bund" pos="8" rst="0">
          <comment>UE RSPRB1,3
0:1
1:3</comment>
        </bits>
        <bits access="rw" name="fh10_bitsel_type" pos="7" rst="1">
          <comment>16bit10bit
0
1</comment>
        </bits>
        <bits access="rw" name="fh10_bitsel" pos="6:4" rst="0">
          <comment>16bit10bit
0x015~6
0x114~5
0x213~4
0x312~3
0x411~2
0x510~1
0x69~0
RESERVED</comment>
        </bits>
        <bits access="rw" name="fh16_bitsel" pos="3:0" rst="6">
          <comment>16bit
0x028~13
0x127~12
0x226~11
0x325~10
0x424~9
0x523~8
0x622~7
0x721~6
0x820~5
0x919~4
0xa18~3
0xb17~2
0xc16~1
0xd15~0
RESERVED</comment>
        </bits>
      </reg>
      <reg name="che_th_para" protect="rw">
        <bits access="rw" name="th16_bitsel" pos="3:0" rst="5">
          <comment>0x02510
0x1249
0x2238
0x3227
0x4216
0x5205
0x6194
0x7183
0x8172
0x9161
0xa150</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_factor0" protect="rw">
        <bits access="rw" name="pbch_scale_sel" pos="27" rst="0">
          <comment>PBCH
0
1</comment>
        </bits>
        <bits access="rw" name="pbch_scale2" pos="26:18" rst="0">
          <comment>2</comment>
        </bits>
        <bits access="rw" name="pbch_scale1" pos="17:9" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="pbch_scale0" pos="8:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_factor1" protect="rw">
        <bits access="rw" name="mpdcch_scale_sel" pos="27" rst="0">
          <comment>MPDCCH
0
1</comment>
        </bits>
        <bits access="rw" name="mpdcch_scale2" pos="26:18" rst="0">
          <comment>2</comment>
        </bits>
        <bits access="rw" name="mpdcch_scale1" pos="17:9" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="mpdcch_scale0" pos="8:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_factor2" protect="rw">
        <bits access="rw" name="pdsch_scale_sel" pos="12" rst="0">
          <comment>PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="pdsch_scale0" pos="11:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_factor3" protect="rw">
        <bits access="rw" name="pdsch_scale2" pos="23:12" rst="0">
          <comment>2</comment>
        </bits>
        <bits access="rw" name="pdsch_scale1" pos="11:0" rst="0">
          <comment>1</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_factor4" protect="rw">
        <bits access="rw" name="pdsch_scale4" pos="23:12" rst="0">
          <comment>4</comment>
        </bits>
        <bits access="rw" name="pdsch_scale3" pos="11:0" rst="0">
          <comment>3</comment>
        </bits>
      </reg>
      <reg name="sd_data_factor1" protect="rw">
        <bits access="rw" name="cr_data_factor" pos="31:16" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
        <bits access="rw" name="ucr_data_factor" pos="15:0" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
      </reg>
      <reg name="sd_data_factor2" protect="rw">
        <bits access="rw" name="cr_data_factor" pos="31:16" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
        <bits access="rw" name="ucr_data_factor" pos="15:0" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
      </reg>
      <reg name="sd_data_factor3" protect="rw">
        <bits access="rw" name="cr_data_factor" pos="31:16" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
        <bits access="rw" name="ucr_data_factor" pos="15:0" rst="8192">
          <comment>OFDMCELL RSdata</comment>
        </bits>
      </reg>
      <reg name="sd_noise_nxt" protect="rw">
        <bits access="rw" name="noise" pos="31:0" rst="0">
          <comment>32Q3007fff_ffff</comment>
        </bits>
      </reg>
      <reg name="sd_noise_agc_nxt" protect="rw">
        <bits access="rw" name="noise_agc" pos="9:0" rst="0">
          <comment>AGC</comment>
        </bits>
      </reg>
      <reg name="sd_noise_th" protect="rw">
        <bits access="rw" name="noise_th_data" pos="31:16" rst="0">
          <comment>PDSCH(16~31bit)</comment>
        </bits>
        <bits access="rw" name="noise_th_ctrl" pos="15:0" rst="0">
          <comment>MPDCCH/PBCH(16~31bit)</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_bout0" protect="r">
        <bits access="r" name="bscale_out3" pos="7:6" rst="0">
          <comment>INDX3</comment>
        </bits>
        <bits access="r" name="bscale_out2" pos="5:4" rst="0">
          <comment>INDX2</comment>
        </bits>
        <bits access="r" name="bscale_out1" pos="3:2" rst="0">
          <comment>INDX1</comment>
        </bits>
        <bits access="r" name="bscale_out0" pos="1:0" rst="0">
          <comment>INDX0</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_bout1" protect="r">
        <bits access="r" name="bscale_out11" pos="15:14" rst="0">
          <comment>INDX11</comment>
        </bits>
        <bits access="r" name="bscale_out10" pos="13:12" rst="0">
          <comment>INDX10</comment>
        </bits>
        <bits access="r" name="bscale_out9" pos="11:10" rst="0">
          <comment>INDX9</comment>
        </bits>
        <bits access="r" name="bscale_out8" pos="9:8" rst="0">
          <comment>INDX8</comment>
        </bits>
        <bits access="r" name="bscale_out7" pos="7:6" rst="0">
          <comment>INDX7</comment>
        </bits>
        <bits access="r" name="bscale_out6" pos="5:4" rst="0">
          <comment>INDX6</comment>
        </bits>
        <bits access="r" name="bscale_out5" pos="3:2" rst="0">
          <comment>INDX5</comment>
        </bits>
        <bits access="r" name="bscale_out4" pos="1:0" rst="0">
          <comment>INDX4</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_bout2" protect="r">
        <bits access="r" name="bscale_out19" pos="15:14" rst="0">
          <comment>INDX19</comment>
        </bits>
        <bits access="r" name="bscale_out18" pos="13:12" rst="0">
          <comment>INDX18</comment>
        </bits>
        <bits access="r" name="bscale_out17" pos="11:10" rst="0">
          <comment>INDX17</comment>
        </bits>
        <bits access="r" name="bscale_out16" pos="9:8" rst="0">
          <comment>INDX16</comment>
        </bits>
        <bits access="r" name="bscale_out15" pos="7:6" rst="0">
          <comment>INDX15</comment>
        </bits>
        <bits access="r" name="bscale_out14" pos="5:4" rst="0">
          <comment>INDX14</comment>
        </bits>
        <bits access="r" name="bscale_out13" pos="3:2" rst="0">
          <comment>INDX13</comment>
        </bits>
        <bits access="r" name="bscale_out12" pos="1:0" rst="0">
          <comment>INDX12</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_cout0" protect="r">
        <bits access="r" name="cscale_out9" pos="19:18" rst="0">
          <comment>INDX9</comment>
        </bits>
        <bits access="r" name="cscale_out8" pos="17:16" rst="0">
          <comment>INDX8</comment>
        </bits>
        <bits access="r" name="cscale_out7" pos="15:14" rst="0">
          <comment>INDX7</comment>
        </bits>
        <bits access="r" name="cscale_out6" pos="13:12" rst="0">
          <comment>INDX6</comment>
        </bits>
        <bits access="r" name="cscale_out5" pos="11:10" rst="0">
          <comment>INDX5</comment>
        </bits>
        <bits access="r" name="cscale_out4" pos="9:8" rst="0">
          <comment>INDX4</comment>
        </bits>
        <bits access="r" name="cscale_out3" pos="7:6" rst="0">
          <comment>INDX3</comment>
        </bits>
        <bits access="r" name="cscale_out2" pos="5:4" rst="0">
          <comment>INDX2</comment>
        </bits>
        <bits access="r" name="cscale_out1" pos="3:2" rst="0">
          <comment>INDX1</comment>
        </bits>
        <bits access="r" name="cscale_out0" pos="1:0" rst="0">
          <comment>INDX0</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_cout1" protect="r">
        <bits access="r" name="cscale_out19" pos="19:18" rst="0">
          <comment>INDX19</comment>
        </bits>
        <bits access="r" name="cscale_out18" pos="17:16" rst="0">
          <comment>INDX18</comment>
        </bits>
        <bits access="r" name="cscale_out17" pos="15:14" rst="0">
          <comment>INDX17</comment>
        </bits>
        <bits access="r" name="cscale_out16" pos="13:12" rst="0">
          <comment>INDX16</comment>
        </bits>
        <bits access="r" name="cscale_out15" pos="11:10" rst="0">
          <comment>INDX15</comment>
        </bits>
        <bits access="r" name="cscale_out14" pos="9:8" rst="0">
          <comment>INDX14</comment>
        </bits>
        <bits access="r" name="cscale_out13" pos="7:6" rst="0">
          <comment>INDX13</comment>
        </bits>
        <bits access="r" name="cscale_out12" pos="5:4" rst="0">
          <comment>INDX12</comment>
        </bits>
        <bits access="r" name="cscale_out11" pos="3:2" rst="0">
          <comment>INDX11</comment>
        </bits>
        <bits access="r" name="cscale_out10" pos="1:0" rst="0">
          <comment>INDX10</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_cout2" protect="r">
        <bits access="r" name="cscale_out32" pos="25:24" rst="0">
          <comment>INDX32</comment>
        </bits>
        <bits access="r" name="cscale_out31" pos="23:22" rst="0">
          <comment>INDX31</comment>
        </bits>
        <bits access="r" name="cscale_out30" pos="21:20" rst="0">
          <comment>INDX30</comment>
        </bits>
        <bits access="r" name="cscale_out29" pos="19:18" rst="0">
          <comment>INDX29</comment>
        </bits>
        <bits access="r" name="cscale_out28" pos="17:16" rst="0">
          <comment>INDX28</comment>
        </bits>
        <bits access="r" name="cscale_out27" pos="15:14" rst="0">
          <comment>INDX27</comment>
        </bits>
        <bits access="r" name="cscale_out26" pos="13:12" rst="0">
          <comment>INDX26</comment>
        </bits>
        <bits access="r" name="cscale_out25" pos="11:10" rst="0">
          <comment>INDX25</comment>
        </bits>
        <bits access="r" name="cscale_out24" pos="9:8" rst="0">
          <comment>INDX24</comment>
        </bits>
        <bits access="r" name="cscale_out23" pos="7:6" rst="0">
          <comment>INDX23</comment>
        </bits>
        <bits access="r" name="cscale_out22" pos="5:4" rst="0">
          <comment>INDX22</comment>
        </bits>
        <bits access="r" name="cscale_out21" pos="3:2" rst="0">
          <comment>INDX21</comment>
        </bits>
        <bits access="r" name="cscale_out20" pos="1:0" rst="0">
          <comment>INDX20</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_dout0" protect="r">
        <bits access="r" name="dscale_out7" pos="23:21" rst="0">
          <comment>INDX7</comment>
        </bits>
        <bits access="r" name="dscale_out6" pos="20:18" rst="0">
          <comment>INDX6</comment>
        </bits>
        <bits access="r" name="dscale_out5" pos="17:15" rst="0">
          <comment>INDX5</comment>
        </bits>
        <bits access="r" name="dscale_out4" pos="14:12" rst="0">
          <comment>INDX4</comment>
        </bits>
        <bits access="r" name="dscale_out3" pos="11:9" rst="0">
          <comment>INDX3</comment>
        </bits>
        <bits access="r" name="dscale_out2" pos="8:6" rst="0">
          <comment>INDX2</comment>
        </bits>
        <bits access="r" name="dscale_out1" pos="5:3" rst="0">
          <comment>INDX1</comment>
        </bits>
        <bits access="r" name="dscale_out0" pos="2:0" rst="0">
          <comment>INDX0</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_dout1" protect="r">
        <bits access="r" name="dscale_out15" pos="23:21" rst="0">
          <comment>INDX15</comment>
        </bits>
        <bits access="r" name="dscale_out14" pos="20:18" rst="0">
          <comment>INDX14</comment>
        </bits>
        <bits access="r" name="dscale_out13" pos="17:15" rst="0">
          <comment>INDX13</comment>
        </bits>
        <bits access="r" name="dscale_out12" pos="14:12" rst="0">
          <comment>INDX12</comment>
        </bits>
        <bits access="r" name="dscale_out11" pos="11:9" rst="0">
          <comment>INDX11</comment>
        </bits>
        <bits access="r" name="dscale_out10" pos="8:6" rst="0">
          <comment>INDX10</comment>
        </bits>
        <bits access="r" name="dscale_out9" pos="5:3" rst="0">
          <comment>INDX9</comment>
        </bits>
        <bits access="r" name="dscale_out8" pos="2:0" rst="0">
          <comment>INDX8</comment>
        </bits>
      </reg>
      <reg name="sd_scaling_dout2" protect="r">
        <bits access="r" name="dscale_out16" pos="2:0" rst="0">
          <comment>INDX16</comment>
        </bits>
      </reg>
      <reg name="hq_mpdcch_cut" protect="rw">
        <bits access="rw" name="hq_ccut2" pos="15:8" rst="128">
          <comment>HARQ1280255</comment>
        </bits>
        <bits access="rw" name="hq_ccut1" pos="7:0" rst="32">
          <comment>HARQ320255</comment>
        </bits>
      </reg>
      <reg name="hq_pdsch_cut" protect="rw">
        <bits access="rw" name="hq_dcut2" pos="25:13" rst="64">
          <comment>HARQ6408191</comment>
        </bits>
        <bits access="rw" name="hq_dcut1" pos="12:0" rst="16">
          <comment>HARQ1608191</comment>
        </bits>
      </reg>
      <reg name="hq_ypk0" protect="rw">
        <bits access="rw" name="ypk4" pos="19:16" rst="0">
          <comment>MPDCCH m ECCEYpk4</comment>
        </bits>
        <bits access="rw" name="ypk3" pos="15:12" rst="0">
          <comment>MPDCCH m ECCEYpk3</comment>
        </bits>
        <bits access="rw" name="ypk2" pos="11:8" rst="0">
          <comment>MPDCCH m ECCEYpk2</comment>
        </bits>
        <bits access="rw" name="ypk1" pos="7:4" rst="0">
          <comment>MPDCCH m ECCEYpk1</comment>
        </bits>
        <bits access="rw" name="ypk0" pos="3:0" rst="0">
          <comment>MPDCCH m ECCEYpk0</comment>
        </bits>
      </reg>
      <reg name="hq_ypk1" protect="rw">
        <bits access="rw" name="ypk9" pos="19:16" rst="0">
          <comment>MPDCCH m ECCEYpk9</comment>
        </bits>
        <bits access="rw" name="ypk8" pos="15:12" rst="0">
          <comment>MPDCCH m ECCEYpk8</comment>
        </bits>
        <bits access="rw" name="ypk7" pos="11:8" rst="0">
          <comment>MPDCCH m ECCEYpk7</comment>
        </bits>
        <bits access="rw" name="ypk6" pos="7:4" rst="0">
          <comment>MPDCCH m ECCEYpk6</comment>
        </bits>
        <bits access="rw" name="ypk5" pos="3:0" rst="0">
          <comment>MPDCCH m ECCEYpk5</comment>
        </bits>
      </reg>
      <reg name="hq_hb_sta" protect="rw">
        <bits access="rc" name="hb7_sta" pos="7" rst="0">
          <comment>bit type is changed from rw1c to rc.
          7HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb6_sta" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          6HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb5_sta" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          5HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb4_sta" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          4HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb3_sta" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          3HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb2_sta" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          2HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb1_sta" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1HARQBUFFER
0:
1:</comment>
        </bits>
        <bits access="rc" name="hb0_sta" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0HARQBUFFER
0:
1:</comment>
        </bits>
      </reg>
      <reg name="hq_hb_proc" protect="r">
        <bits access="r" name="hb7_sta" pos="31:28" rst="0">
          <comment>7HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb6_sta" pos="27:24" rst="0">
          <comment>6HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb5_sta" pos="23:20" rst="0">
          <comment>5HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb4_sta" pos="19:16" rst="0">
          <comment>4HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb3_sta" pos="15:12" rst="0">
          <comment>3HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb2_sta" pos="11:8" rst="0">
          <comment>2HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb1_sta" pos="7:4" rst="0">
          <comment>1HARQBUFFER:0~15</comment>
        </bits>
        <bits access="r" name="hb0_sta" pos="3:0" rst="0">
          <comment>0HARQBUFFER:0~15</comment>
        </bits>
      </reg>
      <reg name="hq_pdsch_info1" protect="r">
        <bits access="r" name="hq_tbsize" pos="21:12" rst="0">
          <comment>max1000</comment>
        </bits>
        <bits access="r" name="hq_pdsch_e" pos="11:0" rst="0">
          <comment>PDSCH</comment>
        </bits>
      </reg>
      <reg name="hq_pdsch_info2" protect="r">
        <bits access="r" name="hq_pdsch_ave" pos="22:13" rst="0">
          <comment>PDSCH</comment>
        </bits>
        <bits access="r" name="hq_comb_dcnt" pos="12:0" rst="0">
          <comment>PDSCHmax4*2048-1</comment>
        </bits>
      </reg>
      <reg name="turbo_para" protect="rw">
        <bits access="rw" name="shift_en" pos="14" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="ave_sel" pos="13:12" rst="2">
          <comment>N
01
11.5
22
3 2.5</comment>
        </bits>
        <bits access="rw" name="shift_iternum2" pos="11:8" rst="5">
          <comment>2</comment>
        </bits>
        <bits access="rw" name="shift_iternum1" pos="7:4" rst="2">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="iter_num_max" pos="3:0" rst="8">
          <comment>1
908</comment>
        </bits>
      </reg>
      <reg name="turbo_iter" protect="r">
        <bits access="r" name="real_iter" pos="3:0" rst="0">
          <comment>-1</comment>
        </bits>
      </reg>
      <reg name="vit_itnum" protect="rw">
        <bits access="rw" name="vit_itnum_vit_itnum" pos="1:0" rst="1">
          <comment>VIT
0:1
1:2
2:3
3:4</comment>
        </bits>
      </reg>
      <reg name="dci0_out1" protect="r">
        <bits access="r" name="dci0_out1_dci0_out1" pos="31:0" rst="0">
          <comment>DCI032</comment>
        </bits>
      </reg>
      <reg name="dci0_out2" protect="r">
        <bits access="r" name="dci0_out2_dci0_out2" pos="31:0" rst="0">
          <comment>DCI032</comment>
        </bits>
      </reg>
      <reg name="dci0_info1" protect="r">
        <bits access="r" name="trans_scheme" pos="29:27" rst="0">
          <comment>0
1
2
3PORT7
4PORT8</comment>
        </bits>
        <bits access="r" name="ant_sel" pos="26" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="r" name="dci_prb_len" pos="25:24" rst="0">
          <comment>PRB2+4DCIPRB
0:2PRB
1:4PRB
2:6PRB</comment>
        </bits>
        <bits access="r" name="dci_set_ind" pos="23" rst="0">
          <comment>DCI
01
12</comment>
        </bits>
        <bits access="r" name="dci_comm_ue" pos="22" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="r" name="dci_ri_ind" pos="21:20" rst="0">
          <comment>DCIRi
0R0
1R1
2R2
3R3</comment>
        </bits>
        <bits access="r" name="dci_port_sel" pos="19:18" rst="0">
          <comment>DCIPORTn0
Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8
0PORT107
1PORT108
2PORT109
3PORT110
Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9
0:107
1:109
Extended cyclic prefix
0:107
1:108</comment>
        </bits>
        <bits access="r" name="dci_start_pos" pos="17:13" rst="0">
          <comment>DCI(index:023)</comment>
        </bits>
        <bits access="r" name="dci_rnti_ind" pos="12:9" rst="0">
          <comment>DCI RNTI
0RNTI0C-RNTI
1RNTI1SPS-C-RNTI
2RNTI2TPC-PDCCH-RNTI
3RNTI3TPC-PDSCH-RNTI
4RNTI4P-RNTI
5RNTI5RA-RNTI
6RNTI6Temp-C-RNTI
7RNTI7SC-RNTI
8RNTI8G-RNTI</comment>
        </bits>
        <bits access="r" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="r" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci0_info2" protect="r">
        <bits access="r" name="pmi_ind" pos="30:27" rst="0">
          <comment>tx2:03tx4:015</comment>
        </bits>
        <bits access="r" name="hq_proc_ind" pos="26:23" rst="0">
          <comment>HARQ:015</comment>
        </bits>
        <bits access="r" name="n_scid" pos="22" rst="0">
          <comment>Nscid(UE)01</comment>
        </bits>
        <bits access="r" name="rv_sel" pos="21:20" rst="0">
          <comment>03</comment>
        </bits>
        <bits access="r" name="modu" pos="19" rst="0">
          <comment>0:QPSK
1:16QAM</comment>
        </bits>
        <bits access="r" name="tbsize" pos="18:6" rst="0">
          <comment>max2984</comment>
        </bits>
        <bits access="r" name="lcrb" pos="5:3" rst="0">
          <comment>RB16</comment>
        </bits>
        <bits access="r" name="rb_start" pos="2:0" rst="0">
          <comment>RB05</comment>
        </bits>
      </reg>
      <reg name="dci0_info3" protect="r">
        <bits access="r" name="ackdly" pos="29:27" rst="0">
          <comment>HARQ-ACK delay</comment>
        </bits>
        <bits access="r" name="bundling" pos="26" rst="0">
          <comment>HARQ-ACK bundling flag</comment>
        </bits>
        <bits access="r" name="sps_ind" pos="25:24" rst="0">
          <comment>SPS-C-RNTI
0
1
2</comment>
        </bits>
        <bits access="r" name="ackoffset_scnote" pos="23:22" rst="0">
          <comment>DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification</comment>
        </bits>
        <bits access="r" name="srsreq" pos="21" rst="0">
          <comment>DCI6-0A /DCI6-1ASRS</comment>
        </bits>
        <bits access="r" name="csireq" pos="20" rst="0">
          <comment>DCI6-0ACSI</comment>
        </bits>
        <bits access="r" name="dai_ulind" pos="19:18" rst="0">
          <comment>DCI6-1A/DCI6-0A(TDD,uldl:16)DAI
DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX</comment>
        </bits>
        <bits access="r" name="tpc" pos="17:16" rst="0">
          <comment>DCI6-0A /DCI6-1A</comment>
        </bits>
        <bits access="r" name="ndi" pos="15" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="rep" pos="14:12" rst="0">
          <comment>PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03)</comment>
        </bits>
        <bits access="r" name="dci_rep_bund_num" pos="11:10" rst="0">
          <comment>MPDCCH DCI (03),Transport blocks in a bundle</comment>
        </bits>
        <bits access="r" name="di_order_flag" pos="9" rst="0">
          <comment>DCI2DI(direct indication)
0PAGING
1DI
DCI6-1ADCI1-BPDCCH ORDER
0ORDER
1ORDER</comment>
        </bits>
        <bits access="r" name="pmi_sel" pos="8" rst="0">
          <comment>0DCI
1</comment>
        </bits>
        <bits access="r" name="fhop_en" pos="7" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="r" name="dci_format" pos="6:4" rst="0">
          <comment>DCI
0:DCI6-1A
1:DCI6-1B
2:DCI6-0A
3:DCI6-0B
4:DCI3/3A
5:DCI2</comment>
        </bits>
        <bits access="r" name="nb_ind" pos="3:0" rst="0">
          <comment>015</comment>
        </bits>
      </reg>
      <reg name="dci0_info4" protect="r">
        <bits access="r" name="tbsize2" pos="11:0" rst="0">
          <comment>DCI6-1APDSCH1tbsize</comment>
        </bits>
      </reg>
      <reg name="dci0_pwr" protect="r">
        <bits access="r" name="dci_fa" pos="31:24" rst="0">
          <comment>DCIfalse alarm(vit)</comment>
        </bits>
        <bits access="r" name="dci_fa_zero" pos="23:16" rst="0">
          <comment>DCIfalse alarm0</comment>
        </bits>
        <bits access="r" name="dci_pwr" pos="15:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci1_out1" protect="r">
        <bits access="r" name="dci1_out1_dci1_out1" pos="31:0" rst="0">
          <comment>DCI132</comment>
        </bits>
      </reg>
      <reg name="dci1_out2" protect="r">
        <bits access="r" name="dci1_out2_dci1_out2" pos="31:0" rst="0">
          <comment>DCI132</comment>
        </bits>
      </reg>
      <reg name="dci1_info1" protect="r">
        <bits access="r" name="trans_scheme" pos="29:27" rst="0">
          <comment>0
1
2
3PORT7
4PORT8</comment>
        </bits>
        <bits access="r" name="ant_sel" pos="26" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="r" name="dci_prb_len" pos="25:24" rst="0">
          <comment>PRB2+4DCIPRB
0:2PRB
1:4PRB
2:6PRB</comment>
        </bits>
        <bits access="r" name="dci_set_ind" pos="23" rst="0">
          <comment>DCI
01
12</comment>
        </bits>
        <bits access="r" name="dci_comm_ue" pos="22" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="r" name="dci_ri_ind" pos="21:20" rst="0">
          <comment>DCIRi
0R0
1R1
2R2
3R3</comment>
        </bits>
        <bits access="r" name="dci_port_sel" pos="19:18" rst="0">
          <comment>DCIPORTn0
Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8
0PORT107
1PORT108
2PORT109
3PORT110
Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9
0:107
1:109
Extended cyclic prefix
0:107
1:108</comment>
        </bits>
        <bits access="r" name="dci_start_pos" pos="17:13" rst="0">
          <comment>DCI(index:023)</comment>
        </bits>
        <bits access="r" name="dci_rnti_ind" pos="12:9" rst="0">
          <comment>DCI RNTI
0RNTI0C-RNTI
1RNTI1SPS-C-RNTI
2RNTI2TPC-PDCCH-RNTI
3RNTI3TPC-PDSCH-RNTI
4RNTI4P-RNTI
5RNTI5RA-RNTI
6RNTI6Temp-C-RNTI
7RNTI7SC-RNTI
8RNTI8G-RNTI</comment>
        </bits>
        <bits access="r" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="r" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci1_info2" protect="r">
        <bits access="r" name="pmi_ind" pos="30:27" rst="0">
          <comment>tx2:03tx4:015</comment>
        </bits>
        <bits access="r" name="hq_proc_ind" pos="26:23" rst="0">
          <comment>HARQ:015</comment>
        </bits>
        <bits access="r" name="n_scid" pos="22" rst="0">
          <comment>Nscid(UE)01</comment>
        </bits>
        <bits access="r" name="rv_sel" pos="21:20" rst="0">
          <comment>03</comment>
        </bits>
        <bits access="r" name="modu" pos="19" rst="0">
          <comment>0:QPSK
1:16QAM</comment>
        </bits>
        <bits access="r" name="tbsize" pos="18:6" rst="0">
          <comment>max2984</comment>
        </bits>
        <bits access="r" name="lcrb" pos="5:3" rst="0">
          <comment>RB16</comment>
        </bits>
        <bits access="r" name="rb_start" pos="2:0" rst="0">
          <comment>RB05</comment>
        </bits>
      </reg>
      <reg name="dci1_info3" protect="r">
        <bits access="r" name="ackdly" pos="29:27" rst="0">
          <comment>HARQ-ACK delay</comment>
        </bits>
        <bits access="r" name="bundling" pos="26" rst="0">
          <comment>HARQ-ACK bundling flag</comment>
        </bits>
        <bits access="r" name="sps_ind" pos="25:24" rst="0">
          <comment>SPS-C-RNTI
0
1
2</comment>
        </bits>
        <bits access="r" name="ackoffset_scnote" pos="23:22" rst="0">
          <comment>DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification</comment>
        </bits>
        <bits access="r" name="srsreq" pos="21" rst="0">
          <comment>DCI6-0A /DCI6-1ASRS</comment>
        </bits>
        <bits access="r" name="csireq" pos="20" rst="0">
          <comment>DCI6-0ACSI</comment>
        </bits>
        <bits access="r" name="dai_ulind" pos="19:18" rst="0">
          <comment>DCI6-1A/DCI6-0A(TDD,uldl:16)DAI
DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX</comment>
        </bits>
        <bits access="r" name="tpc" pos="17:16" rst="0">
          <comment>DCI6-0A /DCI6-1A</comment>
        </bits>
        <bits access="r" name="ndi" pos="15" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="rep" pos="14:12" rst="0">
          <comment>PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03)</comment>
        </bits>
        <bits access="r" name="dci_rep_bund_num" pos="11:10" rst="0">
          <comment>MPDCCH DCI (03),Transport blocks in a bundle</comment>
        </bits>
        <bits access="r" name="di_order_flag" pos="9" rst="0">
          <comment>DCI2DI(direct indication)
0PAGING
1DI
DCI6-1ADCI1-BPDCCH ORDER
0ORDER
1ORDER</comment>
        </bits>
        <bits access="r" name="pmi_sel" pos="8" rst="0">
          <comment>0DCI
1</comment>
        </bits>
        <bits access="r" name="fhop_en" pos="7" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="r" name="dci_format" pos="6:4" rst="0">
          <comment>DCI
0:DCI6-1A
1:DCI6-1B
2:DCI6-0A
3:DCI6-0B
4:DCI3/3A
5:DCI2</comment>
        </bits>
        <bits access="r" name="nb_ind" pos="3:0" rst="0">
          <comment>015</comment>
        </bits>
      </reg>
      <reg name="dci1_info4" protect="r">
        <bits access="r" name="tbsize2" pos="11:0" rst="0">
          <comment>DCI6-1APDSCH1tbsize</comment>
        </bits>
      </reg>
      <reg name="dci1_pwr" protect="r">
        <bits access="r" name="dci_fa" pos="31:24" rst="0">
          <comment>DCIfalse alarm(vit)</comment>
        </bits>
        <bits access="r" name="dci_fa_zero" pos="23:16" rst="0">
          <comment>DCIfalse alarm0</comment>
        </bits>
        <bits access="r" name="dci_pwr" pos="15:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci2_out1" protect="r">
        <bits access="r" name="dci2_out1_dci2_out1" pos="31:0" rst="0">
          <comment>DCI232</comment>
        </bits>
      </reg>
      <reg name="dci2_out2" protect="r">
        <bits access="r" name="dci2_out2_dci2_out2" pos="31:0" rst="0">
          <comment>DCI232</comment>
        </bits>
      </reg>
      <reg name="dci2_info1" protect="r">
        <bits access="r" name="trans_scheme" pos="29:27" rst="0">
          <comment>0
1
2
3PORT7
4PORT8</comment>
        </bits>
        <bits access="r" name="ant_sel" pos="26" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="r" name="dci_prb_len" pos="25:24" rst="0">
          <comment>PRB2+4DCIPRB
0:2PRB
1:4PRB
2:6PRB</comment>
        </bits>
        <bits access="r" name="dci_set_ind" pos="23" rst="0">
          <comment>DCI
01
12</comment>
        </bits>
        <bits access="r" name="dci_comm_ue" pos="22" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="r" name="dci_ri_ind" pos="21:20" rst="0">
          <comment>DCIRi
0R0
1R1
2R2
3R3</comment>
        </bits>
        <bits access="r" name="dci_port_sel" pos="19:18" rst="0">
          <comment>DCIPORTn0
Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8
0PORT107
1PORT108
2PORT109
3PORT110
Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9
0:107
1:109
Extended cyclic prefix
0:107
1:108</comment>
        </bits>
        <bits access="r" name="dci_start_pos" pos="17:13" rst="0">
          <comment>DCI(index:023)</comment>
        </bits>
        <bits access="r" name="dci_rnti_ind" pos="12:9" rst="0">
          <comment>DCI RNTI
0RNTI0C-RNTI
1RNTI1SPS-C-RNTI
2RNTI2TPC-PDCCH-RNTI
3RNTI3TPC-PDSCH-RNTI
4RNTI4P-RNTI
5RNTI5RA-RNTI
6RNTI6Temp-C-RNTI
7RNTI7SC-RNTI
8RNTI8G-RNTI</comment>
        </bits>
        <bits access="r" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="r" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci2_info2" protect="r">
        <bits access="r" name="pmi_ind" pos="30:27" rst="0">
          <comment>tx2:03tx4:015</comment>
        </bits>
        <bits access="r" name="hq_proc_ind" pos="26:23" rst="0">
          <comment>HARQ:015</comment>
        </bits>
        <bits access="r" name="n_scid" pos="22" rst="0">
          <comment>Nscid(UE)01</comment>
        </bits>
        <bits access="r" name="rv_sel" pos="21:20" rst="0">
          <comment>03</comment>
        </bits>
        <bits access="r" name="modu" pos="19" rst="0">
          <comment>0:QPSK
1:16QAM</comment>
        </bits>
        <bits access="r" name="tbsize" pos="18:6" rst="0">
          <comment>max2984</comment>
        </bits>
        <bits access="r" name="lcrb" pos="5:3" rst="0">
          <comment>RB16</comment>
        </bits>
        <bits access="r" name="rb_start" pos="2:0" rst="0">
          <comment>RB05</comment>
        </bits>
      </reg>
      <reg name="dci2_info3" protect="r">
        <bits access="r" name="ackdly" pos="29:27" rst="0">
          <comment>HARQ-ACK delay</comment>
        </bits>
        <bits access="r" name="bundling" pos="26" rst="0">
          <comment>HARQ-ACK bundling flag</comment>
        </bits>
        <bits access="r" name="sps_ind" pos="25:24" rst="0">
          <comment>SPS-C-RNTI
0
1
2</comment>
        </bits>
        <bits access="r" name="ackoffset_scnote" pos="23:22" rst="0">
          <comment>DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification</comment>
        </bits>
        <bits access="r" name="srsreq" pos="21" rst="0">
          <comment>DCI6-0A /DCI6-1ASRS</comment>
        </bits>
        <bits access="r" name="csireq" pos="20" rst="0">
          <comment>DCI6-0ACSI</comment>
        </bits>
        <bits access="r" name="dai_ulind" pos="19:18" rst="0">
          <comment>DCI6-1A/DCI6-0A(TDD,uldl:16)DAI
DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX</comment>
        </bits>
        <bits access="r" name="tpc" pos="17:16" rst="0">
          <comment>DCI6-0A /DCI6-1A</comment>
        </bits>
        <bits access="r" name="ndi" pos="15" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="rep" pos="14:12" rst="0">
          <comment>PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03)</comment>
        </bits>
        <bits access="r" name="dci_rep_bund_num" pos="11:10" rst="0">
          <comment>MPDCCH DCI (03),Transport blocks in a bundle</comment>
        </bits>
        <bits access="r" name="di_order_flag" pos="9" rst="0">
          <comment>DCI2DI(direct indication)
0PAGING
1DI
DCI6-1ADCI1-BPDCCH ORDER
0ORDER
1ORDER</comment>
        </bits>
        <bits access="r" name="pmi_sel" pos="8" rst="0">
          <comment>0DCI
1</comment>
        </bits>
        <bits access="r" name="fhop_en" pos="7" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="r" name="dci_format" pos="6:4" rst="0">
          <comment>DCI
0:DCI6-1A
1:DCI6-1B
2:DCI6-0A
3:DCI6-0B
4:DCI3/3A
5:DCI2</comment>
        </bits>
        <bits access="r" name="nb_ind" pos="3:0" rst="0">
          <comment>015</comment>
        </bits>
      </reg>
      <reg name="dci2_info4" protect="r">
        <bits access="r" name="tbsize2" pos="11:0" rst="0">
          <comment>DCI6-1APDSCH1tbsize</comment>
        </bits>
      </reg>
      <reg name="dci2_pwr" protect="r">
        <bits access="r" name="dci_fa" pos="31:24" rst="0">
          <comment>DCIfalse alarm(vit)</comment>
        </bits>
        <bits access="r" name="dci_fa_zero" pos="23:16" rst="0">
          <comment>DCIfalse alarm0</comment>
        </bits>
        <bits access="r" name="dci_pwr" pos="15:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="dci3_out1" protect="r">
        <bits access="r" name="dci3_out1_dci3_out1" pos="31:0" rst="0">
          <comment>DCI332</comment>
        </bits>
      </reg>
      <reg name="dci3_out2" protect="r">
        <bits access="r" name="dci3_out2_dci3_out2" pos="31:0" rst="0">
          <comment>DCI332</comment>
        </bits>
      </reg>
      <reg name="dci3_info1" protect="r">
        <bits access="r" name="trans_scheme" pos="29:27" rst="0">
          <comment>0
1
2
3PORT7
4PORT8</comment>
        </bits>
        <bits access="r" name="ant_sel" pos="26" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="r" name="dci_prb_len" pos="25:24" rst="0">
          <comment>PRB2+4DCIPRB
0:2PRB
1:4PRB
2:6PRB</comment>
        </bits>
        <bits access="r" name="dci_set_ind" pos="23" rst="0">
          <comment>DCI
01
12</comment>
        </bits>
        <bits access="r" name="dci_comm_ue" pos="22" rst="0">
          <comment>DCICOMMUE
0
1UE</comment>
        </bits>
        <bits access="r" name="dci_ri_ind" pos="21:20" rst="0">
          <comment>DCIRi
0R0
1R1
2R2
3R3</comment>
        </bits>
        <bits access="r" name="dci_port_sel" pos="19:18" rst="0">
          <comment>DCIPORTn0
Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8
0PORT107
1PORT108
2PORT109
3PORT110
Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9
0:107
1:109
Extended cyclic prefix
0:107
1:108</comment>
        </bits>
        <bits access="r" name="dci_start_pos" pos="17:13" rst="0">
          <comment>DCI(index:023)</comment>
        </bits>
        <bits access="r" name="dci_rnti_ind" pos="12:9" rst="0">
          <comment>DCI RNTI
0RNTI0C-RNTI
1RNTI1SPS-C-RNTI
2RNTI2TPC-PDCCH-RNTI
3RNTI3TPC-PDSCH-RNTI
4RNTI4P-RNTI
5RNTI5RA-RNTI
6RNTI6Temp-C-RNTI
7RNTI7SC-RNTI
8RNTI8G-RNTI</comment>
        </bits>
        <bits access="r" name="dci_llevel" pos="8:6" rst="0">
          <comment>DCIL
000L=1;
001L=2;
010L=4;
011L=8;
100L=12;
101L=16;
110L=24;</comment>
        </bits>
        <bits access="r" name="dci_len" pos="5:0" rst="0">
          <comment>DCI (max38)</comment>
        </bits>
      </reg>
      <reg name="dci3_info2" protect="r">
        <bits access="r" name="pmi_ind" pos="30:27" rst="0">
          <comment>tx2:03tx4:015</comment>
        </bits>
        <bits access="r" name="hq_proc_ind" pos="26:23" rst="0">
          <comment>HARQ:015</comment>
        </bits>
        <bits access="r" name="n_scid" pos="22" rst="0">
          <comment>Nscid(UE)01</comment>
        </bits>
        <bits access="r" name="rv_sel" pos="21:20" rst="0">
          <comment>03</comment>
        </bits>
        <bits access="r" name="modu" pos="19" rst="0">
          <comment>0:QPSK
1:16QAM</comment>
        </bits>
        <bits access="r" name="tbsize" pos="18:6" rst="0">
          <comment>max2984</comment>
        </bits>
        <bits access="r" name="lcrb" pos="5:3" rst="0">
          <comment>RB16</comment>
        </bits>
        <bits access="r" name="rb_start" pos="2:0" rst="0">
          <comment>RB05</comment>
        </bits>
      </reg>
      <reg name="dci3_info3" protect="r">
        <bits access="r" name="ackdly" pos="29:27" rst="0">
          <comment>HARQ-ACK delay</comment>
        </bits>
        <bits access="r" name="bundling" pos="26" rst="0">
          <comment>HARQ-ACK bundling flag</comment>
        </bits>
        <bits access="r" name="sps_ind" pos="25:24" rst="0">
          <comment>SPS-C-RNTI
0
1
2</comment>
        </bits>
        <bits access="r" name="ackoffset_scnote" pos="23:22" rst="0">
          <comment>DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification</comment>
        </bits>
        <bits access="r" name="srsreq" pos="21" rst="0">
          <comment>DCI6-0A /DCI6-1ASRS</comment>
        </bits>
        <bits access="r" name="csireq" pos="20" rst="0">
          <comment>DCI6-0ACSI</comment>
        </bits>
        <bits access="r" name="dai_ulind" pos="19:18" rst="0">
          <comment>DCI6-1A/DCI6-0A(TDD,uldl:16)DAI
DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX</comment>
        </bits>
        <bits access="r" name="tpc" pos="17:16" rst="0">
          <comment>DCI6-0A /DCI6-1A</comment>
        </bits>
        <bits access="r" name="ndi" pos="15" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="rep" pos="14:12" rst="0">
          <comment>PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03)</comment>
        </bits>
        <bits access="r" name="dci_rep_bund_num" pos="11:10" rst="0">
          <comment>MPDCCH DCI (03),Transport blocks in a bundle</comment>
        </bits>
        <bits access="r" name="di_order_flag" pos="9" rst="0">
          <comment>DCI2DI(direct indication)
0PAGING
1DI
DCI6-1ADCI1-BPDCCH ORDER
0ORDER
1ORDER</comment>
        </bits>
        <bits access="r" name="pmi_sel" pos="8" rst="0">
          <comment>0DCI
1</comment>
        </bits>
        <bits access="r" name="fhop_en" pos="7" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="r" name="dci_format" pos="6:4" rst="0">
          <comment>DCI
0:DCI6-1A
1:DCI6-1B
2:DCI6-0A
3:DCI6-0B
4:DCI3/3A
5:DCI2</comment>
        </bits>
        <bits access="r" name="nb_ind" pos="3:0" rst="0">
          <comment>015</comment>
        </bits>
      </reg>
      <reg name="dci3_info4" protect="r">
        <bits access="r" name="tbsize2" pos="11:0" rst="0">
          <comment>DCI6-1APDSCH1tbsize</comment>
        </bits>
      </reg>
      <reg name="dci3_pwr" protect="r">
        <bits access="r" name="dci_fa" pos="31:24" rst="0">
          <comment>DCIfalse alarm(vit)</comment>
        </bits>
        <bits access="r" name="dci_fa_zero" pos="23:16" rst="0">
          <comment>DCIfalse alarm0</comment>
        </bits>
        <bits access="r" name="dci_pwr" pos="15:0" rst="0">
          <comment>DCI</comment>
        </bits>
      </reg>
      <reg name="mib0_out" protect="r">
        <bits access="r" name="mib0_out_mib0_out" pos="23:0" rst="0">
          <comment>MIB</comment>
        </bits>
      </reg>
      <reg name="mib0_info" protect="r">
        <bits access="r" name="sib1_schedule" pos="14:10" rst="0">
          <comment>SIB1schedule0~31</comment>
        </bits>
        <bits access="r" name="bw_ind" pos="9:7" rst="0">
          <comment>01.4Mhz
13Mhz
25Mhz
310Mhz
415Mhz
520Mhz
6~75</comment>
        </bits>
        <bits access="r" name="sf_ind" pos="6:5" rst="0">
          <comment>MIB
00
11
22
33</comment>
        </bits>
        <bits access="r" name="rep_ind" pos="4:0" rst="0">
          <comment>MIB
bit0
bit11 alllegacyTDD0FDD90
bit221 onlylegacyTDD0FDD90
bit32 alllegacyTDD05FDD
bit42 onlylegacyTDD05FDD</comment>
        </bits>
      </reg>
      <reg name="mib1_out" protect="r">
        <bits access="r" name="mib1_out_mib1_out" pos="23:0" rst="0">
          <comment>MIB</comment>
        </bits>
      </reg>
      <reg name="mib1_info" protect="r">
        <bits access="r" name="sib1_schedule" pos="14:10" rst="0">
          <comment>SIB1schedule0~31</comment>
        </bits>
        <bits access="r" name="bw_ind" pos="9:7" rst="0">
          <comment>01.4Mhz
13Mhz
25Mhz
310Mhz
415Mhz
520Mhz
6~75</comment>
        </bits>
        <bits access="r" name="sf_ind" pos="6:5" rst="0">
          <comment>MIB
00
11
22
33</comment>
        </bits>
        <bits access="r" name="rep_ind" pos="4:0" rst="0">
          <comment>MIB
bit0
bit11 alllegacyTDD0FDD90
bit221 onlylegacyTDD0FDD90
bit32 alllegacyTDD05FDD
bit42 onlylegacyTDD05FDD</comment>
        </bits>
      </reg>
      <reg name="pmi_out" protect="r">
        <bits access="r" name="pmi_out_pmi_out" pos="3:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="shft_fact_out0" protect="r">
        <bits access="r" name="shft5" pos="29:25" rst="0">
          <comment>5</comment>
        </bits>
        <bits access="r" name="shft4" pos="24:20" rst="0">
          <comment>4</comment>
        </bits>
        <bits access="r" name="shft3" pos="19:15" rst="0">
          <comment>3</comment>
        </bits>
        <bits access="r" name="shft2" pos="14:10" rst="0">
          <comment>2</comment>
        </bits>
        <bits access="r" name="shft1" pos="9:5" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="r" name="shft0" pos="4:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="shft_fact_out1" protect="r">
        <bits access="r" name="shft11" pos="29:25" rst="0">
          <comment>11</comment>
        </bits>
        <bits access="r" name="shft10" pos="24:20" rst="0">
          <comment>10</comment>
        </bits>
        <bits access="r" name="shft9" pos="19:15" rst="0">
          <comment>9</comment>
        </bits>
        <bits access="r" name="shft8" pos="14:10" rst="0">
          <comment>8</comment>
        </bits>
        <bits access="r" name="shft7" pos="9:5" rst="0">
          <comment>7</comment>
        </bits>
        <bits access="r" name="shft6" pos="4:0" rst="0">
          <comment>6</comment>
        </bits>
      </reg>
      <reg name="shft_fact_out2" protect="r">
        <bits access="r" name="shft13" pos="9:5" rst="0">
          <comment>13</comment>
        </bits>
        <bits access="r" name="shft12" pos="4:0" rst="0">
          <comment>12</comment>
        </bits>
      </reg>
      <reg name="ldtc_run_ctrl" protect="rw">
        <bits access="rw" name="ldtc_run_ctrl_ldtc_run_ctrl" pos="19:0" rst="78000">
          <comment>LDTC CYCLE
LDTCCYCLE</comment>
        </bits>
      </reg>
      <reg name="reis_conf_nxt" protect="rw">
        <bits access="rw" name="reis_en" pos="9" rst="0">
          <comment>REIS
0
1</comment>
        </bits>
        <bits access="rw" name="reis_dc_en" pos="8" rst="0">
          <comment>REIS
0
1REIS</comment>
        </bits>
        <bits access="rw" name="reis_dc_shift" pos="7:4" rst="0">
          <comment>REIS0</comment>
        </bits>
        <bits access="rw" name="reis_num" pos="3:0" rst="0">
          <comment>REISNUM</comment>
        </bits>
      </reg>
      <reg name="reis_pos0_nxt" protect="rw">
        <bits access="rw" name="reis_shift1" pos="31:28" rst="0">
          <comment>REIS1</comment>
        </bits>
        <bits access="rw" name="reis_re1" pos="26:16" rst="0">
          <comment>REIS1RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_shift0" pos="15:12" rst="0">
          <comment>REIS0</comment>
        </bits>
        <bits access="rw" name="reis_re0" pos="10:0" rst="0">
          <comment>REIS0 RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="reis_pos1_nxt" protect="rw">
        <bits access="rw" name="reis_shift3" pos="31:28" rst="0">
          <comment>REIS3</comment>
        </bits>
        <bits access="rw" name="reis_re3" pos="26:16" rst="0">
          <comment>REIS3RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_shift2" pos="15:12" rst="0">
          <comment>REIS2</comment>
        </bits>
        <bits access="rw" name="reis_re2" pos="10:0" rst="0">
          <comment>REIS2 RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="reis_pos2_nxt" protect="rw">
        <bits access="rw" name="reis_shift5" pos="31:28" rst="0">
          <comment>REIS3</comment>
        </bits>
        <bits access="rw" name="reis_re5" pos="26:16" rst="0">
          <comment>REIS3RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_shift4" pos="15:12" rst="0">
          <comment>REIS2</comment>
        </bits>
        <bits access="rw" name="reis_re4" pos="10:0" rst="0">
          <comment>REIS2 RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="reis_pos3_nxt" protect="rw">
        <bits access="rw" name="reis_shift7" pos="31:28" rst="0">
          <comment>REIS3</comment>
        </bits>
        <bits access="rw" name="reis_re7" pos="26:16" rst="0">
          <comment>REIS3RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_shift6" pos="15:12" rst="0">
          <comment>REIS2</comment>
        </bits>
        <bits access="rw" name="reis_re6" pos="10:0" rst="0">
          <comment>REIS2 RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="rbis_conf" protect="rw">
        <bits access="rw" name="rbis_portsel" pos="31" rst="0">
          <comment>2ABISPORT
0port0
1port1</comment>
        </bits>
        <bits access="rw" name="rbis_en" pos="30" rst="0">
          <comment>RBIS
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_sdden" pos="29" rst="0">
          <comment>RBISSD PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_sdcen" pos="28" rst="0">
          <comment>RBISSD MPDCCH
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_sdben" pos="27" rst="0">
          <comment>RBISSD PBCH
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_posen" pos="26" rst="0">
          <comment>RBIS
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_num" pos="25:23" rst="0">
          <comment>RBIS
01
12
23
34
45</comment>
        </bits>
        <bits access="rw" name="rbis_dipos" pos="22:16" rst="0">
          <comment>RBIS</comment>
        </bits>
        <bits access="rw" name="rbis_factor" pos="15:0" rst="0">
          <comment>RBIS</comment>
        </bits>
      </reg>
      <reg name="rbis_posout" protect="r">
        <bits access="r" name="rbis_posout4" pos="19:16" rst="15">
          <comment>RBIS0~5</comment>
        </bits>
        <bits access="r" name="rbis_posout3" pos="15:12" rst="15">
          <comment>RBIS0~5</comment>
        </bits>
        <bits access="r" name="rbis_posout2" pos="11:8" rst="15">
          <comment>RBIS0~5</comment>
        </bits>
        <bits access="r" name="rbis_posout1" pos="7:4" rst="15">
          <comment>RBIS0~5</comment>
        </bits>
        <bits access="r" name="rbis_posout0" pos="3:0" rst="15">
          <comment>RBIS0~5</comment>
        </bits>
      </reg>
      <reg name="rbis_ave" protect="r">
        <bits access="r" name="rbis_ave_rbis_ave" pos="31:0" rst="0">
          <comment>RBIS</comment>
        </bits>
      </reg>
      <reg name="rbis_max" protect="r">
        <bits access="r" name="rbis_max_rbis_max" pos="24:0" rst="0">
          <comment>RBIS</comment>
        </bits>
      </reg>
      <reg name="abis_enbl_nxt" protect="rw">
        <bits access="rw" name="abis_portsel2" pos="10:9" rst="0">
          <comment>2
02port0port14port0port1port2port3
12port04port0port2port3
22port14port1port2port3</comment>
        </bits>
        <bits access="rw" name="abis_portsel1" pos="8:7" rst="0">
          <comment>1
02port0port14port0port1port2port3
12port04port0port2port3
22port14port1port2port3</comment>
        </bits>
        <bits access="rw" name="abis_portsel0" pos="6:5" rst="0">
          <comment>02port0port14port0port1port2port3
12port04port0port2port3
22port14port1port2port3</comment>
        </bits>
        <bits access="rw" name="mc_en" pos="4" rst="0">
          <comment>MultiCell
0SingalCell
1:MultiCell</comment>
        </bits>
        <bits access="rw" name="abis_sdden" pos="3" rst="0">
          <comment>ABIS SD PDSCH
0
1</comment>
        </bits>
        <bits access="rw" name="abis_sdcen" pos="2" rst="0">
          <comment>ABIS SD MPDCCH
0
1</comment>
        </bits>
        <bits access="rw" name="abis_sdben" pos="1" rst="0">
          <comment>ABIS SD PBCH
0
1</comment>
        </bits>
        <bits access="rw" name="abis_en" pos="0" rst="0">
          <comment>ABIS
0
1</comment>
        </bits>
      </reg>
      <reg name="abis_cfg_nxt" protect="rw">
        <bits access="rw" name="abis_num" pos="29:28" rst="0">
          <comment>000
011
102
0</comment>
        </bits>
        <bits access="rw" name="abis_txnum2" pos="27:26" rst="0">
          <comment>2
001port
012port
104port
1port</comment>
        </bits>
        <bits access="rw" name="abis_txnum1" pos="25:24" rst="0">
          <comment>1
001port
012port
104port
1port</comment>
        </bits>
        <bits access="rw" name="abis_nrb2" pos="23:21" rst="0">
          <comment>2
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
6prb</comment>
        </bits>
        <bits access="rw" name="abis_nrb1" pos="20:18" rst="0">
          <comment>1
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
6prb</comment>
        </bits>
        <bits access="rw" name="abis_cellid2" pos="17:9" rst="0">
          <comment>2 CELL ID</comment>
        </bits>
        <bits access="rw" name="abis_cellid1" pos="8:0" rst="0">
          <comment>1 CELL ID</comment>
        </bits>
      </reg>
      <reg name="abis_dly1_nxt" protect="rw">
        <bits access="rw" name="abis_dly1" pos="18:0" rst="0">
          <comment>1TS</comment>
        </bits>
      </reg>
      <reg name="abis_dly2_nxt" protect="rw">
        <bits access="rw" name="abis_dly2" pos="18:0" rst="0">
          <comment>2TS</comment>
        </bits>
      </reg>
      <reg name="abis_shft" protect="r">
        <bits access="r" name="abis_shft3" pos="11:8" rst="0">
          <comment>ABIS31+2</comment>
        </bits>
        <bits access="r" name="abis_shft2" pos="7:4" rst="0">
          <comment>ABIS22</comment>
        </bits>
        <bits access="r" name="abis_shft1" pos="3:0" rst="0">
          <comment>ABIS11</comment>
        </bits>
      </reg>
      <reg name="pbml_cfg_nxt" protect="rw">
        <bits access="rw" name="pbml_en" pos="20" rst="0">
          <comment>PBML
0
1</comment>
        </bits>
        <bits access="rw" name="pbml_cal_len" pos="19:14" rst="0">
          <comment>LLR</comment>
        </bits>
        <bits access="rw" name="pbml_pos_sta" pos="13:8" rst="0">
          <comment>LLR</comment>
        </bits>
        <bits access="rw" name="pbml_alpha" pos="7:0" rst="0">
          <comment>LLR
0~255</comment>
        </bits>
      </reg>
      <reg name="vit_faconf" protect="rw">
        <bits access="rw" name="fa_en" pos="8" rst="0">
          <comment>PDCCHfalse alarm</comment>
        </bits>
        <bits access="rw" name="fa_th" pos="7:0" rst="0">
          <comment>PDCCHfalse alarm(U8Q7)</comment>
        </bits>
      </reg>
      <reg name="sw_cin_nxt" protect="rw">
        <bits access="rw" name="sw_in" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="sw_cout_nxt" protect="r">
        <bits access="r" name="sw_out" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="sw_din_nxt" protect="rw">
        <bits access="rw" name="sw_in" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="sw_dout_nxt" protect="r">
        <bits access="r" name="sw_out" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="ldtc_intflag" protect="rw">
        <bits access="rc" name="pmi_flag" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PMI
0
1</comment>
        </bits>
        <bits access="rc" name="b_flag" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PBCH
0
1</comment>
        </bits>
        <bits access="rc" name="d_flag" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          PDSCH
0
1</comment>
        </bits>
        <bits access="rc" name="c_flag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          MPDCCH
0
1</comment>
        </bits>
      </reg>
      <reg name="ldtc_cout" protect="r">
        <bits access="r" name="dci_det_full" pos="12" rst="0">
          <comment>DCI
0
1</comment>
        </bits>
        <bits access="r" name="dci_rlastval" pos="11:8" rst="0">
          <comment>DCI Ri
0DCI
1DCIRi</comment>
        </bits>
        <bits access="r" name="dci_reconfmval" pos="7:4" rst="0">
          <comment>DCI2
0DCI
1DCI2</comment>
        </bits>
        <bits access="r" name="dci_nowvalid" pos="3:0" rst="0">
          <comment>DCI
0DCI
1DCI</comment>
        </bits>
      </reg>
      <reg name="ldtc_dmout" protect="r">
        <bits access="r" name="mib_valid" pos="3:2" rst="0">
          <comment>MIB
0MIB
1MIB</comment>
        </bits>
        <bits access="r" name="pdsch_zero_flag" pos="1" rst="0">
          <comment>PDSCH CRC
0
1</comment>
        </bits>
        <bits access="r" name="pdsch_crc_flag" pos="0" rst="1">
          <comment>PDSCH CRC
0CRC
1CRC</comment>
        </bits>
      </reg>
      <reg name="ldtc_state_l" protect="r">
        <bits access="r" name="ldtc_state_l_ldtc_state_l" pos="31:0" rst="1">
          <comment>LDTC</comment>
        </bits>
      </reg>
      <reg name="ldtc_state_h" protect="r">
        <bits access="r" name="ldtc_state_h_ldtc_state_h" pos="9:0" rst="0">
          <comment>LDTC</comment>
        </bits>
      </reg>
      <reg name="mc_dly1_nxt" protect="rw">
        <bits access="rw" name="mc_dly1" pos="18:0" rst="0">
          <comment>1TS</comment>
        </bits>
      </reg>
      <reg name="mc_dly2_nxt" protect="rw">
        <bits access="rw" name="mc_dly2" pos="18:0" rst="0">
          <comment>2TS</comment>
        </bits>
      </reg>
      <reg name="mc_dlyth_nxt" protect="rw">
        <bits access="rw" name="mc_dlyth" pos="9:0" rst="0">
          <comment>TS</comment>
        </bits>
      </reg>
      <hole size="28704"/>
      <reg name="fftbuf0" protect="rw">
        <bits access="rw" name="fftbuf0_fftbuf0" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="fftbuf1" protect="rw">
        <bits access="rw" name="fftbuf1_fftbuf1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="rsram0" protect="rw">
        <bits access="rw" name="rsram0_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="rsram0_0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="rsram1" protect="rw">
        <bits access="rw" name="rsram1_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="rsram1_0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="rsram2" protect="rw">
        <bits access="rw" name="rsram2_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="rsram2_0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="rsram3" protect="rw">
        <bits access="rw" name="rsram3_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="rsram3_0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="rsram4" protect="rw">
        <bits access="rw" name="rsram4_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="rsram4_0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="qfram0" protect="rw">
        <bits access="rw" name="qfram0_1" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="qfram0_0" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="qfram1" protect="rw">
        <bits access="rw" name="qfram1_1" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="qfram1_0" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="qtram0" protect="rw">
        <bits access="rw" name="qtram0_qtram0" pos="31:19" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="qtram1" protect="rw">
        <bits access="rw" name="qtram0" pos="31:19" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="lspreram" protect="rw">
        <bits access="rw" name="lspreram1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="lspreram0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="lscurram" protect="rw">
        <bits access="rw" name="lscurram1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="lscurram0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="fhram" protect="rw">
        <bits access="rw" name="fhram1" pos="31:22" rst="0">
      </bits>
        <bits access="rw" name="fhram0" pos="15:6" rst="0">
      </bits>
      </reg>
      <hole size="98272"/>
      <reg name="hqinram0" protect="rw">
        <bits access="r" name="hqinram0_1_0" pos="31:29" rst="0">
      </bits>
        <bits access="rw" name="hqinram0_1" pos="28:19" rst="0">
      </bits>
        <bits access="r" name="hqinram0_0_0" pos="15:13" rst="0">
      </bits>
        <bits access="rw" name="hqinram0_0" pos="12:3" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="hqinram1" protect="rw">
        <bits access="rw" name="hqinram1_1" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="hqinram1_0" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="hqinram2" protect="rw">
        <bits access="rw" name="hqinram2_1" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="hqinram2_0" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="16352"/>
      <reg name="tboutram" protect="rw">
        <bits access="rw" name="tboutram_tboutram" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="tbinram" protect="rw">
        <bits access="rw" name="tbinram_tbinram" pos="29:0" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="hqbuf0" protect="rw">
        <bits access="rw" name="hqbuf0_hqbuf0" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="hqbuf1" protect="rw">
        <bits access="rw" name="hqbuf1_1" pos="31:22" rst="0">
      </bits>
        <bits access="rw" name="hqbuf1_0" pos="15:6" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="hqbuf2" protect="rw">
        <bits access="rw" name="hqbuf2_hqbuf2" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="hqinram3" protect="rw">
        <bits access="rw" name="hqinram3_hqinram3" pos="19:0" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="qfram2" protect="rw">
        <bits access="rw" name="qfram2_1" pos="31:19" rst="0">
      </bits>
        <bits access="rw" name="qfram2_0" pos="15:3" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="qtram2" protect="rw">
        <bits access="rw" name="qtram2_qtram2" pos="31:19" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_dlfft.xml">
    <module category="LTE_SYS" name="CP_LTE_DLFFT">
      <reg name="dlfft_frame_config_next" protect="rw">
        <bits access="rw" name="crs_pow_ofdm0_next" pos="19" rst="1">
          <comment>CATMCELL RSOFDM0
0OFDM0
1OFDM0</comment>
        </bits>
        <bits access="rw" name="fft_norm_sel_next" pos="18" rst="0">
          <comment>FFT
0
1</comment>
        </bits>
        <bits access="rw" name="fft_norm_en_next" pos="17" rst="0">
          <comment>0FFTFFT
1FFTFFT</comment>
        </bits>
        <bits access="rw" name="dlfft_only_en_next" pos="16" rst="0">
          <comment>0DLFFTLDTC1LDTC
1DLFFTLDTC1LDTC</comment>
        </bits>
        <bits access="rw" name="fft_dma_inten_next" pos="15" rst="1">
          <comment>1DLFFTTXRXOFDM
0DLFFT</comment>
        </bits>
        <bits access="rw" name="master_card_next" pos="14" rst="0">
          <comment>0:
1:</comment>
        </bits>
        <bits access="rw" name="sys_frame_num_next" pos="13:4" rst="0">
          <comment>0~1023</comment>
        </bits>
        <bits access="rw" name="sub_frame_num_next" pos="3:0" rst="0">
          <comment>0~9</comment>
        </bits>
      </reg>
      <reg name="cat1_rs_ctrl_next" protect="rw">
        <bits access="rw" name="crs_pow_index_next" pos="21:19" rst="0">
          <comment>CELL RS&amp;AGC
000
001
010
011
100</comment>
        </bits>
        <bits access="rw" name="cat1_crs_pow_ofdm0_next" pos="18" rst="1">
          <comment>CAT1CELL RSOFDM0
0OFDM0
1OFDM0</comment>
        </bits>
        <bits access="rw" name="mbms_mode_sel_next" pos="17:16" rst="0">
          <comment>MBMS
2b00MBMSCELLRS
2b01MBMS1CELLRS
2b10MBMS2CELLRS
2b1100</comment>
        </bits>
        <bits access="rw" name="mbms_en_next" pos="15" rst="0">
          <comment>0MBMS
1MBMS</comment>
        </bits>
        <bits access="rw" name="cellid_next" pos="14:6" rst="0">
          <comment>CELLID</comment>
        </bits>
        <bits access="rw" name="cp_sel_next" pos="5" rst="0">
          <comment>CP
0NORM CP
1EX CP</comment>
        </bits>
        <bits access="rw" name="cellport_sel_next" pos="4:3" rst="0">
          <comment>CELLRS PORT
2b00port0
2b01port0/1
2b10port0/1/2/3
2b11CELLPORT_SEL2b112b00prot0</comment>
        </bits>
        <bits access="rw" name="ueport_sel_next" pos="2" rst="0">
          <comment>UERS PORT
0port5
1port7/8</comment>
        </bits>
        <bits access="rw" name="cellrs_en_next" pos="1" rst="0">
          <comment>0CELLRS
1CELLRS</comment>
        </bits>
        <bits access="rw" name="uers_en_next" pos="0" rst="0">
          <comment>0UERS
1UERS</comment>
        </bits>
      </reg>
      <reg name="cat1_csi_para_next" protect="rw">
        <bits access="rw" name="csirs_bitmap_next" pos="19:8" rst="0">
          <comment>RSCSIRSCSIRS BITMAP</comment>
        </bits>
        <bits access="rw" name="csirs_ofdm1_next" pos="7:4" rst="0">
          <comment>CSIRSCSIRSOFDM</comment>
        </bits>
        <bits access="rw" name="csirs_ofdm0_next" pos="3:0" rst="0">
          <comment>CSIRSCSIRSOFDM</comment>
        </bits>
      </reg>
      <reg name="cat1_agc_next" protect="rw">
        <bits access="rw" name="agc1_next" pos="19:10" rst="0">
          <comment>MBMSCELLRSOFDMAGC</comment>
        </bits>
        <bits access="rw" name="agc0_next" pos="9:0" rst="0">
          <comment>MBMSAGCMBMSCELLRSOFDMAGC</comment>
        </bits>
      </reg>
      <reg name="cat1_dlfft_ctrl_next" protect="rw">
        <bits access="rw" name="pbch_en_next" pos="1" rst="0">
          <comment>0PBCH
1PBCH</comment>
        </bits>
        <bits access="rw" name="csirs_en_next" pos="0" rst="0">
          <comment>0CSIRS
1CSIRS</comment>
        </bits>
      </reg>
      <reg name="cat1_sys_config_next" protect="rw">
        <bits access="rw" name="prb_index_next" pos="10:8" rst="0">
          <comment>PRB
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
1116prb</comment>
        </bits>
        <bits access="rw" name="up_down_config" pos="7:5" rst="0">
          <comment>0~6</comment>
        </bits>
        <bits access="rw" name="mode_sel_next" pos="4" rst="0">
          <comment>0TDD MODE
1FDD MODE</comment>
        </bits>
        <bits access="rw" name="s_frame_config" pos="3:0" rst="0">
          <comment>0~9</comment>
        </bits>
      </reg>
      <reg name="cat1_fft_gate_next" protect="rw">
        <bits access="rw" name="fft_gate_next" pos="12:0" rst="0">
          <comment>FFT0~4096</comment>
        </bits>
      </reg>
      <reg name="catm_nb_sys_config_next" protect="rw">
        <bits access="rw" name="prb_index_next" pos="11:9" rst="0">
          <comment>NBIOTNBPRB0~5</comment>
        </bits>
        <bits access="rw" name="cp_sel_next" pos="8" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="rw" name="up_down_config_next" pos="7:5" rst="0">
          <comment>0~6</comment>
        </bits>
        <bits access="rw" name="mode_sel_next" pos="4" rst="0">
          <comment>0TDD MODE
1FDD MODE</comment>
        </bits>
        <bits access="rw" name="s_frame_config_next" pos="3:0" rst="0">
          <comment>0~9</comment>
        </bits>
      </reg>
      <reg name="catm_nb_rs_config_next" protect="rw">
        <bits access="rw" name="crs_pow_index_next" pos="15:13" rst="0">
          <comment>CELL RS&amp;AGC
000
001
010
011
100</comment>
        </bits>
        <bits access="rw" name="crs_nrs_sel_next" pos="12" rst="0">
          <comment>0NBNRS
1NBCRS</comment>
        </bits>
        <bits access="rw" name="id_value_next" pos="11:3" rst="0">
          <comment>CELLRSNRSID</comment>
        </bits>
        <bits access="rw" name="rsport_sel_next" pos="2:1" rst="0">
          <comment>CELLRSNRS PORT
2b00port0
2b01port0/1
2b10port0/1/2/3
2b112b10</comment>
        </bits>
      </reg>
      <reg name="catm_nb_nbw_next" protect="rw">
        <bits access="rw" name="nbw_cover_zero_sel_next" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="catm_agc_next" protect="rw">
        <bits access="rw" name="catm_agc_next_catm_agc_next" pos="9:0" rst="0">
          <comment>CATMAGC</comment>
        </bits>
      </reg>
      <reg name="abis_config_next" protect="rw">
        <bits access="rw" name="frame_intra_sel_next" pos="31" rst="0">
          <comment>0LDTC1LLR0
1LDTC1LLR</comment>
        </bits>
        <bits access="rw" name="ctcg_sel_next" pos="30" rst="0">
          <comment>CTCG
0OFDM4(OFDM4)CRS
1OFDM8(OFDM8)CRS</comment>
        </bits>
        <bits access="rw" name="num_neibour_next" pos="29:28" rst="0">
          <comment>000
011
102
0</comment>
        </bits>
        <bits access="rw" name="txnum_neibour_next2" pos="27:26" rst="0">
          <comment>2
001port
012port
104port
1port</comment>
        </bits>
        <bits access="rw" name="txnum_neibour_next1" pos="25:24" rst="0">
          <comment>1
001port
012port
104port
1port</comment>
        </bits>
        <bits access="rw" name="nrb_neibour_next2" pos="23:21" rst="0">
          <comment>2
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
6prb</comment>
        </bits>
        <bits access="rw" name="nrb_neibour_next1" pos="20:18" rst="0">
          <comment>1
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
6prb</comment>
        </bits>
        <bits access="rw" name="cellid_neibour_next2" pos="17:9" rst="0">
          <comment>2 CELL ID</comment>
        </bits>
        <bits access="rw" name="cellid_neibour_next1" pos="8:0" rst="0">
          <comment>1 CELL ID</comment>
        </bits>
      </reg>
      <reg name="delay_next1" protect="rw">
        <bits access="rw" name="delay_next1_delay_next1" pos="18:0" rst="0">
          <comment>1TS</comment>
        </bits>
      </reg>
      <reg name="delay_next2" protect="rw">
        <bits access="rw" name="delay_next2_delay_next2" pos="18:0" rst="0">
          <comment>2TS</comment>
        </bits>
      </reg>
      <reg name="pb_next" protect="rw">
        <bits access="rw" name="abis_llr_shift_modify_next" pos="12:8" rst="0">
      </bits>
        <bits access="rw" name="abis_start_ofdm_next" pos="7:4" rst="0">
          <comment>ABISOFDM0~13</comment>
        </bits>
        <bits access="rw" name="pb_next_pb_next" pos="1:0" rst="0">
          <comment>CRSCRS</comment>
        </bits>
      </reg>
      <reg name="noise_delta_next" protect="rw">
        <bits access="rw" name="noise_delta_next_noise_delta_next" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="noise_agc_next" protect="rw">
        <bits access="rw" name="noise_agc_next_noise_agc_next" pos="9:0" rst="0">
          <comment>AGC</comment>
        </bits>
      </reg>
      <reg name="dlfft_mode_next" protect="rw">
        <bits access="rw" name="dlfft_info_sel_next" pos="14" rst="0">
          <comment>0DLFFT_INFO_OUT1
1DLFFT_INFO_OUT2</comment>
        </bits>
        <bits access="rw" name="dlfft_info_next" pos="13:4" rst="0">
          <comment>DLFFT INFO</comment>
        </bits>
        <bits access="rw" name="crs_pow_clr_next" pos="3" rst="0">
          <comment>0CRS_POW_MAXPOWAGC
1CRS_POW_MAXPOWAGC</comment>
        </bits>
        <bits access="rw" name="soft_irt_en_next" pos="2" rst="0">
          <comment>0SOFT_IRT
1SOFT_IRT</comment>
        </bits>
        <bits access="rw" name="dlfft_mode_sel_next" pos="1:0" rst="0">
          <comment>00CAT1
01CATM
10NB-IOT
11CAT1</comment>
        </bits>
      </reg>
      <reg name="fft_lnum_next" protect="rw">
        <bits access="rw" name="fft_lnum11_next" pos="21:20" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum10_next" pos="19:18" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum9_next" pos="17:16" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~18bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum8_next" pos="15:14" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~19bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum7_next" pos="13:12" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~20bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum6_next" pos="11:10" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~21bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum5_next" pos="9:8" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~22bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum4_next" pos="7:6" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~23bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum3_next" pos="5:4" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~24bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum2_next" pos="3:2" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~25bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum1_next" pos="1:0" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~26bit</comment>
        </bits>
      </reg>
      <reg name="dlfft_frame_config_curr" protect="r">
        <bits access="r" name="crs_pow_ofdm0_curr" pos="19" rst="1">
          <comment>ATMCELL RSOFDM0
0OFDM0
1OFDM0</comment>
        </bits>
        <bits access="r" name="fft_norm_sel_curr" pos="18" rst="0">
          <comment>FFT
0
1</comment>
        </bits>
        <bits access="r" name="fft_norm_en_curr" pos="17" rst="0">
          <comment>0FFTFFT
1FFTFFT</comment>
        </bits>
        <bits access="r" name="dlfft_only_en_curr" pos="16" rst="0">
          <comment>0DLFFTLDTC1LDTC
1DLFFTLDTC1LDTC</comment>
        </bits>
        <bits access="r" name="fft_dma_inten_curr" pos="15" rst="1">
          <comment>1DLFFTTXRXOFDM
0DLFFT</comment>
        </bits>
        <bits access="r" name="master_card_curr" pos="14" rst="0">
          <comment>0:
1:</comment>
        </bits>
        <bits access="r" name="sys_frame_num_curr" pos="13:4" rst="0">
          <comment>0~1023</comment>
        </bits>
        <bits access="r" name="sub_frame_num_curr" pos="3:0" rst="0">
          <comment>0~9</comment>
        </bits>
      </reg>
      <reg name="cat1_rs_ctrl_curr" protect="r">
        <bits access="r" name="crs_pow_index_curr" pos="21:19" rst="0">
          <comment>CELL RS&amp;AGC
000
001
010
011
100</comment>
        </bits>
        <bits access="r" name="crs_pow_ofdm0_curr" pos="18" rst="1">
          <comment>CELL RSOFDM0
0OFDM0
1OFDM0</comment>
        </bits>
        <bits access="r" name="mbms_mode_sel_curr" pos="17:16" rst="0">
          <comment>MBMS
2b00MBMSCELLRS
2b01MBMS1CELLRS
2b10MBMS2CELLRS
2b1100</comment>
        </bits>
        <bits access="r" name="mbms_en_curr" pos="15" rst="0">
          <comment>0MBMS
1MBMS</comment>
        </bits>
        <bits access="r" name="cellid_curr" pos="14:6" rst="0">
          <comment>CELLID</comment>
        </bits>
        <bits access="r" name="cp_sel_curr" pos="5" rst="0">
          <comment>CP
0NORM CP
1EX CP</comment>
        </bits>
        <bits access="r" name="cellport_sel_curr" pos="4:3" rst="0">
          <comment>CELLRS PORT
2b00port0
2b01port0/1
2b10port0/1/2/3
2b11CELLPORT_SEL2b112b00prot0</comment>
        </bits>
        <bits access="r" name="ueport_sel_curr" pos="2" rst="0">
          <comment>UERS PORT
0port5
1port7/8</comment>
        </bits>
        <bits access="r" name="cellrs_en_curr" pos="1" rst="0">
          <comment>0CELLRS
1CELLRS</comment>
        </bits>
        <bits access="r" name="uers_en_curr" pos="0" rst="0">
          <comment>0UERS
1UERS</comment>
        </bits>
      </reg>
      <reg name="cat1_csi_para_curr" protect="r">
        <bits access="r" name="csirs_bitmap_curr" pos="19:8" rst="0">
          <comment>RSCSIRSCSIRS BITMAP</comment>
        </bits>
        <bits access="r" name="csirs_ofdm1_curr" pos="7:4" rst="0">
          <comment>CSIRSCSIRSOFDM</comment>
        </bits>
        <bits access="r" name="csirs_ofdm0_curr" pos="3:0" rst="0">
          <comment>CSIRSCSIRSOFDM</comment>
        </bits>
      </reg>
      <reg name="cat1_agc_curr" protect="r">
        <bits access="r" name="agc1_curr" pos="19:10" rst="0">
          <comment>MBMSCELLRSOFDMAGC</comment>
        </bits>
        <bits access="r" name="agc0_curr" pos="9:0" rst="0">
          <comment>MBMSAGCMBMSCELLRSOFDMAGC</comment>
        </bits>
      </reg>
      <reg name="cat1_dlfft_ctrl_curr" protect="r">
        <bits access="r" name="pbch_en_curr" pos="1" rst="0">
          <comment>0PBCH
1PBCH</comment>
        </bits>
        <bits access="r" name="csirs_en_curr" pos="0" rst="0">
          <comment>0CSIRS
1CSIRS</comment>
        </bits>
      </reg>
      <reg name="cat1_sys_config_curr" protect="r">
        <bits access="r" name="prb_index_curr" pos="10:8" rst="0">
          <comment>PRB
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
1116prb</comment>
        </bits>
        <bits access="r" name="up_down_config" pos="7:5" rst="0">
          <comment>0~6</comment>
        </bits>
        <bits access="r" name="mode_sel_curr" pos="4" rst="0">
          <comment>0TDD MODE
1FDD MODE</comment>
        </bits>
        <bits access="r" name="s_frame_config" pos="3:0" rst="0">
          <comment>0~9</comment>
        </bits>
      </reg>
      <reg name="cat1_fft_gate_curr" protect="r">
        <bits access="r" name="fft_gate_curr" pos="12:0" rst="0">
          <comment>FFT0~4096</comment>
        </bits>
      </reg>
      <reg name="catm_nb_sys_config_curr" protect="r">
        <bits access="r" name="prb_index_curr" pos="11:9" rst="0">
          <comment>NBIOTNBPRB0~5</comment>
        </bits>
        <bits access="r" name="cp_sel_curr" pos="8" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="r" name="up_down_config_curr" pos="7:5" rst="0">
          <comment>0~6</comment>
        </bits>
        <bits access="r" name="mode_sel_curr" pos="4" rst="0">
          <comment>0TDD MODE
1FDD MODE</comment>
        </bits>
        <bits access="r" name="s_frame_config_curr" pos="3:0" rst="0">
          <comment>0~9</comment>
        </bits>
      </reg>
      <reg name="catm_nb_rs_config_curr" protect="r">
        <bits access="r" name="crs_pow_index_curr" pos="15:13" rst="0">
          <comment>CELL RS&amp;AGC
000
001
010
011
100</comment>
        </bits>
        <bits access="r" name="crs_nrs_sel_curr" pos="12" rst="0">
          <comment>0NBNRS
1NBCRS</comment>
        </bits>
        <bits access="r" name="id_value_curr" pos="11:3" rst="0">
          <comment>CELLRSNRSID</comment>
        </bits>
        <bits access="r" name="rsport_sel_curr" pos="2:1" rst="0">
          <comment>CELLRSNRS PORT
2b00port0
2b01port0/1
2b10port0/1/2/3
2b112b10</comment>
        </bits>
      </reg>
      <reg name="catm_nb_nbw_curr" protect="r">
        <bits access="r" name="nbw_cover_zero_sel_curr" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="catm_agc_curr" protect="r">
        <bits access="r" name="catm_agc_curr_catm_agc_curr" pos="9:0" rst="0">
          <comment>CATMAGC</comment>
        </bits>
      </reg>
      <reg name="abis_config_curr" protect="r">
        <bits access="r" name="frame_intra_sel_curr" pos="31" rst="0">
          <comment>0LDTC1LLR0
1LDTC1LLR</comment>
        </bits>
        <bits access="r" name="ctcg_sel_curr" pos="30" rst="0">
          <comment>CTCG
0OFDM4(OFDM4)CRS
1OFDM8(OFDM8)CRS</comment>
        </bits>
        <bits access="r" name="num_neibour_curr" pos="29:28" rst="0">
          <comment>000
011
102
0</comment>
        </bits>
        <bits access="r" name="txnum_neibour_curr2" pos="27:26" rst="0">
          <comment>2
001port
012port
104port
1port</comment>
        </bits>
        <bits access="r" name="txnum_neibour_curr1" pos="25:24" rst="0">
          <comment>1
001port
012port
104port
1port</comment>
        </bits>
        <bits access="r" name="nrb_neibour_curr2" pos="23:21" rst="0">
          <comment>2
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
6prb</comment>
        </bits>
        <bits access="r" name="nrb_neibour_curr1" pos="20:18" rst="0">
          <comment>1
0006prb
00115prb
01025prb
01150prb
10075prb
101100prb
6prb</comment>
        </bits>
        <bits access="r" name="cellid_neibour_curr2" pos="17:9" rst="0">
          <comment>2 CELL ID</comment>
        </bits>
        <bits access="r" name="cellid_neibour_curr1" pos="8:0" rst="0">
          <comment>1 CELL ID</comment>
        </bits>
      </reg>
      <reg name="delay_curr1" protect="r">
        <bits access="r" name="delay_curr1_delay_curr1" pos="18:0" rst="0">
          <comment>1TS</comment>
        </bits>
      </reg>
      <reg name="delay_curr2" protect="r">
        <bits access="r" name="delay_curr2_delay_curr2" pos="18:0" rst="0">
          <comment>2TS</comment>
        </bits>
      </reg>
      <reg name="pb_curr" protect="r">
        <bits access="r" name="abis_llr_shift_modify_curr" pos="12:8" rst="0">
          <comment>ABIS LLR-8~8</comment>
        </bits>
        <bits access="r" name="abis_start_ofdm_curr" pos="7:4" rst="0">
          <comment>ABISOFDM0~13</comment>
        </bits>
        <bits access="r" name="pb_curr_pb_curr" pos="1:0" rst="0">
          <comment>CRSCRS</comment>
        </bits>
      </reg>
      <reg name="noise_delta_curr" protect="r">
        <bits access="r" name="noise_delta_curr_noise_delta_curr" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="noise_agc_curr" protect="r">
        <bits access="r" name="noise_agc_curr_noise_agc_curr" pos="9:0" rst="0">
          <comment>AGC</comment>
        </bits>
      </reg>
      <reg name="dlfft_mode_curr" protect="r">
        <bits access="r" name="dlfft_info_sel_curr" pos="14" rst="0">
          <comment>0DLFFT_INFO_OUT1
1DLFFT_INFO_OUT2</comment>
        </bits>
        <bits access="r" name="dlfft_info_curr" pos="13:4" rst="0">
          <comment>DLFFT INFO</comment>
        </bits>
        <bits access="r" name="crs_pow_clr_curr" pos="3" rst="0">
          <comment>0CRS_POW_MAXPOWAGC
1CRS_POW_MAXPOWAGC</comment>
        </bits>
        <bits access="r" name="soft_irt_en_curr" pos="2" rst="0">
          <comment>0SOFT_IRT
1SOFT_IRT</comment>
        </bits>
        <bits access="r" name="dlfft_mode_sel_curr" pos="1:0" rst="0">
          <comment>00CAT1
01CATM
10NB-IOT
11CAT1</comment>
        </bits>
      </reg>
      <reg name="fft_lnum_curr" protect="r">
        <bits access="r" name="fft_lnum11_curr" pos="21:20" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="r" name="fft_lnum10_curr" pos="19:18" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="r" name="fft_lnum9_curr" pos="17:16" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~18bit</comment>
        </bits>
        <bits access="r" name="fft_lnum8_curr" pos="15:14" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~19bit</comment>
        </bits>
        <bits access="r" name="fft_lnum7_curr" pos="13:12" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~20bit</comment>
        </bits>
        <bits access="r" name="fft_lnum6_curr" pos="11:10" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~21bit</comment>
        </bits>
        <bits access="r" name="fft_lnum5_curr" pos="9:8" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~22bit</comment>
        </bits>
        <bits access="r" name="fft_lnum4_curr" pos="7:6" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~23bit</comment>
        </bits>
        <bits access="r" name="fft_lnum3_curr" pos="5:4" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~24bit</comment>
        </bits>
        <bits access="r" name="fft_lnum2_curr" pos="3:2" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~25bit</comment>
        </bits>
        <bits access="r" name="fft_lnum1_curr" pos="1:0" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~26bit</comment>
        </bits>
      </reg>
      <reg name="dlfft_inten" protect="rw">
        <bits access="rw" name="rf_nodata_inten" pos="8" rst="0">
          <comment>1RF
0RF</comment>
        </bits>
        <bits access="rw" name="rf_abnormal_up_inten" pos="7" rst="0">
          <comment>1RF
0RF</comment>
        </bits>
        <bits access="rw" name="rf_abnormal_down_inten" pos="6" rst="0">
          <comment>1RF
0RF</comment>
        </bits>
        <bits access="rw" name="rf_short_inten" pos="5" rst="0">
          <comment>1RF
0RF</comment>
        </bits>
        <bits access="rw" name="rf_over_inten" pos="4" rst="0">
          <comment>1RF
0RF</comment>
        </bits>
        <bits access="rw" name="axi_dma_inten" pos="3" rst="0">
          <comment>1AXIDMA
AXIDMADLFFT
OFDM
0AXIDMA</comment>
        </bits>
        <bits access="rw" name="fft_err_inten" pos="2" rst="0">
          <comment>1DLFFTTXRX or LDTC or LDTC1ERROR
0DLFFTTXRX or LDTCor LDTC1ERROR</comment>
        </bits>
        <bits access="rw" name="fft_core_inten" pos="1" rst="0">
          <comment>1DLFFTOFDM
0DLFFT</comment>
        </bits>
        <bits access="rw" name="fft_dma_inten" pos="0" rst="0">
          <comment>1DLFFTTXRXOFDM
0DLFFT</comment>
        </bits>
      </reg>
      <reg name="catm_nb_fft_gate" protect="rw">
        <bits access="rw" name="fft_gate" pos="12:0" rst="0">
          <comment>FFT0~4096</comment>
        </bits>
      </reg>
      <reg name="dlfft_start" protect="rw">
        <bits access="rw" name="catm_nb_dlfft_start" pos="1" rst="0">
          <comment>0: CATM/NB
1: CATM/NB</comment>
        </bits>
        <bits access="rw" name="cat1_dlfft_start" pos="0" rst="0">
          <comment>0: CAT1
1: CAT1</comment>
        </bits>
      </reg>
      <reg name="dlfft_intf" protect="rw">
        <bits access="rc" name="measpwr_debug_errf" pos="15" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1MEASPWR
0 MEASPWR</comment>
        </bits>
        <bits access="rc" name="rf_nodata_errf" pos="14" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1RF
0RF</comment>
        </bits>
        <bits access="rc" name="sd_rd_errf" pos="13" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1SDDLFFT
0SDDLFFT</comment>
        </bits>
        <bits access="rc" name="coeff2ldtc_errf" pos="12" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1COEFFLDTC
0COEFFLDTC</comment>
        </bits>
        <bits access="rc" name="coeff2ldtc1_errf" pos="11" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1COEFFLDTC1
0COEFFLDTC1</comment>
        </bits>
        <bits access="rc" name="rf_abnormal_up_errf" pos="10" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1RF
0RF</comment>
        </bits>
        <bits access="rc" name="rf_abnormal_down_errf" pos="9" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1RF
0RF</comment>
        </bits>
        <bits access="rc" name="rf_short_errf" pos="8" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1RF
0RF</comment>
        </bits>
        <bits access="rc" name="rf_over_errf" pos="7" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1RF
0RF</comment>
        </bits>
        <bits access="rc" name="axi_dma_intf" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1AXIDMAAXIDMADLFFTOFDM
0AXIDMA</comment>
        </bits>
        <bits access="rc" name="csi_wr_errf" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1CSI
0CSI</comment>
        </bits>
        <bits access="rc" name="mmse_wr_errf" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1MMSE
0MMSE</comment>
        </bits>
        <bits access="rc" name="ldtc_wr_errf" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1LDTC
0LDTC</comment>
        </bits>
        <bits access="rc" name="txrx_rd_errf" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1TXRX
0TXRX</comment>
        </bits>
        <bits access="rc" name="fft_core_intf" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1DLFFTOFDM
0DLFFT</comment>
        </bits>
        <bits access="rc" name="fft_dma_intf" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1DLFFTTXRXOFDM
0DLFFT</comment>
        </bits>
      </reg>
      <reg name="ofdm_count" protect="r">
        <bits access="r" name="ofdm_count_ofdm_count" pos="3:0" rst="0">
          <comment>OFDM0~13</comment>
        </bits>
      </reg>
      <reg name="master_card" protect="r">
        <bits access="r" name="dlfft_info_out2" pos="20:11" rst="0">
          <comment>DLFFT INFO 2</comment>
        </bits>
        <bits access="r" name="dlfft_info_out1" pos="10:1" rst="0">
          <comment>DLFFT INFO 1</comment>
        </bits>
        <bits access="r" name="master_card_out" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="llr_out1" protect="r">
        <bits access="r" name="llr_out1_llr_out1" pos="3:0" rst="15">
          <comment>ABIS11</comment>
        </bits>
      </reg>
      <reg name="llr_out2" protect="r">
        <bits access="r" name="llr_out2_llr_out2" pos="3:0" rst="15">
          <comment>ABIS22</comment>
        </bits>
      </reg>
      <reg name="llr_out3" protect="r">
        <bits access="r" name="llr_out3_llr_out3" pos="3:0" rst="15">
          <comment>ABIS31+2</comment>
        </bits>
      </reg>
      <reg name="crs_pow_max1" protect="r">
        <bits access="r" name="crs_pow_max1_crs_pow_max1" pos="31:0" rst="0">
          <comment>CELLRS</comment>
        </bits>
      </reg>
      <reg name="crs_pow_agc1" protect="r">
        <bits access="r" name="crs_pow_agc1_crs_pow_agc1" pos="9:0" rst="0">
          <comment>CELLRSAGC</comment>
        </bits>
      </reg>
      <reg name="crs_pow_max2" protect="r">
        <bits access="r" name="crs_pow_max2_crs_pow_max2" pos="31:0" rst="0">
          <comment>CELLRS</comment>
        </bits>
      </reg>
      <reg name="crs_pow_agc2" protect="r">
        <bits access="r" name="crs_pow_agc2_crs_pow_agc2" pos="9:0" rst="0">
          <comment>CELLRSAGC</comment>
        </bits>
      </reg>
      <reg name="crs_pow_max3" protect="r">
        <bits access="r" name="crs_pow_max3_crs_pow_max3" pos="31:0" rst="0">
          <comment>CELLRS</comment>
        </bits>
      </reg>
      <reg name="crs_pow_agc3" protect="r">
        <bits access="r" name="crs_pow_agc3_crs_pow_agc3" pos="9:0" rst="0">
          <comment>CELLRSAGC</comment>
        </bits>
      </reg>
      <reg name="crs_pow_max4" protect="r">
        <bits access="r" name="crs_pow_max4_crs_pow_max4" pos="31:0" rst="0">
          <comment>CELLRS</comment>
        </bits>
      </reg>
      <reg name="crs_pow_agc4" protect="r">
        <bits access="r" name="crs_pow_agc4_crs_pow_agc4" pos="9:0" rst="0">
          <comment>CELLRSAGC</comment>
        </bits>
      </reg>
      <reg name="crs_pow_max5" protect="r">
        <bits access="r" name="crs_pow_max5_crs_pow_max5" pos="31:0" rst="0">
          <comment>CELLRS</comment>
        </bits>
      </reg>
      <reg name="crs_pow_agc5" protect="r">
        <bits access="r" name="crs_pow_agc5_crs_pow_agc5" pos="9:0" rst="0">
          <comment>CELLRSAGC</comment>
        </bits>
      </reg>
      <reg name="fsm_state" protect="r">
        <bits access="r" name="fsm_state_fsm_state" pos="31:0" rst="1">
          <comment/>
        </bits>
      </reg>
      <reg name="txrx_norm_gene1" protect="r">
        <bits access="r" name="ofdm7_norm_gene" pos="31:28" rst="0">
          <comment>OFDM 7TXRX</comment>
        </bits>
        <bits access="r" name="ofdm6_norm_gene" pos="27:24" rst="0">
          <comment>OFDM 6TXRX</comment>
        </bits>
        <bits access="r" name="ofdm5_norm_gene" pos="23:20" rst="0">
          <comment>OFDM 5TXRX</comment>
        </bits>
        <bits access="r" name="ofdm4_norm_gene" pos="19:16" rst="0">
          <comment>OFDM 4TXRX</comment>
        </bits>
        <bits access="r" name="ofdm3_norm_gene" pos="15:12" rst="0">
          <comment>OFDM 3TXRX</comment>
        </bits>
        <bits access="r" name="ofdm2_norm_gene" pos="11:8" rst="0">
          <comment>OFDM 2TXRX</comment>
        </bits>
        <bits access="r" name="ofdm1_norm_gene" pos="7:4" rst="0">
          <comment>OFDM 1TXRX</comment>
        </bits>
        <bits access="r" name="ofdm0_norm_gene" pos="3:0" rst="0">
          <comment>OFDM 0TXRX</comment>
        </bits>
      </reg>
      <reg name="txrx_norm_gene2" protect="r">
        <bits access="r" name="ofdm13_norm_gene" pos="23:20" rst="0">
          <comment>OFDM 13TXRX</comment>
        </bits>
        <bits access="r" name="ofdm12_norm_gene" pos="19:16" rst="0">
          <comment>OFDM 12TXRX</comment>
        </bits>
        <bits access="r" name="ofdm11_norm_gene" pos="15:12" rst="0">
          <comment>OFDM 11TXRX</comment>
        </bits>
        <bits access="r" name="ofdm10_norm_gene" pos="11:8" rst="0">
          <comment>OFDM 10TXRX</comment>
        </bits>
        <bits access="r" name="ofdm9_norm_gene" pos="7:4" rst="0">
          <comment>OFDM 9TXRX</comment>
        </bits>
        <bits access="r" name="ofdm8_norm_gene" pos="3:0" rst="0">
          <comment>OFDM 8TXRX</comment>
        </bits>
      </reg>
      <reg name="txrx_soft_offset" protect="r">
        <bits access="r" name="txrx_soft_offset1" pos="9:5" rst="0">
          <comment>TXRXSOFT IRT1</comment>
        </bits>
        <bits access="r" name="txrx_soft_offset0" pos="4:0" rst="0">
          <comment>TXRXSOFT IRT0</comment>
        </bits>
      </reg>
      <reg name="ofdm_assert" protect="r">
        <bits access="r" name="txrx_enable_assert" pos="4" rst="0">
          <comment>ASSERTTXRX_ENABLE</comment>
        </bits>
        <bits access="r" name="ofdm_assert_ofdm_assert" pos="3:0" rst="0">
          <comment>ASSERTOFDM0~13</comment>
        </bits>
      </reg>
      <reg name="fsm_state_assert" protect="r">
        <bits access="r" name="fsm_state_assert_fsm_state_assert" pos="31:0" rst="0">
          <comment>ASSERT</comment>
        </bits>
      </reg>
      <reg name="abis_real_time_flag" protect="r">
        <bits access="r" name="abis_real_time_flag3" pos="2" rst="0">
          <comment>0ABISLLR_OUT3
1ABISLLR_OUT3</comment>
        </bits>
        <bits access="r" name="abis_real_time_flag2" pos="1" rst="0">
          <comment>0ABISLLR_OUT2
1ABISLLR_OUT2</comment>
        </bits>
        <bits access="r" name="abis_real_time_flag1" pos="0" rst="0">
          <comment>0ABISLLR_OUT1
1ABISLLR_OUT1</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_coeff.xml">
    <module category="LTE_SYS" name="CP_LTE_COEFF">
      <reg name="qfqt_start" protect="rw">
        <bits access="rw" name="meas_en" pos="10" rst="0">
          <comment>Coeffmeas
1
0</comment>
        </bits>
        <bits access="rw" name="ldtc_en" pos="9" rst="0">
          <comment>Coeffldtc\ldtc1
1
0</comment>
        </bits>
        <bits access="rw" name="buf_sel" pos="8:7" rst="0">
          <comment>Coeffldtc\ldtc1 buf
00ldtc buf1
01ldtc buf2
10ldtc buf3
11</comment>
        </bits>
        <bits access="rw" name="cat_sel" pos="6" rst="0">
          <comment>CAT1CATM
0CATM
1CAT1</comment>
        </bits>
        <bits access="rw" name="fast_mod" pos="5" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="port_sel" pos="4" rst="0">
          <comment>Port
0Port78
1Port5</comment>
        </bits>
        <bits access="rw" name="qfqt_inten" pos="2" rst="0">
          <comment>0QFQT
1QFQT</comment>
        </bits>
        <bits access="rw" name="cp_type" pos="1" rst="0">
          <comment>0: NCP
1: ECP</comment>
        </bits>
        <bits access="rw" name="qfqt_en" pos="0" rst="0">
          <comment>0: QFQT
1: QFQT</comment>
        </bits>
      </reg>
      <reg name="qfqt_state" protect="rw">
        <bits access="rc" name="which_err" pos="3:2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          buf
00ldtc buf1
01ldtc buf2
10ldtc buf3
11meas buf</comment>
        </bits>
        <bits access="rc" name="err_state" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.</comment>
        </bits>
        <bits access="rc" name="qfqt_intf" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
0:
1:</comment>
        </bits>
      </reg>
      <reg name="qf_conf" protect="rw">
        <bits access="rw" name="sys_band_sel" pos="17:15" rst="0">
          <comment>000: 6PRB
001: 15PRB
010: 25PRB
011: 50PRB
100: 75PRB
101: 100PRB
Others: RESERVED 6PRB</comment>
        </bits>
        <bits access="rw" name="coeff_qf_snr" pos="14:4" rst="1">
          <comment/>
        </bits>
        <bits access="rw" name="cha_mod" pos="1:0" rst="0">
          <comment>00: EPA
01: EVA
10: ETU
11: RESERVED EPA</comment>
        </bits>
      </reg>
      <reg name="qt_conf" protect="rw">
        <bits access="rw" name="doppler" pos="17:16" rst="0">
          <comment>005
0170
10300
11:   850</comment>
        </bits>
        <bits access="rw" name="tdd_fdd" pos="15" rst="0">
          <comment>TDDFDD
0TDD
1FDD</comment>
        </bits>
        <bits access="rw" name="coeff_qt_snr" pos="14:4" rst="1">
          <comment/>
        </bits>
        <bits access="rw" name="ss_sel" pos="3:0" rst="0">
          <comment>0000SS0
0001SS1
0010SS2
0011SS3
0100SS4
0101SS5
0110SS6
0111SS7
1000SS8
1001SS9</comment>
        </bits>
      </reg>
      <reg name="sw_in" protect="rw">
        <bits access="rw" name="sw_in_sw_in" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="sw_out" protect="r">
        <bits access="r" name="sw_out_sw_out" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_rfad.xml">
    <module category="LTE_SYS" name="CP_LTE_RFAD">
      <reg name="mod_en" protect="rw">
        <bits access="rw" name="mod_up_en" pos="1" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="mod_dn_en" pos="0" rst="0">
          <comment>1
0</comment>
        </bits>
      </reg>
      <reg name="ram_addr_map_cfg" protect="rw">
        <bits access="rw" name="ram3_start_addr_up" pos="31:24" rst="0">
          <comment>RAM3RAM
RAM3256+</comment>
        </bits>
        <bits access="rw" name="ram2_start_addr_up" pos="23:16" rst="0">
          <comment>RAM2SPI RAM</comment>
        </bits>
        <bits access="rw" name="ram3_start_addr_dn" pos="15:8" rst="0">
          <comment>RAM3RAM
RAM3256+</comment>
        </bits>
        <bits access="rw" name="ram2_start_addr_dn" pos="7:0" rst="0">
          <comment>RAM2SPI RAM</comment>
        </bits>
      </reg>
      <reg name="gpo_immdata" protect="rw">
        <bits access="rw" name="up_sel" pos="16" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="spi_sel" pos="15" rst="0">
          <comment>SPI
1SPI
0GPO</comment>
        </bits>
        <bits access="rw" name="spi_rw" pos="14" rst="0">
          <comment>SPI
1SPI
0SPI</comment>
        </bits>
        <bits access="rw" name="gpo" pos="13:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="spi_immdata" protect="rw">
        <bits access="rw" name="data" pos="31:0" rst="0">
          <comment>SPI</comment>
        </bits>
      </reg>
      <reg name="spi_cfg" protect="rw">
        <bits access="rw" name="distance" pos="29:26" rst="3">
          <comment>SPISENSCLK</comment>
        </bits>
        <bits access="rw" name="frq_div_rd" pos="25:23" rst="1">
          <comment>SPI
0004
0016default
0108
01110
10012
10114
11016
11118</comment>
        </bits>
        <bits access="rw" name="frq_div_wr" pos="22:20" rst="1">
          <comment>SPI
0004
0016default
0108
01110
10012
10114
11016
11118</comment>
        </bits>
        <bits access="rw" name="cs_inv" pos="19" rst="0">
          <comment>4-W3-W
0
1</comment>
        </bits>
        <bits access="rw" name="dux" pos="18" rst="0">
          <comment>17bit4
0
1</comment>
        </bits>
        <bits access="rw" name="ms" pos="17" rst="0">
          <comment>SPI
03
14</comment>
        </bits>
        <bits access="rw" name="rd_inter" pos="16:15" rst="2">
          <comment>SPISPI
00:0
01:1
10:2
11:3</comment>
        </bits>
        <bits access="rw" name="rd_edge" pos="14" rst="0">
          <comment>00
1</comment>
        </bits>
        <bits access="rw" name="sec" pos="13" rst="0">
          <comment>0Normal SPI
1DigRF SPI</comment>
        </bits>
        <bits access="rw" name="cpha" pos="12" rst="1">
          <comment>SPI
0:
1;
1:
;</comment>
        </bits>
        <bits access="rw" name="cpol" pos="11" rst="0">
          <comment>SPI
0: SPIIDLE
1: SPIIDLE</comment>
        </bits>
        <bits access="rw" name="spol" pos="10" rst="0">
          <comment>SPI
0: SPI
1: SPI</comment>
        </bits>
        <bits access="rw" name="rx_data_len" pos="9:5" rst="15">
          <comment>SPI
00000: 1-bits
00001: 2-bits
...........
11111: 32-bits</comment>
        </bits>
        <bits access="rw" name="tx_data_len" pos="4:0" rst="31">
          <comment>SPI
00000: 1-bits
00001: 2-bits
...........
11111: 32-bits</comment>
        </bits>
      </reg>
      <reg name="spi_rxdata" protect="r">
        <bits access="r" name="rx_data" pos="31:0" rst="0">
          <comment>RFSPI</comment>
        </bits>
      </reg>
      <reg name="debug_data" protect="r">
        <bits access="r" name="framc_err_up_flag" pos="31" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="r" name="insert_err_up_flag" pos="30" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="r" name="addr_err_up" pos="29" rst="0">
          <comment>0RAM
1RAM</comment>
        </bits>
        <bits access="r" name="time_err_up" pos="28" rst="0">
          <comment>0
1
0xf0xA</comment>
        </bits>
        <bits access="r" name="ram_rd_addr_up" pos="24:16" rst="0">
          <comment>RAM</comment>
        </bits>
        <bits access="r" name="framc_err_dn_flag" pos="15" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="r" name="insert_err_dn_flag" pos="14" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="r" name="addr_err_dn" pos="13" rst="0">
          <comment>0RAM
1RAM</comment>
        </bits>
        <bits access="r" name="time_err_dn" pos="12" rst="0">
          <comment>0
1
0xf0xA</comment>
        </bits>
        <bits access="r" name="ram_rd_addr_dn" pos="8:0" rst="0">
          <comment>RAM</comment>
        </bits>
      </reg>
      <reg name="rf_gpo_ctrl" protect="rw">
        <bits access="rw" name="rf_gpo_ctrl_rf_gpo_ctrl" pos="31:0" rst="3">
          <comment>RF GPO control register</comment>
        </bits>
      </reg>
      <reg name="framl_rfad" protect="rw">
        <bits access="rw" name="dont_insert_en" pos="18" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="up_en" pos="17" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="dn_en" pos="16" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="framc_rfad" pos="15:0" rst="30720">
          <comment>RFAD</comment>
        </bits>
      </reg>
      <reg name="framc_err_up" protect="r">
        <bits access="r" name="framc_err_up_flag" pos="24" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="r" name="framc_err_up_framc_err_up" pos="23:0" rst="0">
          <comment>FRAMC</comment>
        </bits>
      </reg>
      <reg name="data_time_err_up" protect="r">
        <bits access="r" name="ram_rd_addr_up" pos="31:24" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="data_time_err_up_data_time_err_up" pos="23:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="framc_err_dn" protect="r">
        <bits access="r" name="framc_err_dn_flag" pos="24" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="r" name="framc_err_dn_framc_err_dn" pos="23:0" rst="0">
          <comment>FRAMC</comment>
        </bits>
      </reg>
      <reg name="data_time_err_dn" protect="r">
        <bits access="r" name="ram_rd_addr_dn" pos="31:24" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="data_time_err_dn_data_time_err_dn" pos="23:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="framl_err" protect="r">
        <bits access="r" name="framl_err_up" pos="31:16" rst="0">
          <comment>FRAML</comment>
        </bits>
        <bits access="r" name="framl_err_dn" pos="15:0" rst="0">
          <comment>FRAML</comment>
        </bits>
      </reg>
      <reg name="dont_insert_err_up" protect="r">
        <bits access="r" name="ram_rd_addr_up" pos="31:24" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="framc_err_up" pos="23:0" rst="0">
          <comment>FRAMC</comment>
        </bits>
      </reg>
      <reg name="dont_insert_err_dn" protect="r">
        <bits access="r" name="ram_rd_addr_dn" pos="31:24" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="framc_err_dn" pos="23:0" rst="0">
          <comment>FRAMC</comment>
        </bits>
      </reg>
      <hole size="32256"/>
      <reg name="down_mem" protect="rw">
        <bits access="rw" name="down_mem_down_mem" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="up_mem" protect="rw">
        <bits access="rw" name="up_mem_up_mem" pos="31:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_uldft.xml">
    <module category="LTE_SYS" name="CP_LTE_ULDFT">
      <reg name="dft_ctrl_next" protect="rw">
        <bits access="rw" name="dft_npts_next" pos="10:5" rst="0">
          <comment>bit type is changed from r/w to rw.
          DFT/IDFTindex0~4344index</comment>
        </bits>
        <bits access="rw" name="pus_modu_sel_next" pos="4:3" rst="0">
          <comment>bit type is changed from r/w to rw.
          00: BPSK
01: QPSK
10: 16QAM
11: 64QAM</comment>
        </bits>
        <bits access="rw" name="dft_en_next" pos="2" rst="0">
          <comment>bit type is changed from r/w to rw.
          0DFT/IDFT
1DFT/IDFT</comment>
        </bits>
        <bits access="rw" name="pus_mod_en_next" pos="1" rst="0">
          <comment>bit type is changed from r/w to rw.
          0PUSCH
1PUSCH</comment>
        </bits>
        <bits access="rw" name="dft_idft_sel_next" pos="0" rst="0">
          <comment>bit type is changed from r/w to rw.
          0: DFT
1: IDFT</comment>
        </bits>
      </reg>
      <reg name="puc_mod_data_next" protect="rw">
        <bits access="rw" name="puc_mod_data_next_puc_mod_data_next" pos="21:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          PUCCHd(n)</comment>
        </bits>
      </reg>
      <reg name="srs_map_cfg_next" protect="rw">
        <bits access="rw" name="k_tc_num_next" pos="26" rst="0">
          <comment>SRS
021
143</comment>
        </bits>
        <bits access="rw" name="k_tc_next" pos="25:24" rst="0">
          <comment>bit type is changed from r/w to rw.
000
011
102
113</comment>
        </bits>
        <bits access="rw" name="srs_map_len_next" pos="22:16" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRS</comment>
        </bits>
        <bits access="rw" name="srs_map_start2_next" pos="14:8" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRS</comment>
        </bits>
        <bits access="rw" name="srs_map_start1_next" pos="6:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRS</comment>
        </bits>
      </reg>
      <reg name="srs_zc_len_next" protect="rw">
        <bits access="rw" name="srs_num_next" pos="24" rst="0">
          <comment>0SRS1
1SRS2</comment>
        </bits>
        <bits access="rw" name="srs_map_ofdm2_next" pos="23:20" rst="0">
          <comment>SRSOFDM</comment>
        </bits>
        <bits access="rw" name="sra_map_ofdm1_next" pos="19:16" rst="0">
          <comment>SRSOFDM</comment>
        </bits>
        <bits access="rw" name="special_frame_start_next" pos="15:12" rst="0">
          <comment>SRSOFDM</comment>
        </bits>
        <bits access="rw" name="srs_zc_len_next_srs_zc_len_next" pos="10:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRSZC</comment>
        </bits>
      </reg>
      <reg name="puc_map_cfg_next" protect="rw">
        <bits access="rw" name="tx_fir_en_next" pos="31" rst="0">
          <comment>0TX
1TX</comment>
        </bits>
        <bits access="rw" name="tx_nb_start2_next" pos="30:24" rst="0">
          <comment>2</comment>
        </bits>
        <bits access="rw" name="tx_nb_start1_next" pos="22:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="puc_map_start2_next" pos="14:8" rst="0">
          <comment>PUCCH</comment>
        </bits>
        <bits access="rw" name="puc_map_start1_next" pos="6:0" rst="0">
          <comment>PUCCH</comment>
        </bits>
      </reg>
      <reg name="pus_map_cfg_next" protect="rw">
        <bits access="rw" name="pus_map_sel_next" pos="31" rst="0">
          <comment>PUSCH
00.5ms
11ms</comment>
        </bits>
        <bits access="rw" name="pus_map_len2_next" pos="30:24" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="pus_map_len1_next" pos="22:16" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="pus_map_start2_next" pos="14:8" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="pus_map_start1_next" pos="6:0" rst="0">
          <comment>PUSCH</comment>
        </bits>
      </reg>
      <reg name="hard_para_next1" protect="rw">
        <bits access="rw" name="pus_dmrs_w_flag" pos="15" rst="0">
          <comment>PUSCH DMRS
1
0</comment>
        </bits>
        <bits access="rw" name="pucpus_shortened_mode_next" pos="14:11" rst="0">
          <comment>PUSCH/PUCCH
0000normal
0001type0_shortend
0010type1_shortend
0011type2_shortend
0100type3_shortend
0101type4_shortend
0110type5_shortend
0111:  type6_shortend
1000:  type7_shortend
1001:  other</comment>
        </bits>
        <bits access="rw" name="group_hop_flag_next" pos="10" rst="0">
          <comment>1u
0u</comment>
        </bits>
        <bits access="rw" name="seq_hop_flag_next" pos="9" rst="0">
          <comment>1v
0v</comment>
        </bits>
        <bits access="rw" name="ta_overlap_next" pos="8:3" rst="0">
          <comment>TA0~32</comment>
        </bits>
        <bits access="rw" name="cyclic_shift_field_next" pos="2:0" rst="0">
          <comment>dmrsValue0~7</comment>
        </bits>
      </reg>
      <reg name="hard_para_next2" protect="rw">
        <bits access="rw" name="delta_apc_srs_next" pos="31:16" rst="0">
          <comment>SRSAPC</comment>
        </bits>
        <bits access="rw" name="delta_apc_scr_next" pos="15:0" rst="0">
          <comment>PUSCH/PUCCH/PRACHAPC</comment>
        </bits>
      </reg>
      <reg name="hard_para_next3" protect="rw">
        <bits access="rw" name="n1_pucch_next" pos="31:20" rst="0">
          <comment>PUCCH1/1a/1b0~4095</comment>
        </bits>
        <bits access="rw" name="srs_cycle_shift_next" pos="19:16" rst="0">
          <comment>SRS</comment>
        </bits>
        <bits access="rw" name="subframe_slot_cnt_next" pos="14:10" rst="0">
          <comment>CAT1/CATM/CAT-NB15kHz1ms2CAT-NB3.75kHz2ms1</comment>
        </bits>
        <bits access="rw" name="nf_next" pos="9:0" rst="0">
          <comment>0~1023</comment>
        </bits>
      </reg>
      <reg name="ofdm_offset_next" protect="rw">
        <bits access="rw" name="ofdm_offset_last_next" pos="31:16" rst="0">
          <comment>OFDMoffset</comment>
        </bits>
        <bits access="rw" name="ofdm_offset_first_next" pos="15:0" rst="0">
          <comment>OFDMoffset</comment>
        </bits>
      </reg>
      <reg name="dft_fft_inten_next" protect="rw">
        <bits access="rw" name="err_inten_next" pos="15" rst="0">
          <comment>0ULDFTTXRXPUSCHERROR
1ULDFTTXRXPUSCHERROR</comment>
        </bits>
        <bits access="rw" name="dma_inten_next" pos="14" rst="0">
          <comment>1AXIDMA
0AXIDMA</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten13_next" pos="13" rst="0">
          <comment>1OFDM13
0OFDM13</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten12_next" pos="12" rst="0">
          <comment>1OFDM12
0OFDM12</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten11_next" pos="11" rst="0">
          <comment>1OFDM11
0OFDM11</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten10_next" pos="10" rst="0">
          <comment>1OFDM10
0OFDM10</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten9_next" pos="9" rst="0">
          <comment>1OFDM9
0OFDM9</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten8_next" pos="8" rst="0">
          <comment>1OFDM8
0OFDM8</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten7_next" pos="7" rst="0">
          <comment>1OFDM7
0OFDM7</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten6_next" pos="6" rst="0">
          <comment>1OFDM6
0OFDM6</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten5_next" pos="5" rst="0">
          <comment>1OFDM5
0OFDM5</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten4_next" pos="4" rst="0">
          <comment>1OFDM4
0OFDM4</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten3_next" pos="3" rst="0">
          <comment>1OFDM3
0OFDM3</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten2_next" pos="2" rst="0">
          <comment>1OFDM2
0OFDM2</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten1_next" pos="1" rst="0">
          <comment>1OFDM1
0OFDM1</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten0_next" pos="0" rst="0">
          <comment>1OFDM0
0OFDM0</comment>
        </bits>
      </reg>
      <reg name="dft_fft_intf_next" protect="rw">
        <bits access="rc" name="dft_fft_intf13_next" pos="15" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM13
0OFDM13</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf12_next" pos="14" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM12
0OFDM12</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf11_next" pos="13" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM11
0OFDM11</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf10_next" pos="12" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM10
0OFDM10</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf9_next" pos="11" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM9
0OFDM9</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf8_next" pos="10" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM8
0OFDM8</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf7_next" pos="9" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM7
0OFDM7</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf6_next" pos="8" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM6
0OFDM6</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf5_next" pos="7" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM5
0OFDM5</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf4_next" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM4
0OFDM4</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf3_next" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM3
0OFDM3</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf2_next" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM2
0OFDM2</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf1_next" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM1
0OFDM1</comment>
        </bits>
        <bits access="rc" name="dft_fft_intf0_next" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1OFDM0
0OFDM0</comment>
        </bits>
        <bits access="rc" name="pus_rd_errf" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1pusch
0pusch</comment>
        </bits>
        <bits access="rc" name="txrx_wr_errf" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1txrx
0txrx</comment>
        </bits>
      </reg>
      <reg name="ofdm_zero_next" protect="rw">
        <bits access="rw" name="ofdm_zero_next_ofdm_zero_next" pos="13:0" rst="0">
          <comment>OFDM
14b0
14b10
14b1101
14b111012</comment>
        </bits>
      </reg>
      <reg name="dft_fft_ctrl_next" protect="rw">
        <bits access="rw" name="dftfft_soft_start" pos="30" rst="0">
          <comment>0ULDFT
1ULDFT</comment>
        </bits>
        <bits access="rw" name="dft_trig_mode" pos="29" rst="0">
          <comment>0ULDFT
1ULDFTPUSCH</comment>
        </bits>
        <bits access="rw" name="launch_en_next" pos="28" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="srs_en_next" pos="27" rst="0">
          <comment>0SRS
1SRS</comment>
        </bits>
        <bits access="rw" name="clear_en_next" pos="26" rst="0">
          <comment>0FFTMEM
1FFTMEM</comment>
        </bits>
        <bits access="rw" name="fft_ifft_sel_next" pos="25" rst="0">
          <comment>1IFFT
0FFT</comment>
        </bits>
        <bits access="rw" name="fft_cal_next" pos="24" rst="0">
          <comment>1FFT/IFFT
0FFT/IFFT</comment>
        </bits>
        <bits access="rw" name="pwradj_en_next" pos="23" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="prach_format_sel_next" pos="22:20" rst="0">
          <comment>PRACH
000PRACH0
001PRACH1
010PRACH2
011PRACH3
100PRACH4</comment>
        </bits>
        <bits access="rw" name="pucch_format_sel_next" pos="19:17" rst="0">
          <comment>PUCCH
000PUCCH1
001PUCCH1a
010PUCCH1b
011PUCCH2
100PUCCH2a
101PUCCH2b</comment>
        </bits>
        <bits access="rw" name="npusch_formatsel_next" pos="16" rst="0">
          <comment>0NPUSCH format 1
1NPUSCH format2</comment>
        </bits>
        <bits access="rw" name="ofdm_num_next" pos="15:12" rst="0">
          <comment>OFDM</comment>
        </bits>
        <bits access="rw" name="datadrive_en_next" pos="10" rst="0">
          <comment>0DATADRIVE
1DATADRIVE</comment>
        </bits>
        <bits access="rw" name="pus_buf_sel_next" pos="9:8" rst="0">
          <comment>UL_DFTPUSCH BUFFER
00PUSCH BUFFER1
01PUSCH BUFFER2
10PUSCH BUFFER3
11PUSCH PRA_BUF</comment>
        </bits>
        <bits access="rw" name="chan_mode_next" pos="6:4" rst="0">
          <comment>000PUSCH
001PUCCH
010PRACH
011SRS
100NPUSCH
101NPRACH</comment>
        </bits>
        <bits access="rw" name="fft_npts" pos="3:1" rst="0">
          <comment>FFT/IFFT
111
110
101
1002048
0111024
010512
001256
000128</comment>
        </bits>
        <bits access="rw" name="dftfft_irqen_next" pos="0" rst="0">
          <comment>0:
1:</comment>
        </bits>
      </reg>
      <reg name="fft_lnum_srs_next" protect="rw">
        <bits access="rw" name="fft_lnum11_srs_next" pos="21:20" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum10_srs_next" pos="19:18" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum9_srs_next" pos="17:16" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum8_srs_next" pos="15:14" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum7_srs_next" pos="13:12" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum6_srs_next" pos="11:10" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum5_srs_next" pos="9:8" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum4_srs_next" pos="7:6" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum3_srs_next" pos="5:4" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum2_srs_next" pos="3:2" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum1_srs_next" pos="1:0" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
      </reg>
      <reg name="fft_lnum_scr_next" protect="rw">
        <bits access="rw" name="fft_lnum11_scr_next" pos="21:20" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum10_scr_next" pos="19:18" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum9_scr_next" pos="17:16" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum8_scr_next" pos="15:14" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum7_scr_next" pos="13:12" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum6_scr_next" pos="11:10" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum5_scr_next" pos="9:8" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum4_scr_next" pos="7:6" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum3_scr_next" pos="5:4" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum2_scr_next" pos="3:2" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum1_scr_next" pos="1:0" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
      </reg>
      <reg name="npus_map_cfg_next" protect="rw">
        <bits access="rw" name="npus_rep_cnt_next" pos="23:17" rst="0">
          <comment>NPUSCH0~127</comment>
        </bits>
        <bits access="rw" name="n_ru_sc_next" pos="16:15" rst="0">
          <comment>001
013
106
1112</comment>
        </bits>
        <bits access="rw" name="isc_start_index_next" pos="14:9" rst="0">
          <comment>NPUSCH 0~47</comment>
        </bits>
        <bits access="rw" name="n_slot_cnt_next" pos="8:1" rst="0">
          <comment>Nslots1~160</comment>
        </bits>
        <bits access="rw" name="npus_sub_space_next" pos="0" rst="0">
          <comment>0: 3.75KHz
1: 15KHz</comment>
        </bits>
      </reg>
      <reg name="npus_dmrs_cfg_next" protect="rw">
        <bits access="rw" name="first_ru_slot_next" pos="26:22" rst="0">
          <comment>RU0~19</comment>
        </bits>
        <bits access="rw" name="slot_n_next" pos="21:7" rst="0">
          <comment>1DMRS0~20480</comment>
        </bits>
        <bits access="rw" name="base_seq_next" pos="6:2" rst="0">
          <comment>BASE_SEQ_NEXT0~30</comment>
        </bits>
        <bits access="rw" name="cyclic_shift_next" pos="1:0" rst="0">
          <comment>CYCLIC_SHIFT0~3</comment>
        </bits>
      </reg>
      <reg name="npra_cfg_next" protect="rw">
        <bits access="rw" name="sym_group_rep_cnt_next" pos="16:9" rst="0">
          <comment>t0~128</comment>
        </bits>
        <bits access="rw" name="nprach_sc_offset_next" pos="8:6" rst="0">
          <comment>frequency location of the first sub-carrier allocated to NPRACH
000frequency location0
001frequency location2
010frequency location12
011frequency location18
100frequency location24
101frequency location34
110frequency location36
1110</comment>
        </bits>
        <bits access="rw" name="init_sc_next" pos="5:0" rst="0">
          <comment>being the subcarrier selected by the MAC layer from  0-47</comment>
        </bits>
      </reg>
      <reg name="inout_para" protect="rw">
        <bits access="rw" name="fir_bit_sel" pos="28:25" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="delta_ss" pos="24:20" rst="0">
          <comment>0~29</comment>
        </bits>
        <bits access="rw" name="n2_pucch" pos="19:9" rst="0">
          <comment>PUCCH2/2a/2b0~1184</comment>
        </bits>
        <bits access="rw" name="cyclic_shift" pos="8:6" rst="0">
          <comment>0~7</comment>
        </bits>
        <bits access="rw" name="cp_mode" pos="2" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="rw" name="tdd_fdd_mode_sel" pos="1" rst="0">
          <comment>0TDD  mode
1FDD  mode</comment>
        </bits>
        <bits access="rw" name="inout_ctrl" pos="0" rst="0">
          <comment>1:
0:</comment>
        </bits>
      </reg>
      <reg name="id_para" protect="rw">
        <bits access="rw" name="ncs_u_gold_mode" pos="29" rst="0">
          <comment>NCSUGOLDC_INI
1if no value for   or   is configured by higher layers or the PUSCH transmission corresponds to a Random Access Response Grant or a retransmission of the same transport block as part of the contention based random access procedure
0otherwise</comment>
        </bits>
        <bits access="rw" name="csh_dmrs_id" pos="28:19" rst="0">
          <comment>NCS_U_GOLD_MODE1 + 0~532NCS_U_GOLD_MODE0 0~509</comment>
        </bits>
        <bits access="rw" name="rs_id" pos="18:9" rst="0">
          <comment>NCS_U_GOLD_MODE1 + 0~532NCS_U_GOLD_MODE0 0~509</comment>
        </bits>
        <bits access="rw" name="cell_id" pos="8:0" rst="0">
          <comment>ID0~503</comment>
        </bits>
      </reg>
      <reg name="pucch_dummy_id" protect="rw">
        <bits access="rw" name="puc_dummy_id" pos="8:0" rst="0">
          <comment>RSID</comment>
        </bits>
      </reg>
      <reg name="puc_rbmap_config" protect="rw">
        <bits access="rw" name="ncs1_puc" pos="14:12" rst="0">
          <comment>nCsAn1/1a/1b0~7</comment>
        </bits>
        <bits access="rw" name="ce_mode_flag" pos="10" rst="0">
          <comment>CE_mode
0CE_modeA
1CE_modeB</comment>
        </bits>
        <bits access="rw" name="delta_shift_puc" pos="9:8" rst="0">
          <comment>00 1
01 2
10 3
1100 1</comment>
        </bits>
        <bits access="rw" name="nrb2" pos="6:0" rst="0">
          <comment>cqiNrb PUCCH2/2a/2b0~98</comment>
        </bits>
      </reg>
      <reg name="sysband_config" protect="rw">
        <bits access="rw" name="mode_sel" pos="4:3" rst="0">
          <comment>ULDFT
00CAT1
01CATM
10NB-IOT
11CAT1</comment>
        </bits>
        <bits access="rw" name="sys_band" pos="2:0" rst="0">
          <comment>CAT1
0006PRB
00115PRB
01025PRB
01150PRB
10075PRB
101100PRB
6PRB</comment>
        </bits>
      </reg>
      <reg name="dftfft_launch" protect="rw">
        <bits access="rw" name="dma_start_en" pos="1" rst="0">
          <comment>0DMA
1DMA</comment>
        </bits>
        <bits access="rw" name="dftfft_launch_dftfft_launch" pos="0" rst="0">
          <comment>0:
1:</comment>
        </bits>
      </reg>
      <reg name="dft_fft_sw_stop" protect="rw">
        <bits access="rw" name="sw_pause_ofdm" pos="17:4" rst="0">
          <comment>SW_PAUSE_EN=1OFDM
14`b0
14`b1OFDM0
14`b11OFDM01
14`b111OFDM012</comment>
        </bits>
        <bits access="rw" name="sw_pause_way" pos="3" rst="0">
          <comment>SW_PAUSE_EN=1
0SW_PAUSE_OFDMOFDM
1SW_PAUSE_OFDMOFDM</comment>
        </bits>
        <bits access="rw" name="sw_pause_en" pos="2" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="sw_tmp_en" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="sw_stop_en" pos="0" rst="0">
          <comment>0
1OFDM</comment>
        </bits>
      </reg>
      <reg name="dft_fft_sw_stop_flag" protect="rw">
        <bits access="rc" name="sw_pause_flag" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
        <bits access="rc" name="sw_stop_flag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
      </reg>
      <reg name="dft_ctrl_curr1" protect="rw">
        <bits access="rw" name="dft_npts_curr" pos="10:5" rst="0">
          <comment>bit type is changed from r/w to rw.
          DFT/IDFTindex0~4344index</comment>
        </bits>
        <bits access="rw" name="pus_modu_sel_curr" pos="4:3" rst="0">
          <comment>bit type is changed from r/w to rw.
          00: BPSK
01: QPSK
10: 16QAM
11: 64QAM</comment>
        </bits>
        <bits access="rw" name="dft_en_curr" pos="2" rst="0">
          <comment>bit type is changed from r/w to rw.
          0DFT/IDFT
1DFT/IDFT</comment>
        </bits>
        <bits access="rw" name="pus_mod_en_curr" pos="1" rst="0">
          <comment>bit type is changed from r/w to rw.
          0PUSCH
1PUSCH</comment>
        </bits>
        <bits access="rw" name="dft_idft_sel_curr" pos="0" rst="0">
          <comment>bit type is changed from r/w to rw.
          0: DFT
1: IDFT</comment>
        </bits>
      </reg>
      <reg name="puc_mod_data_curr1" protect="rw">
        <bits access="rw" name="puc_mod_data_curr" pos="21:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          PUCCHd(n)</comment>
        </bits>
      </reg>
      <reg name="srs_map_cfg_curr1" protect="rw">
        <bits access="rw" name="k_tc_num_curr" pos="26" rst="0">
          <comment>SRS
021
143</comment>
        </bits>
        <bits access="rw" name="k_tc_curr" pos="25:24" rst="0">
          <comment>bit type is changed from r/w to rw.
000
011
102
113</comment>
        </bits>
        <bits access="rw" name="srs_map_len_curr" pos="22:16" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRS</comment>
        </bits>
        <bits access="rw" name="srs_map_start2_curr" pos="14:8" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRS</comment>
        </bits>
        <bits access="rw" name="srs_map_start1_curr" pos="6:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRS</comment>
        </bits>
      </reg>
      <reg name="srs_zc_len_curr1" protect="rw">
        <bits access="rw" name="srs_num_curr" pos="24" rst="0">
          <comment>0SRS1
1SRS2</comment>
        </bits>
        <bits access="rw" name="srs_map_ofdm2_curr" pos="23:20" rst="0">
          <comment>SRSOFDM</comment>
        </bits>
        <bits access="rw" name="sra_map_ofdm1_curr" pos="19:16" rst="0">
          <comment>SRSOFDM</comment>
        </bits>
        <bits access="rw" name="special_frame_start_curr" pos="15:12" rst="0">
          <comment>SRSOFDM</comment>
        </bits>
        <bits access="rw" name="srs_zc_len_curr" pos="10:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRSZC</comment>
        </bits>
      </reg>
      <reg name="puc_map_cfg_curr1" protect="rw">
        <bits access="rw" name="tx_fir_en_curr" pos="31" rst="0">
          <comment>0TX
1TX</comment>
        </bits>
        <bits access="rw" name="tx_nb_start2_curr" pos="30:24" rst="0">
          <comment>2</comment>
        </bits>
        <bits access="rw" name="tx_nb_start1_curr" pos="22:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="puc_map_start2_curr" pos="14:8" rst="0">
          <comment>PUCCH</comment>
        </bits>
        <bits access="rw" name="puc_map_start1_curr" pos="6:0" rst="0">
          <comment>PUCCH</comment>
        </bits>
      </reg>
      <reg name="pus_map_cfg_curr1" protect="rw">
        <bits access="rw" name="pus_map_sel_curr" pos="31" rst="0">
          <comment>PUSCH
00.5ms
11ms</comment>
        </bits>
        <bits access="rw" name="pus_map_len2_curr" pos="30:24" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="pus_map_len1_curr" pos="22:16" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="pus_map_start2_curr" pos="14:8" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="pus_map_start1_curr" pos="6:0" rst="0">
          <comment>PUSCH</comment>
        </bits>
      </reg>
      <reg name="hard_para_curr11" protect="rw">
        <bits access="rw" name="pucpus_shortened_mode_curr" pos="14:11" rst="0">
          <comment>PUSCH/PUCCH
0000normal
0001type0_shortend
0010type1_shortend
0011type2_shortend
0100type3_shortend
0101type4_shortend
0110type5_shortend
0111:  type6_shortend
1000:  type7_shortend
1001:  other</comment>
        </bits>
        <bits access="rw" name="group_hop_flag_curr" pos="10" rst="0">
          <comment>1u
0u</comment>
        </bits>
        <bits access="rw" name="seq_hop_flag_curr" pos="9" rst="0">
          <comment>1v
0v</comment>
        </bits>
        <bits access="rw" name="ta_overlap_curr" pos="8:3" rst="0">
          <comment>TA0~32</comment>
        </bits>
        <bits access="rw" name="cyclic_shift_field_curr" pos="2:0" rst="0">
          <comment>dmrsValue0~7</comment>
        </bits>
      </reg>
      <reg name="hard_para_curr21" protect="rw">
        <bits access="rw" name="delta_apc_srs_curr" pos="31:16" rst="0">
          <comment>SRSAPC</comment>
        </bits>
        <bits access="rw" name="delta_apc_scr_curr" pos="15:0" rst="0">
          <comment>PUSCH/PUCCH/PRACHAPC</comment>
        </bits>
      </reg>
      <reg name="hard_para_curr31" protect="rw">
        <bits access="rw" name="n1_pucch_curr" pos="31:20" rst="0">
          <comment>PUCCH1/1a/1b0~4095</comment>
        </bits>
        <bits access="rw" name="srs_cycle_shift_curr" pos="19:16" rst="0">
          <comment>SRS</comment>
        </bits>
        <bits access="rw" name="subframe_slot_cnt_curr" pos="14:10" rst="0">
          <comment>CAT1/CATM/CAT-NB15kHz1ms2CAT-NB3.75kHz2ms1</comment>
        </bits>
        <bits access="rw" name="nf_curr" pos="9:0" rst="0">
          <comment>0~1023</comment>
        </bits>
      </reg>
      <reg name="ofdm_offset_curr1" protect="rw">
        <bits access="rw" name="ofdm_offset_last_curr" pos="31:16" rst="0">
          <comment>OFDMoffset</comment>
        </bits>
        <bits access="rw" name="ofdm_offset_first_curr" pos="15:0" rst="0">
          <comment>OFDMoffset</comment>
        </bits>
      </reg>
      <reg name="dft_fft_inten_curr1" protect="rw">
        <bits access="rw" name="err_inten_curr" pos="15" rst="0">
          <comment>0ULDFTTXRXPUSCHERROR
1ULDFTTXRXPUSCHERROR</comment>
        </bits>
        <bits access="rw" name="dma_inten_curr" pos="14" rst="0">
          <comment>1AXIDMA
0AXIDMA</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten13_curr" pos="13" rst="0">
          <comment>1OFDM13
0OFDM13</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten12_curr" pos="12" rst="0">
          <comment>1OFDM12
0OFDM12</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten11_curr" pos="11" rst="0">
          <comment>1OFDM11
0OFDM11</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten10_curr" pos="10" rst="0">
          <comment>1OFDM10
0OFDM10</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten9_curr" pos="9" rst="0">
          <comment>1OFDM9
0OFDM9</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten8_curr" pos="8" rst="0">
          <comment>1OFDM8
0OFDM8</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten7_curr" pos="7" rst="0">
          <comment>1OFDM7
0OFDM7</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten6_curr" pos="6" rst="0">
          <comment>1OFDM6
0OFDM6</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten5_curr" pos="5" rst="0">
          <comment>1OFDM5
0OFDM5</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten4_curr" pos="4" rst="0">
          <comment>1OFDM4
0OFDM4</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten3_curr" pos="3" rst="0">
          <comment>1OFDM3
0OFDM3</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten2_curr" pos="2" rst="0">
          <comment>1OFDM2
0OFDM2</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten1_curr" pos="1" rst="0">
          <comment>1OFDM1
0OFDM1</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten0_curr" pos="0" rst="0">
          <comment>1OFDM0
0OFDM0</comment>
        </bits>
      </reg>
      <reg name="ofdm_zero_curr1" protect="rw">
        <bits access="rw" name="ofdm_zero_curr" pos="13:0" rst="0">
          <comment>OFDM
14b0
14b10
14b1101
14b111012</comment>
        </bits>
      </reg>
      <reg name="dft_fft_ctrl_curr1" protect="rw">
        <bits access="rw" name="dftfft_soft_start" pos="30" rst="0">
          <comment>0ULDFT
1ULDFT</comment>
        </bits>
        <bits access="rw" name="dft_trig_mode" pos="29" rst="0">
          <comment>0ULDFT
1ULDFTPUSCH</comment>
        </bits>
        <bits access="rw" name="launch_en_curr" pos="28" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="srs_en_curr" pos="27" rst="0">
          <comment>0SRS
1SRS</comment>
        </bits>
        <bits access="rw" name="clear_en_curr" pos="26" rst="0">
          <comment>0FFTMEM
1FFTMEM</comment>
        </bits>
        <bits access="rw" name="fft_ifft_sel_curr" pos="25" rst="0">
          <comment>1IFFT
0FFT</comment>
        </bits>
        <bits access="rw" name="fft_cal_curr" pos="24" rst="0">
          <comment>1FFT/IFFT
0FFT/IFFT</comment>
        </bits>
        <bits access="rw" name="pwradj_en_curr" pos="23" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="prach_format_sel_curr" pos="22:20" rst="0">
          <comment>PRACH
000PRACH0
001PRACH1
010PRACH2
011PRACH3
100PRACH4</comment>
        </bits>
        <bits access="rw" name="pucch_format_sel_curr" pos="19:17" rst="0">
          <comment>PUCCH
000PUCCH1
001PUCCH1a
010PUCCH1b
011PUCCH2
100PUCCH2a
101PUCCH2b</comment>
        </bits>
        <bits access="rw" name="npusch_formatsel_curr" pos="16" rst="0">
          <comment>0NPUSCH format 1
1NPUSCH format2</comment>
        </bits>
        <bits access="rw" name="ofdm_num_curr" pos="15:12" rst="0">
          <comment>OFDM</comment>
        </bits>
        <bits access="rw" name="datadrive_en_curr" pos="10" rst="0">
          <comment>0DATADRIVE
1DATADRIVE</comment>
        </bits>
        <bits access="rw" name="pus_buf_sel_curr" pos="9:8" rst="0">
          <comment>UL_DFTPUSCH BUFFER
00PUSCH BUFFER1
01PUSCH BUFFER2
10PUSCH BUFFER3
11PUSCH PRA_BUF</comment>
        </bits>
        <bits access="rw" name="chan_mode_curr" pos="6:4" rst="0">
          <comment>000PUSCH
001PUCCH
010PRACH
011SRS
100NPUSCH
101NPRACH</comment>
        </bits>
        <bits access="rw" name="fft_npts" pos="3:1" rst="0">
          <comment>FFT/IFFT
111
110
101
1002048
0111024
010512
001256
000128</comment>
        </bits>
        <bits access="rw" name="dftfft_irqen_curr" pos="0" rst="0">
          <comment>0:
1:</comment>
        </bits>
      </reg>
      <reg name="fft_lnum_srs_curr1" protect="rw">
        <bits access="rw" name="fft_lnum11_srs_curr" pos="21:20" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum10_srs_curr" pos="19:18" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum9_srs_curr" pos="17:16" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum8_srs_curr" pos="15:14" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum7_srs_curr" pos="13:12" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum6_srs_curr" pos="11:10" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum5_srs_curr" pos="9:8" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum4_srs_curr" pos="7:6" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum3_srs_curr" pos="5:4" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum2_srs_curr" pos="3:2" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum1_srs_curr" pos="1:0" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
      </reg>
      <reg name="fft_lnum_scr_curr1" protect="rw">
        <bits access="rw" name="fft_lnum11_scr_curr" pos="21:20" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum10_scr_curr" pos="19:18" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum9_scr_curr" pos="17:16" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum8_scr_curr" pos="15:14" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum7_scr_curr" pos="13:12" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum6_scr_curr" pos="11:10" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum5_scr_curr" pos="9:8" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum4_scr_curr" pos="7:6" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum3_scr_curr" pos="5:4" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum2_scr_curr" pos="3:2" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum1_scr_curr" pos="1:0" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
      </reg>
      <reg name="npus_map_cfg_curr1" protect="rw">
        <bits access="rw" name="npus_rep_cnt_curr" pos="23:17" rst="0">
          <comment>NPUSCH0~127</comment>
        </bits>
        <bits access="rw" name="n_ru_sc_curr" pos="16:15" rst="0">
          <comment>001
013
106
1112</comment>
        </bits>
        <bits access="rw" name="isc_start_index_curr" pos="14:9" rst="0">
          <comment>NPUSCH 0~47</comment>
        </bits>
        <bits access="rw" name="n_slot_cnt_curr" pos="8:1" rst="0">
          <comment>Nslots1~160</comment>
        </bits>
        <bits access="rw" name="npus_sub_space_curr" pos="0" rst="0">
          <comment>0: 3.75KHz
1: 15KHz</comment>
        </bits>
      </reg>
      <reg name="npus_dmrs_cfg_curr1" protect="rw">
        <bits access="rw" name="first_ru_slot_curr" pos="26:22" rst="0">
          <comment>RU0~19</comment>
        </bits>
        <bits access="rw" name="slot_n_curr" pos="21:7" rst="0">
          <comment>1DMRS0~20480</comment>
        </bits>
        <bits access="rw" name="base_seq_curr" pos="6:2" rst="0">
          <comment>BASE_SEQ_CURR0~30</comment>
        </bits>
        <bits access="rw" name="cyclic_shift_curr" pos="1:0" rst="0">
          <comment>CYCLIC_SHIFT0~3</comment>
        </bits>
      </reg>
      <reg name="npra_cfg_curr1" protect="rw">
        <bits access="rw" name="sym_group_rep_cnt_curr" pos="16:9" rst="0">
          <comment>t0~128</comment>
        </bits>
        <bits access="rw" name="nprach_sc_offset_curr" pos="8:6" rst="0">
          <comment>frequency location of the first sub-carrier allocated to NPRACH
000frequency location0
001frequency location2
010frequency location12
011frequency location18
100frequency location24
101frequency location34
110frequency location36
1110</comment>
        </bits>
        <bits access="rw" name="init_sc_curr" pos="5:0" rst="0">
          <comment>being the subcarrier selected by the MAC layer from  0-47</comment>
        </bits>
      </reg>
      <reg name="dft_ctrl_curr2" protect="rw">
        <bits access="rw" name="dft_npts_curr" pos="10:5" rst="0">
          <comment>bit type is changed from r/w to rw.
          DFT/IDFTindex0~4344index</comment>
        </bits>
        <bits access="rw" name="pus_modu_sel_curr" pos="4:3" rst="0">
          <comment>bit type is changed from r/w to rw.
          00: BPSK
01: QPSK
10: 16QAM
11: 64QAM</comment>
        </bits>
        <bits access="rw" name="dft_en_curr" pos="2" rst="0">
          <comment>bit type is changed from r/w to rw.
          0DFT/IDFT
1DFT/IDFT</comment>
        </bits>
        <bits access="rw" name="pus_mod_en_curr" pos="1" rst="0">
          <comment>bit type is changed from r/w to rw.
          0PUSCH
1PUSCH</comment>
        </bits>
        <bits access="rw" name="dft_idft_sel_curr" pos="0" rst="0">
          <comment>bit type is changed from r/w to rw.
          0: DFT
1: IDFT</comment>
        </bits>
      </reg>
      <reg name="puc_mod_data_curr2" protect="rw">
        <bits access="rw" name="puc_mod_data_curr" pos="21:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          PUCCHd(n)</comment>
        </bits>
      </reg>
      <reg name="srs_map_cfg_curr2" protect="rw">
        <bits access="rw" name="k_tc_num_curr" pos="26" rst="0">
          <comment>SRS
021
143</comment>
        </bits>
        <bits access="rw" name="k_tc_curr" pos="25:24" rst="0">
          <comment>bit type is changed from r/w to rw.
000
011
102
113</comment>
        </bits>
        <bits access="rw" name="srs_map_len_curr" pos="22:16" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRS</comment>
        </bits>
        <bits access="rw" name="srs_map_start2_curr" pos="14:8" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRS</comment>
        </bits>
        <bits access="rw" name="srs_map_start1_curr" pos="6:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRS</comment>
        </bits>
      </reg>
      <reg name="srs_zc_len_curr2" protect="rw">
        <bits access="rw" name="srs_num_curr" pos="24" rst="0">
          <comment>0SRS1
1SRS2</comment>
        </bits>
        <bits access="rw" name="srs_map_ofdm2_curr" pos="23:20" rst="0">
          <comment>SRSOFDM</comment>
        </bits>
        <bits access="rw" name="sra_map_ofdm1_curr" pos="19:16" rst="0">
          <comment>SRSOFDM</comment>
        </bits>
        <bits access="rw" name="special_frame_start_curr" pos="15:12" rst="0">
          <comment>SRSOFDM</comment>
        </bits>
        <bits access="rw" name="srs_zc_len_curr" pos="10:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          SRSZC</comment>
        </bits>
      </reg>
      <reg name="puc_map_cfg_curr2" protect="rw">
        <bits access="rw" name="tx_fir_en_curr" pos="31" rst="0">
          <comment>0TX
1TX</comment>
        </bits>
        <bits access="rw" name="tx_nb_start2_curr" pos="30:24" rst="0">
          <comment>2</comment>
        </bits>
        <bits access="rw" name="tx_nb_start1_curr" pos="22:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="puc_map_start2_curr" pos="14:8" rst="0">
          <comment>PUCCH</comment>
        </bits>
        <bits access="rw" name="puc_map_start1_curr" pos="6:0" rst="0">
          <comment>PUCCH</comment>
        </bits>
      </reg>
      <reg name="pus_map_cfg_curr2" protect="rw">
        <bits access="rw" name="pus_map_sel_curr" pos="31" rst="0">
          <comment>PUSCH
00.5ms
11ms</comment>
        </bits>
        <bits access="rw" name="pus_map_len2_curr" pos="30:24" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="pus_map_len1_curr" pos="22:16" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="pus_map_start2_curr" pos="14:8" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="pus_map_start1_curr" pos="6:0" rst="0">
          <comment>PUSCH</comment>
        </bits>
      </reg>
      <reg name="hard_para_curr12" protect="rw">
        <bits access="rw" name="pucpus_shortened_mode_curr" pos="14:11" rst="0">
          <comment>PUSCH/PUCCH
0000normal
0001type0_shortend
0010type1_shortend
0011type2_shortend
0100type3_shortend
0101type4_shortend
0110type5_shortend
0111:  type6_shortend
1000:  type7_shortend
1001:  other</comment>
        </bits>
        <bits access="rw" name="group_hop_flag_curr" pos="10" rst="0">
          <comment>1u
0u</comment>
        </bits>
        <bits access="rw" name="seq_hop_flag_curr" pos="9" rst="0">
          <comment>1v
0v</comment>
        </bits>
        <bits access="rw" name="ta_overlap_curr" pos="8:3" rst="0">
          <comment>TA0~32</comment>
        </bits>
        <bits access="rw" name="cyclic_shift_field_curr" pos="2:0" rst="0">
          <comment>dmrsValue0~7</comment>
        </bits>
      </reg>
      <reg name="hard_para_curr22" protect="rw">
        <bits access="rw" name="delta_apc_srs_curr" pos="31:16" rst="0">
          <comment>SRSAPC</comment>
        </bits>
        <bits access="rw" name="delta_apc_scr_curr" pos="15:0" rst="0">
          <comment>PUSCH/PUCCH/PRACHAPC</comment>
        </bits>
      </reg>
      <reg name="hard_para_curr32" protect="rw">
        <bits access="rw" name="n1_pucch_curr" pos="31:20" rst="0">
          <comment>PUCCH1/1a/1b0~4095</comment>
        </bits>
        <bits access="rw" name="srs_cycle_shift_curr" pos="19:16" rst="0">
          <comment>SRS</comment>
        </bits>
        <bits access="rw" name="subframe_slot_cnt_curr" pos="14:10" rst="0">
          <comment>CAT1/CATM/CAT-NB15kHz1ms2CAT-NB3.75kHz2ms1</comment>
        </bits>
        <bits access="rw" name="nf_curr" pos="9:0" rst="0">
          <comment>0~1023</comment>
        </bits>
      </reg>
      <reg name="ofdm_offset_curr2" protect="rw">
        <bits access="rw" name="ofdm_offset_last_curr" pos="31:16" rst="0">
          <comment>OFDMoffset</comment>
        </bits>
        <bits access="rw" name="ofdm_offset_first_curr" pos="15:0" rst="0">
          <comment>OFDMoffset</comment>
        </bits>
      </reg>
      <reg name="dft_fft_inten_curr2" protect="rw">
        <bits access="rw" name="err_inten_curr" pos="15" rst="0">
          <comment>0ULDFTTXRXPUSCHERROR
1ULDFTTXRXPUSCHERROR</comment>
        </bits>
        <bits access="rw" name="dma_inten_curr" pos="14" rst="0">
          <comment>1AXIDMA
0AXIDMA</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten13_curr" pos="13" rst="0">
          <comment>1OFDM13
0OFDM13</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten12_curr" pos="12" rst="0">
          <comment>1OFDM12
0OFDM12</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten11_curr" pos="11" rst="0">
          <comment>1OFDM11
0OFDM11</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten10_curr" pos="10" rst="0">
          <comment>1OFDM10
0OFDM10</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten9_curr" pos="9" rst="0">
          <comment>1OFDM9
0OFDM9</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten8_curr" pos="8" rst="0">
          <comment>1OFDM8
0OFDM8</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten7_curr" pos="7" rst="0">
          <comment>1OFDM7
0OFDM7</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten6_curr" pos="6" rst="0">
          <comment>1OFDM6
0OFDM6</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten5_curr" pos="5" rst="0">
          <comment>1OFDM5
0OFDM5</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten4_curr" pos="4" rst="0">
          <comment>1OFDM4
0OFDM4</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten3_curr" pos="3" rst="0">
          <comment>1OFDM3
0OFDM3</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten2_curr" pos="2" rst="0">
          <comment>1OFDM2
0OFDM2</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten1_curr" pos="1" rst="0">
          <comment>1OFDM1
0OFDM1</comment>
        </bits>
        <bits access="rw" name="dft_fft_inten0_curr" pos="0" rst="0">
          <comment>1OFDM0
0OFDM0</comment>
        </bits>
      </reg>
      <reg name="ofdm_zero_curr2" protect="rw">
        <bits access="rw" name="ofdm_zero_curr" pos="13:0" rst="0">
          <comment>OFDM
14b0
14b10
14b1101
14b111012</comment>
        </bits>
      </reg>
      <reg name="dft_fft_ctrl_curr2" protect="rw">
        <bits access="rw" name="dftfft_soft_start" pos="30" rst="0">
          <comment>0ULDFT
1ULDFT</comment>
        </bits>
        <bits access="rw" name="dft_trig_mode" pos="29" rst="0">
          <comment>0ULDFT
1ULDFTPUSCH</comment>
        </bits>
        <bits access="rw" name="launch_en_curr" pos="28" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="srs_en_curr" pos="27" rst="0">
          <comment>0SRS
1SRS</comment>
        </bits>
        <bits access="rw" name="clear_en_curr" pos="26" rst="0">
          <comment>0FFTMEM
1FFTMEM</comment>
        </bits>
        <bits access="rw" name="fft_ifft_sel_curr" pos="25" rst="0">
          <comment>1IFFT
0FFT</comment>
        </bits>
        <bits access="rw" name="fft_cal_curr" pos="24" rst="0">
          <comment>1FFT/IFFT
0FFT/IFFT</comment>
        </bits>
        <bits access="rw" name="pwradj_en_curr" pos="23" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="prach_format_sel_curr" pos="22:20" rst="0">
          <comment>PRACH
000PRACH0
001PRACH1
010PRACH2
011PRACH3
100PRACH4</comment>
        </bits>
        <bits access="rw" name="pucch_format_sel_curr" pos="19:17" rst="0">
          <comment>PUCCH
000PUCCH1
001PUCCH1a
010PUCCH1b
011PUCCH2
100PUCCH2a
101PUCCH2b</comment>
        </bits>
        <bits access="rw" name="npusch_formatsel_curr" pos="16" rst="0">
          <comment>0NPUSCH format 1
1NPUSCH format2</comment>
        </bits>
        <bits access="rw" name="ofdm_num_curr" pos="15:12" rst="0">
          <comment>OFDM</comment>
        </bits>
        <bits access="rw" name="datadrive_en_curr" pos="10" rst="0">
          <comment>0DATADRIVE
1DATADRIVE</comment>
        </bits>
        <bits access="rw" name="pus_buf_sel_curr" pos="9:8" rst="0">
          <comment>UL_DFTPUSCH BUFFER
00PUSCH BUFFER1
01PUSCH BUFFER2
10PUSCH BUFFER3
11PUSCH PRA_BUF</comment>
        </bits>
        <bits access="rw" name="chan_mode_curr" pos="6:4" rst="0">
          <comment>000PUSCH
001PUCCH
010PRACH
011SRS
100NPUSCH
101NPRACH</comment>
        </bits>
        <bits access="rw" name="fft_npts" pos="3:1" rst="0">
          <comment>FFT/IFFT
111
110
101
1002048
0111024
010512
001256
000128</comment>
        </bits>
        <bits access="rw" name="dftfft_irqen_curr" pos="0" rst="0">
          <comment>0:
1:</comment>
        </bits>
      </reg>
      <reg name="fft_lnum_srs_curr2" protect="rw">
        <bits access="rw" name="fft_lnum11_srs_curr" pos="21:20" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum10_srs_curr" pos="19:18" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum9_srs_curr" pos="17:16" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum8_srs_curr" pos="15:14" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum7_srs_curr" pos="13:12" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum6_srs_curr" pos="11:10" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum5_srs_curr" pos="9:8" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum4_srs_curr" pos="7:6" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum3_srs_curr" pos="5:4" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum2_srs_curr" pos="3:2" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum1_srs_curr" pos="1:0" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
      </reg>
      <reg name="fft_lnum_scr_curr2" protect="rw">
        <bits access="rw" name="fft_lnum11_scr_curr" pos="21:20" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum10_scr_curr" pos="19:18" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum9_scr_curr" pos="17:16" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum8_scr_curr" pos="15:14" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum7_scr_curr" pos="13:12" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum6_scr_curr" pos="11:10" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum5_scr_curr" pos="9:8" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum4_scr_curr" pos="7:6" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum3_scr_curr" pos="5:4" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum2_scr_curr" pos="3:2" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
        <bits access="rw" name="fft_lnum1_scr_curr" pos="1:0" rst="0">
          <comment>FFT
2b0025~14bit
2b0126~15bit
2b1027~16bit
2b1128~17bit</comment>
        </bits>
      </reg>
      <reg name="npus_map_cfg_curr2" protect="rw">
        <bits access="rw" name="npus_rep_cnt_curr" pos="23:17" rst="0">
          <comment>NPUSCH0~127</comment>
        </bits>
        <bits access="rw" name="n_ru_sc_curr" pos="16:15" rst="0">
          <comment>001
013
106
1112</comment>
        </bits>
        <bits access="rw" name="isc_start_index_curr" pos="14:9" rst="0">
          <comment>NPUSCH 0~47</comment>
        </bits>
        <bits access="rw" name="n_slot_cnt_curr" pos="8:1" rst="0">
          <comment>Nslots1~160</comment>
        </bits>
        <bits access="rw" name="npus_sub_space_curr" pos="0" rst="0">
          <comment>0: 3.75KHz
1: 15KHz</comment>
        </bits>
      </reg>
      <reg name="npus_dmrs_cfg_curr2" protect="rw">
        <bits access="rw" name="first_ru_slot_curr" pos="26:22" rst="0">
          <comment>RU0~19</comment>
        </bits>
        <bits access="rw" name="slot_n_curr" pos="21:7" rst="0">
          <comment>1DMRS0~20480</comment>
        </bits>
        <bits access="rw" name="base_seq_curr" pos="6:2" rst="0">
          <comment>BASE_SEQ_CURR0~30</comment>
        </bits>
        <bits access="rw" name="cyclic_shift_curr" pos="1:0" rst="0">
          <comment>CYCLIC_SHIFT0~3</comment>
        </bits>
      </reg>
      <reg name="npra_cfg_curr2" protect="rw">
        <bits access="rw" name="sym_group_rep_cnt_curr" pos="16:9" rst="0">
          <comment>t0~128</comment>
        </bits>
        <bits access="rw" name="nprach_sc_offset_curr" pos="8:6" rst="0">
          <comment>frequency location of the first sub-carrier allocated to NPRACH
000frequency location0
001frequency location2
010frequency location12
011frequency location18
100frequency location24
101frequency location34
110frequency location36
1110</comment>
        </bits>
        <bits access="rw" name="init_sc_curr" pos="5:0" rst="0">
          <comment>being the subcarrier selected by the MAC layer from  0-47</comment>
        </bits>
      </reg>
      <reg name="fsm_state" protect="r">
        <bits access="r" name="ocp_pi" pos="31" rst="0">
          <comment>TXRX PING
1
0</comment>
        </bits>
        <bits access="r" name="ocp_pa" pos="30" rst="0">
          <comment>TXRX PANG
1
0</comment>
        </bits>
        <bits access="r" name="frame_state" pos="29:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="ofdm_state" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="ofdm_count" protect="r">
        <bits access="r" name="ofdm_count_ofdm_count" pos="3:0" rst="0">
          <comment>OFDM0~13</comment>
        </bits>
      </reg>
      <reg name="fsm_state_assert" protect="r">
        <bits access="r" name="ocp_pi_assert" pos="31" rst="0">
          <comment>ASSERT TXRX PING
1
0</comment>
        </bits>
        <bits access="r" name="ocp_pa_assert" pos="30" rst="0">
          <comment>ASSERT TXRX PANG
1
0</comment>
        </bits>
        <bits access="r" name="frame_state_assert" pos="29:16" rst="0">
          <comment>ASSERT</comment>
        </bits>
        <bits access="r" name="ofdm_state_assert" pos="15:0" rst="0">
          <comment>ASSERT</comment>
        </bits>
      </reg>
      <reg name="ofdm_assert" protect="r">
        <bits access="r" name="ofdm_assert_ofdm_assert" pos="3:0" rst="0">
          <comment>ASSERT OFDM0~13</comment>
        </bits>
      </reg>
      <hole size="30624"/>
      <reg name="uldft_mem1" protect="rw">
        <bits access="rw" name="uldft_mem1_uldft_mem1" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="uldft_mem2" protect="rw">
        <bits access="rw" name="uldft_mem2_uldft_mem2" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="uldft_mem3" protect="rw">
        <bits access="rw" name="uldft_mem3_uldft_mem3" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="uldft_mem4" protect="rw">
        <bits access="rw" name="uldft_mem4_uldft_mem4" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="uldft_mem5" protect="rw">
        <bits access="rw" name="uldft_mem5_uldft_mem5" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="uldft_mem6" protect="rw">
        <bits access="rw" name="uldft_mem6_uldft_mem6" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="uldft_mem7" protect="rw">
        <bits access="rw" name="uldft_mem7_uldft_mem7" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="uldft_mem8" protect="rw">
        <bits access="rw" name="uldft_mem8_uldft_mem8" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="8160"/>
      <reg name="uldft_mem9" protect="rw">
        <bits access="rw" name="uldft_mem9_uldft_mem9" pos="31:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_txrx.xml">
    <module category="LTE_SYS" name="CP_LTE_TXRX">
      <reg name="int_flag" protect="rw">
        <bits access="rc" name="tx_trace_fin" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          TRACE
0
1</comment>
        </bits>
        <bits access="rc" name="rx_trace_fin" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          TRACE
0
1</comment>
        </bits>
        <bits access="rc" name="tx_fin" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
        <bits access="rc" name="tx_ofdm" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
        <bits access="rc" name="rx_fin" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
        <bits access="rc" name="rx_ofdm" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
      </reg>
      <reg name="int_mask" protect="rw">
        <bits access="rw" name="tx_trace_fin" pos="5" rst="0">
          <comment>TRACE
0
1</comment>
        </bits>
        <bits access="rw" name="rx_trace_fin" pos="4" rst="0">
          <comment>TRACE
0
1</comment>
        </bits>
        <bits access="rw" name="tx_finish_mask" pos="3" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="tx_ofdm_mask" pos="2" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="rx_finish_mask" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="rx_ofdm_mask" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="int_flag_ofdm_rx" protect="rw">
        <bits access="rc" name="rx_ofdm_int_14" pos="14" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM14
1OFDM14</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_13" pos="13" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM13
1OFDM13</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_12" pos="12" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM12
1OFDM12</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_11" pos="11" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM11
1OFDM11</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_10" pos="10" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM10
1OFDM10</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_9" pos="9" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM9
1OFDM9</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_8" pos="8" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM8
1OFDM8</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_7" pos="7" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM7
1OFDM7</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_6" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM6
1OFDM6</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_5" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM5
1OFDM5</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_4" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM4
1OFDM4</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_3" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM3
1OFDM3</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_2" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM2
1OFDM2</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_1" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM1
1OFDM1</comment>
        </bits>
        <bits access="rc" name="rx_ofdm_int_0" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          0OFDM0
1OFDM0</comment>
        </bits>
      </reg>
      <reg name="int_mask_ofdm_rx" protect="rw">
        <bits access="rw" name="rx_inten" pos="16" rst="0">
          <comment>1
0
1</comment>
        </bits>
        <bits access="rw" name="rx_last_int_en" pos="15" rst="0">
          <comment>0OFDM
1OFDM</comment>
        </bits>
        <bits access="rw" name="rx_int_en14" pos="14" rst="0">
          <comment>0OFDM14
1OFDM14</comment>
        </bits>
        <bits access="rw" name="rx_int_en13" pos="13" rst="0">
          <comment>0OFDM13
1OFDM13</comment>
        </bits>
        <bits access="rw" name="rx_int_en12" pos="12" rst="0">
          <comment>0OFDM12
1OFDM12</comment>
        </bits>
        <bits access="rw" name="rx_int_en11" pos="11" rst="0">
          <comment>0OFDM11
1OFDM11</comment>
        </bits>
        <bits access="rw" name="rx_int_en10" pos="10" rst="0">
          <comment>0OFDM10
1OFDM10</comment>
        </bits>
        <bits access="rw" name="rx_int_en9" pos="9" rst="0">
          <comment>0OFDM9
1OFDM9</comment>
        </bits>
        <bits access="rw" name="rx_int_en8" pos="8" rst="0">
          <comment>0OFDM8
1OFDM8</comment>
        </bits>
        <bits access="rw" name="rx_int_en7" pos="7" rst="0">
          <comment>0OFDM7
1OFDM7</comment>
        </bits>
        <bits access="rw" name="rx_int_en6" pos="6" rst="0">
          <comment>0OFDM6
1OFDM6</comment>
        </bits>
        <bits access="rw" name="rx_int_en5" pos="5" rst="0">
          <comment>0OFDM5
1OFDM5</comment>
        </bits>
        <bits access="rw" name="rx_int_en4" pos="4" rst="0">
          <comment>0OFDM4
1OFDM4</comment>
        </bits>
        <bits access="rw" name="rx_int_en3" pos="3" rst="0">
          <comment>0OFDM3
1OFDM3</comment>
        </bits>
        <bits access="rw" name="rx_int_en2" pos="2" rst="0">
          <comment>0OFDM2
1OFDM2</comment>
        </bits>
        <bits access="rw" name="rx_int_en1" pos="1" rst="0">
          <comment>0OFDM1
1OFDM1</comment>
        </bits>
        <bits access="rw" name="rx_int_en0" pos="0" rst="0">
          <comment>0OFDM0
1OFDM0</comment>
        </bits>
      </reg>
      <reg name="sys_cfg" protect="rw">
        <bits access="rw" name="rx_dcoc_sel" pos="5" rst="0">
          <comment>DCOC
1
0</comment>
        </bits>
        <bits access="rw" name="rx_ovt" pos="4" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="tx_ovt" pos="3" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="tx_dfe_en" pos="2" rst="0">
          <comment>DFE
0DFE
1DFE</comment>
        </bits>
        <bits access="rw" name="tx_nb_en" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="cat1_en" pos="0" rst="0">
          <comment>CAT1
0CAT1
1CAT1</comment>
        </bits>
      </reg>
      <reg name="stop_cfg" protect="rw">
        <bits access="rw" name="tx_stop_en" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="rx_stop_en" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="rx_cfg" protect="rw">
        <bits access="rw" name="rx_soft_afc_en" pos="31" rst="0">
          <comment>SOFT AFC
0
1</comment>
        </bits>
        <bits access="rw" name="rx_rssi_cfg" pos="30" rst="0">
          <comment>RSSI
1data
0data</comment>
        </bits>
        <bits access="rw" name="rssi_save_sel" pos="27:25" rst="0">
          <comment>RSSI
0: RSSI_MAX1
1: RSSI_MAX2
2: RSSI_MAX3
3: RSSI_MAX4
4: RSSI_MAX5
Other:</comment>
        </bits>
        <bits access="rw" name="rx_hf_fir_en" pos="23" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="rx_otdoa_en" pos="22" rst="0">
          <comment>OTDOA
1
0</comment>
        </bits>
        <bits access="rw" name="offset_ctrl_flag" pos="21" rst="0">
          <comment>offset
1RXoffsetcp
0offset</comment>
        </bits>
        <bits access="rw" name="rx_iddet_en" pos="19" rst="0">
          <comment>1IDDET
0IDDET</comment>
        </bits>
        <bits access="rw" name="rx_dlfft_en" pos="18" rst="0">
          <comment>DLFFT DATA_DRIVE
0
1</comment>
        </bits>
        <bits access="rw" name="rx_cp_type" pos="17:16" rst="0">
          <comment>00CP
01CP
10CPIDDET</comment>
        </bits>
        <bits access="rw" name="hf_firbitsel" pos="11:8" rst="0">
          <comment>FIR
4h033-22
4h132-21
4h231-20
4h330-19
4h429-18
4h528-17
4h627-16
4h726-15
4h825-14
4h924-13
4ha23-12
4hb22-11
4hc21-10
4hd20-9
4he19-8
4hf18-7</comment>
        </bits>
        <bits access="rw" name="rx_trace_en" pos="7" rst="0">
          <comment>TRACE
1
0</comment>
        </bits>
        <bits access="rw" name="offset_zero_flag" pos="6" rst="0">
          <comment>0measpwr/dlfft offset
10
0offsetoffset_ctrl_flag</comment>
        </bits>
        <bits access="rw" name="rx_meas_en" pos="5" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="rx_norm_en" pos="4" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="rx_ave_en" pos="3" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="rx_sat_en" pos="2" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="rx_rssi_en" pos="1" rst="0">
          <comment>RSSI
1
0</comment>
        </bits>
        <bits access="rw" name="glb_rxen" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="rx_1st_ofdm_len_offset" protect="rw">
        <bits access="rw" name="rx_ist_ofdm_len_offset" pos="9:0" rst="0">
          <comment>OFDM</comment>
        </bits>
      </reg>
      <reg name="rx_afc_factor" protect="rw">
        <bits access="rw" name="rx_afc_update" pos="16" rst="0">
          <comment>AFC
1
0</comment>
        </bits>
        <bits access="rw" name="rx_afc_factor_rx_afc_factor" pos="15:0" rst="0">
          <comment>AFC
10hz</comment>
        </bits>
      </reg>
      <reg name="rx_rssi_max_cfg" protect="rw">
        <bits access="rw" name="next_en" pos="5" rst="0">
          <comment>1
0
AD_ON0</comment>
        </bits>
        <bits access="rw" name="rssi_max_clear" pos="4" rst="0">
          <comment>RSSI0
1
0</comment>
        </bits>
        <bits access="rw" name="rssi_max_start" pos="3:0" rst="0">
          <comment>RSSI</comment>
        </bits>
      </reg>
      <reg name="rx_norm_cfg" protect="rw">
        <bits access="rw" name="rx_norm_cfg_rx_norm_cfg" pos="2:0" rst="1">
          <comment>1~5</comment>
        </bits>
      </reg>
      <reg name="rx_sat_val" protect="rw">
        <bits access="rw" name="sat_val_max" pos="27:16" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="sat_val_min" pos="11:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="rx_pre_cfg" protect="rw">
        <bits access="rw" name="rx_freq_factor" pos="22:12" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="rx_bw_sel" pos="10:8" rst="0">
          <comment>3h5: 20M       (1/16)
3h4: 15M       (1/16)
3h3: 10M       (1/8)
3h2: 5M        (1/4)
3h1: 3M        (1/2)
3h0: 1.4M
Other:</comment>
        </bits>
        <bits access="rw" name="freq_en" pos="7" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="fir_en" pos="6" rst="0">
          <comment>FIR
1
0</comment>
        </bits>
        <bits access="rw" name="rx_bitsel" pos="4:0" rst="8">
          <comment>FIR
5b0000034-23
5b0000133-22
5b0001032-21
5b0001131-20
5b0010030-19
5b0010129-18
5b0011028-17
5b0011127-16
5b0100026-15
5b0100125-14
5b0101024-13
5b0101123-12
5b0110022-11
5b0110121-10
5b0111020-9
5b0111119-8
5b1000018-7
5b1000117-6
5b1001016-5
Other</comment>
        </bits>
      </reg>
      <reg name="rx_aux_cfg" protect="rw">
        <bits access="rw" name="rx_aux" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="rx_phy_factor" protect="rw">
        <bits access="rw" name="rx_phy_factor_rx_phy_factor" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="rx_dc_cfg" protect="rw">
        <bits access="rw" name="rx_dc_update" pos="31" rst="0">
          <comment>DCOC
0
1</comment>
        </bits>
        <bits access="rw" name="rx_dc_i" pos="27:16" rst="0">
          <comment>I</comment>
        </bits>
        <bits access="rw" name="rx_dc_q" pos="11:0" rst="0">
          <comment>Q</comment>
        </bits>
      </reg>
      <reg name="rx_gain1_cfg" protect="rw">
        <bits access="rw" name="rx_gain1_en" pos="16" rst="0">
          <comment>GAIN1
0
1</comment>
        </bits>
        <bits access="rw" name="rx_gain1" pos="9:0" rst="0">
          <comment>GAIN1</comment>
        </bits>
      </reg>
      <reg name="rx_gain2_cfg" protect="rw">
        <bits access="rw" name="rx_gain2_en" pos="16" rst="0">
          <comment>GAIN2
0
1</comment>
        </bits>
        <bits access="rw" name="rx_gain2" pos="9:0" rst="0">
          <comment>GAIN2</comment>
        </bits>
      </reg>
      <reg name="rx_out_cfg" protect="rw">
        <bits access="rw" name="iddet_dat_start" pos="21:20" rst="3">
          <comment>IDDET
2h0:bit7
2'h1:bit8
2h2:bit9
2'h3:bit10</comment>
        </bits>
        <bits access="rw" name="iddet_dat_fin" pos="18:16" rst="0">
          <comment>IDDET
3h0:bit0
3'h1:bit1
3h2:bit2
3'h3:bit3
3h4:bit4
other:reserved</comment>
        </bits>
        <bits access="rw" name="otdoa_dat_start" pos="13:12" rst="3">
          <comment>OTDOA
2h0:bit7
2'h1:bit8
2h2:bit9
2'h3:bit10</comment>
        </bits>
        <bits access="rw" name="otdoa_dat_fin" pos="10:8" rst="0">
          <comment>OTDOA
3h0:bit0
3'h1:bit1
3h2:bit2
3'h3:bit3
3h4:bit4
other:reserved</comment>
        </bits>
        <bits access="rw" name="meas_dat_start" pos="5:4" rst="3">
          <comment>MEASPWR
2h0:bit7
2'h1:bit8
2h2:bit9
2'h3:bit10</comment>
        </bits>
        <bits access="rw" name="meas_dat_fin" pos="2:0" rst="0">
          <comment>MEASPWR
3h0:bit0
3'h1:bit1
3h2:bit2
3'h3:bit3
3h4:bit4
other:reserved</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="tx_cfg" protect="rw">
        <bits access="rw" name="tx_loop" pos="4" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="tx_data_drive" pos="3" rst="0">
          <comment>DATA_DRIVE
0
1</comment>
        </bits>
        <bits access="rw" name="tx_cp_type" pos="2" rst="0">
          <comment>1CP
0CP</comment>
        </bits>
        <bits access="rw" name="glb_txen" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="tx_1st_ofdm_len_offset" protect="rw">
        <bits access="rw" name="tx_1st_ofdm_len_offset_tx_1st_ofdm_len_offset" pos="6:0" rst="0">
          <comment>OFDM(-32~31)</comment>
        </bits>
      </reg>
      <reg name="tx_ofdm0_len" protect="rw">
        <bits access="rw" name="tx_ofdm0_len_tx_ofdm0_len" pos="11:0" rst="137">
          <comment>PINGCP0</comment>
        </bits>
      </reg>
      <reg name="tx_ofdm1_len" protect="rw">
        <bits access="rw" name="tx_ofdm1_len_tx_ofdm1_len" pos="11:0" rst="136">
          <comment>PANGCP0</comment>
        </bits>
      </reg>
      <reg name="tx_post_cfg" protect="rw">
        <bits access="r" name="prach_en" pos="23" rst="0">
          <comment>PRACH
1
0
DFT</comment>
        </bits>
        <bits access="r" name="prach_format" pos="22:20" rst="0">
          <comment>PRACH
3hxxx0~4
DFT</comment>
        </bits>
        <bits access="r" name="tx_nb_start" pos="18:12" rst="0">
          <comment>NB
DFT</comment>
        </bits>
        <bits access="r" name="tx_fir_en" pos="11" rst="0">
          <comment>1
0
DFT</comment>
        </bits>
        <bits access="rw" name="tx_bw_sel" pos="10:8" rst="0">
          <comment>3h5: 20M       (16)
3h4: 15M       (16)
3h3: 10M       (8)
3h2: 5M        (4)
3h1: 3M        (2)
3h0: 1.4M
Other:</comment>
        </bits>
        <bits access="rw" name="tx_freq_en" pos="7" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="tx_bitsel" pos="4:0" rst="8">
          <comment>FIR
5b0000034-23
5b0000133-22
5b0001032-21
5b0001131-20
5b0010030-19
5b0010129-18
5b0011028-17
5b0011127-16
5b0100026-15
5b0100125-14
5b0101024-13
5b0101123-12
5b0110022-11
5b0110121-10
5b0111020-9
5b0111119-8
5b1000018-7
5b1000117-6
5b1001016-5
Other</comment>
        </bits>
      </reg>
      <reg name="tx_fill0_num" protect="rw">
        <bits access="rw" name="tx_fill0_num_tx_fill0_num" pos="7:0" rst="0">
          <comment>0
8hff : 255
8hfe: 254
8h01: 1
8h00: 0</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="rx_phy_factor_cur" protect="r">
        <bits access="r" name="rx_phy_factor_cur_rx_phy_factor_cur" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="rx_sat_cnt" protect="r">
        <bits access="r" name="sat_cnt" pos="31:0" rst="0">
          <comment>32h0:0
32h1:1
?????????</comment>
        </bits>
      </reg>
      <reg name="rx_norm_data" protect="r">
        <bits access="r" name="rx_norm_data_rx_norm_data" pos="3:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="rssi_max1" protect="r">
        <bits access="r" name="rssi_max1_rssi_max1" pos="31:0" rst="0">
          <comment>RSSI</comment>
        </bits>
      </reg>
      <reg name="rssi_max2" protect="r">
        <bits access="r" name="rssi_max2_rssi_max2" pos="31:0" rst="0">
          <comment>RSSI</comment>
        </bits>
      </reg>
      <reg name="rssi_max3" protect="r">
        <bits access="r" name="rssi_max3_rssi_max3" pos="31:0" rst="0">
          <comment>RSSI</comment>
        </bits>
      </reg>
      <reg name="rssi_max4" protect="r">
        <bits access="r" name="rssi_max4_rssi_max4" pos="31:0" rst="0">
          <comment>RSSI</comment>
        </bits>
      </reg>
      <reg name="rssi_max5" protect="r">
        <bits access="r" name="rssi_max5_rssi_max5" pos="31:0" rst="0">
          <comment>RSSI</comment>
        </bits>
      </reg>
      <reg name="rx_dc_cal_value" protect="r">
        <bits access="r" name="rx_dc_cal_value_i" pos="31:16" rst="0">
          <comment>I</comment>
        </bits>
        <bits access="r" name="rx_dc_cal_value_q" pos="15:0" rst="0">
          <comment>Q</comment>
        </bits>
      </reg>
      <hole size="224"/>
      <reg name="rx_ofdm_stat" protect="r">
        <bits access="r" name="rx_mem_addr" pos="27:16" rst="0">
          <comment>RX_MEM</comment>
        </bits>
        <bits access="r" name="ad_on" pos="13" rst="0">
          <comment>AD_ON</comment>
        </bits>
        <bits access="r" name="rx_running" pos="12" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="r" name="rx_dlfft_en" pos="11" rst="0">
          <comment>DLFFT</comment>
        </bits>
        <bits access="r" name="rx_otdoa_en" pos="10" rst="0">
          <comment>OTDOA</comment>
        </bits>
        <bits access="r" name="rx_iddet_en" pos="9" rst="0">
          <comment>IDDET</comment>
        </bits>
        <bits access="r" name="rx_meas_en" pos="8" rst="0">
          <comment>MEAS</comment>
        </bits>
        <bits access="r" name="cp_err" pos="7" rst="0">
          <comment>CP
0
1</comment>
        </bits>
        <bits access="r" name="rx_no_data_err" pos="6" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="r" name="ping_pang_stat" pos="4" rst="0">
          <comment>PING_PANG</comment>
        </bits>
        <bits access="r" name="rx_ofdm_stat_rx_ofdm_stat" pos="3:0" rst="0">
          <comment>OFDM</comment>
        </bits>
      </reg>
      <reg name="tx_fifo_stat" protect="r">
        <bits access="r" name="tx_mem_addr" pos="27:16" rst="0">
          <comment>TX_MEM</comment>
        </bits>
        <bits access="r" name="da_on" pos="13" rst="0">
          <comment>DA_ON</comment>
        </bits>
        <bits access="r" name="tx_running" pos="12" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="r" name="tx_fifo_stat_tx_fifo_stat" pos="4" rst="0">
          <comment>FIFO
0ping
1pang</comment>
        </bits>
        <bits access="r" name="tx_ofdm_stat" pos="3:0" rst="0">
          <comment>OFDM</comment>
        </bits>
      </reg>
      <reg name="rx_err_stat" protect="r">
        <bits access="r" name="frame_num" pos="31:28" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="ts_cnt" pos="27:12" rst="0">
          <comment>TS</comment>
        </bits>
        <bits access="r" name="ofdm_num_rx" pos="11:8" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="ad_on" pos="5" rst="0">
          <comment>AD_ON</comment>
        </bits>
        <bits access="r" name="rx_running" pos="4" rst="0">
          <comment>01</comment>
        </bits>
        <bits access="r" name="dlfft_mem_sel" pos="3" rst="0">
          <comment>mem</comment>
        </bits>
        <bits access="r" name="pingpang_flag" pos="2" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="cp_type_rx" pos="1:0" rst="0">
          <comment>CP</comment>
        </bits>
      </reg>
      <reg name="tx_err_stat" protect="r">
        <bits access="r" name="frame_num" pos="31:28" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="ts_cnt" pos="27:12" rst="0">
          <comment>TS</comment>
        </bits>
        <bits access="r" name="ofdm_num_tx" pos="11:8" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="da_on" pos="6" rst="0">
          <comment>DA_ON</comment>
        </bits>
        <bits access="r" name="tx_running" pos="5" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="r" name="ram_pi_sel" pos="4" rst="0">
          <comment>PING RAM</comment>
        </bits>
        <bits access="r" name="dft_wr_pi_err" pos="3" rst="0">
          <comment>DFTPING</comment>
        </bits>
        <bits access="r" name="dft_wr_pa_err" pos="2" rst="0">
          <comment>DFTPANG</comment>
        </bits>
        <bits access="r" name="pi_empty_err" pos="1" rst="0">
          <comment>PING</comment>
        </bits>
        <bits access="r" name="pa_empty_err" pos="0" rst="0">
          <comment>PANG</comment>
        </bits>
      </reg>
      <reg name="st_cnt_framc" protect="r">
        <bits access="r" name="adon_pos_framc" pos="31:16" rst="0">
          <comment>ADONFRAMC</comment>
        </bits>
        <bits access="r" name="rf_1st_int_framc" pos="15:0" rst="0">
          <comment>FRAMC</comment>
        </bits>
      </reg>
      <reg name="st_cnt_add" protect="r">
        <bits access="r" name="rf_int_num" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="rf_int_sub_add" pos="15:0" rst="0">
          <comment>FRAMC</comment>
        </bits>
      </reg>
      <reg name="ad_on_time" protect="r">
        <bits access="r" name="ad_on_neg_time1" pos="31:24" rst="0">
          <comment>AD_ON</comment>
        </bits>
        <bits access="r" name="ad_on_pos_time1" pos="23:16" rst="0">
          <comment>AD_ON</comment>
        </bits>
        <bits access="r" name="ad_on_neg_time0" pos="15:8" rst="0">
          <comment>AD_ON</comment>
        </bits>
        <bits access="r" name="ad_on_pos_time0" pos="7:0" rst="0">
          <comment>AD_ON</comment>
        </bits>
      </reg>
      <reg name="da_on_time" protect="r">
        <bits access="r" name="da_on_neg_time1" pos="31:24" rst="0">
          <comment>DA_ON</comment>
        </bits>
        <bits access="r" name="da_on_pos_time1" pos="23:16" rst="0">
          <comment>DA_ON</comment>
        </bits>
        <bits access="r" name="da_on_neg_time0" pos="15:8" rst="0">
          <comment>DA_ON</comment>
        </bits>
        <bits access="r" name="da_on_pos_time0" pos="7:0" rst="0">
          <comment>DA_ON</comment>
        </bits>
      </reg>
      <reg name="fftbuf1_time" protect="r">
        <bits access="r" name="fftbuf1_time4" pos="31:24" rst="0">
          <comment>4FFTBUF1</comment>
        </bits>
        <bits access="r" name="fftbuf1_time3" pos="23:16" rst="0">
          <comment>3FFTBUF1</comment>
        </bits>
        <bits access="r" name="fftbuf1_time2" pos="15:8" rst="0">
          <comment>2FFTBUF1</comment>
        </bits>
        <bits access="r" name="fftbuf1_time1" pos="7:0" rst="0">
          <comment>1FFTBUF1</comment>
        </bits>
      </reg>
      <reg name="fftbuf2_time" protect="r">
        <bits access="r" name="fftbuf2_time4" pos="31:24" rst="0">
          <comment>4FFTBUF2</comment>
        </bits>
        <bits access="r" name="fftbuf2_time3" pos="23:16" rst="0">
          <comment>3FFTBUF2</comment>
        </bits>
        <bits access="r" name="fftbuf2_time2" pos="15:8" rst="0">
          <comment>2FFTBUF2</comment>
        </bits>
        <bits access="r" name="fftbuf2_time1" pos="7:0" rst="0">
          <comment>1FFTBUF2</comment>
        </bits>
      </reg>
      <reg name="fft2ldtc_time" protect="r">
        <bits access="r" name="fft2ldtc_time4" pos="31:24" rst="0">
          <comment>4FFT2LDTC</comment>
        </bits>
        <bits access="r" name="fft2ldtc_time3" pos="23:16" rst="0">
          <comment>3FFT2LDTC</comment>
        </bits>
        <bits access="r" name="fft2ldtc_time2" pos="15:8" rst="0">
          <comment>2FFT2LDTC</comment>
        </bits>
        <bits access="r" name="fft2ldtc_time1" pos="7:0" rst="0">
          <comment>1FFT2LDTC</comment>
        </bits>
      </reg>
      <hole size="522432"/>
      <reg name="mem1" protect="rw">
        <bits access="rw" name="mem1_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="mem1_2" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="mem2" protect="rw">
        <bits access="rw" name="mem2_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="mem2_2" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="98240"/>
      <reg name="mem5" protect="rw">
        <bits access="rw" name="mem5_mem5" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32768"/>
      <reg name="mem3" protect="rw">
        <bits access="rw" name="mem3_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="mem3_2" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="mem4" protect="rw">
        <bits access="rw" name="mem4_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="mem4_2" pos="15:4" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_measpwr.xml">
    <module category="LTE_SYS" name="CP_LTE_MEASPWR">
      <reg name="measpwr_rxdata_ctrl1" protect="rw">
        <bits access="rw" name="fdd_tdd" pos="31" rst="1">
          <comment>FDD_TDD
0FDD
1TDD</comment>
        </bits>
        <bits access="rw" name="rx_offset1" pos="18:0" rst="0">
          <comment>TXRXAD_ON
0~30720*10-110ms(AD ON)</comment>
        </bits>
      </reg>
      <reg name="measpwr_rxdata_ctrl2" protect="rw">
        <bits access="rw" name="rx_len" pos="15:0" rst="0">
          <comment>MEASPWR1~30720*6(6ms)</comment>
        </bits>
      </reg>
      <reg name="measpwr_rxdata_val_ctrl" protect="rw">
        <bits access="w" name="invalid_flag" pos="20" rst="0">
          <comment>Offset2
0offset2
1offset2</comment>
        </bits>
        <bits access="rw" name="rx_offset2" pos="17:0" rst="0">
          <comment>MEASPWR 0~30720*6-1</comment>
        </bits>
      </reg>
      <reg name="measpwr_rxdata_offset3_id1" protect="rw">
        <bits access="rw" name="rx_offset3_id1" pos="19:0" rst="0">
          <comment>ID1 (0~30720*10-1)</comment>
        </bits>
      </reg>
      <reg name="measpwr_rxdata_offset3_id2" protect="rw">
        <bits access="rw" name="rx_offset3_id2" pos="19:0" rst="0">
          <comment>ID2 (0~30720*10-1)</comment>
        </bits>
      </reg>
      <reg name="measpwr_rxdata_offset3_id3" protect="rw">
        <bits access="rw" name="rx_offset3_id3" pos="19:0" rst="0">
          <comment>s</comment>
        </bits>
      </reg>
      <reg name="measpwr_rxdata_offset3_id4" protect="rw">
        <bits access="rw" name="rx_offset3_id4" pos="19:0" rst="0">
          <comment>ID4 (0~30720*10-1)</comment>
        </bits>
      </reg>
      <reg name="measpwr_rxdata_offset3_id5" protect="rw">
        <bits access="rw" name="rx_offset3_id5" pos="19:0" rst="0">
          <comment>ID5 (0~30720*10-1)</comment>
        </bits>
      </reg>
      <reg name="measpwr_rxdata_offset3_id6" protect="rw">
        <bits access="rw" name="rx_offset3_id6" pos="19:0" rst="0">
          <comment>ID6 (0~30720*10-1)</comment>
        </bits>
      </reg>
      <reg name="measpwr_rxdata_offset3_id7" protect="rw">
        <bits access="rw" name="rx_offset3_id7" pos="19:0" rst="0">
          <comment>ID7 (0~30720*10-1)</comment>
        </bits>
      </reg>
      <reg name="measpwr_rxdata_offset3_id8" protect="rw">
        <bits access="rw" name="rx_offset3_id8" pos="19:0" rst="0">
          <comment>ID8 (0~30720*10-1)</comment>
        </bits>
      </reg>
      <reg name="measpwr_nb_offset4" protect="rw">
        <bits access="rw" name="nb_offet4" pos="14:0" rst="0">
          <comment>Nboffset4</comment>
        </bits>
      </reg>
      <reg name="measpwr_total_subf" protect="rw">
        <bits access="rw" name="totalsubf_num_id3_8" pos="20:12" rst="0">
          <comment>ID3~ID8
01
12
23
511:512</comment>
        </bits>
        <bits access="rw" name="totalsubf_num_id1_2" pos="8:0" rst="0">
          <comment>ID1ID2
01
12
23
511:512</comment>
        </bits>
      </reg>
      <reg name="measpwr_ifft_para" protect="rw">
        <bits access="rw" name="ifft_cut7" pos="13:12" rst="0">
          <comment>IFFT</comment>
        </bits>
        <bits access="rw" name="ifft_cut6" pos="11:10" rst="0">
          <comment>IFFT</comment>
        </bits>
        <bits access="rw" name="ifft_cut5" pos="9:8" rst="0">
          <comment>IFFT</comment>
        </bits>
        <bits access="rw" name="ifft_cut4" pos="7:6" rst="0">
          <comment>IFFT</comment>
        </bits>
        <bits access="rw" name="ifft_cut3" pos="5:4" rst="0">
          <comment>IFFT</comment>
        </bits>
        <bits access="rw" name="ifft_cut2" pos="3:2" rst="0">
          <comment>IFFT</comment>
        </bits>
        <bits access="rw" name="ifft_cut1" pos="1:0" rst="0">
          <comment>IFFT
2b00:bit[25:14]
2b01:bit[26:15]
2b10:bit[27:16]
2b11:bit[28:17]</comment>
        </bits>
      </reg>
      <reg name="measpwr_ifft_gate" protect="rw">
        <bits access="rw" name="ifft_gate" pos="6:0" rst="0">
          <comment>IFFT</comment>
        </bits>
      </reg>
      <reg name="measpwr_int_en" protect="rw">
        <bits access="rw" name="id8_interrupt_enable" pos="31:28" rst="0">
          <comment>ID8 10
bit[28]
bit[29]
bit[30]AFC
bit[31]:agc_compare</comment>
        </bits>
        <bits access="rw" name="id7_interrupt_enable" pos="27:24" rst="0">
          <comment>ID7 10
bit[24]
bit[25]
bit[26]AFC
bit[27]:agc_compare</comment>
        </bits>
        <bits access="rw" name="id6_interrupt_enable" pos="23:20" rst="0">
          <comment>ID6 10
bit[20]
bit[21]
bit[22]AFC
bit[23]:agc_compare</comment>
        </bits>
        <bits access="rw" name="id5_interrupt_enable" pos="19:16" rst="0">
          <comment>ID5 10
bit[16]
bit[17]
bit[18]AFC
bit[19]:agc_compare</comment>
        </bits>
        <bits access="rw" name="id4_interrupt_enable" pos="15:12" rst="0">
          <comment>ID4 10
bit[12]
bit[13]
bit[14]AFC
bit[15]:agc_compare</comment>
        </bits>
        <bits access="rw" name="id3_interrupt_enable" pos="11:8" rst="0">
          <comment>ID3 10
bit[8]
bit[9]
bit[10]AFC
bit[11]:agc_compare</comment>
        </bits>
        <bits access="rw" name="id2_interrupt_enable" pos="7:4" rst="0">
          <comment>ID2 10
bit[4]
bit[5]
bit[6]AFC
bit[7]:agc_compare</comment>
        </bits>
        <bits access="rw" name="id1_interrupt_enable" pos="3:0" rst="0">
          <comment>ID1 10
bit[0]
bit[1]
bit[2]AFC
bit[3]:agc_compare</comment>
        </bits>
      </reg>
      <reg name="measpwr_int_sta" protect="rw">
        <bits access="rc" name="id8_interrupt_state" pos="31:28" rst="0">
          <comment>bit type is changed from r1c to rc.
          ID8 10
bit[28]
bit[29]
bit[30]AFC
bit[31]:agc_compare</comment>
        </bits>
        <bits access="rc" name="id7_interrupt_state" pos="27:24" rst="0">
          <comment>bit type is changed from r1c to rc.
          ID7 10
bit[24]
bit[25]
bit[26]AFC
bit[27]:agc_compare</comment>
        </bits>
        <bits access="rc" name="id6_interrupt_state" pos="23:20" rst="0">
          <comment>bit type is changed from r1c to rc.
          ID6 10
bit[20]
bit[21]
bit[22]AFC
bit[23]:agc_compare</comment>
        </bits>
        <bits access="rc" name="id5_interrupt_state" pos="19:16" rst="0">
          <comment>bit type is changed from r1c to rc.
          ID5 10
bit[16]
bit[17]
bit[18]AFC
bit[19]:agc_compare</comment>
        </bits>
        <bits access="rc" name="id4_interrupt_state" pos="15:12" rst="0">
          <comment>bit type is changed from r1c to rc.
          ID4 10
bit[12]
bit[13]
bit[14]AFC
bit[15]:agc_compare</comment>
        </bits>
        <bits access="rc" name="id3_interrupt_state" pos="11:8" rst="0">
          <comment>bit type is changed from r1c to rc.
          ID3 10
bit[8]
bit[9]
bit[10]AFC
bit[11]:agc_compare</comment>
        </bits>
        <bits access="rc" name="id2_interrupt_state" pos="7:4" rst="0">
          <comment>bit type is changed from r1c to rc.
          ID2 10
bit[4]
bit[5]
bit[6]AFC
bit[7]:agc_compare</comment>
        </bits>
        <bits access="rc" name="id1_interrupt_state" pos="3:0" rst="0">
          <comment>bit type is changed from r1c to rc.
          ID1 10
bit[0]
bit[1]
bit[2]AFC
bit[3]:agc_compare</comment>
        </bits>
      </reg>
      <reg name="measpwr_id1_id2_func_ctrl" protect="rw">
        <bits access="rw" name="id1_id2_trmsf_en" pos="8" rst="0">
          <comment>TRMS</comment>
        </bits>
        <bits access="rw" name="id1_id2_sigma_en" pos="7" rst="0">
          <comment>SIGMA</comment>
        </bits>
        <bits access="rw" name="id1_id2_doppler_en" pos="6" rst="0">
          <comment>DOPPLER</comment>
        </bits>
        <bits access="rw" name="id1_id2_sinr_en" pos="5" rst="0">
          <comment>SINR</comment>
        </bits>
        <bits access="rw" name="id1_id2_afc_com_en" pos="4" rst="0">
          <comment>AFC</comment>
        </bits>
        <bits access="rw" name="id1_id2_afc_hst_en" pos="3" rst="0">
          <comment>AFC</comment>
        </bits>
        <bits access="rw" name="id1_id2_trms_en" pos="2" rst="0">
          <comment>TRMS</comment>
        </bits>
        <bits access="rw" name="id1_id2_rsrp_en" pos="1" rst="0">
          <comment>RSRP</comment>
        </bits>
        <bits access="rw" name="id1_id2_irt_en" pos="0" rst="0">
          <comment>IRT</comment>
        </bits>
      </reg>
      <reg name="measpwr_id3_id8_func_ctrl" protect="rw">
        <bits access="rw" name="id3_id8_trmsf_en" pos="8" rst="0">
          <comment>TRMS</comment>
        </bits>
        <bits access="rw" name="id3_id8_sigma_en" pos="7" rst="0">
          <comment>SIGMA</comment>
        </bits>
        <bits access="rw" name="id3_id8_doppler_en" pos="6" rst="0">
          <comment>DOPPLER</comment>
        </bits>
        <bits access="rw" name="id3_id8_sinr_en" pos="5" rst="0">
          <comment>SINR</comment>
        </bits>
        <bits access="rw" name="id3_id8_afc_com_en" pos="4" rst="0">
          <comment>AFC</comment>
        </bits>
        <bits access="rw" name="id3_id8_afc_hst_en" pos="3" rst="0">
          <comment>AFC</comment>
        </bits>
        <bits access="rw" name="id3_id8_trms_en" pos="2" rst="0">
          <comment>TRMS</comment>
        </bits>
        <bits access="rw" name="id3_id8_rsrp_en" pos="1" rst="0">
          <comment>RSRP</comment>
        </bits>
        <bits access="rw" name="id3_id8_irt_en" pos="0" rst="0">
          <comment>IRT</comment>
        </bits>
      </reg>
      <reg name="measpwr_agc_compare" protect="rw">
        <bits access="rw" name="agc_compare" pos="9:0" rst="511">
          <comment>agcagcagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_nb_para" protect="rw">
        <bits access="rw" name="id38_nb_ind" pos="11:8" rst="0">
          <comment>ID3-80-15CATM</comment>
        </bits>
        <bits access="rw" name="id2_nb_ind" pos="7:4" rst="0">
          <comment>ID20-15CATM</comment>
        </bits>
        <bits access="rw" name="id1_nb_ind" pos="3:0" rst="0">
          <comment>ID10-15CATM</comment>
        </bits>
      </reg>
      <reg name="measpwr_band_para" protect="rw">
        <bits access="rw" name="meas_bw_id38" pos="14:12" rst="0">
          <comment>ID3-8
01.4m
13m
25m
310m
415m
520m</comment>
        </bits>
        <bits access="rw" name="sys_bw_id38" pos="10:8" rst="0">
          <comment>ID3-8
01.4m
13m
25m
310m
415m
520m</comment>
        </bits>
        <bits access="rw" name="meas_bw_id12" pos="6:4" rst="0">
          <comment>ID1-2
01.4m
13m
25m
310m
415m
520m</comment>
        </bits>
        <bits access="rw" name="sys_bw_id12" pos="2:0" rst="0">
          <comment>ID1-2
01.4m
13m
25m
310m
415m
520m</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="measpwr_afc_para" protect="rw">
        <bits access="rw" name="afc_factor" pos="23:8" rst="0">
          <comment>Afc_factor</comment>
        </bits>
        <bits access="rw" name="afc_related_flag" pos="4" rst="0">
          <comment>AFC
0
1
4</comment>
        </bits>
        <bits access="rw" name="afc_renum" pos="2:0" rst="0">
          <comment>AFC
0001
0012
0103
0114
1006
10112
Other:1</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc_soft_reect1" protect="rw">
        <bits access="rw" name="afc_soft_fa_ctor1" pos="15:0" rst="0">
          <comment>ID1 AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr_para" protect="rw">
        <bits access="rw" name="sigpwr_alpha" pos="28:12" rst="0">
          <comment>SIGPWR alpha</comment>
        </bits>
        <bits access="rw" name="sigpwr_ofdmnum" pos="9:8" rst="0">
          <comment>SIGPWR
001
012
114
Other1</comment>
        </bits>
        <bits access="rw" name="sigpwr_renum" pos="7:0" rst="0">
          <comment>ID1-2 SIGPWR(</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma_para" protect="rw">
        <bits access="rw" name="sigma_alpha" pos="24:8" rst="0">
          <comment>SIGMA alpha</comment>
        </bits>
        <bits access="rw" name="sigma_win" pos="6:0" rst="0">
          <comment>SIGMA1~80</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler_para" protect="rw">
        <bits access="rw" name="doppler_alpha1" pos="29:13" rst="0">
          <comment>Id1-2 Doppler alpha</comment>
        </bits>
        <bits access="rw" name="doppler_scale" pos="11:8" rst="0">
          <comment>Doppler_scaleQ12</comment>
        </bits>
        <bits access="rw" name="doppler_win" pos="6:0" rst="0">
          <comment>DOPPLER1~80</comment>
        </bits>
      </reg>
      <reg name="measpwr_trms_para1" protect="rw">
        <bits access="rw" name="t_th" pos="23:16" rst="0">
          <comment>Trms8q0</comment>
        </bits>
        <bits access="rw" name="noise_sel" pos="12" rst="0">
          <comment>0TRMSDis_Limit
1RSRPDis_Limit</comment>
        </bits>
        <bits access="rw" name="d_flag2" pos="9" rst="0">
          <comment>ID3-8:
0:1L_U16ExtractStepTab_true1
11L_U16ExtractStepTab_true</comment>
        </bits>
        <bits access="rw" name="d_flag" pos="8" rst="0">
          <comment>ID1-2:
0:1L_U16ExtractStepTab_true1
11L_U16ExtractStepTab_true</comment>
        </bits>
        <bits access="rw" name="dis_limit" pos="7:0" rst="0">
          <comment>(N2N+1)</comment>
        </bits>
      </reg>
      <reg name="measpwr_trms_para2" protect="rw">
        <bits access="rw" name="s_th" pos="31:16" rst="0">
          <comment>ID1-216q15</comment>
        </bits>
        <bits access="rw" name="n_th" pos="15:0" rst="0">
          <comment>ID1-216q10</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp_para1" protect="rw">
        <bits access="rw" name="d_flag2" pos="25" rst="1">
          <comment>ID3-8</comment>
        </bits>
        <bits access="rw" name="d_flag" pos="24" rst="1">
          <comment>ID1-2</comment>
        </bits>
        <bits access="rw" name="beta" pos="23:8" rst="0">
          <comment>ID1-2beta16Q10</comment>
        </bits>
        <bits access="rw" name="dis_limit" pos="7:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_rsrp_para2" protect="rw">
        <bits access="rw" name="mode1_compensate2" pos="25:17" rst="0">
          <comment>ID3-8RSRP</comment>
        </bits>
        <bits access="rw" name="mode1_compensate" pos="16:8" rst="0">
          <comment>ID1-2RSRP</comment>
        </bits>
        <bits access="rw" name="rsrp_agcadjust" pos="7:0" rst="0">
          <comment>L_S32RsrpdB_Temp = L_S32RsrpdB  - AGC_Base*16 - RSRPAgcAdjust*16 + L_U16DownSamplingCompensate*16</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp_para3" protect="rw">
        <bits access="rw" name="s_th" pos="23:8" rst="0">
          <comment>ID1-2</comment>
        </bits>
        <bits access="rw" name="rssi_q" pos="6:0" rst="0">
          <comment>RSSI Q()</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp_para4" protect="rw">
        <bits access="rw" name="powq_value" pos="15:8" rst="0">
          <comment>FFTIFFTQ</comment>
        </bits>
        <bits access="rw" name="pow_pa" pos="7:0" rst="0">
          <comment>FFTIFFT</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_para1" protect="rw">
        <bits access="rw" name="val_sel" pos="20" rst="0">
          <comment>IRT
08910
1</comment>
        </bits>
        <bits access="rw" name="pow_max_num" pos="19:16" rst="0">
          <comment>pow</comment>
        </bits>
        <bits access="rw" name="n_scale" pos="15:12" rst="0">
          <comment>Scale</comment>
        </bits>
        <bits access="rw" name="dis_limit" pos="11:4" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="irt_ofdm_num" pos="1:0" rst="0">
          <comment>IRT
001
012
114</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_para2" protect="rw">
        <bits access="rw" name="s_th" pos="31:16" rst="0">
          <comment>ID1-2</comment>
        </bits>
        <bits access="rw" name="n_th" pos="15:0" rst="0">
          <comment>ID1-216q10</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale_th1" protect="rw">
        <bits access="rw" name="scaleth_1" pos="31:0" rst="0">
          <comment>1ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale_th2" protect="rw">
        <bits access="rw" name="scaleth_2" pos="31:0" rst="0">
          <comment>2ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale_th4" protect="rw">
        <bits access="rw" name="scaleth_4" pos="31:0" rst="0">
          <comment>4ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale_th8" protect="rw">
        <bits access="rw" name="scaleth_8" pos="31:0" rst="0">
          <comment>8ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale_th16" protect="rw">
        <bits access="rw" name="scaleth_16" pos="31:0" rst="0">
          <comment>16ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale_th32" protect="rw">
        <bits access="rw" name="scaleth_32" pos="31:0" rst="0">
          <comment>32ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale_th64" protect="rw">
        <bits access="rw" name="scaleth_64" pos="31:0" rst="0">
          <comment>64ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale_th128" protect="rw">
        <bits access="rw" name="scaleth_128" pos="31:0" rst="0">
          <comment>128ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale_th256" protect="rw">
        <bits access="rw" name="scaleth_256" pos="31:0" rst="0">
          <comment>256ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale_th512" protect="rw">
        <bits access="rw" name="scaleth_512" pos="31:0" rst="0">
          <comment>512ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi_para" protect="rw">
        <bits access="rw" name="rssi_compensate2" pos="19:12" rst="0">
          <comment>ID3-8 Rssi</comment>
        </bits>
        <bits access="rw" name="rssi_compensate" pos="11:4" rst="0">
          <comment>ID1-2 Rssi</comment>
        </bits>
        <bits access="rw" name="rssi_sel" pos="0" rst="1">
          <comment>IDRSSI
0MEASPWROFDMRSSI
1MEASPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_agc" protect="rw">
        <bits access="rw" name="agc_rx" pos="9:0" rst="0">
          <comment>AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_id1_para1" protect="rw">
        <bits access="rw" name="lnum_mod" pos="31:28" rst="0">
          <comment>FFT
4`b0000
4`b0001
4`b0010
.</comment>
        </bits>
        <bits access="rw" name="offline0_time" pos="27:24" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="afc_out_num" pos="23:16" rst="0">
          <comment>AFC</comment>
        </bits>
        <bits access="rw" name="crs_rssi_sel" pos="15:14" rst="0">
          <comment>Crs_rssi
00
01
10
11reserved</comment>
        </bits>
        <bits access="rw" name="firstd_ofdm_flag" pos="13" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="nid" pos="12:4" rst="0">
          <comment>NID 0~503</comment>
        </bits>
        <bits access="rw" name="tx_flag" pos="3" rst="0">
          <comment>2port
0port 0 and port 1
1only port 1</comment>
        </bits>
        <bits access="rw" name="afc_out_sel" pos="2" rst="0">
          <comment>AFC
0IRT
1bit[8:1]</comment>
        </bits>
        <bits access="rw" name="tx_num" pos="1" rst="0">
          <comment>01
12</comment>
        </bits>
        <bits access="rw" name="cp_index" pos="0" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="measpwr_id1_para2" protect="rw">
        <bits access="rw" name="qf_mem_sel" pos="31" rst="0">
          <comment>Hmmse QF mem
0QF mem
1QF mem</comment>
        </bits>
        <bits access="rw" name="irt_scale_disable" pos="30" rst="0">
          <comment>IRT scale
0
1</comment>
        </bits>
        <bits access="rw" name="pow_data_sel" pos="29:28" rst="0">
          <comment>AFC\POW
00hls
01hmmse
10freqfirst
11hls</comment>
        </bits>
        <bits access="rw" name="crs_rssi_clr" pos="26" rst="0">
          <comment>Crs_rssi</comment>
        </bits>
        <bits access="rw" name="frame_map" pos="25:16" rst="0">
          <comment>bit[25:16]9-0</comment>
        </bits>
        <bits access="rw" name="offline0_step" pos="15:7" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="sinr_map" pos="6:4" rst="0">
          <comment>SINR
000NASINR
0011
0102
0113
1004
OtherNA</comment>
        </bits>
        <bits access="rw" name="afcrelateden" pos="3" rst="0">
          <comment>AFC
0
1</comment>
        </bits>
        <bits access="rw" name="last_flag" pos="2" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="windows_clr" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="restart" pos="0" rst="0">
          <comment>0
1
1</comment>
        </bits>
      </reg>
      <reg name="measpwr_id2_para1" protect="rw">
        <bits access="rw" name="lnum_mod" pos="31:28" rst="0">
          <comment>FFT
4`b0000
4`b0001
4`b0010
.</comment>
        </bits>
        <bits access="rw" name="offline0_time" pos="27:24" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="afc_out_num" pos="23:16" rst="0">
          <comment>AFC</comment>
        </bits>
        <bits access="rw" name="crs_rssi_sel" pos="15:14" rst="0">
          <comment>Crs_rssi
00
01
10
11reserved</comment>
        </bits>
        <bits access="rw" name="firstd_ofdm_flag" pos="13" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="nid" pos="12:4" rst="0">
          <comment>NID 0~503</comment>
        </bits>
        <bits access="rw" name="tx_flag" pos="3" rst="0">
          <comment>2port
0port 0 and port 1
1only port 1</comment>
        </bits>
        <bits access="rw" name="afc_out_sel" pos="2" rst="0">
          <comment>AFC
0IRT
1bit[8:1]</comment>
        </bits>
        <bits access="rw" name="tx_num" pos="1" rst="0">
          <comment>01
12</comment>
        </bits>
        <bits access="rw" name="cp_index" pos="0" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="measpwr_id2_para2" protect="rw">
        <bits access="rw" name="qf_mem_sel" pos="31" rst="0">
          <comment>Hmmse QF mem
0QF mem
1QF mem</comment>
        </bits>
        <bits access="rw" name="irt_scale_disable" pos="30" rst="0">
          <comment>IRT scale
0
1</comment>
        </bits>
        <bits access="rw" name="pow_data_sel" pos="29:28" rst="0">
          <comment>AFC\POW
00hls
01hmmse
10freqfirst
11hls</comment>
        </bits>
        <bits access="rw" name="crs_rssi_clr" pos="26" rst="0">
          <comment>Crs_rssi</comment>
        </bits>
        <bits access="rw" name="frame_map" pos="25:16" rst="0">
          <comment>bit[25:16]9-0</comment>
        </bits>
        <bits access="rw" name="offline0_step" pos="15:7" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="r" name="reserve2" pos="6:4" rst="0">
      </bits>
        <bits access="rw" name="afcrelateden" pos="3" rst="0">
          <comment>AFC
0
1</comment>
        </bits>
        <bits access="rw" name="last_flag" pos="2" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="windows_clr" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="restart" pos="0" rst="0">
          <comment>0
1
1</comment>
        </bits>
      </reg>
      <reg name="measpwr_id3_para1" protect="rw">
        <bits access="rw" name="lnum_mod" pos="27:24" rst="0">
          <comment>FFT
4`b0000
4`b0001
4`b0010
.</comment>
        </bits>
        <bits access="rw" name="offline0_time" pos="23:20" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="firstd_ofdm_flag" pos="17" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="nid" pos="16:8" rst="0">
          <comment>NID 0~503</comment>
        </bits>
        <bits access="rw" name="tx_flag" pos="6" rst="0">
          <comment>2port
0port 0 and port 1
1only port 1</comment>
        </bits>
        <bits access="rw" name="tx_num" pos="5" rst="0">
          <comment>01
12</comment>
        </bits>
        <bits access="rw" name="cp_index" pos="4" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="rw" name="crs_rssi_clr" pos="3" rst="0">
          <comment>Crs_rssi</comment>
        </bits>
        <bits access="rw" name="last_flag" pos="2" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="windows_clr" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="restart" pos="0" rst="0">
          <comment>0
1
1</comment>
        </bits>
      </reg>
      <reg name="measpwr_id4_para1" protect="rw">
        <bits access="rw" name="lnum_mod" pos="27:24" rst="0">
          <comment>FFT
4`b0000
4`b0001
4`b0010
.</comment>
        </bits>
        <bits access="rw" name="offline0_time" pos="23:20" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="firstd_ofdm_flag" pos="17" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="nid" pos="16:8" rst="0">
          <comment>NID 0~503</comment>
        </bits>
        <bits access="rw" name="tx_flag" pos="6" rst="0">
          <comment>2port
0port 0 and port 1
1only port 1</comment>
        </bits>
        <bits access="rw" name="tx_num" pos="5" rst="0">
          <comment>01
12</comment>
        </bits>
        <bits access="rw" name="cp_index" pos="4" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="rw" name="crs_rssi_clr" pos="3" rst="0">
          <comment>Crs_rssi</comment>
        </bits>
        <bits access="rw" name="last_flag" pos="2" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="windows_clr" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="restart" pos="0" rst="0">
          <comment>0
1
1</comment>
        </bits>
      </reg>
      <reg name="measpwr_id5_para1" protect="rw">
        <bits access="rw" name="lnum_mod" pos="27:24" rst="0">
          <comment>FFT
4`b0000
4`b0001
4`b0010
.</comment>
        </bits>
        <bits access="rw" name="offline0_time" pos="23:20" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="firstd_ofdm_flag" pos="17" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="nid" pos="16:8" rst="0">
          <comment>NID 0~503</comment>
        </bits>
        <bits access="rw" name="tx_flag" pos="6" rst="0">
          <comment>2port
0port 0 and port 1
1only port 1</comment>
        </bits>
        <bits access="rw" name="tx_num" pos="5" rst="0">
          <comment>01
12</comment>
        </bits>
        <bits access="rw" name="cp_index" pos="4" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="rw" name="crs_rssi_clr" pos="3" rst="0">
          <comment>Crs_rssi</comment>
        </bits>
        <bits access="rw" name="last_flag" pos="2" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="windows_clr" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="restart" pos="0" rst="0">
          <comment>0
1
1</comment>
        </bits>
      </reg>
      <reg name="measpwr_id6_para1" protect="rw">
        <bits access="rw" name="lnum_mod" pos="27:24" rst="0">
          <comment>FFT
4`b0000
4`b0001
4`b0010
.</comment>
        </bits>
        <bits access="rw" name="offline0_time" pos="23:20" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="firstd_ofdm_flag" pos="17" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="nid" pos="16:8" rst="0">
          <comment>NID 0~503</comment>
        </bits>
        <bits access="rw" name="tx_flag" pos="6" rst="0">
          <comment>2port
0port 0 and port 1
1only port 1</comment>
        </bits>
        <bits access="rw" name="tx_num" pos="5" rst="0">
          <comment>01
12</comment>
        </bits>
        <bits access="rw" name="cp_index" pos="4" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="rw" name="crs_rssi_clr" pos="3" rst="0">
          <comment>Crs_rssi</comment>
        </bits>
        <bits access="rw" name="last_flag" pos="2" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="windows_clr" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="restart" pos="0" rst="0">
          <comment>0
1
1</comment>
        </bits>
      </reg>
      <reg name="measpwr_id7_para1" protect="rw">
        <bits access="rw" name="lnum_mod" pos="27:24" rst="0">
          <comment>FFT
4`b0000
4`b0001
4`b0010
.</comment>
        </bits>
        <bits access="rw" name="offline0_time" pos="23:20" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="firstd_ofdm_flag" pos="17" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="nid" pos="16:8" rst="0">
          <comment>NID 0~503</comment>
        </bits>
        <bits access="rw" name="tx_flag" pos="6" rst="0">
          <comment>2port
0port 0 and port 1
1only port 1</comment>
        </bits>
        <bits access="rw" name="tx_num" pos="5" rst="0">
          <comment>01
12</comment>
        </bits>
        <bits access="rw" name="cp_index" pos="4" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="rw" name="crs_rssi_clr" pos="3" rst="0">
          <comment>Crs_rssi</comment>
        </bits>
        <bits access="rw" name="last_flag" pos="2" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="windows_clr" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="restart" pos="0" rst="0">
          <comment>0
1
1</comment>
        </bits>
      </reg>
      <reg name="measpwr_id8_para1" protect="rw">
        <bits access="rw" name="lnum_mod" pos="27:24" rst="0">
          <comment>FFT
4`b0000
4`b0001
4`b0010
.</comment>
        </bits>
        <bits access="rw" name="offline0_time" pos="23:20" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="firstd_ofdm_flag" pos="17" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="nid" pos="16:8" rst="0">
          <comment>NID 0~503</comment>
        </bits>
        <bits access="rw" name="tx_flag" pos="6" rst="0">
          <comment>2port
0port 0 and port 1
1only port 1</comment>
        </bits>
        <bits access="rw" name="tx_num" pos="5" rst="0">
          <comment>01
12</comment>
        </bits>
        <bits access="rw" name="cp_index" pos="4" rst="0">
          <comment>CP
0CP
1CP</comment>
        </bits>
        <bits access="rw" name="crs_rssi_clr" pos="3" rst="0">
          <comment>Crs_rssi</comment>
        </bits>
        <bits access="rw" name="last_flag" pos="2" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="windows_clr" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="restart" pos="0" rst="0">
          <comment>0
1
1</comment>
        </bits>
      </reg>
      <reg name="measpwr_id_para" protect="rw">
        <bits access="rw" name="offline_mod_sel" pos="28" rst="0">
          <comment>Offline
00
11</comment>
        </bits>
        <bits access="rw" name="offlin_data_sel" pos="24" rst="0">
          <comment>offline
0
1</comment>
        </bits>
        <bits access="rw" name="nid12_info" pos="19:4" rst="0">
          <comment>NID1-2</comment>
        </bits>
        <bits access="rw" name="irt_soft_en" pos="3" rst="0">
          <comment>IRT
0
1</comment>
        </bits>
        <bits access="rw" name="afc_soft_en" pos="2" rst="0">
          <comment>AFC
0
1</comment>
        </bits>
        <bits access="rw" name="mode_sel" pos="1:0" rst="0">
          <comment>0CATM
1CAT1
2NB
NB_LTEFFT</comment>
        </bits>
      </reg>
      <reg name="measpwr_id_ctrl" protect="rw">
        <bits access="rs" name="invalid_flag" pos="29" rst="0">
          <comment>bit type is changed from r1s to rs.
          NID_MAP
0
1</comment>
        </bits>
        <bits access="rs" name="nid38_info" pos="28:19" rst="0">
          <comment>bit type is changed from r1s to rs.
          NID3-8</comment>
        </bits>
        <bits access="rs" name="offline_sel" pos="8" rst="0">
          <comment>bit type is changed from r1s to rs.
          Offlineonline
0online
1offline</comment>
        </bits>
        <bits access="rs" name="nid8" pos="7" rst="0">
          <comment>bit type is changed from r1s to rs.
          ID1
0</comment>
        </bits>
        <bits access="rs" name="nid7" pos="6" rst="0">
          <comment>bit type is changed from r1s to rs.
          ID1
0</comment>
        </bits>
        <bits access="rs" name="nid6" pos="5" rst="0">
          <comment>bit type is changed from r1s to rs.
          ID1
0</comment>
        </bits>
        <bits access="rs" name="nid5" pos="4" rst="0">
          <comment>bit type is changed from r1s to rs.
          ID1
0</comment>
        </bits>
        <bits access="rs" name="nid4" pos="3" rst="0">
          <comment>bit type is changed from r1s to rs.
          ID1
0</comment>
        </bits>
        <bits access="rs" name="nid3" pos="2" rst="0">
          <comment>bit type is changed from r1s to rs.
          ID1
0</comment>
        </bits>
        <bits access="rs" name="nid2" pos="1" rst="0">
          <comment>bit type is changed from r1s to rs.
          ID1
0</comment>
        </bits>
        <bits access="rs" name="nid1" pos="0" rst="0">
          <comment>bit type is changed from r1s to rs.
          ID1
0</comment>
        </bits>
      </reg>
      <reg name="measpwr_ctrl" protect="rw">
        <bits access="rs" name="nid8_en" pos="7" rst="0">
          <comment>bit type is changed from rw1s to rs.
          NID8</comment>
        </bits>
        <bits access="rs" name="nid7_en" pos="6" rst="0">
          <comment>bit type is changed from rw1s to rs.
          NID7</comment>
        </bits>
        <bits access="rs" name="nid6_en" pos="5" rst="0">
          <comment>bit type is changed from rw1s to rs.
          NID6</comment>
        </bits>
        <bits access="rs" name="nid5_en" pos="4" rst="0">
          <comment>bit type is changed from rw1s to rs.
          NID5</comment>
        </bits>
        <bits access="rs" name="nid4_en" pos="3" rst="0">
          <comment>bit type is changed from rw1s to rs.
          NID4</comment>
        </bits>
        <bits access="rs" name="nid3_en" pos="2" rst="0">
          <comment>bit type is changed from rw1s to rs.
          NID3</comment>
        </bits>
        <bits access="rs" name="nid2_en" pos="1" rst="0">
          <comment>bit type is changed from rw1s to rs.
          NID2</comment>
        </bits>
        <bits access="rs" name="nid1_en" pos="0" rst="0">
          <comment>bit type is changed from rw1s to rs.
          NID1</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc1_out" protect="r">
        <bits access="r" name="afc_out1" pos="15:0" rst="0">
          <comment>AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc2_out" protect="r">
        <bits access="r" name="afc_out2" pos="15:0" rst="0">
          <comment>AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc3_out" protect="r">
        <bits access="r" name="afc_out3" pos="15:0" rst="0">
          <comment>AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc4_out" protect="r">
        <bits access="r" name="afc_out4" pos="15:0" rst="0">
          <comment>AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc5_out" protect="r">
        <bits access="r" name="afc_out5" pos="15:0" rst="0">
          <comment>AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc1_rsrp" protect="r">
        <bits access="r" name="afc_rsrp1" pos="15:0" rst="0">
          <comment>AFCRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc2_rsrp" protect="r">
        <bits access="r" name="afc_rsrp2" pos="15:0" rst="0">
          <comment>AFCRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc3_rsrp" protect="r">
        <bits access="r" name="afc_rsrp3" pos="15:0" rst="0">
          <comment>AFCRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc4_rsrp" protect="r">
        <bits access="r" name="afc_rsrp4" pos="15:0" rst="0">
          <comment>AFCRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc5_rsrp" protect="r">
        <bits access="r" name="afc_rsrp5" pos="15:0" rst="0">
          <comment>AFCRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr1_out1" protect="r">
        <bits access="r" name="sigpwr1_out1" pos="31:0" rst="0">
          <comment>1SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr1_out2" protect="r">
        <bits access="r" name="sigpwr1_out2" pos="31:0" rst="0">
          <comment>2SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr1_out3" protect="r">
        <bits access="r" name="sigpwr1_out3" pos="31:0" rst="0">
          <comment>3SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr1_out4" protect="r">
        <bits access="r" name="sigpwr1_out4" pos="31:0" rst="0">
          <comment>4SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr1_out5" protect="r">
        <bits access="r" name="sigpwr1_out5" pos="31:0" rst="0">
          <comment>5SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr1_out6" protect="r">
        <bits access="r" name="sigpwr1_out6" pos="31:0" rst="0">
          <comment>6SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr2_out" protect="r">
        <bits access="r" name="sigpwr2_out" pos="31:0" rst="0">
          <comment>ID2SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr3_out" protect="r">
        <bits access="r" name="sigpwr3_out" pos="31:0" rst="0">
          <comment>ID3SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr4_out4" protect="r">
        <bits access="r" name="sigpwr4_out" pos="31:0" rst="0">
          <comment>ID4SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr5_out5" protect="r">
        <bits access="r" name="sigpwr5_out" pos="31:0" rst="0">
          <comment>ID5SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_out1" protect="r">
        <bits access="r" name="sigma1_out1" pos="31:0" rst="0">
          <comment>1SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_agc_out1" protect="r">
        <bits access="r" name="sinr1_log_out1" pos="26:16" rst="0">
          <comment>1SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc1_out1" pos="9:0" rst="0">
          <comment>1SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_out2" protect="r">
        <bits access="r" name="sigma1_out2" pos="31:0" rst="0">
          <comment>2SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_agc_out2" protect="r">
        <bits access="r" name="sinr1_log_out2" pos="26:16" rst="0">
          <comment>2SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc1_out2" pos="9:0" rst="0">
          <comment>2SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_out3" protect="r">
        <bits access="r" name="sigma1_out3" pos="31:0" rst="0">
          <comment>3SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_agc_out3" protect="r">
        <bits access="r" name="sinr1_log_out3" pos="26:16" rst="0">
          <comment>3SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc1_out3" pos="9:0" rst="0">
          <comment>3SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_out4" protect="r">
        <bits access="r" name="sigma1_out4" pos="31:0" rst="0">
          <comment>4SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_agc_out4" protect="r">
        <bits access="r" name="sinr1_log_out4" pos="26:16" rst="0">
          <comment>4SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc1_out4" pos="9:0" rst="0">
          <comment>4SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_out5" protect="r">
        <bits access="r" name="sigma1_out5" pos="31:0" rst="0">
          <comment>SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_agc_out5" protect="r">
        <bits access="r" name="sinr1_log_out5" pos="26:16" rst="0">
          <comment>5SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc1_out5" pos="9:0" rst="0">
          <comment>SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_out6" protect="r">
        <bits access="r" name="sigma1_out6" pos="31:0" rst="0">
          <comment>ID1SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_agc_out6" protect="r">
        <bits access="r" name="sinr1_log_out6" pos="26:16" rst="0">
          <comment>6SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc1_out6" pos="9:0" rst="0">
          <comment>ID1SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma2_out" protect="r">
        <bits access="r" name="sigma2_out" pos="31:0" rst="0">
          <comment>ID2SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma2_agc_out" protect="r">
        <bits access="r" name="sinr2_log_out" pos="26:16" rst="0">
          <comment>ID2SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc2_out" pos="9:0" rst="0">
          <comment>ID2SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma3_out" protect="r">
        <bits access="r" name="sigma3_out" pos="31:0" rst="0">
          <comment>ID3SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma3_agc_out" protect="r">
        <bits access="r" name="sinr3_log_out" pos="26:16" rst="0">
          <comment>ID3SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc3_out" pos="9:0" rst="0">
          <comment>ID3SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma4_out" protect="r">
        <bits access="r" name="sigma4_out" pos="31:0" rst="0">
          <comment>ID4SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma4_agc_out" protect="r">
        <bits access="r" name="sinr4_log_out" pos="26:16" rst="0">
          <comment>ID4SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc4_out" pos="9:0" rst="0">
          <comment>ID4SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma5_out" protect="r">
        <bits access="r" name="sigma5_out" pos="31:0" rst="0">
          <comment>ID5SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma5_agc_out" protect="r">
        <bits access="r" name="sinr5_log_out" pos="26:16" rst="0">
          <comment>ID5SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc5_out" pos="9:0" rst="0">
          <comment>ID5SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr1_out1" protect="r">
        <bits access="r" name="sinr1_out1" pos="31:0" rst="0">
          <comment>1SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr1_out2" protect="r">
        <bits access="r" name="sinr1_out2" pos="31:0" rst="0">
          <comment>2SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr1_out3" protect="r">
        <bits access="r" name="sinr1_out3" pos="31:0" rst="0">
          <comment>3SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr1_out4" protect="r">
        <bits access="r" name="sinr1_out4" pos="31:0" rst="0">
          <comment>4SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr1_out5" protect="r">
        <bits access="r" name="sinr1_out5" pos="31:0" rst="0">
          <comment>SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr1_out6" protect="r">
        <bits access="r" name="sinr1_out" pos="31:0" rst="0">
          <comment>ID1SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr2_out" protect="r">
        <bits access="r" name="sinr2_out" pos="31:0" rst="0">
          <comment>ID2SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr3_out" protect="r">
        <bits access="r" name="sinr3_out" pos="31:0" rst="0">
          <comment>ID3SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr4_out" protect="r">
        <bits access="r" name="sinr4_out" pos="31:0" rst="0">
          <comment>ID4SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr5_out" protect="r">
        <bits access="r" name="sinr5_out" pos="31:0" rst="0">
          <comment>ID5SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler1_out" protect="r">
        <bits access="r" name="hls_agc_base1" pos="25:16" rst="0">
          <comment>hls_agc_base</comment>
        </bits>
        <bits access="r" name="doppler1_out" pos="10:0" rst="0">
          <comment>DOPPLER</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler2_out" protect="r">
        <bits access="r" name="hls_agc_base2" pos="25:16" rst="0">
          <comment>hls_agc_base</comment>
        </bits>
        <bits access="r" name="doppler2_out" pos="10:0" rst="0">
          <comment>DOPPLER</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp1_out" protect="r">
        <bits access="r" name="rsrp_liner" pos="31:0" rst="0">
          <comment>RSRP</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp1_db" protect="r">
        <bits access="r" name="rsrp_pwr_db" pos="15:0" rst="0">
          <comment>RSRPdB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp1_scale" protect="rw">
        <bits access="rw" name="scale_rsrp" pos="31:0" rst="0">
          <comment>Scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp1_scale_db" protect="rw">
        <bits access="rw" name="scale_rsrp_db" pos="15:0" rst="0">
          <comment>ScaledB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrq1_db" protect="r">
        <bits access="r" name="rsrq_db" pos="15:0" rst="0">
          <comment>RSRQdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi1_out" protect="r">
        <bits access="r" name="rssi" pos="31:0" rst="0">
          <comment>RSSIRSSI AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi1_db" protect="r">
        <bits access="r" name="rssi_db" pos="15:0" rst="0">
          <comment>RSSIdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp2_out" protect="r">
        <bits access="r" name="rsrp_liner" pos="31:0" rst="0">
          <comment>RSRP</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp2_db" protect="r">
        <bits access="r" name="rsrp_pwr_db" pos="15:0" rst="0">
          <comment>RSRPdB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp2_scale" protect="rw">
        <bits access="rw" name="scale_rsrp" pos="31:0" rst="0">
          <comment>Scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp2_scale_db" protect="rw">
        <bits access="rw" name="scale_rsrp_db" pos="15:0" rst="0">
          <comment>ScaledB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrq2_db" protect="r">
        <bits access="r" name="rsrq_db" pos="15:0" rst="0">
          <comment>RSRQdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi2_out" protect="r">
        <bits access="r" name="rssi" pos="31:0" rst="0">
          <comment>RSSIRSSI AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi2_db" protect="r">
        <bits access="r" name="rssi_db" pos="15:0" rst="0">
          <comment>RSSIdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp3_out" protect="r">
        <bits access="r" name="rsrp_liner" pos="31:0" rst="0">
          <comment>RSRP</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp3_db" protect="r">
        <bits access="r" name="rsrp_pwr_db" pos="15:0" rst="0">
          <comment>RSRPdB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp3_scale" protect="rw">
        <bits access="rw" name="scale_rsrp" pos="31:0" rst="0">
          <comment>Scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp3_scale_db" protect="rw">
        <bits access="rw" name="scale_rsrp_db" pos="15:0" rst="0">
          <comment>ScaledB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrq3_db" protect="r">
        <bits access="r" name="rsrq_db" pos="15:0" rst="0">
          <comment>RSRQdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi3_out" protect="r">
        <bits access="r" name="rssi" pos="31:0" rst="0">
          <comment>RSSIRSSI AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi3_db" protect="r">
        <bits access="r" name="rssi_db" pos="15:0" rst="0">
          <comment>RSSIdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp4_out" protect="r">
        <bits access="r" name="rsrp_liner" pos="31:0" rst="0">
          <comment>RSRP</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp4_db" protect="r">
        <bits access="r" name="rsrp_pwr_db" pos="15:0" rst="0">
          <comment>RSRPdB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp4_scale" protect="rw">
        <bits access="rw" name="scale_rsrp" pos="31:0" rst="0">
          <comment>Scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp4_scale_db" protect="rw">
        <bits access="rw" name="scale_rsrp_db" pos="15:0" rst="0">
          <comment>ScaledB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrq4_db" protect="r">
        <bits access="r" name="rsrq_db" pos="15:0" rst="0">
          <comment>RSRQdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi4_out" protect="r">
        <bits access="r" name="rssi" pos="31:0" rst="0">
          <comment>RSSIRSSI AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi4_db" protect="r">
        <bits access="r" name="rssi_db" pos="15:0" rst="0">
          <comment>RSSIdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp5_out" protect="r">
        <bits access="r" name="rsrp_liner" pos="31:0" rst="0">
          <comment>RSRP</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp5_db" protect="r">
        <bits access="r" name="rsrp_pwr_db" pos="15:0" rst="0">
          <comment>RSRPdB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp5_scale" protect="rw">
        <bits access="rw" name="scale_rsrp" pos="31:0" rst="0">
          <comment>Scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp5_scale_db" protect="rw">
        <bits access="rw" name="scale_rsrp_db" pos="15:0" rst="0">
          <comment>ScaledB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrq5_db" protect="r">
        <bits access="r" name="rsrq_db" pos="15:0" rst="0">
          <comment>RSRQdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi5_out" protect="r">
        <bits access="r" name="rssi" pos="31:0" rst="0">
          <comment>RSSIRSSI AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi5_db" protect="r">
        <bits access="r" name="rssi_db" pos="15:0" rst="0">
          <comment>RSSIdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp6_out" protect="r">
        <bits access="r" name="rsrp_liner" pos="31:0" rst="0">
          <comment>RSRP</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp6_db" protect="r">
        <bits access="r" name="rsrp_pwr_db" pos="15:0" rst="0">
          <comment>RSRPdB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp6_scale" protect="rw">
        <bits access="rw" name="scale_rsrp" pos="31:0" rst="0">
          <comment>Scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp6_scale_db" protect="rw">
        <bits access="rw" name="scale_rsrp_db" pos="15:0" rst="0">
          <comment>ScaledB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrq6_db" protect="r">
        <bits access="r" name="rsrq_db" pos="15:0" rst="0">
          <comment>RSRQdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi6_out" protect="r">
        <bits access="r" name="rssi" pos="31:0" rst="0">
          <comment>RSSIRSSI AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi6_db" protect="r">
        <bits access="r" name="rssi_db" pos="15:0" rst="0">
          <comment>RSSIdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp7_out" protect="r">
        <bits access="r" name="rsrp_liner" pos="31:0" rst="0">
          <comment>RSRP</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp7_db" protect="r">
        <bits access="r" name="rsrp_pwr_db" pos="15:0" rst="0">
          <comment>RSRPdB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp7_scale" protect="rw">
        <bits access="rw" name="scale_rsrp" pos="31:0" rst="0">
          <comment>Scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp7_scale_db" protect="rw">
        <bits access="rw" name="scale_rsrp_db" pos="15:0" rst="0">
          <comment>ScaledB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrq7_db" protect="r">
        <bits access="r" name="rsrq_db" pos="15:0" rst="0">
          <comment>RSRQdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi7_out" protect="r">
        <bits access="r" name="rssi" pos="31:0" rst="0">
          <comment>RSSIRSSI AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi7_db" protect="r">
        <bits access="r" name="rssi_db" pos="15:0" rst="0">
          <comment>RSSIdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp8_out" protect="r">
        <bits access="r" name="rsrp_liner" pos="31:0" rst="0">
          <comment>RSRP</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp8_db" protect="r">
        <bits access="r" name="rsrp_pwr_db" pos="15:0" rst="0">
          <comment>RSRPdB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp8_scale" protect="rw">
        <bits access="rw" name="scale_rsrp" pos="31:0" rst="0">
          <comment>Scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp8_scale_db" protect="rw">
        <bits access="rw" name="scale_rsrp_db" pos="15:0" rst="0">
          <comment>ScaledB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrq8_db" protect="r">
        <bits access="r" name="rsrq_db" pos="15:0" rst="0">
          <comment>RSRQdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi8_out" protect="r">
        <bits access="r" name="rssi" pos="31:0" rst="0">
          <comment>RSSIRSSI AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_rssi8_db" protect="r">
        <bits access="r" name="rssi_db" pos="15:0" rst="0">
          <comment>RSSIdBOFDM</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt1_delay" protect="r">
        <bits access="r" name="irt_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_irt1outflag" protect="r">
        <bits access="r" name="irt_validflag" pos="12" rst="0">
          <comment>Irt_scale
1
0</comment>
        </bits>
        <bits access="r" name="subf_num" pos="8:0" rst="0">
          <comment>IRTscale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt1_scale" protect="r">
        <bits access="r" name="irt_scale" pos="31:0" rst="0">
          <comment>IRT scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt2_delay" protect="r">
        <bits access="r" name="irt_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_irt2outflag" protect="r">
        <bits access="r" name="irt_validflag" pos="12" rst="0">
          <comment>Irt_scale
1
0</comment>
        </bits>
        <bits access="r" name="subf_num" pos="8:0" rst="0">
          <comment>IRTscale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt2_scale" protect="r">
        <bits access="r" name="irt_scale" pos="31:0" rst="0">
          <comment>IRT scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt3_delay" protect="r">
        <bits access="r" name="irt_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_irt3outflag" protect="r">
        <bits access="r" name="irt_validflag" pos="12" rst="0">
          <comment>Irt_scale
1
0</comment>
        </bits>
        <bits access="r" name="subf_num" pos="8:0" rst="0">
          <comment>IRTscale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt3_scale" protect="r">
        <bits access="r" name="irt_scale" pos="31:0" rst="0">
          <comment>IRT scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt4_delay" protect="r">
        <bits access="r" name="irt_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_irt4outflag" protect="r">
        <bits access="r" name="irt_validflag" pos="12" rst="0">
          <comment>Irt_scale
1
0</comment>
        </bits>
        <bits access="r" name="subf_num" pos="8:0" rst="0">
          <comment>IRTscale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt4_scale" protect="r">
        <bits access="r" name="irt_scale" pos="31:0" rst="0">
          <comment>IRT scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt5_delay" protect="r">
        <bits access="r" name="irt_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_irt5outflag" protect="r">
        <bits access="r" name="irt_validflag" pos="12" rst="0">
          <comment>Irt_scale
1
0</comment>
        </bits>
        <bits access="r" name="subf_num" pos="8:0" rst="0">
          <comment>IRTscale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt5_scale" protect="r">
        <bits access="r" name="irt_scale" pos="31:0" rst="0">
          <comment>IRT scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt6_delay" protect="r">
        <bits access="r" name="irt_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_irt6outflag" protect="r">
        <bits access="r" name="irt_validflag" pos="12" rst="0">
          <comment>Irt_scale
1
0</comment>
        </bits>
        <bits access="r" name="subf_num" pos="8:0" rst="0">
          <comment>IRTscale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt6_scale" protect="r">
        <bits access="r" name="irt_scale" pos="31:0" rst="0">
          <comment>IRT scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt7_delay" protect="r">
        <bits access="r" name="irt_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_irt7outflag" protect="r">
        <bits access="r" name="irt_validflag" pos="12" rst="0">
          <comment>Irt_scale
1
0</comment>
        </bits>
        <bits access="r" name="subf_num" pos="8:0" rst="0">
          <comment>IRTscale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt7_scale" protect="r">
        <bits access="r" name="irt_scale" pos="31:0" rst="0">
          <comment>IRT scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt8_delay" protect="r">
        <bits access="r" name="irt_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_irt8outflag" protect="r">
        <bits access="r" name="irt_validflag" pos="12" rst="0">
          <comment>Irt_scale
1
0</comment>
        </bits>
        <bits access="r" name="subf_num" pos="8:0" rst="0">
          <comment>IRTscale</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt8_scale" protect="r">
        <bits access="r" name="irt_scale" pos="31:0" rst="0">
          <comment>IRT scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_trms1_out" protect="r">
        <bits access="r" name="trms_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_trms2_out" protect="r">
        <bits access="r" name="trms_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_id_info" protect="r">
        <bits access="r" name="id2_info" pos="31:16" rst="0">
          <comment>ID2</comment>
        </bits>
        <bits access="r" name="id1_info" pos="15:0" rst="0">
          <comment>ID1</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis_para" protect="rw">
        <bits access="rw" name="rbis_correct" pos="29" rst="0">
          <comment>ID1-2 RBIS CORRECT
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_judge" pos="28" rst="0">
          <comment>ID1-2 RBIS JUDGE
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_en" pos="27" rst="0">
          <comment>ID1-2 RBIS
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_posen" pos="26" rst="0">
          <comment>ID1-2 RBIS
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_num" pos="25:23" rst="0">
          <comment>ID1-2 RBIS
01
12
23
34
45</comment>
        </bits>
        <bits access="rw" name="rbis_dipos" pos="22:16" rst="0">
          <comment>ID1-2 RBIS</comment>
        </bits>
        <bits access="rw" name="rbis_factor" pos="15:0" rst="0">
          <comment>ID1-2 RBIS</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis_out1" protect="r">
        <bits access="r" name="rbis_out3" pos="30:24" rst="0">
          <comment>ID14RBIPRB</comment>
        </bits>
        <bits access="r" name="rbis_out2" pos="22:16" rst="0">
          <comment>ID13RBIPRB</comment>
        </bits>
        <bits access="r" name="rbis_out1" pos="14:8" rst="0">
          <comment>ID12RBIPRB</comment>
        </bits>
        <bits access="r" name="rbis_out0" pos="6:0" rst="0">
          <comment>ID11RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis_out2" protect="r">
        <bits access="r" name="rbis_num" pos="10:8" rst="0">
          <comment>ID1 RBIS JUDGE</comment>
        </bits>
        <bits access="r" name="rbis_out4" pos="6:0" rst="0">
          <comment>ID15RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis_ave" protect="r">
        <bits access="r" name="rbis_ave" pos="31:0" rst="0">
          <comment>ID1 RBIS</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis_max" protect="r">
        <bits access="r" name="rbis_max" pos="24:0" rst="0">
          <comment>ID1 RBIS</comment>
        </bits>
      </reg>
      <reg name="measpwr_rx_irt" protect="r">
        <bits access="r" name="id2_offset4" pos="30:21" rst="0">
          <comment>ID2 offset4</comment>
        </bits>
        <bits access="r" name="id2_rx_irt" pos="20:16" rst="0">
          <comment>ID2 RX IRT</comment>
        </bits>
        <bits access="r" name="id1_offset4" pos="14:5" rst="0">
          <comment>ID1 offset4</comment>
        </bits>
        <bits access="r" name="id1_rx_irt" pos="4:0" rst="0">
          <comment>ID1 RX IRT</comment>
        </bits>
      </reg>
      <reg name="measpwr_debug1" protect="r">
        <bits access="r" name="debug_rev_flag" pos="23" rst="0">
          <comment>debug_rev_flag</comment>
        </bits>
        <bits access="r" name="debug_update_flag" pos="22" rst="0">
          <comment>debug_update_flag</comment>
        </bits>
        <bits access="r" name="id_update" pos="21" rst="0">
          <comment>id_update</comment>
        </bits>
        <bits access="r" name="offset2_update" pos="20" rst="0">
          <comment>offset2_update</comment>
        </bits>
        <bits access="r" name="din_id_sel" pos="18:16" rst="0">
          <comment>din_id_sel</comment>
        </bits>
        <bits access="r" name="datagen_state" pos="14:4" rst="0">
          <comment>datagen_state</comment>
        </bits>
        <bits access="r" name="datain_state" pos="2:0" rst="0">
          <comment>datain_state</comment>
        </bits>
      </reg>
      <reg name="measpwr_debug2" protect="r">
        <bits access="r" name="inmem_in_act" pos="31" rst="0">
          <comment>inmem_in_act</comment>
        </bits>
        <bits access="r" name="invalid_data_cont" pos="30:16" rst="0">
          <comment>invalid_data_cont</comment>
        </bits>
        <bits access="r" name="inmem_cont" pos="15:0" rst="0">
          <comment>inmem_cont</comment>
        </bits>
      </reg>
      <reg name="measpwr_debug3" protect="r">
        <bits access="r" name="datain_state_cur" pos="26:24" rst="0">
          <comment>datain_state_cur</comment>
        </bits>
        <bits access="r" name="func_id_sel" pos="22:20" rst="0">
          <comment>func_id_sel</comment>
        </bits>
        <bits access="r" name="pow_state" pos="16:12" rst="0">
          <comment>pow_state</comment>
        </bits>
        <bits access="r" name="func_state" pos="8:0" rst="0">
          <comment>func_state</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr6_out" protect="r">
        <bits access="r" name="sigpwr6_out" pos="31:0" rst="0">
          <comment>ID6SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr7_out" protect="r">
        <bits access="r" name="sigpwr7_out" pos="31:0" rst="0">
          <comment>ID7SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr8_out" protect="r">
        <bits access="r" name="sigpwr8_out" pos="31:0" rst="0">
          <comment>ID8SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma6_out" protect="r">
        <bits access="r" name="sigma6_out" pos="31:0" rst="0">
          <comment>ID6SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma6_agc_out" protect="r">
        <bits access="r" name="sinr6_log_out" pos="26:16" rst="0">
          <comment>ID6SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc6_out" pos="9:0" rst="0">
          <comment>ID6SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma7_out" protect="r">
        <bits access="r" name="sigma7_out" pos="31:0" rst="0">
          <comment>ID7SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma7_agc_out" protect="r">
        <bits access="r" name="sinr7_log_out" pos="26:16" rst="0">
          <comment>ID7SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc7_out" pos="9:0" rst="0">
          <comment>ID7SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma8_out" protect="r">
        <bits access="r" name="sigma8_out" pos="31:0" rst="0">
          <comment>ID8SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma8_agc_out" protect="r">
        <bits access="r" name="sinr8_log_out" pos="26:16" rst="0">
          <comment>ID8SINR LOG</comment>
        </bits>
        <bits access="r" name="baseagc8_out" pos="9:0" rst="0">
          <comment>ID8SIGMAAGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr6_out" protect="r">
        <bits access="r" name="sinr6_out" pos="31:0" rst="0">
          <comment>ID6SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr7_out" protect="r">
        <bits access="r" name="sinr7_out" pos="31:0" rst="0">
          <comment>ID7SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sinr8_out" protect="r">
        <bits access="r" name="sinr8_out" pos="31:0" rst="0">
          <comment>ID8SINR</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc_soft_reect2" protect="rw">
        <bits access="rw" name="afc_soft_fa_ctor2" pos="15:0" rst="0">
          <comment>ID2 AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc_soft_reect3" protect="rw">
        <bits access="rw" name="afc_soft_fa_ctor3" pos="15:0" rst="0">
          <comment>ID3 AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc_soft_reect4" protect="rw">
        <bits access="rw" name="afc_soft_fa_ctor4" pos="15:0" rst="0">
          <comment>ID4 AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc_soft_reect5" protect="rw">
        <bits access="rw" name="afc_soft_fa_ctor5" pos="15:0" rst="0">
          <comment>ID5 AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc_soft_reect6" protect="rw">
        <bits access="rw" name="afc_soft_fa_ctor6" pos="15:0" rst="0">
          <comment>ID6 AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc_soft_reect7" protect="rw">
        <bits access="rw" name="afc_soft_fa_ctor7" pos="15:0" rst="0">
          <comment>ID7 AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc_soft_reect8" protect="rw">
        <bits access="rw" name="afc_soft_fa_ctor8" pos="15:0" rst="0">
          <comment>ID8 AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler_para2" protect="rw">
        <bits access="rw" name="doppler_alpha2" pos="16:0" rst="0">
          <comment>Id3-8 Doppler alpha</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf_para" protect="rw">
        <bits access="rw" name="trmsf_scale" pos="27:24" rst="0">
          <comment>trmsf_scale(Q12</comment>
        </bits>
        <bits access="rw" name="trmsf_space" pos="21:20" rst="0">
          <comment>TRMS</comment>
        </bits>
        <bits access="rw" name="trmsf_alpha" pos="16:0" rst="0">
          <comment>TRMS alpha</comment>
        </bits>
      </reg>
      <reg name="measpwr_id3_para2" protect="rw">
        <bits access="rw" name="offline0_step" pos="24:16" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="qf_mem_sel" pos="15" rst="0">
          <comment>Hmmse QF mem
0QF mem
1QF mem</comment>
        </bits>
        <bits access="rw" name="irt_scale_disable" pos="14" rst="0">
          <comment>IRT scale
0
1</comment>
        </bits>
        <bits access="rw" name="pow_data_sel" pos="13:12" rst="0">
          <comment>AFC\POW
00hls
01hmmse
10freqfirst
11hls</comment>
        </bits>
        <bits access="rw" name="frame_map" pos="9:0" rst="0">
          <comment>bit[9:0]9-0</comment>
        </bits>
      </reg>
      <reg name="measpwr_id4_para2" protect="rw">
        <bits access="rw" name="offline0_step" pos="24:16" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="qf_mem_sel" pos="15" rst="0">
          <comment>Hmmse QF mem
0QF mem
1QF mem</comment>
        </bits>
        <bits access="rw" name="irt_scale_disable" pos="14" rst="0">
          <comment>IRT scale
0
1</comment>
        </bits>
        <bits access="rw" name="pow_data_sel" pos="13:12" rst="0">
          <comment>AFC\POW
00hls
01hmmse
10freqfirst
11hls</comment>
        </bits>
        <bits access="rw" name="frame_map" pos="9:0" rst="0">
          <comment>bit[9:0]9-0</comment>
        </bits>
      </reg>
      <reg name="measpwr_id5_para2" protect="rw">
        <bits access="rw" name="offline0_step" pos="24:16" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="qf_mem_sel" pos="15" rst="0">
          <comment>Hmmse QF mem
0QF mem
1QF mem</comment>
        </bits>
        <bits access="rw" name="irt_scale_disable" pos="14" rst="0">
          <comment>IRT scale
0
1</comment>
        </bits>
        <bits access="rw" name="pow_data_sel" pos="13:12" rst="0">
          <comment>AFC\POW
00hls
01hmmse
10freqfirst
11hls</comment>
        </bits>
        <bits access="rw" name="frame_map" pos="9:0" rst="0">
          <comment>bit[9:0]9-0</comment>
        </bits>
      </reg>
      <reg name="measpwr_id6_para2" protect="rw">
        <bits access="rw" name="offline0_step" pos="24:16" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="qf_mem_sel" pos="15" rst="0">
          <comment>Hmmse QF mem
0QF mem
1QF mem</comment>
        </bits>
        <bits access="rw" name="irt_scale_disable" pos="14" rst="0">
          <comment>IRT scale
0
1</comment>
        </bits>
        <bits access="rw" name="pow_data_sel" pos="13:12" rst="0">
          <comment>AFC\POW
00hls
01hmmse
10freqfirst
11hls</comment>
        </bits>
        <bits access="rw" name="frame_map" pos="9:0" rst="0">
          <comment>bit[9:0]9-0</comment>
        </bits>
      </reg>
      <reg name="measpwr_id7_para2" protect="rw">
        <bits access="rw" name="offline0_step" pos="24:16" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="qf_mem_sel" pos="15" rst="0">
          <comment>Hmmse QF mem
0QF mem
1QF mem</comment>
        </bits>
        <bits access="rw" name="irt_scale_disable" pos="14" rst="0">
          <comment>IRT scale
0
1</comment>
        </bits>
        <bits access="rw" name="pow_data_sel" pos="13:12" rst="0">
          <comment>AFC\POW
00hls
01hmmse
10freqfirst
11hls</comment>
        </bits>
        <bits access="rw" name="frame_map" pos="9:0" rst="0">
          <comment>bit[9:0]9-0</comment>
        </bits>
      </reg>
      <reg name="measpwr_id8_para2" protect="rw">
        <bits access="rw" name="offline0_step" pos="24:16" rst="0">
          <comment>OFFLINE0</comment>
        </bits>
        <bits access="rw" name="qf_mem_sel" pos="15" rst="0">
          <comment>Hmmse QF mem
0QF mem
1QF mem</comment>
        </bits>
        <bits access="rw" name="irt_scale_disable" pos="14" rst="0">
          <comment>IRT scale
0
1</comment>
        </bits>
        <bits access="rw" name="pow_data_sel" pos="13:12" rst="0">
          <comment>AFC\POW
00hls
01hmmse
10freqfirst
11hls</comment>
        </bits>
        <bits access="rw" name="frame_map" pos="9:0" rst="0">
          <comment>bit[9:0]9-0</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc1_hst" protect="r">
        <bits access="r" name="afc_hst" pos="15:0" rst="0">
          <comment>AFC HST</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc2_hst" protect="r">
        <bits access="r" name="afc_hst" pos="15:0" rst="0">
          <comment>AFC HST</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc3_hst" protect="r">
        <bits access="r" name="afc_hst" pos="15:0" rst="0">
          <comment>AFC HST</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc4_hst" protect="r">
        <bits access="r" name="afc_hst" pos="15:0" rst="0">
          <comment>AFC HST</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc5_hst" protect="r">
        <bits access="r" name="afc_hst" pos="15:0" rst="0">
          <comment>AFC HST</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc6_hst" protect="r">
        <bits access="r" name="afc_hst" pos="15:0" rst="0">
          <comment>AFC HST</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc7_hst" protect="r">
        <bits access="r" name="afc_hst" pos="15:0" rst="0">
          <comment>AFC HST</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc8_hst" protect="r">
        <bits access="r" name="afc_hst" pos="15:0" rst="0">
          <comment>AFC HST</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr1_bef" protect="r">
        <bits access="r" name="sigpwr1_bef" pos="31:0" rst="0">
          <comment>ID1SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr2_bef" protect="r">
        <bits access="r" name="sigpwr2_bef" pos="31:0" rst="0">
          <comment>ID2SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr3_bef" protect="r">
        <bits access="r" name="sigpwr3_bef" pos="31:0" rst="0">
          <comment>ID3SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr4_bef" protect="r">
        <bits access="r" name="sigpwr4_bef" pos="31:0" rst="0">
          <comment>ID4SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr5_bef" protect="r">
        <bits access="r" name="sigpwr5_bef" pos="31:0" rst="0">
          <comment>ID5SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr6_bef" protect="r">
        <bits access="r" name="sigpwr6_bef" pos="31:0" rst="0">
          <comment>ID6SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr7_bef" protect="r">
        <bits access="r" name="sigpwr7_bef" pos="31:0" rst="0">
          <comment>ID7SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr8_bef" protect="r">
        <bits access="r" name="sigpwr8_bef" pos="31:0" rst="0">
          <comment>ID8SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma1_bef" protect="r">
        <bits access="r" name="sigma1_bef" pos="31:0" rst="0">
          <comment>ID1SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma2_bef" protect="r">
        <bits access="r" name="sigma2_bef" pos="31:0" rst="0">
          <comment>ID2SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma3_bef" protect="r">
        <bits access="r" name="sigma3_bef" pos="31:0" rst="0">
          <comment>ID3SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma4_bef" protect="r">
        <bits access="r" name="sigma4_bef" pos="31:0" rst="0">
          <comment>ID4SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma5_bef" protect="r">
        <bits access="r" name="sigma5_bef" pos="31:0" rst="0">
          <comment>ID5SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma6_bef" protect="r">
        <bits access="r" name="sigma6_bef" pos="31:0" rst="0">
          <comment>ID6SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma7_bef" protect="r">
        <bits access="r" name="sigma7_bef" pos="31:0" rst="0">
          <comment>ID7SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigma8_bef" protect="r">
        <bits access="r" name="sigma8_bef" pos="31:0" rst="0">
          <comment>ID8SIGMA</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler3_out" protect="r">
        <bits access="r" name="hls_agc_base3" pos="25:16" rst="0">
          <comment>hls_agc_base</comment>
        </bits>
        <bits access="r" name="doppler3_out" pos="10:0" rst="0">
          <comment>DOPPLER</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler4_out" protect="r">
        <bits access="r" name="hls_agc_base4" pos="25:16" rst="0">
          <comment>hls_agc_base</comment>
        </bits>
        <bits access="r" name="doppler4_out" pos="10:0" rst="0">
          <comment>DOPPLER</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler5_out" protect="r">
        <bits access="r" name="hls_agc_base5" pos="25:16" rst="0">
          <comment>hls_agc_base</comment>
        </bits>
        <bits access="r" name="doppler5_out" pos="10:0" rst="0">
          <comment>DOPPLER</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler6_out" protect="r">
        <bits access="r" name="hls_agc_base6" pos="25:16" rst="0">
          <comment>hls_agc_base</comment>
        </bits>
        <bits access="r" name="doppler6_out" pos="10:0" rst="0">
          <comment>DOPPLER</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler7_out" protect="r">
        <bits access="r" name="hls_agc_base7" pos="25:16" rst="0">
          <comment>hls_agc_base</comment>
        </bits>
        <bits access="r" name="doppler7_out" pos="10:0" rst="0">
          <comment>DOPPLER</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler8_out" protect="r">
        <bits access="r" name="hls_agc_base8" pos="25:16" rst="0">
          <comment>hls_agc_base</comment>
        </bits>
        <bits access="r" name="doppler8_out" pos="10:0" rst="0">
          <comment>DOPPLER</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler1_bef1" protect="r">
        <bits access="r" name="doppler1_bef1" pos="31:0" rst="0">
          <comment>DOPPLER1</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler1_bef2" protect="r">
        <bits access="r" name="doppler1_bef2" pos="31:0" rst="0">
          <comment>DOPPLER2</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler2_bef1" protect="r">
        <bits access="r" name="doppler2_bef1" pos="31:0" rst="0">
          <comment>DOPPLER1</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler2_bef2" protect="r">
        <bits access="r" name="doppler2_bef2" pos="31:0" rst="0">
          <comment>DOPPLER2</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf1_out" protect="r">
        <bits access="r" name="trmsf_delay" pos="31:0" rst="0">
          <comment>TRMS</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf2_out" protect="r">
        <bits access="r" name="trmsf_delay" pos="31:0" rst="0">
          <comment>TRMS</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf3_out" protect="r">
        <bits access="r" name="trmsf_delay" pos="31:0" rst="0">
          <comment>TRMS</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf4_out" protect="r">
        <bits access="r" name="trmsf_delay" pos="31:0" rst="0">
          <comment>TRMS</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf5_out" protect="r">
        <bits access="r" name="trmsf_delay" pos="31:0" rst="0">
          <comment>TRMS</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf6_out" protect="r">
        <bits access="r" name="trmsf_delay" pos="31:0" rst="0">
          <comment>TRMS</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf7_out" protect="r">
        <bits access="r" name="trmsf_delay" pos="31:0" rst="0">
          <comment>TRMS</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf8_out" protect="r">
        <bits access="r" name="trmsf_delay" pos="31:0" rst="0">
          <comment>TRMS</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="measpwr_trmsf1_bef1" protect="r">
        <bits access="r" name="trmsf_bef1" pos="31:0" rst="0">
          <comment>TRMSPART1</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf1_bef2" protect="r">
        <bits access="r" name="trmsf_bef2" pos="31:0" rst="0">
          <comment>TRMSPART2</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf2_bef1" protect="r">
        <bits access="r" name="trmsf_bef1" pos="31:0" rst="0">
          <comment>TRMSPART1</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf2_bef2" protect="r">
        <bits access="r" name="trmsf_bef2" pos="31:0" rst="0">
          <comment>TRMSPART2</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf3_bef1" protect="r">
        <bits access="r" name="trmsf_bef1" pos="31:0" rst="0">
          <comment>TRMSPART1</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf3_bef2" protect="r">
        <bits access="r" name="trmsf_bef2" pos="31:0" rst="0">
          <comment>TRMSPART2</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf4_bef1" protect="r">
        <bits access="r" name="trmsf_bef1" pos="31:0" rst="0">
          <comment>TRMSPART1</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf4_bef2" protect="r">
        <bits access="r" name="trmsf_bef2" pos="31:0" rst="0">
          <comment>TRMSPART2</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf5_bef1" protect="r">
        <bits access="r" name="trmsf_bef1" pos="31:0" rst="0">
          <comment>TRMSPART1</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf5_bef2" protect="r">
        <bits access="r" name="trmsf_bef2" pos="31:0" rst="0">
          <comment>TRMSPART2</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf6_bef1" protect="r">
        <bits access="r" name="trmsf_bef1" pos="31:0" rst="0">
          <comment>TRMSPART1</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf6_bef2" protect="r">
        <bits access="r" name="trmsf_bef2" pos="31:0" rst="0">
          <comment>TRMSPART2</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf7_bef1" protect="r">
        <bits access="r" name="trmsf_bef1" pos="31:0" rst="0">
          <comment>TRMSPART1</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf7_bef2" protect="r">
        <bits access="r" name="trmsf_bef2" pos="31:0" rst="0">
          <comment>TRMSPART2</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf8_bef1" protect="r">
        <bits access="r" name="trmsf_bef1" pos="31:0" rst="0">
          <comment>TRMSPART1</comment>
        </bits>
      </reg>
      <reg name="measpwr_trmsf8_bef2" protect="r">
        <bits access="r" name="trmsf_bef2" pos="31:0" rst="0">
          <comment>TRMSPART2</comment>
        </bits>
      </reg>
      <reg name="measpwr_pow1_max" protect="r">
        <bits access="r" name="pow_max" pos="31:7" rst="0">
          <comment>POWbit[23:0]</comment>
        </bits>
        <bits access="r" name="pow_max_addr" pos="6:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_pow2_max" protect="r">
        <bits access="r" name="pow_max" pos="31:7" rst="0">
          <comment>POWbit[23:0]</comment>
        </bits>
        <bits access="r" name="pow_max_addr" pos="6:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_pow3_max" protect="r">
        <bits access="r" name="pow_max" pos="31:7" rst="0">
          <comment>POWbit[23:0]</comment>
        </bits>
        <bits access="r" name="pow_max_addr" pos="6:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_pow4_max" protect="r">
        <bits access="r" name="pow_max" pos="31:7" rst="0">
          <comment>POWbit[23:0]</comment>
        </bits>
        <bits access="r" name="pow_max_addr" pos="6:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_pow5_max" protect="r">
        <bits access="r" name="pow_max" pos="31:7" rst="0">
          <comment>POWbit[23:0]</comment>
        </bits>
        <bits access="r" name="pow_max_addr" pos="6:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_pow6_max" protect="r">
        <bits access="r" name="pow_max" pos="31:7" rst="0">
          <comment>POWbit[23:0]</comment>
        </bits>
        <bits access="r" name="pow_max_addr" pos="6:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_pow7_max" protect="r">
        <bits access="r" name="pow_max" pos="31:7" rst="0">
          <comment>POWbit[23:0]</comment>
        </bits>
        <bits access="r" name="pow_max_addr" pos="6:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_pow8_max" protect="r">
        <bits access="r" name="pow_max" pos="31:7" rst="0">
          <comment>POWbit[23:0]</comment>
        </bits>
        <bits access="r" name="pow_max_addr" pos="6:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_trms3_out" protect="r">
        <bits access="r" name="trms_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_trms4_out" protect="r">
        <bits access="r" name="trms_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_trms5_out" protect="r">
        <bits access="r" name="trms_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_trms6_out" protect="r">
        <bits access="r" name="trms_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_trms7_out" protect="r">
        <bits access="r" name="trms_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_trms8_out" protect="r">
        <bits access="r" name="trms_delay" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="measpwr_reis_conf" protect="rw">
        <bits access="rw" name="reis_dc_en" pos="5" rst="0">
          <comment>REIS_DC</comment>
        </bits>
        <bits access="rw" name="reis_en" pos="4" rst="0">
          <comment>REIS
0
1</comment>
        </bits>
        <bits access="rw" name="reis_num" pos="3:0" rst="0">
          <comment>REISNUM</comment>
        </bits>
      </reg>
      <reg name="measpwr_reis_pos0" protect="rw">
        <bits access="rw" name="reis_re1" pos="26:16" rst="0">
          <comment>REIS1RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_re0" pos="10:0" rst="0">
          <comment>REIS0RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="measpwr_reis_pos1" protect="rw">
        <bits access="rw" name="reis_re3" pos="26:16" rst="0">
          <comment>REIS3RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_re2" pos="10:0" rst="0">
          <comment>REIS2RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="measpwr_reis_pos2" protect="rw">
        <bits access="rw" name="reis_re5" pos="26:16" rst="0">
          <comment>REIS5RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_re4" pos="10:0" rst="0">
          <comment>REIS4RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="measpwr_reis_pos3" protect="rw">
        <bits access="rw" name="reis_re7" pos="26:16" rst="0">
          <comment>REIS7RE20M1200RE</comment>
        </bits>
        <bits access="rw" name="reis_re6" pos="10:0" rst="0">
          <comment>REIS6RE20M1200RE</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_sel" protect="rw">
        <bits access="rw" name="pos_delay_sel" pos="8" rst="0">
          <comment>Pos\delay
0pos
1:delay</comment>
        </bits>
        <bits access="rw" name="jump_flag" pos="5:4" rst="0">
          <comment>00IRT_Scale
01RSRP_Scale
10SINR
11POWMAX_Scale</comment>
        </bits>
        <bits access="rw" name="decision_flag" pos="1:0" rst="0">
          <comment>00IRT_Scale
01Sigpwr
10SINR
11IRT_Scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_th" protect="rw">
        <bits access="rw" name="offline_th" pos="31:0" rst="0">
          <comment>Offline
MEASPWR_OFFLINE_SEL[5:4]</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_pos" protect="r">
        <bits access="r" name="id8_max_position" pos="31:28" rst="0">
          <comment>Id8TBin</comment>
        </bits>
        <bits access="r" name="id7_max_position" pos="27:24" rst="0">
          <comment>Id7TBin</comment>
        </bits>
        <bits access="r" name="id6_max_position" pos="23:20" rst="0">
          <comment>Id6TBin</comment>
        </bits>
        <bits access="r" name="id5_max_position" pos="19:16" rst="0">
          <comment>Id5TBin</comment>
        </bits>
        <bits access="r" name="id4_max_position" pos="15:12" rst="0">
          <comment>Id4TBin</comment>
        </bits>
        <bits access="r" name="id3_max_position" pos="11:8" rst="0">
          <comment>Id3TBin</comment>
        </bits>
        <bits access="r" name="id2_max_position" pos="7:4" rst="0">
          <comment>Id2TBin</comment>
        </bits>
        <bits access="r" name="id1_max_position" pos="3:0" rst="0">
          <comment>Id1TBin</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_id" protect="r">
        <bits access="r" name="tbin_position_valid_flag" pos="11:4" rst="0">
          <comment>TbinID1~ID8
0
1</comment>
        </bits>
        <bits access="r" name="offline_jump_id" pos="3:0" rst="15">
          <comment>Offline
0xF</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline1_para" protect="rw">
        <bits access="rw" name="first_ofdm" pos="12" rst="0">
          <comment>00
143</comment>
        </bits>
        <bits access="rw" name="offline1_mod_sel" pos="9:8" rst="0">
          <comment>Offline1
000
0105
1050
1190</comment>
        </bits>
        <bits access="rw" name="offline1_num" pos="5" rst="0">
          <comment>Offline1
01
12</comment>
        </bits>
        <bits access="rw" name="offline1_time" pos="4:0" rst="0">
          <comment>Offline1</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline1_agc1" protect="rw">
        <bits access="rw" name="offline1_agc3" pos="29:20" rst="0">
          <comment>3 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc2" pos="19:10" rst="0">
          <comment>2 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc1" pos="9:0" rst="0">
          <comment>1 AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline1_agc2" protect="rw">
        <bits access="rw" name="offline1_agc6" pos="29:20" rst="0">
          <comment>6 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc5" pos="19:10" rst="0">
          <comment>5 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc4" pos="9:0" rst="0">
          <comment>4 AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline1_agc3" protect="rw">
        <bits access="rw" name="offline1_agc9" pos="29:20" rst="0">
          <comment>9 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc8" pos="19:10" rst="0">
          <comment>8 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc7" pos="9:0" rst="0">
          <comment>7 AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline1_agc4" protect="rw">
        <bits access="rw" name="offline1_agc12" pos="29:20" rst="0">
          <comment>12 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc11" pos="19:10" rst="0">
          <comment>11 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc10" pos="9:0" rst="0">
          <comment>10 AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline1_agc5" protect="rw">
        <bits access="rw" name="offline1_agc15" pos="29:20" rst="0">
          <comment>15 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc14" pos="19:10" rst="0">
          <comment>14 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc13" pos="9:0" rst="0">
          <comment>13 AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline1_agc6" protect="rw">
        <bits access="rw" name="offline1_agc18" pos="29:20" rst="0">
          <comment>18 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc17" pos="19:10" rst="0">
          <comment>17 AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc16" pos="9:0" rst="0">
          <comment>16 AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi1_out1" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi1_out2" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi1_out3" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi2_out1" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi2_out2" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi2_out3" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="measpwr_crs_rssi3_out" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi4_out" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi5_out" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi6_out" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi7_out" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi8_out" protect="r">
        <bits access="r" name="crs_rssi_max" pos="31:0" rst="0">
          <comment>Crs rssi</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi1_agc1" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi1_agc2" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi1_agc3" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi2_agc1" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi2_agc2" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi2_agc3" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi3_agc" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi4_agc" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi5_agc" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi6_agc" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi7_agc" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_crs_rssi8_agc" protect="r">
        <bits access="r" name="crs_rssi_agc" pos="9:0" rst="0">
          <comment>Crs rssiagc</comment>
        </bits>
      </reg>
      <reg name="measpwr_hmmse_win" protect="rw">
        <bits access="rw" name="fh_wl_ind" pos="0" rst="0">
          <comment>03PRB
16PRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_hmmse_bitsel" protect="rw">
        <bits access="rw" name="fh_bitsel" pos="3:0" rst="6">
          <comment>13bit
0x029~17
0x128~16
0x227~15
0x326~14
0x425~13
0x524~12
0x623~11
0x722~10
0x821~9
0x920~8
0xa19~7
0xb18~6
0xc17~5
0xd16~4
0xe15~3
0xf14~2</comment>
        </bits>
      </reg>
      <reg name="measpwr_hmmse_flag" protect="r">
        <bits access="r" name="used_wl_ind" pos="4" rst="0">
          <comment>USED_WL_IND</comment>
        </bits>
        <bits access="r" name="qf_mem_mark" pos="1:0" rst="0">
          <comment>QF MEM
00mem
01mem
Othermem</comment>
        </bits>
      </reg>
      <reg name="measpwr_id_info2" protect="r">
        <bits access="r" name="id38_info" pos="9:0" rst="0">
          <comment>ID38</comment>
        </bits>
      </reg>
      <reg name="measpwr_inmem_mode" protect="rw">
        <bits access="rw" name="inmem_mode" pos="1:0" rst="0">
          <comment>INMEM
00 measpwr
01OTDOA
10
11</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc1_rsrp_hst" protect="r">
        <bits access="r" name="afc_rsrp1_hst" pos="15:0" rst="0">
          <comment>AFC HSTRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc2_rsrp_hst" protect="r">
        <bits access="r" name="afc_rsrp2_hst" pos="15:0" rst="0">
          <comment>AFC HSTRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc3_rsrp_hst" protect="r">
        <bits access="r" name="afc_rsrp3_hst" pos="15:0" rst="0">
          <comment>AFC HSTRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc4_rsrp_hst" protect="r">
        <bits access="r" name="afc_rsrp4_hst" pos="15:0" rst="0">
          <comment>AFC HSTRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc5_rsrp_hst" protect="r">
        <bits access="r" name="afc_rsrp5_hst" pos="15:0" rst="0">
          <comment>AFC HSTRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc6_rsrp_hst" protect="r">
        <bits access="r" name="afc_rsrp6_hst" pos="15:0" rst="0">
          <comment>AFC HSTRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc7_rsrp_hst" protect="r">
        <bits access="r" name="afc_rsrp7_hst" pos="15:0" rst="0">
          <comment>AFC HSTRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc8_rsrp_hst" protect="r">
        <bits access="r" name="afc_rsrp8_hst" pos="15:0" rst="0">
          <comment>AFC HSTRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_powmax1_scale" protect="r">
        <bits access="r" name="pow_max_scale" pos="31:0" rst="0">
          <comment>Pow_max_scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_powmax2_scale" protect="r">
        <bits access="r" name="pow_max_scale" pos="31:0" rst="0">
          <comment>Pow_max_scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_powmax3_scale" protect="r">
        <bits access="r" name="pow_max_scale" pos="31:0" rst="0">
          <comment>Pow_max_scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_powmax4_scale" protect="r">
        <bits access="r" name="pow_max_scale" pos="31:0" rst="0">
          <comment>Pow_max_scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_powmax5_scale" protect="r">
        <bits access="r" name="pow_max_scale" pos="31:0" rst="0">
          <comment>Pow_max_scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_powmax6_scale" protect="r">
        <bits access="r" name="pow_max_scale" pos="31:0" rst="0">
          <comment>Pow_max_scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_powmax7_scale" protect="r">
        <bits access="r" name="pow_max_scale" pos="31:0" rst="0">
          <comment>Pow_max_scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_powmax8_scale" protect="r">
        <bits access="r" name="pow_max_scale" pos="31:0" rst="0">
          <comment>Pow_max_scale</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc6_out" protect="r">
        <bits access="r" name="afc_out6" pos="15:0" rst="0">
          <comment>AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc7_out" protect="r">
        <bits access="r" name="afc_out7" pos="15:0" rst="0">
          <comment>AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc8_out" protect="r">
        <bits access="r" name="afc_out8" pos="15:0" rst="0">
          <comment>AFC</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc6_rsrp" protect="r">
        <bits access="r" name="afc_rsrp6" pos="15:0" rst="0">
          <comment>AFCRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc7_rsrp" protect="r">
        <bits access="r" name="afc_rsrp7" pos="15:0" rst="0">
          <comment>AFCRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_afc8_rsrp" protect="r">
        <bits access="r" name="afc_rsrp8" pos="15:0" rst="0">
          <comment>AFCRSRP db</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler3_bef1" protect="r">
        <bits access="r" name="doppler3_bef1" pos="31:0" rst="0">
          <comment>DOPPLER1</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler3_bef2" protect="r">
        <bits access="r" name="doppler3_bef2" pos="31:0" rst="0">
          <comment>DOPPLER2</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler4_bef1" protect="r">
        <bits access="r" name="doppler4_bef1" pos="31:0" rst="0">
          <comment>DOPPLER1</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler4_bef2" protect="r">
        <bits access="r" name="doppler4_bef2" pos="31:0" rst="0">
          <comment>DOPPLER2</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler5_bef1" protect="r">
        <bits access="r" name="doppler5_bef1" pos="31:0" rst="0">
          <comment>DOPPLER1</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler5_bef2" protect="r">
        <bits access="r" name="doppler5_bef2" pos="31:0" rst="0">
          <comment>DOPPLER2</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler6_bef1" protect="r">
        <bits access="r" name="doppler6_bef1" pos="31:0" rst="0">
          <comment>DOPPLER1</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler6_bef2" protect="r">
        <bits access="r" name="doppler6_bef2" pos="31:0" rst="0">
          <comment>DOPPLER2</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler7_bef1" protect="r">
        <bits access="r" name="doppler7_bef1" pos="31:0" rst="0">
          <comment>DOPPLER1</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler7_bef2" protect="r">
        <bits access="r" name="doppler7_bef2" pos="31:0" rst="0">
          <comment>DOPPLER2</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler8_bef1" protect="r">
        <bits access="r" name="doppler8_bef1" pos="31:0" rst="0">
          <comment>DOPPLER1</comment>
        </bits>
      </reg>
      <reg name="measpwr_doppler8_bef2" protect="r">
        <bits access="r" name="doppler8_bef2" pos="31:0" rst="0">
          <comment>DOPPLER2</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline1_agc7" protect="rw">
        <bits access="rw" name="offline1_agc20" pos="19:10" rst="0">
          <comment>20AGC</comment>
        </bits>
        <bits access="rw" name="offline1_agc19" pos="9:0" rst="0">
          <comment>19AGC</comment>
        </bits>
      </reg>
      <reg name="measpwr_int_join" protect="rw">
        <bits access="rw" name="interrupt_join_flag" pos="7:0" rst="0">
          <comment>bit[7:0]id8-id1
0:
1</comment>
        </bits>
      </reg>
      <reg name="measpwr_int_mark" protect="r">
        <bits access="r" name="id8_interrupt_mark" pos="31:28" rst="0">
          <comment>ID1</comment>
        </bits>
        <bits access="r" name="id7_interrupt_mark" pos="27:24" rst="0">
          <comment>ID1</comment>
        </bits>
        <bits access="r" name="id6_interrupt_mark" pos="23:20" rst="0">
          <comment>ID1</comment>
        </bits>
        <bits access="r" name="id5_interrupt_mark" pos="19:16" rst="0">
          <comment>ID1</comment>
        </bits>
        <bits access="r" name="id4_interrupt_mark" pos="15:12" rst="0">
          <comment>ID1</comment>
        </bits>
        <bits access="r" name="id3_interrupt_mark" pos="11:8" rst="0">
          <comment>ID1</comment>
        </bits>
        <bits access="r" name="id2_interrupt_mark" pos="7:4" rst="0">
          <comment>ID1</comment>
        </bits>
        <bits access="r" name="id1_interrupt_mark" pos="3:0" rst="0">
          <comment>ID110
bit[0]\offine
bit[1]
bit[2]AFC
bit[3]Agc_compare</comment>
        </bits>
      </reg>
      <reg name="measpwr_int_flag" protect="r">
        <bits access="r" name="interrupt_flag" pos="7:0" rst="0">
          <comment>bit[7:0]id8-id1
0
1</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_decpos1" protect="rw">
        <bits access="rw" name="decision_position3" pos="26:18" rst="0">
          <comment>ID13</comment>
        </bits>
        <bits access="rw" name="decision_position2" pos="17:9" rst="0">
          <comment>ID12</comment>
        </bits>
        <bits access="rw" name="decision_position1" pos="8:0" rst="0">
          <comment>ID11</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_decpos2" protect="rw">
        <bits access="rw" name="decision_position3" pos="26:18" rst="0">
          <comment>ID23</comment>
        </bits>
        <bits access="rw" name="decision_position2" pos="17:9" rst="0">
          <comment>ID22</comment>
        </bits>
        <bits access="rw" name="decision_position1" pos="8:0" rst="0">
          <comment>ID21</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_decpos3" protect="rw">
        <bits access="rw" name="decision_position3" pos="26:18" rst="0">
          <comment>ID33</comment>
        </bits>
        <bits access="rw" name="decision_position2" pos="17:9" rst="0">
          <comment>ID32</comment>
        </bits>
        <bits access="rw" name="decision_position1" pos="8:0" rst="0">
          <comment>ID31</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_decpos4" protect="rw">
        <bits access="rw" name="decision_position3" pos="26:18" rst="0">
          <comment>ID43</comment>
        </bits>
        <bits access="rw" name="decision_position2" pos="17:9" rst="0">
          <comment>ID42</comment>
        </bits>
        <bits access="rw" name="decision_position1" pos="8:0" rst="0">
          <comment>ID41</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_decpos5" protect="rw">
        <bits access="rw" name="decision_position3" pos="26:18" rst="0">
          <comment>ID53</comment>
        </bits>
        <bits access="rw" name="decision_position2" pos="17:9" rst="0">
          <comment>ID52</comment>
        </bits>
        <bits access="rw" name="decision_position1" pos="8:0" rst="0">
          <comment>ID51</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_decpos6" protect="rw">
        <bits access="rw" name="decision_position3" pos="26:18" rst="0">
          <comment>ID63</comment>
        </bits>
        <bits access="rw" name="decision_position2" pos="17:9" rst="0">
          <comment>ID62</comment>
        </bits>
        <bits access="rw" name="decision_position1" pos="8:0" rst="0">
          <comment>ID61</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_decpos7" protect="rw">
        <bits access="rw" name="decision_position3" pos="26:18" rst="0">
          <comment>ID73</comment>
        </bits>
        <bits access="rw" name="decision_position2" pos="17:9" rst="0">
          <comment>ID72</comment>
        </bits>
        <bits access="rw" name="decision_position1" pos="8:0" rst="0">
          <comment>ID71</comment>
        </bits>
      </reg>
      <reg name="measpwr_offline0_decpos8" protect="rw">
        <bits access="rw" name="decision_position3" pos="26:18" rst="0">
          <comment>ID83</comment>
        </bits>
        <bits access="rw" name="decision_position2" pos="17:9" rst="0">
          <comment>ID82</comment>
        </bits>
        <bits access="rw" name="decision_position1" pos="8:0" rst="0">
          <comment>ID81</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis_para2" protect="rw">
        <bits access="rw" name="rbis_correct" pos="29" rst="0">
          <comment>ID3-8 RBIS CORRECT
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_judge" pos="28" rst="0">
          <comment>ID3-8 RBIS JUDGE
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_en" pos="27" rst="0">
          <comment>ID3-8 RBIS
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_posen" pos="26" rst="0">
          <comment>ID3-8 RBIS
0
1</comment>
        </bits>
        <bits access="rw" name="rbis_num" pos="25:23" rst="0">
          <comment>ID3-8 RBIS
01
12
23
34
45</comment>
        </bits>
        <bits access="rw" name="rbis_dipos" pos="22:16" rst="0">
          <comment>ID3-8 RBIS</comment>
        </bits>
        <bits access="rw" name="rbis_factor" pos="15:0" rst="0">
          <comment>ID3-8 RBIS</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis2_out1" protect="r">
        <bits access="r" name="rbis_out3" pos="30:24" rst="0">
          <comment>ID24RBIPRB</comment>
        </bits>
        <bits access="r" name="rbis_out2" pos="22:16" rst="0">
          <comment>ID23RBIPRB</comment>
        </bits>
        <bits access="r" name="rbis_out1" pos="14:8" rst="0">
          <comment>ID22RBIPRB</comment>
        </bits>
        <bits access="r" name="rbis_out0" pos="6:0" rst="0">
          <comment>ID21RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis2_out2" protect="r">
        <bits access="r" name="rbis_num" pos="10:8" rst="0">
          <comment>ID2 RBIS JUDGE</comment>
        </bits>
        <bits access="r" name="rbis_out4" pos="6:0" rst="0">
          <comment>ID25RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis2_ave" protect="r">
        <bits access="r" name="rbis_ave" pos="31:0" rst="0">
          <comment>ID2 RBIS</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis2_max" protect="r">
        <bits access="r" name="rbis_max" pos="24:0" rst="0">
          <comment>ID2 RBIS</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis3_out1" protect="r">
        <bits access="r" name="rbis_out3" pos="30:24" rst="0">
          <comment>ID3-84RBIPRB</comment>
        </bits>
        <bits access="r" name="rbis_out2" pos="22:16" rst="0">
          <comment>ID3-83RBIPRB</comment>
        </bits>
        <bits access="r" name="rbis_out1" pos="14:8" rst="0">
          <comment>ID3-82RBIPRB</comment>
        </bits>
        <bits access="r" name="rbis_out0" pos="6:0" rst="0">
          <comment>ID3-81RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis3_out2" protect="r">
        <bits access="r" name="rbis_num" pos="10:8" rst="0">
          <comment>ID3-8 RBIS JUDGE</comment>
        </bits>
        <bits access="r" name="rbis_out4" pos="6:0" rst="0">
          <comment>ID3-85RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis3_ave" protect="r">
        <bits access="r" name="rbis_ave" pos="31:0" rst="0">
          <comment>ID3-8 RBIS</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis3_max" protect="r">
        <bits access="r" name="rbis_max" pos="24:0" rst="0">
          <comment>ID3-8 RBIS</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale2_th1" protect="rw">
        <bits access="rw" name="scaleth_1" pos="31:0" rst="0">
          <comment>1ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale2_th2" protect="rw">
        <bits access="rw" name="scaleth_2" pos="31:0" rst="0">
          <comment>2ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale2_th4" protect="rw">
        <bits access="rw" name="scaleth_4" pos="31:0" rst="0">
          <comment>4ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale2_th8" protect="rw">
        <bits access="rw" name="scaleth_8" pos="31:0" rst="0">
          <comment>8ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale2_th16" protect="rw">
        <bits access="rw" name="scaleth_16" pos="31:0" rst="0">
          <comment>16ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale2_th32" protect="rw">
        <bits access="rw" name="scaleth_32" pos="31:0" rst="0">
          <comment>32ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale2_th64" protect="rw">
        <bits access="rw" name="scaleth_64" pos="31:0" rst="0">
          <comment>64ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale2_th128" protect="rw">
        <bits access="rw" name="scaleth_128" pos="31:0" rst="0">
          <comment>128ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale2_th256" protect="rw">
        <bits access="rw" name="scaleth_256" pos="31:0" rst="0">
          <comment>256ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_scale2_th512" protect="rw">
        <bits access="rw" name="scaleth_512" pos="31:0" rst="0">
          <comment>512ScaleTh</comment>
        </bits>
      </reg>
      <reg name="measpwr_sigpwr_para2" protect="rw">
        <bits access="rw" name="sigpwr_renum" pos="7:0" rst="0">
          <comment>ID3-8 SIGPWR</comment>
        </bits>
      </reg>
      <reg name="measpwr_irt_para3" protect="rw">
        <bits access="rw" name="s_th" pos="31:16" rst="0">
          <comment>ID3-8</comment>
        </bits>
        <bits access="rw" name="n_th" pos="15:0" rst="0">
          <comment>id3-816q10</comment>
        </bits>
      </reg>
      <reg name="measpwr_trms_para3" protect="rw">
        <bits access="rw" name="s_th" pos="31:16" rst="0">
          <comment>ID3-816q15</comment>
        </bits>
        <bits access="rw" name="n_th" pos="15:0" rst="0">
          <comment>ID3-816q10</comment>
        </bits>
      </reg>
      <reg name="measpwr_rsrp_para5" protect="rw">
        <bits access="rw" name="beta" pos="31:16" rst="0">
          <comment>id3-8beta16Q10</comment>
        </bits>
        <bits access="rw" name="s_th" pos="15:0" rst="0">
          <comment>ID3-8</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis_in1" protect="rw">
        <bits access="rw" name="rbis_in3" pos="30:24" rst="0">
          <comment>ID14RBIPRB</comment>
        </bits>
        <bits access="rw" name="rbis_in2" pos="22:16" rst="0">
          <comment>ID13RBIPRB</comment>
        </bits>
        <bits access="r" name="reserced3" pos="15" rst="0">
      </bits>
        <bits access="rw" name="rbis_in1" pos="14:8" rst="0">
          <comment>ID12RBIPRB</comment>
        </bits>
        <bits access="rw" name="rbis_in0" pos="6:0" rst="0">
          <comment>ID11RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis_in2" protect="rw">
        <bits access="rw" name="rbis_in_num" pos="10:8" rst="0">
          <comment>ID1 RBIS JUDGE</comment>
        </bits>
        <bits access="rw" name="rbis_in4" pos="6:0" rst="0">
          <comment>ID15RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis2_in1" protect="rw">
        <bits access="rw" name="rbis_in3" pos="30:24" rst="0">
          <comment>ID24RBIPRB</comment>
        </bits>
        <bits access="rw" name="rbis_in2" pos="22:16" rst="0">
          <comment>ID23RBIPRB</comment>
        </bits>
        <bits access="r" name="reserced3" pos="15" rst="0">
      </bits>
        <bits access="rw" name="rbis_in1" pos="14:8" rst="0">
          <comment>ID22RBIPRB</comment>
        </bits>
        <bits access="rw" name="rbis_in0" pos="6:0" rst="0">
          <comment>ID21RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis2_in2" protect="rw">
        <bits access="rw" name="rbis_in_num" pos="10:8" rst="0">
          <comment>ID2 RBIS JUDGE</comment>
        </bits>
        <bits access="rw" name="rbis_in4" pos="6:0" rst="0">
          <comment>ID25RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis3_in1" protect="rw">
        <bits access="rw" name="rbis_in3" pos="30:24" rst="0">
          <comment>ID3-84RBIPRB</comment>
        </bits>
        <bits access="rw" name="rbis_in2" pos="22:16" rst="0">
          <comment>ID3-83RBIPRB</comment>
        </bits>
        <bits access="r" name="reserced3" pos="15" rst="0">
      </bits>
        <bits access="rw" name="rbis_in1" pos="14:8" rst="0">
          <comment>ID3-82RBIPRB</comment>
        </bits>
        <bits access="rw" name="rbis_in0" pos="6:0" rst="0">
          <comment>ID3-81RBIPRB</comment>
        </bits>
      </reg>
      <reg name="measpwr_rbis3_in2" protect="rw">
        <bits access="rw" name="rbis_in_num" pos="10:8" rst="0">
          <comment>ID3-8 RBIS JUDGE</comment>
        </bits>
        <bits access="rw" name="rbis_in4" pos="6:0" rst="0">
          <comment>ID3-85RBIPRB</comment>
        </bits>
      </reg>
      <hole size="1034944"/>
      <reg name="mem_in_1" protect="rw">
        <bits access="rw" name="mem_in_1_mem_in_1" pos="23:0" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="mem_in_2" protect="rw">
        <bits access="rw" name="mem_in_2_mem_in_2" pos="23:0" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="mem_in_3" protect="rw">
        <bits access="rw" name="mem_in_3_mem_in_3" pos="23:0" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="mem_in_4" protect="rw">
        <bits access="rw" name="mem_in_4_mem_in_4" pos="23:0" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="mem_in_5" protect="rw">
        <bits access="rw" name="mem_in_5_mem_in_5" pos="23:0" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="mem_in_6" protect="rw">
        <bits access="rw" name="mem_in_6_mem_in_6" pos="23:0" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="mem_in_7" protect="rw">
        <bits access="rw" name="mem_in_7_mem_in_7" pos="23:0" rst="0">
      </bits>
      </reg>
      <hole size="262112"/>
      <reg name="mem_in_8" protect="rw">
        <bits access="rw" name="mem_in_8_mem_in_8" pos="23:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_iddet.xml">
    <module category="LTE_SYS" name="CP_LTE_IDDET">
      <reg name="iddet_start" protect="rw">
        <bits access="rw" name="rd_pre_pwr" pos="27" rst="0">
          <comment>DMAIDDET
0:
1:</comment>
        </bits>
        <bits access="rw" name="save_last_pwr" pos="26" rst="0">
          <comment>DMAMEM
0:
1:</comment>
        </bits>
        <bits access="rw" name="sample_len" pos="25:12" rst="0">
          <comment>5ms+2OFDM
1~9856</comment>
        </bits>
        <bits access="rw" name="sample_num" pos="11:8" rst="0">
          <comment>4b000: 5ms+2OFDM
4b0001: 1
4b1111: 15</comment>
        </bits>
        <bits access="rw" name="rec_continuity" pos="7" rst="1">
          <comment>0:
1:</comment>
        </bits>
        <bits access="rw" name="flow_sel" pos="6:4" rst="0">
          <comment>3b001: PSS
3b010: PSS
3b011: SSS
3b100:
3b101:
3b110:</comment>
        </bits>
        <bits access="rw" name="txrx_offset_en" pos="3" rst="0">
          <comment>bit type is changed from r/w to rw.
          TXRXOFFSET
1:OFFSET
0:OFFSET</comment>
        </bits>
        <bits access="rw" name="data_move_out" pos="2" rst="0">
          <comment>1: TXRXDMA;
0: TXRXDMA</comment>
        </bits>
        <bits access="rw" name="iddet_stop" pos="1" rst="0">
          <comment>1: IDDET
0: IDDET</comment>
        </bits>
        <bits access="rw" name="iddet_start_iddet_start" pos="0" rst="0">
          <comment>1: IDDET
0: IDDET</comment>
        </bits>
      </reg>
      <reg name="pss1_ctrl" protect="rw">
        <bits access="rw" name="rssi_en" pos="16" rst="1">
          <comment>bit type is changed from r/w to rw.
          RSSI</comment>
        </bits>
        <bits access="rw" name="output_num" pos="15:12" rst="3">
          <comment>PSS.1~12512</comment>
        </bits>
        <bits access="rw" name="max_num" pos="10:8" rst="1">
          <comment>,1~5</comment>
        </bits>
        <bits access="rw" name="flow_mode_sel" pos="7" rst="0">
          <comment>0: ICS;1: IDDET</comment>
        </bits>
        <bits access="rw" name="ppm_en" pos="6" rst="1">
          <comment>0:  0:</comment>
        </bits>
        <bits access="rw" name="id_mode_sel" pos="5:4" rst="0">
          <comment>0: ID2  1: ID20  2: ID21  3: ID22</comment>
        </bits>
        <bits access="rw" name="localpss_freq_en" pos="3:2" rst="3">
          <comment>0:   1: 1
2: 3  3: 5</comment>
        </bits>
        <bits access="rw" name="dagc_en" pos="1" rst="1">
          <comment>0: AGC  1: AGC</comment>
        </bits>
        <bits access="rw" name="dc_en" pos="0" rst="1">
          <comment>0:    1:</comment>
        </bits>
      </reg>
      <reg name="pss2_ctrl" protect="rw">
        <bits access="rw" name="rssi_en" pos="8" rst="1">
          <comment>bit type is changed from r/w to rw.
          RSSI</comment>
        </bits>
        <bits access="rw" name="pos_num" pos="7:4" rst="3">
          <comment>1~12</comment>
        </bits>
        <bits access="rw" name="ppm_en" pos="3" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="localpss_freq_en" pos="2" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="dagc_en" pos="1" rst="1">
          <comment>1: AGC
0: AGC</comment>
        </bits>
        <bits access="rw" name="dc_en" pos="0" rst="1">
          <comment>1:
0:</comment>
        </bits>
      </reg>
      <reg name="sss_ctrl" protect="rw">
        <bits access="rw" name="rssi_en" pos="27" rst="1">
          <comment>bit type is changed from r/w to rw.
          RSSI</comment>
        </bits>
        <bits access="rw" name="pos_slide_num" pos="26:25" rst="0">
          <comment>bit type is changed from r/w to rw.
0:
1:1
2:2
3:4</comment>
        </bits>
        <bits access="rw" name="sort_sel" pos="24" rst="0">
          <comment>bit type is changed from r/w to rw.
          0:
1:</comment>
        </bits>
        <bits access="rw" name="normalsort_num" pos="23:20" rst="0">
          <comment>1~10</comment>
        </bits>
        <bits access="rw" name="nid1" pos="19:12" rst="0">
          <comment>NID1ID  0~168</comment>
        </bits>
        <bits access="rw" name="pos_num" pos="11:8" rst="3">
          <comment>ICSIDDET1~12</comment>
        </bits>
        <bits access="rw" name="ppm_en" pos="7" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="flow_mode_sel" pos="6" rst="0">
          <comment>0:ICS
1: ID DETECT</comment>
        </bits>
        <bits access="rw" name="id_mode_sel" pos="5" rst="0">
          <comment>1: ID   0: ID</comment>
        </bits>
        <bits access="rw" name="fdd_tdd_sel" pos="4" rst="0">
          <comment>1: FDD  0: TDD</comment>
        </bits>
        <bits access="rw" name="ic_en" pos="3" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="freq_en" pos="2" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="dagc_en" pos="1" rst="1">
          <comment>1: AGC
0: AGC</comment>
        </bits>
        <bits access="rw" name="dc_en" pos="0" rst="1">
          <comment>1:
0:</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_ctrl" protect="rw">
        <bits access="rw" name="rssi_en" pos="18" rst="1">
          <comment>RSSI</comment>
        </bits>
        <bits access="rw" name="pos_slide_num" pos="17:16" rst="0">
          <comment>0:
1:1
2:2
3:4</comment>
        </bits>
        <bits access="rw" name="pos_num" pos="15:12" rst="3">
          <comment>1~12</comment>
        </bits>
        <bits access="rw" name="slide_num" pos="10:8" rst="4">
          <comment>PSSSSSM0~4</comment>
        </bits>
        <bits access="rw" name="fdd_tdd_sel" pos="5" rst="0">
          <comment>1: FDD
0: TDD</comment>
        </bits>
        <bits access="rw" name="freq_en" pos="4" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="freqitm_en" pos="3" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="ppm_en" pos="2" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="dagc_en" pos="1" rst="1">
          <comment>1: AGC
0: AGC</comment>
        </bits>
        <bits access="rw" name="dc_en" pos="0" rst="1">
          <comment>1:
0:</comment>
        </bits>
      </reg>
      <reg name="resync_ctrl" protect="rw">
        <bits access="rw" name="rssi_en" pos="21" rst="1">
          <comment>RSSI</comment>
        </bits>
        <bits access="rw" name="data_len" pos="20:18" rst="1">
          <comment>0:1ms
1:2ms
2:3ms
3:4ms
4:5ms</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="17:16" rst="0">
          <comment>00:  01: 0   10: 5</comment>
        </bits>
        <bits access="rw" name="max_num" pos="14:12" rst="1">
          <comment>1~5</comment>
        </bits>
        <bits access="rw" name="id1" pos="11:4" rst="0">
          <comment>ID1  0~167</comment>
        </bits>
        <bits access="rw" name="id2" pos="3:2" rst="0">
          <comment>ID2  0~2</comment>
        </bits>
        <bits access="rw" name="dagc_en" pos="1" rst="1">
          <comment>0: AGC
1: AGC</comment>
        </bits>
        <bits access="rw" name="dc_en" pos="0" rst="1">
          <comment>0:
1:</comment>
        </bits>
      </reg>
      <reg name="shift_ctrl0" protect="rw">
        <bits access="rw" name="pwr_acc_s3" pos="31:28" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="rssi_s3" pos="27:24" rst="0">
          <comment>RSSI -8~7</comment>
        </bits>
        <bits access="rw" name="pwr_acc_s2" pos="23:20" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="rssi_s2" pos="19:16" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="pwr_acc_s1" pos="15:12" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="rssi_s1" pos="11:8" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="pwr_acc_s0" pos="7:4" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="rssi_s0" pos="3:0" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
      </reg>
      <reg name="shift_ctrl1" protect="rw">
        <bits access="rw" name="pwr_acc_s7" pos="31:28" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="rssi_s7" pos="27:24" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="pwr_acc_s6" pos="23:20" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="rssi_s6" pos="19:16" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="pwr_acc_s5" pos="15:12" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="rssi_s5" pos="11:8" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="pwr_acc_s4" pos="7:4" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="rssi_s4" pos="3:0" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
      </reg>
      <reg name="shift_ctrl2" protect="rw">
        <bits access="rw" name="pwr_acc_s9" pos="15:12" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="rssi_s9" pos="11:8" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="pwr_acc_s8" pos="7:4" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
        <bits access="rw" name="rssi_s8" pos="3:0" rst="0">
          <comment>RSSI  -8~7</comment>
        </bits>
      </reg>
      <reg name="int_ctrl" protect="rw">
        <bits access="rw" name="discon_section_fin_irq_en" pos="10" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="freq_search_irq_en" pos="9" rst="1">
          <comment>1: 1
0: 1</comment>
        </bits>
        <bits access="rw" name="rssi_en" pos="8" rst="1">
          <comment>1:RSSI
0: RSSI</comment>
        </bits>
        <bits access="rw" name="stop" pos="7" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="error_irq_en" pos="6" rst="1">
          <comment>1: AXIDMA
0: AXIDMA</comment>
        </bits>
        <bits access="rw" name="txrx_suspend_irq_en" pos="5" rst="1">
          <comment>1:TXRX
0: TXRX</comment>
        </bits>
        <bits access="rw" name="resync_fin_irq_en" pos="4" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="freq_idident_fin_irq_en" pos="3" rst="1">
          <comment>1:
0:</comment>
        </bits>
        <bits access="rw" name="sss_fin_irq_en" pos="2" rst="1">
          <comment>1:SSS
0: SSS</comment>
        </bits>
        <bits access="rw" name="pssitm_fin_irq_en" pos="1" rst="1">
          <comment>1:PSS
0: PSS</comment>
        </bits>
        <bits access="rw" name="pssgru_fin_irq_en" pos="0" rst="1">
          <comment>1:PSS
0: PSS</comment>
        </bits>
      </reg>
      <reg name="pos_offset" protect="rw">
        <bits access="rw" name="pss1_rssi_th" pos="31:16" rst="0">
          <comment>RSSI</comment>
        </bits>
        <bits access="rw" name="pssitm_sss_offset_pos" pos="14:0" rst="0">
          <comment>PSSTXRX0PSSSSSTXRX
00~19200</comment>
        </bits>
      </reg>
      <reg name="sam_num_ctrl1" protect="rw">
        <bits access="rw" name="sam_num" pos="7:0" rst="0">
          <comment>0~200</comment>
        </bits>
      </reg>
      <reg name="sam_num_ctrl2" protect="rw">
        <bits access="rw" name="sam_num" pos="7:0" rst="0">
          <comment>0~200</comment>
        </bits>
      </reg>
      <reg name="sam_num_ctrl3" protect="rw">
        <bits access="rw" name="sam_num" pos="7:0" rst="0">
          <comment>0~200</comment>
        </bits>
      </reg>
      <reg name="sam_num_ctrl4" protect="rw">
        <bits access="rw" name="sam_num" pos="7:0" rst="0">
          <comment>0~200</comment>
        </bits>
      </reg>
      <reg name="sam_num_ctrl5" protect="rw">
        <bits access="rw" name="sam_num" pos="7:0" rst="0">
          <comment>0~200</comment>
        </bits>
      </reg>
      <reg name="sam_num_ctrl6" protect="rw">
        <bits access="rw" name="sam_num" pos="7:0" rst="0">
          <comment>0~200</comment>
        </bits>
      </reg>
      <reg name="sam_num_ctrl7" protect="rw">
        <bits access="rw" name="sam_num" pos="7:0" rst="0">
          <comment>0~200</comment>
        </bits>
      </reg>
      <reg name="sam_num_ctrl8" protect="rw">
        <bits access="rw" name="sam_num" pos="7:0" rst="0">
          <comment>0~200</comment>
        </bits>
      </reg>
      <reg name="sam_num_ctrl9" protect="rw">
        <bits access="rw" name="sam_num" pos="7:0" rst="0">
          <comment>0~200</comment>
        </bits>
      </reg>
      <reg name="sam_num_ctrl10" protect="rw">
        <bits access="rw" name="sam_num" pos="7:0" rst="0">
          <comment>0~200</comment>
        </bits>
      </reg>
      <reg name="end_threshold1" protect="rw">
        <bits access="rw" name="end_threshold1_end_threshold1" pos="31:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="end_threshold0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="end_threshold2" protect="rw">
        <bits access="rw" name="end_threshold1" pos="31:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="end_threshold0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="end_threshold3" protect="rw">
        <bits access="rw" name="end_threshold1" pos="31:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="end_threshold0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="end_threshold4" protect="rw">
        <bits access="rw" name="end_threshold1" pos="31:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="end_threshold0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="end_threshold5" protect="rw">
        <bits access="rw" name="end_threshold1" pos="31:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="end_threshold0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="end_threshold6" protect="rw">
        <bits access="rw" name="end_threshold1" pos="31:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="end_threshold0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="end_threshold7" protect="rw">
        <bits access="rw" name="end_threshold1" pos="31:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="end_threshold0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="end_threshold8" protect="rw">
        <bits access="rw" name="end_threshold1" pos="31:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="end_threshold0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="end_threshold9" protect="rw">
        <bits access="rw" name="end_threshold1" pos="31:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="end_threshold0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="end_threshold10" protect="rw">
        <bits access="rw" name="end_threshold1" pos="31:16" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="end_threshold0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para1" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para2" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para3" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para4" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para5" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para6" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para7" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para8" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para9" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para10" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para11" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="pssitm_id_para12" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>PSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para1" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para2" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para3" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para4" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para5" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para6" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para7" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para8" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para9" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para10" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para11" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="sss_id_para12" protect="rw">
        <bits access="rw" name="pssgru_freqoff" pos="27:12" rst="0">
          <comment>PSSID-32768~32767</comment>
        </bits>
        <bits access="rw" name="pssgru_ppm" pos="9:4" rst="0">
          <comment>PSSID-32~31</comment>
        </bits>
        <bits access="rw" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)15  00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="1:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para1" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para2" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para3" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para4" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para5" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para6" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para7" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para8" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para9" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para10" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para11" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="freqitm_idident_para12" protect="rw">
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>NID1  0-167</comment>
        </bits>
      </reg>
      <reg name="id_postion1" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion2" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion3" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion4" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion5" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion6" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion7" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion8" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion9" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion10" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion11" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="id_postion12" protect="rw">
        <bits access="rw" name="id_pos" pos="13:0" rst="0">
          <comment>ID  0~9599</comment>
        </bits>
      </reg>
      <reg name="pss_sss_find" protect="rw">
        <bits access="rw" name="find_win" pos="27:24" rst="0">
          <comment>SSSMAX 10</comment>
        </bits>
        <bits access="rw" name="nois_win" pos="21:20" rst="0">
          <comment>0:31  1:61  2:127</comment>
        </bits>
        <bits access="rw" name="assist_win" pos="19:18" rst="0">
          <comment>IDDET PSSASSIST_WINMAX_NUMPOS_NUMPOS_NUM</comment>
        </bits>
        <bits access="rw" name="wipe_win" pos="17:16" rst="0">
          <comment>2b00:2  2b01:4  2b10:8 others:2</comment>
        </bits>
        <bits access="rw" name="p2p_win" pos="15:9" rst="0">
          <comment>0-127</comment>
        </bits>
        <bits access="rw" name="noisth_en" pos="8" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="nois_th" pos="7:0" rst="0">
          <comment>Q3</comment>
        </bits>
      </reg>
      <reg name="freq_pssgru1" protect="rw">
        <bits access="rw" name="freq_pssgru2" pos="29:20" rst="0">
          <comment>PSS2   -1024~1023</comment>
        </bits>
        <bits access="rw" name="freq_pssgru1_freq_pssgru1" pos="19:10" rst="56">
          <comment>PSS1   -1024~1023</comment>
        </bits>
        <bits access="rw" name="freq_pssgru0" pos="9:0" rst="47">
          <comment>PSS0   -1024~1023</comment>
        </bits>
      </reg>
      <reg name="freq_pssgru2" protect="rw">
        <bits access="rw" name="freq_pssgru4" pos="19:10" rst="17">
          <comment>PSS4   -1024~1023</comment>
        </bits>
        <bits access="rw" name="freq_pssgru3" pos="9:0" rst="8">
          <comment>PSS3   -1024~1023</comment>
        </bits>
      </reg>
      <reg name="freq_pssitm1" protect="rw">
        <bits access="rw" name="freq_pssitm" pos="12:0" rst="5192">
          <comment>PSS  -4096~4095</comment>
        </bits>
      </reg>
      <reg name="freq_pssitm2" protect="rw">
        <bits access="rw" name="freq_pssitm" pos="12:0" rst="7192">
          <comment>PSS  -4096~4095</comment>
        </bits>
      </reg>
      <reg name="freq_pssitm3" protect="rw">
        <bits access="rw" name="freq_pssitm" pos="12:0" rst="1000">
          <comment>PSS  -4096~4095</comment>
        </bits>
      </reg>
      <reg name="freq_pssitm4" protect="rw">
        <bits access="rw" name="freq_pssitm" pos="12:0" rst="3000">
          <comment>PSS  -4096~4095</comment>
        </bits>
      </reg>
      <reg name="rssi_target" protect="rw">
        <bits access="rw" name="rssi_target_rssi_target" pos="31:0" rst="3227">
          <comment>RSSI</comment>
        </bits>
      </reg>
      <reg name="ppm_gru_cfg1" protect="rw">
        <bits access="rw" name="ppm1" pos="13:8" rst="50">
          <comment>PSS  -32~31</comment>
        </bits>
        <bits access="rw" name="ppm0" pos="5:0" rst="46">
          <comment>PSS  -32~31</comment>
        </bits>
      </reg>
      <reg name="ppm_gru_cfg2" protect="rw">
        <bits access="rw" name="ppm1" pos="13:8" rst="58">
          <comment>PSS  -32~31</comment>
        </bits>
        <bits access="rw" name="ppm0" pos="5:0" rst="54">
          <comment>PSS  -32~31</comment>
        </bits>
      </reg>
      <reg name="ppm_gru_cfg3" protect="rw">
        <bits access="rw" name="ppm1" pos="13:8" rst="2">
          <comment>PSS  -32~31</comment>
        </bits>
        <bits access="rw" name="ppm0" pos="5:0" rst="62">
          <comment>PSS  -32~31</comment>
        </bits>
      </reg>
      <reg name="ppm_gru_cfg4" protect="rw">
        <bits access="rw" name="ppm1" pos="13:8" rst="10">
          <comment>PSS  -32~31</comment>
        </bits>
        <bits access="rw" name="ppm0" pos="5:0" rst="6">
          <comment>PSS  -32~31</comment>
        </bits>
      </reg>
      <reg name="ppm_gru_cfg5" protect="rw">
        <bits access="rw" name="ppm1" pos="13:8" rst="18">
          <comment>PSS  -32~31</comment>
        </bits>
        <bits access="rw" name="ppm0" pos="5:0" rst="14">
          <comment>PSS  -32~31</comment>
        </bits>
      </reg>
      <reg name="ppm_delt_cfg" protect="rw">
        <bits access="rw" name="delt_ppm3" pos="15:12" rst="3">
          <comment>-8~7</comment>
        </bits>
        <bits access="rw" name="delt_ppm2" pos="11:8" rst="1">
          <comment>-8~7</comment>
        </bits>
        <bits access="rw" name="delt_ppm1" pos="7:4" rst="15">
          <comment>-8~7</comment>
        </bits>
        <bits access="rw" name="delt_ppm0" pos="3:0" rst="13">
          <comment>-8~7</comment>
        </bits>
      </reg>
      <reg name="fft_cut" protect="rw">
        <bits access="rw" name="lnum_mod2" pos="7:4" rst="0">
          <comment>FFT/IFFT ()
4`b0000
4`b0001
4`b0010</comment>
        </bits>
        <bits access="rw" name="lnum_mod1" pos="3:0" rst="0">
          <comment>FFT/IFFT PSS/SSS
4`b0000
4`b0001
4`b0010</comment>
        </bits>
      </reg>
      <reg name="ic_id_para" protect="rw">
        <bits access="rw" name="freq_off_en" pos="28" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="rw" name="freq_off" pos="27:12" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="cptype" pos="11" rst="0">
          <comment>IDCP
1EXTEND CP   0NORMAL CP</comment>
        </bits>
        <bits access="rw" name="sfnum" pos="10" rst="0">
          <comment>ID(SSS)
15   00</comment>
        </bits>
        <bits access="rw" name="nid2" pos="9:8" rst="0">
          <comment>SSS</comment>
        </bits>
        <bits access="rw" name="nid1" pos="7:0" rst="0">
          <comment>SSS</comment>
        </bits>
      </reg>
      <reg name="ic_cfg" protect="rw">
        <bits access="rw" name="ic_ppm" pos="23:18" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="sssic_pos" pos="17:4" rst="0">
          <comment>SSS 9600</comment>
        </bits>
        <bits access="rw" name="ic_shift" pos="3:0" rst="0">
          <comment>0
11
22
-11
-22</comment>
        </bits>
      </reg>
      <reg name="freqitm_out0" protect="r">
        <bits access="r" name="freq_itm_out0" pos="15:0" rst="0">
          <comment>0</comment>
        </bits>
      </reg>
      <reg name="valid_node" protect="r">
        <bits access="r" name="valid_node1" pos="7:4" rst="0">
          <comment>SSS
00
11
1212</comment>
        </bits>
        <bits access="r" name="valid_node0" pos="3:0" rst="0">
          <comment>PSSPSSSSS
00
11
1212</comment>
        </bits>
      </reg>
      <reg name="sample_sum" protect="rw">
        <bits access="rw" name="sample_sum_sample_sum" pos="7:0" rst="0">
          <comment>PSSPSSSSS
0~200</comment>
        </bits>
      </reg>
      <reg name="rssi" protect="r">
        <bits access="r" name="rssi_rssi" pos="15:0" rst="0">
          <comment>PSSRSSIPSSSSS
RSSI</comment>
        </bits>
      </reg>
      <reg name="id_power_noise1" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise2" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise3" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise4" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise5" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise6" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise7" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise8" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise9" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise10" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise11" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_power_noise12" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="id_position_freq1" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq2" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq3" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq4" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq5" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq6" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq7" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq8" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq9" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq10" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq11" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_position_freq12" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="id_info1" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info2" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info3" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info4" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info5" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info6" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info7" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info8" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info9" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info10" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info11" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="id_info12" protect="r">
        <bits access="r" name="pos_index" pos="25:22" rst="0">
          <comment>SSS IDDET
0~11</comment>
        </bits>
        <bits access="r" name="pos_slide" pos="21:18" rst="0">
          <comment>0-8</comment>
        </bits>
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="assist_id_power_noise1" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="assist_id_power_noise2" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="assist_id_power_noise3" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="assist_id_power_noise4" protect="r">
        <bits access="r" name="noise" pos="31:16" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
        <bits access="r" name="power" pos="15:0" rst="0">
          <comment>PSSPSSSSS</comment>
        </bits>
      </reg>
      <reg name="assist_id_position_freq1" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="assist_id_position_freq2" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="assist_id_position_freq3" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="assist_id_position_freq4" protect="r">
        <bits access="r" name="freq_offset" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="postion" pos="13:0" rst="0">
          <comment>PSSPSSSSSID</comment>
        </bits>
      </reg>
      <reg name="assist_id_info1" protect="r">
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="assist_id_info2" protect="r">
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="assist_id_info3" protect="r">
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="assist_id_info4" protect="r">
        <bits access="r" name="ppm" pos="17:12" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="nid1" pos="11:4" rst="0">
          <comment>NID1
0-167</comment>
        </bits>
        <bits access="r" name="cptype" pos="3" rst="0">
          <comment>IDCP
1EXTEND CP
0NORMAL CP</comment>
        </bits>
        <bits access="r" name="sfnum" pos="2" rst="0">
          <comment>ID(SSS)
15
00</comment>
        </bits>
        <bits access="r" name="nid2" pos="1:0" rst="0">
          <comment>NID2
0-2</comment>
        </bits>
      </reg>
      <reg name="int_flag" protect="rw">
        <bits access="rc" name="discon_section_finish" pos="11" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:
0:</comment>
        </bits>
        <bits access="rc" name="freq_search" pos="10" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:
0:</comment>
        </bits>
        <bits access="rc" name="freq_search_sbi" pos="9" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:1
0:</comment>
        </bits>
        <bits access="rc" name="rssi" pos="8" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:RSSI
0: RSSI</comment>
        </bits>
        <bits access="rc" name="stop" pos="7" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:
0:</comment>
        </bits>
        <bits access="rc" name="error_state" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:AXIDMA
0:</comment>
        </bits>
        <bits access="rc" name="txrx_suspend" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:TXRX
0:</comment>
        </bits>
        <bits access="rc" name="resync_finish" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:
0:</comment>
        </bits>
        <bits access="rc" name="freq_idident_finish" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:
0:</comment>
        </bits>
        <bits access="rc" name="sss_finish" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:SSS
0:</comment>
        </bits>
        <bits access="rc" name="pssitm_finish" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:PSS
0:</comment>
        </bits>
        <bits access="rc" name="pssgru_finish" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:PSS
0:</comment>
        </bits>
      </reg>
      <reg name="sta_flag" protect="r">
        <bits access="r" name="freq_search_run" pos="5" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="r" name="resyn_run" pos="4" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="r" name="freqitm_idident_run" pos="3" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="r" name="sss_run" pos="2" rst="0">
          <comment>1
0</comment>
        </bits>
        <bits access="r" name="pss_itm_run" pos="1" rst="0">
          <comment>PSS
1
0</comment>
        </bits>
        <bits access="r" name="pss_gru_run" pos="0" rst="0">
          <comment>PSS
1
0</comment>
        </bits>
      </reg>
      <reg name="soft_use" protect="rw">
        <bits access="rw" name="soft_use_soft_use" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="pre_sample_count" protect="rw">
        <bits access="rw" name="pre_sample_count_pre_sample_count" pos="9:0" rst="0">
          <comment>0~1023</comment>
        </bits>
      </reg>
      <reg name="freq_search_ctrl" protect="rw">
        <bits access="rw" name="sort_mode" pos="26" rst="0">
          <comment>0:
1:</comment>
        </bits>
        <bits access="rw" name="fft_en" pos="25" rst="0">
          <comment>FFT
0: FFT
1: FFT(1024),FFT</comment>
        </bits>
        <bits access="rw" name="sort_en" pos="24" rst="0">
          <comment>:
0:
1: ,</comment>
        </bits>
        <bits access="rw" name="sort_end_addr" pos="23:14" rst="0">
          <comment>1~999</comment>
        </bits>
        <bits access="rw" name="sort_start_addr" pos="13:4" rst="0">
          <comment>0~999</comment>
        </bits>
        <bits access="rw" name="freq_sel" pos="3:2" rst="0">
          <comment>0: 5M
1: 10M
2: 20M
: 5M</comment>
        </bits>
        <bits access="rw" name="last_5ms" pos="1" rst="0">
          <comment>0: 5ms
1: 5ms</comment>
        </bits>
        <bits access="rw" name="first_5ms" pos="0" rst="0">
          <comment>0: 5ms
1: 5ms</comment>
        </bits>
      </reg>
      <reg name="freq_search_config1" protect="rw">
        <bits access="rw" name="pwrwin_32to20bitsel" pos="30:27" rst="9">
          <comment>;
0:[19:0],20bit
1:[20:1],20bit
12:[31:12],20bit
:12;</comment>
        </bits>
        <bits access="rw" name="pwr_32to16bitsel" pos="26:23" rst="0">
          <comment>,;I^2+Q^2=PWR(32bit)
0:[31:15],16bit
1:[31:14],16bit
15:[31:0],16bit</comment>
        </bits>
        <bits access="rw" name="cur_sbi_num" pos="22:17" rst="0">
          <comment>0~49</comment>
        </bits>
        <bits access="rw" name="sbi_max" pos="16:11" rst="0">
          <comment>0~50</comment>
        </bits>
        <bits access="rw" name="freq_20m_en" pos="10" rst="0">
          <comment>20MHz
0:
1:</comment>
        </bits>
        <bits access="rw" name="freq_15m_en" pos="9" rst="0">
          <comment>15MHz
0:
1:</comment>
        </bits>
        <bits access="rw" name="freq_10m_en" pos="8" rst="0">
          <comment>10MHz
0:
1:</comment>
        </bits>
        <bits access="rw" name="freq_5m_en" pos="7" rst="0">
          <comment>5MHz
0:
1:</comment>
        </bits>
        <bits access="rw" name="freq_3m_en" pos="6" rst="0">
          <comment>3MHz
0:
1:</comment>
        </bits>
        <bits access="rw" name="freq_1_4m_en" pos="5" rst="0">
          <comment>1.4MHz
0:
1:</comment>
        </bits>
        <bits access="rw" name="freq_200k_en" pos="4" rst="0">
          <comment>200KHz
0:
1:</comment>
        </bits>
        <bits access="rw" name="m" pos="3:0" rst="5">
          <comment>,1~11</comment>
        </bits>
      </reg>
      <reg name="freq_search_config2" protect="rw">
        <bits access="rw" name="selectbinnum_right" pos="17:9" rst="0">
          <comment>Selectbinnum0~511</comment>
        </bits>
        <bits access="rw" name="selectbinnum_left" pos="8:0" rst="0">
          <comment>selectbinnum0~511</comment>
        </bits>
      </reg>
      <reg name="band_win_start_conf1" protect="rw">
        <bits access="rw" name="band_5mhz" pos="27:21" rst="24">
          <comment>0~99</comment>
        </bits>
        <bits access="rw" name="band_3mhz" pos="20:14" rst="15">
          <comment>0~99</comment>
        </bits>
        <bits access="rw" name="band_1_4mhz" pos="13:7" rst="7">
          <comment>0~99</comment>
        </bits>
        <bits access="rw" name="band_200khz" pos="6:0" rst="2">
          <comment>0~99</comment>
        </bits>
      </reg>
      <reg name="band_win_start_conf2" protect="rw">
        <bits access="rw" name="band_20mhz" pos="20:14" rst="91">
          <comment>0~99</comment>
        </bits>
        <bits access="rw" name="band_15mhz" pos="13:7" rst="69">
          <comment>0~99</comment>
        </bits>
        <bits access="rw" name="band_10mhz" pos="6:0" rst="46">
          <comment>0~99</comment>
        </bits>
      </reg>
      <reg name="band_win_end_conf1" protect="rw">
        <bits access="rw" name="band_20mhz" pos="27:24" rst="9">
          <comment>0~15</comment>
        </bits>
        <bits access="rw" name="band_15mhz" pos="23:20" rst="6">
          <comment>0~15</comment>
        </bits>
        <bits access="rw" name="band_10mhz" pos="19:16" rst="4">
          <comment>0~15</comment>
        </bits>
        <bits access="rw" name="band_5mhz" pos="15:12" rst="1">
          <comment>0~15</comment>
        </bits>
        <bits access="rw" name="band_3mhz" pos="11:8" rst="0">
          <comment>0~15</comment>
        </bits>
        <bits access="rw" name="band_1_4mhz" pos="7:4" rst="0">
          <comment>0~15</comment>
        </bits>
        <bits access="rw" name="band_200khz" pos="3:0" rst="0">
          <comment>0~15</comment>
        </bits>
      </reg>
      <reg name="band_win_end_conf2" protect="r">
      </reg>
      <reg name="agc_conf" protect="rw">
        <bits access="rw" name="agc" pos="6:0" rst="0">
          <comment>0~127</comment>
        </bits>
      </reg>
      <reg name="sbi_sum_len" protect="rw">
        <bits access="rw" name="sbi_sum_len_sbi_sum_len" pos="9:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="target_agc" protect="rw">
        <bits access="rw" name="target_agc_target_agc" pos="9:0" rst="0">
          <comment>AGC</comment>
        </bits>
      </reg>
      <reg name="freqitm_out1" protect="r">
        <bits access="r" name="freq_itm_out2" pos="31:16" rst="0">
          <comment>2</comment>
        </bits>
        <bits access="r" name="freq_itm_out1" pos="15:0" rst="0">
          <comment>1</comment>
        </bits>
      </reg>
      <reg name="pss1_resyn_rssi_range" protect="rw">
        <bits access="rw" name="pss1_rssi_end" pos="29:16" rst="4799">
          <comment>bit type is changed from r/w to rw.
          PSSRSSI0~47990~9599</comment>
        </bits>
        <bits access="rw" name="pss1_rssi_start" pos="13:0" rst="0">
          <comment>bit type is changed from r/w to rw.
          PSSRSSI0~47990~9599</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi0" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi1" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi2" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi3" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi4" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi5" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi6" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi7" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi8" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi9" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi10" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <reg name="pss1_max_rssi11" protect="r">
        <bits access="r" name="pss1_max_rssi" pos="15:0" rst="0">
          <comment>PSSRSSI</comment>
        </bits>
      </reg>
      <hole size="27136"/>
      <reg name="mem8_9_mem10_11" protect="rw">
        <bits access="rw" name="mem8_9_mem10_11_mem8_9_mem10_11" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="mem12" protect="rw">
        <bits access="rw" name="mem12_mem12" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="mem15" protect="rw">
        <bits access="rw" name="mem15_mem15" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="memqf" protect="rw">
        <bits access="rw" name="memqf_memqf" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="mem1_8_mem1_11" protect="rw">
        <bits access="rw" name="mem1_8_mem1_11_1" pos="25:16" rst="0">
      </bits>
        <bits access="rw" name="mem1_8_mem1_11_2" pos="9:0" rst="0">
      </bits>
      </reg>
      <hole size="131040"/>
      <reg name="mem_freq_pwr_before_agc" protect="rw">
        <bits access="rw" name="mem_freq_pwr_before_agc_1" pos="31:16" rst="0">
          <comment>1PWR1</comment>
        </bits>
        <bits access="rw" name="mem_freq_pwr_before_agc_0" pos="15:0" rst="0">
          <comment>1PWR0</comment>
        </bits>
      </reg>
      <hole size="32736"/>
      <reg name="mem_freq_len_agc" protect="rw">
        <bits access="rw" name="mem_freq_len_agc_1" pos="18:10" rst="0">
          <comment>1</comment>
        </bits>
        <bits access="rw" name="mem_freq_len_agc_0" pos="9:0" rst="0">
          <comment>1AGC</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_csirs.xml">
    <module category="LTE_SYS" name="CP_LTE_CSIRS">
      <reg name="csi_start" protect="rw">
        <bits access="rw" name="data_drive_en" pos="2" rst="0">
          <comment>data_drive
0data_drive
1data_drive</comment>
        </bits>
        <bits access="rw" name="dma_start_en" pos="1" rst="0">
          <comment>DMACSI
0
1</comment>
        </bits>
        <bits access="rw" name="csi_en" pos="0" rst="0">
          <comment>CSI
0
1</comment>
        </bits>
      </reg>
      <reg name="csi_cfg_nxt" protect="rw">
        <bits access="rw" name="cp" pos="25" rst="0">
          <comment>cp
0
1</comment>
        </bits>
        <bits access="rw" name="fh_bit_sel" pos="24:20" rst="0">
          <comment>FH
5d0fh[11:0]
5d1fh[12:1]
5d2fh[13:2]
5d16fh[27:16]
othersfh[28:17]</comment>
        </bits>
        <bits access="rw" name="csi_crs_ind" pos="19" rst="0">
          <comment>CSI-RSCRS
0CSI-RS
1CRS</comment>
        </bits>
        <bits access="rw" name="ls_en" pos="18" rst="0">
          <comment>LS/FH/
0LS/FH/
1</comment>
        </bits>
        <bits access="rw" name="sw_ri" pos="17" rst="0">
          <comment>RIri_sel=1PMI
0RI=1
1RI=2</comment>
        </bits>
        <bits access="rw" name="ri_sel" pos="16" rst="0">
          <comment>PMIRI
0RI
1RI</comment>
        </bits>
        <bits access="rw" name="pmi_en" pos="15" rst="0">
          <comment>PMI
0PMI
1PMI</comment>
        </bits>
        <bits access="rw" name="ri_en" pos="14" rst="0">
          <comment>RI
0RI
1RI</comment>
        </bits>
        <bits access="rw" name="old_ri_ind" pos="13" rst="0">
          <comment>RIRI
0RI=1
1RI</comment>
        </bits>
        <bits access="rw" name="total_nrb" pos="12:6" rst="0">
          <comment>6/15/25/50/75/100PRB</comment>
        </bits>
        <bits access="rw" name="sub_nrb" pos="5:2" rst="0">
          <comment>total_nrb=6/15/25/50/75/100sub_nrb=6/2/2/3/4/4 PRB</comment>
        </bits>
        <bits access="rw" name="tx_num" pos="1:0" rst="0">
          <comment>CSI-RS1248CRS24
01RIPMI
12
24
38</comment>
        </bits>
      </reg>
      <reg name="csi_ri_threshold_nxt" protect="rw">
        <bits access="rw" name="th2_cfg" pos="30:16" rst="0">
          <comment>((1-th2)/(1+th2))^2RI01Q15th240</comment>
        </bits>
        <bits access="rw" name="th1_cfg" pos="14:0" rst="0">
          <comment>((1-th1)/(1+th1))^2RI01Q15th160</comment>
        </bits>
      </reg>
      <reg name="csi_code_index1_nxt" protect="rw">
        <bits access="rw" name="code_index1_mask2" pos="31:16" rst="0">
          <comment>RI=2248i1bitmapbit0~bit150~151</comment>
        </bits>
        <bits access="rw" name="code_index1_mask1" pos="15:0" rst="0">
          <comment>RI=1248i1bitmapbit0~bit150~151</comment>
        </bits>
      </reg>
      <reg name="csi_code_index2_nxt" protect="rw">
        <bits access="rw" name="code_index2_mask2" pos="31:16" rst="0">
          <comment>RI=28i2bitmapbit0~bit150~151</comment>
        </bits>
        <bits access="rw" name="code_index2_mask1" pos="15:0" rst="0">
          <comment>RI=18i2bitmapbit0~bit150~151</comment>
        </bits>
      </reg>
      <reg name="csi_inten_nxt" protect="rw">
        <bits access="rw" name="phy_factor" pos="7:4" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="csi_inten" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="csi_cinit1_nxt" protect="rw">
        <bits access="rw" name="cinit0" pos="30:0" rst="0">
          <comment>OFDM0CCSI-RS</comment>
        </bits>
      </reg>
      <reg name="csi_cinit2_nxt" protect="rw">
        <bits access="rw" name="cinit1" pos="30:0" rst="0">
          <comment>OFDM1CCSI-RS</comment>
        </bits>
      </reg>
      <reg name="csi_intf" protect="rw">
        <bits access="rc" name="phy_factor" pos="7:4" rst="0">
          <comment>bit type is changed from rw1c to rc.</comment>
        </bits>
        <bits access="rc" name="csi_intf" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
      </reg>
      <reg name="csi_sw_stop" protect="rw">
        <bits access="rw" name="sw_pause_way" pos="2" rst="0">
          <comment>sw_pause_en=1
0
1</comment>
        </bits>
        <bits access="rw" name="sw_pause_en" pos="1" rst="0">
          <comment>0
10</comment>
        </bits>
        <bits access="rw" name="sw_stop_en" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="csi_sw_stop_flag" protect="rw">
        <bits access="rc" name="sw_pause_flag" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
        <bits access="rc" name="sw_stop_flag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
      </reg>
      <reg name="csi_ri_rpt" protect="r">
        <bits access="r" name="ri_total_rpt" pos="0" rst="0">
          <comment>RIPRBRI
0RI=1
1RI=2</comment>
        </bits>
      </reg>
      <reg name="csi_pmi_rpt" protect="r">
        <bits access="r" name="pmi_total_rpt" pos="7:0" rst="0">
          <comment>PMIPRBPMI</comment>
        </bits>
      </reg>
      <reg name="csi_rx1_sig_rpt" protect="r">
        <bits access="r" name="rx1_sig_rpt" pos="27:0" rst="0">
          <comment>1</comment>
        </bits>
      </reg>
      <reg name="csi_rx2_sig_rpt" protect="r">
        <bits access="r" name="rx2_sig_rpt" pos="27:0" rst="0">
          <comment>2</comment>
        </bits>
      </reg>
      <reg name="csi_rx1_noise_rpt" protect="r">
        <bits access="r" name="rx1_noise_rpt" pos="29:0" rst="0">
          <comment>1</comment>
        </bits>
      </reg>
      <reg name="csi_rx2_noise_rpt" protect="r">
        <bits access="r" name="rx2_noise_rpt" pos="29:0" rst="0">
          <comment>2</comment>
        </bits>
      </reg>
      <reg name="csi_cfg_cur" protect="rw">
        <bits access="rw" name="cp" pos="25" rst="0">
          <comment>cp
0
1</comment>
        </bits>
        <bits access="rw" name="fh_bit_sel" pos="24:20" rst="0">
          <comment>FH
5d0fh[11:0]
5d1fh[12:1]
5d2fh[13:2]
5d16fh[27:16]
othersfh[28:17]</comment>
        </bits>
        <bits access="rw" name="csi_crs_ind" pos="19" rst="0">
          <comment>CSI-RSCRS
0CSI-RS
1CRS</comment>
        </bits>
        <bits access="rw" name="ls_en" pos="18" rst="0">
          <comment>LS/FH/
0LS/FH/
1</comment>
        </bits>
        <bits access="rw" name="sw_ri" pos="17" rst="0">
          <comment>RIri_sel=1PMI
0RI=1
1RI=2</comment>
        </bits>
        <bits access="rw" name="ri_sel" pos="16" rst="0">
          <comment>PMIRI
0RI
1RI</comment>
        </bits>
        <bits access="rw" name="pmi_en" pos="15" rst="0">
          <comment>PMI
0PMI
1PMI</comment>
        </bits>
        <bits access="rw" name="ri_en" pos="14" rst="0">
          <comment>RI
0RI
1RI</comment>
        </bits>
        <bits access="rw" name="old_ri_ind" pos="13" rst="0">
          <comment>RIRI
0RI=1
1RI</comment>
        </bits>
        <bits access="rw" name="total_nrb" pos="12:6" rst="0">
          <comment>6/15/25/50/75/100PRB</comment>
        </bits>
        <bits access="rw" name="sub_nrb" pos="5:2" rst="0">
          <comment>total_nrb=6/15/25/50/75/100sub_nrb=6/2/2/3/4/4 PRB</comment>
        </bits>
        <bits access="rw" name="tx_num" pos="1:0" rst="0">
          <comment>CSI-RS1248CRS24
01RIPMI
12
24
38</comment>
        </bits>
      </reg>
      <reg name="csi_ri_threshold_cur" protect="rw">
        <bits access="rw" name="th2_cfg" pos="30:16" rst="0">
          <comment>((1-th2)/(1+th2))^2RI01Q15th240</comment>
        </bits>
        <bits access="rw" name="th1_cfg" pos="14:0" rst="0">
          <comment>((1-th1)/(1+th1))^2RI01Q15th160</comment>
        </bits>
      </reg>
      <reg name="csi_code_index1_cur" protect="rw">
        <bits access="rw" name="code_index1_mask2" pos="31:16" rst="0">
          <comment>RI=2248i1bitmapbit0~bit150~151</comment>
        </bits>
        <bits access="rw" name="code_index1_mask1" pos="15:0" rst="0">
          <comment>RI=1248i1bitmapbit0~bit150~151</comment>
        </bits>
      </reg>
      <reg name="csi_code_index2_cur" protect="rw">
        <bits access="rw" name="code_index2_mask2" pos="31:16" rst="0">
          <comment>RI=28i2bitmapbit0~bit150~151</comment>
        </bits>
        <bits access="rw" name="code_index2_mask1" pos="15:0" rst="0">
          <comment>RI=18i2bitmapbit0~bit150~151</comment>
        </bits>
      </reg>
      <reg name="csi_inten_cur" protect="rw">
        <bits access="rw" name="csi_inten" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="csi_cinit1_cur" protect="rw">
        <bits access="rw" name="cinit0" pos="30:0" rst="0">
          <comment>OFDM0CCSI-RS</comment>
        </bits>
      </reg>
      <reg name="csi_cinit2_cur" protect="rw">
        <bits access="rw" name="cinit1" pos="30:0" rst="0">
          <comment>OFDM1CCSI-RS</comment>
        </bits>
      </reg>
      <hole size="261376"/>
      <reg name="rs_fh_mem1" protect="rw">
        <bits access="rw" name="rs_fh_mem1_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="rs_fh_mem1_2" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="rs_fh_mem2" protect="rw">
        <bits access="rw" name="rs_fh_mem2_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="rs_fh_mem2_2" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="hls_mem1" protect="rw">
        <bits access="rw" name="hls_mem1_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="hls_mem1_2" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="out_mem" protect="rw">
        <bits access="rw" name="out_mem_out_mem" pos="31:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_ulpcdci.xml">
    <module category="LTE_SYS" name="CP_LTE_ULPCDCI">
      <reg name="ulpcdci_ctrl" protect="rw">
        <bits access="rw" name="dci_int_en" pos="3" rst="0">
          <comment>0PUSCH
1PUSCH</comment>
        </bits>
        <bits access="rw" name="ulpc_int_en" pos="2" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="dci_start" pos="1" rst="0">
          <comment>0PUSCH
1PUSCH</comment>
        </bits>
        <bits access="rw" name="ulpc_start" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="ulpcdci_irq_flag" protect="rw">
        <bits access="rc" name="dci_irq_flag" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          DCI
0
1</comment>
        </bits>
        <bits access="rc" name="ulpc_irq_flag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          ULPC
0
1</comment>
        </bits>
      </reg>
      <reg name="dci_para1" protect="rw">
        <bits access="rw" name="rad_frame" pos="29:20" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="sub_frame" pos="19:16" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="prb_num" pos="15:9" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="cell_id" pos="8:0" rst="0">
          <comment>ID</comment>
        </bits>
      </reg>
      <reg name="dci_para2" protect="rw">
        <bits access="rw" name="res_block_alloc" pos="29:16" rst="0">
          <comment>DCI Format 0
6PRB5bit
15PRB7bit
25PRB9bit
50PRB11bit
75PRB12bit
100PRB13bit
DCI Format 4
6PRB6bit
15PRB7bit
25PRB10bit
50PRB12bit
75PRB13bit
100PRB14bit</comment>
        </bits>
        <bits access="rw" name="hopping_offset" pos="13:7" rst="0">
          <comment>PUSCH</comment>
        </bits>
        <bits access="rw" name="sub_baud" pos="6:4" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="hopping_mode" pos="3" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="hopping_flag" pos="2" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="res_alloc_type" pos="1" rst="0">
          <comment>00
11</comment>
        </bits>
        <bits access="rw" name="sys_mode" pos="0" rst="0">
          <comment>0TDD
1FDD</comment>
        </bits>
      </reg>
      <reg name="dci_result" protect="r">
        <bits access="r" name="len1" pos="30:24" rst="0">
          <comment>type0PRBtype1PRB</comment>
        </bits>
        <bits access="r" name="start1" pos="22:16" rst="0">
          <comment>type0type0Type20type1PRB</comment>
        </bits>
        <bits access="r" name="len2" pos="14:8" rst="0">
          <comment>type0PRBLen1type1PRB</comment>
        </bits>
        <bits access="r" name="start2" pos="6:0" rst="0">
          <comment>type0type0Type21type1PRB</comment>
        </bits>
      </reg>
      <reg name="dci_prb_len" protect="r">
        <bits access="r" name="prb_len" pos="6:0" rst="0">
          <comment>PUSCHPRB
type0PRBLen = Len1 = Len2
type1PRBLen = Len1+Len2</comment>
        </bits>
      </reg>
      <reg name="ulpc_conf" protect="rw">
        <bits access="rw" name="pwr_fci" pos="29:23" rst="0">
          <comment>-6363</comment>
        </bits>
        <bits access="rw" name="pwr_max_calc" pos="22:15" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="pwr_max_conf" pos="14:8" rst="0">
          <comment>UE-3033dBm</comment>
        </bits>
        <bits access="rw" name="alpha" pos="7:5" rst="0">
          <comment>0000
0010.4
0100.5
0110.6
1000.7
1010.8
1100.9
1111</comment>
        </bits>
        <bits access="rw" name="ks" pos="4" rst="0">
          <comment>UE
0Ks0
1Ks1.25</comment>
        </bits>
        <bits access="rw" name="cell_type" pos="3:1" rst="0">
          <comment>000PRACH
001PUSCH
010PUCCH
011PUSCHPUCCH
100SRS
101PUSCHSRS
110PUCCHSRS
111PUSCHPUCCHSRS</comment>
        </bits>
        <bits access="rw" name="cell_index" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="ulpc_rsrp" protect="rw">
        <bits access="rw" name="his_filter_rsrp" pos="28:16" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="init_rsrp" pos="8:0" rst="0">
          <comment>-140dBm-44dBm</comment>
        </bits>
      </reg>
      <reg name="ulpc_ref_pwr" protect="rw">
        <bits access="rw" name="dl_ref_pwr" pos="22:16" rst="0">
          <comment>-60dBm50dBm</comment>
        </bits>
        <bits access="rw" name="ul_ref_pwr" pos="8:0" rst="0">
          <comment>PUSCH-134dBm31dBm</comment>
        </bits>
      </reg>
      <reg name="ulpc_prb" protect="rw">
        <bits access="rw" name="prb_num" pos="22:16" rst="0">
          <comment>PUSCHPRB</comment>
        </bits>
        <bits access="rw" name="sc_init" pos="14:4" rst="0">
          <comment>PUSCH121200</comment>
        </bits>
        <bits access="rw" name="symb_init" pos="3:0" rst="0">
          <comment>PUSCH9101112</comment>
        </bits>
      </reg>
      <reg name="ulpc_tbsize" protect="rw">
        <bits access="rw" name="tb_size" pos="16:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="ulpc_fliter_coeff" protect="rw">
        <bits access="rw" name="cqi_offset" pos="29:24" rst="0">
          <comment>CQI050</comment>
        </bits>
        <bits access="rw" name="cqi_bitlen" pos="23:16" rst="0">
          <comment>CRCCQI</comment>
        </bits>
        <bits access="rw" name="filter_coeff" pos="15:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="ulpc_pucch_para1" protect="rw">
        <bits access="rw" name="pucch_ref_pwr" pos="28:20" rst="0">
          <comment>PUCCH-135-89</comment>
        </bits>
        <bits access="rw" name="sr_en" pos="19" rst="0">
          <comment>0SR
1SR</comment>
        </bits>
        <bits access="rw" name="pwr_gi" pos="18:12" rst="0">
          <comment>-6363</comment>
        </bits>
        <bits access="rw" name="cp_type" pos="11" rst="0">
          <comment>0CP
1CP</comment>
        </bits>
        <bits access="rw" name="pwr_fator2" pos="10:8" rst="0">
          <comment>-22</comment>
        </bits>
        <bits access="rw" name="pwr_fator1" pos="7:4" rst="0">
          <comment>-26</comment>
        </bits>
        <bits access="rw" name="ant_type" pos="3" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="pucch_format" pos="2:0" rst="0">
          <comment>PUCCH
000PUCCH1
001PUCCH1a
010PUCCH1b
011PUCCH2
100PUCCH2a
101PUCCH2b
110PUCCH3
111RESERVED</comment>
        </bits>
      </reg>
      <reg name="ulpc_pucch_para2" protect="rw">
        <bits access="rw" name="harq_bitlen" pos="12:8" rst="0">
          <comment>HARQ</comment>
        </bits>
        <bits access="rw" name="puc_cqi_bitlen" pos="7:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="ulpc_srs" protect="rw">
        <bits access="rw" name="srs_prb" pos="11:5" rst="0">
          <comment>SRS</comment>
        </bits>
        <bits access="rw" name="srs_offset" pos="4:0" rst="0">
          <comment>SRSPUSCH</comment>
        </bits>
      </reg>
      <reg name="ulpc_prach" protect="rw">
        <bits access="rw" name="path_loss" pos="23:16" rst="0">
          <comment>0140</comment>
        </bits>
        <bits access="rw" name="pwr_step" pos="15:14" rst="0">
          <comment>000
012
104
116</comment>
        </bits>
        <bits access="rw" name="delta_preamble" pos="13:12" rst="0">
          <comment>000
01-3
108
11RESERVED</comment>
        </bits>
        <bits access="rw" name="prach_ref_pwr" pos="11:8" rst="0">
          <comment>PRACH
0000-120
0001-118
0010-116
0011-114
0100-112
0101-110
0110-108
0111-106
1000-104
1001-102
1010-100
1011-98
1100-96
1101-94
1110-92
1111-90</comment>
        </bits>
        <bits access="rw" name="preamble_trans_cnt" pos="7:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="ulpc_send_pwr1" protect="r">
        <bits access="r" name="srs_pwr" pos="26:16" rst="0">
          <comment>SRS</comment>
        </bits>
        <bits access="r" name="pusch_pwr" pos="10:0" rst="0">
          <comment>PUSCH</comment>
        </bits>
      </reg>
      <reg name="ulpc_send_pwr2" protect="r">
        <bits access="r" name="prach_pwr" pos="26:16" rst="0">
          <comment>PRACH</comment>
        </bits>
        <bits access="r" name="pucch_pwr" pos="10:0" rst="0">
          <comment>PUCCH</comment>
        </bits>
      </reg>
      <reg name="ulpc_pus_pwr_line" protect="r">
        <bits access="r" name="pusch_pwr_line" pos="19:0" rst="0">
          <comment>PUSCH</comment>
        </bits>
      </reg>
      <reg name="ulpc_srs_pwr_line" protect="r">
        <bits access="r" name="srs_pwr_line" pos="19:0" rst="0">
          <comment>SRS</comment>
        </bits>
      </reg>
      <reg name="ulpc_puc_pwr_line" protect="r">
        <bits access="r" name="pucch_pwr_line" pos="19:0" rst="0">
          <comment>PUCCH</comment>
        </bits>
      </reg>
      <reg name="ulpc_pcmax_pwr_line" protect="r">
        <bits access="r" name="pcmax_pwr_line" pos="19:0" rst="0">
          <comment>UE</comment>
        </bits>
      </reg>
      <reg name="ulpc_phr_type" protect="r">
        <bits access="r" name="phr_type2" pos="22:16" rst="0">
          <comment>PHR Type2</comment>
        </bits>
        <bits access="r" name="phr_type1" pos="6:0" rst="0">
          <comment>PHR Type1</comment>
        </bits>
      </reg>
      <reg name="ulpc_tfci" protect="r">
        <bits access="r" name="cur_filter_rsrp" pos="28:16" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="ulpc_tfci_ulpc_tfci" pos="10:0" rst="0">
          <comment>TF_CI</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_corr.xml">
    <module category="LTE_SYS" name="CP_LTE_CORR">
      <reg name="corr_para" protect="rw">
        <bits access="rw" name="corr_loclen" pos="24:16" rst="0">
          <comment>max384</comment>
        </bits>
        <bits access="rw" name="corr_reclen" pos="15:4" rst="0">
          <comment>max2800</comment>
        </bits>
        <bits access="rw" name="corr_idnum" pos="3:0" rst="0">
          <comment>IDmax10</comment>
        </bits>
      </reg>
      <reg name="corr_start" protect="rw">
        <bits access="rw" name="corr_start_corr_start" pos="0" rst="0">
          <comment>1
0</comment>
        </bits>
      </reg>
      <reg name="corr_out" protect="r">
        <bits access="r" name="corr_pp" pos="16" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="r" name="corr_pos" pos="15:4" rst="0">
          <comment>max2800</comment>
        </bits>
        <bits access="r" name="corr_id" pos="3:0" rst="0">
          <comment>IDmax10</comment>
        </bits>
      </reg>
      <reg name="corr_max" protect="r">
        <bits access="r" name="corr_max_corr_max" pos="23:0" rst="0">
          <comment>CORR_MAX</comment>
        </bits>
      </reg>
      <reg name="corr_sum" protect="r">
        <bits access="r" name="corr_sum_corr_sum" pos="31:0" rst="0">
          <comment>CORR_SUM</comment>
        </bits>
      </reg>
      <reg name="int_en" protect="rw">
        <bits access="rw" name="int_en_int_en" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="int_flag" protect="rw">
        <bits access="rc" name="int_flag_int_flag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
0
1</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_otdoa.xml">
    <module category="LTE_SYS" name="CP_LTE_OTDOA">
      <reg name="otdoa_sys_offset1" protect="rw">
        <bits access="rw" name="otdoaon2validdata_offset" pos="14:0" rst="0">
          <comment>0~30720TS</comment>
        </bits>
      </reg>
      <reg name="otdoa_sys_offset2" protect="rw">
        <bits access="rw" name="otdoaon2rcrfh_offset" pos="19:0" rst="0">
          <comment>-30720x13.8 ~30720x13.8TS</comment>
        </bits>
      </reg>
      <reg name="otdoa_sys_para1" protect="rw">
        <bits access="rw" name="catm_ca1_sel" pos="12" rst="0">
          <comment>0:catm
1:cat1</comment>
        </bits>
        <bits access="rw" name="bw_index" pos="11:10" rst="0">
          <comment>0:1.4M
1:3M
2:5M
:5M</comment>
        </bits>
        <bits access="rw" name="prs_hprb_start" pos="9:2" rst="0">
          <comment>PRSPRB100PRB200PRB0~199</comment>
        </bits>
        <bits access="rw" name="ref_sel" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="slide_length" pos="0" rst="0">
          <comment>0512
1256</comment>
        </bits>
      </reg>
      <reg name="otdoa_sys_para2" protect="rw">
        <bits access="rw" name="first_occasion" pos="23:0" rst="0">
          <comment>0occasion
1occasion
[0]ID1
[23]ID24</comment>
        </bits>
      </reg>
      <reg name="otdoa_sys_para3" protect="rw">
        <bits access="rw" name="id_valid_bitmap" pos="23:0" rst="0">
          <comment>ID
0ID
1ID
[0]ID1
[23]ID24</comment>
        </bits>
      </reg>
      <reg name="otdoa_sys_para4" protect="rw">
        <bits access="rw" name="id_en_bitmap" pos="23:0" rst="0">
          <comment>ID
0ID
1ID
[0]ID1
[23]ID24</comment>
        </bits>
      </reg>
      <reg name="otdoa_sys_rxmem_len" protect="rw">
        <bits access="rw" name="rx_len" pos="18:0" rst="0">
          <comment>eg1IQ</comment>
        </bits>
      </reg>
      <reg name="otdoa_sys_agc" protect="rw">
        <bits access="rw" name="agc" pos="9:0" rst="0">
          <comment>occasionAGC</comment>
        </bits>
      </reg>
      <reg name="otdoa_id1_para1" protect="rw">
        <bits access="rw" name="sf_num_id1" pos="21:18" rst="0">
          <comment>occasionID10~120ID1SF_ID1</comment>
        </bits>
        <bits access="rw" name="sf_id1" pos="17:14" rst="0">
          <comment>occasionID210~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id1" pos="13:2" rst="0">
          <comment>PRSID2ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id1" pos="1" rst="0">
          <comment>ID1
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id1" pos="0" rst="0">
          <comment>ID1CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id1_para2" protect="rw">
        <bits access="rw" name="certain_id1" pos="29:13" rst="0">
          <comment>ID1certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id1" pos="12:0" rst="0">
          <comment>ID1uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id2_para1" protect="rw">
        <bits access="rw" name="sf_num_id2" pos="21:18" rst="0">
          <comment>occasionID20~120ID2SF_ID2</comment>
        </bits>
        <bits access="rw" name="sf_id2" pos="17:14" rst="0">
          <comment>occasionID210~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id2" pos="13:2" rst="0">
          <comment>PRSID2ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id2" pos="1" rst="0">
          <comment>ID2
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id2" pos="0" rst="0">
          <comment>ID2CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id2_para2" protect="rw">
        <bits access="rw" name="certain_id2" pos="29:13" rst="0">
          <comment>ID2certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id2" pos="12:0" rst="0">
          <comment>ID2uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id3_para1" protect="rw">
        <bits access="rw" name="sf_num_id3" pos="21:18" rst="0">
          <comment>occasionID30~120ID3SF_ID3</comment>
        </bits>
        <bits access="rw" name="sf_id3" pos="17:14" rst="0">
          <comment>occasionID310~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id3" pos="13:2" rst="0">
          <comment>PRSID3ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id3" pos="1" rst="0">
          <comment>ID3
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id3" pos="0" rst="0">
          <comment>ID3CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id3_para2" protect="rw">
        <bits access="rw" name="certain_id3" pos="29:13" rst="0">
          <comment>ID3certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id3" pos="12:0" rst="0">
          <comment>ID3uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id4_para1" protect="rw">
        <bits access="rw" name="sf_num_id4" pos="21:18" rst="0">
          <comment>occasionID40~120ID4SF_ID4</comment>
        </bits>
        <bits access="rw" name="sf_id4" pos="17:14" rst="0">
          <comment>occasionID410~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id4" pos="13:2" rst="0">
          <comment>PRSID4ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id4" pos="1" rst="0">
          <comment>ID4
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id4" pos="0" rst="0">
          <comment>ID4CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id4_para2" protect="rw">
        <bits access="rw" name="certain_id4" pos="29:13" rst="0">
          <comment>ID4certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id4" pos="12:0" rst="0">
          <comment>ID4uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id5_para1" protect="rw">
        <bits access="rw" name="sf_num_id5" pos="21:18" rst="0">
          <comment>occasionID50~120ID5SF_ID5</comment>
        </bits>
        <bits access="rw" name="sf_id5" pos="17:14" rst="0">
          <comment>occasionID510~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id5" pos="13:2" rst="0">
          <comment>PRSID5ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id5" pos="1" rst="0">
          <comment>ID5
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id5" pos="0" rst="0">
          <comment>ID5CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id5_para2" protect="rw">
        <bits access="rw" name="certain_id5" pos="29:13" rst="0">
          <comment>ID5certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id5" pos="12:0" rst="0">
          <comment>ID5uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id6_para1" protect="rw">
        <bits access="rw" name="sf_num_id6" pos="21:18" rst="0">
          <comment>occasionID60~120ID6SF_ID6</comment>
        </bits>
        <bits access="rw" name="sf_id6" pos="17:14" rst="0">
          <comment>occasionID610~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id6" pos="13:2" rst="0">
          <comment>PRSID6ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id6" pos="1" rst="0">
          <comment>ID6
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id6" pos="0" rst="0">
          <comment>ID6CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id6_para2" protect="rw">
        <bits access="rw" name="certain_id6" pos="29:13" rst="0">
          <comment>ID6certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id6" pos="12:0" rst="0">
          <comment>ID6uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id7_para1" protect="rw">
        <bits access="rw" name="sf_num_id7" pos="21:18" rst="0">
          <comment>occasionID70~120ID7SF_ID7</comment>
        </bits>
        <bits access="rw" name="sf_id7" pos="17:14" rst="0">
          <comment>occasionID710~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id7" pos="13:2" rst="0">
          <comment>PRSID7ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id7" pos="1" rst="0">
          <comment>ID7
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id7" pos="0" rst="0">
          <comment>ID7CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id7_para2" protect="rw">
        <bits access="rw" name="certain_id7" pos="29:13" rst="0">
          <comment>ID7certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id7" pos="12:0" rst="0">
          <comment>ID7uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id8_para1" protect="rw">
        <bits access="rw" name="sf_num_id8" pos="21:18" rst="0">
          <comment>occasionID80~120ID8SF_ID8</comment>
        </bits>
        <bits access="rw" name="sf_id8" pos="17:14" rst="0">
          <comment>occasionID810~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id8" pos="13:2" rst="0">
          <comment>PRSID8ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id8" pos="1" rst="0">
          <comment>ID8
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id8" pos="0" rst="0">
          <comment>ID8CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id8_para2" protect="rw">
        <bits access="rw" name="certain_id8" pos="29:13" rst="0">
          <comment>ID8certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id8" pos="12:0" rst="0">
          <comment>ID8uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id9_para1" protect="rw">
        <bits access="rw" name="sf_num_id9" pos="21:18" rst="0">
          <comment>occasionID90~120ID9SF_ID9</comment>
        </bits>
        <bits access="rw" name="sf_id9" pos="17:14" rst="0">
          <comment>occasionID910~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id9" pos="13:2" rst="0">
          <comment>PRSID9ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id9" pos="1" rst="0">
          <comment>ID9
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id9" pos="0" rst="0">
          <comment>ID9CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id9_para2" protect="rw">
        <bits access="rw" name="certain_id9" pos="29:13" rst="0">
          <comment>ID9certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id9" pos="12:0" rst="0">
          <comment>ID9uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id10_para1" protect="rw">
        <bits access="rw" name="sf_num_id10" pos="21:18" rst="0">
          <comment>occasionID100~120ID10SF_ID10</comment>
        </bits>
        <bits access="rw" name="sf_id10" pos="17:14" rst="0">
          <comment>occasionID1010~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id10" pos="13:2" rst="0">
          <comment>PRSID10ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id10" pos="1" rst="0">
          <comment>ID10
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id10" pos="0" rst="0">
          <comment>ID10CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id10_para2" protect="rw">
        <bits access="rw" name="certain_id10" pos="29:13" rst="0">
          <comment>ID10certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id10" pos="12:0" rst="0">
          <comment>ID10uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id11_para1" protect="rw">
        <bits access="rw" name="sf_num_id11" pos="21:18" rst="0">
          <comment>occasionID110~120ID11SF_ID11</comment>
        </bits>
        <bits access="rw" name="sf_id11" pos="17:14" rst="0">
          <comment>occasionID1110~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id11" pos="13:2" rst="0">
          <comment>PRSID11ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id11" pos="1" rst="0">
          <comment>ID11
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id11" pos="0" rst="0">
          <comment>ID11CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id11_para2" protect="rw">
        <bits access="rw" name="certain_id11" pos="29:13" rst="0">
          <comment>ID11certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id11" pos="12:0" rst="0">
          <comment>ID11uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id12_para1" protect="rw">
        <bits access="rw" name="sf_num_id12" pos="21:18" rst="0">
          <comment>occasionID120~120ID12SF_ID12</comment>
        </bits>
        <bits access="rw" name="sf_id12" pos="17:14" rst="0">
          <comment>occasionID1210~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id12" pos="13:2" rst="0">
          <comment>PRSID12ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id12" pos="1" rst="0">
          <comment>ID12
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id12" pos="0" rst="0">
          <comment>ID12CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id12_para2" protect="rw">
        <bits access="rw" name="certain_id12" pos="29:13" rst="0">
          <comment>ID12certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id12" pos="12:0" rst="0">
          <comment>ID12uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id13_para1" protect="rw">
        <bits access="rw" name="sf_num_id13" pos="21:18" rst="0">
          <comment>occasionID130~120ID13SF_ID13</comment>
        </bits>
        <bits access="rw" name="sf_id13" pos="17:14" rst="0">
          <comment>occasionID1310~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id13" pos="13:2" rst="0">
          <comment>PRSID13ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id13" pos="1" rst="0">
          <comment>ID13
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id13" pos="0" rst="0">
          <comment>ID13CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id13_para2" protect="rw">
        <bits access="rw" name="certain_id13" pos="29:13" rst="0">
          <comment>ID13certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id13" pos="12:0" rst="0">
          <comment>ID13uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id14_para1" protect="rw">
        <bits access="rw" name="sf_num_id14" pos="21:18" rst="0">
          <comment>occasionID140~120ID14SF_ID14</comment>
        </bits>
        <bits access="rw" name="sf_id14" pos="17:14" rst="0">
          <comment>occasionID1410~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id14" pos="13:2" rst="0">
          <comment>PRSID14ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id14" pos="1" rst="0">
          <comment>ID14
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id14" pos="0" rst="0">
          <comment>ID14CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id14_para2" protect="rw">
        <bits access="rw" name="certain_id14" pos="29:13" rst="0">
          <comment>ID14certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id14" pos="12:0" rst="0">
          <comment>ID14uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id15_para1" protect="rw">
        <bits access="rw" name="sf_num_id15" pos="21:18" rst="0">
          <comment>occasionID150~120ID15SF_ID15</comment>
        </bits>
        <bits access="rw" name="sf_id15" pos="17:14" rst="0">
          <comment>occasionID1510~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id15" pos="13:2" rst="0">
          <comment>PRSID15ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id15" pos="1" rst="0">
          <comment>ID15
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id15" pos="0" rst="0">
          <comment>ID15CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id15_para2" protect="rw">
        <bits access="rw" name="certain_id15" pos="29:13" rst="0">
          <comment>ID15certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id15" pos="12:0" rst="0">
          <comment>ID15uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id16_para1" protect="rw">
        <bits access="rw" name="sf_num_id16" pos="21:18" rst="0">
          <comment>occasionID160~120ID16SF_ID16</comment>
        </bits>
        <bits access="rw" name="sf_id16" pos="17:14" rst="0">
          <comment>occasionID1610~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id16" pos="13:2" rst="0">
          <comment>PRSID16ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id16" pos="1" rst="0">
          <comment>ID16
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id16" pos="0" rst="0">
          <comment>ID16CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id16_para2" protect="rw">
        <bits access="rw" name="certain_id16" pos="29:13" rst="0">
          <comment>ID16certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id16" pos="12:0" rst="0">
          <comment>ID16uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id17_para1" protect="rw">
        <bits access="rw" name="sf_num_id17" pos="21:18" rst="0">
          <comment>occasionID170~120ID17SF_ID17</comment>
        </bits>
        <bits access="rw" name="sf_id17" pos="17:14" rst="0">
          <comment>occasionID1710~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id17" pos="13:2" rst="0">
          <comment>PRSID17ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id17" pos="1" rst="0">
          <comment>ID17
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id17" pos="0" rst="0">
          <comment>ID17CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id17_para2" protect="rw">
        <bits access="rw" name="certain_id17" pos="29:13" rst="0">
          <comment>ID17certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id17" pos="12:0" rst="0">
          <comment>ID17uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id18_para1" protect="rw">
        <bits access="rw" name="sf_num_id18" pos="21:18" rst="0">
          <comment>occasionID180~120ID18SF_ID18</comment>
        </bits>
        <bits access="rw" name="sf_id18" pos="17:14" rst="0">
          <comment>occasionID1810~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id18" pos="13:2" rst="0">
          <comment>PRSID18ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id18" pos="1" rst="0">
          <comment>ID18
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id18" pos="0" rst="0">
          <comment>ID18CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id18_para2" protect="rw">
        <bits access="rw" name="certain_id18" pos="29:13" rst="0">
          <comment>ID18certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id18" pos="12:0" rst="0">
          <comment>ID18uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id19_para1" protect="rw">
        <bits access="rw" name="sf_num_id19" pos="21:18" rst="0">
          <comment>occasionID190~120ID19SF_ID19</comment>
        </bits>
        <bits access="rw" name="sf_id19" pos="17:14" rst="0">
          <comment>occasionID1910~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id19" pos="13:2" rst="0">
          <comment>PRSID19ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id19" pos="1" rst="0">
          <comment>ID19
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id19" pos="0" rst="0">
          <comment>ID19CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id19_para2" protect="rw">
        <bits access="rw" name="certain_id19" pos="29:13" rst="0">
          <comment>ID19certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id19" pos="12:0" rst="0">
          <comment>ID19uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id20_para1" protect="rw">
        <bits access="rw" name="sf_num_id20" pos="21:18" rst="0">
          <comment>occasionID200~120ID20SF_ID20</comment>
        </bits>
        <bits access="rw" name="sf_id20" pos="17:14" rst="0">
          <comment>occasionID2010~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id20" pos="13:2" rst="0">
          <comment>PRSID20ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id20" pos="1" rst="0">
          <comment>ID20
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id20" pos="0" rst="0">
          <comment>ID20CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id20_para2" protect="rw">
        <bits access="rw" name="certain_id20" pos="29:13" rst="0">
          <comment>ID20certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id20" pos="12:0" rst="0">
          <comment>ID20uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id21_para1" protect="rw">
        <bits access="rw" name="sf_num_id21" pos="21:18" rst="0">
          <comment>occasionID210~120ID21SF_ID21</comment>
        </bits>
        <bits access="rw" name="sf_id21" pos="17:14" rst="0">
          <comment>occasionID2110~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id21" pos="13:2" rst="0">
          <comment>PRSID21ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id21" pos="1" rst="0">
          <comment>ID21
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id21" pos="0" rst="0">
          <comment>ID21CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id21_para2" protect="rw">
        <bits access="rw" name="certain_id21" pos="29:13" rst="0">
          <comment>ID21certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id21" pos="12:0" rst="0">
          <comment>ID21uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id22_para1" protect="rw">
        <bits access="rw" name="sf_num_id22" pos="21:18" rst="0">
          <comment>occasionID220~120ID22SF_ID22</comment>
        </bits>
        <bits access="rw" name="sf_id22" pos="17:14" rst="0">
          <comment>occasionID2210~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id22" pos="13:2" rst="0">
          <comment>PRSID22ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id22" pos="1" rst="0">
          <comment>ID22
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id22" pos="0" rst="0">
          <comment>ID22CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id22_para2" protect="rw">
        <bits access="rw" name="certain_id22" pos="29:13" rst="0">
          <comment>ID22certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id22" pos="12:0" rst="0">
          <comment>ID22uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id23_para1" protect="rw">
        <bits access="rw" name="sf_num_id23" pos="21:18" rst="0">
          <comment>occasionID230~120ID23SF_ID23</comment>
        </bits>
        <bits access="rw" name="sf_id23" pos="17:14" rst="0">
          <comment>occasionID2310~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id23" pos="13:2" rst="0">
          <comment>PRSID23ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id23" pos="1" rst="0">
          <comment>ID23
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id23" pos="0" rst="0">
          <comment>ID23CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id23_para2" protect="rw">
        <bits access="rw" name="certain_id23" pos="29:13" rst="0">
          <comment>ID23certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id23" pos="12:0" rst="0">
          <comment>ID23uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_id24_para1" protect="rw">
        <bits access="rw" name="sf_num_id24" pos="21:18" rst="0">
          <comment>occasionID240~120ID24SF_ID24</comment>
        </bits>
        <bits access="rw" name="sf_id24" pos="17:14" rst="0">
          <comment>occasionID2410~9</comment>
        </bits>
        <bits access="rw" name="prsnid_id24" pos="13:2" rst="0">
          <comment>PRSID24ID 0~4095</comment>
        </bits>
        <bits access="rw" name="tx_num_id24" pos="1" rst="0">
          <comment>ID24
012
14</comment>
        </bits>
        <bits access="rw" name="cp_index_id24" pos="0" rst="0">
          <comment>ID24CP
0CP
1CP</comment>
        </bits>
      </reg>
      <reg name="otdoa_id24_para2" protect="rw">
        <bits access="rw" name="certain_id24" pos="29:13" rst="0">
          <comment>ID24certain-8192x3x2 TS ~8192x3x2TS1</comment>
        </bits>
        <bits access="rw" name="uncertain_id24" pos="12:0" rst="0">
          <comment>ID24uncertain0 TS ~1024x3x2TS2</comment>
        </bits>
      </reg>
      <reg name="otdoa_fft_para" protect="rw">
        <bits access="rw" name="fft_cut9" pos="17:16" rst="0">
          <comment>FFT9</comment>
        </bits>
        <bits access="rw" name="fft_cut8" pos="15:14" rst="0">
          <comment>FFT8</comment>
        </bits>
        <bits access="rw" name="fft_cut7" pos="13:12" rst="0">
          <comment>FFT7</comment>
        </bits>
        <bits access="rw" name="fft_cut6" pos="11:10" rst="0">
          <comment>FFT6</comment>
        </bits>
        <bits access="rw" name="fft_cut5" pos="9:8" rst="0">
          <comment>FFT5</comment>
        </bits>
        <bits access="rw" name="fft_cut4" pos="7:6" rst="0">
          <comment>FFT4</comment>
        </bits>
        <bits access="rw" name="fft_cut3" pos="5:4" rst="0">
          <comment>FFT3</comment>
        </bits>
        <bits access="rw" name="fft_cut2" pos="3:2" rst="0">
          <comment>FFT2</comment>
        </bits>
        <bits access="rw" name="fft_cut1" pos="1:0" rst="0">
          <comment>FFT1
2b00:bit[29:14]
2b01:bit[30:15]
2b10:bit[31:16]
2b11:bit[32:17]</comment>
        </bits>
      </reg>
      <reg name="otdoa_ifft_para" protect="rw">
        <bits access="rw" name="ifft_cut8" pos="15:14" rst="0">
          <comment>IFFT8</comment>
        </bits>
        <bits access="rw" name="ifft_cut7" pos="13:12" rst="0">
          <comment>IFFT7</comment>
        </bits>
        <bits access="rw" name="ifft_cut6" pos="11:10" rst="0">
          <comment>IFFT6</comment>
        </bits>
        <bits access="rw" name="ifft_cut5" pos="9:8" rst="0">
          <comment>IFFT5</comment>
        </bits>
        <bits access="rw" name="ifft_cut4" pos="7:6" rst="0">
          <comment>IFFT4</comment>
        </bits>
        <bits access="rw" name="ifft_cut3" pos="5:4" rst="0">
          <comment>IFFT3</comment>
        </bits>
        <bits access="rw" name="ifft_cut2" pos="3:2" rst="0">
          <comment>IFFT2</comment>
        </bits>
        <bits access="rw" name="ifft_cut1" pos="1:0" rst="0">
          <comment>FFT
2b00:bit[29:14]
2b01:bit[30:15]
2b10:bit[31:16]
2b11:bit[32:17]</comment>
        </bits>
      </reg>
      <reg name="otdoa_inter_ifft_para" protect="rw">
        <bits access="rw" name="max_sel" pos="19" rst="0">
          <comment>0phasemax,2
1phasephasemax,2</comment>
        </bits>
        <bits access="rw" name="inter_peak_zone" pos="18:14" rst="0">
          <comment>0~31,3</comment>
        </bits>
        <bits access="rw" name="inter_ifft_cut7" pos="13:12" rst="0">
          <comment>IFFT7</comment>
        </bits>
        <bits access="rw" name="inter_ifft_cut6" pos="11:10" rst="0">
          <comment>IFFT6</comment>
        </bits>
        <bits access="rw" name="inter_ifft_cut5" pos="9:8" rst="0">
          <comment>IFFT5</comment>
        </bits>
        <bits access="rw" name="inter_ifft_cut4" pos="7:6" rst="0">
          <comment>IFFT4</comment>
        </bits>
        <bits access="rw" name="inter_ifft_cut3" pos="5:4" rst="0">
          <comment>IFFT3</comment>
        </bits>
        <bits access="rw" name="inter_ifft_cut2" pos="3:2" rst="0">
          <comment>IFFT2</comment>
        </bits>
        <bits access="rw" name="inter_ifft_cut1" pos="1:0" rst="0">
          <comment>FFT
2b00:bit[29:14]
2b01:bit[30:15]
2b10:bit[31:16]
2b11:bit[32:17]</comment>
        </bits>
      </reg>
      <reg name="otdoa_signal_noise_zone" protect="rw">
        <bits access="rw" name="noise_zone2" pos="27:21" rst="0">
          <comment>0~32x2,2/3</comment>
        </bits>
        <bits access="rw" name="noise_zone1" pos="20:14" rst="0">
          <comment>0~32x2,2/3</comment>
        </bits>
        <bits access="rw" name="signal_zone2" pos="13:7" rst="0">
          <comment>0~32x2,1</comment>
        </bits>
        <bits access="rw" name="signal_zone1" pos="6:0" rst="0">
          <comment>0~32x2,1</comment>
        </bits>
      </reg>
      <reg name="int_ctrl" protect="rw">
        <bits access="rw" name="irq_en" pos="0" rst="0">
          <comment>0:
1:</comment>
        </bits>
      </reg>
      <reg name="otdoa_start" protect="rw">
        <bits access="rw" name="otdoa_start_otdoa_start" pos="0" rst="0">
          <comment>0: OTDOA/
1: OTDOA</comment>
        </bits>
      </reg>
      <reg name="int_flag" protect="rw">
        <bits access="rc" name="int_flag_int_flag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:
0:</comment>
        </bits>
      </reg>
      <reg name="otdoa2rx_mem_error_flag" protect="r">
        <bits access="r" name="otdoa2rx_mem1to8_error_flag" pos="7:0" rst="0">
          <comment>Bit[n]:
0:
1:
Bit01
Bit78</comment>
        </bits>
      </reg>
      <reg name="otdoa_debug_ctrl_state" protect="r">
        <bits access="r" name="otdoa_debug_ctrl_state_otdoa_debug_ctrl_state" pos="27:0" rst="1">
          <comment/>
        </bits>
      </reg>
      <reg name="otdoa_debug_memreq_axidma_state" protect="r">
        <bits access="r" name="otdoa_debug_axidma_state" pos="12:8" rst="1">
          <comment>axidma</comment>
        </bits>
        <bits access="r" name="otdoa_debug_memreq_state" pos="7:0" rst="1">
          <comment>OTDOA</comment>
        </bits>
      </reg>
      <hole size="192"/>
      <reg name="pbmeas_sample0" protect="rw">
        <bits access="rw" name="subframe_offset" pos="29:16" rst="0">
          <comment>Ts</comment>
        </bits>
        <bits access="rw" name="sample_offset" pos="12:0" rst="0">
          <comment>AD_ON16Ts</comment>
        </bits>
      </reg>
      <reg name="pbmeas_sample1" protect="rw">
        <bits access="rw" name="sample_len" pos="12:0" rst="2048">
          <comment>16Ts</comment>
        </bits>
      </reg>
      <reg name="pbmeas_sample2" protect="rw">
        <bits access="rw" name="sample_num" pos="24:20" rst="0">
          <comment>IRT/AFCPDPPWR/RSSI MAX:20</comment>
        </bits>
        <bits access="rw" name="sample_vld" pos="19:0" rst="0">
          <comment>IRT/AFC
20bitbit
0
1</comment>
        </bits>
      </reg>
      <reg name="pbmeas_phase0" protect="rw">
        <bits access="rw" name="phase_irt_num" pos="18:15" rst="7">
          <comment>IRTPHASE</comment>
        </bits>
        <bits access="rw" name="phase_irt_step" pos="14:9" rst="19">
          <comment>IRTPHASE16Ts</comment>
        </bits>
        <bits access="rw" name="phase_irt_offset" pos="8:0" rst="192">
          <comment>IRT(-256~25516TsOFFSET)</comment>
        </bits>
      </reg>
      <reg name="pbmeas_phase1" protect="rw">
        <bits access="rw" name="phase_afc_offset" pos="12:0" rst="0">
          <comment>AFC-4096~2095TsOFFSET</comment>
        </bits>
      </reg>
      <reg name="pbmeas_agc" protect="rw">
        <bits access="rw" name="agc" pos="9:0" rst="0">
          <comment>xAGC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_agc0" protect="rw">
        <bits access="rw" name="agc2" pos="29:20" rst="0">
          <comment>2AGC</comment>
        </bits>
        <bits access="rw" name="agc1" pos="19:10" rst="0">
          <comment>1AGC</comment>
        </bits>
        <bits access="rw" name="agc0" pos="9:0" rst="0">
          <comment>0AGC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_agc1" protect="rw">
        <bits access="rw" name="agc5" pos="29:20" rst="0">
          <comment>5AGC</comment>
        </bits>
        <bits access="rw" name="agc4" pos="19:10" rst="0">
          <comment>4AGC</comment>
        </bits>
        <bits access="rw" name="agc3" pos="9:0" rst="0">
          <comment>3AGC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_agc2" protect="rw">
        <bits access="rw" name="agc8" pos="29:20" rst="0">
          <comment>8AGC</comment>
        </bits>
        <bits access="rw" name="agc7" pos="19:10" rst="0">
          <comment>7AGC</comment>
        </bits>
        <bits access="rw" name="agc6" pos="9:0" rst="0">
          <comment>6AGC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_agc3" protect="rw">
        <bits access="rw" name="agc11" pos="29:20" rst="0">
          <comment>11AGC</comment>
        </bits>
        <bits access="rw" name="agc10" pos="19:10" rst="0">
          <comment>10AGC</comment>
        </bits>
        <bits access="rw" name="agc9" pos="9:0" rst="0">
          <comment>9AGC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_agc4" protect="rw">
        <bits access="rw" name="agc14" pos="29:20" rst="0">
          <comment>14AGC</comment>
        </bits>
        <bits access="rw" name="agc13" pos="19:10" rst="0">
          <comment>13AGC</comment>
        </bits>
        <bits access="rw" name="agc12" pos="9:0" rst="0">
          <comment>12AGC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_agc5" protect="rw">
        <bits access="rw" name="agc17" pos="29:20" rst="0">
          <comment>17AGC</comment>
        </bits>
        <bits access="rw" name="agc16" pos="19:10" rst="0">
          <comment>16AGC</comment>
        </bits>
        <bits access="rw" name="agc15" pos="9:0" rst="0">
          <comment>15AGC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_agc6" protect="rw">
        <bits access="rw" name="agc19" pos="19:10" rst="0">
          <comment>19AGC</comment>
        </bits>
        <bits access="rw" name="agc18" pos="9:0" rst="0">
          <comment>18AGC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_mib" protect="rw">
        <bits access="rw" name="sample_pat" pos="22" rst="0">
          <comment>0: 0
1FDD90TDD05</comment>
        </bits>
        <bits access="rw" name="subfn5_ind" pos="21" rst="0">
          <comment>5
05
15</comment>
        </bits>
        <bits access="rw" name="sfn" pos="20:11" rst="0">
          <comment>40MS</comment>
        </bits>
        <bits access="rw" name="mib_sib1" pos="10:6" rst="0">
          <comment>schedulingInfoSIB1-BR-r13</comment>
        </bits>
        <bits access="rw" name="mib_phi_res" pos="5:4" rst="0">
          <comment>phich-Config: PHICH resource</comment>
        </bits>
        <bits access="rw" name="mib_phi_dur" pos="3" rst="0">
          <comment>phich-Config: PHICH duration</comment>
        </bits>
        <bits access="rw" name="mib_bw" pos="2:0" rst="0">
          <comment>dl-Bandwidth</comment>
        </bits>
      </reg>
      <reg name="pbmeas_sys" protect="rw">
        <bits access="rw" name="tx_sel" pos="19:18" rst="0">
          <comment>PORT
0: 2PORT0PORT14PORT0PORT1PORT2PORT3
1: PORT0
2: PORT1</comment>
        </bits>
        <bits access="rw" name="tx_ant" pos="17:16" rst="0">
          <comment>0:1
1:2
2:4</comment>
        </bits>
        <bits access="rw" name="cell_id" pos="15:7" rst="0">
          <comment>ID0~504</comment>
        </bits>
        <bits access="rw" name="pbch_rep" pos="6" rst="0">
          <comment>PBCH
0:
1:</comment>
        </bits>
        <bits access="rw" name="cp_ind" pos="5" rst="0">
          <comment>CP
0: NORMAL CP
1: EXTEND CP</comment>
        </bits>
        <bits access="rw" name="fdd_tdd" pos="4" rst="0">
          <comment>FDD/TDD
0: TDD
1: FDD</comment>
        </bits>
        <bits access="rw" name="tx_ant_afc" pos="3:2" rst="0">
          <comment>AFC
0: 1
1: 2
2: 4</comment>
        </bits>
        <bits access="rw" name="tx_ant_irt" pos="1:0" rst="0">
          <comment>IRT
0: 1
1: 2
2: 4</comment>
        </bits>
      </reg>
      <reg name="pbmeas_arg0" protect="rw">
        <bits access="rw" name="irt_max_sel" pos="17" rst="0">
          <comment>IRT
0
1SCALE</comment>
        </bits>
        <bits access="rw" name="irt_inter_range" pos="16:12" rst="15">
          <comment>IRT0~31</comment>
        </bits>
        <bits access="rw" name="irt_signal_sel" pos="11" rst="0">
          <comment>IRTSCALE
0
1</comment>
        </bits>
        <bits access="rw" name="irt_signal_range" pos="10:5" rst="30">
          <comment>IRT0~63</comment>
        </bits>
        <bits access="rw" name="afc_ofdm_inter" pos="4:3" rst="3">
          <comment>AFCOFDM
0:1
1:2
2:3
3:4</comment>
        </bits>
        <bits access="rw" name="afc_freq_block" pos="2:0" rst="2">
          <comment>AFC
0: 1RE
1: 1PRB
2: 2PRB
3: 3PRB
4: 6PRB</comment>
        </bits>
      </reg>
      <reg name="pbmeas_arg1" protect="rw">
        <bits access="rw" name="irt_noise_th" pos="31:16" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="irt_signal_th" pos="15:0" rst="32767">
          <comment/>
        </bits>
      </reg>
      <reg name="pbmeas_int_en" protect="rw">
        <bits access="rw" name="int_en" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="pbmeas_start" protect="rw">
        <bits access="rw" name="afc_first" pos="5" rst="1">
          <comment>AFC
0FIRST
1FIRST</comment>
        </bits>
        <bits access="rw" name="irt_first" pos="4" rst="1">
          <comment>IRT
0FIRST
1FIRST</comment>
        </bits>
        <bits access="rw" name="afc_en" pos="3" rst="0">
          <comment>AFC
0
1</comment>
        </bits>
        <bits access="rw" name="irt_en" pos="2" rst="0">
          <comment>IRT
0
1</comment>
        </bits>
        <bits access="rw" name="rec_en" pos="1" rst="0">
          <comment>0
1</comment>
        </bits>
        <bits access="rw" name="pbmeas_start_pbmeas_start" pos="0" rst="0">
          <comment>PBMEAS
0
1</comment>
        </bits>
      </reg>
      <reg name="pbmeas_irt_out" protect="r">
        <bits access="r" name="irt_out" pos="15:0" rst="0">
          <comment>IRT_OUTTs</comment>
        </bits>
      </reg>
      <reg name="pbmeas_tsinr_lout" protect="r">
        <bits access="r" name="sinr_out" pos="31:0" rst="0">
          <comment>SINR</comment>
        </bits>
      </reg>
      <reg name="pbmeas_tsinr_dbout" protect="r">
        <bits access="r" name="sinr_out" pos="15:0" rst="0">
          <comment>SINRDB</comment>
        </bits>
      </reg>
      <reg name="pbmeas_tpwr_out" protect="r">
        <bits access="r" name="pwr_out" pos="15:0" rst="0">
          <comment>POWER</comment>
        </bits>
      </reg>
      <reg name="pbmeas_tpwr_agc_out" protect="r">
        <bits access="r" name="pwr_agc" pos="9:0" rst="0">
          <comment>POWER</comment>
        </bits>
      </reg>
      <reg name="pbmeas_afc_out" protect="r">
        <bits access="r" name="afc_out" pos="15:0" rst="0">
          <comment>AFC_OUTHz</comment>
        </bits>
      </reg>
      <reg name="pbmeas_sigma_out" protect="r">
        <bits access="r" name="sigma_out" pos="31:0" rst="0">
          <comment>SIGMA</comment>
        </bits>
      </reg>
      <reg name="pbmeas_fpwr_out" protect="r">
        <bits access="r" name="pwr_out" pos="15:0" rst="0">
          <comment>POWER</comment>
        </bits>
      </reg>
      <reg name="pbmeas_fsinr_lout" protect="r">
        <bits access="r" name="sinr_out" pos="31:0" rst="0">
          <comment>SINR</comment>
        </bits>
      </reg>
      <reg name="pbmeas_fsinr_dbout" protect="r">
        <bits access="r" name="sinr_out" pos="15:0" rst="0">
          <comment>SINRDB</comment>
        </bits>
      </reg>
      <reg name="pbmeas_rssi0_out" protect="r">
        <bits access="r" name="rssi_out" pos="15:0" rst="0">
          <comment>RSSI(DBQ4)</comment>
        </bits>
      </reg>
      <reg name="pbmeas_rssi1_out" protect="r">
        <bits access="r" name="rssi_out" pos="15:0" rst="0">
          <comment>RSSI(DBQ4)</comment>
        </bits>
      </reg>
      <reg name="pbmeas_rsrq_out" protect="r">
        <bits access="r" name="rssi_out" pos="15:0" rst="0">
          <comment>RSSI(DBQ4)</comment>
        </bits>
      </reg>
      <reg name="pbmeas_agc_out" protect="r">
        <bits access="r" name="agc_out" pos="9:0" rst="0">
          <comment>AGC_OUT(DBQ0)</comment>
        </bits>
      </reg>
      <reg name="pbmeas_afc_acci0" protect="r">
        <bits access="r" name="afc_accil" pos="31:0" rst="0">
          <comment>AFCAFC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_afc_acci1" protect="r">
        <bits access="r" name="afc_accih" pos="15:0" rst="0">
          <comment>AFCAFC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_afc_accq0" protect="r">
        <bits access="r" name="afc_accql" pos="31:0" rst="0">
          <comment>AFCAFC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_afc_accq1" protect="r">
        <bits access="r" name="afc_accqh" pos="15:0" rst="0">
          <comment>AFCAFC</comment>
        </bits>
      </reg>
      <reg name="pbmeas_int_flag" protect="rw">
        <bits access="rc" name="err_memreq" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          MEM</comment>
        </bits>
        <bits access="rc" name="err_memover" pos="3" rst="0">
          <comment>bit type is changed from rw1c to rc.
          MEM</comment>
        </bits>
        <bits access="rc" name="int_afc_flag" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1: AFC
0:</comment>
        </bits>
        <bits access="rc" name="int_irt_flag" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1: IRT
0:</comment>
        </bits>
        <bits access="rc" name="int_rec_flag" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          1:REC
0:</comment>
        </bits>
      </reg>
      <reg name="pbmeas_mfact0" protect="rw">
        <bits access="rw" name="afc_rsrp_mfact" pos="31:16" rst="0">
          <comment>AFC RSRP
16Q4</comment>
        </bits>
        <bits access="rw" name="irt_rsrp_mfact" pos="15:0" rst="0">
          <comment>IRT RSRP
16Q4</comment>
        </bits>
      </reg>
      <reg name="pbmeas_mfact1" protect="rw">
        <bits access="rw" name="afc_rsrq_mfact" pos="31:16" rst="0">
          <comment>AFC RSRQ
16Q4RSRPRSSI</comment>
        </bits>
        <bits access="rw" name="afc_rssi_mfact" pos="15:0" rst="0">
          <comment>AFC RSSI
16Q4</comment>
        </bits>
      </reg>
      <reg name="pbmeas_debug_ctrl_state" protect="r">
        <bits access="r" name="pbmeas_debug_ctrl_state_pbmeas_debug_ctrl_state" pos="11:0" rst="1">
          <comment>PBMEAS</comment>
        </bits>
      </reg>
      <reg name="pbmeas_debug_first_pos" protect="r">
        <bits access="r" name="first_mem" pos="15:13" rst="0">
          <comment>MEM</comment>
        </bits>
        <bits access="r" name="first_addr" pos="12:0" rst="0">
          <comment>ADDR</comment>
        </bits>
      </reg>
      <reg name="pbmeas_debug_first_dat" protect="r">
        <bits access="r" name="first_dat" pos="23:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="pbmeas_debug_first_local" protect="r">
        <bits access="r" name="first_local" pos="23:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="pbmeas_debug_irt_fine" protect="r">
        <bits access="r" name="irt_fine" pos="7:0" rst="0">
          <comment>IRT</comment>
        </bits>
      </reg>
      <reg name="pbmeas_debug_irt_crud" protect="r">
        <bits access="r" name="irt_crud" pos="10:0" rst="0">
          <comment>IRT</comment>
        </bits>
      </reg>
      <reg name="pbmeas_debug_irt_phase" protect="r">
        <bits access="r" name="irt_phase" pos="3:0" rst="0">
          <comment>IRTPHASE</comment>
        </bits>
      </reg>
      <hole size="28960"/>
      <reg name="result" protect="rw">
        <bits access="rw" name="result_result" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="491488"/>
      <reg name="pwr" protect="rw">
        <bits access="rw" name="pwr_pwr" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="524256"/>
      <reg name="slot0_gold" protect="rw">
        <bits access="rw" name="slot0_gold_slot0_gold" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="524256"/>
      <reg name="slot1_gold" protect="rw">
        <bits access="rw" name="slot1_gold_slot1_gold" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="524256"/>
      <reg name="slot0_rs" protect="rw">
        <bits access="rw" name="slot0_rs_slot0_rs" pos="31:0" rst="0">
      </bits>
      </reg>
      <hole size="524256"/>
      <reg name="slot1_rs" protect="rw">
        <bits access="rw" name="slot1_rs_slot1_rs" pos="31:0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="cp_lte_rxcapt.xml">
    <module category="LTE_SYS" name="CP_LTE_RXCAPT">
      <reg name="rxcapt_en" protect="rw">
        <bits access="rw" name="rxcapt_en" pos="0" rst="0">
          <comment>0
1</comment>
        </bits>
      </reg>
      <reg name="capt_cfg" protect="rw">
        <bits access="rw" name="capt_dump" pos="4" rst="0">
          <comment>Dump
1
0</comment>
        </bits>
        <bits access="rw" name="capt_tx" pos="3" rst="0">
          <comment>Tx Trace
1
0</comment>
        </bits>
        <bits access="rw" name="capt_iddet_offline" pos="2" rst="0">
          <comment>IDDET offline
1
0</comment>
        </bits>
        <bits access="rw" name="capt_odtoa" pos="1" rst="0">
          <comment>ODTOA
1
0</comment>
        </bits>
        <bits access="rw" name="capt_rx" pos="0" rst="0">
          <comment>RX
1
0</comment>
        </bits>
      </reg>
      <reg name="fill_cfg1" protect="rw">
        <bits access="rw" name="fill_len" pos="31:4" rst="268435455">
          <comment/>
        </bits>
        <bits access="rw" name="fill_dl_offline" pos="3" rst="0">
          <comment>DL offline
1
0</comment>
        </bits>
        <bits access="rw" name="fill_div" pos="2:0" rst="0">
          <comment>3h0:420M/15M
3h1:810M
3h2:165M
3h3:323M
3h4:641.4M
Others: 4</comment>
        </bits>
      </reg>
      <reg name="fill_cfg2" protect="rw">
        <bits access="rw" name="fill_len" pos="31:4" rst="268435455">
          <comment/>
        </bits>
        <bits access="rw" name="fill_iddet_offline" pos="3" rst="0">
          <comment>IDDET offline
1
0</comment>
        </bits>
        <bits access="rw" name="fill_div" pos="2:0" rst="0">
          <comment>3h0:420M/15M
3h1:810M
3h2:165M
3h3:323M
3h4:641.4M
Others: 4</comment>
        </bits>
      </reg>
      <reg name="dma_req_en" protect="rw">
        <bits access="rw" name="dma_req7_en" pos="7" rst="0">
          <comment>DMA_req7
1
0</comment>
        </bits>
        <bits access="rw" name="dma_req6_en" pos="6" rst="0">
          <comment>DMA_req6
1
0</comment>
        </bits>
        <bits access="rw" name="dma_req5_en" pos="5" rst="0">
          <comment>DMA_req5
1
0</comment>
        </bits>
        <bits access="rw" name="dma_req4_en" pos="4" rst="0">
          <comment>DMA_req4
1
0</comment>
        </bits>
        <bits access="rw" name="dma_req3_en" pos="3" rst="0">
          <comment>DMA_req3
1
0</comment>
        </bits>
        <bits access="rw" name="dma_req2_en" pos="2" rst="0">
          <comment>DMA_req2
1
0</comment>
        </bits>
        <bits access="rw" name="dma_req1_en" pos="1" rst="0">
          <comment>DMA_req1
1
0</comment>
        </bits>
        <bits access="rw" name="dma_req0_en" pos="0" rst="0">
          <comment>DMA_req0
1
0</comment>
        </bits>
      </reg>
      <reg name="irq_inten" protect="rw">
        <bits access="rw" name="capt_err34" pos="13" rst="0">
          <comment>Capt_err34
1
0</comment>
        </bits>
        <bits access="rw" name="capt_err12" pos="12" rst="0">
          <comment>Capt_err12
1
0</comment>
        </bits>
        <bits access="rw" name="mem56_finish_irq" pos="10" rst="0">
          <comment>Mem56 finish
1
0</comment>
        </bits>
        <bits access="rw" name="mem56_pang_irq" pos="9" rst="0">
          <comment>Mem56 pang
1
0</comment>
        </bits>
        <bits access="rw" name="mem56_ping_irq" pos="8" rst="0">
          <comment>Mem56 ping
1
0</comment>
        </bits>
        <bits access="rw" name="mem34_finish_irq" pos="6" rst="0">
          <comment>Mem34 finish
1
0</comment>
        </bits>
        <bits access="rw" name="mem34_pang_irq" pos="5" rst="0">
          <comment>Mem34 pang
1
0</comment>
        </bits>
        <bits access="rw" name="mem34_ping_irq" pos="4" rst="0">
          <comment>Mem34 ping
1
0</comment>
        </bits>
        <bits access="rw" name="mem12_finish_irq" pos="2" rst="0">
          <comment>Mem12 finish
1
0</comment>
        </bits>
        <bits access="rw" name="mem12_pang_irq" pos="1" rst="0">
          <comment>Mem12 pang
1
0</comment>
        </bits>
        <bits access="rw" name="mem12_ping_irq" pos="0" rst="0">
          <comment>Mem12 ping
1
0</comment>
        </bits>
      </reg>
      <reg name="irq_inten_set" protect="rw">
        <bits access="rs" name="capt_err34" pos="13" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Capt_err34
1
0</comment>
        </bits>
        <bits access="rs" name="capt_err12" pos="12" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Capt_err12
1
0</comment>
        </bits>
        <bits access="rs" name="mem56_finish_irq" pos="10" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Mem56 finish
1
0</comment>
        </bits>
        <bits access="rs" name="mem56_pang_irq" pos="9" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Mem56 pang
1
0</comment>
        </bits>
        <bits access="rs" name="mem56_ping_irq" pos="8" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Mem56 ping
1
0</comment>
        </bits>
        <bits access="rs" name="mem34_finish_irq" pos="6" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Mem34 finish
1
0</comment>
        </bits>
        <bits access="rs" name="mem34_pang_irq" pos="5" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Mem34 pang
1
0</comment>
        </bits>
        <bits access="rs" name="mem34_ping_irq" pos="4" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Mem34 ping
1
0</comment>
        </bits>
        <bits access="rs" name="mem12_finish_irq" pos="2" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Mem12 finish
1
0</comment>
        </bits>
        <bits access="rs" name="mem12_pang_irq" pos="1" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Mem12 pang
1
0</comment>
        </bits>
        <bits access="rs" name="mem12_ping_irq" pos="0" rst="0">
          <comment>bit type is changed from rw1s to rs.
          Mem12 ping
1
0</comment>
        </bits>
      </reg>
      <reg name="irq_inten_clr" protect="rw">
        <bits access="rc" name="capt_err34" pos="13" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Capt_err34
1
0</comment>
        </bits>
        <bits access="rc" name="capt_err12" pos="12" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Capt_err12
1
0</comment>
        </bits>
        <bits access="rc" name="mem56_finish_irq" pos="10" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem56 finish
1
0</comment>
        </bits>
        <bits access="rc" name="mem56_pang_irq" pos="9" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem56 pang
1
0</comment>
        </bits>
        <bits access="rc" name="mem56_ping_irq" pos="8" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem56 ping
1
0</comment>
        </bits>
        <bits access="rc" name="mem34_finish_irq" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem34 finish
1
0</comment>
        </bits>
        <bits access="rc" name="mem34_pang_irq" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem34 pang
1
0</comment>
        </bits>
        <bits access="rc" name="mem34_ping_irq" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem34 ping
1
0</comment>
        </bits>
        <bits access="rc" name="mem12_finish_irq" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem12 finish
1
0</comment>
        </bits>
        <bits access="rc" name="mem12_pang_irq" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem12 pang
1
0</comment>
        </bits>
        <bits access="rc" name="mem12_ping_irq" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem12 ping
1
0</comment>
        </bits>
      </reg>
      <reg name="irq_state" protect="rw">
        <bits access="rc" name="capt_err34_irq" pos="13" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Capt_err34</comment>
        </bits>
        <bits access="rc" name="capt_err12_irq" pos="12" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Capt_err12</comment>
        </bits>
        <bits access="rc" name="mem56_finish_irq" pos="10" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem56 finish</comment>
        </bits>
        <bits access="rc" name="mem56_pang_irq" pos="9" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem56 pang</comment>
        </bits>
        <bits access="rc" name="mem56_ping_irq" pos="8" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem56 ping</comment>
        </bits>
        <bits access="rc" name="mem34_finish_irq" pos="6" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem34 finish</comment>
        </bits>
        <bits access="rc" name="mem34_pang_irq" pos="5" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem34 pang</comment>
        </bits>
        <bits access="rc" name="mem34_ping_irq" pos="4" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem34 ping</comment>
        </bits>
        <bits access="rc" name="mem12_finish_irq" pos="2" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem12 finish</comment>
        </bits>
        <bits access="rc" name="mem12_pang_irq" pos="1" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem12 pang</comment>
        </bits>
        <bits access="rc" name="mem12_ping_irq" pos="0" rst="0">
          <comment>bit type is changed from rw1c to rc.
          Mem12 ping</comment>
        </bits>
      </reg>
      <reg name="capt_end_addr12" protect="rw">
        <bits access="rw" name="end_addr12" pos="10:0" rst="1999">
          <comment>Mem12</comment>
        </bits>
      </reg>
      <reg name="capt_end_addr34" protect="rw">
        <bits access="rw" name="end_addr34" pos="8:0" rst="499">
          <comment>Mem34</comment>
        </bits>
      </reg>
      <reg name="fill_end_addr12" protect="rw">
        <bits access="rw" name="end_addr12" pos="10:0" rst="2047">
          <comment>Mem12</comment>
        </bits>
      </reg>
      <reg name="fill_end_addr56" protect="rw">
        <bits access="rw" name="end_addr56" pos="9:0" rst="1023">
          <comment>Mem56</comment>
        </bits>
      </reg>
      <reg name="norm_ctrl" protect="rw">
        <bits access="rw" name="norm_ctrl_norm_ctrl" pos="31:0" rst="0">
          <comment/>
        </bits>
      </reg>
      <reg name="state_mem12" protect="r">
        <bits access="r" name="pang_sta" pos="30:28" rst="0">
          <comment>Mem12 pang
000IDLE
001MEM
010MEM
011DMA
100MEM
Others: IDLE</comment>
        </bits>
        <bits access="r" name="pang_addr" pos="26:16" rst="0">
          <comment>Mem12 pang</comment>
        </bits>
        <bits access="r" name="ping_sta" pos="14:12" rst="0">
          <comment>Mem12 ping
000IDLE
001MEM
010MEM
011DMA
100MEM
Others: IDLE</comment>
        </bits>
        <bits access="r" name="ping_addr" pos="10:0" rst="0">
          <comment>Mem12 ping</comment>
        </bits>
      </reg>
      <reg name="state_mem34" protect="r">
        <bits access="r" name="pang_sta" pos="30:28" rst="0">
          <comment>Mem34 pang
000IDLE
001MEM
010MEM
011DMA
100MEM
Others: IDLE</comment>
        </bits>
        <bits access="r" name="pang_addr" pos="24:16" rst="0">
          <comment>Mem34 pang</comment>
        </bits>
        <bits access="r" name="ping_sta" pos="14:12" rst="0">
          <comment>Mem34 ping
000IDLE
001MEM
010MEM
011DMA
100MEM
Others: IDLE</comment>
        </bits>
        <bits access="r" name="ping_addr" pos="8:0" rst="0">
          <comment>Mem34 ping</comment>
        </bits>
      </reg>
      <reg name="state_mem56" protect="r">
        <bits access="r" name="pang_sta" pos="30:28" rst="0">
          <comment>Mem56 pang
000IDLE
001MEM
010MEM
011DMA
100MEM
Others: IDLE</comment>
        </bits>
        <bits access="r" name="pang_addr" pos="25:16" rst="0">
          <comment>Mem56 pang</comment>
        </bits>
        <bits access="r" name="ping_sta" pos="14:12" rst="0">
          <comment>Mem56 ping
000IDLE
001MEM
010MEM
011DMA
100MEM
Others: IDLE</comment>
        </bits>
        <bits access="r" name="ping_addr" pos="9:0" rst="0">
          <comment>Mem56 ping</comment>
        </bits>
      </reg>
      <reg name="state_err12" protect="r">
        <bits access="r" name="which_mem" pos="24" rst="0">
          <comment>Err
0MEM12 Ping
1MEM12 Pang</comment>
        </bits>
        <bits access="r" name="err_fn" pos="23:0" rst="0">
          <comment>Error(ERR</comment>
        </bits>
      </reg>
      <reg name="state_err34" protect="r">
        <bits access="r" name="which_mem" pos="24" rst="0">
          <comment>Err
0MEM34 Ping
1MEM34 Pang</comment>
        </bits>
        <bits access="r" name="err_fn" pos="23:0" rst="0">
          <comment>Error(ERR</comment>
        </bits>
      </reg>
      <hole size="523680"/>
      <reg name="mem12_ping" protect="rw">
        <bits access="rw" name="mem12_ping_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="mem12_ping_0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="mem12_pang" protect="rw">
        <bits access="rw" name="mem12_pang_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="mem12_pang_0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="65504"/>
      <reg name="mem34_ping" protect="rw">
        <bits access="rw" name="mem34_ping_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="mem34_ping_0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="16352"/>
      <reg name="mem34_pang" protect="rw">
        <bits access="rw" name="mem34_pang_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="mem34_pang_0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="16352"/>
      <reg name="mem56_ping" protect="rw">
        <bits access="rw" name="mem56_ping_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="mem56_ping_0" pos="15:4" rst="0">
      </bits>
      </reg>
      <hole size="32736"/>
      <reg name="mem56_pang" protect="rw">
        <bits access="rw" name="mem56_pang_1" pos="31:20" rst="0">
      </bits>
        <bits access="rw" name="mem56_pang_0" pos="15:4" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="bb2g_ram.xml">
    <var name="BB2G_RAM_SIZE" value="32*4096"/>
    <module category="GGE_SYS" name="BB2G_RAM">
      <memory name="ram_array" size="BB2G_RAM_SIZE">
        <comment>
          BB2G Ram Space
          <br/>
           This RAM is used in 2G mode as ACC buffer and code space.
          <br/>
           In NB mode, it can also be used as TCM memory space.
        </comment>
      </memory>
    </module>
  </archive>
  <archive relative="bb_cp2.xml">
    <module category="GGE_SYS" name="BB_CP2">
      <reg name="ctrl" protect="rw">
        <bits access="rw" display="hex" name="first poly" pos="2:0" rst="111">
          <comment>
            This field is used for setting the first polynomial to encode
                     or the CRC computation
            <br/>
            First polynomial to encode :
            <br/>
            000 = G0
            <br/>
            001 = G1
            <br/>
            010 = G2
            <br/>
            011 = G3
            <br/>
            100 = G4
            <br/>
            101 = G5
            <br/>
            110 = G6
            <br/>
            111 = No polynomial code used (input connected to output)
            <br/>
            Cyclic code :
            <br/>
            000 = D8 + D4 + D3 + D2 + 1
            <br/>
            001 = D3 + D + 1
            <br/>
            010 = D14 + D13 + D5 + D3 + D2 +1
            <br/>
            011 = D6 + D5 + D3 + D2 + D1 + 1
            <br/>
            100 = D10 + D8 + D6 + D5 + D4 + D2 + 1
            <br/>
            101 = D16 + D12 + D5 + 1
            <br/>
            110 = (D23 + 1)*(D17 + D3 + 1)
            <br/>
            111 = reserved
          </comment>
        </bits>
        <bits access="rw" display="hex" name="second poly" pos="5:3" rst="111">
          <comment>
            Second polynomial to encode :
            <br/>
            000 = G0
            <br/>
            001 = G1
            <br/>
            010 = G2
            <br/>
            011 = G3
            <br/>
            100 = G4
            <br/>
            101 = G5
            <br/>
            110 = G6
            <br/>
            111 = No polynomial code used (input connected to output)
          </comment>
        </bits>
        <bits access="rw" display="hex" name="third poly" pos="8:6" rst="111">
          <comment>
            Third polynomial to encode:
            <br/>
            000 = G0
            <br/>
            001 = G1
            <br/>
            010 = G2
            <br/>
            011 = G3
            <br/>
            100 = G4
            <br/>
            101 = G5
            <br/>
            110 = G6
            <br/>
            111 = No polynomial code used (input connected to output)
          </comment>
        </bits>
        <bits access="rw" display="hex" name="fourth poly" pos="11:9" rst="111">
          <comment>
            Fourth polynomial to encode:
            <br/>
            000 = G0
            <br/>
            001 = G1
            <br/>
            010 = G2
            <br/>
            011 = G3
            <br/>
            100 = G4
            <br/>
            101 = G5
            <br/>
            110 = G6
            <br/>
            111 = No polynomial code used (input connected to output)
          </comment>
        </bits>
        <bits access="rw" display="hex" name="fith poly" pos="14:12" rst="111">
          <comment>
            Fith polynomial to encode:
            <br/>
            000 = G0
            <br/>
            001 = G1
            <br/>
            010 = G2
            <br/>
            011 = G3
            <br/>
            100 = G4
            <br/>
            101 = G5
            <br/>
            110 = G6
            <br/>
            111 = No polynomial code used (input connected to output)
          </comment>
        </bits>
        <bits access="rw" display="hex" name="sixth poly" pos="17:15" rst="111">
          <comment>
            Sixth polynomial to encode:
            <br/>
            000 = G0
            <br/>
            001 = G1
            <br/>
            010 = G2
            <br/>
            011 = G3
            <br/>
            100 = G4
            <br/>
            101 = G5
            <br/>
            110 = G6
            <br/>
            111 = No polynomial code used (input connected to output)
          </comment>
        </bits>
        <bits access="rw" display="hex" name="rsc poly" pos="20:18" rst="111">
          <comment>
            RSC (Recursive Systematic Convolutional) polynomial code:
            <br/>
            000 = G0
            <br/>
            001 = G1
            <br/>
            010 = G2
            <br/>
            011 = G3
            <br/>
            100 = G4
            <br/>
            101 = G5
            <br/>
            110 = G6
            <br/>
            111 = No RSC
          </comment>
        </bits>
        <bits access="rw" display="hex" name="nb poly" pos="23:21" rst="111">
          <comment>
            Number of polynomial code to process:
            <br/>
            0x0 = 0
            <br/>
            0x1 = 1 (First Poly)
            <br/>
            0x2 = 2 (First poly and second Poly)
            <br/>
            0x3 = 3 (First poly, second poly, third Poly)
            <br/>
            0x6 = 6 (first Poly to sixth Poly)
            <br/>
            0x7 = reserved
          </comment>
        </bits>
        <bits access="rw" name="enable puncturing" pos="24" rst="1">
          <comment>
            Enable Puncturing
            <br/>
            0 = No puncturing (puncturing disabled)
            <br/>
            1 = Enable puncturing
          </comment>
        </bits>
      </reg>
      <reg name="bit number" protect="rw">
        <bits access="rw" display="hex" name="bit number" pos="8:0" rst="0x1FF">
          <comment>
            Number of inputs bits to process
            <br/>
            0x01 = 1
            <br/>
            0x02 = 2
            <br/>
            0x03 = 3
            <br/>
            ...
            <br/>
            0xFD = 253
            <br/>
            0xFE = 254
            <br/>
            0xFF = 255
            <br/>
            0x100 = 256
            <br/>
            ...
            <br/>
            0x1BF = 447
            <br/>
            0x1C0 = 448
          </comment>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="enable" pos="0:0" rst="0">
          <comment>When 1 the bb_cp2 is running</comment>
        </bits>
      </reg>
      <reg name="lram_addr" protect="rw">
        <bits access="rw" display="hex" name="lram address" pos="4:0" rst="0x0">
          <comment>
            LRAM address for the next access
            <br/>
            Automatically incremented after each access
          </comment>
        </bits>
        <bits access="rw" name="lram select" pos="5" rst="0x1">
          <comment>
            Select LRAM for the next access
            <br/>
            0 = Puncturing LRAM
            <br/>
            1 = Data LRAM
          </comment>
        </bits>
      </reg>
      <reg name="crc code lsb" protect="r">
        <bits access="r" display="hex" name="crc code" pos="31:0" rst="0xFFFFFFFF">
          <comment>CRC code LSB bits</comment>
        </bits>
      </reg>
      <reg name="crc code msb" protect="r">
        <bits access="r" display="hex" name="crc code" pos="7:0" rst="0x03">
          <comment>CRC code MSB bits</comment>
        </bits>
      </reg>
      <hole size="800"/>
      <reg name="cp2_select_reg" protect="rw">
        <bits access="rw" name="cp2 select" pos="0" rst="1">
          <comment>
            CP2 register access selection bit
            <br/>
            0= All registers are only accessible through the APB bus
            <br/>
            1= All registers are only accessible by the BCPU through the CP2 bus
          </comment>
        </bits>
      </reg>
      <reg name="lram_data_reg" protect="rw">
        <bits access="rw" display="hex" name="lram data" pos="31:0" rst="no">
          <comment>
            LRAM Data. This register is used for access to the
                     puncturing LRAM or to the Data LRAM.
            <br/>
            All access into this register, increment the LRAM_ADDR register.
          </comment>
        </bits>
      </reg>
    </module>
    <cjoker>
// changing xml generated defines
#undef BB_CP2_ENABLE_PUNCTURING
#undef BB_CP2_LRAM_DATA
#undef BB_CP2_BIT_NUMBER
#define BB_CP2_ENABLE_PUNCTURING(n) (((n)&amp;1)&lt;&lt;24)
/// BB_CP2 address mapping
#define BB_CP2_CTRL                              0
#define BB_CP2_BIT_NUMBER                        1
#define BB_CP2_STATUS                            2
#define BB_CP2_LRAM_ADDR                         3
#define BB_CP2_CRC_CODE_LSB                      4
#define BB_CP2_CRC_CODE_MSB                      5
#define BB_CP2_LRAM_DATA                         0
#define BB_CP2_LRAM_PUNC                         (0&lt;&lt;5)
#define BB_CP2_DATA_LRAM                         (1&lt;&lt;5)
/* BB_CP2 ACCESSES */
// macro for converting a constant to a string
#define CT_CONVERT_TO_STRING(x) #x
// control register -&gt; GPR
#define CT_BB_CP2_RD_CTRL_REG(regaddr, n)       asm volatile(&quot;cfc2 %0, $&quot; CT_CONVERT_TO_STRING(regaddr) :&quot;=r&quot;((n)))
//              GPR -&gt; control register
#define CT_BB_CP2_WR_CTRL_REG(regaddr, n)       asm volatile(&quot;ctc2 %0, $&quot; CT_CONVERT_TO_STRING(regaddr) ::&quot;r&quot;((n)))
// general register -&gt; GPR
#define CT_BB_CP2_RD_GNRL_REG_GPR(regaddr, n)   asm volatile(&quot;mfc2 %0, $&quot; CT_CONVERT_TO_STRING(regaddr) :&quot;=r&quot;((n)))
//              GPR -&gt; general register
#define CT_BB_CP2_WR_GNRL_REG_GPR(regaddr, n)   asm volatile(&quot;mtc2 %0, $&quot; CT_CONVERT_TO_STRING(regaddr) ::&quot;r&quot;((n)))
// general register -&gt; memory
#define CT_BB_CP2_RD_GNRL_REG_MEM(regaddr, out)	asm volatile(&quot;swc2 $&quot; CT_CONVERT_TO_STRING(regaddr) &quot;, 0(%0)&quot;::&quot;r&quot;((out)))
//           memory -&gt; general register
#define CT_BB_CP2_WR_GNRL_REG_MEM(regaddr, in) 	asm volatile(&quot;lwc2 $&quot; CT_CONVERT_TO_STRING(regaddr) &quot;, 0(%0)&quot;::&quot;r&quot;((in)))
</cjoker>
  </archive>
  <archive relative="bb_irq.xml">
    <include file="globals.xml"/>
    <module category="GGE_SYS" name="BB_IRQ">
      <enum name="BCPU_Irq_Lines">
        <entry name="BCpu_Main_Irq_Line">
          <comment>BCPU Irq Lines</comment>
        </entry>
        <entry name="XCpu_Wdt_Irq_Line" value="1"/>
        <entry name="BCpu_Debug_Irq_Line" value="4"/>
        <entry name="BCpu_Host_Irq_Line"/>
      </enum>
      <reg name="cause" protect="r">
        <comment>
          If cause is not null and interrupt are enabled then the interrupt line 0 is driven on the system CPU.
          <br/>
          The cause for the Irq sources, one bit for each module's irq source.
          <br/>
          The cause is the actual Irq source masked by the mask register.
        </comment>
        <bits access="r" cut="1" cutenum="Gge_Bb_Irq_Id" cutprefix="" cutstart="0" name="cause" pos="NB_GGE_BB_IRQ-1:0" rst="0"/>
      </reg>
      <reg name="status" protect="r">
        <comment>
          The status for the level Irq sources, one bit for each module's irq source.
          <br/>
          The status reflect the actual Irq source.
        </comment>
        <bits access="r" cut="1" cutenum="Gge_Bb_Irq_Id" cutprefix="" cutstart="0" name="status" pos="NB_GGE_BB_IRQ-1:0" rst="0"/>
      </reg>
      <reg name="mask_set" protect="rw">
        <comment>
          Writing '1' sets the corresponding bit in the mask register to '1'.
          <br/>
          Reading gives the value of the mask register.
        </comment>
        <bits access="rs" cut="1" cutenum="Gge_Bb_Irq_Id" cutprefix="" cutstart="0" name="mask_set" pos="NB_GGE_BB_IRQ-1:0" rst="0"/>
      </reg>
      <reg name="mask_clear" protect="rw">
        <comment>
          Writing '1' clears the corresponding bit in the mask register to '0'.
          <br/>
          Reading gives the value of the mask register.
        </comment>
        <bits access="rc" cut="1" cutenum="Gge_Bb_Irq_Id" cutprefix="" cutstart="0" name="mask_clr" pos="NB_GGE_BB_IRQ-1:0" rst="0"/>
      </reg>
      <reg name="nonmaskable" protect="rw">
        <bits access="r" name="main_irq" pos="10" rst="0">
          <comment>
            This is the Main Irq source it drive the system CPU interrupt line 0.
            <br/>
            This bit comes from the modules irq and is masked by the Mask and SC registers.
          </comment>
        </bits>
        <bits access="r" name="wdt_irq" pos="11" rst="0">
          <comment>
            This is the WDT Irq source it drive the system CPU interrupt line 1.
            <br/>
            This bit comes from watchdog module.
          </comment>
        </bits>
        <bits access="rw" name="debug_irq" pos="14" rst="0">
          <comment>This is the debug Irq source, the value written here drives the system CPU interrupt line 4.</comment>
        </bits>
        <bits access="r" name="host_irq" pos="15" rst="0">
          <comment>
            This is the Host Irq source it drive the system CPU interrupt line 5.
            <br/>
            This bit is controlled by the host internal register.
          </comment>
        </bits>
        <bits access="r" name="intenable_status" pos="31" rst="1">
          <comment>Status of the Interrupt enable semaphore bit.</comment>
        </bits>
      </reg>
      <reg name="sc" protect="">
        <bits access="rw" name="intenable" pos="0" rst="1">
          <comment>
            Interrupt enable semaphore, used for critical section.
            <br/>
            Read returns its value and then clears it to '0' disabling interrupts.
            <br/>
            Write the read value to restore the previous state, this will exit the critical section.
          </comment>
        </bits>
      </reg>
      <reg name="wakeup_mask" protect="rw">
        <comment>Each bit to '1' in that registers allows the correcponding interrupt to wake up the System CPU (i.e.: Reenable it's clock, see CLOCK_BB_ENABLE and CLOCK_BB_DISABLE registers in general registers section)</comment>
        <bits access="rw" cut="1" cutenum="Gge_Bb_Irq_Id" cutprefix="" cutstart="0" name="wakeup_mask" pos="NB_GGE_BB_IRQ-1:0" rst="0"/>
      </reg>
      <reg name="cpu_sleep" protect="w">
        <bits access="w" name="sleep" pos="0" rst="0">
          <comment>Writing '1' to this bit will put the BCPU to sleep (i.e.: Disable it's clock, see CLOCK_BB_ENABLE and CLOCK_BB_DISABLE registers in general registers section)</comment>
        </bits>
      </reg>
      <reg name="pulse_mask_set" protect="rw">
        <comment>
          Writing '1' sets the corresponding bit in the mask register to '1'.
          <br/>
          Reading gives the value of the mask register.
        </comment>
        <bits access="rs" cut="1" cutenum="Gge_Bb_Irq_Id" cutprefix="" cutstart="0" name="pulse_mask_set" pos="NB_GGE_BB_IRQ_PULSE-1:0" rst="0"/>
      </reg>
      <reg name="pulse_mask_clr" protect="rw">
        <comment>
          Writing '1' clears the corresponding bit in the mask register to '0'.
          <br/>
          Reading gives the value of the mask register.
        </comment>
        <bits access="rc" cut="1" cutenum="Gge_Bb_Irq_Id" cutprefix="" cutstart="0" name="pulse_mask_clr" pos="NB_GGE_BB_IRQ_PULSE-1:0" rst="0"/>
      </reg>
      <reg name="pulse_clear" protect="rw">
        <comment>
          Writing '1' clears the corresponding Pulse IRQ.
          <br/>
          Pulse IRQ are set by the modules and cleared here.
        </comment>
        <bits access="c" cut="1" cutenum="Gge_Bb_Irq_Id" cutprefix="" cutstart="0" name="pulse_clr" pos="NB_GGE_BB_IRQ_PULSE-1:0" rst="0"/>
      </reg>
      <reg name="pulse_status" protect="r">
        <comment>
          The status for the Pulse Irq sources, one bit for each module's irq source.
          <br/>
          The status reflect the actual Irq source.
        </comment>
        <bits access="r" cut="1" cutenum="Gge_Bb_Irq_Id" cutprefix="" cutstart="0" name="status" pos="NB_GGE_BB_IRQ_PULSE-1:0" rst="0"/>
      </reg>
    </module>
  </archive>
  <archive relative="bb_rom.xml">
    <var name="BB_ROM_SIZE" value="160*1024"/>
    <var name="NB_BB_PATCH" value="16"/>
    <var name="BB_PATCH_SIZE" value="64*4"/>
    <module category="GGE_SYS" name="BB_ROM">
      <memory name="rom_array" size="BB_ROM_SIZE">
        <comment>
          BB Rom Space
          <br/>
          This rom is used for BCPU.
        </comment>
      </memory>
    </module>
    <module category="GGE_SYS" name="BB_ROM_CTRL">
      <reg count="NB_BB_PATCH" name="rom_patch" protect="rw">
        <bits access="rw" name="block_addr" pos="18:4" rst="0">
          <comment>Base address of block in int_Rom patched (corresponding data are read from int_SRam)</comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
        <bits access="rw" name="patch_en" pos="31" rst="0">
          <options>
            <option name="Enable" value="1"/>
            <option name="Disable" value="0"/>
          </options>
        </bits>
      </reg>
      <hole size="1536"/>
      <memory name="ram_array" size="BB_PATCH_SIZE">
        <comment>
          BB Rom patch Ram Space
          <br/>
           Used for store the patch instead of rom, when patch is valid
        </comment>
      </memory>
    </module>
  </archive>
  <archive relative="cholk.xml">
    <module category="GGE_SYS" name="CHOLK">
      <reg32 name="cholk_ctrl" protect="rw">
        <bits access="rw" name="cholk_on" pos="0" rst="0">
          <comment>write 1 will enable CHOLK module</comment>
        </bits>
        <bits access="rw" name="cholk_int_mask" pos="1" rst="0">
          <comment>1:level INT will be masked, 0:level INT will not be masked</comment>
        </bits>
        <bits access="rw" name="cholk_mode" pos="2" rst="0">
          <comment>1: Complex mode ; 0: Real mode</comment>
        </bits>
      </reg32>
      <reg32 name="gain" protect="rw">
        <bits access="rw" name="resi_gain" pos="1:0" rst="0">
          <comment>RESI GAIN</comment>
        </bits>
        <bits access="rw" name="resi2_gain" pos="3:2" rst="0">
          <comment>RESI2 GAIN</comment>
        </bits>
        <bits access="rw" name="ogrs_gain" pos="5:4" rst="0">
          <comment>OGRS_GAIN</comment>
        </bits>
        <bits access="rw" name="oles1_gain" pos="7:6" rst="0">
          <comment>OLES1_GAIN</comment>
        </bits>
        <bits access="rw" name="oles2_gain" pos="9:8" rst="0">
          <comment>OLES2_GAIN</comment>
        </bits>
        <bits access="rw" name="coef_gain" pos="11:10" rst="0">
          <comment>COEF_GAIN</comment>
        </bits>
        <bits access="rw" name="grad_gain" pos="13:12" rst="0">
          <comment>GRAD_GAIN</comment>
        </bits>
        <bits access="rw" name="gops_gain" pos="15:14" rst="0">
          <comment>GOPS_GAIN</comment>
        </bits>
        <bits access="rw" name="oles3_gain" pos="17:16" rst="0">
          <comment>OLES3_GAIN</comment>
        </bits>
      </reg32>
      <reg32 name="iter_thre" protect="rw">
        <bits access="rw" name="iter_thre1" pos="15:0" rst="0">
          <comment>ITER_THRE1</comment>
        </bits>
      </reg32>
      <reg32 name="mcova_base" protect="rw">
        <bits access="rw" name="mcova_base" pos="12:0" rst="0">
          <comment>Matrix COVA base addr in BBSRAM</comment>
        </bits>
      </reg32>
      <reg32 name="mce_base" protect="rw">
        <bits access="rw" name="mce_base" pos="12:0" rst="0">
          <comment>CE base addr in BBSRAM</comment>
        </bits>
      </reg32>
      <reg32 name="mcoef_base" protect="rw">
        <bits access="rw" name="mcoef_base" pos="12:0" rst="0">
          <comment>COEF base addr in BBSRAM</comment>
        </bits>
      </reg32>
      <reg32 name="number" protect="rw">
        <bits access="rw" name="row_number" pos="4:0" rst="0">
          <comment>Matrix Row Number, maximal is 24 for Real, and 16 for Complex</comment>
        </bits>
        <bits access="rw" name="mcova_number" pos="13:5" rst="0">
          <comment>Matrix COVA effective element number - 1 to read</comment>
        </bits>
        <bits access="rw" name="iter_number" pos="18:14" rst="0">
          <comment>MAXIMAL iteration number - 1 for CHOLK</comment>
        </bits>
      </reg32>
      <reg32 name="cholk_status" protect="rw">
        <bits access="rw" name="cholk_status" pos="0" rst="1">
          <comment>CHOLK Done status, ACC enable and SW write this bit will clear this Done status, hardware will set this bit when done.</comment>
        </bits>
      </reg32>
      <reg32 name="echolk_int" protect="rw">
        <bits access="rw" name="echolk_int_raw" pos="0" rst="1">
          <comment>write 0 to this bit will clear CHOLK level RAW interrupt source bit, write 1 will not. read this bit will get raw cholk INT source bit</comment>
        </bits>
        <bits access="r" name="echolk_int_out" pos="1" rst="1">
          <comment>read this bit will get cholk INT status after masking. INT_out = INT_RAW and ~MASK</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="cipher.xml">
    <module category="GGE_SYS" name="CIPHER">
      <reg name="ctrl" protect="rw">
        <bits access="w" name="enable" pos="0" rst="no">
          <comment>Writing a '1' in this register triggers an A5 process. Ignored if the module is
            already processing. Auto-reset bit</comment>
        </bits>
        <bits access="rw" name="algorithm" pos="4" rst="1">
          <comment>Selects the appropriate algorithm</comment>
          <options>
            <option name="A5_1" value="0"/>
            <option name="A5_2" value="1"/>
          </options>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="running" pos="0" rst="0">
          <comment>1 when running, 0 in other case.</comment>
        </bits>
        <bits access="r" name="data_blk_rdy" pos="4" rst="0">
          <comment>1 when data block ready (Ciphering processed), reseted when the data register is read.</comment>
        </bits>
      </reg>
      <reg name="kc low" protect="rw">
        <bits access="rw" display="hex" name="kc_lsb" pos="31:0" rst="0xFFFFFFFF">
          <comment>Cipher key Kc, LSB bit [31:0].</comment>
        </bits>
      </reg>
      <reg name="kc high" protect="rw">
        <bits access="rw" display="hex" name="kc_msb" pos="31:0" rst="0xFFFFFFFF">
          <comment>Cipher key Kc, MSB bit [31:0].</comment>
        </bits>
      </reg>
      <reg name="count" protect="rw">
        <bits access="rw" display="hex" name="count" pos="21:0" rst="0x3FFFFFF">
          <comment>Count register, this field represent the TDMA frame number.</comment>
        </bits>
      </reg>
      <reg name="data0_block2" protect="r">
        <bits access="r" name="data_blk2" pos="31:0" rst="no">
          <comment>Data block2 bit[31:0]</comment>
        </bits>
      </reg>
      <reg name="data1_block2" protect="r">
        <bits access="r" name="data_blk2" pos="31:0" rst="no">
          <comment>Data block2 bit[63:32]</comment>
        </bits>
      </reg>
      <reg name="data2_block2" protect="r">
        <bits access="r" name="data_blk2" pos="31:0" rst="no">
          <comment>Data block2 bit[95:64]</comment>
        </bits>
      </reg>
      <reg name="data3_block2" protect="r">
        <bits access="r" name="data_blk2" pos="17:0" rst="no">
          <comment>Data block2 bit[113:96]</comment>
        </bits>
      </reg>
      <struct count="29" name="data_block1">
        <reg name="data block1" protect="r">
          <bits access="r" name="bit0" pos="7" rst="no">
            <comment/>
          </bits>
          <bits access="r" name="bit1" pos="15" rst="no">
            <comment/>
          </bits>
          <bits access="r" name="bit2" pos="23" rst="no">
            <comment/>
          </bits>
          <bits access="r" name="bit3" pos="31" rst="no">
            <comment/>
          </bits>
        </reg>
      </struct>
    </module>
  </archive>
  <archive relative="cipher_a53.xml">
    <module category="GGE_SYS" name="CIPHER_A53">
      <reg16 name="ciph_stat" protect="rw">
        <bits access="r" name="res" pos="15:5" rst="0">
      </bits>
        <bits access="rw" name="a53" pos="4" rst="0">
          <comment>Select Between A5/1-A5/2 and A5/3 Ciphering Block</comment>
        </bits>
        <bits access="rw" name="init" pos="3" rst="0">
          <comment>Initialize A5/3 Ciphering</comment>
        </bits>
        <bits access="rw" name="edge" pos="2" rst="0">
          <comment>Select Ciphering Blcok Size</comment>
        </bits>
        <bits access="rw" name="a52" pos="1" rst="0">
          <comment>Switch Between A5/1 and A5/2 Algorithm if A5/1-A5/2 Block is Selected</comment>
        </bits>
        <bits access="rw" name="cact" pos="0" rst="0">
          <comment>Status and Activation of Ciphering Block</comment>
        </bits>
      </reg16>
      <reg16 name="key register0" protect="rw">
        <bits access="rw" name="key0" pos="15:0" rst="0">
          <comment>Cipher Key0</comment>
        </bits>
      </reg16>
      <reg16 name="key register1" protect="rw">
        <bits access="rw" name="key1" pos="15:0" rst="0">
          <comment>Cipher Key1</comment>
        </bits>
      </reg16>
      <reg16 name="key register2" protect="rw">
        <bits access="rw" name="key2" pos="15:0" rst="0">
          <comment>Cipher Key2</comment>
        </bits>
      </reg16>
      <reg16 name="key register3" protect="rw">
        <bits access="rw" name="key3" pos="15:0" rst="0">
          <comment>Cipher Key3</comment>
        </bits>
      </reg16>
      <reg16 name="tmod26" protect="rw">
        <bits access="rw" name="a52_res_tmod26" pos="15:5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="a52_t26n" pos="4:0" rst="0">
          <comment/>
        </bits>
      </reg16>
      <reg16 name="tmod51" protect="rw">
        <bits access="rw" name="a52_res_tmod51" pos="15:6" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="a52_t51n" pos="5:0" rst="0">
          <comment/>
        </bits>
      </reg16>
      <reg16 name="sfnum" protect="rw">
        <bits access="rw" name="a52_res_sfnum" pos="15:11" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="a52_sfn" pos="10:0" rst="0">
          <comment/>
        </bits>
      </reg16>
      <reg16 name="key register4" protect="rw">
        <bits access="rw" name="key4" pos="15:0" rst="0">
          <comment>Cipher Key4</comment>
        </bits>
      </reg16>
      <reg16 name="key register5" protect="rw">
        <bits access="rw" name="key5" pos="15:0" rst="0">
          <comment>Cipher Key5</comment>
        </bits>
      </reg16>
      <reg16 name="key register6" protect="rw">
        <bits access="rw" name="key6" pos="15:0" rst="0">
          <comment>Cipher Key6</comment>
        </bits>
      </reg16>
      <reg16 name="key register7" protect="rw">
        <bits access="rw" name="key7" pos="15:0" rst="0">
          <comment>Cipher Key7</comment>
        </bits>
      </reg16>
      <reg16 name="key data1" protect="rw">
        <bits access="rw" name="ca" pos="15:8" rst="0">
          <comment>GSM mode:00001111
              EDGE mode:11110000</comment>
        </bits>
        <bits access="rw" name="cb" pos="7:3" rst="0">
          <comment>CB=0000</comment>
        </bits>
        <bits access="rw" name="cd" pos="2" rst="0">
          <comment>CD=0</comment>
        </bits>
        <bits access="r" name="res_key_dat1" pos="1:0" rst="0">
          <comment/>
        </bits>
      </reg16>
      <reg16 name="key data2" protect="rw">
        <bits access="rw" name="ce" pos="15:0" rst="0">
          <comment>CE=0000000000000000</comment>
        </bits>
      </reg16>
      <reg16 name="key data3" protect="rw">
        <bits access="r" name="res_15_14" pos="15:14" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="sfn_10_5" pos="13:8" rst="0">
          <comment/>
        </bits>
        <bits access="r" name="res_7_0" pos="7:0" rst="0">
          <comment/>
        </bits>
      </reg16>
      <reg16 name="key data4" protect="rw">
        <bits access="rw" name="sfn_4_0" pos="15:11" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="t51n" pos="10:5" rst="0">
          <comment/>
        </bits>
        <bits access="rw" name="t26n" pos="4:0" rst="0">
          <comment/>
        </bits>
      </reg16>
      <reg16 count="112" name="unused1" protect="rc">
  </reg16>
      <reg16 count="8" name="block1" protect="rw">
  </reg16>
      <reg16 count="24" name="unused2" protect="rc">
  </reg16>
      <reg16 count="8" name="block2" protect="rw">
  </reg16>
    </module>
    <module category="System" name="CIPHER_A53_SPRAM">
      <memory name="spram_array" size="64*2">
        <comment>cipher_a53 internal Spram space</comment>
      </memory>
    </module>
  </archive>
  <archive relative="cordic.xml">
    <module category="GGE_SYS" name="CORDIC">
      <reg name="yin" protect="rw">
        <bits access="rw" name="y_addr" pos="31:0" rst="0x0">
          <comment>Control setting. y, i.e. numerator of atan computation.</comment>
        </bits>
      </reg>
      <reg name="xin" protect="rw">
        <bits access="rw" name="x_addr" pos="31:0" rst="0x0">
          <comment>Control setting. x, i.e. denominator of atan computation.</comment>
        </bits>
      </reg>
      <reg name="cmd" protect="rw">
        <bits access="rw" name="cmd" pos="0:0" rst="0x0">
          <comment>The start signal. Use the posedge of this signal.</comment>
          <options>
            <option name="RST" value="0"/>
            <option name="START" value="1"/>
          </options>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="op" pos="31:0" rst="0x0">
          <comment>Status is set to 1 when an operation is finished.</comment>
          <options>
            <option name="Busy" value="0x00000000"/>
            <option name="Free" value="0xFFFFFFFF"/>
          </options>
        </bits>
      </reg>
      <reg name="dout" protect="r">
        <bits access="r" name="result_angle" pos="15:0" rst="0x0">
          <comment>. angle. The actual value is angle*pi/4</comment>
        </bits>
        <bits access="r" name="result_amplitude" pos="31:16" rst="0x0">
          <comment>amplitude.</comment>
        </bits>
      </reg>
      <reg name="amp" protect="r">
        <bits access="r" name="result_amp" pos="16:0" rst="0x0">
          <comment>amplitude only.</comment>
          <options>
            <mask/>
          </options>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="excor.xml">
    <include file="globals.xml"/>
    <module category="GGE_SYS" name="EXCOR">
      <var name="EXCOR_IDLE" value="0"/>
      <var name="EXCOR_BMMLZF" value="1"/>
      <var name="EXCOR_COMPMATRIMUL" value="2"/>
      <var name="EXCOR_COMPCONV" value="3"/>
      <var name="EXCOR_COMPPOW" value="4"/>
      <var name="EXCOR_DEROTATE" value="5"/>
      <var name="EXCOR_DCCOMP" value="6"/>
      <var name="EXCOR_SRECPSK8" value="7"/>
      <var name="EXCOR_FCCH" value="8"/>
      <var name="EXCOR_IR_COMB" value="9"/>
      <var name="EXCOR_IQ_SHIFT" value="10"/>
      <var name="EXCOR_STATUS_MASK" value="1"/>
      <var name="EXCOR_FASTMATRIMUL" value="11"/>
      <var name="EXCOR_FASTCONV" value="12"/>
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="cmd" pos="7:0" rst="0x0">
          <comment>Control setting. comand type.</comment>
        </bits>
        <bits access="rw" name="nb_iloop" pos="15:8" rst="0x0">
          <comment>Control setting. Number of internal loop iteration.</comment>
        </bits>
        <bits access="rw" name="nb_oloop" pos="25:16" rst="0x0">
          <comment>Control setting. Number of nb_symbol.</comment>
        </bits>
        <bits access="rw" name="shift_bit" pos="30:26" rst="0x0">
          <comment>Control setting. Number of shift bits.</comment>
        </bits>
      </reg>
      <reg name="addr0" protect="rw">
        <bits access="rw" name="addr0" pos="14:0" rst="0x0">
          <comment>address register 0.</comment>
        </bits>
      </reg>
      <reg name="addr1" protect="rw">
        <bits access="rw" name="addr1" pos="14:0" rst="0x0">
          <comment>address register 1.</comment>
        </bits>
      </reg>
      <reg name="addr2" protect="rw">
        <bits access="rw" name="addr2" pos="14:0" rst="0x0">
          <comment>address register 2.</comment>
        </bits>
      </reg>
      <reg name="addr3" protect="rw">
        <bits access="rw" name="addr3" pos="31:0" rst="0x0">
          <comment>address register 3.</comment>
        </bits>
      </reg>
      <reg name="addr4" protect="rw">
        <bits access="rw" name="addr4" pos="31:0" rst="0x0">
          <comment>address register 4.</comment>
        </bits>
      </reg>
      <reg name="addr5" protect="rw">
        <bits access="rw" name="addr5" pos="31:0" rst="0x0">
          <comment>address register 5.</comment>
        </bits>
      </reg>
      <reg name="data0" protect="rw">
        <bits access="rw" name="data0" pos="31:0" rst="0x0">
          <comment>data register 0.</comment>
        </bits>
      </reg>
      <reg name="data1" protect="rw">
        <bits access="rw" name="data1" pos="31:0" rst="0x0">
          <comment>data register 1.</comment>
        </bits>
      </reg>
      <reg name="data2" protect="rw">
        <bits access="rw" name="data2" pos="31:0" rst="0x0">
          <comment>data register 2.</comment>
        </bits>
      </reg>
      <reg name="data3" protect="rw">
        <bits access="rw" name="data3" pos="31:0" rst="0x0">
          <comment>data register 3.</comment>
        </bits>
      </reg>
      <reg name="data4" protect="rw">
        <bits access="rw" name="ircom_psidx0" pos="1:0" rst="0x0">
          <comment>for ircombine idx0</comment>
        </bits>
        <bits access="rw" name="ircom_psidx2" pos="5:4" rst="0x0">
          <comment>for ircombine idx1</comment>
        </bits>
        <bits access="rw" name="ircom_psidx1" pos="18:8" rst="0x0">
          <comment>for ircombine idx2</comment>
        </bits>
      </reg>
      <reg name="data5" protect="rw">
        <bits access="rw" name="data5" pos="31:0" rst="0x0">
          <comment>data register 5.</comment>
        </bits>
      </reg>
      <reg name="status" protect="rw">
        <bits access="rw" name="status" pos="7:0" rst="0x0">
          <comment>Status is set to 1 when an operation is finished.</comment>
        </bits>
      </reg>
      <reg name="ctrl_fast" protect="rw">
        <bits access="rw" name="loop_num_a" pos="2:0" rst="0x0">
          <comment>Control setting. Number of A row.</comment>
        </bits>
        <bits access="rw" name="loop_num_b" pos="6:4" rst="0x0">
          <comment>Control setting. Number of B column.</comment>
        </bits>
        <bits access="rw" name="loop_num_ab" pos="15:8" rst="0x0">
          <comment>Control setting. Number of  A column and B row.</comment>
        </bits>
        <bits access="rw" name="shift_bit_reg1" pos="20:16" rst="0x0">
          <comment>Control setting. Number of  shift bit after multiply.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="itlv.xml">
    <include file="globals.xml"/>
    <module category="GGE_SYS" name="ITLV">
      <reg name="command" protect="rw">
        <bits access="rw" name="nb_bits" pos="30:20" rst="0x0">
          <comment>Number of bits to be (De)Interleaved.</comment>
        </bits>
        <bits access="rw" name="burst_offset" pos="12:8" rst="0x0">
          <comment>This value gives the write offset (in number of bursts) to be
      added to a Burst Base address (ignored for Type 1b). For normal
      operation, this offset should be even (lsb will be ignored).</comment>
        </bits>
        <bits access="rw" name="itlv_type" pos="7:4" rst="0x0">
          <comment>Selects (de-)interleaving type.</comment>
          <options>
            <option name="TYPE_1A" value="0">
              <comment>TCH/FS, TCH/EFS, FACCH/F, TCH/F2.4, TCH/AFS (speech, ratscch, sid_first)</comment>
            </option>
            <option name="TYPE_1B" value="1">
              <comment>SACCH, TCH/AFS(sid_update), PDTCH(CS-1 to CS-4), BCCH, PCH, AGCH, PACCH, PBCCH, PAGCH, PPCH, PNCH, PTCCH/D</comment>
            </option>
            <option name="TYPE_1C" value="2">
              <comment>FACCH/H</comment>
            </option>
            <option name="TYPE_2A" value="3">
              <comment>TCH/HS and TCH/AHS</comment>
            </option>
            <option name="TYPE_2B" value="4">
              <comment>TCH/HS and TCH/AHS</comment>
            </option>
            <option name="TYPE_3" value="5">
              <comment>TCH/F14.4, TCH/F9.6, TCH/F4.8, TCH/H4.8, and TCH/H2.4</comment>
            </option>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="int_mask" pos="3" rst="0x0">
          <comment>Sets the interrupt mask ('1': interruption enabled)</comment>
        </bits>
        <bits access="rw" name="ditlv_start" pos="1" rst="0x0">
          <comment>Starts the de-interleaving process.</comment>
        </bits>
        <bits access="rw" name="itlv_start" pos="0" rst="0x0">
          <comment>Starts the interleaving process.</comment>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="busy" pos="0" rst="0x0">
          <comment>This bit is high when a (de-)interleaving process is ongoing. It
      stays high if the module is stalled during operation.</comment>
        </bits>
      </reg>
      <reg name="burst_base" protect="rw">
        <bits access="rw" name="burst_base" pos="BB_SRAM_ADDR_WIDTH+1:4" rst="0x0">
          <comment>This is the start address of the burst buffer in SRAM</comment>
        </bits>
      </reg>
      <reg name="frame_base" protect="rw">
        <bits access="rw" name="frame_base" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
          <comment>This is the start address of the frame buffer in
      SRAM.</comment>
        </bits>
      </reg>
      <reg name="int_status" protect="r">
        <bits access="r" name="it_status" pos="16" rst="0x0">
          <comment>This bit is the unmasked version of the IT_CAUSE bit.</comment>
        </bits>
        <bits access="r" name="it_cause" pos="0" rst="0x0">
          <comment>This bit is set when the ITLV module finishes an ongoing
      operation. It can be masked by setting ITLV_CMD(IT_MASK) to '1'.
      Resetting this bit is done by writing in IT_CLEAR register. IT_CAUSE is
      the image of the ITLV_DONE_H interrupt line to the CPU.</comment>
        </bits>
      </reg>
      <reg name="int_clear" protect="w">
        <bits access="w" name="it_clear" pos="0" rst="0x0">
          <comment>Setting this bit to '1' resets the Interleaver's
      interrupt.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_if.xml">
    <module category="GGE_SYS" name="RF_IF">
      <reg name="buffer" protect="rw">
        <bits access="rw" name="rx_tx data" pos="31:0" rst="no">
          <comment>
            In read mode this register contains the sample received on the Rx chain. I component is located on bit[15:0] and Q component is located on bit[31:16].
            <br/>
            This register accesses to the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data sample arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overflow error will also occur.
            <br/>
            The data written[29:0] into this register is the data transmitted. Any attempt to write data when the FIFO is full results in the write data being lost.
          </comment>
        </bits>
      </reg>
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="enable" pos="0" rst="0">
          <options>
            <option name="Disable" value="0"/>
            <option name="Enable" value="1"/>
          </options>
          <comment>Turn on/off the rf_if interface</comment>
        </bits>
        <bits access="rw" name="digrf enable" pos="1" rst="0">
          <options>
            <option name="Disable" value="0">
              <comment>Analog more selected</comment>
            </option>
            <option name="Enable" value="1">
              <comment>DigRF mode selected</comment>
            </option>
          </options>
          <comment>Turn on/off the DigRF mode</comment>
        </bits>
        <bits access="rw" name="rx overflow enable" pos="4" rst="1">
          <options>
            <option name="Disable" value="0">
              <comment>Disable (mask) Rx fifo overflow interrupt</comment>
            </option>
            <option name="Enable" value="1">
              <comment>Enable Rx fifo overflow interrupt</comment>
            </option>
          </options>
          <comment>Rx Fifo Overflow interrupt Enable</comment>
        </bits>
        <bits access="rw" name="rx cal bypass" pos="5" rst="1">
          <options>
            <option name="Enabled" value="0"/>
            <option name="Bypassed" value="1"/>
          </options>
          <comment>Calibration bypass</comment>
        </bits>
        <bits access="rw" name="rx swap i_q" pos="6" rst="0">
          <options>
            <option name="NO" value="0">
              <comment>No Swap</comment>
            </option>
            <option name="YES" value="1">
              <comment>Swap I/Q</comment>
            </option>
          </options>
          <comment>Rx swap I/Q</comment>
        </bits>
        <bits access="rw" name="rx force adc on" pos="7" rst="0">
          <options>
            <option name="NO" value="0">
              <comment>No forced, Rx_On output controlled by TCO_RX_ON signal from the TCU</comment>
            </option>
            <option name="YES" value="1">
              <comment>Forced ADC on;Rx_On output always high</comment>
            </option>
          </options>
          <comment>Force Rx On. This bit is used only with the analog option.</comment>
        </bits>
        <bits access="rw" name="rx force dec on" pos="8" rst="0">
          <options>
            <option name="NO" value="0">
              <comment>No forced, decimator controlled by Rx_dec_on signal from the TCU</comment>
            </option>
            <option name="YES" value="1">
              <comment>Forced; decimator always on</comment>
            </option>
          </options>
          <comment>Force Decimator On</comment>
        </bits>
        <bits access="w" name="rx force soc" pos="9" rst="no">
          <comment>
            Force start of calibation in receive mode
            <br/>
            Writing a 1 to this bit launch the calibration phase. Write only bit, this bit doesn't need to be cleared.
          </comment>
        </bits>
        <bits access="w" name="rx fifo reset" pos="10" rst="no">
          <comment>
            Writing a 1 to this bit resets and flush the receive Fifo.
            <br/>
            Write only bit, this bit doesn't need to be cleared.
          </comment>
        </bits>
        <bits access="rw" name="tx overflow enable" pos="16" rst="1">
          <options>
            <option name="Disable" value="0">
              <comment>Disable (mask) Tx fifo overflow interrupt</comment>
            </option>
            <option name="Enable" value="1">
              <comment>Enable Tx fifo overflow interrupt</comment>
            </option>
          </options>
          <comment>Tx Fifo Overflow interrupt Enable</comment>
        </bits>
        <bits access="rw" name="tx underflow enable" pos="17" rst="1">
          <options>
            <option name="Disable" value="0">
              <comment>Disable (mask) Tx fifo undeflow interrupt</comment>
            </option>
            <option name="Enable" value="1">
              <comment>Enable Tx fifo underflow interrupt</comment>
            </option>
          </options>
          <comment>Tx Fifo Underflow interrupt Enable:</comment>
        </bits>
        <bits access="rw" name="tx force dac on" pos="18" rst="0">
          <options>
            <option name="NO" value="0">
              <comment>No forced, Tx_On output controlled by TCO_TX_ON signal from the TCU</comment>
            </option>
            <option name="YES" value="1">
              <comment>Forced DAC on; Tx_On output always high</comment>
            </option>
          </options>
          <comment>Force DAC On. This bit is used only with the analog option.</comment>
        </bits>
        <bits access="rw" name="tx force dac off" pos="19" rst="0">
          <options>
            <option name="NO" value="0">
              <comment>No forced, Tx_On output controlled by TCO_TX_ON signal from the TCU</comment>
            </option>
            <option name="YES" value="1">
              <comment>Forced DAC Off; Tx_On output always low</comment>
            </option>
          </options>
          <comment>Force DAC Off. This bit is used only with the analog option.</comment>
        </bits>
        <bits access="rw" name="tx force oen" pos="20" rst="0">
          <options>
            <option name="NO" value="0">
              <comment>No forced, Tx_Oen controlled by TCO_TX_OEN signal from the TCU</comment>
            </option>
            <option name="YES" value="1">
              <comment>Forced; Tx_Oen always high, Low pass output in HZ</comment>
            </option>
          </options>
          <comment>Force Tx Oen. This bit is used only with the analog option.</comment>
        </bits>
        <bits access="rw" name="tx force gmsk on" pos="21" rst="0">
          <options>
            <option name="NO" value="0">
              <comment>No forced, transmit serial interface controlled by TCO_GMSK_ON signal from the TCU</comment>
            </option>
            <option name="YES" value="1">
              <comment>Forced; serializer always enabled</comment>
            </option>
          </options>
          <comment>Force GMSK On.</comment>
        </bits>
        <bits access="rw" name="tx swap i_q" pos="22" rst="0">
          <options>
            <option name="NO" value="0">
              <comment>No Swap</comment>
            </option>
            <option name="YES" value="1">
              <comment>Swap I/Q</comment>
            </option>
          </options>
          <comment>Tx swap I/Q. This bit is used only with the analog option.</comment>
        </bits>
        <bits access="w" name="tx fifo reset" pos="23" rst="no">
          <comment>
            Writing a 1 to this bit resets and flush the transmit Fifo.
            <br/>
            Write only bit, this bit doesn.t need to be cleared.
          </comment>
        </bits>
        <bits access="rw" name="digrf rx rate" pos="24" rst="1">
          <options>
            <option name="ONE" value="0">
              <comment>One sample per symbol</comment>
            </option>
            <option name="TWO" value="1">
              <comment>Two samples per symbol</comment>
            </option>
          </options>
          <comment>Rx rate for DigRF interface. This bit is used only when DigRF is enabled (DigRF Enabled)</comment>
        </bits>
        <bits access="rw" name="digrf rx clk pol" pos="25" rst="1">
          <comment>
            Change the polarity of the DigRF Rx clock. This bit is used only when DigRF is enabled (DigRF Enabled)
            <br/>
            0 = No inversion
            <br/>
            1 = Invert clock polarity
          </comment>
        </bits>
        <bits access="rw" name="digrf tx mode" pos="26" rst="1">
          <options>
            <option name="Stream" value="0"/>
            <option name="Block" value="1"/>
          </options>
          <comment>Tx mode for the DigRF interface. This bit is used only when DigRF is enabled (DigRF Enabled)</comment>
        </bits>
        <bits access="rw" name="digrf tx clk pol" pos="27" rst="1">
          <comment>
            Change the polarity of the DigRF Rx clock. This bit is used only when DigRF is enabled (DigRF Enabled)
            <br/>
            0 = No inversion
            <br/>
            1 = Invert clock polarity
          </comment>
        </bits>
        <bits access="rw" display="hex" name="digrf sample size" pos="30:28" rst="all1">
          <comment>
            Shift input sample in DigRF mode only.
            <br/>
            The Rx sample are on 16-bit, this field select a variable of bit among 16.
            <br/>
            000 = 16-bit selected
            <br/>
            001 = 15-bit selected
            <br/>
            010 = 14-bit selected
            <br/>
            011 = 13-bit selected
            <br/>
            100 = 12-bit selected
          </comment>
        </bits>
        <bits access="rw" display="hex" name="digrf alignement select" pos="31" rst="1">
          <comment>
            Select the sample alignement in DigRF mode only..
            <br/>
            0 = MSB aligned sample
            <br/>
            1 = LSB aligned sample
          </comment>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="rx fifo level" pos="4:0" rst="0">
          <comment>Those bits indicate the number of data available in the Rx Fifo.</comment>
        </bits>
        <bits access="r" name="tx fifo level" pos="6:5" rst="0">
          <comment>Those bits indicate the number of data available in the Tx Fifo. Those data will be sent.</comment>
        </bits>
        <bits access="r" name="rx overflow cause" pos="8" rst="0">
          <comment>
            Rx overflow cause register
            <br/>
            This bit indicates that an interruption was generated when the Rx fifo is overflow.
            <br/>
            This bit is cleared when the Rx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written.
          </comment>
        </bits>
        <bits access="r" name="tx overflow cause" pos="9" rst="0">
          <comment>
            Tx overflow cause register
            <br/>
            This bit indicates that an interruption was generated when the Tx fifo is overflow.
            <br/>
            This bit is cleared when the Tx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written.
          </comment>
        </bits>
        <bits access="r" name="tx underflow cause" pos="10" rst="0">
          <comment>
            Tx underflow cause register
            <br/>
            This bit indicates that an interruption was generated when the Tx fifo is underflow.
            <br/>
            This bit is cleared when the Tx_underflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written.
          </comment>
        </bits>
        <bits access="r" name="rx overflow status" pos="16" rst="0">
          <comment>
            This bit indicates that the receiver received a new sample when the FIFO was already full.
            <br/>
            The new sample is discarded. This bit is cleared when the Rx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written
          </comment>
        </bits>
        <bits access="r" name="tx overflow status" pos="17" rst="0">
          <comment>
            This bit indicates that the user tried to write on the FIFO while it was already full.
            <br/>
            This bit is cleared when the Tx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written
          </comment>
        </bits>
        <bits access="r" name="tx underflow status" pos="18" rst="0">
          <comment>
            This bit indicates that the modulator tried to read on the FIFO while it was empty.
            <br/>
            This bit is cleared when the Tx_Underflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written
          </comment>
        </bits>
      </reg>
      <reg name="interruption_clear" protect="w">
        <bits access="w" name="rx overflow" pos="0" rst="no">
          <comment>Clear Rx Interrupt Overflow interrupt.</comment>
        </bits>
        <bits access="w" name="tx overflow" pos="1" rst="no">
          <comment>Clear Tx Interrupt Overflow interrupt.</comment>
        </bits>
        <bits access="w" name="tx underflow" pos="2" rst="no">
          <comment>Clear Tx Interrupt Underflow interrupt.</comment>
        </bits>
      </reg>
      <reg count="4" name="tx burst descriptor" protect="rw">
        <bits access="rw" name="nb symbols" pos="7:0" rst="0">
          <comment>Number of symbol to transmit</comment>
        </bits>
        <bits access="rw" name="modulation" pos="16" rst="0">
          <comment>0 for GMSK, 1 for 8PSK</comment>
        </bits>
        <bits access="rw" name="end burst" pos="24" rst="0">
          <comment>Indicate an end of the transmit for this current burst</comment>
        </bits>
      </reg>
      <reg name="rx offset" protect="r">
        <bits access="r" display="hex" name="rx_offset_i" pos="15:0" rst="all0">
          <comment>Rx offset measured after calibration for I channel</comment>
        </bits>
        <bits access="r" display="hex" name="rx_offset_q" pos="31:16" rst="all0">
          <comment>Rx offset measured after calibratio for Q channel</comment>
        </bits>
      </reg>
      <reg name="rx gain" protect="rw">
        <bits access="rw" display="hex" name="rx_gain_dig" pos="9:0" rst="all0">
          <comment>Rx Gain digital</comment>
        </bits>
        <bits access="rw" display="hex" name="rx_gain_ana" pos="12:10" rst="all0">
          <comment>Rx Gain analog</comment>
        </bits>
        <bits access="rw" display="hex" name="rx_gain_en" pos="13" rst="all0">
          <comment>Rx Gain  enable</comment>
        </bits>
      </reg>
      <hole size="192"/>
      <reg name="rx_control" protect="w">
        <bits access="w" name="enable_ctrl" pos="0" rst="no">
          <comment>
            Channel Enable, write one in this bit enable the channel.
            <br/>
            When the channel is enabled, for a peripheral to memory transfer
       the DMA wait request from peripheral to start transfer.
          </comment>
        </bits>
        <bits access="w" name="disable_ctrl" pos="1" rst="no">
          <comment>
            Channel Disable, write one in this bit disable the channel.
            <br/>
            When writing one in this bit, the current AHB transfer and current
       APB transfer (if one in progress) is completed and the channel is then
       disabled.
          </comment>
        </bits>
        <bits access="rw" name="burst_size" pos="16" rst="1">
          <comment>
            Burst size on AHB bus
            <br/>
            0 = Single access
            <br/>
            1 = burst Access (4 words).
          </comment>
        </bits>
        <bits access="rw" name="fifo_mode" pos="17" rst="1">
          <comment>
            Set FIFO mode .
            <br/>
            0 = no fifo mode, transfer stop when the
      current transfer counter reaches zero. Channel must be re-enabled for
      future transfer.
            <br/>
            1 = Fifo mode, when the current AHB address
      counter reaches the end address of the FIFO. AHB address counter is
      reloaded with the initial value. In FIFO mode channel is not disabled at
      the end of the transfer.
          </comment>
        </bits>
      </reg>
      <reg name="rx_status" protect="r">
        <bits access="r" name="enable_ctrl" pos="0" rst="0">
          <options>
            <option name="DISABLE" value="0"/>
            <option name="ENABLE" value="1"/>
            <default/>
          </options>
          <comment>In no fifo mode the channel is automatically disabled at the
       end of the transfer. In fifo mode the channel is disabled only when
       disabled write is performed in the control register.</comment>
        </bits>
        <bits access="r" name="fifo_empty" pos="1" rst="1">
          <comment>When 1 the fifo is empty</comment>
        </bits>
        <bits access="r" name="cause_nb_htc" pos="2" rst="0">
          <comment>Cause interrupt half tc  when fifo mode is enable.</comment>
        </bits>
        <bits access="r" name="nb_htc" pos="3" rst="0">
          <comment>Half of TC interrupt when fifo mode is enable status bit.</comment>
        </bits>
        <bits access="r" name="cause_itc" pos="4" rst="0">
          <comment>Cause interrupt End of TC.</comment>
        </bits>
        <bits access="r" name="cause_ief" pos="5" rst="0">
          <comment>Cause interrupt End of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_ihtc" pos="6" rst="0">
          <comment>Cause interrupt Half Transfer Count (This interruption is
      generated when the IFC has transferred 96 word).</comment>
        </bits>
        <bits access="r" name="itc" pos="7" rst="0">
          <comment>End of TC interrupt status bit.</comment>
        </bits>
        <bits access="r" name="ief" pos="8" rst="0">
          <comment>End of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="ihtc" pos="9" rst="0">
          <comment>Half TC interrupt status bit.</comment>
        </bits>
        <bits access="r" name="cur_tc" pos="31:10" rst="0x3fffff">
          <comment>Current value of transfer counter.</comment>
        </bits>
      </reg>
      <reg name="rx_start_addr" protect="rw">
        <bits access="rw" display="hex" name="start_addr" pos="31:2" rst="0x3FFFFFFF">
          <comment>AHB Start Address.</comment>
        </bits>
      </reg>
      <reg name="rx_end_addr" protect="rw">
        <bits access="rw" display="hex" name="end_addr" pos="31:2" rst="0x3FFFFFFF">
          <comment>The last page address of the FIFO, it is the first address not
      used for the FIFO. The start address of the FIFO is specified by the
      register AHB_ADDR and the last page address of the FIFO is specified by
      this field. The size of the fifo (END_ADDR - START_ADDR) must be a
      multiple of burst of 4x32-bits.</comment>
        </bits>
      </reg>
      <reg name="rx_tc_reg" protect="rw">
        <bits access="r" display="hex" name="tc_reg" pos="21:0" rst="0x3FFFFF">
          <comment>
            Transfer Count
            <br/>
            In no FIFO mode, this bit indicated
      the transfer size in 32-bits word to perform. Up to 2^18 32-bits word per
      transfer.
            <br/>
            In FIFO mode this field define, after how many
      transfer an interrupt in generated.
          </comment>
        </bits>
      </reg>
      <reg name="rx_int_mask" protect="rw">
        <bits access="rw" name="end_tc" pos="0" rst="0">
          <comment>End TC Mask interrupt. When one this interrupt is
      enabled.</comment>
        </bits>
        <bits access="rw" name="end_fifo" pos="1" rst="0">
          <comment>END FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="half_tc" pos="2" rst="0">
          <comment>Half TC Mask interrupt. When one this interrupt is
      enabled</comment>
        </bits>
        <bits access="rw" name="nb_half_tc" pos="3" rst="0">
          <comment>NB Half TC Mask interrupt. only fifo mode is enabled, When one this interrupt is
      enabled</comment>
        </bits>
      </reg>
      <reg name="rx_int_clear" protect="rw">
        <bits access="c" name="end_tc" pos="0" rst="0">
          <comment>Write one to clear end of TC interrupt.</comment>
        </bits>
        <bits access="c" name="end_fifo" pos="1" rst="0">
          <comment>Write one to clear end of FIFO interrupt.</comment>
        </bits>
        <bits access="c" name="half_fifo" pos="2" rst="0">
          <comment>Write one to clear end of Half TC interrupt.</comment>
        </bits>
        <bits access="c" name="nb_half_fifo" pos="3" rst="0">
          <comment>Write one to clear end of Half TC (the real one) interrupt.</comment>
        </bits>
      </reg>
      <reg name="rx_cur_ahb_addr" protect="r">
        <bits access="r" name="cur_ahb_addr" pos="31:0" rst="0x3ffe000">
          <comment>Current AHB address value.</comment>
        </bits>
      </reg>
      <reg name="tx_control" protect="w">
        <bits access="w" name="enable_ctrl" pos="0" rst="no">
          <comment>
            Channel Enable, write one in this bit enable the channel.
            <br/>
            When the channel is enabled, for a peripheral to memory transfer
       the DMA wait request from peripheral to start transfer.
          </comment>
        </bits>
        <bits access="w" name="disable_ctrl" pos="1" rst="no">
          <comment>
            Channel Disable, write one in this bit disable the channel.
            <br/>
            When writing one in this bit, the current AHB transfer and current
       APB transfer (if one in progress) is completed and the channel is then
       disabled.
          </comment>
        </bits>
        <bits access="rw" name="burst_size" pos="16" rst="1">
          <comment>
            Burst size on AHB bus
            <br/>
            0 = Single access
            <br/>
            1 = burst Access (4 words).
          </comment>
        </bits>
        <bits access="rw" name="fifo_mode" pos="17" rst="1">
          <comment>
            Set FIFO mode .
            <br/>
            0 = no fifo mode, transfer stop when the
      current transfer counter reaches zero. Channel must be re-enabled for
      future transfer.
            <br/>
            1 = Fifo mode, when the current AHB address
      counter reaches the end address of the FIFO. AHB address counter is
      reloaded with the initial value. In FIFO mode channel is not disabled at
      the end of the transfer.
          </comment>
        </bits>
      </reg>
      <reg name="tx_status" protect="r">
        <bits access="r" name="enable_ctrl" pos="0" rst="0">
          <options>
            <option name="DISABLE" value="0"/>
            <option name="ENABLE" value="1"/>
            <default/>
          </options>
          <comment>In no fifo mode the channel is automatically disabled at the
       end of the transfer. In fifo mode the channel is disabled only when
       disabled write is performed in the control register.</comment>
        </bits>
        <bits access="r" name="fifo_empty" pos="1" rst="1">
          <comment>When 1 the fifo is empty</comment>
        </bits>
        <bits access="r" name="cause_nb_htc" pos="2" rst="0">
          <comment>Cause interrupt half tc  when fifo mode is enable.</comment>
        </bits>
        <bits access="r" name="nb_htc" pos="3" rst="0">
          <comment>Half of TC interrupt when fifo mode is enable status bit.</comment>
        </bits>
        <bits access="r" name="cause_itc" pos="4" rst="0">
          <comment>Cause interrupt End of TC.</comment>
        </bits>
        <bits access="r" name="cause_ief" pos="5" rst="0">
          <comment>Cause interrupt End of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_ihtc" pos="6" rst="0">
          <comment>Cause interrupt Half Transfer Count (This interruption is
      generated when the IFC has transferred 96 word).</comment>
        </bits>
        <bits access="r" name="itc" pos="7" rst="0">
          <comment>End of TC interrupt status bit.</comment>
        </bits>
        <bits access="r" name="ief" pos="8" rst="0">
          <comment>End of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="ihtc" pos="9" rst="0">
          <comment>Half TC interrupt status bit.</comment>
        </bits>
        <bits access="r" name="cur_tc" pos="31:10" rst="0x3fffff">
          <comment>Current value of transfer counter.</comment>
        </bits>
      </reg>
      <reg name="tx_start_addr" protect="rw">
        <bits access="rw" display="hex" name="start_addr" pos="31:2" rst="0x3FFFFFFF">
          <comment>AHB Start Address.</comment>
        </bits>
      </reg>
      <reg name="tx_end_addr" protect="rw">
        <bits access="rw" display="hex" name="end_addr" pos="31:2" rst="0x3FFFFFFF">
          <comment>The last page address of the FIFO, it is the first address not
      used for the FIFO. The start address of the FIFO is specified by the
      register AHB_ADDR and the last page address of the FIFO is specified by
      this field. The size of the fifo (END_ADDR - START_ADDR) must be a
      multiple of burst of 4x32-bits.</comment>
        </bits>
      </reg>
      <reg name="tx_tc_reg" protect="rw">
        <bits access="r" display="hex" name="tc_reg" pos="21:0" rst="0x3FFFFF">
          <comment>
            Transfer Count
            <br/>
            In no FIFO mode, this bit indicated
      the transfer size in 32-bits word to perform. Up to 2^18 32-bits word per
      transfer.
            <br/>
            In FIFO mode this field define, after how many
      transfer an interrupt in generated.
          </comment>
        </bits>
      </reg>
      <reg name="tx_int_mask" protect="rw">
        <bits access="rw" name="end_tc" pos="0" rst="0">
          <comment>End TC Mask interrupt. When one this interrupt is
      enabled.</comment>
        </bits>
        <bits access="rw" name="end_fifo" pos="1" rst="0">
          <comment>END FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="half_tc" pos="2" rst="0">
          <comment>Half TC Mask interrupt. When one this interrupt is
      enabled</comment>
        </bits>
        <bits access="rw" name="nb_half_tc" pos="3" rst="0">
          <comment>NB Half TC Mask interrupt. only fifo mode is enabled, When one this interrupt is
      enabled</comment>
        </bits>
      </reg>
      <reg name="tx_int_clear" protect="rw">
        <bits access="c" name="end_tc" pos="0" rst="0">
          <comment>Write one to clear end of TC interrupt.</comment>
        </bits>
        <bits access="c" name="end_fifo" pos="1" rst="0">
          <comment>Write one to clear end of FIFO interrupt.</comment>
        </bits>
        <bits access="c" name="half_fifo" pos="2" rst="0">
          <comment>Write one to clear end of Half TC interrupt.</comment>
        </bits>
        <bits access="c" name="nb_half_fifo" pos="3" rst="0">
          <comment>Write one to clear end of Half TC (the real one) interrupt.</comment>
        </bits>
      </reg>
      <reg name="tx_cur_ahb_addr" protect="r">
        <bits access="r" name="cur_ahb_addr" pos="31:0" rst="0x3ffe000">
          <comment>Current AHB address value.</comment>
        </bits>
      </reg>
      <reg name="rfif_ctrl" protect="rw">
        <bits access="rw" display="hex" name="dump_en" pos="0" rst="0x0">
          <comment>dump the 'data from dfe to nb core' to mem</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_mode" pos="1" rst="0x0">
          <comment>when the bit is 1, dump only when nb-core comes an pulse ,capture the set data numbers ,then stop
                   when the bit is 0, dump all bit normal dump mode</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_downsample" pos="2" rst="0x0">
          <comment>when the bit is 1, downsample enable
                   when the bit is 0, disable</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_dl" pos="4" rst="0x0">
          <comment>get data from mem, simu the data format from dfe to nb core</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_ul" pos="5" rst="0x0">
          <comment>get data from mem, simu the data format from nbcore to dfe</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_speed_div" pos="23:8" rst="0x20">
          <comment>feed data rate  1.92MHz=0x20 192KHz=0x140, 96KHz=0x280, 38.4KHz=0x640, 32KHz=0x780</comment>
        </bits>
        <bits access="r" display="hex" name="feed_fifo_empty" pos="24" rst="0x1">
          <comment>fifo empty siganl</comment>
        </bits>
        <bits access="r" display="hex" name="dump_fifo_empty" pos="25" rst="0x1">
          <comment>fifo empty signal</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_fifo_clr" pos="26" rst="0x0">
          <comment>clr feed fifo point</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_fifo_clr" pos="27" rst="0x0">
          <comment>clr dump fifo point</comment>
        </bits>
        <bits access="rw" display="hex" name="nb_debug" pos="31" rst="0x0">
          <comment>when the bit is 1, nb use the rf_dma
                   when the bit is 0, 2g use the rf_dma</comment>
        </bits>
      </reg>
      <reg name="dfe_filter_ctrl" protect="rw">
        <bits access="rw" display="hex" name="bw_sel" pos="3:0" rst="0x0">
          <comment>the bandwidth select signal</comment>
        </bits>
        <bits access="rw" display="hex" name="filter_bypass" pos="4" rst="0x1">
          <comment>bypass the filter function to the data</comment>
        </bits>
        <bits access="rw" display="hex" name="iq_mismatch" pos="8" rst="0x0">
          <comment>combine a unused data with I0 used as I0Q0,  combine Q0I1 , used as I1Q1.
                   next goes on. the last Qn will be discarded.</comment>
        </bits>
        <bits access="rw" display="hex" name="rbdp_delay_sel" pos="15:12" rst="0xa">
          <comment>set the delay of fclk_fordata to delay the rbdp_tx data</comment>
        </bits>
        <bits access="rw" display="hex" name="fclk_delay_sel" pos="19:16" rst="0x2">
          <comment>set the delay of fclk external, only for the clk_phy gen fclk</comment>
        </bits>
        <bits access="rw" display="hex" name="fclk_source_sel" pos="20" rst="0x0">
          <comment>1'b0 the source is fclk gen by clk_phy, 1'b1 the source is mclk</comment>
        </bits>
      </reg>
      <hole size="192"/>
      <reg name="nb_if_irsr" protect="rw">
        <bits access="rw" display="hex" name="dump_ovfl" pos="0" rst="0x0">
          <comment>dump_ovfl irq</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_udfl" pos="1" rst="0x0">
          <comment>dump_udfl irq</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_ovfl" pos="2" rst="0x0">
          <comment>feed_ovfl irq</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_udfl" pos="3" rst="0x0">
          <comment>feed_udfl irq</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_ovfl_real" pos="4" rst="0x0">
          <comment>dump_ovfl  when  ifc is still working irq</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_udfl_real" pos="5" rst="0x0">
          <comment>dump_udfl  when  ifc is still working irq</comment>
        </bits>
      </reg>
      <reg name="nb_if_imr" protect="rw">
        <bits access="rw" display="hex" name="dump_ovfl" pos="0" rst="0x0">
          <comment>dump_ovfl mask</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_udfl" pos="1" rst="0x0">
          <comment>dump_udfl mask</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_ovfl" pos="2" rst="0x0">
          <comment>feed_ovfl mask</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_udfl" pos="3" rst="0x0">
          <comment>feed_udfl mask</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_ovfl_real" pos="4" rst="0x0">
          <comment>dump_ovfl  when  ifc is still working  mask</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_udfl_real" pos="5" rst="0x0">
          <comment>dump_udfl  when  ifc is still working  mask</comment>
        </bits>
      </reg>
      <reg name="nb_if_isr" protect="rw">
        <bits access="rw" display="hex" name="dump_ovfl" pos="0" rst="0x0">
          <comment>dump_ovfl  before mask irq source</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_udfl" pos="1" rst="0x0">
          <comment>dump_udfl  before mask irq source</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_ovfl" pos="2" rst="0x0">
          <comment>feed_ovfl  before mask irq source</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_udfl" pos="3" rst="0x0">
          <comment>feed_udfl  before mask irq source</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_ovfl_real" pos="4" rst="0x0">
          <comment>dump_ovfl  when  ifc is still working irq  source</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_udfl_real" pos="5" rst="0x0">
          <comment>dump_udfl  when  ifc is still working irq source</comment>
        </bits>
      </reg>
      <reg name="nb_if_icr" protect="rw">
        <bits access="rw" display="hex" name="dump_ovfl" pos="0" rst="0x0">
          <comment>dump_ovfl clr irq</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_udfl" pos="1" rst="0x0">
          <comment>dump_udfl clr irq</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_ovfl" pos="2" rst="0x0">
          <comment>feed_ovfl clr irq</comment>
        </bits>
        <bits access="rw" display="hex" name="feed_udfl" pos="3" rst="0x0">
          <comment>feed_udfl clr irq</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_ovfl_real" pos="4" rst="0x0">
          <comment>dump_ovfl  when  ifc is still working clr irq</comment>
        </bits>
        <bits access="rw" display="hex" name="dump_udfl_real" pos="5" rst="0x0">
          <comment>dump_udfl  when  ifc is still working clr irq</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_spi.xml">
    <var name="CMD_FIFO_LEN_BITS" value="5"/>
    <var name="CMD_FIFO_LEN" value="20"/>
    <var name="CMD_SIZE_BITS" value="8"/>
    <var name="CMD_DATA_FIFO_LEN_BITS" value="4"/>
    <var name="CMD_DATA_FIFO_LEN" value="exp2(CMD_DATA_FIFO_LEN_BITS)"/>
    <var name="GAIN_TABLE_LEN_BITS" value="4"/>
    <var name="GAIN_TABLE_LEN" value="15"/>
    <var name="GAIN_SIZE_BITS" value="4"/>
    <var name="RX_DATA_FIFO_LEN_BITS" value="2"/>
    <var name="RX_DATA_FIFO_LEN" value="exp2(RX_DATA_FIFO_LEN_BITS)"/>
    <module category="GGE_SYS" name="RF_SPI">
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="enable" pos="0" rst="0">
          <comment>
            Enable the rf spi
            <br/>
            1 = Enable
            <br/>
            0 = Disable (will finish current command anyway)
          </comment>
        </bits>
        <bits access="rw" name="cs_polarity" pos="1" rst="1">
          <comment>
            Chip select polarity
            <br/>
            1 = the chip select is active low
            <br/>
            0 = the chip select is active high
          </comment>
        </bits>
        <bits access="rw" name="digrf_read" pos="2" rst="1">
          <comment>
            DigRF Read style mode
            <br/>
            1 = DigRF Read style mode (read after CS disabled)
            <br/>
            0 = SPI Read mode (read during write)
          </comment>
        </bits>
        <bits access="rw" name="clocked_back2back" pos="3" rst="1">
          <comment>
            DigRF style clocked back to back mode
            <br/>
            1 = clocked back to back transfers using turnarround timing only when more data are present in the FIFO.
            <br/>
            0 = stop the clock between each access according to CS_End_Hold and CS_Pulse_Min timings
          </comment>
        </bits>
        <bits access="rw" name="input_mode" pos="4" rst="1">
          <comment>
            Input mode
            <br/>
            1 = Record input data to input FIFO
            <br/>
            0 = No input data
          </comment>
        </bits>
        <bits access="rw" name="clock_polarity" pos="5" rst="1">
          <comment>
            SPI Clock polarity
            <br/>
            1 = the clock disabled level is high, and the first edge is a falling edge.
            <br/>
            0 = the clock disabled level is low, and the first edge is a rising edge.
          </comment>
        </bits>
        <bits access="rw" name="clock_delay" pos="7:6" rst="3">
          <comment>
            Transfer start to first edge delay
            <br/>
             value from 0 to 2 is the number of spi clock half period between the Transfer start and the first clock edge.
          </comment>
        </bits>
        <bits access="rw" name="do_delay" pos="9:8" rst="3">
          <comment>
            Transfer start to first data out delay
            <br/>
             value from 0 to 2 is the number of spi clock half period between the Transfer start and the first data out.
          </comment>
        </bits>
        <bits access="rw" name="di_delay" pos="11:10" rst="3">
          <comment>
            Transfer start to first data in sampled delay
            <br/>
             value from 0 to 3 is the number of spi clock half period between the Transfer start and the first data sampled in.
            <br/>
             The DI_Delay only specify the sampling time, for frame size, the counter is based on the DO_Delay even in DigRF read mode.
          </comment>
        </bits>
        <bits access="rw" name="cs_delay" pos="13:12" rst="3">
          <comment>
            Transfer start to CS activation delay
            <br/>
             value from 0 to 3 is the number of spi clock half period between the Transfer start and the CS activation edge.
          </comment>
        </bits>
        <bits access="rw" name="cs_end_hold" pos="15:14" rst="3">
          <comment>
            Transfer end to chip select deactivation delay
            <br/>
             value from 0 to 3 is the number of spi clock half period between the end of transfer (DO) and the CS deactivation edge.
            <br/>
            <Strong>Not used for Clocked_Back2Back mode</Strong>
          </comment>
        </bits>
        <bits access="rw" name="frame_size" pos="20:16" rst="31">
          <comment>
            Number of data in the frame, or number of out data in DigRF read mode.
            <br/>
            The actual frame size is the value of this register + 1; valid value are 3 to 31 (frame size 4 to 32bits)
            <br/>
            The frame size is given for the number of data, the actual number of clock pulses might be greater. First if Clock_Delay &lt; DO_Delay an extra clock pulse is generated, second in case of DigRF read or back2back, some more clock pulses will be generated.
          </comment>
          <options>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="cs_end_pulse" pos="23:22" rst="3">
          <comment>
            Chip select deactivation to new start of transfer minimum delay
            <br/>
            value from 0 to 3 is the number of spi clock half period between the CS deactivation and a new transfer start (transfer will start only if more data are available in the transmit FIFO)
            <br/>
            <Strong>Not used for Clocked_Back2Back mode</Strong>
          </comment>
        </bits>
        <bits access="rw" name="input_frame_size" pos="28:24" rst="31">
          <comment>
            Frame Size For Input in DigRF input mode
            <br/>
            The actual frame size is the value of this register + 1; valid value are 3 to 31 (frame size 4 to 32bits)
          </comment>
          <options>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
        <bits access="rw" name="turnaround_time" pos="31:30" rst="3">
          <comment>
            TurnAround time: end of write frame to start of read frame delay (in cycles)
            <br/>
            value from 0 to 3 is the number of spi clock period between the end of the output frame (without the DO_Delay) and the Input Frame start.
            <br/>
            Also used for Clocked_Back2Back mode, when Clocked_Back2Back=1 and there is more data available in the transmit FIFO:
            <br/>
            value from 0 to 3 is the number of spi clock period between the end of the frame (without the DO_Delay) and the start of the new frame.
                (It can also be seen as the number of spi clock period between the end of the last data bit and the start of the new data bit.)
          </comment>
        </bits>
      </reg>
      <reg name="status" protect="rw">
        <bits access="r" name="active_status" pos="0" rst="0">
          <comment>
            The SPI activity status
            <br/>
            1 = A transfer is in progress
            <br/>
            0 = The transfer is done
          </comment>
        </bits>
        <bits access="rc" name="error_cmd" pos="1" rst="0">
          <comment>
            Error status
            <br/>
            1 = a new command (or gain) has been requested while a command was in progress.
            <br/>
            0 = No error
            <br/>
            Write 1 to clear.
          </comment>
        </bits>
        <bits access="rc" name="table_ovf" pos="6" rst="0">
          <comment>
            The Gain Table overflow status.
            <br/>
            1 = Too many data has been written in the table
            <br/>
            Writing a 1 clear the overflow status.
          </comment>
        </bits>
        <bits access="rc" name="table_udf" pos="7" rst="0">
          <comment>
            The Gain Table underflow status.
            <br/>
             1 = a next gain request has been received while the read pointer was already at the top of the table.
            <br/>
             Writing a '1' clear the underflow status.
          </comment>
        </bits>
        <bits access="r" name="cmd_level" pos="CMD_FIFO_LEN_BITS+7:8" rst="0">
          <options>
            <mask/>
            <shift/>
          </options>
          <comment>Command FIFO level, number of command in the FIFO</comment>
        </bits>
        <bits access="rc" name="cmd_ovf" pos="14" rst="0">
          <comment>
            The command FIFO overflow status.
            <br/>
            1 = Too many data has been written in the FIFO
            <br/>
            Writing a 1 clear the overflow status.
          </comment>
        </bits>
        <bits access="rc" name="cmd_udf" pos="15" rst="0">
          <comment>
            The command FIFO underflow status.
            <br/>
            1 = Data has been requested to read while the FIFO was empty
            <br/>
            Writing a 1 clear the underflow status.
          </comment>
        </bits>
        <bits access="r" name="cmd_data_level" pos="CMD_DATA_FIFO_LEN_BITS+16:16" rst="0">
          <options>
            <mask/>
            <shift/>
          </options>
          <comment>Command FIFO level, number of bytes in the FIFO</comment>
        </bits>
        <bits access="rc" name="cmd_data_ovf" pos="22" rst="0">
          <comment>
            The command data FIFO overflow status.
            <br/>
            1 = Too many data has been written in the FIFO
            <br/>
            Writing a 1 clear the overflow status.
          </comment>
        </bits>
        <bits access="rc" name="cmd_data_udf" pos="23" rst="0">
          <comment>
            The command data FIFO underflow status.
            <br/>
            1 = Data has been requested to read while the FIFO was empty
            <br/>
            Writing a 1 clear the underflow status.
          </comment>
        </bits>
        <bits access="r" name="rx_level" pos="RX_DATA_FIFO_LEN_BITS+24:24" rst="0">
          <options>
            <mask/>
            <shift/>
          </options>
          <comment>Receive FIFO level, number of bytes in the FIFO</comment>
        </bits>
        <bits access="rc" name="rx_ovf" pos="30" rst="0">
          <comment>
            The receive FIFO overflow status.
            <br/>
            1 = Too many data has been written in the FIFO
            <br/>
            Writing a 1 clear the overflow status.
          </comment>
        </bits>
        <bits access="rc" name="rx_udf" pos="31" rst="0">
          <comment>
            The receive FIFO underflow status.
            <br/>
            1 = Data has been requested to read while the FIFO was empty
            <br/>
            Writing a 1 clear the underflow status.
          </comment>
        </bits>
      </reg>
      <reg name="rx_data" protect="">
        <bits access="rw" name="rx_data" pos="7:0" rst="no">
          <comment>
            Read in the receive FIFO
            <br/>
            Writing this register will write to Cmd_Data fifo (same as Cmd_Data register). This is because this address is used by the IFC channels to access the fifos.
          </comment>
        </bits>
      </reg>
      <reg name="command" protect="w">
        <bits access="w" name="send_cmd" pos="0" rst="0">
          <comment>Writing 1 send the next command in the Cmd FIFO (This replace the TCU next cmd signal)</comment>
        </bits>
        <bits access="w" name="flush_cmd_fifo" pos="8" rst="0">
          <comment>
            Writing 1 flush both Cmd, and cmd_data FIFO,
            <Strong>don't do it when SPI is active (transfer in progress)</Strong>
          </comment>
        </bits>
        <bits access="w" name="flush_rx_fifo" pos="16" rst="0">
          <comment>
            Writing 1 flush the receive data FIFO,
            <Strong>don't do it when SPI is active (transfer in progress)</Strong>
          </comment>
        </bits>
        <bits access="w" name="restart_gain" pos="24" rst="0">
          <comment>
            Writing 1 place the read pointer at the beginning of the gain table.
            <Strong>don't do it when SPI is active (transfer in progress)</Strong>
          </comment>
        </bits>
        <bits access="w" name="reload_gain" pos="28" rst="0">
          <comment>Writing 1 place the write pointer at the beginning of the gain table allowing to fill the table.</comment>
        </bits>
        <bits access="rw" name="drive_zero" pos="31" rst="1">
          <comment>Writing 1 change all the ouputs of the SPI interface to drive a logical '0'. This mode stops when a new command is requested to be send (by TCU) or when writting 0 to this register. This mode is useful when powering off the tranciever chip connected to the RF_SPI.</comment>
        </bits>
      </reg>
      <reg name="cmd_size" protect="w">
        <bits access="w" name="cmd_size" pos="CMD_SIZE_BITS-1:0" rst="no">
          <comment>Write the size in bytes of the next command in the FIFO</comment>
        </bits>
        <bits access="w" name="cmd_mark" pos="31" rst="no">
          <comment>
            Write 1 to mark the command.
            <br/>
            Marked commands are discarded if Enable_Rf_Spi_Marked_Cmd is low in the tcu register.
          </comment>
        </bits>
      </reg>
      <reg name="cmd_data" protect="w">
        <bits access="w" name="cmd_data" pos="7:0" rst="no">
          <comment>Write in the Command data FIFO</comment>
        </bits>
      </reg>
      <reg name="gain_size" protect="rw">
        <bits access="rw" name="gain_size" pos="GAIN_SIZE_BITS-1:0" rst="0">
          <comment>Size of a Gain command in bytes.</comment>
        </bits>
      </reg>
      <reg name="gain_data" protect="w">
        <bits access="w" name="gain_data" pos="7:0" rst="no">
          <comment>Write in the Gain Table (the pointer auto increments)</comment>
        </bits>
      </reg>
      <reg name="irq" protect="rw">
        <bits access="rc" name="cmd_data_dma_done_cause" pos="0" rst="0">
          <comment>
            Cmd_Data_DMA_Done IRQ Cause bit
            <br/>
             1 = the IRQ was triggered by the end of the DMA transfer to the cmd FIFO.
            <br/>
             To clear it write 1 in this bit or Cmd_Data_DMA_Done_Status bit.
          </comment>
        </bits>
        <bits access="r" name="cmd_fifo_empty_cause" pos="2" rst="0">
          <comment>
            Cmd_FIFO_empty IRQ Cause bit
            <br/>
             1 = the IRQ was triggered because the Cmd_FIFO is empty.
            <br/>
             To clear it, fill the FIFO.
          </comment>
        </bits>
        <bits access="r" name="cmd_threshold_cause" pos="3" rst="0">
          <comment>
            Cmd_Threshold IRQ Cause bit
            <br/>
             1 = the IRQ was triggered because the Cmd_FIFO level is below the Cmd_Threshold.
            <br/>
             To clear it, fill the FIFO.
          </comment>
        </bits>
        <bits access="r" name="rx_fifo_full_cause" pos="4" rst="0">
          <comment>
            Rx_FIFO_full IRQ Cause bit
            <br/>
             1 = the IRQ was triggered because the Rx_Data_FIFO is full.
            <br/>
             To clear it, read from the FIFO.
          </comment>
        </bits>
        <bits access="r" name="rx_threshold_cause" pos="5" rst="0">
          <comment>
            Rx_Threshold IRQ Cause bit
            <br/>
             1 = the IRQ was triggered because the Rx_Data_FIFO level is over the Rx_Threshold.
            <br/>
             To clear it, read from the FIFO.
          </comment>
        </bits>
        <bits access="r" name="error_cause" pos="6" rst="0">
          <comment>
            Error IRQ Cause bit
            <br/>
             1 = the IRQ was triggered because an error occured. Read the Status register to check the kind of error.
            <br/>
             To clear it, clear it in the Status register.
          </comment>
        </bits>
        <bitgroup name="all_cause">
          <entry ref="cmd_data_dma_done_cause"/>
          <entry ref="cmd_fifo_empty_cause"/>
          <entry ref="cmd_threshold_cause"/>
          <entry ref="rx_fifo_full_cause"/>
          <entry ref="rx_threshold_cause"/>
          <entry ref="error_cause"/>
        </bitgroup>
        <bits access="rc" name="cmd_data_dma_done_status" pos="16" rst="0">
          <comment>
            Cmd_Data_DMA_Done IRQ Status bit
            <br/>
             1 = the end of the DMA transfer to the cmd FIFO occured.
            <br/>
             To clear it write 1 in this bit or Cmd_Data_DMA_Done_Cause bit.
          </comment>
        </bits>
        <bits access="r" name="cmd_fifo_empty_status" pos="18" rst="1">
          <comment>
            Cmd_FIFO_empty IRQ Status bit
            <br/>
             1 = the Cmd_FIFO is empty.
          </comment>
        </bits>
        <bits access="r" name="cmd_threshold_status" pos="19" rst="1">
          <comment>
            Cmd_Threshold IRQ Status bit
            <br/>
             1 = the Cmd_FIFO level is bellow the Cmd_Threshold.
          </comment>
        </bits>
        <bits access="r" name="rx_fifo_full_status" pos="20" rst="0">
          <comment>
            Rx_FIFO_full IRQ Status bit
            <br/>
             1 = the Rx_Data_FIFO is full.
          </comment>
        </bits>
        <bits access="r" name="rx_threshold_status" pos="21" rst="0">
          <comment>
            Rx_Threshold IRQ Status bit
            <br/>
             1 = the Rx_Data_FIFO level is over the Rx_Threshold.
          </comment>
        </bits>
        <bits access="r" name="error_status" pos="22" rst="0">
          <comment>
            Error IRQ Status bit
            <br/>
             1 = an error occured. Read the Status register to check the kind of error.
          </comment>
        </bits>
        <bitgroup name="all_status">
          <entry ref="cmd_data_dma_done_status"/>
          <entry ref="cmd_fifo_empty_status"/>
          <entry ref="cmd_threshold_status"/>
          <entry ref="rx_fifo_full_status"/>
          <entry ref="rx_threshold_status"/>
          <entry ref="error_status"/>
        </bitgroup>
      </reg>
      <reg name="irq_mask" protect="rw">
        <bits access="rw" name="cmd_data_dma_done_mask" pos="0" rst="0">
          <comment>
            Cmd_Data_DMA_Done IRQ Mask bit
            <br/>
             1 = the Cmd_Data_DMA_Done IRQ is enabled
            <br/>
             0 = the Cmd_Data_DMA_Done IRQ is disabled
          </comment>
        </bits>
        <bits access="rw" name="cmd_fifo_empty_mask" pos="2" rst="0">
          <comment>
            Cmd_FIFO_empty IRQ Mask bit
            <br/>
             1 = the Cmd_FIFO_empty IRQ is enabled
            <br/>
             0 = the Cmd_FIFO_empty IRQ is disabled
          </comment>
        </bits>
        <bits access="rw" name="cmd_threshold_mask" pos="3" rst="0">
          <comment>
            Cmd_Threshold IRQ Mask bit
            <br/>
             1 = the Cmd_Threshold IRQ is enabled
            <br/>
             0 = the Cmd_Threshold IRQ is disabled
          </comment>
        </bits>
        <bits access="rw" name="rx_fifo_full_mask" pos="4" rst="0">
          <comment>
            Rx_FIFO_full IRQ Mask bit
            <br/>
             1 = the Rx_FIFO_full IRQ is enabled
            <br/>
             0 = the Rx_FIFO_full IRQ is disabled
          </comment>
        </bits>
        <bits access="rw" name="rx_threshold_mask" pos="5" rst="0">
          <comment>
            Rx_Threshold IRQ Mask bit
            <br/>
             1 = the Rx_Threshold IRQ is enabled
            <br/>
             0 = the Rx_Threshold IRQ is disabled
          </comment>
        </bits>
        <bits access="rw" name="error_mask" pos="6" rst="0">
          <comment>
            Error IRQ Mask bit
            <br/>
             1 = the Error IRQ is enabled
            <br/>
             0 = the Error IRQ is disabled
          </comment>
        </bits>
        <bitgroup name="all_mask">
          <entry ref="cmd_data_dma_done_mask"/>
          <entry ref="cmd_fifo_empty_mask"/>
          <entry ref="cmd_threshold_mask"/>
          <entry ref="rx_fifo_full_mask"/>
          <entry ref="rx_threshold_mask"/>
          <entry ref="error_mask"/>
        </bitgroup>
      </reg>
      <reg name="irq_threshold" protect="rw">
        <bits access="r" name="cmd_threshold" pos="CMD_FIFO_LEN_BITS+7:8" rst="all1">
          <comment>Command FIFO Threshold, number of command in the FIFO bellow which the Cmd_Threshold_IRQ is triggered.</comment>
        </bits>
        <bits access="r" name="rx_threshold" pos="RX_DATA_FIFO_LEN_BITS+23:24" rst="all1">
          <comment>Receive FIFO Threshold, number of bytes in the FIFO above which the Rx_Threshold_IRQ is triggered.</comment>
        </bits>
      </reg>
      <reg name="divider" protect="rw">
        <bits access="rw" name="divider" pos="6:1" rst="0">
          <comment>
            Clock Divider
            <br/>
            The state machine clock is generated by dividing the system clock by the value of this register + 1. So the output clock is divided by (register + 1)*2
          </comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="clock_limiter" pos="28" rst="0">
          <comment>
            When enabled the clock input to the divider is not the system clock, but a limited version of it: It cannot be above 52MHz, so the output clock will never be above 26MHz.
            <br/>
             for system clock of 104Mhz the clock input to the divider is 52Mhz, for system clock of 78Mhz the clock input to the divider is 39Mhz, for lower system clock value, the input to the divider is the system clock.
          </comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="sys_ifc.xml">
    <include file="globals.xml"/>
    <include file="gallite_generic_config.xml"/>
    <var name="SYS_IFC_ADDR_ALIGN" value="0"/>
    <var name="SYS_IFC_TC_LEN" value="23"/>
    <var name="SYS_IFC_STD_CHAN_NB" value="SYS_IFC_NB_STD_CHANNEL"/>
    <var name="SYS_IFC_RFSPI_CHAN" value="2"/>
    <module category="GGE_SYS" name="SYS_IFC">
      <reg name="get_ch" protect="">
        <bits access="r" name="ch_to_use" pos="3:0" rst="0">
          <comment>
            This field indicates which standard channel to use.
            <br/>
             Before using a channel, the CPU read this register to know which channel must be used.
      After reading this registers, the channel is to be regarded as
      busy.
            <br/>
             After reading this register, if the CPU doesn't want to use
      the specified channel, the CPU must write a disable in the control
      register of the channel to release the channel.
            <br/>
            0000 = use Channel0
            <br/>
            0001 = use Channel1
            <br/>
            0010 = use Channel2
            <br/>
             ...
            <br/>
            0111 = use Channel7
            <br/>
            1111 = all channels are busy
          </comment>
          <options>
            <mask/>
            <shift/>
            <default/>
          </options>
        </bits>
      </reg>
      <reg name="dma_status" protect="r">
        <bits access="r" name="ch_enable" pos="SYS_IFC_STD_CHAN_NB+SYS_IFC_RFSPI_CHAN-1:0" rst="0">
          <comment>
            This register indicates which channel is enabled. It is a copy
      of the enable bit of the control register of each channel. One bit per
      channel, for example:
            <br/>
            0000_0000 = All channels disabled
            <br/>
            0000_0001 = Ch0 enabled
            <br/>
            0000_0010 = Ch1 enabled
            <br/>
            0000_0100 = Ch2 enabled
            <br/>
            0000_0101 = Ch0 and Ch2 enabled
            <br/>
            0000_0111 = Ch0, Ch1 and Ch2 enabled
            <br/>
            1111_1111 = all channels enabled
          </comment>
        </bits>
        <bits access="r" name="ch_busy" pos="SYS_IFC_STD_CHAN_NB-1+16:16" rst="0">
          <comment>This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel</comment>
        </bits>
      </reg>
      <reg name="debug_status" protect="r">
        <bits access="r" name="dbg_status" pos="0" rst="1">
          <comment>
            Debug Channel Status .
            <br/>
            0= The debug channel is running
      (not idle)
            <br/>
            1= The debug channel is in idle mode
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <struct count="SYS_IFC_STD_CHAN_NB" name="std_ch">
        <reg name="control" protect="rw">
          <bits access="w" name="enable" pos="0" rst="no">
            <comment>
              Channel Enable, write one in this bit enable the channel.
              <br/>
              When the channel is enabled, for a peripheral to memory transfer
        the DMA wait request from peripheral to start transfer.
            </comment>
          </bits>
          <bits access="w" name="disable" pos="1" rst="no">
            <comment>
              Channel Disable, write one in this bit disable the channel.
              <br/>
              When writing one in this bit, the current AHB transfer and
        current APB transfer (if one in progress) is completed and the channel
        is then disabled.
            </comment>
          </bits>
          <bits access="rw" name="ch_rd_hw_exch" pos="2" rst="0">
            <comment>
              Exchange the read data from fifo halfword MSB or LSB
              <br/>
            </comment>
          </bits>
          <bits access="rw" name="ch_wr_hw_exch" pos="3" rst="0">
            <comment>
              Exchange the write data to fifo  halfword MSB or LSB
              <br/>
            </comment>
          </bits>
          <bits access="rw" name="autodisable" pos="4" rst="1">
            <comment>
              Set Auto-disable mode
              <br/>
               0 = when TC reach zero the
        channel is not automatically released.
              <br/>
               1 = At the end of the
        transfer when TC reach zero the channel is automatically disabled. the
        current channel is released.
            </comment>
          </bits>
          <bits access="rw" name="size" pos="5" rst="0">
            <comment>
              Peripheral Size
              <br/>
               0= 8-bit peripheral
              <br/>
               1= 32-bit peripheral
            </comment>
          </bits>
          <bits access="rw" display="hex" name="req_src" pos="12:8" rst="0x7">
            <options linkenum="Gge_Ifc_Request_IDs">
              <shift/>
              <mask/>
              <default/>
            </options>
            <comment>Select DMA Request source</comment>
          </bits>
          <bits access="rw" name="flush" pos="16" rst="0">
            <comment>
              When one, flush the internal FIFO channel.
              <br/>
              This bit must be used only in case of Rx transfer. Until this bit is 1, the APB
              request is masked. The flush doesn't release the channel.
              <br/>
               Before writting back this bit to zero the internal fifo must empty.
            </comment>
          </bits>
          <bits access="rw" name="max_burst_length" pos="18:17" rst="00">
            <comment>
              Set the MAX burst length for channel 0,1.
                 This bit field is only used in channel 0~1, for channel 2~6, it is reserved.
              <br/>
               The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4.
              <br/>
               .
            </comment>
          </bits>
        </reg>
        <reg name="status" protect="r">
          <bits access="r" name="enable" pos="0" rst="0">
            <comment>Enable bit, when '1' the channel is running</comment>
          </bits>
          <bits access="r" name="fifo_empty" pos="4" rst="1">
            <comment>The internal channel fifo is empty</comment>
          </bits>
        </reg>
        <reg name="start_addr" protect="rw">
          <bits access="rw" display="hex" name="start_addr" pos="NB_BITS_ADDR-1:SYS_IFC_ADDR_ALIGN" rst="0xFFFFFFF">
            <comment>
              AHB Address. This field represent the start address of the
        transfer.
              <br/>
              For a 32-bit peripheral, this address must be aligned 32-bit.
            </comment>
          </bits>
        </reg>
        <reg name="tc" protect="rw">
          <bits access="rw" display="hex" name="tc" pos="SYS_IFC_TC_LEN-1:0" rst="0xFFFFFF">
            <comment>
              Transfer Count, this field indicated the transfer size in bytes to perform.
              <br/>
              During a transfer a write in this register add the new value to the current TC.
              <br/>
              A read of this register return the current current transfer count.
            </comment>
          </bits>
        </reg>
      </struct>
      <hole size="32*4*(7-SYS_IFC_STD_CHAN_NB)"/>
      <struct count="SYS_IFC_RFSPI_CHAN" name="rfspi_ch">
        <reg name="ch_rfspi_control" protect="rw">
          <bits access="s" name="enable" pos="0" rst="no">
            <comment>
              Channel Enable, write one in this bit enable the channel.
              <br/>
              This channel works only in fifo mode.
            </comment>
          </bits>
          <bits access="c" name="disable" pos="1" rst="no">
            <comment>Channel Disable, write one in this bit to disable the channel.</comment>
          </bits>
        </reg>
        <reg name="ch_rfspi_status" protect="r">
          <bits access="r" name="enable" pos="0" rst="0">
            <comment>Enable bit, when '1' the channel is running</comment>
          </bits>
          <bits access="r" name="fifo_empty" pos="4" rst="1">
            <comment>The internal channel fifo is empty</comment>
          </bits>
          <bits access="r" name="fifo_level" pos="12:8" rst="0">
            <comment>Internal fifo level</comment>
          </bits>
        </reg>
        <reg name="ch_rfspi_start_addr" protect="rw">
          <bits access="rw" display="hex" name="start_ahb_addr" pos="NB_BITS_ADDR-1:SYS_IFC_ADDR_ALIGN" rst="0xFFFFFFF">
            <comment>
              AHB Start Address.
              <br/>
              This field represent the start address of the fifo.
                 The start address must 32-bit aligned.
            </comment>
          </bits>
        </reg>
        <reg name="ch_rfspi_end_addr" protect="rw">
          <bits access="rw" display="hex" name="end_ahb_addr" pos="NB_BITS_ADDR-1:SYS_IFC_ADDR_ALIGN" rst="0xFFFFFFF">
            <comment>
              AHB End Address.
              <br/>
              This field represent the last address of the fifo (it is the first address not used in the fifo).
              <br/>
              The end address must 32-bit aligned.
            </comment>
          </bits>
        </reg>
        <reg name="ch_rfspi_tc" protect="rw">
          <bits access="rw" display="hex" name="tc" pos="13:0" rst="0x0">
            <comment>
              Transfer Count, transfer size in bytes.
              <br/>
              This bit
        indicated the transfer size in bytes to perform. Up to 16kbytes per
        transfer.
              <br/>
              During a transfer a write in this register add the new
        value to the current TC. A read of this register return the current
        current transfer count.
            </comment>
          </bits>
        </reg>
      </struct>
    </module>
  </archive>
  <archive relative="gge_sys_ctrl.xml">
    <module category="GGE_SYS" name="GGE_SYS_CTRL">
      <reg name="sys_ctrl" protect="rw">
        <bits access="rw" name="sel_clk_tcu_gsm" pos="0" rst="0x1">
          <comment>
            0: sel 26MHz clock.
            <br/>
            1: sel 32KHz clock.
          </comment>
        </bits>
        <bits access="rw" name="sel_clk_tcu_nb" pos="1" rst="0x1">
          <comment>
            0: sel 61.44MHz clock.
            <br/>
            1: sel 32KHz clock.
          </comment>
        </bits>
        <bits access="rw" name="snap_config_gsm" pos="2" rst="0x0">
          <comment>Number of snapshot.</comment>
        </bits>
        <bits access="rw" name="snap_config_nb" pos="3" rst="0x0">
          <comment>Number of snapshot.</comment>
        </bits>
        <bits access="r" name="snapshot_gsm" pos="29:28" rst="0x0">
          <comment>Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg.</comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="snapshot_nb" pos="31:30" rst="0x0">
          <comment>Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg.</comment>
          <options>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <reg name="soft_rst_gge" protect="rw">
        <comment>
          0: low active, assert reset.
          <br/>
          1: high inactive, deassert reset.
        </comment>
        <bits access="rw" name="soft_rst_bcpu" pos="0" rst="0">
    </bits>
        <bits access="rw" name="soft_rst_bb_rom" pos="1" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_bb_ram" pos="2" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_bb_irq" pos="3" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_a53" pos="4" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_cipher" pos="5" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_cp2" pos="6" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_xcor" pos="7" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_excor" pos="8" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_vitac" pos="9" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_evitac" pos="10" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_itlv" pos="11" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_cholk" pos="12" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_cordic" pos="13" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_rf_if" pos="14" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_rf_spi_gsm" pos="15" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_sys_wdt" pos="16" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_tcu_gsm" pos="17" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_nbiot" pos="18" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_sys_ifc" pos="19" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_rf_spi_nb" pos="20" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_tcu_nb" pos="21" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_bb_dma" pos="22" rst="1">
    </bits>
        <bits access="rw" name="soft_rst_global" pos="31" rst="1">
    </bits>
      </reg>
      <reg name="ip_clk_disable_gge" protect="rw">
        <comment>
          0: not disable ip_* clock.
          <br/>
          1: disable ip_* clock.
        </comment>
        <bits access="rw" name="clk_dis_bcpu" pos="0" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_bb_rom" pos="1" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_bb_ram" pos="2" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_a53" pos="4" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_cp2" pos="6" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_xcor" pos="7" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_excor" pos="8" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_vitac" pos="9" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_evitac" pos="10" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_itlv" pos="11" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_cholk" pos="12" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_rf_if" pos="14" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_nbiot" pos="18" rst="0">
    </bits>
        <bits access="rw" name="clk_dis_sys_ifc" pos="19" rst="0">
    </bits>
      </reg>
      <reg name="dbg_disable_acg_hclk" protect="rw">
        <comment>
          0: enable hclk_* auto clock gating.
          <br/>
          1: disable hclk_* auto clock gating.
        </comment>
        <bits access="rw" name="dis_acg_hclk_matrix" pos="0" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_bcpu" pos="1" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_bcpu_int" pos="2" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_bb_rom" pos="3" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_bb_ram" pos="4" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_always" pos="5" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_bb_decoder" pos="6" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_rf_if" pos="7" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_a53" pos="8" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_cp2" pos="9" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_cp2_reg" pos="10" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_xcor" pos="11" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_excor" pos="12" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_vitac" pos="13" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_evitac" pos="14" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_itlv" pos="15" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_cholk" pos="16" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_nbiot" pos="17" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_sys_ifc" pos="18" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_sys_ifc_ch0" pos="19" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_sys_ifc_ch1" pos="20" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_sys_ifc_ch2" pos="21" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_sys_ifc_ch3" pos="22" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_hclk_bb_dma" pos="23" rst="0">
    </bits>
      </reg>
      <reg name="dbg_disable_acg_pclk" protect="rw">
        <comment>
          0: enable pclk_* auto clock gating.
          <br/>
          1: disable pclk_* auto clock gating.
        </comment>
        <bits access="rw" name="dis_acg_pclk_bcpu" pos="0" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_bb_rom" pos="1" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_always" pos="2" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_rf_if" pos="3" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_mod_rf_if" pos="4" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_always_rf_if" pos="5" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_bb_irq" pos="6" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_mod_bb_irq" pos="7" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_cipher" pos="8" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_mod_cipher" pos="9" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_cp2" pos="10" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_xcor" pos="11" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_excor" pos="12" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_always_excor" pos="13" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_vitac" pos="14" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_evitac" pos="15" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_always_evitac" pos="16" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_itlv" pos="17" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_cholk" pos="18" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_always_cholk" pos="19" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_cordic" pos="20" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_tcu_gsm" pos="21" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_mod_tcu_gsm" pos="22" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_always_tcu_gsm" pos="23" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_rf_spi_gsm" pos="24" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_always_rf_spi_gsm" pos="25" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_rf_spi_per_gsm" pos="26" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_always_sys_wdt" pos="27" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_nbiot" pos="28" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_sys_ifc" pos="29" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_tcu_nb" pos="30" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_mod_tcu_nb" pos="31" rst="0">
    </bits>
      </reg>
      <reg name="dbg_disable_acg_clk" protect="rw">
        <comment>
          0: enable pclk_* and clk_* auto clock gating.
          <br/>
          1: disable pclk_* and clk_* auto clock gating.
        </comment>
        <bits access="rw" name="dis_acg_pclk_always_tcu_nb" pos="0" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_rf_spi_nb" pos="1" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_always_rf_spi_nb" pos="2" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_rf_spi_per_nb" pos="3" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_pclk_bb_dma" pos="4" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_clk_rf_tx" pos="16" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_clk_rf_rx" pos="17" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_clk_phy_rf_if" pos="18" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_clk_sys_timer" pos="19" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_clk_nbiot" pos="20" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_clk_tcu_gsm" pos="21" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_clk_sys_wdt" pos="22" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_clk_osc" pos="23" rst="0">
    </bits>
        <bits access="rw" name="dis_acg_clk_tcu_nb" pos="24" rst="0">
    </bits>
      </reg>
      <reg name="cfg_ram" protect="rw">
        <bits access="rw" name="cfg_ram" pos="31:0" rst="0x00020202">
          <comment>cfg ram.</comment>
        </bits>
      </reg>
      <reg name="debug_sel" protect="rw">
        <bits access="rw" name="dbgmux_sel" pos="3:0" rst="0x0">
          <comment>
            select debug signal.
            <br/>
            0: nbiot_dbgout
            <br/>
            1: irq_dbg0 = {int_cholk, int_xcor, int_vitac, int_itlv, int_excor, int_evitac, rf_if_tx_irq, rf_if_rx_irq, rf_if_dbg_nb_irq,rf_if_dbg_2g_irq, 2'b0, int_a53,  gsm_fint_h_bb, gsm_tcu_bcpu_irq_h};
            <br/>
            2: irq_dbg1 = {5'h0, irq_aif_apb_h, nb_acc_int_dsp, nb_tx_int_dsp, nb_rx_int_dsp, nb_tcu_sync_irq_h, irq_mailbox_gge_h, nb_rf_spi_irq, gsm_rf_spi_irq};
            <br/>
            3: irq_dbg2 = {int_cholk, int_xcor, int_vitac, int_itlv, int_excor, int_evitac, rf_if_tx_irq, rf_if_rx_irq, rf_if_dbg_nb_irq,rf_if_dbg_2g_irq, 2'b0, int_a53,  nb_fint_h_bb, nb_tcu_bcpu_irq_h};
            <br/>
            4: tcu_dbg0 = {gsm_tcu_lps_fint, gsm_lps_tcu_fint_masked, gsm_lps_tcu_stop_counters, gsm_lp_pu_ready, gsm_lp_pu_done, tcu_nb_fint, gsm_fint_h_sys, gsm_fint_h_bb, gsm_toggle_fint_x, gsm_toggle_fint_b,
            <br/>
                           gsm_snap_config, gsm_send_spi_cmd_h, nb_o_tcu_trig, gsm_enable_rf_spi_marked_cmd_h};
            <br/>
            5: tcu_dbg1 = {5'h0, gsm_send_spi_cmd_h, gsm_next_gain_h, gsm_first_gain_h, rx_soc_h, digrf_strobe_h, gsm_tcu_bcpu_irq_h, gsm_tcu_xcpu_irq_h, 1'b0, nb_tcu_sync_irq_h};
            <br/>
            6: tcu_dbg2 = {4'h0, gsm_tco};
            <br/>
            7: tcu_dbg3 = {nb_tcu_lps_fint, nb_lps_tcu_fint_masked, nb_lps_tcu_stop_counters, nb_lp_pu_ready, nb_lp_pu_done, tcu_nb_fint, nb_fint_h_sys, nb_fint_h_bb, nb_toggle_fint_x, nb_toggle_fint_b,
            <br/>
                          nb_snap_config, nb_send_spi_cmd_h, nb_o_tcu_trig, nb_enable_rf_spi_marked_cmd_h};
            <br/>
            8: tcu_dbg4 = {5'h0, nb_send_spi_cmd_h, nb_next_gain_h, nb_first_gain_h, rx_soc_h, digrf_strobe_h, nb_tcu_bcpu_irq_h, nb_tcu_xcpu_irq_h, 1'b0, nb_tcu_sync_irq_h};
            <br/>
            9: tcu_dbg5 = {4'h0, nb_tco};
            <br/>
            deault: 16'hDABC;
          </comment>
        </bits>
        <bits access="rw" name="dump_ctrl" pos="5:4" rst="0x0">
          <comment>
            select rfif dump signal.
            <br/>
            0: dfe_dump_data
            <br/>
            1: dfe_rx_data
            <br/>
            2: dfe_tx_data
            <br/>
            deault: dfe_dump_data
          </comment>
        </bits>
      </reg>
      <reg name="bcpu_ctrl" protect="rw">
        <bits access="ro" name="bcpu_cache_disable_reg" pos="1" rst="0x0">
          <comment>when bcpu is sleep, can disable bcpu cache mem.</comment>
        </bits>
        <bits access="ro" name="autodisable_cache_h" pos="0" rst="0x0">
          <comment>when bcpu not use cache, can disable bcpu cache mem.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="tcu.xml">
    <module category="GGE_SYS" name="TCU">
      <var name="NB_TCO" value="12"/>
      <var name="NB_TCU_PROG_EVENTS" value="60"/>
      <enum name="Internal_TCO_mapping">
        <entry name="TCO_GMSK_ON" value="6">
          <comment>Internal TCO mapping</comment>
        </entry>
        <entry name="TCO_TX_OEN"/>
        <entry name="TCO_TX_ON"/>
        <entry name="TCO_RX_ON"/>
        <entry name="TCO_RX_DEC_ON"/>
        <entry name="TCO_PDN"/>
      </enum>
      <enum name="TCU_Event">
        <entry name="Clr_TCO_0" value="0">
          <comment>
            Clear TCO 0 : set the TCO 0 to the inactive state
            <br/>
            To clear TCO n, use event 2*n
          </comment>
        </entry>
        <entry name="Set_TCO_0" value="1">
          <comment>
            Set TCO 0 : set the TCO 0 to the active state
            <br/>
            To set TCO n, use event 2*n+1
          </comment>
        </entry>
        <entry name="Clr_TCO_1">
          <comment>...</comment>
        </entry>
        <entry name="Set_TCO_1"/>
        <entry name="Clr_TCO_2"/>
        <entry name="Set_TCO_2"/>
        <entry name="Clr_TCO_3"/>
        <entry name="Set_TCO_3"/>
        <entry name="Clr_TCO_4"/>
        <entry name="Set_TCO_4"/>
        <entry name="Clr_TCO_5"/>
        <entry name="Set_TCO_5"/>
        <entry name="Stop_GMSK" value="TCO_GMSK_ON*2">
          <comment>stop modulation</comment>
        </entry>
        <entry name="Start_GMSK" value="TCO_GMSK_ON*2+1">
          <comment>starts modulation and output on IQ DAC</comment>
        </entry>
        <entry name="HighZ_IQ_DAC" value="TCO_TX_OEN*2"/>
        <entry name="Drive_IQ_DAC" value="TCO_TX_OEN*2+1"/>
        <entry name="disable_IQ_DAC" value="TCO_TX_ON*2"/>
        <entry name="enable_IQ_DAC" value="TCO_TX_ON*2+1"/>
        <entry name="disable_IQ_ADC" value="TCO_RX_ON*2">
          <comment>disable IQ ADC</comment>
        </entry>
        <entry name="enable_IQ_ADC" value="TCO_RX_ON*2+1">
          <comment>enable IQ ADC</comment>
        </entry>
        <entry name="stop_RFin_record" value="TCO_RX_DEC_ON*2">
          <comment>stop recording IQ samples</comment>
        </entry>
        <entry name="start_RFin_record" value="TCO_RX_DEC_ON*2+1">
          <comment>start recording IQ samples</comment>
        </entry>
        <entry name="Clr_PDN" value="TCO_PDN*2">
          <comment>Clear RF_PDN</comment>
        </entry>
        <entry name="Set_PDN" value="TCO_PDN*2+1">
          <comment>Set RF_PDN</comment>
        </entry>
        <entry name="SEND_SPI_CMD" value="NB_TCO*2">
          <comment>Send RF spi command</comment>
        </entry>
        <entry name="NEXT_GAIN"/>
        <entry name="FIRST_GAIN"/>
        <entry name="NEXT_FC"/>
        <entry name="PA_RAMP0">
          <comment>Start Ramp 0</comment>
        </entry>
        <entry name="PA_RAMP1">
          <comment>Start Ramp 1</comment>
        </entry>
        <entry name="PA_RAMP2">
          <comment>Start Ramp 2</comment>
        </entry>
        <entry name="PA_RAMP3">
          <comment>Start Ramp 3</comment>
        </entry>
        <entry name="PA_RAMP4">
          <comment>Start Ramp 4</comment>
        </entry>
        <entry name="RX_SOC"/>
        <entry name="DIGRF_STB"/>
        <entry name="BCPU_TCU_IRQ0">
          <comment>Trigger BCPU TCU irq 0</comment>
        </entry>
        <entry name="BCPU_TCU_IRQ1">
          <comment>Trigger BCPU TCU irq 1</comment>
        </entry>
        <entry name="XCPU_TCU_IRQ0">
          <comment>Trigger XCPU TCU irq 0</comment>
        </entry>
        <entry name="XCPU_TCU_IRQ1">
          <comment>Trigger XCPU TCU irq 1</comment>
        </entry>
        <entry name="WAKEUP_DONE">
          <comment>End of the WakeUp Mode</comment>
        </entry>
        <entry name="RFSPI_START">
          <comment>Start of Rf_spi Transfer</comment>
        </entry>
        <entry name="RFSPI_END">
          <comment>End of Rf_spi Transfer</comment>
        </entry>
        <entry name="NO_EVENT" value="63"/>
      </enum>
      <reg name="ctrl" protect="rw">
        <bits access="rw" display="hex" name="load_val" pos="13:0" rst="all1">
          <comment>Value loaded into the TCU counter when the Load bit is set to 1</comment>
        </bits>
        <bits access="rw" name="enable" pos="16" rst="0">
          <options>
            <option name="Disabled" value="0"/>
            <option name="Enabled" value="1"/>
          </options>
        </bits>
        <bits access="w" name="load" pos="20" rst="0">
          <comment>
            Writing a 1 to this bit will load the TCU with the TCU loadval value
            <br/>
            Writing a 0 has no effect
          </comment>
        </bits>
        <bits access="rw" name="nolatch" pos="28" rst="0">
          <options>
            <option name="Normal" value="0">
              <comment>Normal Behavior, The programmation area is copied to the active area when the tcu wraps</comment>
            </option>
            <option name="Force_Only" value="1">
              <comment>The programmation area is copied into the active area only when force latch is used</comment>
            </option>
          </options>
        </bits>
        <bits access="rw" name="wakeup_en" pos="30" rst="0">
          <comment>
            Writing a 1 to enable run tcu wakeup function in lowpower skip frame
            <br/>
            Writing a 0 to disable
          </comment>
        </bits>
      </reg>
      <reg name="wrap_val" protect="rw">
        <bits access="rw" display="hex" name="wrap_val" pos="13:0" rst="all1">
          <comment>
            TCU counter wrap value.
            <br/>
            The TCU counter returns to 0 when this value is reached
          </comment>
        </bits>
      </reg>
      <reg name="cur_val" protect="rw">
        <bits access="r" display="hex" name="cur_val" pos="13:0" rst="0">
          <comment>TCU counter current value</comment>
        </bits>
      </reg>
      <reg name="latch" protect="rw">
        <bits access="w" cut="1" cutprefix="ForceLatch_Area" name="forcelatch" pos="7:0" rst="0">
          <comment>Writing 1 transfer the programmed events to the active area.</comment>
        </bits>
        <bits access="w" name="force_noevent" pos="16" rst="0">
          <comment>Writing 1 to this bit with one of the ForceLatch bit will force the corresponding Active Area to receive no events (i.e. clear it) instead of transfering the programmed area.</comment>
        </bits>
        <bits access="w" name="clearprogarea" pos="31" rst="0">
          <comment>Writing 1 clears the Program Area</comment>
        </bits>
      </reg>
      <reg name="setup" protect="rw">
        <bits access="rw" cut="1" cutprefix="POL_TCO" name="tco_polarity" pos="NB_TCO-1:0" rst="0">
          <comment>Configure the TCO polarity</comment>
          <options>
            <option name="Active High" value="0"/>
            <option name="Active Low" value="1"/>
          </options>
        </bits>
        <bits access="rc" name="write_error" pos="28" rst="0">
          <comment>
            Error Status: become 1 when writing to Program Area while the TCU is coping the Program Area to the Active Area. In this case the write is ignored.
            <br/>
            Write 1 to clear it.
          </comment>
        </bits>
        <bits access="rw" name="debug_active" pos="31" rst="0">
          <comment>This bit allows to access directly the active area for debug purposes</comment>
          <options>
            <option name="Normal" value="0"/>
            <option name="Debug" value="1">
              <comment>the active area is directly mapped instead of the program area.</comment>
            </option>
          </options>
        </bits>
      </reg>
      <reg name="disable_event" protect="rw">
        <bits access="rw" cut="1" cutprefix="Disable_TCO" name="disable_tco" pos="5:0" rst="all1">
          <comment>
            Writing 1 disable the events that affect corresponding TCO.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" cut="1" cutenum="Internal_TCO_mapping" cutprefix="Disable" name="disable_internal_tco" pos="11:6" rst="all1">
          <comment>
            Writing 1 disable the events that affect corresponding TCO.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="disable_send_spi_cmd" pos="12" rst="1">
          <comment>
            Writing 1 disable the events SEND_SPI_CMD.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="disable_next_gain" pos="13" rst="1">
          <comment>
            Writing 1 disable the events NEXT_GAIN.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="disable_first_gain" pos="14" rst="1">
          <comment>
            Writing 1 disable the events FIRST_GAIN.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="disable_next_fc" pos="15" rst="1">
          <comment>
            Writing 1 disable the events NEXT_FC.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" cut="1" cutprefix="Disable_Ramp" name="disable_ramp" pos="20:16" rst="all1">
          <comment>
            Writing 1 disable the corresponding Ramp event.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="disable_rx_soc" pos="21" rst="1">
          <comment>
            Writing 1 disable the events RX_SOC.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="disable_digrf_strobe" pos="22" rst="1">
          <comment>
            Writing 1 disable the events DIGRF_STB.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" cut="1" cutprefix="Disable_Bcpu_Irq" name="disable_bcpu_irq" pos="24:23" rst="all1">
          <comment>
            Writing 1 disable the corresponding BCPU TCU irq event.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" cut="1" cutprefix="Disable_Xcpu_Irq" name="disable_xcpu_irq" pos="26:25" rst="all1">
          <comment>
            Writing 1 disable the corresponding XCPU TCU irq event.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="disable_rfspi_start" pos="28" rst="1">
          <comment>
            Writing 1 disable the events RFSPI_START.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="disable_rfspi_end" pos="29" rst="1">
          <comment>
            Writing 1 disable the events RFSPI_END.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="disable_rf_spi_marked_cmd" pos="31" rst="1">
          <comment>
            Writing 1 disable the marked rf spi commands (cf RF SPI).
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
      </reg>
      <reg name="enable_event" protect="rw">
        <bits access="rs" cut="1" cutprefix="Enable_TCO" name="enable_tco" pos="5:0" rst="all1">
          <comment>
            Writing 1 enable the events that affect corresponding TCO.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" cut="1" cutenum="Internal_TCO_mapping" cutprefix="Enable" name="enable_internal_tco" pos="11:6" rst="all1">
          <comment>
            Writing 1 enable the events that affect corresponding TCO.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" name="enable_send_spi_cmd" pos="12" rst="1">
          <comment>
            Writing 1 enable the events SEND_SPI_CMD.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" name="enable_next_gain" pos="13" rst="1">
          <comment>
            Writing 1 enable the events NEXT_GAIN.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" name="enable_first_gain" pos="14" rst="1">
          <comment>
            Writing 1 enable the events FIRST_GAIN.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" name="enable_next_fc" pos="15" rst="1">
          <comment>
            Writing 1 enable the events NEXT_FC.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" cut="1" cutprefix="Enable_Ramp" name="enable_ramp" pos="20:16" rst="all1">
          <comment>
            Writing 1 enable the corresponding Ramp event.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" name="enable_rx_soc" pos="21" rst="1">
          <comment>
            Writing 1 enable the events RX_SOC.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" name="enable_digrf_strobe" pos="22" rst="1">
          <comment>
            Writing 1 enable the events DIGRF_STB.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" cut="1" cutprefix="Enable_Bcpu_Irq" name="enable_bcpu_irq" pos="24:23" rst="all1">
          <comment>
            Writing 1 enable the corresponding BCPU TCU irq event.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" cut="1" cutprefix="Enable_Xcpu_Irq" name="enable_xcpu_irq" pos="26:25" rst="all1">
          <comment>
            Writing 1 enable the corresponding XCPU TCU irq event.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="enable_rfspi_start" pos="28" rst="1">
          <comment>
            Writing 1 enable the events RFSPI_START.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rw" name="enable_rfspi_end" pos="29" rst="1">
          <comment>
            Writing 1 enable the events RFSPI_END.
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
        <bits access="rs" name="enable_rf_spi_marked_cmd" pos="31" rst="1">
          <comment>
            Writing 1 enable the marked rf spi commands (cf RF SPI).
            <br/>
            Reading return the actual enable state.
          </comment>
        </bits>
      </reg>
      <reg name="set_tco" protect="rw">
        <bits access="s" cut="1" cutprefix="Set_TCO" name="set_tco" pos="NB_TCO-1:0" rst="0">
          <comment>
            Writing 1 set corresponding TCO to the active state (The actual line state also depends on TCO_Polarity).
            <br/>
            Reading returns the actual state of all TCOs.
          </comment>
        </bits>
      </reg>
      <reg name="clr_tco" protect="rw">
        <bits access="c" cut="1" cutprefix="Clr_TCO" name="clr_tco" pos="NB_TCO-1:0" rst="0">
          <comment>
            Writing 1 set corresponding TCO to the inactive state (The actual line state also depends on TCO_Polarity).
            <br/>
            Reading returns the actual state of all TCOs.
          </comment>
        </bits>
      </reg>
      <reg name="cfg_clk_div" protect="rw">
        <bits access="rw" name="tcu_clk_same_sys" pos="29" rst="0">
          <comment>Enable Clk_TCU same with Clk_Sys.</comment>
          <options>
            <option name="Disabled" value="0"/>
            <option name="Enabled" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="enable_dai_simple_208k" pos="30" rst="0">
          <comment>Enable the 208kHz pulse generation for DAI Simple. (!) When enabling the clock field Enable_Qbit should also be enabled.</comment>
          <options>
            <option name="Disabled" value="0"/>
            <option name="Enabled" value="1"/>
          </options>
        </bits>
        <bits access="rw" name="enable_qbit" pos="31" rst="0">
          <comment>Enable the Quarter bit generation (required for normal TCU operation)</comment>
          <options>
            <option name="Disabled" value="0"/>
            <option name="Enabled" value="1"/>
          </options>
        </bits>
      </reg>
      <reg name="tcu_irq" protect="rw">
        <bits access="rc" name="tcu_sync_done_cause" pos="0" rst="0">
          <comment>
            1 when the IRQ was triggered because the tcu counter synchronization is done.
            <br/>
            Write 1 in cause or status bit to clear.
          </comment>
        </bits>
        <bitgroup name="tcu_irq_cause">
          <entry ref="tcu_sync_done_cause"/>
        </bitgroup>
        <bits access="rc" name="tcu_sync_done_status" pos="16" rst="0">
          <comment>
            1 when the tcu counter synchronization is done.
            <br/>
            Write 1 in cause or status bit to clear.
          </comment>
        </bits>
        <bitgroup name="tcu_irq_status">
          <entry ref="tcu_sync_done_status"/>
        </bitgroup>
      </reg>
      <reg name="tcu_irq_mask" protect="rw">
        <bits access="rw" name="tcu_sync_done_mask" pos="0" rst="0">
          <comment>when 1 the LPS_IRQ_TCU_Sync_Done is enabled.</comment>
        </bits>
        <bitgroup name="tcu_irq_mask">
          <entry ref="tcu_sync_done_mask"/>
        </bitgroup>
      </reg>
      <reg name="global_sync_ctrl" protect="rw">
        <bits access="rw" name="tcu_sync_enable" pos="0" rst="0">
          <comment>enable sync tcu counter to global counter function.</comment>
        </bits>
        <bits access="rw" name="tcu_sync_value" pos="15:2" rst="0">
          <comment>tcu counter load value when synchronized.</comment>
        </bits>
      </reg>
      <reg name="tco_dbg_sel" protect="rw">
        <bits access="rw" name="tco_dbg0_sel" pos="3:0" rst="0">
        </bits>
        <bits access="rw" name="tco_dbg1_sel" pos="7:4" rst="0">
        </bits>
      </reg>
      <reg name="rfspi_conflict_val" protect="rw">
        <bits access="r" display="hex" name="rfspi_conflict_val" pos="13:0" rst="0">
          <comment>TCU counter value when rfspi conflict happen</comment>
        </bits>
      </reg>
      <hole size="1568"/>
      <reg count="NB_TCU_PROG_EVENTS" name="event" protect="rw">
        <bits access="rw" name="event_time" pos="13:0" rst="all1">
          <comment>The event Id will be executed when the TCU counter reaches the value programmed in Event time field of this register.</comment>
        </bits>
        <bits access="rw" name="event_id" pos="21:16" rst="all1">
          <comment>
            Event to be executed when the TCU counter reaches the programmed event time.
            <br/>
          </comment>
          <options linkenum="TCU_Event">
            <default/>
          </options>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="vitac.xml">
    <include file="globals.xml"/>
    <module category="GGE_SYS" name="VITAC">
      <reg name="command" protect="rw">
        <bits access="rw" name="start_equ" pos="0" rst="0x0">
          <comment>Writing a '1' in this register triggers a Viterbi Equalization
      process. Ignored if any Viterbi process is already ongoing. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="start_dec" pos="1" rst="0x0">
          <comment>Writing a '1' in this register triggers a Viterbi Decoding
      process. Ignored if any Viterbi process is already ongoing. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="start_tb" pos="2" rst="0x0">
          <comment>Writing a '1' in this register triggers the TraceBack process.
      Ignored if any Viterbi process is already ongoing. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="int_mask" pos="3" rst="0x0">
          <comment>When this bit is set, it enables the generation of the
      VITAC_DONE_H interrupt.</comment>
        </bits>
        <bits access="rw" name="punctured" pos="4" rst="0x0">
          <comment>Indicates whether a puncturing scheme has to be used during
      decoding. If this bit is set to '0', the code is assumed unpunctured and
      no puncturing matrix is needed.</comment>
        </bits>
        <bits access="rw" name="nb_states" pos="6:5" rst="0x0">
          <comment>
            This field sets the number of states of the Trellis:
            <br/>
            &quot;00&quot;: 16 states
            <br/>
            &quot;01&quot;: 32 states
            <br/>
            &quot;10&quot;: 64 states
            <br/>
            &quot;11&quot;: reserved
          </comment>
        </bits>
        <bits access="rw" name="bkwd_trellis" pos="7" rst="0x0">
          <comment>When this bit is set, the channel symbols are treated in the
      reverse order, i.e. CH_SYMB_ADDR represents the end of the buffer and
      the symbols are read out backward.</comment>
        </bits>
        <bits access="rw" name="code_rate" pos="10:8" rst="0x0">
          <comment>
            This field sets the convolutional code rate for decoding:
            <br/>
            &quot;010&quot;: 1/2 rate
            <br/>
            &quot;011&quot;: 1/3 rate
            <br/>
            &quot;100&quot;: 1/4 rate
            <br/>
            &quot;101&quot;: 1/5 rate
            <br/>
            &quot;110&quot;: 1/6 rate
            <br/>
            others: reserved
          </comment>
        </bits>
        <bits access="rw" name="bm_shift_lev" pos="14:11" rst="0x0">
          <comment>
            This field sets the amount of shift right applied at the output
      of the equalizer BM calculation:
            <br/>
            &quot;0000&quot;: BM = OUT[30:19]
            <br/>
            &quot;0001&quot;: BM = OUT[29:18]
            <br/>
            ...
            <br/>
            &quot;1111&quot;: BM = OUT[15:4]
          </comment>
        </bits>
        <bits access="rw" name="sv_shift_lev" pos="18:15" rst="0x0">
          <comment>
            This field sets the amount of shift right applied to the
      difference of the two metrics arriving at a node to create a Softvalue:
            <br/>
            &quot;0000&quot;: SoftVal = DELTA[15:9]
            <br/>
            &quot;0001&quot;: SoftVal =
      DELTA[14:8]
            <br/>
            ...
            <br/>
            &quot;1101&quot;: SoftVal = DELTA[2:0]&amp;&quot;0000&quot;
            <br/>
            others:
      reserved
          </comment>
        </bits>
        <bits access="rw" name="nb_symbols" pos="28:20" rst="0x0">
          <comment>Number of symbols to be Equalized / Decoded. Auto decrement.</comment>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="equ_pending" pos="0" rst="0x0">
          <comment>This bit is high when an equalization process is ongoing. It
      stays high when the module is stalled during operation.</comment>
        </bits>
        <bits access="r" name="dec pending" pos="1" rst="0x0">
          <comment>This bit is high when an decoding process is ongoing. It stays
      high when the module is stalled during operation.</comment>
        </bits>
        <bits access="r" name="tb_pending" pos="2" rst="0x0">
          <comment>This bit is high when an traceback process is ongoing. It stays
      high when the module is stalled during operation.</comment>
        </bits>
        <bits access="r" name="nb_rescales" pos="7:4" rst="0x0">
          <comment>
            After a Viterbi process, this field reports the number of
      rescaling operations that have been performed along the trellis.
            <br/>
            This field is reset at every new Viterbi process.
          </comment>
        </bits>
      </reg>
      <reg name="ch_symb_addr" protect="rw">
        <bits access="rw" name="addr" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
          <comment>
            This is the start address of the channel symbols buffer in
      SRAM. For Equalization channel symbols are the sampled RF samples
      (2x12-bits packed complex values), and for Decoding channel symbols are
      a frame of softvalues (4x8-bits packed).
            <br/>
            This address must be
      4-bytes aligned, bits[1:0] will be ignored.
          </comment>
        </bits>
      </reg>
      <reg name="exp_symb_addr" protect="rw">
        <bits access="rw" name="addr" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
          <comment>
            For Equalization, this is the base address of the partial sum
      terms buffer in SRAM. (2x12-bits packed complex values)
            <br/>
            For
      Decoding, this is the base address of the puncturing matrix.
            <br/>
            This
      address must be 4-bytes aligned, bits[1:0] will be ignored.
          </comment>
        </bits>
      </reg>
      <reg name="pm_base_addr" protect="rw">
        <bits access="rw" name="addr" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
          <comment>
            This is the base address in SRAM of the Path Metrics buffer.
      The VITAC will read and update PMs according to the scheme given in
      1.2.1.2. (2x16-bits packed values).
            <br/>
            This address must be 4-bytes
      aligned, bits[1:0] will be ignored.
          </comment>
        </bits>
      </reg>
      <reg name="out_base_addr" protect="rw">
        <bits access="rw" name="addr" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
          <comment>
            This is the start address of the output buffer in SRAM. When in
      Equalizer mode, the VITAC will output the calculated Softvalues
      according to the scheme given in 1.2.1.7. When in Decoder mode, the
      VITAC will output the trace words according to the scheme given in
      1.2.2.4.
            <br/>
            This address must be 4-bytes aligned, bits[1:0] will be
      ignored.
          </comment>
        </bits>
      </reg>
      <reg name="h0_param" protect="rw">
        <bits access="rw" name="h0_i_part" pos="BB_SYMBOL_SIZE-1:0" rst="0x0">
          <comment>Real part of the h0 parameter of the estimated channel
      response.</comment>
        </bits>
        <bits access="rw" name="h0_q_part" pos="BB_SYMBOL_SIZE+15:16" rst="0x0">
          <comment>Imaginary part of the h0 parameter of the estimated channel
      response.</comment>
        </bits>
      </reg>
      <reg name="hl_param" protect="rw">
        <bits access="rw" name="hl_i_part" pos="BB_SYMBOL_SIZE-1:0" rst="0x0">
          <comment>Real part of the hL parameter of the estimated channel
      response.</comment>
        </bits>
        <bits access="rw" name="hl_q_part" pos="BB_SYMBOL_SIZE+15:16" rst="0x0">
          <comment>Imaginary part of the hL parameter of the estimated channel
      response.</comment>
        </bits>
      </reg>
      <reg name="rescale" protect="rw">
        <bits access="rw" name="threshold" pos="15:0" rst="0x0">
          <comment>This field indicates the threshold value to be reach by every
      PMs for triggering a rescale operation. The rescale operation consist in
      subtracting the threshold value to every PMs to avoid overflow during PM
      update.</comment>
        </bits>
      </reg>
      <reg count="3" name="res_poly" protect="rw">
        <comment>This register bank stores the less significant bit of the output
    from the coder for a particular code (see 1.2.2.1). The kth butterfly uses
    the bit k of this register.</comment>
        <bits access="rw" name="res_poly" pos="31:0" rst="0x0">
          <comment>This register stores the less significant bit of the output
      from the coder for a particular code (see 1.2.2.1). The kth butterfly
      uses the bit k of this register.</comment>
        </bits>
      </reg>
      <reg name="int_status" protect="r">
        <bits access="r" name="it_cause" pos="0" rst="0x0">
          <comment>
            This bit is set when the VITAC module finishes an ongoing
      operation. It can be masked by setting VITAC_CMD(IT_MASK) to '1'.
            <br/>
            Resetting this bit is done by writing in IT_CLEAR register.
            <br/>
            IT_CAUSE is the image of the VITAC_DONE_H interrupt line to the
      CPU.
          </comment>
        </bits>
        <bits access="r" name="it_status" pos="16" rst="0x0">
          <comment>This bit is the unmasked version of the IT_CAUSE bit.</comment>
        </bits>
      </reg>
      <reg name="int_clear" protect="w">
        <bits access="w" name="it_clear" pos="0" rst="0x0">
          <comment>Setting this bit to '1' resets the VITAC interrupt.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wdt.xml">
    <module category="GGE_SYS" name="WDT">
      <reg name="wdt_cvr0" protect="rw">
        <bits access="rw" name="count_value_0" pos="23:0" rst="0xffffff">
          <comment>Count Value for 1st TimeOut</comment>
        </bits>
      </reg>
      <reg name="wdt_cvr1" protect="rw">
        <bits access="rw" name="count_value_1" pos="23:0" rst="0xffffff">
          <comment>Count Value for 2nd TimeOut</comment>
        </bits>
      </reg>
      <reg name="wdt_cr" protect="rw">
        <bits access="rw" name="mode" pos="4:4" rst="0x1">
          <comment>
            Watchdog response mode.
            <br/>
            0 = Generate a system reset.
            <br/>
            1 = First generate an interrupt and if it is not cleared by the time a second timeout occurs then generate a system reset.
          </comment>
        </bits>
        <bits access="rw" name="reset_length" pos="2:0" rst="0x0">
          <comment>
            Reset pulse length in number of wdt clock cycles. The range of values available is 1 to 8 clk cycles.
            <br/>
            3'b000 - 1 clk cycle
            <br/>
            3'b001 - 2 clk cycles
            <br/>
            3'b010 - 3 clk cycles
            <br/>
            ...
            <br/>
            3'b111 - 8 clk cycles
          </comment>
        </bits>
      </reg>
      <reg name="wdt_cmd" protect="rw">
        <bits access="rw" name="cmd" pos="7:0" rst="0x0">
          <comment>
            This register is used to restart/stop the WDT counter. As a safety feature to prevent accidental restarts/stops, write 8'h76 to restart and 8'h34 to stop.
            <br/>
            When written is done, this register is self-cleared on the next clock cycle. Reading this register always returns zero.
          </comment>
        </bits>
      </reg>
      <reg name="wdt_icr" protect="rw">
        <bits access="rw" name="int_clr" pos="0:0" rst="0x0">
          <comment>
            A pulse to clear interrupt.
            <br/>
            When written is done, this register is self-cleared on the next clock cycle. Reading this register always returns zero.
          </comment>
        </bits>
      </reg>
      <reg name="wdt_sr" protect="r">
        <bits access="r" name="wdt_active" pos="1:1" rst="0x0">
          <comment>
            This register shows the word status of the WDT.
            <br/>
            0 = The watchdog counter is idle/stopped.
            <br/>
            1 = The watchdog counter runs.
          </comment>
        </bits>
        <bits access="r" name="int_assert" pos="0:0" rst="0x0">
          <comment>
            This register shows the interrupt status of the WDT.
            <br/>
            0 = Interrupt is inactive.
            <br/>
            1 = Interrupt asserts.
          </comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="xcor.xml">
    <include file="globals.xml"/>
    <module category="GGE_SYS" name="XCOR">
      <var name="XCOR_SYMBOL_SIZE" value="VITAC_MULT_SIZE"/>
      <var name="XCOR_SADDER_SIZE" value="XCOR_SYMBOL_SIZE+1 +6"/>
      <reg name="command" protect="rw">
        <bits access="rw" name="biterr_en" pos="0" rst="0x0">
          <comment>Enables the Biterror calculation mode. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="dco1p_en" pos="1" rst="0x0">
          <comment>Enables the DC Offset Correction (1st pass) mode. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="dco2p_en" pos="2" rst="0x0">
          <comment>Enables the DC Offset Correction (2nd pass) mode. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="dco3p_en" pos="3" rst="0x0">
          <comment>Enables the DC Offset Correction (3rd pass) mode. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="tscxc_en" pos="4" rst="0x0">
          <comment>Enables the Training Sequence Cross-Correlation mode.
      Auto-reset.</comment>
        </bits>
        <bits access="rw" name="srec_en" pos="5" rst="0x0">
          <comment>Enables the Symbol Re-Construction mode. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="bext_en" pos="6" rst="0x0">
          <comment>Enables the Bit Extraction mode. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="sproc_en" pos="7" rst="0x0">
          <comment>Enables the Sum Of PROduCt mode. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="chest_en" pos="8" rst="0x0">
          <comment>Enables the Channel Estimation mode. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="fchxc_en" pos="9" rst="0x0">
          <comment>Enables the FCH Xcorrelation mode. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="sldwin_en" pos="10" rst="0x0">
          <comment>Enables the Sliding window mode. Auto-reset.</comment>
        </bits>
        <bits access="rw" name="it_mask" pos="11" rst="0x0">
          <comment>Mask of the end of processing interrupt.</comment>
        </bits>
        <bits access="rw" name="pack_iq" pos="12" rst="0x0">
          <comment>Data path setting. Pack I and Q on a single 32-bits word.</comment>
        </bits>
        <bits access="rw" name="derotation_en" pos="13" rst="0x0">
          <comment>Data path setting. Enables derotation for DCOC 3pass.</comment>
        </bits>
        <bits access="rw" name="nb_iloop" pos="23:16" rst="0x0">
          <comment>Control setting. Number of internal loop iteration.</comment>
        </bits>
        <bits access="rw" name="nb_symb" pos="31:24" rst="0x0">
          <comment>Control setting. Number of symbols to process.</comment>
        </bits>
      </reg>
      <reg name="status" protect="rw">
        <bits access="r" name="op_pending" pos="0" rst="0x0">
          <comment>This bit is high when an operation is ongoing.</comment>
        </bits>
        <bits access="r" name="it_cause" pos="16" rst="0x0">
          <comment>Masked version of it_status that goes to Interrupt controller.</comment>
        </bits>
        <bits access="rw" name="it_status" pos="31" rst="0x0">
          <comment>This bit is set high when an operation is finished. It must be reset before lauching a new operation if Xcor interrupt is enabled.</comment>
        </bits>
      </reg>
      <reg name="hv0" protect="rw">
        <comment>
          Multipurpose Data Register.
          <br/>
           Store Training Sequence in
    TSXC mode.
          <br/>
           Store SUM in DCOC 3rd pass mode.
          <br/>
           Store bit
    sequence in SREC mode.
          <br/>
           Store SUM in SPROC mode.
          <br/>
           Store I SUM
    in CHEST mode.
          <br/>
           Store R(k-1) in FCHXC mode.
        </comment>
        <bits access="rw" name="hv0" pos="31:0" rst="0x0">
          <comment>Multipurpose.</comment>
        </bits>
      </reg>
      <reg name="hv1" protect="rw">
        <comment>
          Multipurpose Data Register.
          <br/>
           Store Training Sequence in
    TSXC mode.
          <br/>
           Store bit sequence in SREC mode.
          <br/>
           Store Q SUM in
    CHEST mode.
        </comment>
        <bits access="rw" name="hv1" pos="31:0" rst="0x0">
          <comment>Multipurpose.</comment>
        </bits>
      </reg>
      <reg count="6" name="data" protect="rw">
        <comment>
          Multipurpose Data Registers.
          <br/>
          D0 stores
    symbols/softvalues/channel taps depending on mode. Not readable.
          <br/>
          D1
    stores decoded bits/IQ threshols/IQ Offsets/A terms depending on mode. Not
    readable.
          <br/>
          D2 (aka A1) serves as Rd address (decoded bits, A or B
    terms) / Wr address register (I or packed IQ results, Symbols) / event
    counter depending on mode.
          <br/>
          D3 (aka A2) serves as Wr address (Q
    results) / event counter depending on mode.
          <br/>
          D4 stores results from
    VITAC / extracted HardValues depending on mode. Not readable.
          <br/>
          D5 (aka
    A3) serves as Wr address (CQ results) Not readable.
        </comment>
        <bits access="rw" name="data" pos="31:0" rst="0x0">
          <comment>Multipurpose.</comment>
        </bits>
      </reg>
      <reg name="accui" protect="r">
        <bits access="r" name="accui" pos="XCOR_SADDER_SIZE-1:0" rst="0x0">
          <comment>I part accumulator register.</comment>
        </bits>
      </reg>
      <reg name="accuq" protect="r">
        <bits access="r" name="accuq" pos="XCOR_SADDER_SIZE-1:0" rst="0x0">
          <comment>I part accumulator register.</comment>
        </bits>
      </reg>
      <reg name="addr0" protect="rw">
        <comment>
          Address 0 Register.
          <br/>
          Stores Rd address for symbols /
    SoftValues / A terms depending on mode.
          <br/>
           Auto
    increment/decrement/reset.
        </comment>
        <bits access="rw" name="addr0" pos="BB_SRAM_ADDR_WIDTH+1:2" rst="0x0">
          <comment>32-bit word address (bits 0 and 1 disregarded).</comment>
        </bits>
      </reg>
      <reg count="6" name="data_e" protect="rw">
        <comment>Multipurpose Data Edge Registers.</comment>
        <bits access="rw" name="data" pos="31:0" rst="0x0">
          <comment>Multipurpose.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="mips32r6.xml">
    <module category="Debug" name="MIPS32R6">
      <hole size="32"/>
      <reg name="rf0_addr" protect="r">
        <bits access="r" name="rf0_addr" pos="31:0" rst="0">
          <comment>program counter for the RF stage.</comment>
        </bits>
      </reg>
      <hole size="3008"/>
      <reg name="cp0_rd_addr" protect="r">
        <bits access="r" name="cp0_rd_addr" pos="5:0" rst="0"/>
      </reg>
      <reg name="cp0_dcache_pfn" protect="r">
        <bits access="r" name="cp0_dcache_pfn" pos="28:12" rst="0"/>
      </reg>
      <reg name="cp0_tlb_badvaddr" protect="r">
        <bits access="r" name="cp0_tlb_badvaddr" pos="31:0" rst="0"/>
      </reg>
      <reg name="cp0_adr_badvaddr" protect="r">
        <bits access="r" name="cp0_adr_badvaddr" pos="31:0" rst="0"/>
      </reg>
      <reg name="cp0_cause" protect="r">
        <bits access="r" name="cp0_cause_exccode" pos="5:2" rst="0">
          <options>
            <option name="Int" value="0">
              <comment>Interrupt</comment>
            </option>
            <option name="Mod" value="1">
              <comment>TLB modification exception</comment>
            </option>
            <option name="TLBL" value="2">
              <comment>TLB exception (load or instruction fetch)</comment>
            </option>
            <option name="TLBS" value="3">
              <comment>TLB exception (store)</comment>
            </option>
            <option name="AdEL" value="4">
              <comment>Address error exception (load or instruction fetch)</comment>
            </option>
            <option name="AdES" value="5">
              <comment>Address error exception (store)</comment>
            </option>
            <option name="IBE" value="6">
              <comment>Bus error exception (instruction fetch)</comment>
            </option>
            <option name="DBE" value="7">
              <comment>Bus error exception (data reference: load or store)</comment>
            </option>
            <option name="Sys" value="8">
              <comment>Syscall exception</comment>
            </option>
            <option name="Pb" value="9">
              <comment>Breakpoint exception</comment>
            </option>
            <option name="Ri" value="10">
              <comment>Reserved instruction exception</comment>
            </option>
            <option name="CpU" value="11">
              <comment>Coprocessor Unusable exception</comment>
            </option>
            <option name="Ov" value="12">
              <comment>Arithmetic Overflow exception</comment>
            </option>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="cp0_cause_ip_soft" pos="9:8" rst="0">
          <comment>Theses interrupt lines are software interrupts (the cpu can write in the CP0 bits to trigger and clear them).</comment>
          <options>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="cp0_cause_ip_ext" pos="15:10" rst="0">
          <comment>Theses interrupt lines maps to the hardware interrupt lines from the corresponding irq module.</comment>
          <options>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bitgroup name="cp0_cause_ip">
          <entry ref="cp0_cause_ip_soft"/>
          <entry ref="cp0_cause_ip_ext"/>
        </bitgroup>
        <bits access="r" name="cp0_cause_ce" pos="29:28" rst="0">
          <comment>The Coprocessor Error (CE) field indicate the coprocessor unit number referenced when a Coprocessor Unusable exception is taken.</comment>
          <options>
            <default/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="cp0_cause_bd" pos="31" rst="0">
          <comment>The Branch Delay (BD) bit indicate whether the last exception was taken while executing in a branch delay slot.</comment>
          <options>
            <option name="Normal" value="0"/>
            <option name="Delay_slot" value="1"/>
            <mask/>
            <shift/>
          </options>
        </bits>
      </reg>
      <reg name="cp0_status" protect="r">
        <bits access="r" name="cp0_status_iec" pos="0" rst="0">
          <comment>Current Interrupt Enable</comment>
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="cp0_status_kuc" pos="1" rst="0">
          <comment>Current Kernel/User mode</comment>
          <options>
            <option name="kernel" value="0"/>
            <option name="user" value="1"/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="cp0_status_iep" pos="2" rst="0">
          <comment>Previous Interrupt Enable</comment>
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="cp0_status_kup" pos="3" rst="0">
          <comment>Previous Kernel/User mode</comment>
          <options>
            <option name="kernel" value="0"/>
            <option name="user" value="1"/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="cp0_status_ieo" pos="4" rst="0">
          <comment>Old Interrupt Enable</comment>
          <options>
            <option name="disable" value="0"/>
            <option name="enable" value="1"/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="cp0_status_kuo" pos="5" rst="0">
          <comment>Old Kernel/User mode</comment>
          <options>
            <option name="kernel" value="0"/>
            <option name="user" value="1"/>
            <mask/>
            <shift/>
          </options>
        </bits>
        <bits access="r" name="cp0_status_kui" pos="6" rst="0">
        </bits>
        <bits access="r" name="cp0_status_intmask" pos="15:8" rst="0">
          <comment>Interrupt Mask control the enabling of each of the external and software interrupts. (See Cause for more information on interruptions).</comment>
        </bits>
        <bits access="r" name="cp0_streaming_disable" pos="16" rst="0">
          <comment>This bit control handling of non-cached instruction fetch requests. By default, the system block reads multiple words of data from the AMBA bus in burst transactions and saves them in the Streaming Buffer. Non cached instruction fetch requests get their data directly from the Streaming Buffer.
            When &quot;1&quot; the cpu does not use the streaming buffer and does not ask for burst requests on the AMBA bus for non-cache instruction fetch requests.</comment>
        </bits>
        <bits access="r" name="cp0_status_cm" pos="19" rst="0">
          <comment>
            Cache Miss
            <br/>
            Signals that the most recent access to the cachable space resulted in cache miss.
          </comment>
        </bits>
        <bits access="r" name="cp0_status_ts" pos="21" rst="0">
          <comment>Signals that 2 entries in the TLB matched the virtual address. This is an error condition but the processor takes no action other than signalling it via this bit in the Status Register.</comment>
        </bits>
        <bits access="r" name="cp0_status_bev" pos="22" rst="1">
          <comment>Select the location of the exception vectors in ROM or in DRAM.</comment>
        </bits>
        <bits access="r" name="cp0_status_re" pos="25" rst="0">
          <comment>
            Reverse Endian in User mode.
            <font color="red">(probably unused in xcpu)</font>
          </comment>
        </bits>
        <bits access="r" cut="1" name="cp0_status_cu_0" pos="28" rst="0">
          <comment>Control the Usability of the corresponding Coprocessor Unit. (CP0 is always usable when in Kernel mode, regardless of the setting of the CU_0 bit.</comment>
        </bits>
        <bits access="r" cut="1" cutprefix="cp0_Status_CU" cutstart="1" name="cp0_status_cu_123" pos="31:29" rst="0">
          <comment>Control the Usability of the corresponding Coprocessor Unit.</comment>
        </bits>
        <bitgroup name="cp0_status_cu">
          <entry ref="cp0_status_cu_0"/>
          <entry ref="cp0_status_cu_123"/>
        </bitgroup>
      </reg>
      <reg name="cp0_epc" protect="r">
        <bits access="r" name="cp0_epc" pos="31:0" rst="0">
          <comment>Exception Program Counter. Saves the value of the program counter for the instruction
                that caused the exception.</comment>
        </bits>
      </reg>
      <reg name="cp0_entryhi" protect="r">
        <bits access="r" name="cp0_entryhi_pid" pos="11:6" rst="0">
        </bits>
        <bits access="r" name="cp0_entryhi_vpn" pos="31:12" rst="0">
        </bits>
      </reg>
      <reg name="cp0_entrylo" protect="r">
        <bits access="r" name="cp0_pagemask" pos="7:2" rst="0">
        </bits>
        <bits access="r" name="cp0_entrylo_g" pos="8" rst="0">
        </bits>
        <bits access="r" name="cp0_entrylo_v" pos="9" rst="0">
        </bits>
        <bits access="r" name="cp0_entrylo_d" pos="10" rst="0">
        </bits>
        <bits access="r" name="cp0_entrylo_n" pos="11" rst="0">
        </bits>
        <bits access="r" name="cp0_entrylo_pfn" pos="31:12" rst="0">
        </bits>
      </reg>
      <reg name="cp0_index" protect="r">
        <bits access="r" name="cp0_index" pos="13:8" rst="0">
        </bits>
        <bits access="r" name="cp0_index_p" pos="31" rst="0">
        </bits>
      </reg>
      <reg name="cp0_random" protect="r">
        <bits access="r" name="cp0_random" pos="13:8" rst="0">
        </bits>
        <bits access="r" name="cp0_wired" pos="31:26" rst="0">
        </bits>
      </reg>
      <reg name="cp0_context" protect="r">
        <bits access="r" name="cp0_context_badvpn" pos="20:2" rst="0">
        </bits>
        <bits access="r" name="cp0_context_ptebase" pos="31:21" rst="0">
        </bits>
      </reg>
      <reg name="cp0_badvaddr" protect="r">
        <bits access="r" name="cp0_badvaddr" pos="31:0" rst="0">
          <comment>Bad virtual address. Saves the address that caused the address exception.</comment>
        </bits>
      </reg>
      <reg name="cp0_depc" protect="r">
        <bits access="r" name="cp0_depc" pos="31:0" rst="0">
          <comment>Exception Program Counter. Saves the value of the program counter for the instruction
                that caused the exception by break point instruction.</comment>
        </bits>
      </reg>
      <hole size="576"/>
      <reg name="rf0_data" protect="r">
        <bits access="r" name="rf0_data" pos="31:0" rst="0"/>
      </reg>
      <hole size="160"/>
      <reg name="dc0_result" protect="r">
        <bits access="r" name="dc0_result" pos="31:0" rst="0"/>
      </reg>
      <hole size="2848"/>
      <hole size="32"/>
      <reg name="regfile_at" protect="r">
        <bits access="r" name="at" pos="31:0" rst="no">
          <comment>assembler temporary register;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_v0" protect="r">
        <bits access="r" name="v0" pos="31:0" rst="no">
          <comment>
            Used for expression evaluations and for hold integer function results.
            <br/>
             Also used to pass the statuc link when calling nested procedure.
          </comment>
        </bits>
      </reg>
      <reg name="regfile_v1" protect="r">
        <bits access="r" name="v1" pos="31:0" rst="no">
          <comment>
            Used for expression evaluations and for hold integer function results.
            <br/>
             Also used to pass the statuc link when calling nested procedure.
          </comment>
        </bits>
      </reg>
      <reg name="regfile_a0" protect="r">
        <bits access="r" name="a0" pos="31:0" rst="no">
          <comment>register A0 to A3 is used to pass the first 4 words of integer type actual arguments;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_a1" protect="r">
        <bits access="r" name="a1" pos="31:0" rst="no">
          <comment>register A0 to A3 is used to pass the first 4 words of integer type actual arguments;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_a2" protect="r">
        <bits access="r" name="a2" pos="31:0" rst="no">
          <comment>register A0 to A3 is used to pass the first 4 words of integer type actual arguments;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_a3" protect="r">
        <bits access="r" name="a3" pos="31:0" rst="no">
          <comment>register A0 to A3 is used to pass the first 4 words of integer type actual arguments;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_t0" protect="r">
        <bits access="r" name="t0" pos="31:0" rst="no">
          <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_t1" protect="r">
        <bits access="r" name="t1" pos="31:0" rst="no">
          <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_t2" protect="r">
        <bits access="r" name="t2" pos="31:0" rst="no">
          <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_t3" protect="r">
        <bits access="r" name="t3" pos="31:0" rst="no">
          <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_t4" protect="r">
        <bits access="r" name="t4" pos="31:0" rst="no">
          <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_t5" protect="r">
        <bits access="r" name="t5" pos="31:0" rst="no">
          <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_t6" protect="r">
        <bits access="r" name="t6" pos="31:0" rst="no">
          <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_t7" protect="r">
        <bits access="r" name="t7" pos="31:0" rst="no">
          <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_s0" protect="r">
        <bits access="r" name="s0" pos="31:0" rst="no">
          <comment>saved register;
                their values must preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_s1" protect="r">
        <bits access="r" name="s1" pos="31:0" rst="no">
          <comment>saved register;
                their values must preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_s2" protect="r">
        <bits access="r" name="s2" pos="31:0" rst="no">
          <comment>saved register;
                their values must preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_s3" protect="r">
        <bits access="r" name="s3" pos="31:0" rst="no">
          <comment>saved register;
                their values must preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_s4" protect="r">
        <bits access="r" name="s4" pos="31:0" rst="no">
          <comment>saved register;
                their values must preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_s5" protect="r">
        <bits access="r" name="s5" pos="31:0" rst="no">
          <comment>saved register;
                their values must preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_s6" protect="r">
        <bits access="r" name="s6" pos="31:0" rst="no">
          <comment>saved register;
                their values must preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_s7" protect="r">
        <bits access="r" name="s7" pos="31:0" rst="no">
          <comment>saved register;
                their values must preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_t8" protect="r">
        <bits access="r" name="t8" pos="31:0" rst="no">
          <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_t9" protect="r">
        <bits access="r" name="t9" pos="31:0" rst="no">
          <comment>temporary register, used for expression evaluations;
                their values are not preserved across procedure calls.</comment>
        </bits>
      </reg>
      <reg name="regfile_k0" protect="r">
        <bits access="r" name="k0" pos="31:0" rst="no">
          <comment>reserved for the operating system kernal.</comment>
        </bits>
      </reg>
      <reg name="regfile_k1" protect="r">
        <bits access="r" name="k1" pos="31:0" rst="no">
          <comment>reserved for the operating system kernal.</comment>
        </bits>
      </reg>
      <reg name="regfile_gp" protect="r">
        <bits access="r" name="gp" pos="31:0" rst="no">
          <comment>contains the global pointer.</comment>
        </bits>
      </reg>
      <reg name="regfile_sp" protect="r">
        <bits access="r" name="sp" pos="31:0" rst="no">
          <comment>contains the stack pointer.</comment>
        </bits>
      </reg>
      <reg name="regfile_s8" protect="r">
        <bits access="r" name="s8" pos="31:0" rst="no">
          <comment>a saved register (like s0-s7).</comment>
        </bits>
      </reg>
      <reg name="regfile_ra" protect="r">
        <bits access="r" name="ra" pos="31:0" rst="no">
          <comment>contains the return address; used for expression evaluation.</comment>
        </bits>
      </reg>
      <hole size="512"/>
      <reg name="debug_page_address" protect="rw">
        <bits access="rw" name="debug_page_address" pos="3:0" rst="0">
          <comment>
            Debug Page Address Register Is a 4 bit register used for extending the address of
the debug to enable full access to the cache RAMs.
            <br/>
            bit 3 is used when accessing the TAGs to select between Instruction TAG (0) or Data TAG (1).
          </comment>
          <options>
            <option name="ITag" value="0"/>
            <option name="DTag" value="8"/>
            <default/>
            <shift/>
            <mask/>
          </options>
        </bits>
      </reg>
      <reg name="cache_control" protect="rw">
        <bits access="rw" name="dcache_inhibit" pos="0" rst="no">
          <comment>when &quot;ON&quot; all accesses for data are treated as non cache. Data is fetched directly from main memory. The content of the Data Cache is not altered.</comment>
        </bits>
        <bits access="rw" name="icache_inhibit" pos="1" rst="no">
          <comment>when &quot;ON&quot; all accesses for instructions are treated as non cache. Data is fetched directly from main memory. The content of the cache is not altered.</comment>
        </bits>
        <bits access="rw" name="cache hit disable" pos="2" rst="no">
          <comment>when &quot;ON&quot; all accesses to either Instruction or data caches result in a cache miss and a cache refill. This is a quick way to initialize the caches.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="ela.xml">
    <var name="NUM_TRIG_STATES" value="4"/>
    <var name="ID_CAPTURE_SIZE" value="10"/>
    <var name="RAM_ADDR_SIZE" value="10"/>
    <module category="Debug" name="ELA">
      <reg name="ctrl" protect="rw">
        <comment>logic analyzer control register</comment>
        <bits access="rw" name="run" pos="0" rst="0x0">
          <comment>
            run control.
            <br/>
            0 ela-500 disabled. register programming permitted.
            <br/>
            1 ela-500 enabled.
          </comment>
        </bits>
      </reg>
      <reg name="timectrl" protect="rw">
        <comment>timestamp control register</comment>
        <bits access="rw" name="tsen" pos="16" rst="0x0">
          <comment>timestamp enable.</comment>
        </bits>
        <bits access="rw" name="tsint" pos="15:12" rst="0x0">
          <comment>
            timestamp interval.
            <br/>
            when timestamps are enabled, tsint specifies the bit number of the 16-bit trace counter that causes a timestamp
        packet to be requested. the trace counter runs from elaclk. when the specified bit changes, a timestamp
        packet is requested to be inserted into the trace sram when there is an elaclk cycle during which trace data is
        not being captured. the ela-500 does not insert back-to-back timestamps in the sram, even when tsint
        causes multiple requests to be made.
            <br/>
            when tsint = 0, a timestamp is written when action.trace disables trace. looping trigger states enable
        and then disable trace, causing timestamp writes. a timestamp is always written when ctrl.run is cleared and
        the previous trace write contained a data payload.
          </comment>
        </bits>
        <bits access="rw" name="tcsel1" pos="7:4" rst="0x0">
          <comment>
            trace counter 1 select.
            <br/>
            selects the bit number of the 16-bit trace counter that is presented as trace counter[1] in the sram header byte.
          </comment>
        </bits>
        <bits access="rw" name="tcsel0" pos="3:0" rst="0xb">
          <comment>
            trace counter 0 select.
            <br/>
            selects the bit number of the 16-bit trace counter that is presented as trace counter[0] in the sram header byte.
          </comment>
        </bits>
      </reg>
      <reg name="tssr" protect="rw">
        <comment>trigger state select register</comment>
        <bits access="rw" name="altts" pos="7:0" rst="0x0">
          <comment>
            each bit identifies the trigger state that enables independent trace. only trigger state 4 supports independent trace.
            <br/>
            altts[4]=0 trigger state 4 independent trace disabled.
            <br/>
            altts[4]=1 trigger state 4 independent trace enabled.
            <br/>
            all other bits read zero.
          </comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="ptaction" protect="rw">
        <comment>pre-trigger action register</comment>
        <bits access="rw" name="elaoutput" pos="7:4" rst="0x0">
          <comment>sets the value to drive on elaoutput[3:0].</comment>
        </bits>
        <bits access="rw" name="trace" pos="3" rst="0x0">
          <comment>enables trace.</comment>
        </bits>
        <bits access="rw" name="stopclock" pos="2" rst="0x0">
          <comment>sets the level to drive on stopclock.</comment>
        </bits>
        <bits access="rw" name="cttrigout" pos="1:0" rst="0x0">
          <comment>sets the value to drive on cttrigout[1:0].</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="ctsr" protect="ro">
        <comment>current trigger state register</comment>
        <bits access="ro" name="finalstate" pos="31" rst="0x0">
          <comment>
            0 ela-500 is still tracing.
            <br/>
            1 indicates that the ela-500 has stopped advancing trigger states and stopped trace.
            <br/>
            finalstate can be set by trigctrl.countbrk reaching the final loop count,
        or by programming nextstate or altnextstate to zero.
          </comment>
        </bits>
        <bits access="ro" name="ctsr" pos="NUM_TRIG_STATES-1:0" rst="0x1">
          <comment>
            reads current trigger state. this is a one-hot encoded field.
            <br/>
            when ctrl.run:
            <br/>
            0 raz
            <br/>
            1 returns current trigger state.
            <br/>
            if finalstate is 1, then the ctsr field gives the trigger state when finalstate
        became 1.
          </comment>
        </bits>
      </reg>
      <reg name="ccvr" protect="ro">
        <comment>current counter value register</comment>
        <bits access="ro" name="ccvr" pos="31:0" rst="0x0">
          <comment>returns the counter value when the ctsr was last read. if the ctsr has never been read, then the value in the ccvr
        is undefined.</comment>
        </bits>
      </reg>
      <reg name="cavr" protect="ro">
        <comment>current action value register</comment>
        <bits access="ro" name="elaoutput" pos="7:4" rst="0x00">
          <comment>value driven on elaoutput[3:0].</comment>
        </bits>
        <bits access="ro" name="trace" pos="3" rst="0x00">
          <comment>
            trace active.
            <br/>
            0b0 trace is not active.
            <br/>
            0b1 trace is active.
          </comment>
        </bits>
        <bits access="ro" name="stopclock" pos="2" rst="0x00">
          <comment>
            level driven on stopclock.
            <br/>
            0b0 0 driven on stopclock.
            <br/>
            0b1 1 driven on stopclock.
          </comment>
        </bits>
        <bits access="ro" name="cttrigout" pos="1:0" rst="0x00">
          <comment>value driven on cttrigout[1:0].</comment>
        </bits>
      </reg>
      <reg name="rdcaptid" protect="ro">
        <comment>read captured transaction id register</comment>
        <bits access="ro" name="rdcaptid" pos="ID_CAPTURE_SIZE-1:0" rst="-">
          <comment>returns the captured transaction id.</comment>
        </bits>
      </reg>
      <hole size="128"/>
      <reg name="rrar" protect="rw">
        <comment>ram read address register</comment>
        <bits access="rw" name="rra" pos="RAM_ADDR_SIZE-1:0" rst="-">
          <comment>
            ram read address.
            <br/>
            writes to the rra cause the trace sram data at that address to be transferred into the holding
        register.
            <br/>
            after the sram read data is transferred to the holding register, rra increments by one. this
        prepares the rra address for sequential rrdr reads.
            <br/>
            the rra automatically increments after apb reads from the rrdr have read the contents of the
        holding register. an rrdr read of the last data in the holding register initiates a read to sram at
        the address pointed to by the rra. the holding register is filled with the data at this address, then
        the rra increments.
          </comment>
        </bits>
      </reg>
      <reg name="rrdr" protect="ro">
        <comment>ram read data register</comment>
        <bits access="ro" name="rrd" pos="31:0" rst="-">
          <comment>
            reads sram data from the holding register.
            <br/>
            reads from the rrd return the sram data from the holding register. the first read of the rrd after an rrar update
        returns the trace data header byte value, zero-extended to 32 bits. subsequent reads of the rrd return 32-bit chunks of
        the trace data payload, starting with the least significant word, until all the payload data has been read, that is, two
        words if grp_width = 64, four words if grp_width = 128, and eight words if grp_width = 256.
            <br/>
            when the final 32 bits of the payload have been read, the rra is incremented automatically, and the next word of
        sram data is copied into the holding register. this enables the sram data content to be read out efficiently.
            <br/>
            the rra wraps to address zero if it is incremented beyond the maximum depth of the sram.
          </comment>
        </bits>
      </reg>
      <reg name="rwar" protect="rw">
        <comment>ram write address register</comment>
        <bits access="rw" name="wrap" pos="31" rst="-">
          <comment>
            the wrap bit is set when the ram write address is incremented beyond 2ram_addr_size while
            <br/>
            the ela-500 is capturing trace data. the wrap bit is not set by writes to the rwdr that cause the
            <br/>
            ram write address to roll over. software must clear the wrap bit when writing to the rwar.
          </comment>
        </bits>
        <bits access="rw" name="rwa" pos="RAM_ADDR_SIZE-1:0" rst="-">
          <comment>
            ram write address.
            <br/>
            writes to the rwa set the sram address for data that is then written through the rwdr.
            <br/>
            reads from the rwa return the address of the sram location that is to be written next, either by
        writes to the rwdr, or by the trace unit.
            <br/>
            when trace is stopped, the rwa contains the address of the last sram location that was written
        plus one. if the ram write address was incremented beyond the depth of the ram while the
        ela-500 was capturing trace data, the wrap bit is set.
            <br/>
            the rwar is automatically incremented by apb writes to the sram through the rwdr.
          </comment>
        </bits>
      </reg>
      <reg name="rwdr" protect="wo">
        <comment>ram write data register</comment>
        <bits access="wo" name="rwdr" pos="31:0" rst="-">
          <comment>
            writes data to the write holding register and initiates an sram write when the write holding register is full.
        writes to the rwd update the internal write holding register.
            <br/>
            the first write to the rwd sets the header byte value from the least significant byte written. subsequent writes to the
        rwd set 32-bit chunks of the payload, starting with the least significant chunk. when the final 32 bits of the payload
        have been written, the content of the holding register is copied into the sram and the rwa is incremented
        automatically.
          </comment>
        </bits>
      </reg>
      <hole size="1408"/>
      <struct count="NUM_TRIG_STATES" name="trig_state">
        <reg name="sigsel" protect="rw">
          <comment>signal select registers</comment>
          <bits access="rw" name="sigsel" pos="11:0" rst="-">
            <comment>
              selects signal group.
              <br/>
              0x1 selects signal group 0.
              <br/>
              0x2 selects signal group 1.
              <br/>
              0x4 selects signal group 2.
              <br/>
              0x8 selects signal group 3.
              <br/>
              0x10 selects signal group 4.
              <br/>
              0x20 selects signal group 5.
              <br/>
              0x40 selects signal group 6.
              <br/>
              0x80 selects signal group 7.
              <br/>
              0x100 selects signal group 8.
              <br/>
              0x200 selects signal group 9.
              <br/>
              0x400 selects signal group 10.
              <br/>
              0x800 selects signal group 11.
            </comment>
          </bits>
        </reg>
        <reg name="trigctrl" protect="rw">
          <comment>trigger control registers</comment>
          <bits access="rw" name="altcompsel" pos="15" rst="-">
            <comment>
              selects the alternative comparison mode:
              <br/>
              0b0 trigger signal alternative comparisons selected.
              <br/>
              0b1 trigger counter alternative comparisons selected.
            </comment>
          </bits>
          <bits access="rw" name="altcomp" pos="14:12" rst="-">
            <comment>
              trigger signal alternative comparison type select:
              <br/>
              0b000 trigger signal alternative comparisons disabled.
              <br/>
              0b001 alternative compare type is equal (==).
              <br/>
              0b010 alternative compare type is greater than (&gt;).
              <br/>
              0b011 alternative compare type is greater than or equal (&gt;=).
              <br/>
              0b101 alternative compare type is not equal (!=).
              <br/>
              0b110 alternative compare type is less than (&lt;).
              <br/>
              0b111 alternative compare type is less than or equal (&lt;=).
            </comment>
          </bits>
          <bits access="rw" name="captid" pos="11:10" rst="-">
            <comment>
              <br/>
              0b00 disable use of the captured id for signal comparisons.
              <br/>
              0b01 capture id when trigger signal condition matches.
          the id is captured, from signalgrp[id_capture_size-1:0].
              <br/>
              0b10 use the captured id instead of the target value in sigcomp[id_capture_size-1:0] for
          comparison of signalgrp[id_capture_size-1:0].
              <br/>
              0b11 use the captured id instead of the signalgrp[id_capture_size-1:0] for a comparison
          against sigcomp[id_capture_size-1:0].
            </comment>
          </bits>
          <bits access="rw" name="countbrk" pos="9" rst="-">
            <comment>
              loop counter break.
              <br/>
              the loop counter break uses the trigger state counter to break loops between trigger states after a trigger
          counter comparison. when the counter comparison matches, the trigger state goes to a final state, which
          stops trace writes and leaves the output actions at the previous trigger state action value.
              <br/>
              0b0 normal operation.
              <br/>
              0b1 break trigger state loop: a counter comparison match causes a transition to the
          final state, otherwise go to the nextstate trigger state as the counter
          increments.
            </comment>
          </bits>
          <bits access="rw" name="countclr" pos="8" rst="-">
            <comment>
              counter clear.
              <br/>
              0b0 do not clear the counter value when moving to a different nextstate.
              <br/>
              0b1 clear the counter value when moving to a different nextstate.
              <br/>
              note: trigctrl.watchrst must be 0b0 when using this feature.
            </comment>
          </bits>
          <bits access="rw" name="trace" pos="7:6" rst="-">
            <comment>
              trace capture control.
              <br/>
              0b00 trace is captured when trigger signal comparison succeeds.
              <br/>
              0b01 trace is captured when trigger counter comparison succeeds.
              <br/>
              0b10 trace is captured every elaclk cycle.
              <br/>
              0b11 reserved.
            </comment>
          </bits>
          <bits access="rw" name="countsrc" pos="5" rst="-">
            <comment>
              counter source select.
              <br/>
              0b0 counter is incremented every elaclk cycle.
              <br/>
              0b1 counter is incremented when trigger signal comparison matches.
            </comment>
          </bits>
          <bits access="rw" name="watchrst" pos="4" rst="-">
            <comment>
              counter reset.
              <br/>
              0b0 do not reset the counter after a trigger signal comparison match.
              <br/>
              0b1 reset the counter after a trigger signal comparison match.
              <br/>
              the counter acts like an activity watchdog timer, only allowing advancement to the
          next trigger state when the trigger counter comparison is reached. the counter is
          reset by a signal comparison.
            </comment>
          </bits>
          <bits access="rw" name="compsel" pos="3" rst="-">
            <comment>
              comparison mode. acts as both a counter enable and a select for the comparison mode.
              <br/>
              0b0 disable counters and select trigger signal comparison mode.
              <br/>
              0b1 enable counters and select trigger counter comparison mode.
            </comment>
          </bits>
          <bits access="rw" name="comp" pos="2:0" rst="-">
            <comment>
              trigger signal comparison type select.
              <br/>
              0b000 trigger signal comparisons disabled. the enabled counters count clocks
          immediately after the trigger state has been entered and generate a programmable
          output action and transition to the next trigger state when the counter compare
          register count is reached, that is when a trigger counter comparison match
          occurs.
              <br/>
              0b001 compare type is equal (==).
              <br/>
              0b010 compare type is greater than (&gt;).
              <br/>
              0b011 compare type is greater than or equal (&gt;=).
              <br/>
              0b101 compare type is not equal (!=).
              <br/>
              0b110 compare type is less than (&lt;).
              <br/>
              0b111 compare type is less than or equal (&lt;=).
            </comment>
          </bits>
        </reg>
        <reg name="nextstate" protect="rw">
          <comment>next state registers</comment>
          <bits access="rw" name="nextstate" pos="NUM_TRIG_STATES-1:0" rst="-">
            <comment>
              selects the next state to move to after the trigger condition has been met in the current
          state.
              <br/>
              0x0 do not change state. this is the final trigger state.
              <br/>
              0x1 selects trigger state 0.
              <br/>
              0x2 selects trigger state 1.
              <br/>
              0x4 selects trigger state 2.
              <br/>
              0x8 selects trigger state 3.
              <br/>
              0x10 selects trigger state 4, when num_trig_states=5.
            </comment>
          </bits>
        </reg>
        <reg name="action" protect="rw">
          <comment>action registers</comment>
          <bits access="rw" name="elaoutput" pos="7:4" rst="0x00">
            <comment>value to drive on elaoutput[3:0].</comment>
          </bits>
          <bits access="rw" name="trace" pos="3" rst="0x00">
            <comment>
              trace active.
              <br/>
              0b0 trace is not active.
              <br/>
              0b1 trace is active.
            </comment>
          </bits>
          <bits access="rw" name="stopclock" pos="2" rst="0x00">
            <comment>
              level to drive on stopclock.
              <br/>
              0b0 drive 0 on stopclock.
              <br/>
              0b1 drive 1 on stopclock.
            </comment>
          </bits>
          <bits access="rw" name="cttrigout" pos="1:0" rst="0x00">
            <comment>value to drive on cttrigout[1:0].</comment>
          </bits>
        </reg>
        <reg name="altnextstate" protect="rw">
          <comment>alt next state registers</comment>
          <bits access="rw" name="altnextstate" pos="NUM_TRIG_STATES-1:0" rst="-">
            <comment>
              selects the next state to move to after the conditional trigger condition has been
          met in the current state.
              <br/>
              0x0 do not change state. this is the final trigger state.
              <br/>
              0x1 selects trigger state 0.
              <br/>
              0x2 selects trigger state 1.
              <br/>
              0x4 selects trigger state 2.
              <br/>
              0x8 selects trigger state 3.
              <br/>
              0x10 selects trigger state 4, when num_trig_states=5.
            </comment>
          </bits>
        </reg>
        <reg name="altaction" protect="rw">
          <comment>alt action registers</comment>
          <bits access="rw" name="elaoutput" pos="7:4" rst="0x00">
            <comment>value to drive on elaoutput[3:0].</comment>
          </bits>
          <bits access="rw" name="trace" pos="3" rst="0x00">
            <comment>
              trace active.
              <br/>
              0b0 trace is not active.
              <br/>
              0b1 trace is active.
            </comment>
          </bits>
          <bits access="rw" name="stopclock" pos="2" rst="0x00">
            <comment>
              level to drive on stopclock.
              <br/>
              0b0 drive 0 on stopclock.
              <br/>
              0b1 drive 1 on stopclock.
            </comment>
          </bits>
          <bits access="rw" name="cttrigout" pos="1:0" rst="0x00">
            <comment>value to drive on cttrigout[1:0].</comment>
          </bits>
        </reg>
        <hole size="64"/>
        <reg name="countcomp" protect="rw">
          <comment>counter compare registers</comment>
          <bits access="rw" name="countcomp" pos="31:0" rst="-">
            <comment>value that, when reached in the associated up-counter for this trigger state, causes a trigger counter
          comparison match to occur.</comment>
          </bits>
        </reg>
        <hole size="96"/>
        <reg name="extmask" protect="rw">
          <comment>external mask registers</comment>
          <bits access="rw" name="exttrig" pos="7:2" rst="-">
            <comment>
              mask exttrig[5:0] signals. each signal is masked by clearing the appropriate bit.
              <br/>
              0b0 external trigger input signal is masked and is not used in comparisons.
              <br/>
              0b1 external trigger input signal is not masked.
            </comment>
          </bits>
          <bits access="rw" name="cttrigin" pos="1:0" rst="-">
            <comment>
              mask cttrigin[1:0] signals. each signal is masked by clearing the appropriate bit.
              <br/>
              0b0 external trigger input signal is masked and is not used in comparisons.
              <br/>
              0b1 external trigger input signal is not masked.
            </comment>
          </bits>
        </reg>
        <reg name="extcomp" protect="rw">
          <comment>external compare registers</comment>
          <bits access="rw" name="exttrig" pos="7:2" rst="-">
            <comment>compare value for exttrig[5:0] signals.</comment>
          </bits>
          <bits access="rw" name="cttrigin" pos="1:0" rst="-">
            <comment>compare value for cttrigin[1:0] signals.</comment>
          </bits>
        </reg>
        <hole size="64"/>
        <reg count="4" name="sigmask" protect="rw">
          <comment>signal mask registers</comment>
          <bits access="rw" name="sigmask" pos="31:0" rst="-">
            <comment>
              mask bits from sigcomp[31:0].
              <br/>
              mask bits from sigcomp[63:32].
              <br/>
              mask bits from sigcomp[95:64]. these bits are only used if grp_width = 128 or 256.
              <br/>
              mask bits from sigcomp[127:96]. these bits are only used if grp_width = 128 or 256.
            </comment>
          </bits>
        </reg>
        <hole size="384"/>
        <reg count="4" name="sigcomp" protect="rw">
          <comment>signal compare registers</comment>
          <bits access="rw" name="sigcomp" pos="31:0" rst="-">
            <comment>
              compare value for signal group signals[31:0].
              <br/>
              compare value for signal group signals[63:32].
              <br/>
              compare value for signal group signals[95:64]. these bits are only used if grp_width = 128 or 256.
              <br/>
              compare value for signal group signals[127:96]. these bits are only used if grp_width = 128 or 256.
            </comment>
          </bits>
        </reg>
        <hole size="896"/>
      </struct>
      <hole size="20288"/>
      <reg name="ittrigout" protect="wo">
        <comment>integration mode action trigger output register</comment>
        <bits access="wo" name="elaoutput" pos="7:4" rst="0x00">
          <comment>value to drive on elaoutput[3:0] when itctlr.ime = 1.</comment>
        </bits>
        <bits access="wo" name="stopclock" pos="2" rst="0x00">
          <comment>
            level to drive on stopclock when itctlr.ime = 1.
            <br/>
            0b0 drive 0 on stopclock.
            <br/>
            0b1 drive 1 on stopclock.
          </comment>
        </bits>
        <bits access="wo" name="cttrigout" pos="1:0" rst="0x00">
          <comment>value to drive on cttrigout[1:0] when itctlr.ime = 1.</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="ittrigin" protect="ro">
        <comment>integration mode external trigger input register</comment>
        <bits access="ro" name="exttrig" pos="7:2" rst="-">
          <comment>captures the value on exttrig[5:0] when itctlr.ime = 1.</comment>
        </bits>
        <bits access="ro" name="cttrigin" pos="1:0" rst="-">
          <comment>captures the value on cttrigin[1:0] when itctlr.ime = 1.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="itctrl" protect="rw">
        <comment>integration mode control register</comment>
        <bits access="rw" name="ime" pos="0" rst="0x0">
          <comment>
            integration mode enable.
            <br/>
            0b0 integration mode disabled. the ela-500 operates normally.
            <br/>
            0b1 integration mode enabled when ctrl.run = 0.
          </comment>
        </bits>
      </reg>
      <hole size="1376"/>
      <reg name="lar" protect="wo">
        <comment>lock access register</comment>
        <bits access="wo" name="lar" pos="31:0" rst="-">
          <comment>permits writes to the other ela-500 registers when the access code 0xc5acce55 is written. writing any other value
        prevents access to the other ela-500 registers.</comment>
        </bits>
      </reg>
      <reg name="lsr" protect="ro">
        <comment>lock status register</comment>
        <bits access="ro" name="lsr" pos="2:0" rst="0x00">
          <comment>
            returns the status of the lock access control.
            <br/>
            0b001 write access permitted.
            <br/>
            0b011 write access not permitted.
          </comment>
        </bits>
      </reg>
      <reg name="authstatus" protect="ro">
        <comment>authentication status register</comment>
        <bits access="ro" name="snid" pos="7:6" rst="-">
          <comment>
            secure, non-invasive debug.
            <br/>
            0b10 debug disabled.
            <br/>
            0b11 debug enabled.
          </comment>
        </bits>
        <bits access="ro" name="sid" pos="5:4" rst="-">
          <comment>
            secure, invasive debug.
            <br/>
            0b10 debug disabled.
            <br/>
            0b11 debug enabled.
          </comment>
        </bits>
        <bits access="ro" name="nsnid" pos="3:2" rst="-">
          <comment>
            non-secure, non-invasive debug.
            <br/>
            0b10 debug disabled.
            <br/>
            0b11 debug enabled.
          </comment>
        </bits>
        <bits access="ro" name="nsid" pos="1:0" rst="-">
          <comment>
            non-secure, invasive debug.
            <br/>
            0b10 debug disabled.
            <br/>
            0b11 debug enabled.
          </comment>
        </bits>
      </reg>
      <reg name="devarch" protect="ro">
        <comment>device architecture register</comment>
        <bits access="ro" name="architect" pos="31:21" rst="0x23b">
          <comment>
            the architect of the device.
            <br/>
            0x23b arm.
          </comment>
        </bits>
        <bits access="ro" name="present" pos="20" rst="0x1">
          <comment>
            indicates that the register is present.
            <br/>
            1 register present.
          </comment>
        </bits>
        <bits access="ro" name="revision" pos="19:16" rst="0x0">
          <comment>
            architecture revision.
            <br/>
            0 first revision.
          </comment>
        </bits>
        <bits access="ro" name="archid" pos="15:0" rst="0x0a75">
          <comment>
            the architecture of the device.
            <br/>
            0x0a75 coresight ela.
          </comment>
        </bits>
      </reg>
      <reg name="devid2" protect="ro">
        <comment>device configuration register 2</comment>
        <bits access="ro" name="trigin_edge" pos="19:16" rst="-d">
          <comment>
            0: level detect of cttrigin and exttrig.
            <br/>
            1: single edge detect of cttrigin and exttrig.
          </comment>
        </bits>
        <bits access="ro" name="comp_width" pos="15:8" rst="-d">
          <comment>
            indicates the comparator width.
        0: comparator width = grp_width.
            <br/>
            &gt;0: comparator width = (comp_width + 1) x 8.
            <br/>
            for example, if comp_width = 15, then comparator width = 256.
          </comment>
        </bits>
        <bits access="ro" name="altts" pos="7:0" rst="-d">
          <comment>
            0x00 num_trig_states=4. trigger state 4 is not implemented.
            <br/>
            0x10 num_trig_states=5. trigger state 4 is implemented and can be used for independent trace.
            <br/>
            all other encodings are reserved and read as 0x00.
          </comment>
        </bits>
      </reg>
      <reg name="devid1" protect="ro">
        <comment>device configuration register 1</comment>
        <bits access="ro" name="countwidth" pos="31:24" rst="-d">
          <comment>counter width in bits. fixed at 32.</comment>
        </bits>
        <bits access="ro" name="numtrigstates" pos="23:16" rst="-d">
          <comment>number of trigger states. four or five.</comment>
        </bits>
        <bits access="ro" name="siggrpwidth" pos="15:8" rst="-d">
          <comment>
            signal group width. the field value is (signal group width/8) - 1.
            <br/>
            for example, 7 if grp_width = 64, 15 if grp_width = 128, and 31 if grp_width = 256.
          </comment>
        </bits>
        <bits access="ro" name="numsiggrps" pos="7:0" rst="-d">
          <comment>number of signal groups. fixed at 12.</comment>
        </bits>
      </reg>
      <reg name="devid" protect="ro">
        <comment>device configuration register</comment>
        <bits access="ro" name="scrambler" pos="28:25" rst="-d">
          <comment>
            0: trace read data scrambler not present.
            <br/>
            1: trace read data scrambler present.
          </comment>
        </bits>
        <bits access="ro" name="id_capture_size" pos="24:20" rst="-d">
          <comment>2-30 bits when cond_trig = 1, or 0 otherwise.</comment>
        </bits>
        <bits access="ro" name="cond_trig" pos="19:16" rst="-d">
          <comment>
            shows the value of the cond_trig parameter.
            <br/>
            1, when cond_trig = 1, or 0 otherwise.
          </comment>
        </bits>
        <bits access="ro" name="sram_addr_size" pos="15:8" rst="-d">
          <comment>sram address width in bits.</comment>
        </bits>
        <bits access="ro" name="traceformat" pos="7:4" rst="-d">
          <comment>
            trace implementation:
            <br/>
            1 fixed at 1. indicates trace header format revision 1.
          </comment>
        </bits>
        <bits access="ro" name="tracetype" pos="3:0" rst="-d">
          <comment>
            atb trace:
            <br/>
            0 atb trace not implemented.
            <br/>
            1 atb trace is implemented.
          </comment>
        </bits>
      </reg>
      <reg name="devtype" protect="ro">
        <comment>device type identifier register</comment>
        <bits access="ro" name="devtype" pos="7:0" rst="0x75">
          <comment>
            0x75.
            <br/>
            sub type = 0x7.
            <br/>
            major type = 0x5.
          </comment>
        </bits>
      </reg>
      <reg name="pidr4" protect="ro">
        <comment>peripheral id4 register</comment>
        <bits access="ro" name="size" pos="7:4" rst="0x0">
          <comment>0x0. one 4kb count.</comment>
        </bits>
        <bits access="ro" name="des_2" pos="3:0" rst="0x4">
          <comment>0x4. jep continuation code for arm.</comment>
        </bits>
      </reg>
      <reg name="pidr5" protect="ro">
        <comment>peripheral id5 register</comment>
        <bits access="ro" name="pidr5" pos="7:0" rst="0x00">
          <comment>0x00. reserved.</comment>
        </bits>
      </reg>
      <reg name="pidr6" protect="ro">
        <comment>peripheral id6 register</comment>
        <bits access="ro" name="pidr6" pos="7:0" rst="0x00">
          <comment>0x00. reserved.</comment>
        </bits>
      </reg>
      <reg name="pidr7" protect="ro">
        <comment>peripheral id7 register</comment>
        <bits access="ro" name="pidr7" pos="7:0" rst="0x00">
          <comment>0x00. reserved.</comment>
        </bits>
      </reg>
      <reg name="pidr0" protect="ro">
        <comment>peripheral id0 register</comment>
        <bits access="ro" name="part_0" pos="7:0" rst="0xb8">
          <comment>0xb8. bits[7:0] of part number 0x9b8.</comment>
        </bits>
      </reg>
      <reg name="pidr1" protect="ro">
        <comment>peripheral id1 register</comment>
        <bits access="ro" name="des_0" pos="7:4" rst="0xb">
          <comment>0xb. bits[3:0] of jep106 identification code for arm 0x3b.</comment>
        </bits>
        <bits access="ro" name="part_1" pos="3:0" rst="0x9">
          <comment>0x9. bits[11:8] of part number 0x9b8.</comment>
        </bits>
      </reg>
      <reg name="pidr2" protect="ro">
        <comment>peripheral id2 register</comment>
        <bits access="ro" name="revision" pos="7:4" rst="0x2">
          <comment>0x2. revision number. indicates revision r2p0.</comment>
        </bits>
        <bits access="ro" name="jedec" pos="3" rst="0x1">
          <comment>0b1. fixed at 0b1.</comment>
        </bits>
        <bits access="ro" name="des_1" pos="2:0" rst="0x3">
          <comment>0b011. bits[6:4] of jep106 identification code for arm 0x3b.</comment>
        </bits>
      </reg>
      <reg name="pidr3" protect="ro">
        <comment>peripheral id3 register</comment>
        <bits access="ro" name="revand" pos="7:4" rst="0x00">
          <comment>0x0. revand.</comment>
        </bits>
        <bits access="ro" name="cmod" pos="3:0" rst="0x00">
          <comment>0x0. indicates whether the customer has modified the behavior of the component. in most cases, this field is
        0b0000. you can change this value when you make authorized modifications to this component.</comment>
        </bits>
      </reg>
      <reg name="cidr0" protect="ro">
        <comment>component id0 register</comment>
        <bits access="ro" name="prmbl_0" pos="7:0" rst="0x0d">
          <comment>0x0d. preamble.</comment>
        </bits>
      </reg>
      <reg name="cidr1" protect="ro">
        <comment>component id1 register</comment>
        <bits access="ro" name="class" pos="7:4" rst="0x9">
          <comment>0x9. indicates a coresight component.</comment>
        </bits>
        <bits access="ro" name="prmbl_1" pos="3:0" rst="0x0">
          <comment>0x0. preamble.</comment>
        </bits>
      </reg>
      <reg name="cidr2" protect="ro">
        <comment>component id2 register</comment>
        <bits access="ro" name="prmbl_2" pos="7:0" rst="0x05">
          <comment>0x05. preamble.</comment>
        </bits>
      </reg>
      <reg name="cidr3" protect="ro">
        <comment>component id3 register</comment>
        <bits access="ro" name="prmbl_3" pos="7:0" rst="0xb1">
          <comment>0xb1. preamble.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="evitac.xml">
    <include file="globals.xml"/>
    <module category="GGE_SYS" name="EVITAC">
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="psampl_inc" pos="7:0" rst="0x0">
          <comment>Control setting. psample increment.</comment>
        </bits>
        <bits access="rw" name="nb_symbol" pos="15:8" rst="0x0">
          <comment>Control setting. Number of symbols.</comment>
        </bits>
        <bits access="rw" name="nodemetric_his" pos="23:16" rst="0x0">
          <comment>Control setting. node metric history.</comment>
        </bits>
        <bits access="rw" name="cmd" pos="31:24" rst="0x0">
          <comment>Control setting. Command.</comment>
        </bits>
      </reg>
      <reg name="pbmml_addr" protect="rw">
        <bits access="rw" name="pbmml_addr" pos="31:0" rst="0x0">
          <comment>pbmml address.</comment>
        </bits>
      </reg>
      <reg name="pzfm_addr" protect="rw">
        <bits access="rw" name="pzfm_addr" pos="31:0" rst="0x0">
          <comment>pzfm address.</comment>
        </bits>
      </reg>
      <reg name="psmpl_addr" protect="rw">
        <bits access="rw" name="psmpl_addr" pos="31:0" rst="0x0">
          <comment>psample address.</comment>
        </bits>
      </reg>
      <reg name="output_bits_addr" protect="rw">
        <bits access="rw" name="output_bits_addr" pos="31:0" rst="0x0">
          <comment>softbits output address.</comment>
        </bits>
      </reg>
      <reg name="shift_status" protect="rw">
        <bits access="rw" name="status" pos="7:0" rst="0x0">
          <comment>Status is set to 1 when an operation is finished,It must be reset before lauching a new operation</comment>
        </bits>
        <bits access="rw" name="svshift" pos="15:8" rst="0x0">
          <comment>sv shift bits.</comment>
        </bits>
        <bits access="rw" name="bmshift" pos="23:16" rst="0x0">
          <comment>bm shift bits.</comment>
        </bits>
      </reg>
      <reg name="zfhist_history" protect="rw">
        <bits access="rw" name="zfhist_history" pos="31:0" rst="0x0">
          <comment>zfhist history.</comment>
        </bits>
      </reg>
      <var name="EVITAC_START" value="1"/>
    </module>
  </archive>
  <archive relative="dma.xml">
    <module category="GGE_SYS" name="DMA">
      <reg name="get_channel" protect="w">
        <bits access="r" name="get channel" pos="0" rst="1">
          <comment>
            Returns 1 and locks the DMA channel for a transaction if it is
      available. Else returns 0.
            <br/>
            Clear the transfer done interrupt
      status.
          </comment>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="enable" pos="0" rst="0">
          <comment>Status of the DMA: 1 if enabled, 0 if disabled.</comment>
        </bits>
        <bits access="r" name="int done cause" pos="1" rst="0">
          <comment>
            Cause of the interrupt. This bit is set when the transfer is
      done and the interrupt mask bit is set.
            <br/>
            Write one in the Int Clear
      or write 0 in Enable control bits to clear Int Done Cause bit.
          </comment>
        </bits>
        <bits access="r" name="int done status" pos="2" rst="0">
          <comment>
            Status of the interrupt. Status of the transfer: 1 if the
      transfer is finished, 0 if it is not finished.
            <br/>
            Write one in the
      Int Clear or write 0 in Enable control bits to clear Int Done Status
      bit.
          </comment>
        </bits>
        <bits access="r" name="channel lock" pos="4" rst="0">
          <comment>Actual status of channel lock. Channel is unlocked at the end
      of transaction or when the DMA is disabled.</comment>
        </bits>
      </reg>
      <reg name="control" protect="rw">
        <bits access="rw" name="enable" pos="0" rst="0">
          <comment>Controls the DMA. Write 1 to enable the DMA, write 0 to disable
      it. When 0 is written in this register, the Int Done Status and Cause
      bits are reset.</comment>
        </bits>
        <bits access="rw" name="int done mask" pos="1" rst="0">
          <comment>End of transfer interrupt generation. When 1, the DMA will send
      an interrupt at transaction completion.</comment>
          <options>
            <shift/>
          </options>
        </bits>
        <bits access="rw" name="int done clear" pos="2" rst="0">
          <comment>
            Clear the transfer done interruption (this will clear Int Done
      Status and Int Done Cause).
            <br/>
            This bit is auto-clear. You will
      always read 0 here.
          </comment>
        </bits>
        <bits access="rw" name="use pattern" pos="4" rst="0">
          <comment>If this bit is set, the source address will be ignored and the
      memory will be fill with the value of the pattern register.</comment>
        </bits>
        <bits access="rw" name="max_burst_length" pos="6:5" rst="00">
          <comment>
            Set the MAX burst length.
            <br/>
             The 2'b10 mean burst max 16, 2'b01 mean burst max 8, 00 mean burst max 4.
          </comment>
        </bits>
        <bits access="w" name="stop transfer" pos="8" rst="0">
          <comment>The DMA stop the current transfer and flush his FIFO (write
      only bit). When the FIFO is empty and last write performed, the DMA is
      disabled and available for a next transfer. The number of bytes copied
      is readable on DMA_XFER_SIZE register.</comment>
        </bits>
        <bits access="rw" name="gea enable" pos="12" rst="0">
          <options>
            <option name="DMA" value="0"/>
            <option name="GEA" value="1"/>
            <default/>
          </options>
          <comment>Enable Gea process when 1.</comment>
        </bits>
        <bits access="rw" name="gea algorithm" pos="13" rst="1">
          <options>
            <option name="GEA1" value="0"/>
            <option name="GEA2" value="1"/>
            <default/>
          </options>
          <comment>This field sets the type of GEA algorithm to process.</comment>
        </bits>
        <bits access="rw" name="gea direction" pos="14" rst="1">
          <options>
            <shift/>
          </options>
          <comment>This field selects the Direction in the GEA algorithm.</comment>
        </bits>
        <bits access="rw" name="fcs enable" pos="16" rst="0">
          <options>
            <option name="NORMAL_DMA" value="0"/>
            <option name="FCS_PROCESS" value="1"/>
            <default/>
          </options>
          <comment>Enable FCS process when 1.</comment>
        </bits>
        <bits access="rw" name="dst addr mgt" pos="21:20" rst="0">
          <options>
            <option name="NORMAL_DMA" value="0"/>
            <option name="CONST_ADDR" value="1"/>
            <option name="ALTERN_ADDR" value="2"/>
            <option name="RESERVED" value="3"/>
            <default/>
          </options>
          <comment>
            Destination address management.
            <br/>
            00 : Normal DMA operation,
      DMA_DST_ADDR register define the destination address.
            <br/>
             01 : DMA
      write address is constant (no incremented) and defined by the
      DMA_DST_ADDR register. All data write are in 16-bit.
            <br/>
             10 : DMA
      write address is alternatively defined by DMA_DST_ADDR and
      DMA_SD_DST_ADDR registers. All data write are in 16-bit.
            <br/>
            In this
      configuration, DMA write operation is alternatively:
            <br/>
            DMA_DST_ADDR
      &lt;= DMA_PATTERN register
            <br/>
            DMA_SD_DST_ADDR &lt;=
      Data[DMA_SRC_ADDR]
            <br/>
            11 : reserved
          </comment>
        </bits>
      </reg>
      <reg name="src_addr" protect="rw">
        <bits access="rw" name="src address" pos="27:0" rst="0xFFFFFFF">
          <comment>Source start read byte address. When a transfer is stalled by
      the Stop_Transfer bit, this register give the next current source
      address, which is directly the value to re-program to complete the
      transfer stopped.</comment>
        </bits>
      </reg>
      <reg name="dst_addr" protect="rw">
        <bits access="rw" name="dst address" pos="27:0" rst="0xFFFFFFF">
          <comment>Destination start read byte address. When a transfer is stalled
      by the Stop_Transfer bit, this register give the next current
      destination address, which is directly the value to re-program to
      complete the transfer stopped.</comment>
        </bits>
      </reg>
      <reg name="sd_dst_addr" protect="rw">
        <bits access="rw" name="sd dst address" pos="27:0" rst="0xFFFFFFF">
          <comment>Second destination address. This register is only used when
      Dst_Address_Mgt=10.</comment>
        </bits>
      </reg>
      <reg name="xfer_size" protect="rw">
        <bits access="rw" name="transfer size" pos="17:0" rst="0x3FFFF">
          <comment>Transfer size in bytes. Maximum: 262144 bytes. When a transfer
      is stopped by the Stop_Transfer bit, this register give the number of
      remainder bytes to transfer.</comment>
        </bits>
      </reg>
      <reg name="pattern" protect="rw">
        <bits access="rw" name="pattern" pos="31:0" rst="0xFFFFFFFF">
          <comment>Value taken to fill the memory when the configuration bit Use
      Pattern is set. When the pattern mode is used the destination address
      must be 32-bit aligned and the transfer size multiple of 4. when
      Dst_Address_Mgt=10 Pattern is the data written at the address given by
      the Dst_Address register.</comment>
        </bits>
      </reg>
      <reg name="gea_kc_low" protect="rw">
        <bits access="rw" name="kc_lsb" pos="31:0" rst="0xFFFFFFFF">
          <comment>GEA key Kc, LSB bit [31:0].</comment>
        </bits>
      </reg>
      <reg name="gea_kc_high" protect="rw">
        <bits access="rw" name="kc_msb" pos="31:0" rst="0xFFFFFFFF">
          <comment>GEA key Kc, MSB bit [31:0].</comment>
        </bits>
      </reg>
      <reg name="gea_messkey" protect="rw">
        <bits access="rw" name="messkey" pos="31:0" rst="0xFFFFFFFF">
          <comment>MessKey (Input) register.</comment>
        </bits>
      </reg>
      <reg name="fcs" protect="r">
        <bits access="r" name="fcs" pos="23:0" rst="0">
          <comment>Frame Check Sequence.</comment>
        </bits>
        <bits access="r" name="fcs correct" pos="31" rst="0">
          <comment>The FCS is correct in reception when the final remainder is
      equal to C(x)= x^22 + x^21 + x^19 + x^18 + x^16 + x^15 + x^11 + x^8 +
      x^5 + x^4</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="nb_cell_search.xml">
    <module category="NBIOT_PHY" name="NB_CELL_SEARCH">
      <reg32 name="rpss_ctrl" protect="rw">
        <bits access="rw" name="rpss_en" pos="0" rst="0">
          <comment>PSS Enable
1b0: Stop PSS calculation
1b1: Start PSS calculation</comment>
        </bits>
        <bits access="rw" name="rpss_hypo_num" pos="3:1" rst="0">
          <comment>PSS hypothesis number</comment>
        </bits>
        <bits access="rw" name="rpss_out_buf_cfg" pos="4" rst="0">
          <comment>PSS output ping-pong buffer selection
1b1:Select the pong buffer as the first output buffer
1b0: Select the ping buffer as the first output buffer</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_start_os" protect="rw">
        <bits access="rw" name="rpss_start_sample_os" pos="10:0" rst="0">
          <comment>PSS start offset of sample within a sbuframe. Based on 1.92MHz. Range is from 0 to 1920.</comment>
        </bits>
        <bits access="rw" name="rpss_start_sf_os" pos="14:11" rst="0">
          <comment>PSS start offset of subframe. Range is from 0 to 9.</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_sf_cnt" protect="r">
        <bits access="r" name="rpss_sf_cnt" pos="3:0" rst="0">
          <comment>PSS internal sub frame counter(from 0 to 9)</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_out_status" protect="r">
        <bits access="r" name="rpss_obuf_sel" pos="0" rst="0">
          <comment>Indicate the buffer selection on current interrupt
1b0: buffer0 is selection
1b1: buffer1 is selection</comment>
        </bits>
        <bits access="w1c" name="rpss_obuf0_status_0" pos="1" rst="0">
          <comment>PSS output buffer 0 status. Clear by DSP or MCU
1b1: buffer 0 is ready.
1b0:buffer0 is idle</comment>
        </bits>
        <bits access="r" name="rpss_obuf0_status_1" pos="2" rst="0">
          <comment>PSS output buffer 0 status.
1b1: buffer 0 is over written.
1b0: buffer 0 is normal</comment>
        </bits>
        <bits access="w1c" name="rpss_obuf1_status_0" pos="3" rst="0">
          <comment>PSS output buffer 1 status. Clear by DSP or MCU
1b1: buffer 1 is ready.
1b0:buffer 1 is idle</comment>
        </bits>
        <bits access="r" name="rpss_obuf1_status_1" pos="4" rst="0">
          <comment>PSS output buffer 1 status.
1b1: buffer 1 is over written.
1b0: buffer 1 is normal</comment>
        </bits>
        <bits access="w1c" name="rpss_done_status" pos="5" rst="0">
          <comment>PSS calculation done status. Update very 1ms and clear by DSP or MCU.
1b1: PSS calculation done
1b0: PSS is idle or under calculating</comment>
        </bits>
        <bits access="r" name="rpss_mem_arb_status" pos="7:6" rst="0">
          <comment>PSS write memory arbitration error status.
1b1: the memory has conflict
1b0: the memory is normal</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_non_zero_status" protect="r">
        <bits access="r" name="rpss_non_zero_status" pos="8:0" rst="0">
          <comment>bit8: pss final output data non-zero status
bit7: pss 148x40 memory out data non-zero status
bit6: pss 148x40 memory in data non-zero status
bit5: pss power non-zero status
bit4: pss 1312x24 memory out data non-zero status
bit3: pss 1312x24 memory in data non-zero status
bit2: pss in local sequence non-zero status
bit1: pss_corr_calc in data non-zero status
bit0: pss_deci in data non-zero status</comment>
        </bits>
      </reg32>
      <hole size="3*32"/>
      <reg32 name="rpss_sample_pos_pu0" protect="rw">
        <bits access="rw" name="rpss_sample_pos_pu_0" pos="4:0" rst="0">
          <comment>PSS sample position for Pu of hypothesis 0</comment>
        </bits>
        <bits access="rw" name="rpss_sample_pos_pu_1" pos="12:8" rst="0">
          <comment>PSS sample position for Pu of hypothesis 1</comment>
        </bits>
        <bits access="rw" name="rpss_sample_pos_pu_2" pos="20:16" rst="0">
          <comment>PSS sample position for Pu of hypothesis 2</comment>
        </bits>
        <bits access="rw" name="rpss_sample_pos_pu_3" pos="28:24" rst="0">
          <comment>PSS sample position for Pu of hypothesis 3</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_sample_pos_pu1" protect="rw">
        <bits access="rw" name="rpss_sample_pos_pu_4" pos="4:0" rst="0">
          <comment>PSS sample position for Pu of hypothesis 0</comment>
        </bits>
        <bits access="rw" name="rpss_sample_pos_pu_5" pos="12:8" rst="0">
          <comment>PSS sample position for Pu of hypothesis 1</comment>
        </bits>
        <bits access="rw" name="rpss_sample_pos_pu_6" pos="20:16" rst="0">
          <comment>PSS sample position for Pu of hypothesis 2</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_sample_pos_pl0" protect="rw">
        <bits access="rw" name="rpss_sample_pos_pl_0" pos="4:0" rst="0">
          <comment>PSS sample position for Pl of hypothesis 0</comment>
        </bits>
        <bits access="rw" name="rpss_sample_pos_pl_1" pos="12:8" rst="0">
          <comment>PSS sample position for Pl of hypothesis 1</comment>
        </bits>
        <bits access="rw" name="rpss_sample_pos_pl_2" pos="20:16" rst="0">
          <comment>PSS sample position for Pl of hypothesis 2</comment>
        </bits>
        <bits access="rw" name="rpss_sample_pos_pl_3" pos="28:24" rst="0">
          <comment>PSS sample position for Pl of hypothesis 3</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_sample_pos_pl1" protect="rw">
        <bits access="rw" name="rpss_sample_pos_pl_4" pos="4:0" rst="0">
          <comment>PSS sample position for Pl of hypothesis 4</comment>
        </bits>
        <bits access="rw" name="rpss_sample_pos_pl_5" pos="12:8" rst="0">
          <comment>PSS sample position for Pl of hypothesis 5</comment>
        </bits>
        <bits access="rw" name="rpss_sample_pos_pl_6" pos="20:16" rst="0">
          <comment>PSS sample position for Pl of hypothesis 6</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_coeff00" protect="rw">
        <bits access="rw" name="rpss_coef_set0_0" pos="7:0" rst="0">
          <comment>PSS set 0 coefficient for hypothesis 0</comment>
        </bits>
        <bits access="rw" name="rpss_coef_set0_1" pos="15:8" rst="0">
          <comment>PSS set 0 coefficient for hypothesis 1</comment>
        </bits>
        <bits access="rw" name="rpss_coef_set0_2" pos="23:16" rst="0">
          <comment>PSS set 0 coefficient for hypothesis 2</comment>
        </bits>
        <bits access="rw" name="rpss_coef_set0_3" pos="31:24" rst="0">
          <comment>PSS set 0 coefficient for hypothesis 3</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_coeff01" protect="rw">
        <bits access="rw" name="rpss_coef_set0_4" pos="7:0" rst="0">
          <comment>PSS set 0 coefficient for hypothesis 4</comment>
        </bits>
        <bits access="rw" name="rpss_coef_set0_5" pos="15:8" rst="0">
          <comment>PSS set 0 coefficient for hypothesis 5</comment>
        </bits>
        <bits access="rw" name="rpss_coef_set0_6" pos="23:16" rst="0">
          <comment>PSS set 0 coefficient for hypothesis 7</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_coeff10" protect="rw">
        <bits access="rw" name="rpss_coef_set1_0" pos="7:0" rst="0">
          <comment>PSS set 1 coefficient for hypothesis 0</comment>
        </bits>
        <bits access="rw" name="rpss_coef_set1_1" pos="15:8" rst="0">
          <comment>PSS set 1 coefficient for hypothesis 1</comment>
        </bits>
        <bits access="rw" name="rpss_coef_set1_2" pos="23:16" rst="0">
          <comment>PSS set 0 coefficient for hypothesis 2</comment>
        </bits>
        <bits access="rw" name="rpss_coef_set1_3" pos="31:24" rst="0">
          <comment>PSS set 0 coefficient for hypothesis 3</comment>
        </bits>
      </reg32>
      <reg32 name="rpss_coeff11" protect="rw">
        <bits access="rw" name="rpss_coef_set1_4" pos="7:0" rst="0">
          <comment>PSS set 1 coefficient for hypothesis 4</comment>
        </bits>
        <bits access="rw" name="rpss_coef_set1_5" pos="15:8" rst="0">
          <comment>PSS set 1 coefficient for hypothesis 5</comment>
        </bits>
        <bits access="rw" name="rpss_coef_set1_6" pos="23:16" rst="0">
          <comment>PSS set 0 coefficient for hypothesis 6</comment>
        </bits>
      </reg32>
      <hole size="8*32"/>
      <struct count="17" name="pss_seq0_group">
        <reg32 name="rpss_local_seq0" protect="w">
          <bits access="w" name="rpss_local_seq0_re" pos="11:0" rst="0">
            <comment>Real part of the local sequence 0</comment>
          </bits>
          <bits access="w" name="rpss_local_seq0_im" pos="27:16" rst="0">
            <comment>Imag part of the local sequence 0</comment>
          </bits>
        </reg32>
      </struct>
      <struct count="17" name="pss_seq1_group">
        <reg32 name="rpss_local_seq1" protect="w">
          <bits access="w" name="rpss_local_seq1_re" pos="11:0" rst="0">
            <comment>Real part of the local sequence 1</comment>
          </bits>
          <bits access="w" name="rpss_local_seq1_im" pos="27:16" rst="0">
            <comment>Imag part of the local sequence 1</comment>
          </bits>
        </reg32>
      </struct>
      <struct count="17" name="pss_seq2_group">
        <reg32 name="rpss_local_seq2" protect="w">
          <bits access="w" name="rpss_local_seq2_re" pos="11:0" rst="0">
            <comment>Real part of the local sequence 2</comment>
          </bits>
          <bits access="w" name="rpss_local_seq2_im" pos="27:16" rst="0">
            <comment>Imag part of the local sequence 2</comment>
          </bits>
        </reg32>
      </struct>
      <struct count="17" name="pss_seq3_group">
        <reg32 name="rpss_local_seq3" protect="w">
          <bits access="w" name="rpss_local_seq3_re" pos="11:0" rst="0">
            <comment>Real part of the local sequence 3</comment>
          </bits>
          <bits access="w" name="rpss_local_seq3_im" pos="27:16" rst="0">
            <comment>Imag part of the local sequence 3</comment>
          </bits>
        </reg32>
      </struct>
      <struct count="17" name="pss_seq4_group">
        <reg32 name="rpss_local_seq4" protect="w">
          <bits access="w" name="rpss_local_seq4_re" pos="11:0" rst="0">
            <comment>Real part of the local sequence 4</comment>
          </bits>
          <bits access="w" name="rpss_local_seq4_im" pos="27:16" rst="0">
            <comment>Imag part of the local sequence 4</comment>
          </bits>
        </reg32>
      </struct>
      <struct count="17" name="pss_seq5_group">
        <reg32 name="rpss_local_seq5" protect="w">
          <bits access="w" name="rpss_local_seq5_re" pos="11:0" rst="0">
            <comment>Real part of the local sequence 5</comment>
          </bits>
          <bits access="w" name="rpss_local_seq5_im" pos="27:16" rst="0">
            <comment>Imag part of the local sequence 5</comment>
          </bits>
        </reg32>
      </struct>
      <struct count="17" name="pss_seq6_group">
        <reg32 name="rpss_local_seq6" protect="w">
          <bits access="w" name="rpss_local_seq6_re" pos="11:0" rst="0">
            <comment>Real part of the local sequence 6</comment>
          </bits>
          <bits access="w" name="rpss_local_seq6_im" pos="27:16" rst="0">
            <comment>Imag part of the local sequence 6</comment>
          </bits>
        </reg32>
      </struct>
      <hole size="369*32"/>
      <reg32 name="rcfo_start" protect="w">
        <bits access="w" name="rcfo_start" pos="0" rst="0">
          <comment>Start trigger of one CFO calculation process by writing 1 to this register</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_start_os" protect="rw">
        <bits access="rw" name="rcfo_start_sample_os" pos="10:0" rst="0">
          <comment>CFO data capture start offset of samples within a sub-frame. Based on 1.92MHz. Range is from 0 to 1920.</comment>
        </bits>
        <bits access="rw" name="rcfo_start_sf_os" pos="14:11" rst="0">
          <comment>CFO data capture start offset of sub-frame. Range is from 0 to 13.</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_calc_os" protect="rw">
        <bits access="rw" name="rcfo_calc_sample_os" pos="10:0" rst="0">
          <comment>CFO calculation start offset of samples within a sub-frame. Based on 1.92MHz. Range is from 0 to 1920.</comment>
        </bits>
        <bits access="rw" name="rcfo_calc_sf_os" pos="14:11" rst="0">
          <comment>CFO calculation start offset of sub-frame. Range is from 0 to 13.</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_ctrl" protect="rw">
        <bits access="rw" name="rcfo_fn_num" pos="2:0" rst="0">
          <comment>Rotated frequency bin number when rCFO_MODE=0.</comment>
        </bits>
        <bits access="rw" name="rcfo_mode" pos="3" rst="0">
          <comment>1: Normal mode. CFO module only deal with 1 frequency bin(f0) and 9 sampling positions(Tau). 147 correlation results are reported to corresponding ram at most.
0: Searching mode. CFO module deal with 1~7 frequency bins(f0~6) and 21 sampling positions(Tau). 9 correlation results are reported to corresponding registers.</comment>
        </bits>
        <bits access="rw" name="rcfo_rpt_addr" pos="13:4" rst="0">
          <comment>Start write address of CFO correlation results reporting ram</comment>
        </bits>
        <bits access="rw" name="rcfo_gain" pos="16:14" rst="0">
          <comment>Correlation results truncation (32bits to 16bits).
0:&gt;&gt;8    1:&gt;&gt;7    2:&gt;&gt;6    3:&gt;&gt;5
4:&gt;&gt;4    5:&gt;&gt;3    6:&gt;&gt;2    7:&gt;&gt;1</comment>
        </bits>
        <bits access="rw" name="rcfo_tau_num" pos="21:17" rst="0">
          <comment>Tau number of CFO correlation when rCFO_MODE=0.</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_os_f0to3" protect="rw">
        <bits access="rw" name="rcfo_os_f0" pos="7:0" rst="0">
          <comment>Sampling position start offset for bin f0</comment>
        </bits>
        <bits access="rw" name="rcfo_os_f1" pos="15:8" rst="0">
          <comment>Sampling position start offset for bin f1</comment>
        </bits>
        <bits access="rw" name="rcfo_os_f2" pos="23:16" rst="0">
          <comment>Sampling position start offset for bin f2</comment>
        </bits>
        <bits access="rw" name="rcfo_os_f3" pos="31:24" rst="0">
          <comment>Sampling position start offset for bin f3</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_os_f4to6" protect="rw">
        <bits access="rw" name="rcfo_os_f4" pos="7:0" rst="0">
          <comment>Sampling position start offset for bin f4</comment>
        </bits>
        <bits access="rw" name="rcfo_os_f5" pos="15:8" rst="0">
          <comment>Sampling position start offset for bin f5</comment>
        </bits>
        <bits access="rw" name="rcfo_os_f6" pos="23:16" rst="0">
          <comment>Sampling position start offset for bin f6</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_a_f0" protect="rw">
        <bits access="rw" name="rcfo_a_f0" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_a_f1" protect="rw">
        <bits access="rw" name="rcfo_a_f1" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_a_f2" protect="rw">
        <bits access="rw" name="rcfo_a_f2" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_a_f3" protect="rw">
        <bits access="rw" name="rcfo_a_f3" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_a_f4" protect="rw">
        <bits access="rw" name="rcfo_a_f4" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_a_f5" protect="rw">
        <bits access="rw" name="rcfo_a_f5" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_a_f6" protect="rw">
        <bits access="rw" name="rcfo_a_f6" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_b_f0" protect="rw">
        <bits access="rw" name="rcfo_b_f0" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_b_f1" protect="rw">
        <bits access="rw" name="rcfo_b_f1" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_b_f2" protect="rw">
        <bits access="rw" name="rcfo_b_f2" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_b_f3" protect="rw">
        <bits access="rw" name="rcfo_b_f3" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_b_f4" protect="rw">
        <bits access="rw" name="rcfo_b_f4" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_b_f5" protect="rw">
        <bits access="rw" name="rcfo_b_f5" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_b_f6" protect="rw">
        <bits access="rw" name="rcfo_b_f6" pos="31:0" rst="0">
          <comment>The complex value of  e^(-j2xpixf0xTsa). Tsa means decimation with 8.
[31:16]:Imag part
[15:0]: Real part</comment>
        </bits>
      </reg32>
      <hole size="4*32"/>
      <reg32 name="rcfo_status" protect="r">
        <bits access="w1c" name="rcfo_done_status" pos="0" rst="0">
          <comment>CFO calculation done status. Clear by DSP or MCU.
1b1: CFO calculation done
1b0: CFO is idle or under calculating</comment>
        </bits>
        <bits access="r" name="rcfo_wram_err" pos="2:1" rst="0">
          <comment>Memory request error for writing of CFO reporting ram when rCFO_MOED=0
0: Normal
1: Error
Bit 2: DSP control bus error
Bit 1: accelerator memory access collusion</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_corr0" protect="r">
        <bits access="r" name="rcfo_corr0" pos="0" rst="0">
          <comment>When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -4 is reported
[31:16]: imag part
[15:0]: real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_corr1" protect="r">
        <bits access="r" name="rcfo_corr1" pos="0" rst="0">
          <comment>When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -3 is reported
[31:16]: imag part
[15:0]: real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_corr2" protect="r">
        <bits access="r" name="rcfo_corr2" pos="0" rst="0">
          <comment>When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -2 is reported
[31:16]: imag part
[15:0]: real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_corr3" protect="r">
        <bits access="r" name="rcfo_corr3" pos="0" rst="0">
          <comment>When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -1 is reported
[31:16]: imag part
[15:0]: real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_corr4" protect="r">
        <bits access="r" name="rcfo_corr4" pos="0" rst="0">
          <comment>When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = 0 is reported
[31:16]: imag part
[15:0]: real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_corr5" protect="r">
        <bits access="r" name="rcfo_corr5" pos="0" rst="0">
          <comment>When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +1 is reported
[31:16]: imag part
[15:0]: real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_corr6" protect="r">
        <bits access="r" name="rcfo_corr6" pos="0" rst="0">
          <comment>When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +2 is reported
[31:16]: imag part
[15:0]: real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_corr7" protect="r">
        <bits access="r" name="rcfo_corr7" pos="0" rst="0">
          <comment>When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +3 is reported
[31:16]: imag part
[15:0]: real part</comment>
        </bits>
      </reg32>
      <reg32 name="rcfo_corr8" protect="r">
        <bits access="r" name="rcfo_corr8" pos="0" rst="0">
          <comment>When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +4 is reported
[31:16]: imag part
[15:0]: real part</comment>
        </bits>
      </reg32>
      <hole size="30*32"/>
      <reg32 name="rsss_en" protect="rw">
        <bits access="rw" name="rsss_en" pos="0" rst="0">
          <comment>SSS Enable
1b0:Stop SSS calculation
1b1: Start SSS calculation</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_start_os" protect="rw">
        <bits access="rw" name="rsss_start_sample_os" pos="10:0" rst="0">
          <comment>SSS start offset of sample within a sbuframe. Based on 1.92MHz. Range is from 0 to 1920.</comment>
        </bits>
        <bits access="rw" name="rsss_start_sf_os" pos="14:11" rst="0">
          <comment>SSS start offset of subframe. Range is from 0 to 9.</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_start_calc_os" protect="rw">
        <bits access="rw" name="rsss_start_calc_sample_os" pos="10:0" rst="0">
          <comment>SSS start calculation offset of sample within a subframe. Based on 1.92MHz. Range is from 0 to 1920.</comment>
        </bits>
        <bits access="rw" name="rsss_start_calc_sf_os" pos="14:11" rst="0">
          <comment>SSS start calculation offset of subframe. Range is from 0 to 9.</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift0" protect="rw">
        <bits access="rw" name="rsss_phase_shift0_re" pos="11:0" rst="0">
          <comment>Real part of SSS phase shift</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift0_im" pos="27:16" rst="0">
          <comment>Imag part of SSS phase shift</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift1" protect="rw">
        <bits access="rw" name="rsss_phase_shift1_re" pos="15:0" rst="0">
          <comment>Real part of SSS phase shift 1</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift1_im" pos="31:16" rst="0">
          <comment>Imag part of SSS phase shift 1</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift2" protect="rw">
        <bits access="rw" name="rsss_phase_shift2_re" pos="15:0" rst="0">
          <comment>Real part of SSS phase shift 2</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift2_im" pos="31:16" rst="0">
          <comment>Imag part of SSS phase shift 2</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift3" protect="rw">
        <bits access="rw" name="rsss_phase_shift3_re" pos="15:0" rst="0">
          <comment>Real part of SSS phase shift 3</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift3_im" pos="31:16" rst="0">
          <comment>Imag part of SSS phase shift 3</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift4" protect="rw">
        <bits access="rw" name="rsss_phase_shift4_re" pos="15:0" rst="0">
          <comment>Real part of SSS phase shift 4</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift4_im" pos="31:16" rst="0">
          <comment>Imag part of SSS phase shift 4</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift5" protect="rw">
        <bits access="rw" name="rsss_phase_shift5_re" pos="15:0" rst="0">
          <comment>Real part of SSS phase shift 5</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift5_im" pos="31:16" rst="0">
          <comment>Imag part of SSS phase shift 5</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift6" protect="rw">
        <bits access="rw" name="rsss_phase_shift6_re" pos="15:0" rst="0">
          <comment>Real part of SSS phase shift 6</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift6_im" pos="31:16" rst="0">
          <comment>Imag part of SSS phase shift 6</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift7" protect="rw">
        <bits access="rw" name="rsss_phase_shift7_re" pos="15:0" rst="0">
          <comment>Real part of SSS phase shift 7</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift7_im" pos="31:16" rst="0">
          <comment>Imag part of SSS phase shift 7</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift8" protect="rw">
        <bits access="rw" name="rsss_phase_shift8_re" pos="15:0" rst="0">
          <comment>Real part of SSS phase shift 8</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift8_im" pos="31:16" rst="0">
          <comment>Imag part of SSS phase shift 8</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift9" protect="rw">
        <bits access="rw" name="rsss_phase_shift9_re" pos="15:0" rst="0">
          <comment>Real part of SSS phase shift 9</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift9_im" pos="31:16" rst="0">
          <comment>Imag part of SSS phase shift 9</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_phase_shift10" protect="rw">
        <bits access="rw" name="rsss_phase_shift10_re" pos="15:0" rst="0">
          <comment>Real part of SSS phase shift 10</comment>
        </bits>
        <bits access="rw" name="rsss_phase_shift10_im" pos="31:16" rst="0">
          <comment>Imag part of SSS phase shift 10</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_sf_cnt" protect="r">
        <bits access="r" name="rsss_sf_cnt" pos="3:0" rst="0">
          <comment>SSS internal sub frame counter(from 0 to 9)</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_glb_cnt" protect="r">
        <bits access="r" name="rsss_glb_sample_cnt" pos="10:0" rst="0">
          <comment>global sample count value at SSS subframe start</comment>
        </bits>
        <bits access="r" name="rsss_glb_sf_cnt" pos="14:11" rst="0">
          <comment>global subframe count value at SSS subframe start</comment>
        </bits>
        <bits access="r" name="rsss_glb_rf_cnt" pos="17:15" rst="0">
          <comment>Global radio frame count value at SSS subframe start</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_out_status" protect="r">
        <bits access="r" name="rsss_obuf_sel" pos="0" rst="0">
          <comment>Indicate the buffer selection on current interrupt
1b0: MEM0 is selection
1b1: MEM1 is selection</comment>
        </bits>
        <bits access="w1c" name="rsss_obuf0_status_0" pos="2" rst="0">
          <comment>SSS output buffer 0 status. Clear by DSP or MCU
bit 2: 1b1: MEM2 or MEM0  is ready.1b0:buffer0 is idle</comment>
        </bits>
        <bits access="r" name="rsss_obuf0_status_1" pos="3" rst="0">
          <comment>SSS output buffer 0 status.
bit 3: 1b1: MEM2 or MEM0  is over written. 1b0: buffer 0 is normal</comment>
        </bits>
        <bits access="w1c" name="rsss_obuf1_status_0" pos="4" rst="0">
          <comment>SSS output buffer 1 status. Clear by DSP or MCU
bit 4: 1b1: MEM3 or MEM1  is ready.1b0:buffer1 is idle</comment>
        </bits>
        <bits access="r" name="rsss_obuf1_status_1" pos="5" rst="0">
          <comment>SSS output buffer 1 status.
bit 5: 1b1: MEM3 or MEM1  is over written. 1b0: buffer 1 is normal</comment>
        </bits>
        <bits access="w1c" name="rsss_done_status" pos="6" rst="0">
          <comment>SSS calculation done status. Update very 1ms and clear by DSP or MCU.
1b1: SSS calculation done
1b0: SSS is idle or under calculating</comment>
        </bits>
        <bits access="r" name="rsss_mem_arb_status" pos="8:7" rst="0">
          <comment>SSS write memory arbitration error status.
0: Normal
1: Error
Bit 7: DSP control bus error
Bit 8: accelerator memory access collusion</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_fft_ctrl" protect="rw">
        <bits access="rw" name="rsss_fft_cp_os" pos="3:0" rst="0">
          <comment>OFDM symbol CP offset which use to locate the FFT windows start position for serving cell.
Value:[0:9]</comment>
        </bits>
        <bits access="rw" name="rsss_fft_scale" pos="6:4" rst="0">
          <comment>FFT result scaling
3d0: 2^-3
3d1: 2^-2
3d2: 2^-1
3d3: 2^0
3d4: 2^1
3d5: 2^2</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_corr_ctrl" protect="rw">
        <bits access="rw" name="rsss_corr_scal" pos="2:0" rst="5">
          <comment>Correlation result sScaling for both power and correlation
3d0: 20
3d1: 2-1
3d2: 2-2
3d3: 2-3
3d4: 2-4
3d5: 2-5(Default)
3d6: 2-6
3d7: 2-7</comment>
        </bits>
        <bits access="rw" name="rsss_cyclic_shift" pos="4:3" rst="0">
          <comment>Cyclic shift value
It is used when rSSS_CYCLIC_SHIFT_FIX_EN = 1'b1.Rang is from 0 to 2.</comment>
        </bits>
        <bits access="rw" name="rsss_cyclic_shift_fix_en" pos="5" rst="0">
          <comment>Fix cyclic shift enable</comment>
        </bits>
        <bits access="rw" name="rsss_pci_id" pos="14:6" rst="0">
          <comment>PCI ID
It is used when rSSS_PCI_ID_FIX_RN = 1'b1 or rSSS_SIC_EN = 1'b1. Range is from 0 to 503.</comment>
        </bits>
        <bits access="rw" name="rsss_pci_id_fix_en" pos="15" rst="0">
          <comment>Fix PCI ID Enable.</comment>
        </bits>
        <bits access="rw" name="rsss_sic_en" pos="17" rst="0">
          <comment>SIC Enable
Used for succesive interference cancellation.</comment>
        </bits>
        <bits access="rw" name="rsss_out_buf_cfg" pos="18" rst="0">
          <comment>SSS output ping-pong buffer selection
1b1:Select the pong buffer as the first output buffer
1b0: Select the ping buffer as the first output buffer</comment>
        </bits>
        <bits access="rw" name="rsss_corr_scal2" pos="21:19" rst="4">
          <comment>Scaling for correlation only
3d0: 2-4
3d1: 2-3
3d2: 2-2
3d3: 2-1
3d4: 20(Default)
3d5: 21
3d6: 22
3d7: 23</comment>
        </bits>
      </reg32>
      <reg32 name="rsss_pwr" protect="rw">
        <bits access="rw" name="rsss_pwr" pos="15:0" rst="0x0">
          <comment>SSS total power</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="nb_common.xml">
    <module category="NBIOT_PHY" name="NB_COMMON">
      <reg32 name="rrx_int_dsp_sym_bmp_msk" protect="rw">
        <bits access="rw" name="rrx_int_dsp_sym_bmp_msk" pos="13:0" rst="0x1">
          <comment>RX interrupt DSP bitmap mask from 0 to 13. LSB is symbol 0.</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_int_mcu_sym_bmp_msk" protect="rw">
        <bits access="rw" name="rrx_int_mcu_sym_bmp_msk" pos="13:0" rst="0x1">
          <comment>RX interrupt DSP bitmap mask from 0 to 13. LSB is symbol 0.</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_int_os" protect="rw">
        <bits access="rw" name="rrx_int_os" pos="6:0" rst="0x40">
          <comment>RX interrupt output OS 0  127</comment>
        </bits>
      </reg32>
      <hole size="5*32"/>
      <reg32 name="rrx_adj_cctrl" protect="rw">
        <bits access="rw" name="rrx_adj_sf_cnt" pos="3:0" rst="0">
          <comment>RX adjustment subframe count from 0  9 (auto clear in next subframe)</comment>
        </bits>
        <bits access="rw" name="rrx_adj_sym_cnt" pos="7:4" rst="0">
          <comment>RX adjustment symbol count from 0  13 (auto clear in next subframe)</comment>
        </bits>
        <bits access="rw" name="rrx_adj_sym_dir" pos="8" rst="0">
          <comment>RX adjustment symbol direction (auto clear in next subframe)
0: advance
1: postpone</comment>
        </bits>
        <bits access="rw" name="rrx_adj_csample_cnt" pos="23:16" rst="0">
          <comment>RX coarse adjustment sample count from 0  138 in (chip unit) - (auto clear in next subframe)</comment>
        </bits>
        <bits access="rw" name="rrx_adj_csample_dir" pos="24" rst="0">
          <comment>RX coarse adjustment sample direction (auto clear in next subframe)
0: advance
1: postpone</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_adj_fctrl" protect="rw">
        <bits access="rw" name="rrx_adj_fsample_cnt" pos="3:0" rst="0">
          <comment>RX fine adjustment sample count from 0  9 in (chip unit) -  (auto clear in next subframe)</comment>
        </bits>
        <bits access="rw" name="rrx_adj_fsample_dir" pos="4" rst="0">
          <comment>RX fine adjustment sample direction (auto clear in next subframe)
0: advance
1: postpone</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_int_pos_status_dsp" protect="r">
        <bits access="r" name="rrx_int_sym_dsp" pos="3:0" rst="0">
          <comment>RX interrupt symbol number 0-13</comment>
        </bits>
        <bits access="r" name="rrx_int_sf_dsp" pos="7:4" rst="0">
          <comment>RX interrupt symbol number 0-13</comment>
        </bits>
        <bits access="r" name="rrx_int_buf_idx_dsp" pos="8" rst="0">
          <comment>RX interrupt buffer index
Mirror rRX_INT_BUF_IDX_MCU register</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_int_pos_status_mcu" protect="r">
        <bits access="r" name="rrx_int_sym_mcu" pos="3:0" rst="0">
          <comment>RX interrupt symbol number 0-13</comment>
        </bits>
        <bits access="r" name="rrx_int_sf_mcu" pos="7:4" rst="0">
          <comment>RX interrupt symbol number 0-13</comment>
        </bits>
        <bits access="r" name="rrx_int_buf_idx_mcu" pos="8" rst="0">
          <comment>RX interrupt buffer index</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_sfn" protect="rw">
        <bits access="rw" name="rrx_sfn" pos="9:0" rst="0">
          <comment>RX SFN number 0-1023</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_glb_cnt_sf" protect="r">
        <bits access="r" name="rrx_glb_sample_cnt_sf" pos="10:0" rst="0">
          <comment>global sample count value at RX subframe start</comment>
        </bits>
        <bits access="r" name="rrx_glb_sf_cnt_sf" pos="14:11" rst="0">
          <comment>global subframe count value at RX subframe start</comment>
        </bits>
        <bits access="r" name="rrx_glb_rf_cnt_sf" pos="17:15" rst="0">
          <comment>global sample count value at RX subframe start</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_glb_cnt_rf" protect="r">
        <bits access="r" name="rrx_glb_sample_cnt_rf" pos="10:0" rst="0">
          <comment>global sample count value at RX radio frame start</comment>
        </bits>
        <bits access="r" name="rrx_glb_sf_cnt_rf" pos="14:11" rst="0">
          <comment>global subframe count value at RX radio frame start</comment>
        </bits>
        <bits access="r" name="rrx_glb_rf_cnt_rf" pos="17:15" rst="0">
          <comment>global sample count value at RX radio frame start</comment>
        </bits>
      </reg32>
      <reg32 name="rtcu_glb_cnt" protect="r">
        <bits access="r" name="rtcu_glb_sample_cnt" pos="10:0" rst="0">
          <comment>global sample count value at TCU subframe start</comment>
        </bits>
        <bits access="r" name="rtcu_glb_sf_cnt" pos="14:11" rst="0">
          <comment>global subframe count value at TCU subframe start</comment>
        </bits>
        <bits access="r" name="rtcu_glb_rf_cnt" pos="17:15" rst="0">
          <comment>global sample count value at TCU subframe start</comment>
        </bits>
      </reg32>
      <hole size="4*32"/>
      <reg32 name="rtx_adj_cctrl" protect="rw">
        <bits access="rw" name="rtx_adj_csample_cnt" pos="10:0" rst="0">
          <comment>TX coarse adjustment sample count from 0  1919 in (chip unit) - (auto clear in next subframe)</comment>
        </bits>
        <bits access="rw" name="rtx_adj_csample_dir" pos="11" rst="0">
          <comment>TX coarse adjustment sample direction - (auto clear in next subframe)
0: advance
1: postpone</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_adj_fctrl" protect="rw">
        <bits access="rw" name="rtx_adj_fsample_cnt" pos="5:0" rst="0">
          <comment>15KHz: TX fine adjustment sample count from 0  9 in (chip unit)
3.75Hz: TX fine adjustment sample count from (0  9) x 4 in (chip unit)
Remark: SW should configure the sample boundary which is aligned to 3.75Hz sample if the timing adjustment between TX transmission.
(auto clear in next subframe)</comment>
        </bits>
        <bits access="rw" name="rtx_adj_csample_dir" pos="6" rst="0">
          <comment>TX fine adjustment sample direction -  (auto clear in next subframe)
0: advance
1: postpone</comment>
        </bits>
        <bits access="rw" name="rtx_adj_fmode" pos="8" rst="0">
          <comment>TX fine adjustment mode control:
0: adjust the boundary at the end of the current subframe
1: adjust the CP at the first symbol of the next TX</comment>
        </bits>
      </reg32>
      <hole size="1*32"/>
      <reg32 name="rtx_glb_cnt_sf" protect="r">
        <bits access="r" name="rtx_glb_sample_cnt_sf" pos="10:0" rst="0">
          <comment>global sample count value at TX subframe start</comment>
        </bits>
        <bits access="r" name="rtx_glb_sf_cnt_sf" pos="14:11" rst="0">
          <comment>global subframe count value at TX subframe start</comment>
        </bits>
        <bits access="r" name="rtx_glb_rf_cnt_sf" pos="17:15" rst="0">
          <comment>global radio frame count value at TX subframe start</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_subsample_ctrl" protect="rw">
        <bits access="rw" name="rtx_subsample_ctrl" pos="0" rst="0">
          <comment>TX subsample control
0: sync with global subsample counter
1: only sync with RX subsample counter when TX is not on transmission</comment>
        </bits>
      </reg32>
      <reg32 name="rctrl_status" protect="rw">
        <bits access="w1c" name="rctrl_rx_cadj_status" pos="0" rst="0">
          <comment>Control RX coarse adjustment status</comment>
        </bits>
        <bits access="w1c" name="rctrl_rx_fadj_status" pos="1" rst="0">
          <comment>Control RX fine adjustment status</comment>
        </bits>
        <bits access="w1c" name="rctrl_tx_cadj_status" pos="2" rst="0">
          <comment>Control TX coarse adjustment status</comment>
        </bits>
        <bits access="w1c" name="rctrl_tx_fadj_status" pos="3" rst="0">
          <comment>Control TX fine adjustment status</comment>
        </bits>
      </reg32>
      <reg32 name="rctrl_adj_en" protect="rw">
        <bits access="rw" name="rctrl_adj_en" pos="0" rst="0">
          <comment>Control adjustment enable
1: enable
0: disable</comment>
        </bits>
      </reg32>
      <hole size="1*32"/>
      <reg32 name="capture1_glb_cnt" protect="w">
        <bits access="w" name="capture1_glb_cnt" pos="0" rst="0">
          <comment>Trigger to sample global counter position for DSP debegging</comment>
        </bits>
      </reg32>
      <reg32 name="rcapture1_glb_cnt" protect="r">
        <bits access="r" name="rcapture1_glb_cnt" pos="10:0" rst="0">
          <comment>global counter sample position when CAPTURE1_GLB_CNT is accessed</comment>
        </bits>
        <bits access="r" name="rcapture1_glb_sf_cnt" pos="14:11" rst="0">
          <comment>global counter subframe position when CAPTURE1_GLB_CNT is accessed</comment>
        </bits>
        <bits access="r" name="rcapture1_glb_rf_cnt" pos="17:15" rst="0">
          <comment>global counter radio frame position when CAPTURE1_GLB_CNT is accessed</comment>
        </bits>
      </reg32>
      <reg32 name="capture2_glb_cnt" protect="w">
        <bits access="w" name="capture2_glb_cnt" pos="0" rst="0">
          <comment>Trigger to sample global counter position for MCU debegging</comment>
        </bits>
      </reg32>
      <reg32 name="rcapture2_glb_cnt" protect="r">
        <bits access="r" name="rcapture2_glb_cnt" pos="10:0" rst="0">
          <comment>global counter sample position when CAPTURE2_GLB_CNT is accessed</comment>
        </bits>
        <bits access="r" name="rcapture2_glb_sf_cnt" pos="14:11" rst="0">
          <comment>global counter subframe position when CAPTURE2_GLB_CNT is accessed</comment>
        </bits>
        <bits access="r" name="rcapture2_glb_rf_cnt" pos="17:15" rst="0">
          <comment>global counter radio frame position when CAPTURE2_GLB_CNT is accessed</comment>
        </bits>
      </reg32>
      <reg32 name="sleep_w" protect="w">
        <bits access="w" name="sleep_w" pos="0" rst="0">
          <comment>For sleep operation
When SLEEP_W is accessed, the start values needed for wake-up are loaded. Then values have to be written before the SLEEP_W is accessed</comment>
        </bits>
      </reg32>
      <reg32 name="rsleep_glb_cnt" protect="rw">
        <bits access="r" name="rglb_sub_sample_cnt" pos="4:0" rst="0">
          <comment>Sample clock/32 (TX/RX sub-sample is always aligned with Global sub-sample) : this would use for alignment of the DFE input valid.
0-31</comment>
        </bits>
        <bits access="rw" name="rglb_sample_cnt" pos="15:5" rst="0">
          <comment>global counter sample position in sleep mode (in chip unit)</comment>
        </bits>
        <bits access="rw" name="rglb_sf_cnt" pos="19:16" rst="0">
          <comment>global counter subframe position</comment>
        </bits>
        <bits access="rw" name="rglb_rf_cnt" pos="22:20" rst="0">
          <comment>global counter radio frame position</comment>
        </bits>
      </reg32>
      <reg32 name="rsleep_rx/tx_cnt" protect="rw">
        <bits access="rw" name="rtx_sample_cnt" pos="10:0" rst="0">
          <comment>Sample clock/32 (TX/RX sub-sample is always aligned with Global sub-sample) : this would use for align the DFE input valid.
0-31</comment>
        </bits>
        <bits access="rw" name="rrx_sample_cnt" pos="23:16" rst="0">
          <comment>RX sample count value</comment>
        </bits>
        <bits access="rw" name="rrx_sym_cnt" pos="27:24" rst="0">
          <comment>RX OFDM symbol count value</comment>
        </bits>
        <bits access="rw" name="rrx_sf_cnt" pos="31:28" rst="0">
          <comment>RX subframe count value</comment>
        </bits>
      </reg32>
      <reg32 name="rsleep_elapsed_cnt" protect="ro">
        <bits access="ro" name="rsleep_elapsed_subsample_cnt" pos="4:0" rst="0">
          <comment>Sleep Elapsed Subsample counter
Range: 0-31</comment>
        </bits>
        <bits access="ro" name="rsleep_elapsed_sample_cnt" pos="18:8" rst="0">
          <comment>Sleep Elapsed Subsample counter
Range: 0-1919</comment>
        </bits>
      </reg32>
      <reg32 name="rsleep_elapsed_sf_cnt" protect="ro">
        <bits access="ro" name="rsleep_elapsed_sf_cnt" pos="31:0" rst="0">
          <comment>Sleep Elapsed SF counter
Range: 0-2^32-1</comment>
        </bits>
      </reg32>
      <hole size="27*32"/>
      <reg32 name="rtcu_event_trig" protect="rw">
        <bits access="rw" name="rtcu_event_sample_time" pos="15:5" rst="0">
          <comment>TCU event subsample time</comment>
        </bits>
        <bits access="rw" name="rtcu_event_sf_time" pos="19:16" rst="0">
          <comment>TCU event subframe time</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_sync_mode" protect="rw">
        <bits access="rw" name="rrx_sync_mode" pos="0" rst="0">
          <comment>RX synchronization method mode
0: normal mode
1: sync counter with input i_rx_sync_start pulse in DUMP mode only (For testing only)</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_sync_init_1" protect="rw">
        <bits access="rw" name="rrx_sf_sync_init_1" pos="3:0" rst="0x9">
          <comment>RX subframe count sync initialization value - 1</comment>
        </bits>
        <bits access="rw" name="rglb_sf_sync_init_1" pos="11:8" rst="0x9">
          <comment>Global subframe count sync initialization value - 1</comment>
        </bits>
        <bits access="rw" name="rglb_rf_sync_init_1" pos="14:12" rst="0x7">
          <comment>Global radio frame count sync initialization value - 1</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_capture_event_trig" protect="rw">
        <bits access="rw" name="rrx_capture_sample_time" pos="15:5" rst="0">
          <comment>RX Capture event sample time</comment>
        </bits>
        <bits access="rw" name="rrx_capture_sf_time" pos="19:16" rst="0">
          <comment>RX Capture event subframe time</comment>
        </bits>
      </reg32>
      <hole size="60*32"/>
      <reg32 name="rdsp_mem0_ctrl" protect="rw">
        <bits access="rw" name="rdsp_mem0_ctrl" pos="1:0" rst="0">
          <comment>DSP memory 0 control
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
        </bits>
      </reg32>
      <reg32 name="rdsp_mem1_ctrl" protect="rw">
        <bits access="rw" name="rdsp_mem1_ctrl" pos="1:0" rst="0">
          <comment>DSP memory 1 control
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
        </bits>
      </reg32>
      <reg32 name="rdsp_mem2_ctrl" protect="rw">
        <bits access="rw" name="rdsp_mem2_ctrl" pos="1:0" rst="0">
          <comment>DSP memory 2 control
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
        </bits>
      </reg32>
      <reg32 name="rdsp_mem3_ctrl" protect="rw">
        <bits access="rw" name="rdsp_mem3_ctrl" pos="1:0" rst="0">
          <comment>DSP memory 3 control
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
        </bits>
      </reg32>
      <reg32 name="rdsp_mem4_ctrl" protect="rw">
        <bits access="rw" name="rdsp_mem4_ctrl" pos="1:0" rst="0">
          <comment>DSP memory 4 control
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
        </bits>
      </reg32>
      <reg32 name="rdsp_mem5_ctrl" protect="rw">
        <bits access="rw" name="rdsp_mem5_ctrl" pos="1:0" rst="0">
          <comment>DSP memory 5 control
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
        </bits>
      </reg32>
      <hole size="1*32"/>
      <reg32 name="rdsp_mem7_ctrl" protect="rw">
        <bits access="rw" name="rdsp_mem7_ctrl" pos="1:0" rst="0">
          <comment>DSP memory 7 control
00: HW control with NB core clock
10: HW control with AHB clock
11: DSP control with AHB clock</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="nb_ctrl.xml">
    <module category="NBIOT_PHY" name="NB_CTRL">
      <reg32 name="rnbiot_sw_rst" protect="w">
        <bits access="w" name="rrx_fft_sw_rst" pos="0" rst="0">
          <comment>RX FFT sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rrx_pss_sw_rst" pos="1" rst="0">
          <comment>RX Cell Search PSS sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rrx_sss_sw_rst" pos="2" rst="0">
          <comment>RX Cell Search SSS sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rrx_cfo_sw_rst" pos="3" rst="0">
          <comment>RX CFO sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rrx_vit_sw_rst" pos="4" rst="0">
          <comment>RX Viterbi sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rrx_agc_sw_rst" pos="5" rst="0">
          <comment>RX AGC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rds_bsel_sw_rst" pos="6" rst="0">
          <comment>RX DS_BSEL sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rtx_frontend_sw_rst" pos="7" rst="0">
          <comment>TX frontend sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rpusch_enc_sw_rst" pos="8" rst="0">
          <comment>PUSCH encoder sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rtx_chsc_sw_rst" pos="9" rst="0">
          <comment>TX CHSC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rfft_512_sw_rst" pos="10" rst="0">
          <comment>FFT 512 sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rnprs_acc1_sw_rst" pos="11" rst="0">
          <comment>NPRS acc1 sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rfine_ifft_sw_rst" pos="12" rst="0">
          <comment>FINE_IFFT sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rnbiot_sw_rst" pos="13" rst="0">
          <comment>rNBIOT general part reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
        <bits access="w" name="rnbiot_rsrp_rst" pos="14" rst="0">
          <comment>NC_RSRP sub-module reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
      </reg32>
      <reg32 name="rnbiot_clk_en" protect="rw">
        <bits access="rw" name="rrx_fft_clk_en" pos="0" rst="0">
          <comment>Enable/disable the clock for RX FFT/RSRP module
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rrx_pss_clk_en" pos="1" rst="0">
          <comment>Enable/disable the clock for RX Cell Search module PSS
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rrx_sss_clk_en" pos="2" rst="0">
          <comment>Enable/disable the clock for RX Cell Search module SSS
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rrx_cfo_clk_en" pos="3" rst="0">
          <comment>Enable/disable the clock for RX CFO module
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rrx_vit_clk_en" pos="4" rst="0">
          <comment>Enable/disable the clock for RX Viterbi module
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rrx_agc_clk_en" pos="5" rst="0">
          <comment>Enable/disable the clock for RX AGC module
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rds_bsel_clk_en" pos="6" rst="0">
          <comment>Enable/disable the clock for DS_BSEL module
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rtx_frontend_clk_en" pos="7" rst="0">
          <comment>Enable/disable the clock for TX Frontend module.
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rpusch_enc_clk_en" pos="8" rst="0">
          <comment>Enable/disable the clock for PUSCH encoder module.
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rtx_chsc_clk_en" pos="9" rst="0">
          <comment>Enable/disable the clock for TX TX channel-interleaver and scrambling module.
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rfft_512_clk_en" pos="10" rst="0">
          <comment>Enable/disable the clock for FFT 512 module.
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rnprs_acc1_clk_en" pos="11" rst="0">
          <comment>Enable/disable the clock for NPRS ACC1 module.
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rfine_fft_clk_en" pos="12" rst="0">
          <comment>Enable/disable the clock for FINE ifft module
0: clock disabled
1: clock enabled.</comment>
        </bits>
        <bits access="rw" name="rnbiot_clk_en" pos="13" rst="0">
          <comment>Enable/disable the clock for NBIOT module
0: clock disabled
1: clock enabled.</comment>
        </bits>
      </reg32>
      <reg32 name="rnbiot_monitor" protect="rw">
        <bits access="rw" name="rnbiot_monitor_sel" pos="7:0" rst="0">
          <comment>Debug signal selection</comment>
        </bits>
        <bits access="rw" name="rnbiot_monitor_en" pos="8" rst="0">
          <comment>Debug signal output enable</comment>
        </bits>
      </reg32>
      <reg32 name="rnbiot_rfin_sw_rst" protect="w">
        <bits access="w" name="rnbiot_rfin_sw_rst" pos="0" rst="0">
          <comment>RFIN reset by DSP, it is used to re-timing the global timer to balance the timing of IQ data input from DFE in sample boundary. Write 1 and auto-clear by HW.
0: default value
1: reset to re-timing the sample boundary in global timer.</comment>
        </bits>
      </reg32>
      <reg32 name="rnbiot_rfin_status" protect="r">
        <bits access="r" name="rnbiot_rfin_subsmaple_cnt" pos="12:8" rst="0">
          <comment>Sample the glb_subsample_cnt with input rx_data_vld to check the phase change of the input</comment>
        </bits>
        <bits access="r" name="rnbiot_rfin_status_err" pos="0" rst="0">
          <comment>Keep track the RFIN data strobe in valid window.
0: Normal
1: Error</comment>
        </bits>
      </reg32>
      <reg32 name="rnbiot_coarse_clk_gating" protect="rw">
        <bits access="rw" name="rpss_cos_clk_gating" pos="1" rst="0">
          <comment>PSS Correlator coarse clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module PSS Correlator.</comment>
        </bits>
        <bits access="rw" name="rsss_cos_clk_gating" pos="2" rst="0">
          <comment>SSS Correlator coarse clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module SSS Correlator.</comment>
        </bits>
      </reg32>
      <reg32 name="rnbiot_fine_clk_gating" protect="rw">
        <bits access="rw" name="rfft_rsrp_ft_clk_gating" pos="0" rst="0">
          <comment>FFT_RSRP fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module FFT_RSRP.</comment>
        </bits>
        <bits access="rw" name="rpss_ft_clk_gating" pos="1" rst="0">
          <comment>PSS Correlator fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module PSS Correlator.</comment>
        </bits>
        <bits access="rw" name="rsss_ft_clk_gating" pos="2" rst="0">
          <comment>SSS Correlator fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module SSS Correlator.</comment>
        </bits>
        <bits access="rw" name="rcfo_ft_clk_gating" pos="3" rst="0">
          <comment>CFO Correlator fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module CFO Correlator.</comment>
        </bits>
        <bits access="rw" name="rvit_ft_clk_gating" pos="4" rst="0">
          <comment>Viterbi fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module Viterbi.</comment>
        </bits>
        <bits access="rw" name="ragc_ft_clk_gating" pos="5" rst="0">
          <comment>AGC fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module AGC.</comment>
        </bits>
        <bits access="rw" name="rds_bsel_ft_clk_gating" pos="6" rst="0">
          <comment>DS_BSEL fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module DS_BSEL.</comment>
        </bits>
        <bits access="rw" name="rtx_frontend_ft_clk_gating" pos="7" rst="0">
          <comment>TX_FRONTEND fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module TX_FRONTEND.</comment>
        </bits>
        <bits access="rw" name="rpusch_enc_clk_gating" pos="8" rst="0">
          <comment>PUSCH_ENC fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module PUSCH_ENC.</comment>
        </bits>
        <bits access="rw" name="rtx_chsc_clk_gating" pos="9" rst="0">
          <comment>TX_CHSC fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module TX_CHSC.</comment>
        </bits>
        <bits access="rw" name="rfft_512_clk_gating" pos="10" rst="0">
          <comment>FFT 512 fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module FFT 512.</comment>
        </bits>
        <bits access="rw" name="rnprs_acc1_clk_gating" pos="11" rst="0">
          <comment>NPRS ACC1 fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module NPRS ACC1.</comment>
        </bits>
        <bits access="rw" name="rfine_ifft_clk_gating" pos="12" rst="0">
          <comment>FIne IFFT fine clock gating,
0: free running
1: clock gated by the clock enabled signal which generated from sub-module FINE_IFFT.</comment>
        </bits>
      </reg32>
      <reg32 name="rapb_sw_rst" protect="w">
        <bits access="w" name="rapb_sw_rst" pos="0" rst="0">
          <comment>NBIOT CORE APB domain reset by software, auto-clear to zero when write 1 to this register by DSP
0: default value;
1: Reset whole sub-module.</comment>
        </bits>
      </reg32>
      <reg32 name="rnbiot_debug_gpo" protect="rw">
        <bits access="rw" name="rnbiot_debuf_gpo" pos="3:0" rst="0">
          <comment>Debug General Purpose Output
Remark: need to set rNBIOT_MONITOR to 0x1a3</comment>
        </bits>
      </reg32>
      <hole size="55*32"/>
      <reg32 name="rnbiot_revision" protect="r">
        <bits access="r" name="rminor_rev" pos="7:0" rst="0">
          <comment>Minor Revision</comment>
        </bits>
        <bits access="r" name="rmajor_rev" pos="15:8" rst="0">
          <comment>MAJOR Revision</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="nb_ds_bsel.xml">
    <module category="NBIOT_PHY" name="NB_DS_BSEL">
      <reg32 name="rds_bsel_start" protect="w1c">
        <bits access="w1c" name="rds_bsel_start" pos="0" rst="0x0">
          <comment>DS_BSEL accelerator start</comment>
        </bits>
      </reg32>
      <reg32 name="rds_bsel_ctrl" protect="rw">
        <bits access="rw" name="rtimeout_val" pos="15:0" rst="0x7fff">
          <comment>Maximum time out value for TX bit level processing in 61.44Mhz unit</comment>
        </bits>
        <bits access="rw" name="rnum_candidate" pos="17:16" rst="0">
          <comment>Number of Candidate
0: 1 candidate
1: 2 candidate
2: 3 candidate
3: 4 candidate</comment>
        </bits>
        <bits access="rw" name="rdbsp_en" pos="18" rst="0">
          <comment>Bit de-selection and combining
0: Disable
1: enable
Remark: When this bit is disabled, the output data number is equal to rDESCR_SIZE0 and it only support 1 candidate.</comment>
        </bits>
        <bits access="rw" name="rdescr_en" pos="19" rst="0">
          <comment>Descramble enable
0: Disable
1: enable</comment>
        </bits>
        <bits access="rw" name="rncb_minus_size" pos="27:20" rst="0">
          <comment>NCB minus:  NCB  3ND</comment>
        </bits>
      </reg32>
      <reg32 name="rds_x1_0" protect="rw">
        <bits access="rw" name="rds_x1_0" pos="30:0" rst="0">
          <comment>Descramble X1 value for candidate 0</comment>
        </bits>
      </reg32>
      <reg32 name="rds_x1_1" protect="rw">
        <bits access="rw" name="rds_x1_1" pos="30:0" rst="0">
          <comment>Descramble X1 value for candidate 1</comment>
        </bits>
      </reg32>
      <reg32 name="rds_x1_2" protect="rw">
        <bits access="rw" name="rds_x1_2" pos="30:0" rst="0">
          <comment>Descramble X1 value for candidate 2</comment>
        </bits>
      </reg32>
      <reg32 name="rds_x1_3" protect="rw">
        <bits access="rw" name="rds_x1_3" pos="30:0" rst="0x40">
          <comment>Descramble X1 value for candidate 3</comment>
        </bits>
      </reg32>
      <reg32 name="rds_x2_0" protect="rw">
        <bits access="rw" name="rds_x2_0" pos="30:0" rst="0">
          <comment>Descramble X2 value for candidate 0</comment>
        </bits>
      </reg32>
      <reg32 name="rds_x2_1" protect="rw">
        <bits access="rw" name="rds_x2_1" pos="30:0" rst="0">
          <comment>Descramble X2 value for candidate 1</comment>
        </bits>
      </reg32>
      <reg32 name="rds_x2_2" protect="rw">
        <bits access="rw" name="rds_x2_2" pos="30:0" rst="0">
          <comment>Descramble X2 value for candidate 2</comment>
        </bits>
      </reg32>
      <reg32 name="rds_x2_3" protect="rw">
        <bits access="rw" name="rds_x2_3" pos="30:0" rst="0x40">
          <comment>Descramble X2 value for candidate 3</comment>
        </bits>
      </reg32>
      <reg32 name="rdesr_cfg1" protect="rw">
        <bits access="rw" name="rdesr_size0" pos="8:0" rst="0">
          <comment>Descramble size 0</comment>
        </bits>
        <bits access="rw" name="rdesr_size1" pos="24:16" rst="0">
          <comment>Descramble size 1</comment>
        </bits>
      </reg32>
      <reg32 name="rdesr_cfg2" protect="rw">
        <bits access="rw" name="rdesr_size3" pos="8:0" rst="0">
          <comment>Descramble size 3</comment>
        </bits>
        <bits access="rw" name="rdesr_size2" pos="24:16" rst="0">
          <comment>Descramble size 2</comment>
        </bits>
      </reg32>
      <reg32 name="rdesr_cfg3" protect="rw">
        <bits access="rw" name="rdesr_ibuf_start_addr_0" pos="9:0" rst="0">
          <comment>Descramble input buffer start address 0</comment>
        </bits>
        <bits access="rw" name="rdesr_ibuf_start_addr_1" pos="25:16" rst="0">
          <comment>Descramble input buffer start address 1</comment>
        </bits>
      </reg32>
      <reg32 name="rdesr_cfg4" protect="rw">
        <bits access="rw" name="rdesr_ibuf_start_addr_3" pos="9:0" rst="0">
          <comment>Descramble input buffer start address 3</comment>
        </bits>
        <bits access="rw" name="rdesr_ibuf_start_addr_2" pos="25:16" rst="0">
          <comment>Descramble input buffer start address 4</comment>
        </bits>
      </reg32>
      <reg32 name="rds_bsel_omem_start_addr" protect="rw">
        <bits access="rw" name="rds_bsel_omem_start_addr" pos="9:0" rst="0">
          <comment>DS_BSEL output memory start address</comment>
        </bits>
      </reg32>
      <reg32 name="rds_bsel_ds_x1" protect="r">
        <bits access="r" name="rds_bsel_ds_x1" pos="30:0" rst="0">
          <comment>The last candidate Descramble X2 state value</comment>
        </bits>
      </reg32>
      <reg32 name="rds_bsel_ds_x2" protect="r">
        <bits access="r" name="rds_bsel_ds_x2" pos="30:0" rst="0">
          <comment>The last candidate Descramble X2 state value</comment>
        </bits>
      </reg32>
      <reg32 name="rds_bsel_status" protect="r">
        <bits access="wc" name="rdone" pos="0" rst="0">
          <comment>(This bit is write 1 clear)
0: No Done
1: Done</comment>
        </bits>
        <bits access="r" name="roverwritten" pos="1" rst="0">
          <comment>If Done bit would not clear before this engine re-engine would indicate overwritten output buffer
0: Normal
1: Error</comment>
        </bits>
        <bits access="r" name="rbus_error" pos="3:2" rst="0">
          <comment>0: Normal
1: Error
Bit 0: DSP control bus error
Bit 1: accelerator memory access collusion</comment>
        </bits>
        <bits access="r" name="rtimeout" pos="4" rst="0">
          <comment>0: Normal
1: Error</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="nb_fft_rsrp.xml">
    <module category="NBIOT_PHY" name="NB_FFT_RSRP">
      <reg32 name="rfft_ctrl" protect="rw">
        <bits access="rw" name="rfft_en" pos="0" rst="0x0">
          <comment>FFT calculation enable</comment>
        </bits>
        <bits access="rw" name="rfft_done_int_period" pos="1" rst="0x0">
          <comment>the period of FFT done interrupt, 0: one time per-subframe; 1: twice per-subframe.</comment>
        </bits>
      </reg32>
      <reg32 name="rfft_rsrp_cfg" protect="rw">
        <bits access="rw" name="rfft_rsrp_en" pos="0:0" rst="0x0">
          <comment>FFT/RSRP enable</comment>
        </bits>
        <bits access="rw" name="rscaling_alpha" pos="3:1" rst="0x3">
          <comment>FFT result scaling</comment>
        </bits>
        <bits access="rw" name="rfft_rsrp_mode" pos="4" rst="0x0">
          <comment>0: FFT disabled, 5 RSRP CELLs calculation mode; 1:  FFT + 2 RSRP Cell calculation mode.</comment>
        </bits>
      </reg32>
      <reg32 name="rfft_ofdm_cp_os" protect="rw">
        <bits access="rw" name="rfft_ofdm_cp_os" pos="3:0" rst="0x0">
          <comment>FFT OFDM symbol CP offset</comment>
        </bits>
      </reg32>
      <reg32 name="rrsrp_cell_en" protect="rw">
        <bits access="rw" name="rrsrp_cell0_en" pos="0" rst="0">
          <comment>RSRP Cell0 Enabled.</comment>
        </bits>
        <bits access="rw" name="rrsrp_cell1_en" pos="1" rst="0">
          <comment>RSRP Cell1 Enabled.</comment>
        </bits>
        <bits access="rw" name="rrsrp_cell2_en" pos="2" rst="0">
          <comment>RSRP Cell2 Enabled.</comment>
        </bits>
        <bits access="rw" name="rrsrp_cell3_en" pos="3" rst="0">
          <comment>RSRP Cell3 Enabled.</comment>
        </bits>
        <bits access="rw" name="rrsrp_cell4_en" pos="4" rst="0">
          <comment>RSRP Cell4 Enabled.</comment>
        </bits>
      </reg32>
      <reg32 name="rrsrp_cell0_start_pos" protect="rw">
        <bits access="rw" name="rrsrp_cell0_start_pos" pos="14:0" rst="0">
          <comment>Frame start position of RSRP Cell0 based on global timer.</comment>
        </bits>
      </reg32>
      <reg32 name="rrsrp_cell1_start_pos" protect="rw">
        <bits access="rw" name="rrsrp_cell1_start_pos" pos="14:0" rst="0">
          <comment>Frame start position of RSRP Cell1 based on global timer.</comment>
        </bits>
      </reg32>
      <reg32 name="rrsrp_cell2_start_pos" protect="rw">
        <bits access="rw" name="rrsrp_cell2_start_pos" pos="14:0" rst="0">
          <comment>Frame start position of RSRP Cell2 based on global timer.</comment>
        </bits>
      </reg32>
      <reg32 name="rrsrp_cell3_start_pos" protect="rw">
        <bits access="rw" name="rrsrp_cell3_start_pos" pos="14:0" rst="0">
          <comment>Frame start position of RSRP Cell3 based on global timer.</comment>
        </bits>
      </reg32>
      <reg32 name="rrsrp_cell4_start_pos" protect="rw">
        <bits access="rw" name="rrsrp_cell4_start_pos" pos="14:0" rst="0">
          <comment>Frame start position of RSRP Cell4 based on global timer.</comment>
        </bits>
      </reg32>
      <reg32 name="rcell0_ofdm_cp_os" protect="rw">
        <bits access="rw" name="rcell0_ofdm_cp_os" pos="3:0" rst="0">
          <comment>OFDM symbol CP offset for NCELL0.</comment>
        </bits>
      </reg32>
      <reg32 name="rcell1_ofdm_cp_os" protect="rw">
        <bits access="rw" name="rcell1_ofdm_cp_os" pos="3:0" rst="0">
          <comment>OFDM symbol CP offset for NCELL1.</comment>
        </bits>
      </reg32>
      <reg32 name="rcell2_ofdm_cp_os" protect="rw">
        <bits access="rw" name="rcell2_ofdm_cp_os" pos="3:0" rst="0">
          <comment>OFDM symbol CP offset for NCELL2.</comment>
        </bits>
      </reg32>
      <reg32 name="rcell3_ofdm_cp_os" protect="rw">
        <bits access="rw" name="rcell3_ofdm_cp_os" pos="3:0" rst="0">
          <comment>OFDM symbol CP offset for NCELL3.</comment>
        </bits>
      </reg32>
      <reg32 name="rcell4_ofdm_cp_os" protect="rw">
        <bits access="rw" name="rcell4_ofdm_cp_os" pos="3:0" rst="0">
          <comment>OFDM symbol CP offset for NCELL4.</comment>
        </bits>
      </reg32>
      <reg32 name="rncell_v_shift" protect="rw">
        <bits access="rw" name="rncell0_v_shift" pos="2:0" rst="0">
          <comment>vshift of NCELL0.</comment>
        </bits>
        <bits access="rw" name="rncell1_v_shift" pos="5:3" rst="0">
          <comment>vshift of NCELL1.</comment>
        </bits>
        <bits access="rw" name="rncell2_v_shift" pos="8:6" rst="0">
          <comment>vshift of NCELL2.</comment>
        </bits>
        <bits access="rw" name="rncell3_v_shift" pos="11:9" rst="0">
          <comment>vshift of NCELL3.</comment>
        </bits>
        <bits access="rw" name="rncell4_v_shift" pos="14:12" rst="0">
          <comment>vshift of NCELL4.</comment>
        </bits>
      </reg32>
      <reg32 name="rrsrp_subf_idx" protect="rw">
        <bits access="rw" name="rncell0_cfg_subf_idx" pos="3:0" rst="0">
          <comment>confiugred subframe idx when RSRX cell enabled.</comment>
        </bits>
        <bits access="rw" name="rncell1_cfg_subf_idx" pos="7:4" rst="0">
          <comment>confiugred subframe idx when RSRX cell enabled.</comment>
        </bits>
        <bits access="rw" name="rncell2_cfg_subf_idx" pos="11:8" rst="0">
          <comment>confiugred subframe idx when RSRX cell enabled.</comment>
        </bits>
        <bits access="rw" name="rncell3_cfg_subf_idx" pos="15:12" rst="0">
          <comment>confiugred subframe idx when RSRX cell enabled.</comment>
        </bits>
        <bits access="rw" name="rncell4_cfg_subf_idx" pos="19:16" rst="0">
          <comment>confiugred subframe idx when RSRX cell enabled.</comment>
        </bits>
      </reg32>
      <reg32 name="rrsrp_mem_baddr" protect="rw">
        <bits access="rw" name="rrsrp_mem_baddr" pos="8:0" rst="0">
          <comment>Offset address for RSRP write memory buffer.</comment>
        </bits>
      </reg32>
      <reg32 name="rfft_rsrp_status" protect="r">
        <bits access="w1c" name="rfft_buf_status" pos="2:1" rst="0">
          <comment>Indicated whether the data in ping-pong buffer is updated.</comment>
        </bits>
        <bits access="r" name="rfft_buf_switch_status" pos="3" rst="0">
          <comment>FFT buffer ping-pong flag</comment>
        </bits>
        <bits access="w1c" name="rncell0_triple_buf_status" pos="6:4" rst="0">
          <comment>Indicated which triple buffer is UPDATED</comment>
        </bits>
        <bits access="r" name="rncell0_triple_buf_switch_flag" pos="8:7" rst="3">
          <comment>Indicated which buffer is just updated when interrupt asserted.</comment>
        </bits>
        <bits access="w1c" name="rncell1_triple_buf_status" pos="11:9" rst="0">
          <comment>Indicated which triple buffer is UPDATED</comment>
        </bits>
        <bits access="r" name="rncell1_triple_buf_switch_flag" pos="13:12" rst="3">
          <comment>Indicated which buffer is just updated when interrupt asserted.</comment>
        </bits>
        <bits access="w1c" name="rncell2_triple_buf_status" pos="16:14" rst="0">
          <comment>Indicated which triple buffer is UPDATED</comment>
        </bits>
        <bits access="r" name="rncell2_triple_buf_switch_flag" pos="18:17" rst="3">
          <comment>Indicated which buffer is just updated when interrupt asserted.</comment>
        </bits>
        <bits access="w1c" name="rncell3_triple_buf_status" pos="21:19" rst="0">
          <comment>Indicated which triple buffer is UPDATED</comment>
        </bits>
        <bits access="r" name="rncell3_triple_buf_switch_flag" pos="23:22" rst="3">
          <comment>Indicated which buffer is just updated when interrupt asserted.</comment>
        </bits>
        <bits access="w1c" name="rncell4_triple_buf_status" pos="26:24" rst="0">
          <comment>Indicated which triple buffer is UPDATED</comment>
        </bits>
        <bits access="r" name="rncell4_triple_buf_switch_flag" pos="28:27" rst="3">
          <comment>Indicated which buffer is just updated when interrupt asserted.</comment>
        </bits>
      </reg32>
      <reg32 name="rsv_cell_subf_idx" protect="r">
        <bits access="r" name="rsv_cell_subf_idx" pos="3:0" rst="0">
          <comment>subframe index of serving cell</comment>
        </bits>
      </reg32>
      <reg32 name="rncell_subf_idx" protect="r">
        <bits access="r" name="rncell0_subf_idx" pos="3:0" rst="0">
          <comment>subframe idx of NCELL0</comment>
        </bits>
        <bits access="r" name="rncell1_subf_idx" pos="7:4" rst="0">
          <comment>subframe idx of NCELL1</comment>
        </bits>
        <bits access="r" name="rncell2_subf_idx" pos="11:8" rst="0">
          <comment>subframe idx of NCELL2</comment>
        </bits>
        <bits access="r" name="rncell3_subf_idx" pos="15:12" rst="0">
          <comment>subframe idx of NCELL3</comment>
        </bits>
        <bits access="r" name="rncell4_subf_idx" pos="19:16" rst="0">
          <comment>subframe idx of NCELL4</comment>
        </bits>
      </reg32>
      <reg32 name="rfft_rsrp_buf_ovwr" protect="r">
        <bits access="r" name="rfft_buf_ovwr" pos="1:0" rst="0">
          <comment>FFT pingpong buffer overwritten status</comment>
        </bits>
        <bits access="r" name="rrsrp_cell0_buf_ovwr" pos="4:2" rst="0">
          <comment>RSRP Cell0 triple buffer over-written status.</comment>
        </bits>
        <bits access="r" name="rrsrp_cell1_buf_ovwr" pos="7:5" rst="0">
          <comment>RSRP Cell1 triple buffer over-written status.</comment>
        </bits>
        <bits access="r" name="rrsrp_cell2_buf_ovwr" pos="10:8" rst="0">
          <comment>RSRP Cell2 triple buffer over-written status.</comment>
        </bits>
        <bits access="r" name="rrsrp_cell3_buf_ovwr" pos="13:11" rst="0">
          <comment>RSRP Cell3 triple buffer over-written status.</comment>
        </bits>
        <bits access="r" name="rrsrp_cell4_buf_ovwr" pos="16:14" rst="0">
          <comment>RSRP Cell4 triple buffer over-written status.</comment>
        </bits>
        <bits access="r" name="rfft_mem_wr_err" pos="18:17" rst="0">
          <comment>FFT write buffer bus error</comment>
        </bits>
        <bits access="r" name="rrsrp0_mem_wr_err" pos="20:19" rst="0">
          <comment>RSRP CELL0 write buffer bus error</comment>
        </bits>
        <bits access="r" name="rrsrp1_mem_wr_err" pos="22:21" rst="0">
          <comment>RSRP CELL1 write buffer bus error</comment>
        </bits>
        <bits access="r" name="rrsrp2_mem_wr_err" pos="24:23" rst="0">
          <comment>RSRP CELL2 write buffer bus error</comment>
        </bits>
        <bits access="r" name="rrsrp3_mem_wr_err" pos="26:25" rst="0">
          <comment>RSRP CELL3 write buffer bus error</comment>
        </bits>
        <bits access="r" name="rrsrp4_mem_wr_err" pos="28:27" rst="0">
          <comment>RSRP CELL4 write buffer bus error</comment>
        </bits>
      </reg32>
      <reg32 name="rfft_rsrp_buf_idx" protect="r">
        <bits access="r" name="rfft_pingpong_buf_idx" pos="0" rst="0">
          <comment>FFT pingpong buf idx</comment>
        </bits>
        <bits access="r" name="rrsrp0_tri_buf_idx" pos="2:1" rst="0">
          <comment>RSRP0 Triple buffer idx</comment>
        </bits>
        <bits access="r" name="rrsrp1_tri_buf_idx" pos="4:3" rst="0">
          <comment>RSRP1 Triple buffer idx</comment>
        </bits>
        <bits access="r" name="rrsrp2_tri_buf_idx" pos="6:5" rst="0">
          <comment>RSRP2 Triple buffer idx</comment>
        </bits>
        <bits access="r" name="rrsrp3_tri_buf_idx" pos="8:7" rst="0">
          <comment>RSRP3 Triple buffer idx</comment>
        </bits>
        <bits access="r" name="rrsrp4_tri_buf_idx" pos="10:9" rst="0">
          <comment>RSRP4 Triple buffer idx</comment>
        </bits>
      </reg32>
      <reg32 name="rfft_rsrp_subf_idx" protect="r">
        <bits access="r" name="rfft_subf_idx" pos="3:0" rst="0">
          <comment>FFT subframe idx</comment>
        </bits>
        <bits access="r" name="rrsrp0_subf_idx" pos="7:4" rst="0">
          <comment>RSRP Cell0 subframe idx</comment>
        </bits>
        <bits access="r" name="rrsrp1_subf_idx" pos="11:8" rst="0">
          <comment>RSRP Cell1 subframe idx</comment>
        </bits>
        <bits access="r" name="rrsrp2_subf_idx" pos="15:12" rst="0">
          <comment>RSRP Cell2 subframe idx</comment>
        </bits>
        <bits access="r" name="rrsrp3_subf_idx" pos="19:16" rst="0">
          <comment>RSRP Cell3 subframe idx</comment>
        </bits>
        <bits access="r" name="rrsrp4_subf_idx" pos="23:20" rst="0">
          <comment>RSRP Cell4 subframe idx</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="nb_intc.xml">
    <module category="NBIOT_PHY" name="NB_INTC">
      <reg32 name="rrx_int_dsp_masking" protect="rw">
        <bits access="rw" name="rrx_int_dsp_masking" pos="0:0" rst="0x0">
          <comment>Interrupt Masking bit for RX_INT_DSP</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_int_mcu_masking" protect="rw">
        <bits access="rw" name="rrx_int_mcu_masking" pos="0:0" rst="0x0">
          <comment>Interrupt Masking bit for RX_INT_MCU</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_int_dsp_masking" protect="rw">
        <bits access="rw" name="rtx_int_dsp_masking" pos="0:0" rst="0x0">
          <comment>Interrupt Masking bit for TX_INT_DSP</comment>
        </bits>
      </reg32>
      <reg32 name="racc_int_masking" protect="rw">
        <bits access="rw" name="rfft_done_int_masking" pos="0:0" rst="0">
          <comment>Interrupt masking bit from the interrupt of fft_done_int</comment>
        </bits>
        <bits access="rw" name="rncell0_rsrp_dec_done_int_masking" pos="1:1" rst="0">
          <comment>Interrupt masking bit of NCELL0 decode done intterupt</comment>
        </bits>
        <bits access="rw" name="rncell1_rsrp_dec_done_int_masking" pos="2:2" rst="0">
          <comment>Interrupt masking bit of NCELL1 decode done interrupt</comment>
        </bits>
        <bits access="rw" name="rncell2_rsrp_dec_done_int_masking" pos="3:3" rst="0">
          <comment>Interrupt masking bit of NCELL2 decode done interrpt</comment>
        </bits>
        <bits access="rw" name="rncell3_rsrp_dec_done_int_masking" pos="4:4" rst="0">
          <comment>Interrupt masking bit of NCELL3 decode done interrupt</comment>
        </bits>
        <bits access="rw" name="rncell4_rsrp_dec_done_int_masking" pos="5:5" rst="0">
          <comment>Interrupt masking bit of NCELL4 decode done interrupt</comment>
        </bits>
        <bits access="rw" name="rpss_sf_done_int_masking" pos="6:6" rst="0">
          <comment>Interrupt masking bit of PSS SF done interrupt</comment>
        </bits>
        <bits access="rw" name="rsss_sf_done_int_masking" pos="7:7" rst="0">
          <comment>Interrupt masking bit of SSS SF done interrupt</comment>
        </bits>
        <bits access="rw" name="rcfo_sf_done_int_masking" pos="8:8" rst="0">
          <comment>Interrupt masking bit of CFO SF done interrupt</comment>
        </bits>
        <bits access="rw" name="rvit_dec_done_int_masking" pos="9:9" rst="0">
          <comment>Interrupt masking bit of Viterbi decode done interrupt</comment>
        </bits>
        <bits access="rw" name="ragc_pwr_int_masking" pos="10:10" rst="0">
          <comment>Interrupt masking bit of AGC interrupt masking</comment>
        </bits>
        <bits access="rw" name="rds_bsel_int_masking" pos="11:11" rst="0">
          <comment>Interrupt masking bit of DS_BSEL interrupt</comment>
        </bits>
        <bits access="rw" name="rpusch_enc_int_masking" pos="12:12" rst="0">
          <comment>Interrupt masking bit of PUSCH encoder interrupt</comment>
        </bits>
        <bits access="rw" name="rtx_chsc_int_masking" pos="13:13" rst="0">
          <comment>Interrupt masking bit of TX_CHSC interrupt</comment>
        </bits>
        <bits access="rw" name="rfft_512_done_int_masking" pos="14:14" rst="0">
          <comment>Interrupt masking bit of FFT_512 done interrupt</comment>
        </bits>
        <bits access="rw" name="rnprs_acc1_done_int_masking" pos="15:15" rst="0">
          <comment>Interrupt masking bit of NPRS_ACC1 done interrupt</comment>
        </bits>
        <bits access="rw" name="rfine_ifft_done_int_masking" pos="16:16" rst="0">
          <comment>Interrupt masking bit of FINE_IFFT done interrupt</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_int_dsp_status" protect="w1c">
        <bits access="w1c" name="rrx_int_dsp_status" pos="0" rst="0">
          <comment>interrupt status of RX_INT_DSP, write 1 clear.</comment>
        </bits>
      </reg32>
      <reg32 name="rrx_int_mcu_status" protect="w1c">
        <bits access="w1c" name="rrx_int_mcu_status" pos="0:0" rst="0">
          <comment>Interrupt status of RX_INT_MCU, write 1 clear.</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_int_dsp_status" protect="w1c">
        <bits access="w1c" name="rtx_int_dsp_status" pos="0:0" rst="0">
          <comment>Interrupt status of TX_INT_DSP, write 1 clear.</comment>
        </bits>
      </reg32>
      <reg32 name="racc_int_status" protect="w1c">
        <bits access="w1c" name="rfft_int_status" pos="0:0" rst="0">
          <comment>Interrupt status of fft_sf_done_int</comment>
        </bits>
        <bits access="w1c" name="rncell0_rsrp_dec_done_int_status" pos="1:1" rst="0">
          <comment>Interrupt status of RSRP Cell0 decode done interrupt</comment>
        </bits>
        <bits access="w1c" name="rncell1_rsrp_dec_done_int_status" pos="2" rst="0">
          <comment>Interrupt status of RSRP Cell1 decode done interrupt</comment>
        </bits>
        <bits access="w1c" name="rncell2_rsrp_dec_done_int_status" pos="3" rst="0">
          <comment>Interrupt status of RSRP Cell20 decode done interrupt</comment>
        </bits>
        <bits access="w1c" name="rncell3_rsrp_dec_done_int_status" pos="4" rst="0">
          <comment>Interrupt status of RSRP Cell3 decode done interrupt</comment>
        </bits>
        <bits access="w1c" name="rncell4_rsrp_dec_done_int_status" pos="5" rst="0">
          <comment>Interrupt status of RSRP Cell4 decode done interrupt</comment>
        </bits>
        <bits access="w1c" name="rpss_sf_done_int_status" pos="6" rst="0">
          <comment>Interrupt status of PSS SF done interrupt</comment>
        </bits>
        <bits access="w1c" name="rsss_sf_done_int_status" pos="7" rst="0">
          <comment>Interrupt status of SSS SF done interrupt</comment>
        </bits>
        <bits access="w1c" name="rcfo_sf_done_int_status" pos="8" rst="0">
          <comment>Interrupt status of CFO SF done interrupt</comment>
        </bits>
        <bits access="w1c" name="rvit_dec_done_int_status" pos="9" rst="0">
          <comment>Interrupt status of Viterbi decode done</comment>
        </bits>
        <bits access="w1c" name="ragc_int_status" pos="10" rst="0">
          <comment>Interrupt status of AGC interrupt</comment>
        </bits>
        <bits access="w1c" name="rds_bsel_int_status" pos="11" rst="0">
          <comment>Interrupt status of DS_BSEL interrupt</comment>
        </bits>
        <bits access="w1c" name="rpusch_enc_int_status" pos="12" rst="0">
          <comment>Interrupt status of PUSCH Encoder interrupt</comment>
        </bits>
        <bits access="w1c" name="rtx_chsc_int_status" pos="13" rst="0">
          <comment>Interrupt status of TX_CHSC interrupt</comment>
        </bits>
        <bits access="w1c" name="rfft_512_done_int_status" pos="14" rst="0">
          <comment>Interrupt status of FFT_512 done interrupt</comment>
        </bits>
        <bits access="w1c" name="rnprs_acc1_done_int_status" pos="15" rst="0">
          <comment>Interrupt status of NPRS_ACC1 done interrupt</comment>
        </bits>
        <bits access="w1c" name="rfint_ifft_done_int_status" pos="16" rst="0">
          <comment>Interrupt status of FINE IFFT done interrupt</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="nb_meas.xml">
    <module category="NBIOT_PHY" name="NB_MEAS">
      <reg32 name="rasp_on" protect="w">
        <bits access="w" name="rasp_on" pos="0" rst="0">
          <comment>Symbol power accumulation enable/disable signal and effective at subframe boundary.
      1 : enable
      0 : disable</comment>
        </bits>
      </reg32>
      <reg32 name="rasp_ctrl" protect="rw">
        <bits access="rw" name="rasp_gain" pos="12:9" rst="0">
          <comment>Gain used in shift and saturation of accumulation power value.
Bit[3:0]	Gain
0000	        2^-24 (default)
0001	        2^-23
0010	        2^-22
0011	        2^-21</comment>
        </bits>
        <bits access="rw" name="rasp_length" pos="8:7" rst="0">
          <comment>Accumulation length of samples in every symbol.
    0: 128
    1: 64
    2: 32
    3: 16</comment>
        </bits>
        <bits access="rw" name="rasp_offset" pos="6:0" rst="0">
          <comment>Offset of samples from symbols boundaries which is the start boundary of agc symbol power calculation.</comment>
        </bits>
      </reg32>
      <reg32 name="rasp_rd_addr" protect="rw">
        <bits access="rw" name="rasp_rd_addr" pos="5:0" rst="0">
          <comment>Reading address for DSP to read asp response ram, and this register would auto-increment whenever access the  rASP_RD_DATA register
PING buffer address: 0~20
PONG buffer address: 21~41</comment>
        </bits>
      </reg32>
      <reg32 name="rdc_ofs_cfg_data" protect="rw">
        <bits access="rw" name="rdc_ofs_cfg_data" pos="31:0" rst="0">
          <comment>Bit[27:16]: Q DC offset configuration
Bit[11:0]:   I DC offset configuration</comment>
        </bits>
      </reg32>
      <hole size="7*32"/>
      <reg32 name="rasp_status" protect="r">
        <bits access="w1c" name="rasp_done_status" pos="0" rst="0">
          <comment>Report agc symbol power and DCC done status, write 1 to clear this status</comment>
        </bits>
        <bits access="r" name="rasp_buf_ping_pong_idx" pos="1" rst="0">
          <comment>Index bit to indicate which buffer is updated of PING-PONG
1: PONG buffer data is updated
0: PING buffer data is updated</comment>
        </bits>
      </reg32>
      <reg32 name="rasp_rd_data" protect="r">
        <bits access="r" name="rasp_rd_data" pos="31:0" rst="0">
          <comment>Data = mem[rASP_RD_ADDR] which is the ASP response memory data content. The ASP_RD_ADDR would auto increase whenever access this register.
ASP response Memory address range is 0-41
Address(0~6,21~27): symbol power, bit[15:0] for symbol 0,2,4,6,8,10,12 and bit[31:16] for symbol 1,3,5,7,9,11,13
Address(7~20,28~41):dc_offset value, bit[15:0] for I and bit[31:16] for Q</comment>
        </bits>
      </reg32>
      <hole size="51*32"/>
      <reg32 name="rfft_512_ctrl" protect="rw">
        <bits access="rw" name="rfft_fwd_inv" pos="0" rst="0">
          <comment>Forward/Inverse FFT transform computing selection</comment>
        </bits>
        <bits access="rw" name="rfft_buf_idx" pos="1" rst="0">
          <comment>PING-PONG memory selection
1b0: Memory0;
1b1: Memory1.</comment>
        </bits>
        <bits access="rw" name="rfft_scaling_factor" pos="4:2" rst="0">
          <comment>FFT scaling, it can be implemented by bit shift,
3d0: 2^-3
3d1: 2^-2
3d2: 2^-1
3d3: 2^0  (default)
3d4: 2^1
3d5: 2^2
3d6: 2^3
3d7: 2^4</comment>
        </bits>
        <bits access="rw" name="rfft_amp_scaling_factor" pos="7:5" rst="0">
          <comment>FFT_amp_out scaling for amplitude square output, it can be implemented by bit shift,
3d0: 2^-3
3d1: 2^-2
3d2: 2^-1
3d3: 2^0  (default)
3d4: 2^1
3d5: 2^2
3d6: 2^3
3d7: 2^4</comment>
        </bits>
        <bits access="rw" name="rfft_amp_cal_en" pos="8" rst="0">
          <comment>IFFT Output amptitude data
1b0: IFFT output normal data(I+j*Q);
1b1: IFFT output amptitude data(I^2+Q^2).</comment>
        </bits>
      </reg32>
      <reg32 name="rfft_512_start" protect="w">
        <bits access="w" name="rfft_512_start" pos="0" rst="0">
          <comment>FFT start indication, when write 1 to this register, a high active pulse will be generated and input to FFT engine to start FFT calculation.</comment>
        </bits>
      </reg32>
      <reg32 name="rfft_512_status" protect="r">
        <bits access="w1c" name="rfft_done" pos="0" rst="0">
          <comment>FFT done status, write 1 clear.</comment>
        </bits>
        <bits access="r" name="rmem_bus_err" pos="2:1" rst="0">
          <comment>An error grant is received when FFT request memory write bus to store FFT result.
Bit1: DSP control error;
Bit0: Accelerator memory access error.</comment>
        </bits>
        <bits access="r" name="rfft_in_underflow" pos="3" rst="0">
          <comment>This register is used to check the range of FFT/IFFT input,
1b1: absolute maximum FFT/IFFT input less than 32, in this case, the resolution of FFT/IFFT output will loss 1bit;
1b0: normally.</comment>
        </bits>
      </reg32>
      <hole size="61*32"/>
      <reg32 name="rnprs_acc1_start" protect="w">
        <bits access="w" name="rnprs_acc1_start" pos="0" rst="0">
          <comment>NPRS accelerator 1 Start</comment>
        </bits>
      </reg32>
      <reg32 name="rnprs_acc1_ctrl" protect="rw">
        <bits access="rw" name="rtimeout_val" pos="15:0" rst="0x7ff">
          <comment>Maximum time out value in 61.44Mhz unit</comment>
        </bits>
        <bits access="rw" name="rmode" pos="17:16" rst="0">
          <comment>Mode selection:
2b00: copy + dot product
2b01: dot product
2b10: copy</comment>
        </bits>
        <bits access="rw" name="rcp_src_mem" pos="18" rst="0">
          <comment>Copy Source memory before sequence dot product
0: Memory 0
1: Memory 1</comment>
        </bits>
        <bits access="rw" name="rcp_br_addr_en" pos="19" rst="0">
          <comment>Copy memory with bit-reversed address write location enable
0: Disable
1: Enable</comment>
        </bits>
        <bits access="rw" name="rdp_dst_mem" pos="20" rst="0">
          <comment>Destination memory after sequence dot product
0: Memory 0
1: Memory 1</comment>
        </bits>
        <bits access="rw" name="rdp_br_addr_en" pos="21" rst="0">
          <comment>Dot Product from memory 5 to memory 0/1 with bit-reversed address write location enable
0: Disable
1: Enable</comment>
        </bits>
        <bits access="rw" name="rconj_seq_en" pos="22" rst="0">
          <comment>Conjugate Sequence data Enable
0: Disable
1: Enable</comment>
        </bits>
      </reg32>
      <reg32 name="rnprs_acc1_len" protect="rw">
        <bits access="rw" name="rnprs_acc1_len" pos="8:0" rst="0x1ff">
          <comment>Operation length -1
Default : (511)</comment>
        </bits>
      </reg32>
      <reg32 name="rseq_start_ofs_addr" protect="rw">
        <bits access="rw" name="rseq_start_ofs_addr" pos="10:0" rst="0">
          <comment>Sequence Memory Start Offset Address</comment>
        </bits>
      </reg32>
      <reg32 name="rnprs_acc1_status" protect="r">
        <bits access="w1c" name="rdone" pos="0" rst="0">
          <comment>(This bit is read write 1 clear)
0: No Done
1: Done</comment>
        </bits>
        <bits access="r" name="roverwritten" pos="1" rst="0">
          <comment>If Done bit would not clear before this engine re-engine would indicate overwritten output buffer
0: Normal
1: Error</comment>
        </bits>
        <bits access="r" name="rbus error 0" pos="3:2" rst="0">
          <comment>Read/Write process in Memory 0/1 (FFT/IFFT input/output memory)
0: Normal
1: Error
Bit 0: DSP control bus error
Bit 1: accelerator memory access collusion</comment>
        </bits>
        <bits access="r" name="rbus error 1" pos="5:4" rst="0">
          <comment>Read/Write process in Memory 5 (Copied FFT memory)</comment>
        </bits>
        <bits access="r" name="rbus error 2" pos="7:6" rst="0">
          <comment>Read process in Memory 4 (Sequence memory)</comment>
        </bits>
        <bits access="r" name="rtimeout" pos="8" rst="0">
          <comment>0: Normal
1: Error</comment>
        </bits>
      </reg32>
      <hole size="59*32"/>
      <reg32 name="rfine_ifft_start" protect="w">
        <bits access="w" name="rfine_ifft_start" pos="0" rst="0">
          <comment>Fine IFFT START
A pulse to grigger the Fine IFFT</comment>
        </bits>
      </reg32>
      <reg32 name="rfine_ifft_calc_ctrl" protect="rw">
        <bits access="rw" name="rfine_ifft_t" pos="8:0" rst="0">
          <comment>NPRS Coarse Timing Result
Range is from 0 to 272</comment>
        </bits>
        <bits access="rw" name="rfine_ifft_calc_os" pos="22:16" rst="0">
          <comment>Fine IFFT calculation offset. Range is from 0 to 95.</comment>
        </bits>
        <bits access="rw" name="rfine_ifft_calc_len" pos="30:24" rst="0">
          <comment>Fine IFFT calculation length. Range is from 1 to 96.</comment>
        </bits>
      </reg32>
      <reg32 name="rfine_ifft_ioout_ctrl" protect="rw">
        <bits access="rw" name="rfine_ifft_out_iq_scale" pos="2:0" rst="0">
          <comment>Fine IFFT output a+bj scaling
3d0:x2^0(default)
3d1:x2^-1
3d2:x2^-2
3d3:x2^-3
3d4:x2^-4
3d5:x2^-5
3d6:x2^-6
3d7:x2^-7</comment>
        </bits>
        <bits access="rw" name="rfine_ifft_out_pwr_scale" pos="10:8" rst="0">
          <comment>Fine IFFT output power scaling
3d0:x2^-3
3d1:x2^-2
3d2:x2^-1
3d3:x2^0 (default)
3d4:x2^1
3d5:x2^2
3d6:x2^3
3d7:x2^4</comment>
        </bits>
        <bits access="rw" name="rfine_ifft_out_sel" pos="16" rst="0">
          <comment>Fine IFFT output selection
1b0: Output IFFT result: a+bj
1b1: Output power result: a^2+b^2</comment>
        </bits>
        <bits access="rw" name="rfine_ifft_in_ctrl" pos="17" rst="0">
          <comment>Fine IFFT input data control
1b0: Input data in inverse order
1b1: Input data in inverse order and swap bit0~bit255 with bit256~bit511</comment>
        </bits>
      </reg32>
      <reg32 name="rfine_ifft_input_addr" protect="rw">
        <bits access="rw" name="rfine_ifft_input_addr" pos="10:0" rst="0">
          <comment>Fine IFFT input data start address</comment>
        </bits>
      </reg32>
      <reg32 name="rfine_ifft_output_addr" protect="rw">
        <bits access="rw" name="rfine_ifft_output_addr" pos="10:0" rst="0">
          <comment>Fine IFFT output data start address</comment>
        </bits>
      </reg32>
      <reg32 name="rfine_ifft_status" protect="r">
        <bits access="w1c" name="rfine_ifft_done_status" pos="0" rst="0">
          <comment>Fine IFFT calculation done status.
1b1: Fine IFFT calculation done
1b0: Fine IFFT is idle or under calculating</comment>
        </bits>
        <bits access="w1c" name="rfine_ifft_ow_status" pos="1" rst="0">
          <comment>Fine IFFT output buffer status
1b1: Fine IFFT output buffer is over written
1b0: Fine IFFT output buffer is normal</comment>
        </bits>
        <bits access="r" name="rfine_ifft_err_status" pos="3:2" rst="0">
          <comment>Fine IFFT calculation done status.
1b1: Fine IFFT calculation done
1b0: Fine IFFT is idle or under calculating</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="nb_tx_chsc.xml">
    <module category="NBIOT_PHY" name="NB_TX_CHSC">
      <reg32 name="rtx_chsc_ctrl" protect="rw">
        <bits access="rw" name="rtimeout_val" pos="15:0" rst="0x0">
          <comment>Maximum time out value for  TX channel-interleaver and scrambling in 61.44Mhz unit.</comment>
        </bits>
        <bits access="rw" name="rtx_chsc_start_ctrl" pos="16" rst="0x0">
          <comment>Start control:
                     0: Trigger by SW start
                     1: Trigger by HW start.</comment>
        </bits>
        <bits access="rw" name="rch_intrlvr_en" pos="17" rst="0x0">
          <comment>Channel interleaver enable
                     0: Disable
                     1: Enable.</comment>
        </bits>
        <bits access="rw" name="rscr_en" pos="18" rst="0x0">
          <comment>Scramble enable
                    0: Disable
                    1: Enable.</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_chsc_start" protect="w1c">
        <bits access="w1c" name="rtx_chsc_start" pos="0" rst="0x0">
          <comment>TX channel-interleaver and scrambling accelerator 2 start.</comment>
        </bits>
      </reg32>
      <reg32 name="rmem_start_addr" protect="rw">
        <bits access="rw" name="rbsel_mem_start_addr" pos="9:0" rst="0x0">
          <comment>Bit selection memory start address.</comment>
        </bits>
        <bits access="rw" name="rscr_mem_start_addr" pos="25:16" rst="0x0">
          <comment>Scramble memory start output address.</comment>
        </bits>
      </reg32>
      <reg32 name="rbsel_cfg" protect="rw">
        <bits access="rw" name="ncb minus" pos="14:0" rst="0x0">
          <comment>Ncb minus NCB - 3ND.</comment>
        </bits>
        <bits access="rw" name="rk0_minus" pos="30:16" rst="0x0">
          <comment>K0 minus: K0 position without dummy bit..</comment>
        </bits>
      </reg32>
      <reg32 name="rch_intrlvr_cfg" protect="rw">
        <bits access="rw" name="rrow_sz" pos="7:4" rst="0x0">
          <comment>Row size for ch-interleaver.</comment>
        </bits>
        <bits access="rw" name="rmod_type" pos="8" rst="0x0">
          <comment>Modulation type
                        0: BPSK
                        1: QPSK.</comment>
        </bits>
        <bits access="rw" name="rcol_sz_pre_rse_unit" pos="22:16" rst="0x0">
          <comment>Column size in each resource unit:
                 (NUL_sym-1)* Nul_slot.</comment>
        </bits>
      </reg32>
      <reg32 name="rscr_size" protect="rw">
        <bits access="rw" name="rscr_size" pos="7:0" rst="0x0">
          <comment>scrambling size in current subframe.</comment>
        </bits>
      </reg32>
      <reg32 name="rscr_x1" protect="rw">
        <bits access="rw" name="rscr_x1" pos="30:0" rst="0x0">
          <comment>scrambling X1.</comment>
        </bits>
      </reg32>
      <reg32 name="rscr_x2" protect="rw">
        <bits access="rw" name="rscr_x2" pos="30:0" rst="0x0">
          <comment>scrambling X2.</comment>
        </bits>
      </reg32>
      <reg32 name="rlast_scr_x1" protect="rw">
        <bits access="rw" name="rlast_scr_x1" pos="30:0" rst="0x0">
          <comment>Last scrambling state in X1.</comment>
        </bits>
      </reg32>
      <reg32 name="rlast_scr_x2" protect="rw">
        <bits access="rw" name="rlast_scr_x2" pos="30:0" rst="0x0">
          <comment>Last scrambling state in X2.</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_chsc_status" protect="ro">
        <bits access="rw1c" name="done" pos="0" rst="0x0">
          <comment>(This bit is read write 1 clear)
                   0: No Done
                   1: Done.</comment>
        </bits>
        <bits access="ro" name="overwritten" pos="1" rst="0x0">
          <comment>If Done bit would not clear before this engine re-engine would indicate overwritten output buffer
                              0: Normal
                              1: Error</comment>
        </bits>
        <bits access="ro" name="bus error" pos="3:2" rst="0x0">
          <comment>0: Normal
                 1: Error
                 Bit 0: DSP control bus error
                 Bit 1: accelerator memory access collusion</comment>
        </bits>
        <bits access="ro" name="timeout " pos="4" rst="0x0">
          <comment>0: Normal
                 1: Error</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="nb_tx_frontend.xml">
    <module category="NBIOT_PHY" name="NB_TX_FRONTEND">
      <reg32 name="rtx_os" protect="rw">
        <bits access="rw" name="rpusch_os1" pos="7:0" rst="0xb">
          <comment>PUSCH offset1 for 3.75K process delay</comment>
        </bits>
        <bits access="rw" name="rpusch_os0" pos="15:8" rst="0x63">
          <comment>PUSCH offset0 for 15K process delay</comment>
        </bits>
        <bits access="rw" name="rprach_os" pos="23:16" rst="0xb">
          <comment>PRACH offset for process delay</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_ta_value" protect="rw">
        <bits access="rw" name="rtx_ta_value" pos="10:0" rst="0x0">
          <comment>TA Value</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_rach_start_adj" protect="rw">
        <bits access="rw" name="rtx_rach_start_adj" pos="10:0" rst="0x0">
          <comment>the advance time of PRACH start adjustment</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_rf_delay" protect="rw">
        <bits access="rw" name="rtx_rf_delay" pos="15:0" rst="0x0">
          <comment>RF delay from NBIOT_CORE to chip output</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_en" protect="rw">
        <bits access="rw" name="rpusch_en" pos="0" rst="0">
          <comment>PUSCH Enable</comment>
        </bits>
        <bits access="rw" name="rprach_en" pos="1" rst="0">
          <comment>PRACH Enable</comment>
        </bits>
      </reg32>
      <reg32 name="rdelta_cp_adj" protect="rw">
        <bits access="rw" name="rdelta_cp_adj" pos="5:0" rst="0">
          <comment>Delta CP adjustment</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_cfg" protect="rw">
        <bits access="rw" name="rtx_frm_mode" pos="0" rst="0">
          <comment>TX frame mode for PUSCH</comment>
        </bits>
        <bits access="rw" name="rmod_type" pos="1" rst="0">
          <comment>Module type</comment>
        </bits>
        <bits access="rw" name="rtx_buf_idx" pos="2" rst="0">
          <comment>TX Buffer idx</comment>
        </bits>
        <bits access="rw" name="rprach_cp_mode" pos="3" rst="0">
          <comment>CP length of PRACH0/1</comment>
        </bits>
        <bits access="rw" name="rtone_mode" pos="4" rst="0">
          <comment>PUSCH Tone mode</comment>
        </bits>
        <bits access="rw" name="rshorten_pusch_en" pos="5" rst="0">
          <comment>Shorten PUSCH Enable</comment>
        </bits>
        <bits access="rw" name="rpusch_sc_idx" pos="11:6" rst="0">
          <comment>PUSCH Subcarrier POsition</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_gain" protect="rw">
        <bits access="rw" name="rtx_gain" pos="11:0" rst="0">
          <comment>TX Gain</comment>
        </bits>
      </reg32>
      <reg32 name="rpusch_cfg" protect="rw">
        <bits access="rw" name="rthetal_symb_incr" pos="7:0" rst="0">
          <comment>thetal symbol incremental step value</comment>
        </bits>
        <bits access="rw" name="rsymb_num_mod2" pos="8" rst="0">
          <comment>symbol number modulo 2</comment>
        </bits>
      </reg32>
      <reg32 name="rmem_bus_err" protect="rw">
        <bits access="r" name="rmem_bus_err" pos="1:0" rst="0">
          <comment>memory bus access error</comment>
        </bits>
        <bits access="r" name="rtx_status" pos="3:2" rst="0">
          <comment>TX Status, 2'b00: IDLE; 2'b01: PRACH; 2'b10: PUSCH 3.75K; 2'b11: PUSCH 15K</comment>
        </bits>
        <bits access="r" name="rtx_start_sf_idx" pos="7:4" rst="0">
          <comment>Subframe index of NPRACH or NPUSCH transmitted</comment>
        </bits>
      </reg32>
      <hole size="2*32"/>
      <reg32 name="rprach_cmd_fifo0" protect="rw">
        <bits access="rw" name="rprach_sc_idx" pos="5:0" rst="0">
          <comment>PRACH sub-carrier index 0~47</comment>
        </bits>
        <bits access="r" name="rsv" pos="29:6" rst="0">
          <comment>Reserved</comment>
        </bits>
        <bits access="rw" name="rprach_cfg_status" pos="30" rst="0">
          <comment>PRACH CFG Status</comment>
        </bits>
        <bits access="rw" name="rprach_nxt_en" pos="31" rst="0">
          <comment>Next PRACH symbol group enabled</comment>
        </bits>
      </reg32>
      <reg32 name="rprach_cmd_fifo1" protect="rw">
        <bits access="rw" name="rprach_sc_idx" pos="5:0" rst="0">
          <comment>PRACH sub-carrier index 0~47</comment>
        </bits>
        <bits access="r" name="rsv" pos="29:6" rst="0">
          <comment>Reserved</comment>
        </bits>
        <bits access="rw" name="rprach_cfg_status" pos="30" rst="0">
          <comment>PRACH CFG Status</comment>
        </bits>
        <bits access="rw" name="rprach_nxt_en" pos="31" rst="0">
          <comment>Next PRACH symbol group enabled</comment>
        </bits>
      </reg32>
      <reg32 name="rprach_cmd_fifo2" protect="rw">
        <bits access="rw" name="rprach_sc_idx" pos="5:0" rst="0">
          <comment>PRACH sub-carrier index 0~47</comment>
        </bits>
        <bits access="r" name="rsv" pos="29:6" rst="0">
          <comment>Reserved</comment>
        </bits>
        <bits access="rw" name="rprach_cfg_status" pos="30" rst="0">
          <comment>PRACH CFG Status</comment>
        </bits>
        <bits access="rw" name="rprach_nxt_en" pos="31" rst="0">
          <comment>Next PRACH symbol group enabled</comment>
        </bits>
      </reg32>
      <reg32 name="rprach_cmd_fifo3" protect="rw">
        <bits access="rw" name="rprach_sc_idx" pos="5:0" rst="0">
          <comment>PRACH sub-carrier index 0~47</comment>
        </bits>
        <bits access="r" name="rsv" pos="29:6" rst="0">
          <comment>Reserved</comment>
        </bits>
        <bits access="rw" name="rprach_cfg_status" pos="30" rst="0">
          <comment>PRACH CFG Status</comment>
        </bits>
        <bits access="rw" name="rprach_nxt_en" pos="31" rst="0">
          <comment>Next PRACH symbol group enabled</comment>
        </bits>
      </reg32>
      <reg32 name="rprach_nxt_cmd_rd_ptr" protect="r">
        <bits access="r" name="rprach_nxt_cmd_rd_ptr" pos="1:0" rst="0">
          <comment>PRACH Nxt Command Read Pointer</comment>
        </bits>
        <bits access="r" name="rsv" pos="31:2" rst="0">
          <comment>Reserved</comment>
        </bits>
      </reg32>
      <reg32 name="rlpf1_coef0" protect="rw">
        <bits access="rw" name="rlpf1_coef00" pos="9:0" rst="0">
          <comment>LPF1 coefficient0</comment>
        </bits>
        <bits access="rw" name="rlpf1_coef01" pos="25:16" rst="0">
          <comment>LPF1 coefficient1</comment>
        </bits>
      </reg32>
      <reg32 name="rlpf1_coef1" protect="rw">
        <bits access="rw" name="rlpf1_coef10" pos="9:0" rst="0">
          <comment>LPF1 coefficient2</comment>
        </bits>
        <bits access="rw" name="rlpf1_coef11" pos="25:16" rst="0">
          <comment>LPF1 coefficient3</comment>
        </bits>
      </reg32>
      <reg32 name="rlpf2_coef0" protect="rw">
        <bits access="rw" name="rlpf2_coef00" pos="9:0" rst="0">
          <comment>LPF2 coefficient0</comment>
        </bits>
        <bits access="rw" name="rlpf2_coef01" pos="25:16" rst="0">
          <comment>LPF2 coefficient1</comment>
        </bits>
      </reg32>
      <reg32 name="rlpf2_coef1" protect="rw">
        <bits access="rw" name="rlpf2_coef10" pos="9:0" rst="0">
          <comment>LPF2 coefficient2</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_dout_checksum" protect="r">
        <bits access="r" name="rtx_dout_checksum" pos="30:0" rst="0">
          <comment>TX dout checksum</comment>
        </bits>
        <bits access="rw" name="rtx_dout_checksum_en" pos="31" rst="0">
          <comment>TX dout Checksum Enable</comment>
        </bits>
      </reg32>
      <reg32 name="rtx_flt_tail_bit_num" protect="rw">
        <bits access="rw" name="rtx_flt_tail_bit_num" pos="7:0" rst="0x80">
          <comment>Configurable Number of zero data padded at the end of TX transmission</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="nb_tx_pusch_encoder.xml">
    <module category="NBIOT_PHY" name="NB_TX_PUSCH_ENCODER">
      <reg32 name="pusch_enc_ctrl" protect="rw">
        <bits access="rw" name="rtimeout_val" pos="15:0" rst="0x0">
          <comment>Maximum time out value for pusch encoder in 61.44Mhz unit.</comment>
        </bits>
        <bits access="rw" name="swap" pos="18:16" rst="0x0">
          <comment>Endian SWAP control for bit, byte and word.</comment>
        </bits>
      </reg32>
      <reg32 name="pusch_enc_start" protect="wo">
        <bits access="wo" name="pusch_enc_start" pos="0" rst="0x0">
          <comment>Write this register will trigger pusch encoder start</comment>
        </bits>
      </reg32>
      <reg32 name="tbs" protect="rw">
        <bits access="rw" name="tbs" pos="12:0" rst="0x0">
          <comment>TB Size for PUSCH.</comment>
        </bits>
      </reg32>
      <reg32 name="alpha_ini" protect="rw">
        <bits access="rw" name="alpha_ini" pos="12:0" rst="0x0">
          <comment>Alpha init value for QPP interleaver.</comment>
        </bits>
      </reg32>
      <reg32 name="alpha_step" protect="rw">
        <bits access="rw" name="alpha_step" pos="12:0" rst="0x0">
          <comment>Alpha Step value for QPP interleaver.</comment>
        </bits>
      </reg32>
      <reg32 name="pusch_enc_rd_addr" protect="rw">
        <bits access="rw" name="pusch_enc_rd_addr" pos="9:0" rst="0x0">
          <comment>Rd address to DSP memory for pusch encoder.</comment>
        </bits>
      </reg32>
      <reg32 name="pusch_enc_wr_addr" protect="rw">
        <bits access="rw" name="pusch_enc_wr_addr" pos="9:0" rst="0x0">
          <comment>WR address to DSP memory for pusch encoder.</comment>
        </bits>
      </reg32>
      <reg32 name="pusch_enc_status" protect="ro">
        <bits access="rw1c" name="done" pos="0" rst="0x0">
          <comment>(This bit is read write 1 clear)
                   0: No Done
                   1: Done.</comment>
        </bits>
        <bits access="ro" name="overwritten" pos="1" rst="0x0">
          <comment>Indicate overwritten happen for pusch encoder
                  0: Normal
                  1: Error</comment>
        </bits>
        <bits access="ro" name="bus error" pos="3:2" rst="0x0">
          <comment>Bit 0: DSP control bus error, 0-Normal, 1-Error
                 Bit 1: accelerator memory access collusion, 0-Normal, 1-Error</comment>
        </bits>
        <bits access="ro" name="timeout " pos="4" rst="0x0">
          <comment>0: Normal
                 1: Error</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="nb_viterbi.xml">
    <module category="NBIOT_PHY" name="NB_VITERBI">
      <reg32 name="rvd_dec_start" protect="w">
        <bits access="w" name="rvd_dec_start" pos="0" rst="0">
          <comment>Start trigger of one sequential decoding of viterbi decoder which is generated by writing 1 to this register</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_ctrl" protect="rw">
        <bits access="rw" name="rvd_pl_size" pos="27:16" rst="0">
          <comment>Payload size of CBs to be decoded in one sequential decoding</comment>
        </bits>
        <bits access="rw" name="rvd_dec_num" pos="15:13" rst="0">
          <comment>Indicate the number(1~4) of coded blocks to be decoded in one sequential decoding process</comment>
        </bits>
        <bits access="rw" name="rvd_deint_en" pos="12" rst="1">
          <comment>Function of de-interleaving in hardware enable/disable
        1: Enable
        0: Disable</comment>
        </bits>
        <bits access="rw" name="rvd_crcmask_en" pos="11" rst="0">
          <comment>CRC mask checking enable/disable(for RNTI and antenna port number)
        1: Enable
        0: Disable</comment>
        </bits>
        <bits access="rw" name="rvd_crc_type" pos="10" rst="0">
          <comment>Indicate the CRC type of  sequential decoding
        1:24
        0:16</comment>
        </bits>
        <bits access="rw" name="rvd_lva_en" pos="0" rst="0">
          <comment>List viterbi mode enable/disable
        1: Enable
        0: Disable</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_addr_ctrl" protect="rw">
        <bits access="rw" name="rvd_vor_addr_o" pos="29:21" rst="0">
          <comment>This register indicates the start address of viterbi output odd buffer for payload.</comment>
        </bits>
        <bits access="rw" name="rvd_vor_addr_e" pos="20:12" rst="0">
          <comment>This register indicates the start address of viterbi output even buffer for payload.</comment>
        </bits>
        <bits access="rw" name="rvd_vir_addr" pos="11:0" rst="0">
          <comment>This register indicates the start address of data in viterbi input ram.</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_crc_mask01" protect="rw">
        <bits access="rw" name="rvd_crc_mask1" pos="31:16" rst="0">
          <comment>Indicate CRC mask1(for RNTI and antenna port number)</comment>
        </bits>
        <bits access="rw" name="rvd_crc_mask1" pos="15:0" rst="0">
          <comment>Indicate CRC mask0(for RNTI and antenna port number)</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_crc_mask23" protect="rw">
        <bits access="rw" name="rvd_crc_mask3" pos="31:16" rst="0">
          <comment>Indicate CRC mask1(for RNTI and antenna port number)</comment>
        </bits>
        <bits access="rw" name="rvd_crc_mask2" pos="15:0" rst="0">
          <comment>Indicate CRC mask0(for RNTI and antenna port number)</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_long_cfg" protect="rw">
        <bits access="rw" name="rvd_pl_swap" pos="18:16" rst="0">
          <comment>Reorder the 32bit data written to viterbi output buffer
    2:Reverse the word sequence in the Dword(1Dword)
    1: Reverse the byte sequence in every word(2words).
    0: Reverse the bit sequence in every byte(4bytes).</comment>
        </bits>
        <bits access="rw" name="rvd_timecnt_limit" pos="15:0" rst="0xFFFF">
          <comment>In a sequential decoding process, if the corresponding time counter exceeds this set value of rVD_TIMECNT_LIMIT, bit4 of rVD_DEC_SATUS will be set to 1 and sent to high layer.</comment>
        </bits>
      </reg32>
      <hole size="2*32"/>
      <reg32 name="rvd_vor_eo" protect="rw">
        <bits access="rw" name="rvd_vor_eo" pos="0" rst="0">
          <comment>Indicate even/odd viterbi output buffer to be written by decoder:
1: odd output buffer
0: even output buffer</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_dec_ctrl" protect="rw">
        <bits access="rw" name="rvd_scaling_bw_y" pos="31:28" rst="0">
          <comment>Bit width of output scaling data's fractional part(S8.y)</comment>
        </bits>
        <bits access="rw" name="rvd_scaling_bw_x" pos="27:24" rst="0">
          <comment>Bit width of input scaling data's fractional part(S16.x)</comment>
        </bits>
        <bits access="rw" name="rvd_scaling_factor" pos="23:16" rst="0">
          <comment>This register(U8.7) is multiplied by scaling input data(S16.x)</comment>
        </bits>
        <bits access="rw" name="rvd_crcmask_bitmap3" pos="15:12" rst="0">
          <comment>Bitmap of CRC masks(0~3) used in blind decoding for the CB3 to be decoded</comment>
        </bits>
        <bits access="rw" name="rvd_crcmask_bitmap2" pos="11:8" rst="0">
          <comment>Bitmap of CRC masks(0~3) used in blind decoding for the CB2 to be decoded</comment>
        </bits>
        <bits access="rw" name="rvd_crcmask_bitmap1" pos="7:4" rst="0">
          <comment>Bitmap of CRC masks(0~3) used in blind decoding for the CB1 to be decoded</comment>
        </bits>
        <bits access="rw" name="rvd_crcmask_bitmap0" pos="3:0" rst="0">
          <comment>Bitmap of CRC masks(0~3) used in blind decoding for the CB0 to be decoded</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_candi_cfg" protect="rw">
        <bits access="rw" name="rvd_sf_idx" pos="19:16" rst="0">
          <comment>Subframe index of current subframe on which DSP configure the decoding start siganl 'rVD_DEC_START'</comment>
        </bits>
        <bits access="rw" name="rvd_candi_cfg_cb3" pos="15:12" rst="0">
          <comment>15: Antenna number for candidate CB3(0: 1 antenna 1: 2 antennas)
14:12: 80ms SFN for candidate CB3</comment>
        </bits>
        <bits access="rw" name="rvd_candi_cfg_cb2" pos="11:8" rst="0">
          <comment>15: Antenna number for candidate CB2(0: 1 antenna 1: 2 antennas)
14:12: 80ms SFN for candidate CB2</comment>
        </bits>
        <bits access="rw" name="rvd_candi_cfg_cb1" pos="7:4" rst="0">
          <comment>15: Antenna number for candidate CB1(0: 1 antenna 1: 2 antennas)
14:12: 80ms SFN for candidate CB1</comment>
        </bits>
        <bits access="rw" name="rvd_candi_cfg_cb0" pos="3:0" rst="0">
          <comment>15: Antenna number for candidate CB0(0: 1 antenna 1: 2 antennas)
14:12: 80ms SFN for candidate CB0</comment>
        </bits>
      </reg32>
      <hole size="1*32"/>
      <reg32 name="rvd_crcread" protect="r">
        <bits access="r" name="rvd_crcresult_o" pos="31:16" rst="0">
          <comment>CRC checking result of the corresponding code block for output buffer odd, and CRC results from CB0 to CB3 have to be written sequentially to bit[0]~bit[15] of this register.
1: good    0: fail
If rVD_CRCMASK_EN =1, 4 bits mask checking result is reported for every candidate CB
    [31:28] for CB3(28:MASK0, 29:MASK1, 30:MASK2, 31:MASK3)
    [27:24] for CB2(24:MASK0, 25: MASK1, 26: MASK2, 27: MASK3)
    [23:20] for CB1(20: MASK0, 21: MASK1, 22: MASK2, 23: MASK3)
    [19:16] for CB0(16: MASK0, 17: MASK1, 18: MASK2, 19: MASK3)
And if rVD_CRCMASK_EN =0, 1 bit crc checking result is reported for every candidate CB
    [28] for CB3
    [24] for CB2
    [20] for CB1
    [16] for CB0</comment>
        </bits>
        <bits access="r" name="rvd_crcresult_e" pos="15:0" rst="0">
          <comment>CRC check result of the corresponding code block for output buffer even, and CRC results from CB0 to CB3 have to be written sequentially to bit[0]~bit[15] of this register.
1: good    0: fail
If rVD_CRCMASK_EN =1, 4 bits mask checking result is reported for every candidate CB
    [15:12] for CB3(12: MASK0, 13: MASK1, 14: MASK2, 15: MASK3)
    [11:8] for CB2(8: MASK0, 9: MASK1, 10: MASK2, 11: MASK3)
    [7:4] for CB1(4: MASK0, 5: MASK1, 6: MASK2, 7: MASK3)
    [3:0] for CB0(0: MASK0, 1: MASK1, 2: MASK2, 3: MASK3)
And if rVD_CRCMASK_EN =0, 1 bit crc checking result is reported for every candidate CB
    [12] for CB3
    [8] for CB2
    [4] for CB1
    [0] for CB0</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_serread01_e" protect="r">
        <bits access="r" name="rvd_ser_1" pos="27:16" rst="0">
          <comment>Symbol error number of the candidate CB1</comment>
        </bits>
        <bits access="r" name="rvd_ser_0" pos="11:0" rst="0">
          <comment>Symbol error number of the candidate CB0</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_serread01_o" protect="r">
        <bits access="r" name="rvd_ser_1" pos="27:16" rst="0">
          <comment>Symbol error number of the candidate CB1</comment>
        </bits>
        <bits access="r" name="rvd_ser_0" pos="11:0" rst="0">
          <comment>Symbol error number of the candidate CB0</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_serread23_e" protect="r">
        <bits access="r" name="rvd_ser_3" pos="27:16" rst="0">
          <comment>Symbol error number of the candidate CB1</comment>
        </bits>
        <bits access="r" name="rvd_ser_2" pos="11:0" rst="0">
          <comment>Symbol error number of the candidate CB0</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_serread23_o" protect="r">
        <bits access="r" name="rvd_ser_3" pos="27:16" rst="0">
          <comment>Symbol error number of the candidate CB1</comment>
        </bits>
        <bits access="r" name="rvd_ser_2" pos="11:0" rst="0">
          <comment>Symbol error number of the candidate CB0</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_candi_rpt_e" protect="r">
        <bits access="r" name="rvd_candi_rpt_e" pos="31:0" rst="0">
          <comment>Report some configurations to MCU for output buffer even
    [31:20] Report payload size
    [19:0]  Report configuration of register rVD_CANDI_CFG</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_candi_rpt_o" protect="r">
        <bits access="r" name="rvd_candi_rpt_o" pos="31:0" rst="0">
          <comment>Report some configurations to MCU for output buffer even
    [31:20] Report payload size
    [19:0]  Report configuration of register rVD_CANDI_CFG</comment>
        </bits>
      </reg32>
      <reg32 name="rvd_dec_status" protect="ro">
        <bits access="ro" name="rvd_vor_req_fail" pos="8:7" rst="0">
          <comment>Viterbi-in ram reading error</comment>
        </bits>
        <bits access="ro" name="rvd_vir_req_fail" pos="6:5" rst="0">
          <comment>Viterbi output buffer writing error</comment>
        </bits>
        <bits access="w1c" name="rvd_timecnt_out" pos="4" rst="0">
          <comment>This bit indicate that the time counter is exceed the limit of set value</comment>
        </bits>
        <bits access="ro" name="rvd_vor_overwrite" pos="3:2" rst="0">
          <comment>3: This bit is to indicate that the odd memory is overwritten or not before UPDATED is cleared.
2: This bit is to indicate that the even memory is overwritten or not before UPDATED is cleared.</comment>
        </bits>
        <bits access="w1c" name="rvd_vor_updated" pos="1:0" rst="0">
          <comment>1: This bit is to indicate that the odd memory is updated or not.
0: This bit is to indicate that the even memory is updated or not.</comment>
        </bits>
      </reg32>
    </module>
  </archive>
  <archive relative="rf_registers.xml">
    <module category="RF_Dig" name="RF_REGISTERS">
      <hole size="512*8"/>
      <reg name="int_clear0" protect="rw">
        <bits access="rw" name="int_ctrl_bit_0" pos="15:0" rst="0">
          <comment>int clear int[15:0]</comment>
        </bits>
      </reg>
      <reg name="int_clear1" protect="rw">
        <bits access="rw" name="int_ctrl_bit_1" pos="15:0" rst="0">
          <comment>int clear int[31:16]</comment>
        </bits>
      </reg>
      <reg name="int2tmcu0" protect="r">
        <bits access="r" name="irq0" pos="15:0" rst="0">
          <comment>read only irq[15:0]</comment>
        </bits>
      </reg>
      <reg name="int2tmcu1" protect="r">
        <bits access="r" name="irq1" pos="15:0" rst="0">
          <comment>read only irq[31:16]</comment>
        </bits>
      </reg>
      <hole size="832"/>
      <reg name="afc_freq_rxpll1" protect="rw">
        <bits access="rw" name="freq_offset_rxpll1" pos="15:0" rst="0">
          <comment>AFC PLL rxpll freq offset[15:0]</comment>
        </bits>
      </reg>
      <reg name="afc_freq_trxpll2" protect="rw">
        <bits access="rw" name="freq_offset_rxpll2" pos="15:8" rst="0">
          <comment>AFC PLL rxpll freq offset[23:16]</comment>
        </bits>
        <bits access="rw" name="freq_offset_txpll2" pos="7:0" rst="0">
          <comment>AFC PLL txpll freq offset[23:16]</comment>
        </bits>
      </reg>
      <reg name="afc_freq_txpll" protect="rw">
        <bits access="rw" name="freq_offset_txpll1" pos="15:0" rst="0">
          <comment>AFC PLL txpll freq offset[15:0]</comment>
        </bits>
      </reg>
      <reg name="afc_freq_bbpll1" protect="rw">
        <bits access="rw" name="freq_offset_bbpll11" pos="15:0" rst="0">
          <comment>AFC PLL txpll1 freq offset[15:0]</comment>
        </bits>
      </reg>
      <reg name="afc_freq_bbpll12" protect="rw">
        <bits access="rw" name="freq_offset_bbpll12" pos="15:8" rst="0">
          <comment>AFC PLL bbpll1 freq offset[23:16]</comment>
        </bits>
        <bits access="rw" name="freq_offset_bbpll22" pos="7:0" rst="0">
          <comment>AFC PLL bbpll2 freq offset[23:16]</comment>
        </bits>
      </reg>
      <reg name="afc_freq_bbpll2" protect="rw">
        <bits access="rw" name="freq_offset_bbpll21" pos="15:0" rst="0">
          <comment>AFC PLL bbpll2 freq offset[15:0]</comment>
        </bits>
      </reg>
      <reg name="afc_freq_offset_mode" protect="rw">
        <bits access="rw" name="freq_offset_mode_bbpll2" pos="3" rst="0">
          <comment>AFC freq offset mode</comment>
        </bits>
        <bits access="rw" name="freq_offset_mode_bbpll1" pos="2" rst="0">
          <comment>AFC freq offset mode</comment>
        </bits>
        <bits access="rw" name="freq_offset_mode_txpll" pos="1" rst="0">
          <comment>AFC freq offset mode</comment>
        </bits>
        <bits access="rw" name="freq_offset_mode_rxpll" pos="0" rst="0">
          <comment>AFC freq offset mode</comment>
        </bits>
      </reg>
      <hole size="352"/>
      <reg name="rxsdm_reg1" protect="rw">
        <bits access="rw" name="dither_bypass_rxsdm" pos="3" rst="0">
          <comment>sdm rxpll</comment>
        </bits>
        <bits access="rw" name="clk_former_edge_rxsdm" pos="2" rst="0">
          <comment>sdm rxpll</comment>
        </bits>
        <bits access="rw" name="dll_mode_rxsdm" pos="1:0" rst="0">
          <comment>sdm rxpll</comment>
        </bits>
      </reg>
      <reg name="rxsdm_reg2" protect="rw">
        <bits access="rw" name="freq_rxsdm0" pos="15:0" rst="0">
          <comment>sdm rxpll   freq_rxsdm[15:0]   frequency dividing ratio             for rxpll_div_bb[5:0]</comment>
        </bits>
      </reg>
      <reg name="rxsdm_reg3" protect="rw">
        <bits access="rw" name="freq_rxsdm1" pos="15:0" rst="0">
          <comment>sdm rxpll   freq_rxsdm[31:16]  frequency dividing ratio            for rxpll_div_bb[5:0]</comment>
        </bits>
      </reg>
      <reg name="rxsdm_reg4" protect="rw">
        <bits access="rw" name="tx_rx_rxsdm" pos="7" rst="0">
          <comment>sdm rxpll</comment>
        </bits>
        <bits access="rw" name="resetn_rxsdm" pos="6" rst="0">
          <comment>sdm rxpll</comment>
        </bits>
        <bits access="rw" name="int_dec_sel_rxsdm" pos="5:4" rst="0">
          <comment>sdm rxpll   00: int divide;  01: 1 bit decimal divide;10: 2 bits decimal divide;11 :bypass sdm</comment>
        </bits>
        <bits access="rw" name="freq_former_shift_ct_rxsdm" pos="3:1" rst="0">
          <comment>sdm rxpll</comment>
        </bits>
        <bits access="rw" name="freq_former_bypass_rxsdm" pos="0" rst="0">
          <comment>sdm rxpll</comment>
        </bits>
      </reg>
      <reg name="rxsdm_reg5" protect="rw">
        <bits access="rw" name="reser_sdm_rxsdm" pos="7:0" rst="0">
          <comment>sdm rxpll    reserved_sdm_rxsdm</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="freq_offset_ini_rx_reg1" protect="rw">
        <bits access="rw" name="freq_offset_ini_rxpll1" pos="15:0" rst="0">
          <comment>sdm rxpll</comment>
        </bits>
      </reg>
      <reg name="freq_offset_ini_rx_reg2" protect="rw">
        <bits access="rw" name="freq_offset_ini_txpll2" pos="15:8" rst="0">
          <comment>sdm txpll</comment>
        </bits>
        <bits access="rw" name="freq_offset_ini_rxpll2" pos="7:0" rst="0">
          <comment>sdm rxpll</comment>
        </bits>
      </reg>
      <reg name="txsdm_reg1" protect="rw">
        <bits access="rw" name="dll_update_txsdm" pos="4" rst="0">
          <comment>indication of dll_mode_txsdm being updated. write it to 1'b0 before assert it to 1'b1</comment>
        </bits>
        <bits access="rw" name="dither_bypass_txsdm" pos="3" rst="0">
          <comment>sdm txpll</comment>
        </bits>
        <bits access="rw" name="clk_former_edge_txsdm" pos="2" rst="0">
          <comment>sdm txpll</comment>
        </bits>
        <bits access="rw" name="dll_mode_txsdm" pos="1:0" rst="0">
          <comment>indication feedback clock frequency:
          2'b00: 182MHz, div 7
          2'b01: 208MHz, div 8
          2'b10: 234MHz, div 9
          2'b11: 260MHz, div 10</comment>
        </bits>
      </reg>
      <reg name="txsdm_reg4" protect="rw">
        <bits access="rw" name="tx_rx_txsdm" pos="7" rst="0">
          <comment>sdm txpll</comment>
        </bits>
        <bits access="rw" name="resetn_txsdm" pos="6" rst="0">
          <comment>sdm txpll</comment>
        </bits>
        <bits access="rw" name="int_dec_sel_txsdm" pos="5:4" rst="0">
          <comment>sdm txpll   00: int divide;  01: 1 bit decimal divide;10: 2 bits decimal divide;11 :bypass sdm</comment>
        </bits>
        <bits access="rw" name="freq_former_shift_ct_txsdm" pos="3:1" rst="0">
          <comment>sdm txpll</comment>
        </bits>
        <bits access="rw" name="freq_former_bypass_txsdm" pos="0" rst="0">
          <comment>sdm txpll</comment>
        </bits>
      </reg>
      <reg name="txsdm_reg5" protect="rw">
        <bits access="rw" name="reser_sdm_txsdm" pos="7:0" rst="0">
          <comment>sdm txpll  reserved_sdm_txsdm</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="freq_offset_ini_tx_reg1" protect="rw">
        <bits access="rw" name="freq_offset_ini_txpll1" pos="15:0" rst="0">
          <comment>sdm txpll</comment>
        </bits>
      </reg>
      <reg name="freq_offset_ini_bbpll1_reg1" protect="rw">
        <bits access="rw" name="freq_offset_ini_bbpll11" pos="15:0" rst="0">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <reg name="freq_offset_ini_bbpll1_reg2" protect="rw">
        <bits access="rw" name="freq_offset_ini_bbpll22" pos="15:8" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="freq_offset_ini_bbpll12" pos="7:0" rst="0">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <reg name="freq_offset_ini_bbpll2_reg1" protect="rw">
        <bits access="rw" name="freq_offset_ini_bbpll21" pos="15:0" rst="0">
          <comment>bbpll2</comment>
        </bits>
      </reg>
      <reg name="bbpll1_reg1" protect="rw">
        <bits access="rw" name="pll_cpaux_bit_rx" pos="12:10" rst="4">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_filter_ibit_rx" pos="9:7" rst="4">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_cp_bit_rx" pos="6:4" rst="4">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_vreg_bit_rx" pos="3:0" rst="8">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <reg name="bbpll1_reg2" protect="rw">
        <bits access="rw" name="pll_reser_rx" pos="12:9" rst="1">
          <comment>bbpll1     pll_reserved_rx</comment>
        </bits>
        <bits access="rw" name="pll_refmulti2_en_rx" pos="8" rst="1">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_high_test_rx" pos="7" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_low_test_rx" pos="6" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_test_en_rx" pos="5" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_sdm_clk_test_en_rx" pos="4" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_sdm_clk_sel_rst_rx" pos="3" rst="1">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_sdm_clk_sel_nor_rx" pos="2" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pu_pll_dr_rx" pos="1" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pu_pll_reg_rx" pos="0" rst="0">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <reg name="bbpll1_reg3" protect="rw">
        <bits access="rw" name="pll_reser_dig_1_rx" pos="15:0" rst="33352">
          <comment>bbpll1    pll_reserved_dig_1_rx  regplls1_0_bit</comment>
        </bits>
      </reg>
      <reg name="bbpll1_reg5" protect="rw">
        <bits access="rw" name="pll_sdm_freq_rx1" pos="15:0" rst="10240">
          <comment>bbpll1  pll_sdm_freq_rx[31:16]</comment>
        </bits>
      </reg>
      <reg name="bbpll1_reg6" protect="rw">
        <bits access="rw" name="pll_sdm_freq_rx0" pos="15:0" rst="0">
          <comment>bbpll1   pll_sdm_freq_rx[15:0]</comment>
        </bits>
      </reg>
      <reg name="bbpll1_reg7" protect="rw">
        <bits access="rw" name="reser_sdm_rx" pos="15:8" rst="2">
          <comment>bbpll1   reserved_sdm_rx</comment>
        </bits>
        <bits access="rw" name="int_dec_sel_rx" pos="7:5" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="dither_bypass_rx" pos="4" rst="1">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="ss_en_rx" pos="3" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="ss_squre_tri_sel_rx" pos="2" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_sdm_resetn_dr_rx" pos="1" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_sdm_resetn_reg_rx" pos="0" rst="0">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <reg name="bbpll1_reg8" protect="rw">
        <bits access="rw" name="pll_ss_devi_ct_rx" pos="15:8" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_ss_peri_ct_rx" pos="7:0" rst="0">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <reg name="bbpll1_reg9" protect="rw">
        <bits access="rw" name="pll_reser_dig_2_rx" pos="15:0" rst="32">
          <comment>bbpll1     pll_reserved_dig_2_rx</comment>
        </bits>
      </reg>
      <reg name="bbpll1_rega" protect="rw">
        <bits access="rw" name="sdm_reset_time_sel_rx" pos="15:14" rst="1">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="sdmclk_sel_time_sel_rx" pos="13:12" rst="1">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_clk_adc_sel_reg_rx" pos="8:7" rst="0">
      </bits>
        <bits access="rw" name="pll_clk_adc_en_reg_rx" pos="6" rst="0">
      </bits>
        <bits access="rw" name="pll_clk_adc_dfe_en_reg_rx" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pll_clkout_en_reg_rx" pos="4:1" rst="15">
          <comment>bbpll1   plls1_clk_cp26m_en,plls1_clk_cp624m_en,plls1_clk_sdio156m_en,plls1_clk_sdio416m_en</comment>
        </bits>
        <bits access="rw" name="clk_gen_en_reg_rx" pos="0" rst="1">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <reg name="bbpll1_regb" protect="r">
        <bits access="r" name="pu_pll_rx" pos="15" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="r" name="pll_lock_rx" pos="14" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="r" name="pll_sdm_resetn_rx" pos="13" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="r" name="pll_sdm_clk_sel_rx" pos="12" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="r" name="pll_clk_ready_rx" pos="11" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="r" name="pll_lock_steady_rx" pos="10" rst="0">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <reg name="bbpll1_regd" protect="rw">
        <bits access="rw" name="resetn_spll_rx" pos="5" rst="1">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="vco_reset_dis_rx" pos="4" rst="1">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_clkout_en_counter_sel_rx" pos="3:2" rst="2">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="lock_counter_sel_rx" pos="1:0" rst="1">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <reg name="bbpll1_regf" protect="rw">
        <bits access="rw" name="pll_cnt2_rx" pos="13:9" rst="13">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_cnt1_rx" pos="8:4" rst="24">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_mod23_bb2_rx" pos="3" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_mod23_bb_rx" pos="2" rst="1">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_clk_ad_sel1_rx" pos="1" rst="0">
          <comment>bbpll1</comment>
        </bits>
        <bits access="rw" name="pll_clk_ad_sel0_rx" pos="0" rst="1">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <reg name="bbpll2_reg1" protect="rw">
        <bits access="rw" name="pll_cpaux_bit_tx" pos="12:10" rst="4">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_filter_ibit_tx" pos="9:7" rst="4">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_cp_bit_tx" pos="6:4" rst="4">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_vreg_bit_tx" pos="3:0" rst="8">
          <comment>bbpll2</comment>
        </bits>
      </reg>
      <reg name="bbpll2_reg2" protect="rw">
        <bits access="rw" name="pll_reser_tx" pos="12:9" rst="1">
          <comment>bbpll2    pll_reserved_tx</comment>
        </bits>
        <bits access="rw" name="pll_refmulti2_en_tx" pos="8" rst="1">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_high_test_tx" pos="7" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_low_test_tx" pos="6" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_test_en_tx" pos="5" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_sdm_clk_test_en_tx" pos="4" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_sdm_clk_sel_rst_tx" pos="3" rst="1">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_sdm_clk_sel_nor_tx" pos="2" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pu_pll_dr_tx" pos="1" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pu_pll_reg_tx" pos="0" rst="0">
          <comment>bbpll2</comment>
        </bits>
      </reg>
      <reg name="bbpll2_reg3" protect="rw">
        <bits access="rw" name="pll_reser_dig_1_tx" pos="15:0" rst="33352">
          <comment>bbpll2   pll_reserved_dig_1_tx  regplls2_0_bit</comment>
        </bits>
      </reg>
      <reg name="bbpll2_reg5" protect="rw">
        <bits access="rw" name="pll_sdm_freq_tx1" pos="15:0" rst="9679">
          <comment>bbpll2  pll_sdm_freq_tx[31:16]</comment>
        </bits>
      </reg>
      <reg name="bbpll2_reg6" protect="rw">
        <bits access="rw" name="pll_sdm_freq_tx0" pos="15:0" rst="10687">
          <comment>bbpll2   pll_sdm_freq_tx[15:0]</comment>
        </bits>
      </reg>
      <reg name="bbpll2_reg7" protect="rw">
        <bits access="rw" name="reser_sdm_tx" pos="15:8" rst="2">
          <comment>bbpll2    reserved_sdm_tx</comment>
        </bits>
        <bits access="rw" name="int_dec_sel_tx" pos="7:5" rst="3">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="dither_bypass_tx" pos="4" rst="1">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="ss_en_tx" pos="3" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="ss_squre_tri_sel_tx" pos="2" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_sdm_resetn_dr_tx" pos="1" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_sdm_resetn_reg_tx" pos="0" rst="0">
          <comment>bbpll2</comment>
        </bits>
      </reg>
      <reg name="bbpll2_reg8" protect="rw">
        <bits access="rw" name="pll_ss_devi_ct_tx" pos="15:8" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_ss_peri_ct_tx" pos="7:0" rst="0">
          <comment>bbpll2</comment>
        </bits>
      </reg>
      <reg name="bbpll2_reg9" protect="rw">
        <bits access="rw" name="pll_reser_dig_2_tx" pos="15:0" rst="32">
          <comment>bbpll2   pll_reserved_dig_2_tx</comment>
        </bits>
      </reg>
      <reg name="bbpll2_rega" protect="rw">
        <bits access="rw" name="sdm_reset_time_sel_tx" pos="15:14" rst="1">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="sdmclk_sel_time_sel_tx" pos="13:12" rst="1">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_clk_adc_sel_reg_tx" pos="8:7" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_clk_adc_en_reg_tx" pos="6" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_clk_adc_dfe_en_reg_tx" pos="5" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_clkout_en_reg_tx" pos="4:1" rst="15">
          <comment>bbpll2   [1]  plls2_clk_cp307m_en</comment>
        </bits>
        <bits access="rw" name="clk_gen_en_reg_tx" pos="0" rst="1">
          <comment>bbpll2</comment>
        </bits>
      </reg>
      <reg name="bbpll2_regb" protect="r">
        <bits access="r" name="pu_pll_tx" pos="15" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="r" name="pll_lock_tx" pos="14" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="r" name="pll_sdm_resetn_tx" pos="13" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="r" name="pll_sdm_clk_sel_tx" pos="12" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="r" name="pll_clk_ready_tx" pos="11" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="r" name="pll_lock_steady_tx" pos="10" rst="0">
          <comment>bbpll2</comment>
        </bits>
      </reg>
      <reg name="bbpll2_regd" protect="rw">
        <bits access="rw" name="resetn_spll_tx" pos="5" rst="1">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="vco_reset_dis_tx" pos="4" rst="1">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_clkout_en_counter_sel_tx" pos="3:2" rst="2">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="lock_counter_sel_tx" pos="1:0" rst="1">
          <comment>bbpll2</comment>
        </bits>
      </reg>
      <reg name="bbpll2_regf" protect="rw">
        <bits access="rw" name="pll_cnt2_tx" pos="13:9" rst="13">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_cnt1_tx" pos="8:4" rst="24">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_mod23_bb2_tx" pos="3" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_mod23_bb_tx" pos="2" rst="1">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_clk_ad_sel1_tx" pos="1" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="rw" name="pll_clk_ad_sel0_tx" pos="0" rst="1">
          <comment>bbpll2</comment>
        </bits>
      </reg>
      <reg name="rxpll_cal_reg1" protect="rw">
        <bits access="rw" name="reg_90_bit1" pos="15:8" rst="0">
          <comment>rxpll_cal  target freq][15:8]</comment>
        </bits>
        <bits access="rw" name="reg_90_bit0" pos="7:0" rst="0">
          <comment>rxpll_cal  target freq[7:0]</comment>
        </bits>
      </reg>
      <reg name="rxpll_cal_reg2" protect="rw">
        <bits access="rw" name="reg_91_bit15to8" pos="15:8" rst="0">
          <comment>rxpll_cal   [2:0]:rxpll_vco_bits[10:8]   [6]:rxpll_cnt_enable  [7]:rxpll_cal_enable</comment>
        </bits>
        <bits access="rw" name="reg_91_bit70" pos="7" rst="0">
          <comment>rxpll_cal   reset</comment>
        </bits>
        <bits access="rw" name="reg_91_bit6to0" pos="6:0" rst="0">
          <comment>rxpll_cal  [1]:rxpll_cal_opt  [3:2]:rxpll_cnt_delay_sel  [6:4]:rxpll_init_delay</comment>
        </bits>
      </reg>
      <reg name="rxpll_cal_reg3" protect="rw">
        <bits access="rw" name="reg_92_bit1" pos="15:8" rst="0">
          <comment>rxpll_cal</comment>
        </bits>
        <bits access="rw" name="reg_92_bit0" pos="7:0" rst="0">
          <comment>rxpll_cal    [7:0]:rxpll_vco_bits[7:0]</comment>
        </bits>
      </reg>
      <reg name="rxpll_cal_reg4" protect="r">
        <bits access="r" name="rxpll_cal_enable" pos="13" rst="0">
          <comment>rxpll_cal</comment>
        </bits>
        <bits access="r" name="rxpll_cnt_enable" pos="12" rst="0">
          <comment>rxpll_cal</comment>
        </bits>
        <bits access="r" name="rxpll_cal_ready" pos="11" rst="0">
          <comment>rxpll_cal</comment>
        </bits>
        <bits access="r" name="rxpll_vco_bits" pos="10:0" rst="0">
          <comment>rxpll_cal    rxvco_band_bit_bb</comment>
        </bits>
      </reg>
      <reg name="txpll_cal_reg1" protect="rw">
        <bits access="rw" name="reg_98_bit1" pos="15:8" rst="0">
          <comment>txpll_cal   target freq][15:8]</comment>
        </bits>
        <bits access="rw" name="reg_98_bit0" pos="7:0" rst="0">
          <comment>txpll_cal   target freq[7:0]</comment>
        </bits>
      </reg>
      <reg name="txpll_cal_reg2" protect="rw">
        <bits access="rw" name="reg_99_bit15to8" pos="15:8" rst="0">
          <comment>txpll_cal  [2:0]:txpll_vco_bits[10:8]   [6]:txpll_cnt_enable  [7]:txpll_cal_enable</comment>
        </bits>
        <bits access="rw" name="reg_99_bit70" pos="7" rst="0">
          <comment>txpll_cal  reset</comment>
        </bits>
        <bits access="rw" name="reg_99_bit6to0" pos="6:0" rst="0">
          <comment>txpll_cal  [1]:txpll_cal_opt  [3:2]:txpll_cnt_delay_sel  [6:4]:txpll_init_delay</comment>
        </bits>
      </reg>
      <reg name="txpll_cal_reg3" protect="rw">
        <bits access="rw" name="reg_9a_bit1" pos="15:8" rst="0">
          <comment>txpll_cal</comment>
        </bits>
        <bits access="rw" name="reg_9a_bit0" pos="7:0" rst="0">
          <comment>txpll_cal  [7:0]:txpll_vco_bits[7:0]</comment>
        </bits>
      </reg>
      <reg name="txpll_cal_reg4" protect="r">
        <bits access="r" name="txpll_cal_enable" pos="13" rst="0">
          <comment>txpll_cal</comment>
        </bits>
        <bits access="r" name="txpll_cnt_enable" pos="12" rst="0">
          <comment>txpll_cal</comment>
        </bits>
        <bits access="r" name="txpll_cal_ready" pos="11" rst="0">
          <comment>txpll_cal</comment>
        </bits>
        <bits access="r" name="txpll_vco_bits" pos="10:0" rst="0">
          <comment>txpll_cal   txvco_band_bit_bb</comment>
        </bits>
      </reg>
      <reg name="gpio_reg" protect="rw">
        <bits access="rw" name="gpio_reg_out" pos="15:0" rst="0">
          <comment>gpio</comment>
        </bits>
      </reg>
      <hole size="480"/>
      <reg name="strobe_reg" protect="rw">
        <bits access="rw" name="strobe_sel" pos="14" rst="0">
          <comment>pa strobe</comment>
        </bits>
        <bits access="rw" name="multi_slot_sel" pos="13:12" rst="0">
          <comment>pa strobe</comment>
        </bits>
        <bits access="rw" name="strobe" pos="11" rst="0">
          <comment>pa strobe</comment>
        </bits>
        <bits access="rw" name="slot_number_dr" pos="10" rst="0">
          <comment>pa strobe</comment>
        </bits>
        <bits access="rw" name="slot_number_reg" pos="9:8" rst="0">
          <comment>pa strobe</comment>
        </bits>
        <bits access="rw" name="time_sel_after_rampd" pos="7:0" rst="0">
          <comment>pa strobe</comment>
        </bits>
      </reg>
      <reg name="pa_ctrl_reg1" protect="rw">
        <bits access="rw" name="ramp_curve_sel_3" pos="15:12" rst="0">
          <comment>pa ctrl</comment>
        </bits>
        <bits access="rw" name="ramp_curve_sel_2" pos="11:8" rst="0">
          <comment>pa ctrl</comment>
        </bits>
        <bits access="rw" name="ramp_curve_sel_1" pos="7:4" rst="0">
          <comment>pa ctrl</comment>
        </bits>
        <bits access="rw" name="ramp_curve_sel_0" pos="3:0" rst="0">
          <comment>pa ctrl</comment>
        </bits>
      </reg>
      <reg name="pa_ctrl_reg2" protect="rw">
        <bits access="rw" name="ramp_mult_factor_1" pos="15:8" rst="0">
          <comment>pa ctrl</comment>
        </bits>
        <bits access="rw" name="ramp_mult_factor_0" pos="7:0" rst="0">
          <comment>pa ctrl</comment>
        </bits>
      </reg>
      <reg name="pa_ctrl_reg3" protect="rw">
        <bits access="rw" name="ramp_mult_factor_3" pos="15:8" rst="0">
          <comment>pa ctrl</comment>
        </bits>
        <bits access="rw" name="ramp_mult_factor_2" pos="7:0" rst="0">
          <comment>pa ctrl</comment>
        </bits>
      </reg>
      <reg name="pa_ctrl_reg4" protect="rw">
        <bits access="rw" name="ramp_dac_din_reg" pos="10:1" rst="0">
          <comment>pa ctrl</comment>
        </bits>
        <bits access="rw" name="ramp_dac_din_dr" pos="0" rst="0">
          <comment>pa ctrl</comment>
        </bits>
      </reg>
      <hole size="352"/>
      <reg name="ana_ctrl_reg0" protect="rw">
        <bits access="rw" name="reg_100_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg1" protect="rw">
        <bits access="rw" name="reg_101_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg2" protect="rw">
        <bits access="rw" name="reg_102_bit" pos="15:0" rst="2117">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg3" protect="rw">
        <bits access="rw" name="reg_103_bit" pos="15:0" rst="66">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg4" protect="rw">
        <bits access="rw" name="reg_104_bit" pos="15:0" rst="15554">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg5" protect="rw">
        <bits access="rw" name="reg_105_bit" pos="15:0" rst="23632">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg6" protect="rw">
        <bits access="rw" name="reg_106_bit" pos="15:0" rst="34824">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg7" protect="rw">
        <bits access="rw" name="reg_107_bit" pos="15:0" rst="34947">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg8" protect="rw">
        <bits access="rw" name="reg_108_bit" pos="15:0" rst="22880">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg9" protect="rw">
        <bits access="rw" name="reg_109_bit" pos="15:0" rst="2560">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_rega" protect="rw">
        <bits access="rw" name="reg_10a_bit" pos="15:0" rst="20804">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_regb" protect="rw">
        <bits access="rw" name="reg_10b_bit" pos="15:0" rst="22672">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_regc" protect="rw">
        <bits access="rw" name="reg_10c_bit" pos="15:0" rst="34956">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_regd" protect="rw">
        <bits access="rw" name="reg_10d_bit" pos="15:0" rst="34947">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_rege" protect="rw">
        <bits access="rw" name="reg_10e_bit" pos="15:0" rst="22880">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_regf" protect="rw">
        <bits access="rw" name="reg_10f_bit" pos="15:0" rst="2564">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg10" protect="rw">
        <bits access="rw" name="reg_110_bit" pos="15:0" rst="68">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg11" protect="rw">
        <bits access="rw" name="reg_111_bit" pos="15:0" rst="63464">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg12" protect="rw">
        <bits access="rw" name="reg_112_bit" pos="15:0" rst="59864">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg13" protect="rw">
        <bits access="rw" name="reg_113_bit" pos="15:0" rst="43808">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg14" protect="rw">
        <bits access="rw" name="reg_114_bit" pos="15:0" rst="35472">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg15" protect="rw">
        <bits access="rw" name="reg_115_bit" pos="15:0" rst="12298">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg16" protect="rw">
        <bits access="rw" name="reg_116_bit" pos="15:0" rst="49810">
          <comment>ana ctrl   ?????</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg17" protect="rw">
        <bits access="rw" name="reg_117_bit" pos="15:0" rst="18855">
          <comment>ana ctrl  ?????</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg18" protect="rw">
        <bits access="rw" name="reg_118_bit" pos="15:0" rst="8456">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg19" protect="rw">
        <bits access="rw" name="reg_119_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg1a" protect="rw">
        <bits access="rw" name="reg_11a_bit" pos="15:0" rst="4842">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg1b" protect="rw">
        <bits access="rw" name="reg_11b_bit" pos="15:0" rst="48251">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg1c" protect="rw">
        <bits access="rw" name="reg_11c_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg1d" protect="rw">
        <bits access="rw" name="reg_11d_bit" pos="15:0" rst="32896">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg1e" protect="rw">
        <bits access="rw" name="reg_11e_bit" pos="15:0" rst="5504">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg1f" protect="rw">
        <bits access="rw" name="reg_11f_bit" pos="15:0" rst="12942">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg20" protect="rw">
        <bits access="rw" name="reg_120_bit" pos="15:0" rst="2051">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg21" protect="rw">
        <bits access="rw" name="reg_121_bit" pos="15:0" rst="253">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg22" protect="rw">
        <bits access="rw" name="reg_122_bit" pos="15:0" rst="36864">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg23" protect="rw">
        <bits access="rw" name="reg_123_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg24" protect="rw">
        <bits access="rw" name="reg_124_bit" pos="15:0" rst="33410">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg25" protect="rw">
        <bits access="rw" name="reg_125_bit" pos="15:0" rst="6404">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg26" protect="rw">
        <bits access="rw" name="reg_126_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg27" protect="rw">
        <bits access="rw" name="reg_127_bit" pos="15:0" rst="15">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg28" protect="rw">
        <bits access="rw" name="reg_128_bit" pos="15:0" rst="592">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg29" protect="rw">
        <bits access="rw" name="reg_129_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg2a" protect="rw">
        <bits access="rw" name="reg_12a_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg2b" protect="rw">
        <bits access="rw" name="reg_12b_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg2c" protect="rw">
        <bits access="rw" name="reg_12c_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg2d" protect="rw">
        <bits access="rw" name="reg_12d_bit" pos="15:0" rst="2645">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg2e" protect="rw">
        <bits access="rw" name="reg_12e_bit" pos="15:0" rst="8328">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg2f" protect="rw">
        <bits access="rw" name="reg_12f_bit" pos="15:0" rst="8208">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg30" protect="rw">
        <bits access="rw" name="reg_130_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg31" protect="rw">
        <bits access="rw" name="reg_131_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg32" protect="rw">
        <bits access="rw" name="reg_132_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg33" protect="rw">
        <bits access="rw" name="reg_133_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg34" protect="rw">
        <bits access="rw" name="reg_134_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg35" protect="rw">
        <bits access="rw" name="reg_135_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg36" protect="rw">
        <bits access="rw" name="reg_136_bit" pos="15:0" rst="0">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <reg name="ana_ctrl_reg37" protect="rw">
        <bits access="rw" name="reg_137_bit" pos="15:0" rst="65535">
          <comment>ana ctrl</comment>
        </bits>
      </reg>
      <hole size="2304"/>
      <reg name="control_rf_reg0" protect="rw">
        <bits access="rw" name="rx_tx_rf" pos="2" rst="0">
          <comment>controller rf</comment>
        </bits>
        <bits access="rw" name="dccal_q_enable_reg" pos="1" rst="0">
          <comment>controller rf</comment>
        </bits>
        <bits access="rw" name="dccal_i_enable_reg" pos="0" rst="0">
          <comment>controller rf</comment>
        </bits>
      </reg>
      <reg name="control_rf_reg1" protect="rw">
        <bits access="rw" name="gpio_auxclk_en_nodelay" pos="6" rst="1">
          <comment>controller rf</comment>
        </bits>
        <bits access="rw" name="aux_buf_delay" pos="5" rst="0">
          <comment>controller rf</comment>
        </bits>
        <bits access="rw" name="gpio_auxclk_en_dr" pos="4" rst="0">
          <comment>controller rf</comment>
        </bits>
        <bits access="rw" name="gpio_auxclk_en_reg" pos="3" rst="0">
          <comment>controller rf</comment>
        </bits>
        <bits access="rw" name="thermo_cal_enable" pos="2" rst="0">
          <comment>controller rf</comment>
        </bits>
        <bits access="rw" name="polarity_i" pos="1" rst="0">
          <comment>controller rf</comment>
        </bits>
        <bits access="rw" name="polarity_q" pos="0" rst="0">
          <comment>controller rf</comment>
        </bits>
      </reg>
      <reg name="control_rf_reg2" protect="rw">
        <bits access="rw" name="cnt_max_dccal_i" pos="15:0" rst="0">
          <comment>controller rf</comment>
        </bits>
      </reg>
      <reg name="control_rf_reg3" protect="rw">
        <bits access="rw" name="cnt_max_dccal_q" pos="7:0" rst="0">
          <comment>controller rf</comment>
        </bits>
      </reg>
      <reg name="control_rf_reg6" protect="rw">
        <bits access="rw" name="chip_tx_mode_reg" pos="0" rst="0">
          <comment>controller rf</comment>
        </bits>
      </reg>
      <reg name="clk_gen_reg0" protect="rw">
        <bits access="rw" name="freq_clk_div_4" pos="14:12" rst="0">
          <comment>clk gen</comment>
        </bits>
        <bits access="rw" name="freq_clk_div_3" pos="11:9" rst="0">
          <comment>clk gen</comment>
        </bits>
        <bits access="rw" name="freq_clk_div_2" pos="8:6" rst="0">
          <comment>clk gen</comment>
        </bits>
        <bits access="rw" name="freq_clk_div_1" pos="5:3" rst="0">
          <comment>clk gen</comment>
        </bits>
        <bits access="rw" name="freq_clk_div_0" pos="2:0" rst="0">
          <comment>clk gen</comment>
        </bits>
      </reg>
      <reg name="clk_gen_reg1" protect="rw">
        <bits access="rw" name="freq_clk_div_7" pos="8:6" rst="0">
          <comment>clk gen</comment>
        </bits>
        <bits access="rw" name="freq_clk_div_6" pos="5:3" rst="0">
          <comment>clk gen</comment>
        </bits>
        <bits access="rw" name="freq_clk_div_5" pos="2:0" rst="0">
          <comment>clk gen</comment>
        </bits>
      </reg>
      <reg name="clk_gen_reg2" protect="rw">
        <bits access="rw" name="inv_clk_div" pos="15:8" rst="0">
          <comment>clk gen</comment>
        </bits>
        <bits access="rw" name="enable_clk_div" pos="7:0" rst="0">
          <comment>clk gen</comment>
        </bits>
      </reg>
      <hole size="3840"/>
      <reg name="chip_id_reg0" protect="r">
        <bits access="r" name="chip_id0" pos="15:0" rst="33413">
          <comment>chip id</comment>
        </bits>
      </reg>
      <reg name="chip_id_reg1" protect="r">
        <bits access="r" name="chip_id1" pos="7:0" rst="0">
          <comment>chip id</comment>
        </bits>
      </reg>
      <reg name="chip_id_reg2" protect="r">
        <bits access="r" name="revision_id" pos="15:0" rst="0">
          <comment>revision_id</comment>
        </bits>
      </reg>
      <reg name="mean_dcccal_i_reg0" protect="r">
        <bits access="r" name="mean_dccal_i0" pos="15:0" rst="0">
          <comment>mean_dccal_i0</comment>
        </bits>
      </reg>
      <reg name="mean_dcccal_i_reg1" protect="r">
        <bits access="r" name="mean_dccal_i1" pos="0" rst="0">
          <comment>mean_dccal_i1</comment>
        </bits>
      </reg>
      <reg name="mean_dcccal_q_reg" protect="r">
        <bits access="r" name="mean_dccal_q" pos="8:0" rst="0">
          <comment>mean_dccal_q</comment>
        </bits>
      </reg>
      <reg name="revid_reg" protect="r">
        <bits access="r" name="revid_tx" pos="7:4" rst="0">
          <comment>bbpll2</comment>
        </bits>
        <bits access="r" name="revid_rx" pos="3:0" rst="0">
          <comment>bbpll1</comment>
        </bits>
      </reg>
      <hole size="800"/>
      <reg name="ana_rd_reg0" protect="r">
        <bits access="r" name="reg_221_bit" pos="15:0" rst="0">
          <comment>analogy</comment>
        </bits>
      </reg>
      <reg name="ana_rd_reg1" protect="r">
        <bits access="r" name="reg_222_bit" pos="15:0" rst="0">
          <comment>analogy</comment>
        </bits>
      </reg>
      <reg name="ana_rd_reg2" protect="r">
        <bits access="r" name="reg_223_bit" pos="15:0" rst="0">
          <comment>analogy</comment>
        </bits>
      </reg>
      <reg name="ana_rd_reg3" protect="r">
        <bits access="r" name="reg_224_bit" pos="15:0" rst="0">
          <comment>analogy</comment>
        </bits>
      </reg>
      <hole size="7040"/>
      <reg name="pa_ramp_reg0" protect="rw">
        <bits access="rw" name="ramp_curv0_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv0_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg1" protect="rw">
        <bits access="rw" name="ramp_curv0_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv0_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg2" protect="rw">
        <bits access="rw" name="ramp_curv0_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv0_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg3" protect="rw">
        <bits access="rw" name="ramp_curv0_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv0_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg4" protect="rw">
        <bits access="rw" name="ramp_curv0_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv0_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg5" protect="rw">
        <bits access="rw" name="ramp_curv0_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv0_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg6" protect="rw">
        <bits access="rw" name="ramp_curv0_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv0_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg7" protect="rw">
        <bits access="rw" name="ramp_curv0_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv0_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg10" protect="rw">
        <bits access="rw" name="ramp_curv1_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv1_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg11" protect="rw">
        <bits access="rw" name="ramp_curv1_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv1_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg12" protect="rw">
        <bits access="rw" name="ramp_curv1_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv1_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg13" protect="rw">
        <bits access="rw" name="ramp_curv1_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv1_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg14" protect="rw">
        <bits access="rw" name="ramp_curv1_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv1_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg15" protect="rw">
        <bits access="rw" name="ramp_curv1_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv1_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg16" protect="rw">
        <bits access="rw" name="ramp_curv1_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv1_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg17" protect="rw">
        <bits access="rw" name="ramp_curv1_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv1_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg20" protect="rw">
        <bits access="rw" name="ramp_curv2_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv2_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg21" protect="rw">
        <bits access="rw" name="ramp_curv2_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv2_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg22" protect="rw">
        <bits access="rw" name="ramp_curv2_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv2_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg23" protect="rw">
        <bits access="rw" name="ramp_curv2_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv2_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg24" protect="rw">
        <bits access="rw" name="ramp_curv2_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv2_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg25" protect="rw">
        <bits access="rw" name="ramp_curv2_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv2_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg26" protect="rw">
        <bits access="rw" name="ramp_curv2_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv2_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg27" protect="rw">
        <bits access="rw" name="ramp_curv2_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv2_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg30" protect="rw">
        <bits access="rw" name="ramp_curv3_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv3_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg31" protect="rw">
        <bits access="rw" name="ramp_curv3_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv3_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg32" protect="rw">
        <bits access="rw" name="ramp_curv3_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv3_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg33" protect="rw">
        <bits access="rw" name="ramp_curv3_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv3_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg34" protect="rw">
        <bits access="rw" name="ramp_curv3_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv3_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg35" protect="rw">
        <bits access="rw" name="ramp_curv3_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv3_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg36" protect="rw">
        <bits access="rw" name="ramp_curv3_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv3_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg37" protect="rw">
        <bits access="rw" name="ramp_curv3_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv3_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg40" protect="rw">
        <bits access="rw" name="ramp_curv4_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv4_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg41" protect="rw">
        <bits access="rw" name="ramp_curv4_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv4_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg42" protect="rw">
        <bits access="rw" name="ramp_curv4_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv4_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg43" protect="rw">
        <bits access="rw" name="ramp_curv4_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv4_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg44" protect="rw">
        <bits access="rw" name="ramp_curv4_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv4_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg45" protect="rw">
        <bits access="rw" name="ramp_curv4_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv4_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg46" protect="rw">
        <bits access="rw" name="ramp_curv4_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv4_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg47" protect="rw">
        <bits access="rw" name="ramp_curv4_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv4_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg50" protect="rw">
        <bits access="rw" name="ramp_curv5_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv5_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg51" protect="rw">
        <bits access="rw" name="ramp_curv5_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv5_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg52" protect="rw">
        <bits access="rw" name="ramp_curv5_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv5_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg53" protect="rw">
        <bits access="rw" name="ramp_curv5_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv5_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg54" protect="rw">
        <bits access="rw" name="ramp_curv5_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv5_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg55" protect="rw">
        <bits access="rw" name="ramp_curv5_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv5_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg56" protect="rw">
        <bits access="rw" name="ramp_curv5_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv5_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg57" protect="rw">
        <bits access="rw" name="ramp_curv5_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv5_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg60" protect="rw">
        <bits access="rw" name="ramp_curv6_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv6_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg61" protect="rw">
        <bits access="rw" name="ramp_curv6_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv6_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg62" protect="rw">
        <bits access="rw" name="ramp_curv6_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv6_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg63" protect="rw">
        <bits access="rw" name="ramp_curv6_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv6_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg64" protect="rw">
        <bits access="rw" name="ramp_curv6_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv6_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg65" protect="rw">
        <bits access="rw" name="ramp_curv6_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv6_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg66" protect="rw">
        <bits access="rw" name="ramp_curv6_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv6_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg67" protect="rw">
        <bits access="rw" name="ramp_curv6_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv6_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg70" protect="rw">
        <bits access="rw" name="ramp_curv7_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv7_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg71" protect="rw">
        <bits access="rw" name="ramp_curv7_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv7_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg72" protect="rw">
        <bits access="rw" name="ramp_curv7_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv7_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg73" protect="rw">
        <bits access="rw" name="ramp_curv7_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv7_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg74" protect="rw">
        <bits access="rw" name="ramp_curv7_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv7_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg75" protect="rw">
        <bits access="rw" name="ramp_curv7_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv7_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg76" protect="rw">
        <bits access="rw" name="ramp_curv7_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv7_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg77" protect="rw">
        <bits access="rw" name="ramp_curv7_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv7_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg80" protect="rw">
        <bits access="rw" name="ramp_curv8_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv8_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg81" protect="rw">
        <bits access="rw" name="ramp_curv8_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv8_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg82" protect="rw">
        <bits access="rw" name="ramp_curv8_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv8_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg83" protect="rw">
        <bits access="rw" name="ramp_curv8_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv8_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg84" protect="rw">
        <bits access="rw" name="ramp_curv8_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv8_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg85" protect="rw">
        <bits access="rw" name="ramp_curv8_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv8_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg86" protect="rw">
        <bits access="rw" name="ramp_curv8_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv8_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg87" protect="rw">
        <bits access="rw" name="ramp_curv8_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv8_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg90" protect="rw">
        <bits access="rw" name="ramp_curv9_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv9_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg91" protect="rw">
        <bits access="rw" name="ramp_curv9_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv9_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg92" protect="rw">
        <bits access="rw" name="ramp_curv9_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv9_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg93" protect="rw">
        <bits access="rw" name="ramp_curv9_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv9_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg94" protect="rw">
        <bits access="rw" name="ramp_curv9_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv9_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg95" protect="rw">
        <bits access="rw" name="ramp_curv9_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv9_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg96" protect="rw">
        <bits access="rw" name="ramp_curv9_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv9_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg97" protect="rw">
        <bits access="rw" name="ramp_curv9_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv9_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rega0" protect="rw">
        <bits access="rw" name="ramp_curva_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curva_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rega1" protect="rw">
        <bits access="rw" name="ramp_curva_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curva_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rega2" protect="rw">
        <bits access="rw" name="ramp_curva_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curva_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rega3" protect="rw">
        <bits access="rw" name="ramp_curva_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curva_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rega4" protect="rw">
        <bits access="rw" name="ramp_curva_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curva_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rega5" protect="rw">
        <bits access="rw" name="ramp_curva_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curva_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rega6" protect="rw">
        <bits access="rw" name="ramp_curva_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curva_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rega7" protect="rw">
        <bits access="rw" name="ramp_curva_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curva_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regb0" protect="rw">
        <bits access="rw" name="ramp_curvb_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvb_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regb1" protect="rw">
        <bits access="rw" name="ramp_curvb_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvb_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regb2" protect="rw">
        <bits access="rw" name="ramp_curvb_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvb_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regb3" protect="rw">
        <bits access="rw" name="ramp_curvb_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvb_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regb4" protect="rw">
        <bits access="rw" name="ramp_curvb_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvb_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regb5" protect="rw">
        <bits access="rw" name="ramp_curvb_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvb_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regb6" protect="rw">
        <bits access="rw" name="ramp_curvb_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvb_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regb7" protect="rw">
        <bits access="rw" name="ramp_curvb_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvb_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regc0" protect="rw">
        <bits access="rw" name="ramp_curvc_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvc_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regc1" protect="rw">
        <bits access="rw" name="ramp_curvc_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvc_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regc2" protect="rw">
        <bits access="rw" name="ramp_curvc_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvc_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regc3" protect="rw">
        <bits access="rw" name="ramp_curvc_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvc_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regc4" protect="rw">
        <bits access="rw" name="ramp_curvc_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvc_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regc5" protect="rw">
        <bits access="rw" name="ramp_curvc_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvc_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regc6" protect="rw">
        <bits access="rw" name="ramp_curvc_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvc_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regc7" protect="rw">
        <bits access="rw" name="ramp_curvc_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvc_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regd0" protect="rw">
        <bits access="rw" name="ramp_curvd_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvd_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regd1" protect="rw">
        <bits access="rw" name="ramp_curvd_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvd_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regd2" protect="rw">
        <bits access="rw" name="ramp_curvd_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvd_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regd3" protect="rw">
        <bits access="rw" name="ramp_curvd_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvd_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regd4" protect="rw">
        <bits access="rw" name="ramp_curvd_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvd_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regd5" protect="rw">
        <bits access="rw" name="ramp_curvd_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvd_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regd6" protect="rw">
        <bits access="rw" name="ramp_curvd_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvd_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regd7" protect="rw">
        <bits access="rw" name="ramp_curvd_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvd_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rege0" protect="rw">
        <bits access="rw" name="ramp_curve_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curve_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rege1" protect="rw">
        <bits access="rw" name="ramp_curve_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curve_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rege2" protect="rw">
        <bits access="rw" name="ramp_curve_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curve_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rege3" protect="rw">
        <bits access="rw" name="ramp_curve_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curve_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rege4" protect="rw">
        <bits access="rw" name="ramp_curve_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curve_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rege5" protect="rw">
        <bits access="rw" name="ramp_curve_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curve_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rege6" protect="rw">
        <bits access="rw" name="ramp_curve_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curve_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_rege7" protect="rw">
        <bits access="rw" name="ramp_curve_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curve_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regf0" protect="rw">
        <bits access="rw" name="ramp_curvf_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvf_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regf1" protect="rw">
        <bits access="rw" name="ramp_curvf_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvf_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regf2" protect="rw">
        <bits access="rw" name="ramp_curvf_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvf_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regf3" protect="rw">
        <bits access="rw" name="ramp_curvf_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvf_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regf4" protect="rw">
        <bits access="rw" name="ramp_curvf_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvf_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regf5" protect="rw">
        <bits access="rw" name="ramp_curvf_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvf_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regf6" protect="rw">
        <bits access="rw" name="ramp_curvf_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvf_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_regf7" protect="rw">
        <bits access="rw" name="ramp_curvf_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curvf_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg100" protect="rw">
        <bits access="rw" name="ramp_curv10_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv10_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg101" protect="rw">
        <bits access="rw" name="ramp_curv10_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv10_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg102" protect="rw">
        <bits access="rw" name="ramp_curv10_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv10_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg103" protect="rw">
        <bits access="rw" name="ramp_curv10_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv10_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg104" protect="rw">
        <bits access="rw" name="ramp_curv10_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv10_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg105" protect="rw">
        <bits access="rw" name="ramp_curv10_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv10_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg106" protect="rw">
        <bits access="rw" name="ramp_curv10_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv10_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg107" protect="rw">
        <bits access="rw" name="ramp_curv10_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv10_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg110" protect="rw">
        <bits access="rw" name="ramp_curv11_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv11_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg111" protect="rw">
        <bits access="rw" name="ramp_curv11_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv11_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg112" protect="rw">
        <bits access="rw" name="ramp_curv11_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv11_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg113" protect="rw">
        <bits access="rw" name="ramp_curv11_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv11_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg114" protect="rw">
        <bits access="rw" name="ramp_curv11_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv11_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg115" protect="rw">
        <bits access="rw" name="ramp_curv11_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv11_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg116" protect="rw">
        <bits access="rw" name="ramp_curv11_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv11_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg117" protect="rw">
        <bits access="rw" name="ramp_curv11_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv11_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg120" protect="rw">
        <bits access="rw" name="ramp_curv12_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv12_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg121" protect="rw">
        <bits access="rw" name="ramp_curv12_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv12_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg122" protect="rw">
        <bits access="rw" name="ramp_curv12_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv12_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg123" protect="rw">
        <bits access="rw" name="ramp_curv12_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv12_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg124" protect="rw">
        <bits access="rw" name="ramp_curv12_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv12_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg125" protect="rw">
        <bits access="rw" name="ramp_curv12_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv12_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg126" protect="rw">
        <bits access="rw" name="ramp_curv12_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv12_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg127" protect="rw">
        <bits access="rw" name="ramp_curv12_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv12_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg130" protect="rw">
        <bits access="rw" name="ramp_curv13_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv13_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg131" protect="rw">
        <bits access="rw" name="ramp_curv13_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv13_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg132" protect="rw">
        <bits access="rw" name="ramp_curv13_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv13_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg133" protect="rw">
        <bits access="rw" name="ramp_curv13_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv13_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg134" protect="rw">
        <bits access="rw" name="ramp_curv13_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv13_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg135" protect="rw">
        <bits access="rw" name="ramp_curv13_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv13_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg136" protect="rw">
        <bits access="rw" name="ramp_curv13_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv13_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg137" protect="rw">
        <bits access="rw" name="ramp_curv13_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv13_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg140" protect="rw">
        <bits access="rw" name="ramp_curv14_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv14_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg141" protect="rw">
        <bits access="rw" name="ramp_curv14_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv14_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg142" protect="rw">
        <bits access="rw" name="ramp_curv14_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv14_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg143" protect="rw">
        <bits access="rw" name="ramp_curv14_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv14_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg144" protect="rw">
        <bits access="rw" name="ramp_curv14_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv14_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg145" protect="rw">
        <bits access="rw" name="ramp_curv14_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv14_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg146" protect="rw">
        <bits access="rw" name="ramp_curv14_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv14_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg147" protect="rw">
        <bits access="rw" name="ramp_curv14_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv14_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg150" protect="rw">
        <bits access="rw" name="ramp_curv15_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv15_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg151" protect="rw">
        <bits access="rw" name="ramp_curv15_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv15_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg152" protect="rw">
        <bits access="rw" name="ramp_curv15_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv15_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg153" protect="rw">
        <bits access="rw" name="ramp_curv15_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv15_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg154" protect="rw">
        <bits access="rw" name="ramp_curv15_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv15_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg155" protect="rw">
        <bits access="rw" name="ramp_curv15_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv15_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg156" protect="rw">
        <bits access="rw" name="ramp_curv15_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv15_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg157" protect="rw">
        <bits access="rw" name="ramp_curv15_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv15_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg160" protect="rw">
        <bits access="rw" name="ramp_curv16_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv16_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg161" protect="rw">
        <bits access="rw" name="ramp_curv16_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv16_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg162" protect="rw">
        <bits access="rw" name="ramp_curv16_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv16_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg163" protect="rw">
        <bits access="rw" name="ramp_curv16_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv16_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg164" protect="rw">
        <bits access="rw" name="ramp_curv16_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv16_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg165" protect="rw">
        <bits access="rw" name="ramp_curv16_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv16_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg166" protect="rw">
        <bits access="rw" name="ramp_curv16_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv16_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg167" protect="rw">
        <bits access="rw" name="ramp_curv16_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv16_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg170" protect="rw">
        <bits access="rw" name="ramp_curv17_p1" pos="15:8" rst="24">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv17_p0" pos="7:0" rst="0">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg171" protect="rw">
        <bits access="rw" name="ramp_curv17_p3" pos="15:8" rst="76">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv17_p2" pos="7:0" rst="52">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg172" protect="rw">
        <bits access="rw" name="ramp_curv17_p5" pos="15:8" rst="124">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv17_p4" pos="7:0" rst="104">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg173" protect="rw">
        <bits access="rw" name="ramp_curv17_p7" pos="15:8" rst="168">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv17_p6" pos="7:0" rst="148">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg174" protect="rw">
        <bits access="rw" name="ramp_curv17_p9" pos="15:8" rst="204">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv17_p8" pos="7:0" rst="188">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg175" protect="rw">
        <bits access="rw" name="ramp_curv17_pb" pos="15:8" rst="232">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv17_pa" pos="7:0" rst="220">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg176" protect="rw">
        <bits access="rw" name="ramp_curv17_pd" pos="15:8" rst="248">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv17_pc" pos="7:0" rst="240">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_ramp_reg177" protect="rw">
        <bits access="rw" name="ramp_curv17_pf" pos="15:8" rst="255">
          <comment>pa ramp</comment>
        </bits>
        <bits access="rw" name="ramp_curv17_pe" pos="7:0" rst="252">
          <comment>pa ramp</comment>
        </bits>
      </reg>
      <reg name="pa_on_h_reg" protect="rw">
        <bits access="rw" name="pa_on_h_dr_reg" pos="11" rst="0">
          <comment>pa_on_h direct value</comment>
        </bits>
        <bits access="rw" name="pa_on_h_dr_ctrl" pos="10" rst="0">
          <comment>pa_on_h direct control, assert high</comment>
        </bits>
        <bits access="rw" name="ramp_dac_th" pos="9:0" rst="1023">
          <comment>threashold</comment>
        </bits>
      </reg>
      <hole size="2016"/>
      <reg name="sys_ctrl_reg_20" protect="rw">
        <bits access="rw" name="sys_ctrl2_0" pos="15:0" rst="65535">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_22" protect="rw">
        <bits access="rw" name="sys_ctrl2_2" pos="15:0" rst="32767">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_24" protect="rw">
        <bits access="rw" name="sys_ctrl2_4" pos="15:0" rst="65535">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_26" protect="rw">
        <bits access="rw" name="sys_ctrl2_6" pos="15:0" rst="65535">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_28" protect="rw">
        <bits access="rw" name="sys_ctrl2_8" pos="15:0" rst="3">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_2a" protect="rw">
        <bits access="rw" name="sys_ctrl2_a" pos="15:0" rst="0">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_2c" protect="rw">
        <bits access="rw" name="sys_ctrl2_c" pos="15:0" rst="65535">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_2e" protect="rw">
        <bits access="rw" name="sys_ctrl2_e" pos="15:0" rst="65535">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_210" protect="rw">
        <bits access="rw" name="sys_ctrl2_10" pos="15:0" rst="49152">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_212" protect="rw">
        <bits access="rw" name="sys_ctrl2_12" pos="15:0" rst="0">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_214" protect="rw">
        <bits access="rw" name="sys_ctrl2_14" pos="15:0" rst="0">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_216" protect="rw">
        <bits access="rw" name="sys_ctrl2_16" pos="15:0" rst="0">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_218" protect="rw">
        <bits access="rw" name="sys_ctrl2_18" pos="15:0" rst="0">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_21a" protect="rw">
        <bits access="rw" name="sys_ctrl2_1a" pos="15:0" rst="0">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_21c" protect="rw">
        <bits access="rw" name="sys_ctrl2_1c" pos="15:0" rst="16896">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="sys_ctrl_reg_21e" protect="rw">
        <bits access="rw" name="sys_ctrl2_1e" pos="15:0" rst="0">
          <comment>sys ctrl</comment>
        </bits>
      </reg>
      <reg name="dlpf_ctrl_reg" protect="rw">
        <bits access="rw" name="dlpf_vco_band_bit_sel" pos="2" rst="0">
          <comment>DLPF vco band bit enable
          0: TXPLL vco band bit is from pll_cal
          1: TXPLL vco band bit is from DLPF</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_rstn" pos="1" rst="0">
          <comment>reset DLPF IIR3, active low</comment>
        </bits>
        <bits access="rw" name="dlpf_rstn" pos="0" rst="0">
          <comment>reset DLPF, active low</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_timer.xml">
    <module category="RF_Dig" name="RF_TIMER">
      <reg name="timer_ctrl" protect="rw">
        <bits access="r/w" name="int_enable_ctrl" pos="3:3" rst="0x0">
    </bits>
        <bits access="r/w" name="clk_ctrl" pos="2:2" rst="0x0">
    </bits>
        <bits access="r/w" name="enable_ctrl" pos="1:1" rst="0x0">
    </bits>
        <bits access="r/w" name="dec_ctrl" pos="0:0" rst="0x0">
    </bits>
      </reg>
      <reg name="timer_value" protect="rw">
        <bits access="r/w" name="curr_val" pos="31:0" rst="0x0">
    </bits>
      </reg>
      <reg name="timer_reload" protect="rw">
        <bits access="r/w" name="reload_val" pos="31:0" rst="0x0">
    </bits>
      </reg>
      <reg name="timer_intstatus" protect="rw">
        <bits access="r/w" name="timer_int" pos="0:0" rst="0x0">
    </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_uart.xml">
    <module category="RF_Dig" name="RF_UART">
      <reg name="uart_data" protect="rw">
        <bits access="r/w" name="txrx_data" pos="7:0" rst="0x0">
    </bits>
      </reg>
      <reg name="uart_state" protect="rw">
        <bits access="r/w" name="rx_buffer_overrun" pos="3:3" rst="0x0">
    </bits>
        <bits access="r/w" name="tx_buffer_overrun" pos="2:2" rst="0x0">
    </bits>
        <bits access="r" name="rx_buffer_full" pos="1:1" rst="0x0">
    </bits>
        <bits access="r" name="tx_buffer_full" pos="0:0" rst="0x0">
    </bits>
      </reg>
      <reg name="uart_ctrl" protect="rw">
        <bits access="r/w" name="hs_test_mode" pos="6:6" rst="0x0">
    </bits>
        <bits access="r/w" name="tx_overrun_int_enable" pos="5:5" rst="0x0">
    </bits>
        <bits access="r/w" name="tx_overrun_int_enable" pos="4:4" rst="0x0">
    </bits>
        <bits access="r/w" name="rx_int_enable" pos="3:3" rst="0x0">
    </bits>
        <bits access="r/w" name="tx_int_enable" pos="2:2" rst="0x0">
    </bits>
        <bits access="r/w" name="rx_enable" pos="1:1" rst="0x0">
    </bits>
        <bits access="r/w" name="tx_enable" pos="0:0" rst="0x0">
    </bits>
      </reg>
      <reg name="uart_intstatus" protect="rw">
        <bits access="r/w" name="rx_overrun_int" pos="3:3" rst="0x0">
    </bits>
        <bits access="r/w" name="tx_overrun_int" pos="2:2" rst="0x0">
    </bits>
        <bits access="r/w" name="rx_int" pos="1:1" rst="0x0">
    </bits>
        <bits access="r/w" name="tx_int" pos="0:0" rst="0x0">
    </bits>
      </reg>
      <reg name="uart_baud" protect="rw">
        <bits access="r/w" name="baud_div" pos="19:0" rst="0x0">
    </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_wdt.xml">
    <module category="RF_Dig" name="RF_WDT">
      <reg name="wdogload" protect="rw">
        <bits access="r/w" name="wdog_load" pos="31:0" rst="0xffffffff">
    </bits>
      </reg>
      <reg name="wdogvalue" protect="ro">
        <bits access="r" name="wdog_value" pos="31:0" rst="0xffffffff">
    </bits>
      </reg>
      <reg name="wdogctrl" protect="rw">
        <bits access="r/w" name="wdog_res_en" pos="1:1" rst="0x0">
    </bits>
        <bits access="r/w" name="wdog_int_en" pos="0:0" rst="0x0">
    </bits>
      </reg>
      <reg name="wdogintclr" protect="wo">
        <bits access="w" name="wdog_int_clr" pos="0:0" rst="0x0">
    </bits>
      </reg>
      <reg name="wdogris" protect="ro">
        <bits access="r" name="wdog_raw_int_sts" pos="0:0" rst="0x0">
    </bits>
      </reg>
      <reg name="wdogmis" protect="ro">
        <bits access="r" name="wdog_int_sts" pos="0:0" rst="0x0">
    </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_sys_ctrl.xml">
    <module category="RF_Dig" name="RF_SYS_CTRL">
      <reg name="cfg_clk_sys" protect="rw">
        <bits access="r/w" name="clk_sys_sel" pos="11:11" rst="0x1">
    </bits>
        <bits access="r/w" name="div_update" pos="10:10" rst="0x0">
    </bits>
        <bits access="r/w" name="num" pos="8:5" rst="0x1">
    </bits>
        <bits access="r/w" name="denom" pos="3:0" rst="0x3">
    </bits>
      </reg>
      <reg name="cfg_clk_wdt" protect="rw">
        <bits access="r/w" name="div_update" pos="15:15" rst="0x0">
    </bits>
        <bits access="r/w" name="denom" pos="13:0" rst="0x400">
    </bits>
      </reg>
      <reg name="cfg_rst_1" protect="rw">
        <bits access="r/w" name="soft_reset" pos="15:0" rst="0x3fe7">
    </bits>
      </reg>
      <reg name="cfg_rst_2" protect="rw">
        <bits access="r/w" name="bypass_wdt_rst" pos="15:15" rst="0x1">
    </bits>
        <bits access="r/w" name="soft_reset" pos="7:0" rst="0xff">
    </bits>
      </reg>
      <reg name="gpio_out" protect="rw">
        <bits access="r/w" name="out" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="gpio_oen" protect="rw">
        <bits access="r/w" name="oen" pos="15:0" rst="0xffff">
    </bits>
      </reg>
      <reg name="gpio_in" protect="r">
        <bits access="r" name="in" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="debug_reg" protect="rw">
        <bits access="r/w" name="scratch" pos="15:1" rst="0x0">
    </bits>
        <bits access="r/w" name="hresp_err_mask" pos="0:0" rst="0x0">
    </bits>
      </reg>
      <reg name="io_ctrl" protect="rw">
        <bits access="r/w" name="slew_rate_rf" pos="14:14" rst="0x0">
    </bits>
        <bits access="r/w" name="i_bit_rf" pos="13:12" rst="0x1">
    </bits>
        <bits access="r/w" name="slew_rate_jtag" pos="11:11" rst="0x0">
    </bits>
        <bits access="r/w" name="i_bit_jtag" pos="10:9" rst="0x1">
    </bits>
        <bits access="r/w" name="slew_rate_ap" pos="8:8" rst="0x0">
    </bits>
        <bits access="r/w" name="i_bit_ap" pos="7:6" rst="0x1">
    </bits>
        <bits access="r/w" name="slew_rate_uart" pos="5:5" rst="0x0">
    </bits>
        <bits access="r/w" name="i_bit_uart" pos="4:3" rst="0x1">
    </bits>
        <bits access="r/w" name="slew_rate_spi" pos="2:2" rst="0x0">
    </bits>
        <bits access="r/w" name="i_bit_spi" pos="1:0" rst="0x1">
    </bits>
      </reg>
      <reg name="analog_tsen_adc_config0_0" protect="rw">
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_chop_clksel" pos="9:8" rst="0x2">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_clksel" pos="5:4" rst="0x1">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_sdadc_bias" pos="1:0" rst="0x0">
    </bits>
      </reg>
      <reg name="analog_tsen_adc_config0_1" protect="rw">
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_ugbuf_bias" pos="13:12" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_sdadc_vcmi" pos="9:8" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_sdadc_vcmo" pos="5:4" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_ugbuf_ctrl" pos="1:0" rst="0x0">
    </bits>
      </reg>
      <reg name="analog_tsen_adc_config1_0" protect="rw">
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_adcldo_en" pos="10:10" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_sdadc_capchop_en" pos="9:9" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_sdadc_chop_en" pos="8:8" rst="0x1">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_ugbuf_chop_en" pos="7:7" rst="0x1">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_sdadc_en" pos="6:6" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_sdadc_offset_en" pos="5:5" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_input_en" pos="4:4" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_ugbuf_en" pos="3:3" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_sdadc_data_edge_sel" pos="2:2" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_sdadc_rst" pos="1:1" rst="0x0">
    </bits>
      </reg>
      <reg name="analog_tsen_adc_config1_1" protect="rw">
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_adcldoref" pos="12:8" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_adcldo_v" pos="3:0" rst="0x8">
    </bits>
      </reg>
      <reg name="analog_tsen_adc_config2_0" protect="rw">
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_bist_code" pos="14:12" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_test_clk_sel" pos="9:9" rst="0x0">
    </bits>
        <bits access="r/w" name="c2g_analog_tsen_adc_rg_tsen_bist_en" pos="8:8" rst="0x0">
    </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rffe_reg.xml">
    <module category="RF_Dig" name="RFFE_REG">
      <reg name="cmd_mipi0" protect="rw">
        <bits access="rw" name="cmd_mipi_low" pos="15:0" rst="0">
          <comment>cmd_mipi_sr[15:0]</comment>
        </bits>
      </reg>
      <reg name="cmd_mipi1" protect="rw">
        <bits access="rw" name="cmd_mipi_high" pos="15:0" rst="0">
          <comment>cmd_mipi_sr[31:16]</comment>
        </bits>
      </reg>
      <reg name="data_mipi0" protect="rw">
        <bits access="rw" name="data_mipi_low" pos="15:0" rst="0">
          <comment>data_mipi_sr[15:0]</comment>
        </bits>
      </reg>
      <reg name="data_mipi1" protect="rw">
        <bits access="rw" name="data_mipi_high" pos="15:0" rst="0">
          <comment>data_mipi_sr[31:16]</comment>
        </bits>
      </reg>
      <reg name="data_out0" protect="r">
        <bits access="r" name="data_out_low" pos="15:0" rst="0">
          <comment>data_out[15:0]</comment>
        </bits>
      </reg>
      <reg name="data_out1" protect="r">
        <bits access="r" name="data_out_high" pos="15:0" rst="0">
          <comment>data_out[31:16]</comment>
        </bits>
      </reg>
      <reg name="data_valid" protect="r">
        <bits access="r" name="reversed" pos="15:4" rst="0">
          <comment>REVERSED</comment>
        </bits>
        <bits access="r" name="data_valid" pos="3:0" rst="0">
          <comment>data_valid_byte[3:0]</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_pulp_irq.xml">
    <module category="RF_Dig" name="RF_PULP_IRQ">
      <reg name="enable" protect="rw">
        <bits access="rw" name="enable" pos="31:0" rst="0">
          <comment>interrupt enable</comment>
        </bits>
      </reg>
      <reg name="pending" protect="rw">
        <bits access="rw" name="pending" pos="31:0" rst="0">
          <comment>interrupt pending</comment>
        </bits>
      </reg>
      <reg name="set_pending" protect="rw">
        <bits access="rs" name="set_pending" pos="31:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set interrupt pending</comment>
        </bits>
      </reg>
      <reg name="clear_pending" protect="rw">
        <bits access="rc" name="clear_pending" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clear interrupt pending</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_pulp_sleep.xml">
    <module category="RF_Dig" name="RF_PULP_SLEEP">
      <reg name="sleep_ctrl" protect="rw">
        <bits access="rw" name="sleep_enable" pos="0" rst="0">
          <comment>Enable sleep</comment>
        </bits>
      </reg>
      <reg name="sleep_status" protect="rw">
        <bits access="rw" name="sleep" pos="0" rst="0">
          <comment>sleep stauts
0: not_sleep
1: sleep</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_pulp_debug_unit.xml">
    <module category="RF_Dig" name="RF_PULP_DEBUG_UNIT">
      <reg name="dbg_ctrl" protect="rw">
        <bits access="rw" name="halt" pos="16" rst="0">
          <comment>when 1 written,core enters debug mode, when 0 written, core exits debug mode
when read, 1 means core is in debug mode</comment>
        </bits>
        <bits access="rw" name="sste" pos="0" rst="0">
          <comment>single step enable</comment>
        </bits>
      </reg>
      <reg name="dbg_hit" protect="rw">
        <bits access="r" name="sleep" pos="16" rst="0">
          <comment>set when the core is a sleeping state and wait for an event</comment>
        </bits>
        <bits access="rw" name="ssth" pos="0" rst="0">
          <comment>single-step hit, sticky bit that must be cleared by external debugger</comment>
        </bits>
      </reg>
      <reg name="dbg_ie" protect="rw">
        <bits access="rw" name="ecall" pos="11" rst="0">
          <comment>environment call for M-mode</comment>
        </bits>
        <bits access="rw" name="saf" pos="7" rst="0">
          <comment>store access fault (together with laf)</comment>
        </bits>
        <bits access="rw" name="sam" pos="6" rst="0">
          <comment>store address Misaligned (never traps)</comment>
        </bits>
        <bits access="rw" name="laf" pos="5" rst="0">
          <comment>load access fault (together with saf)</comment>
        </bits>
        <bits access="rw" name="lam" pos="4" rst="0">
          <comment>load access Misaligned (never traps)</comment>
        </bits>
        <bits access="rw" name="bp" pos="3" rst="0">
          <comment>ebreak instruction causes trap</comment>
        </bits>
        <bits access="rw" name="ill" pos="2" rst="0">
          <comment>illegal instruction</comment>
        </bits>
        <bits access="rw" name="iaf" pos="1" rst="0">
          <comment>instruction access fault (not implemented)</comment>
        </bits>
        <bits access="rw" name="iam" pos="0" rst="0">
          <comment>instruction address misaligned (never traps)</comment>
        </bits>
      </reg>
      <reg name="dbg_cause" protect="r">
        <bits access="r" name="irq" pos="31" rst="0">
          <comment>interrupt caused us to enter debug mode</comment>
        </bits>
        <bits access="r" name="cause" pos="4:0" rst="0">
          <comment>exception/interrupt number</comment>
        </bits>
      </reg>
      <hole size="8064"/>
      <reg name="dbg_gpr0" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr1" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr2" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr3" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr4" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr5" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr6" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr7" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr8" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr9" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr10" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr11" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr12" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr13" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr14" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr15" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr16" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr17" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr18" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr19" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr20" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr21" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr22" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr23" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr24" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr25" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr26" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr27" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr28" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr29" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr30" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr31" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <hole size="56320"/>
      <reg name="dbg_npc" protect="rw">
        <bits access="rw" name="npc" pos="31:0" rst="0">
          <comment>Next PC to be executed</comment>
        </bits>
      </reg>
      <reg name="dbg_ppc" protect="r">
        <bits access="r" name="ppc" pos="31:0" rst="0">
          <comment>previous PC, already executed</comment>
        </bits>
      </reg>
      <hole size="90048"/>
      <reg name="dbg_mstatus" protect="rw">
        <bits access="r" name="prv" pos="2:1" rst="3">
          <comment>Statically 2'b11 and cannot be altered</comment>
        </bits>
        <bits access="rw" name="int_en" pos="0" rst="0">
          <comment>Interrupt enable:
When an exception is encountered, Interrupt Enable will be set to 1'b0.
When the eret instruction is executed, the original value of the Interrupt Enable will be restored, as MESTATUS will replace MSTATUS.
If you want to be enable interrupt handling in your exception handler, set the Interrupt Enable to 1'b1 inside your handler code.</comment>
        </bits>
      </reg>
      <hole size="2048"/>
      <reg name="dbg_mepc" protect="rw">
        <bits access="rw" name="mepc" pos="31:0" rst="0">
          <comment>When an exception is encountered, the current program counter is saved in MEPC, and the core jumps to the exception address.
When an eret instruction is executed, the value from MEPC replaces the current program counter.</comment>
        </bits>
      </reg>
      <reg name="dbg_mcause" protect="r">
        <bits access="r" name="interrupt" pos="31" rst="0">
          <comment>this bit is  set when the exception was triggerd by an interrupt</comment>
        </bits>
        <bits access="r" name="excp_code" pos="4:0" rst="0">
          <comment>exception code</comment>
        </bits>
      </reg>
      <hole size="36256"/>
      <reg name="dbg_loop_start0" protect="rw">
        <bits access="rw" name="lpstart0" pos="31:0" rst="0">
          <comment>hardware loop 0 start</comment>
        </bits>
      </reg>
      <reg name="dbg_loop_end0" protect="rw">
        <bits access="rw" name="lpend0" pos="31:0" rst="0">
          <comment>hardware loop 0 end</comment>
        </bits>
      </reg>
      <reg name="dbg_loop_cnt0" protect="rw">
        <bits access="rw" name="lpcount0" pos="31:0" rst="0">
          <comment>hardware loop 0 counter</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dbg_loop_start1" protect="rw">
        <bits access="rw" name="lpstart1" pos="31:0" rst="0">
          <comment>hardware loop 1 start</comment>
        </bits>
      </reg>
      <reg name="dbg_loop_end1" protect="rw">
        <bits access="rw" name="lpend1" pos="31:0" rst="0">
          <comment>hardware loop 1 end</comment>
        </bits>
      </reg>
      <reg name="dbg_loop_cnt1" protect="rw">
        <bits access="rw" name="lpcount1" pos="31:0" rst="0">
          <comment>hardware loop 1 counter</comment>
        </bits>
      </reg>
      <hole size="288"/>
      <reg name="dbg_mestatus" protect="rw">
        <bits access="r" name="prv" pos="2:1" rst="3">
          <comment>Statically 2'b11 and cannot be altered</comment>
        </bits>
        <bits access="rw" name="int_en" pos="0" rst="0">
          <comment>Interrupt enable:
When an exception is encountered, the current value of MSTATUS is saved in MESTATUS.
When an eret instruction is executed, the value from MESTATUS replaces MSTATUS register.</comment>
        </bits>
      </reg>
      <hole size="59360"/>
      <reg name="dbg_mcpuid" protect="r">
        <bits access="r" name="base" pos="31:30" rst="0">
          <comment>read as 0, which means RV32I</comment>
        </bits>
        <bits access="r" name="extension" pos="25:0" rst="8392960">
          <comment>RI5CY only supports the I and M extension, plus the RI5CY non-standard extensions. This means bits 8(I), 12(M) and 23(X) are 1, the rest is 0.</comment>
        </bits>
      </reg>
      <reg name="dbg_mimpid" protect="r">
        <bits access="r" name="implementation" pos="31:16" rst="0">
      </bits>
        <bits access="r" name="source" pos="15:0" rst="32768">
      </bits>
      </reg>
      <hole size="448"/>
      <reg name="dbg_hartid" protect="r">
        <bits access="r" name="cluster_id" pos="10:5" rst="0">
          <comment>ID of the cluster</comment>
        </bits>
        <bits access="r" name="core_id" pos="3:0" rst="0">
          <comment>ID of the within the cluster</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_rtc.xml">
    <module category="RF_Dig" name="RF_RTC">
      <hole size="160*8"/>
      <reg name="reg_00_reg" protect="rw">
        <bits access="rw" name="reg_a0_bit" pos="15:8" rst="129">
          <comment>[8]enable_clk_dac_afc;
[9]dac_afc_bit select dig_rtc reg;
[10]dig_afc_bit_dr;
[13]step_offset_update;</comment>
        </bits>
        <bits access="rw" name="reg_a1_bit" pos="7:0" rst="192">
          <comment>[0]vcore_vrtc_pwr_sel source select  0:vcore_vrtc_pwr_sel reg; 1:pu_xtal from IDLE_UART
[1]pu_xtal_ana source select  0: pu_xtal_rtc from IDLE_UART; 1:pu_xtal reg
[6]pu_xtal reg  0:pull down XTAL enter LP mode; 1:pull up XTAL enter normal mode
[7]vcore_vrtc_pwr_sel reg  0: Vrtc power 1: Vcore power</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="reg_0c_reg" protect="rw">
        <bits access="rw" name="reg_a6_bit" pos="15:8" rst="0">
          <comment>RTC</comment>
        </bits>
        <bits access="rw" name="reg_a7_bit" pos="7:0" rst="84">
          <comment>[2]enable_clk26m_lp
[6]idle_uart sw resetn  0:reset 1:release reset</comment>
        </bits>
      </reg>
      <reg name="reg_10_reg" protect="rw">
        <bits access="rw" name="reg_a8_bit" pos="15:8" rst="128">
          <comment>RTC</comment>
        </bits>
        <bits access="rw" name="reg_a9_bit" pos="7:0" rst="64">
          <comment>RTC</comment>
        </bits>
      </reg>
      <reg name="reg_14_reg" protect="rw">
        <bits access="rw" name="reg_aa_bit" pos="15:8" rst="145">
          <comment>[9:8]lp_mode delay pu_xtal cycle select  2'b00: 4us; 2'b01:8us; 2'b10:12us; 2'b11:20us</comment>
        </bits>
        <bits access="rw" name="reg_ab_bit" pos="7:0" rst="0">
          <comment>RTC</comment>
        </bits>
      </reg>
      <reg name="reg_18_reg" protect="rw">
        <bits access="rw" name="reg_ac_bit" pos="15:8" rst="5">
      </bits>
        <bits access="rw" name="reg_ad_bit" pos="7:0" rst="0">
          <comment>32k gen div step_offset LP mode</comment>
        </bits>
      </reg>
      <reg name="reg_1c_reg" protect="rw">
        <bits access="rw" name="reg_ae_bit" pos="15:8" rst="0">
          <comment>32k gen div step_offset Normal mode</comment>
        </bits>
        <bits access="rw" name="reg_af_bit" pos="7:0" rst="1">
          <comment>[5]lp_mode_en_dr;
[4]lp_mode_en_reg;
[7]change_reg_flag_dr;
[6]change_reg_flag_reg;
[3]lp_mode_h_dr;
[2]lp_mode_h_reg;</comment>
        </bits>
      </reg>
      <reg name="reg_c0_reg" protect="rw">
        <bits access="rw" name="enable_clk_6p5m" pos="14" rst="1">
          <comment>to XTAL for input clk_26m enable</comment>
        </bits>
        <bits access="rw" name="dig_afc_bit_reg" pos="13:0" rst="8192">
          <comment>CAFC</comment>
        </bits>
      </reg>
      <reg name="reg_c4_reg" protect="rw">
        <bits access="rw" name="xtal26m_plls2_en" pos="15" rst="1">
          <comment>BBPLL2 ref clk 26m enable</comment>
        </bits>
        <bits access="rw" name="xtal26m_plls1_en" pos="14" rst="1">
          <comment>BBPLL1 ref clk 26m enable</comment>
        </bits>
        <bits access="rw" name="xtal26m_tsxadc_en" pos="13" rst="0">
          <comment>tsxadc clk 26m enable</comment>
        </bits>
        <bits access="rw" name="xtal_reg_bit" pos="12:9" rst="12">
          <comment>XTAL parameter</comment>
        </bits>
        <bits access="rw" name="xtal26m_pwadc_en" pos="8" rst="0">
          <comment>pwdadc clk 26m enable</comment>
        </bits>
        <bits access="rw" name="xtal_osc_ibit_l" pos="7:4" rst="0">
          <comment>xtal_osc_ibit lp mode</comment>
        </bits>
        <bits access="rw" name="xtal_osc_ibit_n" pos="3:0" rst="8">
          <comment>xtal_osc_ibit normal mode</comment>
        </bits>
      </reg>
      <reg name="reg_c8_reg" protect="rw">
        <bits access="rw" name="xtal26m_pllcal_en" pos="11" rst="0">
          <comment>RFPLL refcal clk 26m</comment>
        </bits>
        <bits access="rw" name="xtal26m_ts_en" pos="10" rst="0">
          <comment>oscadc clk 26m enable</comment>
        </bits>
        <bits access="rw" name="xtal_fixi_bit_l" pos="9:5" rst="4">
          <comment>xtal_fixi_bit lp mode</comment>
        </bits>
        <bits access="rw" name="xtal_fixi_bit_n" pos="4:0" rst="24">
          <comment>xtal_fixi_bit normal mode</comment>
        </bits>
      </reg>
      <reg name="reg_cc_reg" protect="rw">
        <bits access="rw" name="xtal26m_pmic_en" pos="14" rst="1">
          <comment>pmic clk 26m enable</comment>
        </bits>
        <bits access="rw" name="xtal26m_interface_en" pos="13" rst="1">
          <comment>clk_26m_interface enable</comment>
        </bits>
        <bits access="rw" name="xdrv_pmic_power_bit" pos="12:10" rst="7">
          <comment>xdrv pmic parameter</comment>
        </bits>
        <bits access="rw" name="xdrv_aux2_power_bit" pos="9:7" rst="7">
          <comment>xdrv aux2 parameter</comment>
        </bits>
        <bits access="rw" name="xdrv_aux1_power_bit" pos="6:4" rst="7">
          <comment>xdrv aux1 parameter</comment>
        </bits>
        <bits access="rw" name="xdrv_reg_bit" pos="3:0" rst="12">
          <comment>xdrv parameter</comment>
        </bits>
      </reg>
      <reg name="reg_d0_reg" protect="rw">
        <bits access="rw" name="xtal_hsel_l" pos="15" rst="1">
          <comment>xtal_hsel lp mode</comment>
        </bits>
        <bits access="rw" name="xtal_capbank_bit_l" pos="14:8" rst="64">
          <comment>CADC bit lp mode</comment>
        </bits>
        <bits access="rw" name="xtal_hsel_n" pos="7" rst="1">
          <comment>xtal_hsel normal mode</comment>
        </bits>
        <bits access="rw" name="xtal_capbank_bit_n" pos="6:0" rst="64">
          <comment>CADC bit normal mode</comment>
        </bits>
      </reg>
      <reg name="reg_d4_reg" protect="rw">
        <bits access="rw" name="rtc_reser_l" pos="15:0" rst="65280">
          <comment>RTC</comment>
        </bits>
      </reg>
      <reg name="reg_d8_reg" protect="rw">
        <bits access="rw" name="rtc_reser_n" pos="15:0" rst="65280">
          <comment>RTC</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="tsen_adc.xml">
    <module category="RF_Dig" name="TSEN_ADC_TOP">
      <hole size="(1)*32"/>
      <hole size="(1)*32"/>
      <hole size="(1)*32"/>
      <reg name="tst_tsen_bist_test" protect="rw">
        <bits access="r/w" name="tst_tsen_bist_bypass" pos="13:13" rst="0x0">
    </bits>
        <bits access="r/w" name="tst_tsen_bist_cfg0" pos="12:10" rst="0x0">
    </bits>
        <bits access="r/w" name="tst_tsen_bist_cfg1" pos="9:7" rst="0x0">
    </bits>
        <bits access="r/w" name="tst_tsen_bist_cfg2" pos="6:4" rst="0x0">
    </bits>
        <bits access="r/w" name="tst_tsen_bist_cfg3" pos="3:1" rst="0x0">
    </bits>
        <bits access="r" name="tst_tsen_bist_done" pos="0:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_bist_test1" protect="rw">
        <bits access="r/w" name="tst_tsen_bist_code_sel" pos="9:9" rst="0x0">
    </bits>
        <bits access="r/w" name="tst_tsen_bist_time_sel_cfg0" pos="8:7" rst="0x0">
    </bits>
        <bits access="r/w" name="tst_tsen_bist_time_sel_cfg1" pos="6:5" rst="0x0">
    </bits>
        <bits access="r/w" name="tst_tsen_bist_time_sel_cfg2" pos="4:3" rst="0x0">
    </bits>
        <bits access="r/w" name="tst_tsen_bist_time_sel_cfg3" pos="2:1" rst="0x0">
    </bits>
        <bits access="r/w" name="tst_tsen_bit_en" pos="0:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c0_test_res0" protect="ro">
        <bits access="r" name="tst_tsen_c0_res0" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c0_test_res1" protect="ro">
        <bits access="r" name="tst_tsen_c0_res1" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c0_test_res2" protect="ro">
        <bits access="r" name="tst_tsen_c0_res2" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c0_test_res3" protect="ro">
        <bits access="r" name="tst_tsen_c0_res3" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c1_test_res0" protect="ro">
        <bits access="r" name="tst_tsen_c1_res0" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c1_test_res1" protect="ro">
        <bits access="r" name="tst_tsen_c1_res1" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c1_test_res2" protect="ro">
        <bits access="r" name="tst_tsen_c1_res2" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c1_test_res3" protect="ro">
        <bits access="r" name="tst_tsen_c1_res3" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c2_test_res0" protect="ro">
        <bits access="r" name="tst_tsen_c2_res0" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c2_test_res1" protect="ro">
        <bits access="r" name="tst_tsen_c2_res1" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c2_test_res2" protect="ro">
        <bits access="r" name="tst_tsen_c2_res2" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c2_test_res3" protect="ro">
        <bits access="r" name="tst_tsen_c2_res3" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c3_test_res0" protect="ro">
        <bits access="r" name="tst_tsen_c3_res0" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c3_test_res1" protect="ro">
        <bits access="r" name="tst_tsen_c3_res1" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c3_test_res2" protect="ro">
        <bits access="r" name="tst_tsen_c3_res2" pos="15:0" rst="0x0">
    </bits>
      </reg>
      <reg name="tst_tsen_c3_test_res3" protect="ro">
        <bits access="r" name="tst_tsen_c3_res3" pos="15:0" rst="0x0">
    </bits>
      </reg>
    </module>
  </archive>
  <archive relative="dfe.xml">
    <module category="RF_Dig" name="DFE">
      <reg name="general_mode" protect="rw">
        <bits access="rw" name="clk_fbc_en_mode" pos="15" rst="0">
          <comment>for TXDP modules after RC
0: use unmasked 61.44MHz clk when polarIQ disabled
1: use 26m_fbc clk when polarIQ enabled</comment>
        </bits>
        <bits access="rw" name="reset_mode" pos="14" rst="0">
          <comment>1: use external resetn, 0-use sw/enable generated internal resetn for rxdp</comment>
        </bits>
        <bits access="rw" name="clk_dac_inv_mode" pos="13" rst="0">
          <comment>0: clk_dac
1: clk_dac invert</comment>
        </bits>
        <bits access="rw" name="clk_adc_inv_mode" pos="12" rst="0">
          <comment>0: clk_adc
1: clk_adc invert</comment>
        </bits>
        <bits access="rw" name="tx_mode" pos="11:8" rst="0">
          <comment>0:GGE, 1:NB, 2:LTE-1.4M, 3:LTE-3M, 4:LTE-5M, 5:LTE-10M, 6:LTE-15M, 7:LTE-20M, 8:WT, 9:eMTC</comment>
        </bits>
        <bits access="rw" name="rx_mode" pos="7:4" rst="0">
          <comment>0:GGE, 1:NB, 2:LTE-1.4M, 3:LTE-3M, 4:LTE-5M, 5:LTE-10M, 6:LTE-15M, 7:LTE-20M, 8:WT</comment>
        </bits>
        <bits access="rw" name="adc_mode" pos="3" rst="0">
          <comment>0: SDM mode
1: SAR mode</comment>
        </bits>
        <bits access="rw" name="adc_clk_mode" pos="2:1" rst="0">
          <comment>0:26M/30.72MHz
1:52M/61.44MHz
2:104M/122.88MHz</comment>
        </bits>
        <bits access="rw" name="zf_if_mode" pos="0" rst="0">
          <comment>0: ZF mode
1: IF mode</comment>
        </bits>
      </reg>
      <reg name="dfe_clock_gate_enable_reg" protect="rw">
        <bits access="rw" name="reg_clkgate_en" pos="14" rst="0">
          <comment>0: registers module clk gating enabled; 1: registers module clk always on</comment>
        </bits>
        <bits access="rw" name="txdp_loft_mode" pos="13" rst="0">
          <comment>0: RX CIC1 doesn't work in loft mode; 1: RX CIC1 works in loft mode</comment>
        </bits>
        <bits access="rw" name="et_rstn_ctrl" pos="11" rst="0">
          <comment>reset for ET, active low</comment>
        </bits>
        <bits access="rw" name="et_clk_en" pos="10" rst="0">
          <comment>clock enable for ET</comment>
        </bits>
        <bits access="rw" name="sw_resetn" pos="9" rst="1">
          <comment>sw controlled resetn for rxdp
0: assert reset
1: not reset</comment>
        </bits>
        <bits access="rw" name="clk_rate_convert_rg" pos="8" rst="0">
          <comment>DFE clock shift control.
0: clock shift disabled
1: clock shift enabled. When it is enabled, all DFE clocks except GSM TX clock are working in 17/16 normal frequency</comment>
        </bits>
        <bits access="rw" name="clk_26m_en" pos="7" rst="1">
          <comment>clock enable for BB GGE @26MHz</comment>
        </bits>
        <bits access="rw" name="clk_122p88m_en" pos="6" rst="1">
          <comment>clock enable for BB LTE @122.88MHz</comment>
        </bits>
        <bits access="rw" name="clk_61p44m_en" pos="5" rst="1">
          <comment>clock enable for BB NB/WT @61.44MHz</comment>
        </bits>
        <bits access="rw" name="txdp_nb_dfe_clk_en" pos="4" rst="0">
          <comment>clock enable for DFE NB/WT/LTE TX</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_dfe_clk_en" pos="3" rst="0">
          <comment>clock enable for DFE GSM TX</comment>
        </bits>
        <bits access="rw" name="rxdp_dfe_clk_en" pos="2" rst="0">
          <comment>clock enable for DFE RX</comment>
        </bits>
        <bits access="rw" name="txdp_clk_dac_en" pos="1" rst="0">
          <comment>clock enable for DAC</comment>
        </bits>
        <bits access="rw" name="rxdp_adc_clk_en" pos="0" rst="0">
          <comment>clock eanble for ADC</comment>
        </bits>
      </reg>
      <reg name="rxdp_dcc" protect="rw">
        <bits access="rw" name="rxdp_dcc_load" pos="6" rst="0">
          <comment>Start to load DC value, active high. Before next load, set it low firstly</comment>
        </bits>
        <bits access="rw" name="dcc_imgrej_rg" pos="5" rst="0">
          <comment>IQ swap in DC module
0: no swap
1. swap</comment>
        </bits>
        <bits access="rw" name="dcc_hold_en_rg" pos="4" rst="0">
          <comment>Hold DC accumulator calculation in DC calibration mode</comment>
        </bits>
        <bits access="rw" name="dcc_bypass_rg" pos="3" rst="0">
          <comment>This register is not used. But DC module bypass is actrually controlled by register rxdp_bypass_dcc and rxdp_bypass_mode_dcc</comment>
        </bits>
        <bits access="rw" name="dcc_dc_delta_ld_st_rg" pos="2" rst="0">
          <comment>Store initial value to DC accumulator at positive edge in DC cancel mode or DC calibration mode.</comment>
        </bits>
        <bits access="rw" name="dcc_dc_calib_en_rg" pos="1" rst="0">
          <comment>Load DC value in calibration mode to debug port, only used for debug purpose</comment>
        </bits>
        <bits access="rw" name="dcc_rx_calib_sel_rg" pos="0" rst="0">
          <comment>DC module work mode.
0: DC calibration mode
1: DC cancel mode</comment>
        </bits>
      </reg>
      <reg name="rxdp_dc_calib_re" protect="rw">
        <bits access="rw" name="rxdp_dc_calib_re_rg" pos="15:0" rst="0">
          <comment>DC real part value used in cancel mode</comment>
        </bits>
      </reg>
      <reg name="rxdp_dc_calib_im" protect="rw">
        <bits access="rw" name="rxdp_dc_calib_im_rg" pos="15:0" rst="0">
          <comment>DC image part value used in cancel mode</comment>
        </bits>
      </reg>
      <reg name="rxdp_dc_delta_re" protect="rw">
        <bits access="rw" name="rxdp_dc_delta_re_rg" pos="15:0" rst="0">
          <comment>Accumulator initial real part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register</comment>
        </bits>
      </reg>
      <reg name="rxdp_dc_delta_im" protect="rw">
        <bits access="rw" name="rxdp_dc_delta_im_rg" pos="15:0" rst="0">
          <comment>Accumulator initial image part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register</comment>
        </bits>
      </reg>
      <reg name="rxdp_dc_cr" protect="rw">
        <bits access="rw" name="conv_slow_bw_ct_rg" pos="11:9" rst="0">
          <comment>Slow convergence control, work with conv_mode_ct_rg register</comment>
        </bits>
        <bits access="rw" name="conv_fast_bw_ct_rg" pos="8:6" rst="0">
          <comment>Fast convergence control, work with conv_mode_ct_rg register</comment>
        </bits>
        <bits access="rw" name="conv_tmr_ct_rg" pos="5:2" rst="0">
          <comment>Duration time of DC calibration, which is based on sample unit</comment>
        </bits>
        <bits access="rw" name="conv_mode_ct_rg" pos="1:0" rst="0">
          <comment>DC convergence loop mode selection.
0: fast
1: slow
2: fast-&gt;slow
3: fast-&gt;hold</comment>
        </bits>
      </reg>
      <reg name="rxdp_gain_ct_reg" protect="rw">
        <bits access="rw" name="rxdp_gain_ct_load" pos="13" rst="0">
          <comment>load rxdp_gain_ct to DFE. Write it to 1b'0 before assert it</comment>
        </bits>
        <bits access="rw" name="rxdp_gain_ct_load_bypass" pos="12" rst="1">
          <comment>bypass rxdp_gain_ct_load</comment>
        </bits>
        <bits access="rw" name="rxdp_gain_ct" pos="10:0" rst="0">
          <comment>Gain BB control. [-24db, 47.9375db], step=1/16db</comment>
        </bits>
      </reg>
      <hole size="160"/>
      <reg name="rxdp_gdeq_coef0_rg_1" protect="rw">
        <bits access="rw" name="rxdp_gdeq_coef0_rg_lo" pos="15:0" rst="0">
          <comment>Bit [15:0] of RX group delay coefficient 0</comment>
        </bits>
      </reg>
      <reg name="rxdp_gdeq_coef0_rg_2" protect="rw">
        <bits access="rw" name="rxdp_gdeq_coef0_rg_hi" pos="3:0" rst="0">
          <comment>Bit [19:16] of RX group delay coefficient 0</comment>
        </bits>
      </reg>
      <reg name="rxdp_gdeq_coef1_rg_1" protect="rw">
        <bits access="rw" name="rxdp_gdeq_coef1_rg_lo" pos="15:0" rst="0">
          <comment>Bit [15:0] of RX group delay coefficient 1</comment>
        </bits>
      </reg>
      <reg name="rxdp_gdeq_coef1_rg_2" protect="rw">
        <bits access="rw" name="rxdp_gdeq_coef1_rg_hi" pos="3:0" rst="0">
          <comment>Bit [19:16] of RX group delay coefficient 1</comment>
        </bits>
      </reg>
      <reg name="rxdp_gdeq_coef2_rg_1" protect="rw">
        <bits access="rw" name="rxdp_gdeq_coef2_rg_lo" pos="15:0" rst="0">
          <comment>Bit [15:0] of RX group delay coefficient 2</comment>
        </bits>
      </reg>
      <reg name="rxdp_gdeq_coef2_rg_2" protect="rw">
        <bits access="rw" name="rxdp_gdeq_coef2_rg_hi" pos="3:0" rst="0">
          <comment>Bit [19:16] of RX group delay coefficient 2</comment>
        </bits>
      </reg>
      <reg name="rxdp_gdeq_coef3_rg_1" protect="rw">
        <bits access="rw" name="rxdp_gdeq_coef3_rg_lo" pos="15:0" rst="0">
          <comment>Bit [15:0] of RX group delay coefficient 3</comment>
        </bits>
      </reg>
      <reg name="rxdp_gdeq_coef3_rg_2" protect="rw">
        <bits access="rw" name="rxdp_gdeq_bp_lp_sel" pos="4" rst="0">
          <comment>1: LP
0: BP</comment>
        </bits>
        <bits access="rw" name="rxdp_gdeq_coef3_rg_hi" pos="3:0" rst="0">
          <comment>Bit [19:16] of RX group delay coefficient 3</comment>
        </bits>
      </reg>
      <reg name="rxdp_adc_wr_buf_fifo" protect="rw">
        <bits access="rw" name="rxdp_adc_smp_rate_rg" pos="6:1" rst="0">
          <comment>Read rate of DFE ADC FIFO, which depends on RX mode.
5'h00: GGE
5'h01: NB/WT</comment>
        </bits>
        <bits access="rw" name="rxdp_adc_wr_en_rg" pos="0" rst="1">
          <comment>Write enable of DFE ADC FIFO, active high</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="rxdp_dcc_valid_o_reg" protect="r">
        <bits access="r" name="rxdp_dcc_val_reg" pos="0" rst="0">
          <comment>Valid indication of DC value after assert rxdp_dcc_load to avoid metastability. rxdp_dcc_re_o and rxdp_dcc_im_o are stable when this register is high</comment>
        </bits>
      </reg>
      <reg name="rxdp_dcc_re_o_reg" protect="r">
        <bits access="r" name="rxdp_dcc_re_o" pos="15:0" rst="0">
          <comment>Real part of DC value, it is stable when rxdp_dcc_val_reg is high</comment>
        </bits>
      </reg>
      <reg name="rxdp_dcc_im_o_reg" protect="r">
        <bits access="r" name="rxdp_dcc_im_o" pos="15:0" rst="0">
          <comment>Image part of DC value, it is stable when rxdp_dcc_val_reg is high</comment>
        </bits>
      </reg>
      <reg name="rxdp_notch_ct" protect="rw">
        <bits access="rw" name="rxdp_notch_dataen0" pos="1" rst="1">
          <comment>Data enable of Notch DC
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="rxdp_notch_dataen1" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="rxdp_notch_a0_i_reg" protect="rw">
        <bits access="rw" name="rxdp_notch_a0_i" pos="11:0" rst="0">
          <comment>Coefficient a for real part of Notch DC</comment>
        </bits>
      </reg>
      <reg name="rxdp_notch_a0_q_reg" protect="rw">
        <bits access="rw" name="rxdp_notch_a0_q" pos="11:0" rst="0">
          <comment>Coefficient a for image part of Notch DC</comment>
        </bits>
      </reg>
      <reg name="rxdp_notch_k_reg" protect="rw">
        <bits access="rw" name="rxdp_notch_k0" pos="3:0" rst="0">
          <comment>Coefficient k of Notch DC</comment>
        </bits>
      </reg>
      <reg name="rxdp_mirror_remove" protect="rw">
        <bits access="rw" name="rxdp_mrrm_bw_sel" pos="1:0" rst="0">
          <comment>mrrm bandwidth selection</comment>
        </bits>
      </reg>
      <reg name="rxdp_notch2_ct" protect="rw">
        <bits access="rw" name="rxdp_notch2_dataen0" pos="1" rst="1">
          <comment>Data enable of Notch H 1st core
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="rxdp_notch2_dataen1" pos="0" rst="1">
          <comment>Data enable of Notch H 2nd core
0: disable
1: enable</comment>
        </bits>
      </reg>
      <reg name="rxdp_notch2_a0_i_reg" protect="rw">
        <bits access="rw" name="rxdp_notch2_a0_i" pos="11:0" rst="0">
          <comment>Coefficient a for real part of Notch H 1st core</comment>
        </bits>
      </reg>
      <reg name="rxdp_notch2_a0_q_reg" protect="rw">
        <bits access="rw" name="rxdp_notch2_a0_q" pos="11:0" rst="0">
          <comment>Coefficient a for image part of Notch H 1st core</comment>
        </bits>
      </reg>
      <reg name="rxdp_notch2_a1_i_reg" protect="rw">
        <bits access="rw" name="rxdp_notch2_a1_i" pos="11:0" rst="0">
          <comment>Coefficient a for real part of Notch H 2nd core</comment>
        </bits>
      </reg>
      <reg name="rxdp_notch2_a1_q_reg" protect="rw">
        <bits access="rw" name="rxdp_notch2_a1_q" pos="11:0" rst="0">
          <comment>Coefficient a for image part of Notch H 2nd core</comment>
        </bits>
      </reg>
      <reg name="rxdp_notch2_k_reg" protect="rw">
        <bits access="rw" name="rxdp_notch2_k0" pos="7:4" rst="0">
          <comment>Coefficient k of Notch H 1st core</comment>
        </bits>
        <bits access="rw" name="rxdp_notch2_k1" pos="3:0" rst="0">
          <comment>Coefficient k of Notch H 2nd core</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef0_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef0" pos="15:0" rst="0">
          <comment>Coefficient COEF0 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef1_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef1" pos="15:0" rst="0">
          <comment>Coefficient COEF1 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef2_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef2" pos="15:0" rst="0">
          <comment>Coefficient COEF2 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef3_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef3" pos="15:0" rst="0">
          <comment>Coefficient COEF3 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef4_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef4" pos="15:0" rst="0">
          <comment>Coefficient COEF4 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef5_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef5" pos="15:0" rst="0">
          <comment>Coefficient COEF5 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef6_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef6" pos="15:0" rst="0">
          <comment>Coefficient COEF6 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef7_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef7" pos="15:0" rst="0">
          <comment>Coefficient COEF7 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef8_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef8" pos="15:0" rst="0">
          <comment>Coefficient COEF8 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef9_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef9" pos="15:0" rst="0">
          <comment>Coefficient COEF9 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef10_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef10" pos="15:0" rst="0">
          <comment>Coefficient COEF10 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef11_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef11" pos="15:0" rst="0">
          <comment>Coefficient COEF11 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef12_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef12" pos="15:0" rst="0">
          <comment>Coefficient COEF12 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef13_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef13" pos="15:0" rst="0">
          <comment>Coefficient COEF13 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef14_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef14" pos="15:0" rst="0">
          <comment>Coefficient COEF14 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef15_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef15" pos="15:0" rst="0">
          <comment>Coefficient COEF15 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef16_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef16" pos="15:0" rst="0">
          <comment>Coefficient COEF16 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef17_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef17" pos="15:0" rst="0">
          <comment>Coefficient COEF17 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef18_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef18" pos="15:0" rst="0">
          <comment>Coefficient COEF18 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef19_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef19" pos="15:0" rst="0">
          <comment>Coefficient COEF19 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef20_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef20" pos="15:0" rst="0">
          <comment>Coefficient COEF20 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef21_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef21" pos="15:0" rst="0">
          <comment>Coefficient COEF21 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef22_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef22" pos="15:0" rst="0">
          <comment>Coefficient COEF22 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_aci_filter_coef23_reg" protect="rw">
        <bits access="rw" name="rxdp_aci_fir_coef23" pos="15:0" rst="0">
          <comment>Coefficient COEF23 of ACI filter</comment>
        </bits>
      </reg>
      <reg name="rxdp_mixer_freq_in_reg0" protect="rw">
        <bits access="rw" name="rxdp_mixer_freq_p0" pos="15:0" rst="0">
          <comment>Bit [15:0] of frequency offset for Mixer</comment>
        </bits>
      </reg>
      <reg name="rxdp_mixer_freq_in_reg1" protect="rw">
        <bits access="rw" name="rxdp_mixer_freq_p1" pos="7:0" rst="0">
          <comment>Bit [23:16] of frequency offset for Mixer</comment>
        </bits>
      </reg>
      <reg name="rxdp_rssi_reg" protect="rw">
        <bits access="rw" name="rxdp_rssi_ob_enable" pos="7" rst="0">
          <comment>Outband RSSI enable</comment>
        </bits>
        <bits access="rw" name="rxdp_rssi_ib_enable" pos="6" rst="0">
          <comment>Inband RSSI enable</comment>
        </bits>
        <bits access="rw" name="rxdp_rssi_ob_ushift" pos="5:3" rst="0">
          <comment>Outband RSSI ushift value</comment>
        </bits>
        <bits access="rw" name="rxdp_rssi_ib_ushift" pos="2:0" rst="0">
          <comment>Inband RSSI ushift value</comment>
        </bits>
      </reg>
      <reg name="rxdp_imbc_wa_reg" protect="rw">
        <bits access="rw" name="rxdp_imbc_wa" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="rxdp_imbc_wq_reg" protect="rw">
        <bits access="rw" name="rxdp_imbc_wq" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="rxdp_imbc_misc_reg" protect="rw">
        <bits access="rw" name="rxdp_imbc_bw_fast_ct_rg" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="rxdp_imbc_bw_slow_ct" pos="6:3" rst="0">
      </bits>
        <bits access="rw" name="rxdp_imbc_hold_dr" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rxdp_imbc_calc_rels" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rxdp_imbc_load" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="rxdp_imbc_wa_out_reg" protect="r">
        <bits access="r" name="rxdp_imbc_wa_out" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="rxdp_imbc_wq_out_reg" protect="r">
        <bits access="r" name="rxdp_imbc_wq_out" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="rxdp_imbc_out_reg" protect="r">
        <bits access="r" name="rxdp_imbc_val_out" pos="0:0" rst="0">
      </bits>
      </reg>
      <reg name="rxdpdecimatefordigrf" protect="rw">
        <bits access="rw" name="rxdp_deci_gge_delay_rg" pos="11:4" rst="0">
          <comment>delay count to discard some initial samples</comment>
        </bits>
        <bits access="rw" name="rxdp_deci_gge_deci_select" pos="3:1" rst="0">
          <comment>sample select in 12x data rate</comment>
        </bits>
        <bits access="rw" name="rxdp_deci_gge_sample_mode" pos="0" rst="0">
          <comment>sample number per symbol
0: 541K, 2x
1: 1.08M, 4x</comment>
        </bits>
      </reg>
      <reg name="rxdpmt_param" protect="rw">
        <bits access="rw" name="rxdp_deci_wt_deci_select" pos="9:6" rst="0">
          <comment>sample select in 192K data rate</comment>
        </bits>
        <bits access="rw" name="rxdp_deci_wt_sample_mode" pos="5:2" rst="0">
          <comment>0: 192K
1: 96K=192K/2
2: 64K=192K/3
....
15: 12K=192K/16</comment>
        </bits>
        <bits access="rw" name="rxdp_cic2_mode" pos="1:0" rst="0">
          <comment>sel CIC2 mode
00: mode0, divided by 40, 96K
01: mode1, divided by 20, 192K
10/11: mode2, divided by 10, 384K</comment>
        </bits>
      </reg>
      <reg name="rxdp_gain_ct_rf_reg" protect="rw">
        <bits access="rw" name="rxdp_gain_ct_rf_load" pos="13" rst="0">
          <comment>load rxdp_gain_ct_rf to DFE. Write it to 1b'0 before assert it</comment>
        </bits>
        <bits access="rw" name="rxdp_gain_ct_rf_load_bypass" pos="12" rst="1">
          <comment>bypass rxdp_gain_ct_rf_load</comment>
        </bits>
        <bits access="rw" name="rxdp_gain_ct_rf" pos="10:0" rst="0">
          <comment>Gain RF control. [-24db, 47.9375db], step=1/16db</comment>
        </bits>
      </reg>
      <reg name="start_max_min_ib_rssi_reg" protect="rw">
        <bits access="rw" name="start_max_min_ib_rssi" pos="0" rst="0">
          <comment>start inband RSSI max and min measurement</comment>
        </bits>
      </reg>
      <reg name="count_16lsb_ib_rssi_reg" protect="rw">
        <bits access="rw" name="count_16lsb_ib_rssi" pos="15:0" rst="30720">
          <comment>timer count[15:0] for max and min measurement report after start</comment>
        </bits>
      </reg>
      <reg name="count_16msb_ib_rssi_reg" protect="rw">
        <bits access="rw" name="count_16msb_ib_rssi" pos="15:0" rst="0">
          <comment>timer count[31:16] for max and min measurement report after start</comment>
        </bits>
      </reg>
      <reg name="load_max_min_ib_rssi_reg" protect="rw">
        <bits access="rw" name="load_max_min_ib_rssi" pos="0" rst="0">
          <comment>start to load max and min measurement report. Before next load, set it low firstly</comment>
        </bits>
      </reg>
      <reg name="rssi_min_ib_rssi" protect="r">
        <bits access="r" name="rssi_max_min_val_reg_ib_rssi" pos="10" rst="0">
          <comment>valid of max and min measurement report</comment>
        </bits>
        <bits access="r" name="rssi_min_reg_ib_rssi" pos="9:0" rst="0">
          <comment>inband RSSI min value</comment>
        </bits>
      </reg>
      <reg name="rssi_max_ib_rssi" protect="r">
        <bits access="r" name="rssi_max_reg_ib_rssi" pos="9:0" rst="0">
          <comment>inband RSSI max value, it is stable when rssi_max_min_val_reg_ib_rssi is high</comment>
        </bits>
      </reg>
      <reg name="int_ib_rssi" protect="rw">
        <bits access="r" name="rssi_int_ib_rssi" pos="2" rst="0">
          <comment>interrupt status to be able to start to load max and min measurement report</comment>
        </bits>
        <bits access="rw" name="int_mask_ib_rssi" pos="1" rst="0">
          <comment>interrupt mask</comment>
        </bits>
        <bits access="rw" name="int_clear_ib_rssi" pos="0" rst="0">
          <comment>interrupt clear</comment>
        </bits>
      </reg>
      <reg name="load_ib_rssi_reg" protect="rw">
        <bits access="rw" name="load_ib_rssi" pos="0" rst="0">
          <comment>indication to read instant measurement report</comment>
        </bits>
      </reg>
      <reg name="rssi_val_ib_rssi" protect="r">
        <bits access="r" name="rssi_val_reg_ib_rssi" pos="0" rst="0">
          <comment>valid of instant measurement report</comment>
        </bits>
      </reg>
      <reg name="rssi_ib_rssi" protect="r">
        <bits access="r" name="rssi_reg_ib_rssi" pos="9:0" rst="0">
          <comment>inband RSSI instant value</comment>
        </bits>
      </reg>
      <reg name="start_max_min_ob_rssi_reg" protect="rw">
        <bits access="rw" name="start_max_min_ob_rssi" pos="0" rst="0">
          <comment>start outband RSSI max and min measurement</comment>
        </bits>
      </reg>
      <reg name="count_16lsb_ob_rssi_reg" protect="rw">
        <bits access="rw" name="count_16lsb_ob_rssi" pos="15:0" rst="30720">
          <comment>timer count[15:0] for max and min measurement report after start</comment>
        </bits>
      </reg>
      <reg name="count_16msb_ob_rssi_reg" protect="rw">
        <bits access="rw" name="count_16msb_ob_rssi" pos="15:0" rst="0">
          <comment>timer count[31:16] for max and min measurement report after start</comment>
        </bits>
      </reg>
      <reg name="load_max_min_ob_rssi_reg" protect="rw">
        <bits access="rw" name="load_max_min_ob_rssi" pos="0" rst="0">
          <comment>indication to read max and min measurement report</comment>
        </bits>
      </reg>
      <reg name="rssi_max_min_val_ob_rssi" protect="r">
        <bits access="r" name="rssi_max_min_val_reg_ob_rssi" pos="0" rst="0">
          <comment>valid of max and min measurement report</comment>
        </bits>
      </reg>
      <reg name="rssi_min_ob_rssi" protect="r">
        <bits access="r" name="rssi_min_reg_ob_rssi" pos="9:0" rst="0">
          <comment>outband RSSI min value</comment>
        </bits>
      </reg>
      <reg name="rssi_max_ob_rssi" protect="r">
        <bits access="r" name="rssi_max_reg_ob_rssi" pos="9:0" rst="0">
          <comment>outband RSSI max value</comment>
        </bits>
      </reg>
      <reg name="int_ob_rssi" protect="rw">
        <bits access="r" name="rssi_int_ob_rssi" pos="2" rst="0">
          <comment>interrupt status to be able to start to load max and min measurement report</comment>
        </bits>
        <bits access="rw" name="int_mask_ob_rssi" pos="1" rst="0">
          <comment>interrupt mask</comment>
        </bits>
        <bits access="rw" name="int_clear_ob_rssi" pos="0" rst="0">
          <comment>interrupt clear</comment>
        </bits>
      </reg>
      <reg name="load_ob_rssi_reg" protect="rw">
        <bits access="rw" name="load_ob_rssi" pos="0" rst="0">
          <comment>indication to read instant measurement report</comment>
        </bits>
      </reg>
      <reg name="rssi_val_ob_rssi" protect="r">
        <bits access="r" name="rssi_val_reg_ob_rssi" pos="0" rst="0">
          <comment>valid of instant measurement report</comment>
        </bits>
      </reg>
      <reg name="rssi_wd_ob_rssi" protect="r">
        <bits access="r" name="rssi_reg_wd_ob_rssi" pos="9:0" rst="0">
          <comment>outband RSSI instant value for WD</comment>
        </bits>
      </reg>
      <reg name="rssi_up_ob_rssi" protect="r">
        <bits access="r" name="rssi_reg_up_ob_rssi" pos="9:0" rst="0">
          <comment>outband RSSI instant value for UP</comment>
        </bits>
      </reg>
      <reg name="rssi_dn_ob_rssi" protect="r">
        <bits access="r" name="rssi_reg_dn_ob_rssi" pos="9:0" rst="0">
          <comment>outband RSSI instant value for DN</comment>
        </bits>
      </reg>
      <reg name="digrf_rx_ctrl_reg" protect="rw">
        <bits access="rw" name="digrf_rx_rx_en_delay_counter" pos="6:3" rst="0">
          <comment>delay counter for rx_en</comment>
        </bits>
        <bits access="rw" name="digrf_rx_rx_iq_order" pos="2" rst="0">
          <comment>RX IQ swap</comment>
        </bits>
        <bits access="rw" name="digrf_rx_rxclk_polarity" pos="1" rst="0">
          <comment>RX clock invert or not</comment>
        </bits>
        <bits access="rw" name="digrf_rx_digrf_enable" pos="0" rst="1">
          <comment>enable digrf RX</comment>
        </bits>
      </reg>
      <reg name="digrf_tx_ctrl_reg" protect="rw">
        <bits access="rw" name="digrf_tx_txdata_out_timer" pos="15:8" rst="0">
          <comment>delay counter for tx_data</comment>
        </bits>
        <bits access="rw" name="digrf_tx_txclk_polarity" pos="1" rst="0">
          <comment>TX clock invert or not</comment>
        </bits>
        <bits access="rw" name="digrf_tx_digrf_stream_mode_enable" pos="0" rst="1">
          <comment>TX mode.
0: block mode
1: stream mode</comment>
        </bits>
      </reg>
      <reg name="rxdp_bypass_control_reg1" protect="rw">
        <bits access="rw" name="rxdp_bypass_uphb1" pos="15" rst="0">
          <comment>Interp. HBF1
0: SW bypass disable
1: SW bypass enable</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_gainbb" pos="14" rst="0">
          <comment>Gain_BB</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_notch2_2" pos="13" rst="0">
          <comment>Notrch(H) 2nd core</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_notch2_1" pos="12" rst="0">
          <comment>Notrch(H) 1st core</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_dnbh1" pos="11" rst="0">
          <comment>Deci. HBF1</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_aci_lpf" pos="10" rst="0">
          <comment>ACI Filter</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_rssi_ob" pos="9" rst="0">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_gainrf" pos="8" rst="0">
          <comment>Gain_RF</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_gdeq" pos="7" rst="0">
          <comment>Group Delay Equ</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_notch1_2" pos="6" rst="0">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_notch1_1" pos="5" rst="0">
          <comment>Notch(DC)</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mixer" pos="4" rst="0">
          <comment>Mixer</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_rc" pos="3" rst="0">
          <comment>RC</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_cic2" pos="2" rst="0">
          <comment>Deci.CIC2</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_dcc" pos="1" rst="0">
          <comment>DC Calib.&amp;Cancel</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_cic1" pos="0" rst="0">
          <comment>Deci.CIC1</comment>
        </bits>
      </reg>
      <reg name="rxdp_bypass_control_reg2" protect="rw">
        <bits access="rw" name="rxdp_bypass_dnhb2" pos="6" rst="0">
          <comment>dnhb2</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_imbc" pos="5" rst="0">
          <comment>imbc</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mrrm" pos="4" rst="0">
          <comment>mrrm</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_rssi_ib" pos="3" rst="0">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_deci_digrf" pos="2" rst="0">
          <comment>deci_digrf</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_uphb3" pos="1" rst="0">
          <comment>Interp. HBF3</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_uphb2" pos="0" rst="0">
          <comment>Interp. HBF2</comment>
        </bits>
      </reg>
      <reg name="rxdp_bypass_mode_control_reg1" protect="rw">
        <bits access="rw" name="rxdp_bypass_mode_uphb1" pos="15" rst="0">
          <comment>Interp. HBF1
0: bypass controlled by HW. HW bypass module automaticlly based on algorithm requirement
1: bypass controlled by SW. When it is set, rxdp_bypass_uphb1 will be used</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_gainbb" pos="14" rst="0">
          <comment>Gain_BB</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_notch2_2" pos="13" rst="0">
          <comment>Notrch(H) 2nd core</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_notch2_1" pos="12" rst="0">
          <comment>Notrch(H) 1st core</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_dnbh1" pos="11" rst="0">
          <comment>Deci. HBF1</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_aci_lpf" pos="10" rst="0">
          <comment>ACI Filter</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_rssi_ob" pos="9" rst="0">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_gainrf" pos="8" rst="0">
          <comment>Gain_RF</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_gdeq" pos="7" rst="0">
          <comment>Group Delay Equ</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_notch1_2" pos="6" rst="0">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_notch1_1" pos="5" rst="0">
          <comment>Notch(DC)</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_mixer" pos="4" rst="0">
          <comment>Mixer</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_rc" pos="3" rst="0">
          <comment>RC</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_cic2" pos="2" rst="0">
          <comment>Deci.CIC2</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_dcc" pos="1" rst="0">
          <comment>DC Calib.&amp;Cancel</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_cic1" pos="0" rst="0">
          <comment>Deci.CIC1</comment>
        </bits>
      </reg>
      <reg name="rxdp_bypass_mode_control_reg2" protect="rw">
        <bits access="rw" name="rxdp_bypass_mode_dnhb2" pos="6" rst="0">
          <comment>dnhb2</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_imbc" pos="5" rst="0">
          <comment>imbc</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_mrrm" pos="4" rst="0">
          <comment>mrrm</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_rssi_ib" pos="3" rst="0">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_deci_digrf" pos="2" rst="0">
          <comment>deci_digrf</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_uphb3" pos="1" rst="0">
          <comment>Interp. HBF3</comment>
        </bits>
        <bits access="rw" name="rxdp_bypass_mode_uphb2" pos="0" rst="0">
          <comment>Interp. HBF2</comment>
        </bits>
      </reg>
      <reg name="rxdp_dcc_re_real_reg" protect="r">
        <bits access="r" name="rxdp_dcc_re_real" pos="15:0" rst="0">
          <comment>instant value of rxdp_dcc_re</comment>
        </bits>
      </reg>
      <reg name="rxdp_dcc_im_real_reg" protect="r">
        <bits access="r" name="rxdp_dcc_im_real" pos="15:0" rst="0">
          <comment>instant value of rxdp_dcc_im</comment>
        </bits>
      </reg>
      <reg name="rssi_real_ib_rssi" protect="r">
        <bits access="r" name="rssi_reg_real_ib_rssi" pos="9:0" rst="0">
          <comment>instant value of rssi_reg_ib_rssi</comment>
        </bits>
      </reg>
      <reg name="rssi_wd_real_ob_rssi" protect="r">
        <bits access="r" name="rssi_reg_wd_real_ob_rssi" pos="9:0" rst="0">
          <comment>instant value of rssi_reg_wd_ob_rssi</comment>
        </bits>
      </reg>
      <reg name="rssi_up_real_ob_rssi" protect="r">
        <bits access="r" name="rssi_reg_up_real_ob_rssi" pos="9:0" rst="0">
          <comment>instant value of rssi_reg_up_ob_rssi</comment>
        </bits>
      </reg>
      <reg name="rssi_dn_real_ob_rssi" protect="r">
        <bits access="r" name="rssi_reg_dn_real_ob_rssi" pos="9:0" rst="0">
          <comment>instant value of rssi_reg_dn_ob_rssi</comment>
        </bits>
      </reg>
      <reg name="rxdp_imbc_wa_out_real_reg" protect="r">
        <bits access="r" name="rxdp_imbc_wa_out_real" pos="15:0" rst="0">
          <comment>instant value of rxdp_imbc_wa_out</comment>
        </bits>
      </reg>
      <reg name="rxdp_imbc_wq_out_real_reg" protect="r">
        <bits access="r" name="rxdp_imbc_wq_out_real" pos="15:0" rst="0">
          <comment>instant value of rxdp_imbc_wq_out</comment>
        </bits>
      </reg>
      <hole size="512"/>
      <reg name="txdp_gsm_a1" protect="rw">
        <bits access="rw" name="txdp_gsm_a1_rg" pos="11:0" rst="0">
          <comment>Coefficient a1 for PLL Equ.</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_a2" protect="rw">
        <bits access="rw" name="txdp_gsm_a2_rg" pos="11:0" rst="0">
          <comment>Coefficient a2 for PLL Equ.</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_b1" protect="rw">
        <bits access="rw" name="txdp_gsm_b1_rg" pos="11:0" rst="0">
          <comment>Coefficient b1 for PLL Equ.</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_b2" protect="rw">
        <bits access="rw" name="txdp_gsm_b2_rg" pos="11:0" rst="0">
          <comment>Coefficient b2 for PLL Equ.</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_g" protect="rw">
        <bits access="rw" name="txdp_gsm_g_rg" pos="15:0" rst="0">
          <comment>Bit [27:12] of gain for PLL Equ. It is valid when AFC adjustment is being enabled</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_equ_bypass_reg" protect="rw">
        <bits access="rw" name="txdp_gsm_g_load_bypass" pos="1" rst="1">
          <comment>Bypass load_g:
0: disable bypass
1: enable bypass</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_equ_bypass" pos="0" rst="1">
          <comment>Bypass PLL Equ:
0: disable bypass
1: enable bypass</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_equ_tx_shift_ct" protect="rw">
        <bits access="rw" name="txdp_gsm_int_dec_sel_rg" pos="6:5" rst="0">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_form_lsb_acc_en" pos="4" rst="0">
          <comment>4 LSB control</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_equ_tx_shift_ct_rg" pos="3:0" rst="0">
          <comment>Former output shift control</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_offset_value0_reg" protect="rw">
        <bits access="rw" name="txdp_gsm_offset_value0" pos="15:0" rst="43691">
          <comment>No use</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_offset_value1_reg" protect="rw">
        <bits access="rw" name="txdp_gsm_offset_value1" pos="7:0" rst="10">
          <comment>no use</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_tx_rx" protect="rw">
        <bits access="rw" name="txdp_gsm_freq_rg2" pos="4:2" rst="0">
          <comment>Bit [34:32] for GSM TX frequency</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_tx_rx_rg" pos="0" rst="1">
          <comment>use former output or not
0: RX don't use
1: TX use</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_freq0" protect="rw">
        <bits access="rw" name="txdp_gsm_freq_rg0" pos="15:0" rst="25200">
          <comment>Bit [15:0] for GSM TX frequency</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_freq1" protect="rw">
        <bits access="rw" name="txdp_gsm_freq_rg1" pos="15:0" rst="37415">
          <comment>Bit [31:16] for GSM TX frequency</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_freq_tx_offset" protect="rw">
        <bits access="rw" name="txdp_gsm_freq_tx_offset_rg" pos="15:0" rst="0">
          <comment>Offset add to GSM TX frequency</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="txdp_gsm_sdmpre_ct" protect="rw">
        <bits access="rw" name="txdp_gsm_mode_on_rg" pos="7" rst="0">
          <comment>Output control for TX SDM frequency
0: freqency from register
1: freqency from psdm, used by GSM or polarIQ</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_tri_wave_bypass_rg" pos="6" rst="0">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_shift_more_rg" pos="5" rst="0">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_offset_enable_rg" pos="4" rst="1">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_int_freq_sel_mode_rg" pos="3:1" rst="0">
          <comment>No use</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_form_bypass" pos="0" rst="0">
          <comment>GSM TX frequency control.
0: modulation signal act on GSM TX freqency
1: GSM TX freqency is fixed</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_misc_reg" protect="rw">
        <bits access="rw" name="gsm_freq_load_bypass_rg" pos="3" rst="0">
          <comment>GSM TX frequency load is at the same time of AFC adjustment or not
0: at the same time
1: not at the same time</comment>
        </bits>
        <bits access="rw" name="gsm_tx_fifo_rd_clr_rg" pos="2" rst="0">
          <comment>Clear bit for read point of GSM TX FIFO</comment>
        </bits>
        <bits access="rw" name="gsm_tx_fifo_wr_clr_rg" pos="1" rst="0">
          <comment>Clear bit for write point of GSM TX FIFO</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_pn_en" pos="0" rst="0">
          <comment>PN test enable</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_pn_switch_reg" protect="rw">
        <bits access="rw" name="txdp_gsm_pn_switch" pos="2:0" rst="0">
          <comment>The mode of pseudo random polynomial</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_encode_en_reg" protect="rw">
        <bits access="rw" name="txdp_gsm_encode_pos_neg" pos="1" rst="0">
          <comment>The initial phase selection of differential encoding</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_encode_en" pos="0" rst="1">
          <comment>The differential encoding enable for GSM TX data</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_g_ext_reg" protect="rw">
        <bits access="rw" name="txdp_gsm_g_ext" pos="11:0" rst="0">
          <comment>Bit [11:0] of gain for PLL Equ. It works with register txdp_gsm_g_rg</comment>
        </bits>
      </reg>
      <reg name="txdp_polar_delay_reg" protect="rw">
        <bits access="rw" name="txdp_polar1_delay" pos="14:5" rst="0">
          <comment>txdp polar1 delay</comment>
        </bits>
        <bits access="rw" name="txdp_polar0_delay" pos="4:0" rst="0">
          <comment>txdp polar0 delay</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_grp_dly_coff1_reg_l" protect="rw">
        <bits access="rw" name="gsm_grp_dly_coff1_rg_l" pos="15:0" rst="0">
          <comment>gsm_grp_dly_coff1_rg[15:0]</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_grp_dly_coff1_reg_m" protect="rw">
        <bits access="rw" name="gsm_grp_dly_coff1_rg_m" pos="3:0" rst="0">
          <comment>gsm_grp_dly_coff1_rg[19:16]</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_grp_dly_coff2_reg_l" protect="rw">
        <bits access="rw" name="gsm_grp_dly_coff2_rg_l" pos="15:0" rst="0">
          <comment>gsm_grp_dly_coff2_rg[15:0]</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_grp_dly_coff2_reg_m" protect="rw">
        <bits access="rw" name="gsm_grp_dly_coff2_rg_m" pos="3:0" rst="0">
          <comment>gsm_grp_dly_coff2_rg[19:16]</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_grp_dly_coff3_reg_l" protect="rw">
        <bits access="rw" name="gsm_grp_dly_coff3_rg_l" pos="15:0" rst="0">
          <comment>gsm_grp_dly_coff3_rg[15:0]</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_grp_dly_coff3_reg_m" protect="rw">
        <bits access="rw" name="gsm_grp_dly_coff3_rg_m" pos="3:0" rst="0">
          <comment>gsm_grp_dly_coff3_rg[19:16]</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_grp_dly_coff4_reg_l" protect="rw">
        <bits access="rw" name="gsm_grp_dly_coff4_rg_l" pos="15:0" rst="0">
          <comment>gsm_grp_dly_coff4_rg[15:0]</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_grp_dly_coff4_reg_m" protect="rw">
        <bits access="rw" name="gsm_grp_dly_coff4_rg_m" pos="3:0" rst="0">
          <comment>gsm_grp_dly_coff4_rg[19:16]</comment>
        </bits>
      </reg>
      <reg name="gsm_grp_dly_in_rg_reg" protect="rw">
        <bits access="rw" name="gsm_grp_dly_in_rg" pos="14:0" rst="0">
          <comment>register value from GSM upper and low branch</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_dpll_ctrl" protect="rw">
        <bits access="rw" name="gsm_grp_dly_position_rg" pos="7" rst="0">
          <comment>position of txdp_gdequ(2) in txdp_gsm
0: upper branch
1: low branch</comment>
        </bits>
        <bits access="rw" name="mdll_mode" pos="6:5" rst="1">
          <comment>MDLL mode:
0: 26MHz*7
1: 26MHz*8
2: 26MHz*9
3: 26MHz*10</comment>
        </bits>
        <bits access="rw" name="dfe_dpll_en" pos="4" rst="0">
          <comment>upper branch enable in txdp_gsm for 2P modulation</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_uplpf_bypass_rg" pos="3" rst="0">
          <comment>bypass txdp_uplpf(2) in txdp_gsm</comment>
        </bits>
        <bits access="rw" name="gsm_grp_dly_in_rg_load" pos="2" rst="0">
          <comment>load gsm_grp_dly_in_rg to DFE, assert it to load. Before load, write it to low firstly</comment>
        </bits>
        <bits access="rw" name="gsm_grp_dly_in_rg_mode" pos="1" rst="0">
          <comment>input mode for upper and low branch:
0: from DFE register, gsm_grp_dly_in_rg
1: from DFE function</comment>
        </bits>
        <bits access="rw" name="gsm_grp_dly_bypass" pos="0" rst="0">
          <comment>bypass txdp_gdequ(2) in txdp_gsm</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_vco_gain_reg" protect="rw">
        <bits access="rw" name="txdp_gsm_vco_gain_rg" pos="15:0" rst="0">
          <comment>vco_gain for upper branch</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_vco_prod_rg_lsb_reg" protect="rw">
        <bits access="rw" name="txdp_gsm_vco_prod_rg_lsb" pos="15:0" rst="0">
          <comment>register value for data_pm_dac[15:0]</comment>
        </bits>
      </reg>
      <reg name="txdp_gsm_vco_prod_rg_msb_reg" protect="rw">
        <bits access="rw" name="txdp_gsm_vco_prod_bypass" pos="15" rst="0">
          <comment>bypass  for data_pm_dac:
0: data_pm_dac from DFE function
1: data_pm_dac from DFE regsiter</comment>
        </bits>
        <bits access="rw" name="txdp_gsm_vco_prod_rg_msb" pos="14:0" rst="0">
          <comment>register value for data_pm_dac[30:16]</comment>
        </bits>
      </reg>
      <hole size="992"/>
      <reg name="txdp_wedge_gain_ct_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_gain_ct_load" pos="13" rst="0">
          <comment>load txdp_wedge_gain_ct to DFE. Write it to 1b'0 before assert it</comment>
        </bits>
        <bits access="rw" name="txdp_wedge_gain_ct_load_bypass" pos="12" rst="1">
          <comment>bypass txdp_wedge_gain_ct_load</comment>
        </bits>
        <bits access="rw" name="txdp_wedge_gain_ct" pos="10:0" rst="0">
          <comment>Gain control of NB/WT TX. [-24db, 47.9375db], step=1/16db</comment>
        </bits>
      </reg>
      <hole size="640"/>
      <reg name="txdp_wedge_pm_split_mode_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_flow_en" pos="1" rst="0">
      </bits>
        <bits access="rw" name="txdp_wedge_split_mode" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="txdp_wedge_am_shrink_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_shrink" pos="7:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="txdp_wedge_pm_shift_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_shift" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="txdp_wedge_am_p0_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p0" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p1_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p1" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p2_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p2" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p3_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p3" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p4_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p4" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p5_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p5" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p6_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p6" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p7_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p7" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p8_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p8" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p9_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p9" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p10_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p10" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p11_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p11" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p12_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p12" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p13_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p13" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p14_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p14" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p15_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p15" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_am_p16_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_am_p16" pos="9:0" rst="0">
          <comment>Amplitude compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p0_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p0" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p1_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p1" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p2_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p2" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p3_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p3" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p4_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p4" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p5_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p5" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p6_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p6" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p7_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p7" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p8_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p8" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p9_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p9" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p10_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p10" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p11_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p11" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p12_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p12" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p13_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p13" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p14_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p14" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p15_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p15" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <reg name="txdp_wedge_pm_p16_reg" protect="rw">
        <bits access="rw" name="txdp_wedge_pm_p16" pos="9:0" rst="0">
          <comment>Phase compensation curve of DPD</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="aclr_coef4" protect="rw">
        <bits access="rw" name="aclr_coef04" pos="9:0" rst="43">
          <comment>Coefficient 4 of ACLR filter</comment>
        </bits>
      </reg>
      <reg name="aclr_coef5" protect="rw">
        <bits access="rw" name="aclr_coef05" pos="9:0" rst="75">
          <comment>Coefficient 5 of ACLR filter</comment>
        </bits>
      </reg>
      <reg name="aclr_coef6" protect="rw">
        <bits access="rw" name="aclr_coef06" pos="9:0" rst="99">
          <comment>Coefficient 6 of ACLR filter</comment>
        </bits>
      </reg>
      <reg name="aclr_coef7" protect="rw">
        <bits access="rw" name="aclr_coef07" pos="9:0" rst="109">
          <comment>Coefficient 7 of ACLR filter</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="clk_dac_ctrl" protect="rw">
        <bits access="rw" name="clk_dac_test_mode" pos="7:4" rst="0">
          <comment>divide resource of clk_dac when test mode.
0: divide by 1
1: divide by 2
2: divide by 4
3: divide by 8
4: divide by 16
5: divide by 32
6: divide by 64
7: divide by 128
8: divide by 256
default: divide by 1</comment>
        </bits>
        <bits access="rw" name="clk_dac_test_sel" pos="3:2" rst="0">
          <comment>resource of clk_dac when test mode.
00: clk_26m
01: clk_245p76m
10: clk_fbc
11: clk_adc_gge_nb</comment>
        </bits>
        <bits access="rw" name="clk_dac_test_en" pos="1" rst="0">
          <comment>enable clk_dac when test mode</comment>
        </bits>
        <bits access="rw" name="clk_dac_sel" pos="0" rst="0">
          <comment>0: clk_dac is from function mode
1: clk_dac is from test mode</comment>
        </bits>
      </reg>
      <reg name="txdp_delay_reg" protect="rw">
        <bits access="rw" name="txdp_delay" pos="6:0" rst="0">
          <comment>txdp iq delay</comment>
        </bits>
      </reg>
      <reg name="aclr_coef0" protect="rw">
        <bits access="rw" name="aclr_coef00" pos="9:0" rst="1011">
          <comment>Coefficient 0 of ACLR filter</comment>
        </bits>
      </reg>
      <reg name="aclr_coef1" protect="rw">
        <bits access="rw" name="aclr_coef01" pos="9:0" rst="1013">
          <comment>Coefficient 1 of ACLR filter</comment>
        </bits>
      </reg>
      <reg name="aclr_coef2" protect="rw">
        <bits access="rw" name="aclr_coef02" pos="9:0" rst="1020">
          <comment>Coefficient 2 of ACLR filter</comment>
        </bits>
      </reg>
      <reg name="aclr_coef3" protect="rw">
        <bits access="rw" name="aclr_coef03" pos="9:0" rst="15">
          <comment>Coefficient 3 of ACLR filter</comment>
        </bits>
      </reg>
      <reg name="txdp_gdeq_coef0_rg_1" protect="rw">
        <bits access="rw" name="txdp_gdeq_coef0_rg_lo" pos="15:0" rst="0">
          <comment>Bit [15:0] of coefficient 0 of group delay equ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_gdeq_coef0_rg_2" protect="rw">
        <bits access="rw" name="txdp_gdeq_coef0_rg_hi" pos="3:0" rst="0">
          <comment>Bit [19:16] of coefficient 0 of group delay equ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_gdeq_coef1_rg_1" protect="rw">
        <bits access="rw" name="txdp_gdeq_coef1_rg_lo" pos="15:0" rst="0">
          <comment>Bit [15:0] of coefficient 1 of group delay equ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_gdeq_coef1_rg_2" protect="rw">
        <bits access="rw" name="txdp_gdeq_coef1_rg_hi" pos="3:0" rst="0">
          <comment>Bit [19:16] of coefficient 1 of group delay equ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_gdeq_coef2_rg_1" protect="rw">
        <bits access="rw" name="txdp_gdeq_coef2_rg_lo" pos="15:0" rst="0">
          <comment>Bit [15:0] of coefficient 2 of group delay equ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_gdeq_coef2_rg_2" protect="rw">
        <bits access="rw" name="txdp_gdeq_coef2_rg_hi" pos="3:0" rst="0">
          <comment>Bit [19:16] of coefficient 2 of group delay equ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_gdeq_coef3_rg_1" protect="rw">
        <bits access="rw" name="txdp_gdeq_coef3_rg_lo" pos="15:0" rst="0">
          <comment>Bit [15:0] of coefficient 3 of group delay equ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_gdeq_coef3_rg_2" protect="rw">
        <bits access="rw" name="txdp_gdeq_coef3_rg_hi" pos="3:0" rst="0">
          <comment>Bit [19:16] of coefficient 3 of group delay equ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef00" protect="rw">
        <bits access="rw" name="txdp_polariq_phase_dly" pos="15:12" rst="11">
          <comment>value to be delayed for phase part</comment>
        </bits>
        <bits access="rw" name="txdp_polariq_fir_coef0" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef01" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef1" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef02" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef2" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef03" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef3" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef04" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef4" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef05" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef5" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef06" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef6" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef07" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef7" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef08" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef8" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef09" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef9" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef010" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef10" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_polariq_fir_coef011" protect="rw">
        <bits access="rw" name="txdp_polariq_fir_coef11" pos="11:0" rst="0">
          <comment>Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_loft_offset_i_reg" protect="rw">
        <bits access="rw" name="txdp_loft_offset_i" pos="11:0" rst="0">
      </bits>
      </reg>
      <reg name="txdp_loft_offset_reg" protect="rw">
        <bits access="rw" name="txdp_loft_offset" pos="11:0" rst="0">
      </bits>
      </reg>
      <reg name="txdp_loft_phase_err_reg" protect="rw">
        <bits access="rw" name="txdp_loft_phase_err" pos="11:0" rst="0">
      </bits>
      </reg>
      <reg name="txdp_loft_amp_err_reg" protect="rw">
        <bits access="rw" name="txdp_loft_amp_err" pos="11:0" rst="0">
      </bits>
      </reg>
      <reg name="txdp_loft_rssi_reg" protect="r">
        <bits access="r" name="txdp_loft_rssi_err" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="txdp_loft_tone_amp_reg" protect="rw">
        <bits access="rw" name="txdp_loft_tone_amp" pos="11:0" rst="511">
      </bits>
      </reg>
      <reg name="txdp_loft_tone_fre_reg0" protect="rw">
        <bits access="rw" name="txdp_loft_tone_fre0" pos="15:0" rst="54613">
      </bits>
      </reg>
      <reg name="txdp_loft_tone_fre_reg1" protect="rw">
        <bits access="rw" name="txdp_loft_tone_fre1" pos="6:0" rst="0">
      </bits>
      </reg>
      <reg name="txdp_loft_misc0_reg" protect="rw">
        <bits access="rw" name="txdp_loft_sincos_en" pos="15:15" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_din_loft_sel" pos="14:14" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_cali_en" pos="13:13" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_cancel_bypass" pos="12:12" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_offset_dr" pos="11:11" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="txdp_loft_phase_err_dr" pos="10:10" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="txdp_loft_amp_err_dr" pos="9:9" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="txdp_loft_flg_loft_calib" pos="8:8" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_bpf_enable" pos="7:7" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="txdp_loft_bpf_bypass" pos="6:6" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="txdp_loft_rssi_ushift" pos="5:3" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_rssi_period_idx" pos="2:2" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_rssi_enable" pos="1:1" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_rssi_load" pos="0:0" rst="0">
      </bits>
      </reg>
      <reg name="txdp_loft_gain1_reg" protect="rw">
        <bits access="r" name="txdp_loft_rssi_val" pos="13" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_gain1_ct" pos="12:7" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_gain1_ct_dyn" pos="6:1" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_gain1_ct_sel" pos="0:0" rst="0">
      </bits>
      </reg>
      <reg name="data_format_ctrl" protect="rw">
        <bits access="rw" name="nb_tx_rx_loop" pos="8" rst="0">
          <comment>BB TX data loopback to BB RX</comment>
        </bits>
        <bits access="rw" name="rx_iq_swap" pos="7" rst="0">
          <comment>BB RX IQ swap. 1: swap; 0: normal</comment>
        </bits>
        <bits access="rw" name="tx_iq_swap" pos="6" rst="0">
          <comment>BB TX IQ swap. 1: swap; 0: normal</comment>
        </bits>
        <bits access="rw" name="adc_iq_swap" pos="5" rst="0">
          <comment>ADC IQ swap. 1: swap; 0: normal</comment>
        </bits>
        <bits access="rw" name="dac_iq_swap" pos="4" rst="0">
          <comment>DAC IQ swap. 1: swap; 0: normal</comment>
        </bits>
        <bits access="rw" name="rx_off_bin_en" pos="3" rst="0">
          <comment>BB RX. 0: two's complement 1: offset binary</comment>
        </bits>
        <bits access="rw" name="tx_off_bin_en" pos="2" rst="0">
          <comment>BB TX. 0: two's complement 1: offset binary</comment>
        </bits>
        <bits access="rw" name="adc_off_bin_en" pos="1" rst="0">
          <comment>RF ADC. 0: two's complement 1: offset binary</comment>
        </bits>
        <bits access="rw" name="dac_off_bin_en" pos="0" rst="1">
          <comment>RF DAC. 0: two's complement 1: offset binary</comment>
        </bits>
      </reg>
      <reg name="txdp_loft_rssi_reg_real" protect="r">
        <bits access="r" name="txdp_loft_rssi_err_real" pos="15:0" rst="0">
          <comment>instant value of txdp_loft_rssi_err</comment>
        </bits>
      </reg>
      <hole size="800"/>
      <reg name="temper_ct" protect="rw">
        <bits access="r" name="temper_pout_val_rg" pos="9" rst="0">
          <comment>valid indication of temper_dout after assert temper_pout_load to avoid metastability. Thetemper_dout is stable when this register is high</comment>
        </bits>
        <bits access="rw" name="temper_pout_load" pos="8" rst="0">
          <comment>start to load the result of temper_dout. Before next load, set it low firstly</comment>
        </bits>
        <bits access="rw" name="temper_lpf3_bypass" pos="7" rst="0">
      </bits>
        <bits access="rw" name="temper_ushift" pos="6:4" rst="0">
          <comment>bandwidth select</comment>
        </bits>
        <bits access="rw" name="temper_bw_sel" pos="3:2" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="temper_lpf_bypass" pos="1" rst="0">
      </bits>
        <bits access="rw" name="temper_hold_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="temper_dout_reg" protect="r">
        <bits access="r" name="temper_dout" pos="15:0" rst="32768">
          <comment>temper_dout value</comment>
        </bits>
      </reg>
      <reg name="osc_temp_clk_ct" protect="rw">
        <bits access="rw" name="temper_clk_en" pos="7" rst="0">
          <comment>clock enable for temper</comment>
        </bits>
        <bits access="rw" name="temper_clk_freq_sel" pos="6:5" rst="0">
          <comment>divide mode of clock from analog for Temcomp
0: not divide
1: 1/2 divide
2: 1/4 divide
3: 1/8 divide</comment>
        </bits>
        <bits access="rw" name="temper_clk_phase_sel" pos="4" rst="0">
          <comment>clock invert for Temcomp
0: clock invert disable
1: clock invert enable</comment>
        </bits>
        <bits access="rw" name="osc_clk_en" pos="3" rst="0">
          <comment>clock enable for temcomp</comment>
        </bits>
        <bits access="rw" name="osc_clk_freq_sel" pos="2:1" rst="0">
          <comment>divide mode of clock from analog for Temcomp
0: not divide
1: 1/2 divide
2: 1/4 divide
3: 1/8 divide</comment>
        </bits>
        <bits access="rw" name="osc_clk_phase_sel" pos="0" rst="0">
          <comment>clock invert for Temcomp
0: clock invert disable
1: clock invert enable</comment>
        </bits>
      </reg>
      <reg name="sdm_fre_hi_reg" protect="rw">
        <bits access="rw" name="sdm_force_bypass" pos="11" rst="0">
          <comment>force bypass, high valid</comment>
        </bits>
        <bits access="rw" name="sdm_bypass" pos="10" rst="1">
          <comment>bypass, high valid</comment>
        </bits>
        <bits access="rw" name="sdm_dither_bypass" pos="9" rst="1">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="sdm_fre_load" pos="8" rst="0">
          <comment>set sdm frequency value, high valid</comment>
        </bits>
        <bits access="rw" name="sdm_fre_hi" pos="7:0" rst="0">
          <comment>sdm frequency value, high 8 bits</comment>
        </bits>
      </reg>
      <reg name="sdm_fre_lo_reg" protect="rw">
        <bits access="rw" name="sdm_fre_lo" pos="15:0" rst="0">
          <comment>sdm frequency value, low 16 bits</comment>
        </bits>
      </reg>
      <reg name="temper_lpf_a11_rg" protect="rw">
        <bits access="rw" name="temper_lpf_a11" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temper_lpf_a12_rg" protect="rw">
        <bits access="rw" name="temper_lpf_a12" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temper_lpf_g1_rg" protect="rw">
        <bits access="rw" name="temper_lpf_g1" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temper_lpf_a21_rg" protect="rw">
        <bits access="rw" name="temper_lpf_a21" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temper_lpf_a22_rg" protect="rw">
        <bits access="rw" name="temper_lpf_a22" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temper_lpf_g2_rg" protect="rw">
        <bits access="rw" name="temper_lpf_g2" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temcom_lpf_a11_rg" protect="rw">
        <bits access="rw" name="temcom_lpf_a11" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temcom_lpf_a12_rg" protect="rw">
        <bits access="rw" name="temcom_lpf_a12" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temcom_lpf_g1_rg" protect="rw">
        <bits access="rw" name="temcom_lpf_g1" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temcom_lpf_a21_rg" protect="rw">
        <bits access="rw" name="temcom_lpf_a21" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temcom_lpf_a22_rg" protect="rw">
        <bits access="rw" name="temcom_lpf_a22" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temcom_lpf_g2_rg" protect="rw">
        <bits access="rw" name="temcom_lpf_g2" pos="13:0" rst="0">
          <comment>Coefficient of filter</comment>
        </bits>
      </reg>
      <reg name="temcom_temp_ct" protect="rw">
        <bits access="r" name="temcom_pout_val_rg" pos="9" rst="0">
          <comment>valid indication of temcom_pwd_dout after assert temcom_pout_load to avoid metastability. The temcom_pwd_dout is stable when this register is high</comment>
        </bits>
        <bits access="rw" name="temcom_pout_load" pos="8" rst="0">
          <comment>start to load the result of thermometer. Before next load, set it low firstly</comment>
        </bits>
        <bits access="rw" name="temcom_temp_lpf3_bypass" pos="7" rst="0">
          <comment>temperature calibration LPF bypass, high valid</comment>
        </bits>
        <bits access="rw" name="temcom_temp_ushift" pos="6:4" rst="0">
          <comment>temperature calibration LPF shift value
0 : left shift by 7 bit
1 : left shift by 6 bit
2 : left shift by 5 bit
3 : left shift by 4 bit
4 : left shift by 3 bit
5 : left shift by 2 bit
6 : left shift by 1 bit
7 : left shift by 0 bit</comment>
        </bits>
        <bits access="rw" name="temcom_temp_bw_sel" pos="3:2" rst="0">
          <comment>select badwidth</comment>
        </bits>
        <bits access="rw" name="temcom_temp_lpf_bypass" pos="1" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="temcom_temp_hold_en" pos="0" rst="0">
          <comment>no use</comment>
        </bits>
      </reg>
      <reg name="temcom_dout_reg" protect="r">
        <bits access="r" name="temcom_pwd_dout" pos="15:0" rst="32768">
          <comment>temcom result</comment>
        </bits>
      </reg>
      <reg name="temper_dout_real_reg" protect="r">
        <bits access="r" name="temper_dout_real" pos="15:0" rst="32768">
          <comment>instant value of temper_dout</comment>
        </bits>
      </reg>
      <reg name="temcom_dout_real_reg" protect="r">
        <bits access="r" name="temcom_pwd_dout_real" pos="15:0" rst="32768">
          <comment>instant value of temcom_pwd_dout</comment>
        </bits>
      </reg>
      <reg name="dfe_sw_clkgate_en_rg" protect="rw">
        <bits access="rw" name="dfe_sw_clkgate_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="mon_ct" protect="rw">
        <bits access="rw" name="dfe_monitor_swap" pos="4" rst="0">
          <comment>swap of dfe_monitor[15:8] and dfe_monitor[7:0]</comment>
        </bits>
        <bits access="rw" name="dfe_monitor_sel" pos="3:0" rst="0">
          <comment>dfe_monitor select</comment>
        </bits>
      </reg>
      <reg name="dac_offset_re_rg" protect="rw">
        <bits access="rw" name="dac_offset_re" pos="11:0" rst="0">
          <comment>The offset on DAC real part</comment>
        </bits>
      </reg>
      <reg name="dac_offset_im_rg" protect="rw">
        <bits access="rw" name="dac_offset_im" pos="11:0" rst="0">
          <comment>The offset on DAC image part</comment>
        </bits>
      </reg>
      <reg name="dac_tx_amp_re_rg" protect="rw">
        <bits access="rw" name="dac_tx_amp_re" pos="11:0" rst="0">
          <comment>The DAC real part on test mode</comment>
        </bits>
      </reg>
      <reg name="dac_tx_amp_im_rg" protect="rw">
        <bits access="rw" name="dac_tx_amp_im" pos="11:0" rst="0">
          <comment>The DAC image part on test mode</comment>
        </bits>
      </reg>
      <reg name="txdp_cic2_mode_rg" protect="rw">
        <bits access="rw" name="txdp_cic2_cfg_mode" pos="2:0" rst="0">
          <comment>Interp.CIC2 config mode for WT:
000: 60, 16K to 960K
001: 30, 32K to 960K
010: 25, 38.4K to 960K
011: 10, 96K to 960K
others: 5, 192K to 960K</comment>
        </bits>
      </reg>
      <reg name="data_dac_ctrl" protect="rw">
        <bits access="rw" name="data_dac_sel" pos="14:13" rst="0">
          <comment>select of function DAC data or test DAC data
00/01: select function DAC data including sine waveform
10: select test DAC data in txdp
11: select test DAC data in txdp</comment>
        </bits>
        <bits access="rw" name="sine_enable_rg" pos="12" rst="0">
          <comment>enable sine generation module</comment>
        </bits>
        <bits access="rw" name="rxdp_test_dac_en_rg" pos="11" rst="0">
          <comment>enable of test DAC data in rxdp</comment>
        </bits>
        <bits access="rw" name="rxdp_test_dac_sel_rg" pos="10:6" rst="0">
          <comment>select of test DAC data in rxdp</comment>
        </bits>
        <bits access="rw" name="txdp_test_dac_en_rg" pos="5" rst="0">
          <comment>enable of test DAC data in txdp</comment>
        </bits>
        <bits access="rw" name="txdp_test_dac_sel_rg" pos="4:0" rst="0">
          <comment>select of test DAC data in txdp</comment>
        </bits>
      </reg>
      <reg name="sincos_amp" protect="rw">
        <bits access="rw" name="sincos_amp_rg" pos="11:0" rst="511">
          <comment>sine amp</comment>
        </bits>
      </reg>
      <reg name="sincos_fre_lo" protect="rw">
        <bits access="rw" name="sincos_fre_rg_lo" pos="15:0" rst="54613">
          <comment>sine frequency[15:0]</comment>
        </bits>
      </reg>
      <reg name="sincos_fre_hi" protect="rw">
        <bits access="rw" name="txdp_bypass_loft" pos="8" rst="0">
          <comment>LOFT</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_loft" pos="7" rst="0">
          <comment>LOFT</comment>
        </bits>
        <bits access="rw" name="sincos_fre_rg_hi" pos="6:0" rst="0">
          <comment>sine frequence[22:16]</comment>
        </bits>
      </reg>
      <reg name="txdp_bypass_reg" protect="rw">
        <bits access="rw" name="txdp_bypass_uplpf1" pos="15" rst="0">
          <comment>UPLPF(1)</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_cic1" pos="14" rst="0">
          <comment>Interp. CIC1
0: SW bypass disable
1: SW bypass enable</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_uphb5" pos="13" rst="0">
          <comment>UPHBF(3)</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_uphb4" pos="12" rst="0">
          <comment>UPHBF(2)</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_gdeq" pos="11" rst="0">
          <comment>Group Delay Equ.</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_polariq_lpf" pos="10" rst="0">
          <comment>LPF of DPD only when PolarIQ</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_polariq_ampm" pos="9" rst="0">
          <comment>AMPM of DPD</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_polariq_split" pos="8" rst="0">
          <comment>Split of DPD</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_polariq" pos="7" rst="0">
          <comment>Whole DPD</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_rc" pos="6" rst="0">
          <comment>RC</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_gain" pos="5" rst="0">
          <comment>Gain</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_uphb3" pos="4" rst="0">
          <comment>UPHBF(5) when PolarIQ</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_uphb2" pos="3" rst="0">
          <comment>UPHBF(4) when PolarIQ</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_uphb1" pos="2" rst="0">
          <comment>UPHBF(1)</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_aclr_lpf" pos="1" rst="0">
          <comment>ACLR LPF</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_ampequ" pos="0" rst="0">
          <comment>ampequ</comment>
        </bits>
      </reg>
      <reg name="txdp_bypass_mode_reg" protect="rw">
        <bits access="rw" name="txdp_bypass_mode_uplpf1" pos="15" rst="0">
          <comment>UPLPF(1)</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_cic1" pos="14" rst="0">
          <comment>Interp. CIC1
0: bypass controlled by HW. HW bypass module automaticlly based on algorithm requirement
1: bypass controlled by SW. When it is set, txdp_bypass_cic1 will be used</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_uphb5" pos="13" rst="0">
          <comment>UPHBF(3)</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_uphb4" pos="12" rst="0">
          <comment>UPHBF(2)</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_gdeq" pos="11" rst="0">
          <comment>Group Delay Equ.</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_polariq_lpf" pos="10" rst="0">
          <comment>LPF of DPD only when PolarIQ</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_polariq_ampm" pos="9" rst="0">
          <comment>AMPM of DPD</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_polariq_split" pos="8" rst="0">
          <comment>Split of DPD</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_polariq" pos="7" rst="0">
          <comment>Whole DPD</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_rc" pos="6" rst="0">
          <comment>RC</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_gain" pos="5" rst="0">
          <comment>Gain</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_uphb3" pos="4" rst="0">
          <comment>UPHBF(5) when PolarIQ</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_uphb2" pos="3" rst="0">
          <comment>UPHBF(4) when PolarIQ</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_uphb1" pos="2" rst="0">
          <comment>UPHBF(1)</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_aclr_lpf" pos="1" rst="0">
          <comment>ACLR LPF</comment>
        </bits>
        <bits access="rw" name="txdp_bypass_mode_ampequ" pos="0" rst="0">
          <comment>ampequ</comment>
        </bits>
      </reg>
      <reg name="lvds_mode_reg" protect="rw">
        <bits access="rw" name="lvds_in_wt" pos="15" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="en_clk_lvds2dfe_bb_rx" pos="14" rst="0">
          <comment>clock enable for BB side when adc-dfe-lvds-bb, enable when lvds_rx_mode is 3</comment>
        </bits>
        <bits access="rw" name="en_clk_lvds2dfe_dfe_tx" pos="13" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="en_clk_lvds2dfe_dfe_rx" pos="12" rst="0">
          <comment>clock enable for ADC RX when adc-lvds-dfe-bb, enable when lvds_rx_mode is 1</comment>
        </bits>
        <bits access="rw" name="en_clk_lvds2dfe_rf_tx" pos="11" rst="0">
          <comment>clock enable for DAC TX when bb-dfe-lvds-dac, enable when lvds_rx_mode is 0</comment>
        </bits>
        <bits access="rw" name="en_clk_dfe2lvds" pos="10" rst="0">
          <comment>clock enable for lvds_tx, enable when lvds_tx_mode is 0/1/2/3</comment>
        </bits>
        <bits access="rw" name="lvds_rx_clk_mux_bb_rx" pos="9" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="lvds_rx_clk_mux_dfe_rx" pos="8" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="lvds_rx_clk_mux_rf_tx" pos="7" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="lvds_tx_clk_mode" pos="6:5" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="lvds_rx_mode" pos="4:3" rst="0">
          <comment>3: lvds_rx in adc-dfe-lvds-bb
2: lvds_rx in bb-lvds-dfe-dac
1: lvds_rx in adc-lvds-dfe-bb
0: lvds_rx in bb-dfe-lvds-dac</comment>
        </bits>
        <bits access="rw" name="lvds_tx_mode" pos="2:1" rst="0">
          <comment>3: lvds_tx in adc-dfe-lvds-bb
2: lvds_tx in bb-lvds-dfe-dac
1: lvds_tx in adc-lvds-dfe-bb
0: lvds_tx in bb-dfe-lvds-dac</comment>
        </bits>
        <bits access="rw" name="lvds_enable" pos="0" rst="0">
          <comment>LVDS enabled in DFE</comment>
        </bits>
      </reg>
      <reg name="lvds_swap_reg" protect="rw">
        <bits access="rw" name="dfe2lvds_bbtx_clkdiv" pos="7:6" rst="0">
          <comment>frequency select of dfe2lvds_clk when bb-lvds-dfe-dac.
0: 7.68MHz
1: 15.36MHz
2: 30.72MHz
3: 61.44MHz</comment>
        </bits>
        <bits access="rw" name="dfe2lvds_bbrx_clkdiv" pos="5:4" rst="0">
          <comment>frequency select of dfe2lvds_clk when adc-dfe-lvds-bb.
0: 7.68MHz
1: 15.36MHz
2: 30.72MHz
3: 61.44MHz</comment>
        </bits>
        <bits access="rw" name="lvds_rx_clk_ref_bb_rx" pos="3" rst="0">
          <comment>clock select in BB side when adc-dfe-lvds-bb and bb-lvds-dfe-dac
0: use LVDS clock
1: use BBPLL clock</comment>
        </bits>
        <bits access="rw" name="lvds2dfe_clk_dig_ref_ind" pos="2" rst="0">
          <comment>frequency indication of lvds2dfe_clk_dig_ref from LVDS
0: 122.88MHz
1: 61.44MHz</comment>
        </bits>
        <bits access="rw" name="lvds_rx_swap" pos="1" rst="0">
          <comment>iq swap on lvds2dfe_data</comment>
        </bits>
        <bits access="rw" name="lvds_tx_swap" pos="0" rst="0">
          <comment>iq swap on dfe2lvds_data</comment>
        </bits>
      </reg>
      <reg name="reserved_all_zeros_reg" protect="rw">
        <bits access="rw" name="rsv_all_zero" pos="15:0" rst="0">
          <comment>all zero bits, reserved for ECO</comment>
        </bits>
      </reg>
      <reg name="reserved_all_ones_reg" protect="rw">
        <bits access="rw" name="rsv_all_ones" pos="15:0" rst="65535">
          <comment>all one bits, reserved for ECO</comment>
        </bits>
      </reg>
      <reg name="pwr_rf_acc_len_reg" protect="rw">
        <bits access="rw" name="pwr_rf_acc_len_rg" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="pwr_rf_acc_misc_reg" protect="rw">
        <bits access="rw" name="pwr_rf_ushift_rg" pos="4:2" rst="0">
      </bits>
        <bits access="rw" name="pwr_rf_start_rg" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pwr_rf_polar_rg" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pwr_rf_acc_report_reg" protect="r">
        <bits access="r" name="pwr_rf_o" pos="11:1" rst="0">
      </bits>
        <bits access="r" name="pwr_rf_calc_done" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pwr_bb_acc_len_reg" protect="rw">
        <bits access="rw" name="pwr_bb_acc_len_rg" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="pwr_bb_acc_misc_reg" protect="rw">
        <bits access="rw" name="pwr_bb_ushift_rg" pos="3:1" rst="0">
      </bits>
        <bits access="rw" name="pwr_bb_start_rg" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pwr_bb_acc_report_reg" protect="r">
        <bits access="r" name="pwr_bb_o" pos="11:1" rst="0">
      </bits>
        <bits access="r" name="pwr_bb_calc_done" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="txdp_clk_gate_enable_reg" protect="rw">
        <bits access="rw" name="txdp_ampequ_clkgate_en" pos="14" rst="0">
      </bits>
        <bits access="rw" name="txdp_aclr_clkgate_en" pos="13" rst="0">
      </bits>
        <bits access="rw" name="txdp_uphb1_clkgate_en" pos="12" rst="0">
      </bits>
        <bits access="rw" name="txdp_uphb2_clkgate_en" pos="11" rst="0">
      </bits>
        <bits access="rw" name="txdp_uphb3_clkgate_en" pos="10" rst="0">
      </bits>
        <bits access="rw" name="txdp_gain_clkgate_en" pos="9" rst="0">
      </bits>
        <bits access="rw" name="txdp_rc_clkgate_en" pos="8" rst="0">
      </bits>
        <bits access="rw" name="txdp_dpd_clkgate_en" pos="7" rst="0">
      </bits>
        <bits access="rw" name="txdp_gdeq_clkgate_en" pos="6" rst="0">
      </bits>
        <bits access="rw" name="txdp_uphb4_clkgate_en" pos="5" rst="0">
      </bits>
        <bits access="rw" name="txdp_uphb5_clkgate_en" pos="4" rst="0">
      </bits>
        <bits access="rw" name="txdp_cic1_clkgate_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="txdp_loft_clkgate_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="txdp_uplpf_clkgate_en" pos="1" rst="0">
      </bits>
        <bits access="rw" name="txdp_sine_clkgate_en" pos="0" rst="0">
          <comment>1: clk always on, 0: clk gating by hardware</comment>
        </bits>
      </reg>
      <reg name="rxdp_clk_gate_enable_reg2" protect="rw">
        <bits access="rw" name="rxdp_rc_clkgate_en" pos="0" rst="0">
          <comment>1: clk always on, 0: clk gating by hardware</comment>
        </bits>
      </reg>
      <reg name="rxdp_clk_gate_enable_reg1" protect="rw">
        <bits access="rw" name="rxdp_imbc_clkgate_en" pos="15" rst="0">
      </bits>
        <bits access="rw" name="rxdp_mixer_clkgate_en" pos="14" rst="0">
      </bits>
        <bits access="rw" name="rxdp_notch1_clkgate_en" pos="13" rst="0">
      </bits>
        <bits access="rw" name="rxdp_gdeq_clkgate_en" pos="12" rst="0">
      </bits>
        <bits access="rw" name="rxdp_gainrf_clkgate_en" pos="11" rst="0">
      </bits>
        <bits access="rw" name="rxdp_ob_clkgate_en" pos="10" rst="0">
      </bits>
        <bits access="rw" name="rxdp_mrrm_clkgate_en" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rxdp_dnhb1_clkgate_en" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rxdp_aci_clkgate_en" pos="7" rst="0">
      </bits>
        <bits access="rw" name="rxdp_notch2_clkgate_en" pos="6" rst="0">
      </bits>
        <bits access="rw" name="rxdp_gainbb_clkgate_en" pos="5" rst="0">
      </bits>
        <bits access="rw" name="rxdp_dnhb2_clkgate_en" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rxdp_ib_clkgate_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rxdp_uphb1_clkgate_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rxdp_uphb2_clkgate_en" pos="1" rst="0">
      </bits>
        <bits access="rw" name="rxdp_deci_clkgate_en" pos="0" rst="0">
          <comment>1: clk always on, 0: clk gating by hardware</comment>
        </bits>
      </reg>
      <reg name="test_dac_bits_sel_register" protect="rw">
        <bits access="rw" name="test_dac_bits_sel" pos="2:0" rst="0">
          <comment>determine dac bits position when test mode.
0:[11:0], 1:[12:1], 2:[13:2], 3:[14:3], 4: [15:4]</comment>
        </bits>
      </reg>
      <reg name="txdp_ampequ_coef0_rg_1" protect="rw">
        <bits access="rw" name="txdp_ampequ_coef0_rg" pos="11:0" rst="0">
          <comment>Bit [11:0] of coefficient 0 of ampequ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_ampequ_coef1_rg_1" protect="rw">
        <bits access="rw" name="txdp_ampequ_coef1_rg" pos="11:0" rst="0">
          <comment>Bit [11:0] of coefficient 1 of ampequ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_ampequ_coef2_rg_1" protect="rw">
        <bits access="rw" name="txdp_ampequ_coef2_rg" pos="11:0" rst="0">
          <comment>Bit [11:0] of coefficient 2 of ampequ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_ampequ_coef3_rg_1" protect="rw">
        <bits access="rw" name="txdp_ampequ_coef3_rg" pos="11:0" rst="0">
          <comment>Bit [11:0] of coefficient 3 of ampequ. for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_ampequ_g" protect="rw">
        <bits access="rw" name="txdp_ampequ_g_rg" pos="15:0" rst="0">
          <comment>Bit [27:12] of gain for ampequ.  for NB/LTE/eMTC TX</comment>
        </bits>
      </reg>
      <reg name="txdp_ampequ_g_ext_reg" protect="rw">
        <bits access="rw" name="txdp_ampequ_g_ext" pos="11:0" rst="0">
          <comment>Bit [11:0] of gain for ampequ. It works with register txdp_ampequ_g_rg</comment>
        </bits>
      </reg>
      <reg name="fifo_sample_rate_reg1" protect="rw">
        <bits access="rw" name="fifo_a_smp_rate_rg" pos="13:7" rst="63">
          <comment>read interval for FIFO A</comment>
        </bits>
        <bits access="rw" name="fifo_b_smp_rate_rg" pos="6:0" rst="63">
          <comment>read interval for FIFO B</comment>
        </bits>
      </reg>
      <reg name="fifo_sample_rate_reg2" protect="rw">
        <bits access="rw" name="fifo_c_smp_rate_rg" pos="13:7" rst="7">
          <comment>read interval for FIFO C</comment>
        </bits>
        <bits access="rw" name="fifo_d_smp_rate_rg" pos="6:0" rst="7">
          <comment>read interval for FIFO D</comment>
        </bits>
      </reg>
      <reg name="fifo_status_reg" protect="r">
        <bits access="r" name="fifo_dump_full_status" pos="15" rst="0">
          <comment>FIFO dump full</comment>
        </bits>
        <bits access="r" name="fifo_dump_empty_status" pos="14" rst="0">
          <comment>FIFO dump empty</comment>
        </bits>
        <bits access="r" name="fifo_txdp_rc_full_status" pos="13" rst="0">
          <comment>FIFO txdp_rc full</comment>
        </bits>
        <bits access="r" name="fifo_txdp_rc_empty_status" pos="12" rst="0">
          <comment>FIFO txdp_rc empty</comment>
        </bits>
        <bits access="r" name="fifo_rxdp_rc_full_status" pos="11" rst="0">
          <comment>FIFO rxdp_rc full</comment>
        </bits>
        <bits access="r" name="fifo_rxdp_rc_empty_status" pos="10" rst="0">
          <comment>FIFO rxdp_rc empty</comment>
        </bits>
        <bits access="r" name="fifo_adc_full_status" pos="9" rst="0">
          <comment>FIFO ADC full</comment>
        </bits>
        <bits access="r" name="fifo_adc_empty_status" pos="8" rst="0">
          <comment>FIFO ADC empty, this FIFO used between ADC and DFE</comment>
        </bits>
        <bits access="r" name="fifo_d_full_status" pos="7" rst="0">
          <comment>FIFO D full</comment>
        </bits>
        <bits access="r" name="fifo_d_empty_status" pos="6" rst="0">
          <comment>FIFO D empty, this FIFO used when LVDS RX for bb-lvds-dfe-dac</comment>
        </bits>
        <bits access="r" name="fifo_c_full_status" pos="5" rst="0">
          <comment>FIFO C full</comment>
        </bits>
        <bits access="r" name="fifo_c_empty_status" pos="4" rst="0">
          <comment>FIFO C empty, this FIFO used when normal TX or LVDS TX for bb-lvds-dfe-dac</comment>
        </bits>
        <bits access="r" name="fifo_b_full_status" pos="3" rst="0">
          <comment>FIFO B full</comment>
        </bits>
        <bits access="r" name="fifo_b_empty_status" pos="2" rst="0">
          <comment>FIFO B empty, this FIFO used when LVDS RX for adc-dfe-lvds-bb</comment>
        </bits>
        <bits access="r" name="fifo_a_full_status" pos="1" rst="0">
          <comment>FIFO A full</comment>
        </bits>
        <bits access="r" name="fifo_a_empty_status" pos="0" rst="0">
          <comment>FIFO A empty, this FIFO used when normal RX or LVDS TX for adc-dfe-lvds-bb</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dfe_dump_reg" protect="rw">
        <bits access="rw" name="sel_clk_dump_w" pos="15:8" rst="0">
          <comment>clock frequency select when dump FIFO write
00000000: clk_122p88m_m
00000001: clk_61p44m_m
0000001x: clk_rxdp
000001xx: clk_rxdp_m
00001xxx: clk_txdp
0001xxxx: clk_245p76m_m(i.e., clk_txdp_m)
001xxxxx: lvds2dfe_clk
01xxxxxx: lvds2dfe_clk_dig_ref
1xxxxxxx: clk_pwd</comment>
        </bits>
        <bits access="rw" name="sel_clk_dump_r" pos="4" rst="0">
          <comment>clock frequency select when dump FIFO read
0: 122.88Mhz
1: 61.44MHz</comment>
        </bits>
        <bits access="rw" name="dfe_dump_en" pos="3" rst="0">
          <comment>enable dump</comment>
        </bits>
        <bits access="rw" name="dfe_dump_sel" pos="2:0" rst="0">
          <comment>dump node selection. It works with register sel_clk_dump_w for correct clock.
0: dump RX data from DFE, sel_clk_dump_w can be clk_122p88m_m/clk_61p44m_m/lvds2dfe_clk_dig_ref
1: dump TX data from BB, sel_clk_dump_w can be clk_122p88m_m/clk_61p44m_m/lvds2dfe_clk_dig_ref
2: dump RXDP data, sel_clk_dump_w can be clk_rxdp/clk_rxdp_m
3: dump TXDP data, sel_clk_dump_w can be clk_txdp/clk_245p76m_m(clk_txdp_m)/clk_pwd
others: dump data from LVDS, sel_clk_dump_w can be can be lvds2dfe_clk</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_dlpf.xml">
    <module category="RF_Dig" name="RF_DLPF">
      <reg name="dlpf_ctrl_reg" protect="rw">
        <bits access="rw" name="dlpf_clk_rdac_en" pos="15" rst="0">
          <comment>DLPF output clk_rdac enable.
0: disable
1: enable</comment>
        </bits>
        <bits access="rw" name="sdm_bypass" pos="14" rst="0">
          <comment>DLPF sdm bypass</comment>
        </bits>
        <bits access="rw" name="dlpf_mode" pos="13" rst="0">
          <comment>1'b0: digital DLPF
1'b1: analog DLPF</comment>
        </bits>
        <bits access="rw" name="vco_add_en" pos="12" rst="1">
          <comment>vco data add enable</comment>
        </bits>
        <bits access="rw" name="vco_rd_en" pos="11" rst="0">
          <comment>read vco data from fifo enable</comment>
        </bits>
        <bits access="rw" name="vco_wr_en" pos="10" rst="0">
          <comment>vco data write into fifo enable</comment>
        </bits>
        <bits access="rw" name="dlpf_vco_band_bit_sel" pos="9" rst="0">
          <comment>no use</comment>
        </bits>
        <bits access="rw" name="dlpf_dpll_rdac_clk_edgesel_bb" pos="8" rst="0">
          <comment>register to analog</comment>
        </bits>
        <bits access="rw" name="dlpf_mdll_num" pos="7:6" rst="1">
          <comment>DLPF MDLL mode
0: 26x7MHz
1: 26x8MHz
2: 26x9MHz
3: 26x10MHz</comment>
        </bits>
        <bits access="rw" name="dlpf_notch_bypass" pos="5" rst="0">
          <comment>DLPF notch bypass</comment>
        </bits>
        <bits access="rw" name="dlpf_clk_inv1_reg" pos="4" rst="0">
          <comment>DLPF output clock inverse</comment>
        </bits>
        <bits access="rw" name="dlpf_clk_inv0_reg" pos="3" rst="0">
          <comment>DLPF input clock inverse</comment>
        </bits>
        <bits access="rw" name="dlpf_lock_mode" pos="2" rst="1">
          <comment>DLPF lock mode</comment>
        </bits>
        <bits access="rw" name="dlpf_en" pos="1" rst="0">
          <comment>enable DLPF</comment>
        </bits>
        <bits access="rw" name="dlpf_rstn" pos="0" rst="0">
          <comment>no use</comment>
        </bits>
      </reg>
      <reg name="dlpf_dr_reg" protect="rw">
        <bits access="rw" name="dlpf_dr_mode" pos="14" rst="0">
          <comment>DLPF output direct control</comment>
        </bits>
        <bits access="rw" name="dlpf_dr_value" pos="13:0" rst="0">
          <comment>DLPF output direct value</comment>
        </bits>
      </reg>
      <reg name="dlpf_afc_pha_offset_reg" protect="rw">
        <bits access="rw" name="dlpf_afc_pha_offset" pos="15:0" rst="200">
          <comment>DLPF afc phase offset</comment>
        </bits>
      </reg>
      <reg name="dlpf_kdco_pha_offset_reg" protect="rw">
        <bits access="rw" name="dlpf_kdco_pha_offset" pos="15:0" rst="200">
          <comment>DLPF kdco phase offset</comment>
        </bits>
      </reg>
      <reg name="dlpf_gain_kp_afc_reg" protect="rw">
        <bits access="rw" name="dlpf_gain_kp_afc" pos="12:0" rst="47">
          <comment>DLPF gain kp afc</comment>
        </bits>
      </reg>
      <reg name="dlpf_gain_ki_afc_reg" protect="rw">
        <bits access="rw" name="dlpf_gain_ki_afc" pos="15:0" rst="80">
          <comment>DLPF gain ki afc</comment>
        </bits>
      </reg>
      <reg name="dlpf_gain_kp_2m_reg" protect="rw">
        <bits access="rw" name="dlpf_gain_kp_2m" pos="12:0" rst="47">
          <comment>DLPF gain kp 2m</comment>
        </bits>
      </reg>
      <reg name="dlpf_gain_ki_2m_reg" protect="rw">
        <bits access="rw" name="dlpf_gain_ki_2m" pos="15:0" rst="80">
          <comment>DLPF gain ki 2m</comment>
        </bits>
      </reg>
      <reg name="dlpf_gain_kp_200k_reg" protect="rw">
        <bits access="rw" name="dlpf_gain_kp_200k" pos="12:0" rst="47">
          <comment>DLPF gain kp 200k</comment>
        </bits>
      </reg>
      <reg name="dlpf_gain_ki_200k_reg" protect="rw">
        <bits access="rw" name="dlpf_gain_ki_200k" pos="15:0" rst="80">
          <comment>DLPF gain ki 200k</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir0_gain0_reg" protect="rw">
        <bits access="rw" name="dlpf_iir0_gain0" pos="15:0" rst="64358">
          <comment>DLPF IIR0 gain0[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir0_gain1_reg" protect="rw">
        <bits access="rw" name="dlpf_iir0_gain1" pos="15:0" rst="588">
          <comment>DLPF IIR0 gain1[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir1_gain0_reg" protect="rw">
        <bits access="rw" name="dlpf_iir1_gain0" pos="15:0" rst="61691">
          <comment>DLPF IIR1 gain0[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir1_gain1_reg" protect="rw">
        <bits access="rw" name="dlpf_iir1_gain1" pos="15:0" rst="1922">
          <comment>DLPF IIR1 gain1[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir_gain_msb_reg" protect="rw">
        <bits access="rw" name="dlpf_iir1_gain1_msb" pos="3" rst="0">
          <comment>DLPF IIR1 gain1[16]</comment>
        </bits>
        <bits access="rw" name="dlpf_iir1_gain0_msb" pos="2" rst="0">
          <comment>DLPF IIR1 gain0[16]</comment>
        </bits>
        <bits access="rw" name="dlpf_iir0_gain1_msb" pos="1" rst="0">
          <comment>DLPF IIR0 gain1[16]</comment>
        </bits>
        <bits access="rw" name="dlpf_iir0_gain0_msb" pos="0" rst="0">
          <comment>DLPF IIR0 gain0[16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_diff_sel_reg" protect="rw">
        <bits access="rw" name="dlpf_diff_sel" pos="2:0" rst="1">
          <comment>diff_sel[2:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_afc_diff_thr_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_afc_diff_thr_lsb" pos="15:0" rst="0">
          <comment>afc_diff_thr[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_afc_diff_thr_msb_reg" protect="rw">
        <bits access="rw" name="dlpf_afc_diff_thr_msb" pos="15:0" rst="2">
          <comment>afc_diff_thr[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_afc_cnt_thr_reg" protect="rw">
        <bits access="rw" name="dlpf_afc_cnt_thr" pos="15:0" rst="100">
          <comment>afc_cnt_thr</comment>
        </bits>
      </reg>
      <reg name="dlpf_lock_2m_diff_thr_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_lock_2m_diff_thr_lsb" pos="15:0" rst="0">
          <comment>lock_2m_diff_thr[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_lock_2m_diff_thr_msb_reg" protect="rw">
        <bits access="rw" name="dlpf_lock_2m_diff_thr_msb" pos="15:0" rst="2">
          <comment>lock_2m_diff_thr[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_lock_2m_cnt_thr_reg" protect="rw">
        <bits access="rw" name="dlpf_lock_2m_cnt_thr" pos="15:0" rst="200">
          <comment>lock_2m_cnt_thr</comment>
        </bits>
      </reg>
      <reg name="dlpf_lock_200k_diff_thr_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_lock_200k_diff_thr_lsb" pos="15:0" rst="0">
          <comment>lock_200k_diff_thr[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_lock_200k_diff_thr_msb_reg" protect="rw">
        <bits access="rw" name="dlpf_lock_200k_diff_thr_msb" pos="15:0" rst="2">
          <comment>lock_200k_diff_thr[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_lock_200k_cnt_thr_reg" protect="rw">
        <bits access="rw" name="dlpf_lock_200k_cnt_thr" pos="15:0" rst="600">
          <comment>lock_200k_cnt_thr</comment>
        </bits>
      </reg>
      <reg name="dlpf_timer0_cnt_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_timer0_cnt_lsb" pos="15:0" rst="100">
          <comment>timer0_cnt[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_timer0_cnt_msb_reg" protect="rw">
        <bits access="rw" name="dlpf_timer0_cnt_msb" pos="15:0" rst="0">
          <comment>timer0_cnt[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_timer1_cnt_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_timer1_cnt_lsb" pos="15:0" rst="100">
          <comment>timer1_cnt[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_timer1_cnt_msb_reg" protect="rw">
        <bits access="rw" name="dlpf_timer1_cnt_msb" pos="15:0" rst="0">
          <comment>timer1_cnt[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_timer2_cnt_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_timer2_cnt_lsb" pos="15:0" rst="100">
          <comment>timer2_cnt[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_timer2_cnt_msb_reg" protect="rw">
        <bits access="rw" name="dlpf_timer2_cnt_msb" pos="15:0" rst="0">
          <comment>timer2_cnt[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_capture_reg" protect="rw">
        <bits access="rw" name="dlpf_capture_en" pos="0" rst="0">
          <comment>DLPF capture enable to dump internal values</comment>
        </bits>
      </reg>
      <reg name="dlpf_status0_reg" protect="r">
        <bits access="r" name="dlpf_afc_code" pos="12:2" rst="0">
          <comment>real time afc_code</comment>
        </bits>
        <bits access="r" name="dlpf_det_status" pos="1:0" rst="0">
          <comment>DLPF detect status</comment>
        </bits>
      </reg>
      <reg name="dlpf_status1_reg" protect="r">
        <bits access="r" name="dlpf_kdco_code" pos="13:0" rst="0">
          <comment>read time kdco_code</comment>
        </bits>
      </reg>
      <reg name="dlpf_afc_code_status" protect="r">
        <bits access="r" name="dlpf_afc_code_reg" pos="10:0" rst="0">
          <comment>captured afc_code</comment>
        </bits>
      </reg>
      <reg name="dlpf_kdco_code_status" protect="r">
        <bits access="r" name="dlpf_kdco_code_reg" pos="13:0" rst="0">
          <comment>captured kdco_code</comment>
        </bits>
      </reg>
      <reg name="dlpf_tdc_code_reg" protect="r">
        <bits access="r" name="dlpf_tdc_code" pos="15:0" rst="0">
          <comment>tdc_code</comment>
        </bits>
      </reg>
      <reg name="dlpf_add_reg" protect="r">
        <bits access="r" name="dlpf_add" pos="15:0" rst="0">
          <comment>dlpf_add</comment>
        </bits>
      </reg>
      <reg name="dlpf_gain0_lsb_reg" protect="r">
        <bits access="r" name="dlpf_gain0_lsb" pos="15:0" rst="0">
          <comment>dlpf_gain0[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_gain0_msb_reg" protect="r">
        <bits access="r" name="dlpf_gain0_msb" pos="6:0" rst="0">
          <comment>dlpf_gain0[22:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_gain1_lsb_reg" protect="r">
        <bits access="r" name="dlpf_gain1_lsb" pos="15:0" rst="0">
          <comment>dlpf_gain1[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_gain1_msb_reg" protect="r">
        <bits access="r" name="dlpf_gain1_msb" pos="14:0" rst="0">
          <comment>dlpf_gain1[30:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_sum0_l_reg" protect="r">
        <bits access="r" name="dlpf_sum0_l" pos="15:0" rst="0">
          <comment>dlpf_sum0[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_sum0_m_reg" protect="r">
        <bits access="r" name="dlpf_sum0_m" pos="15:0" rst="0">
          <comment>dlpf_sum0[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_sum0_h_reg" protect="r">
        <bits access="r" name="dlpf_sum0_h" pos="6:0" rst="0">
          <comment>dlpf_sum0[38:32]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir0_sum0_l_reg" protect="r">
        <bits access="r" name="dlpf_iir0_sum0_l" pos="15:0" rst="0">
          <comment>iir0_sum0[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir0_sum0_m_reg" protect="r">
        <bits access="r" name="dlpf_iir0_sum0_m" pos="15:0" rst="0">
          <comment>iir0_sum0[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir0_sum0_h_reg" protect="r">
        <bits access="r" name="dlpf_iir0_sum0_h" pos="11:0" rst="0">
          <comment>iir0_sum0[43:32]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir0_sum0_reg_l_reg" protect="r">
        <bits access="r" name="dlpf_iir0_sum0_reg_l" pos="15:0" rst="0">
          <comment>iir0_sum0_reg[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir0_sum0_reg_m_reg" protect="r">
        <bits access="r" name="dlpf_iir0_sum0_reg_m" pos="15:0" rst="0">
          <comment>iir0_sum0_reg[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir0_sum0_reg_h_reg" protect="r">
        <bits access="r" name="dlpf_iir0_sum0_reg_h" pos="11:0" rst="0">
          <comment>iir0_sum0_reg[43:32]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir0_data_lsb_reg" protect="r">
        <bits access="r" name="dlpf_iir0_data_lsb" pos="15:0" rst="0">
          <comment>iir0_data[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir0_data_msb_reg" protect="r">
        <bits access="r" name="dlpf_iir0_data_msb" pos="15:0" rst="0">
          <comment>iir0_data[31:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir1_sum0_l_reg" protect="r">
        <bits access="r" name="dlpf_iir1_sum0_l" pos="15:0" rst="0">
          <comment>iir1_sum0[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir1_sum0_m_reg" protect="r">
        <bits access="r" name="dlpf_iir1_sum0_m" pos="15:0" rst="0">
          <comment>iir1_sum0[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir1_sum0_h_reg" protect="r">
        <bits access="r" name="dlpf_iir1_sum0_h" pos="11:0" rst="0">
          <comment>iir1_sum0[43:32]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir1_sum0_reg_l_reg" protect="r">
        <bits access="r" name="dlpf_iir1_sum0_reg_l" pos="15:0" rst="0">
          <comment>iir1_sum0_reg[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir1_sum0_reg_m_reg" protect="r">
        <bits access="r" name="dlpf_iir1_sum0_reg_m" pos="15:0" rst="0">
          <comment>iir1_sum0_reg[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir1_sum0_reg_h_reg" protect="r">
        <bits access="r" name="dlpf_iir1_sum0_reg_h" pos="11:0" rst="0">
          <comment>iir1_sum0_reg[43:32]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir1_data_lsb_reg" protect="r">
        <bits access="r" name="dlpf_iir1_data_lsb" pos="15:0" rst="0">
          <comment>iir1_data[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir1_data_msb_reg" protect="r">
        <bits access="r" name="dlpf_iir1_data_msb" pos="15:0" rst="0">
          <comment>iir1_data[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_lpf2_data_lsb_reg" protect="r">
        <bits access="r" name="dlpf_lpf2_data_lsb" pos="15:0" rst="0">
          <comment>lpf2_data[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_lpf2_data_msb_reg" protect="r">
        <bits access="r" name="dlpf_lpf2_data_msb" pos="15:0" rst="0">
          <comment>lpf2_data[31:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_ctrl_bit_reg" protect="rw">
        <bits access="rw" name="dlpf_ctrl_bit" pos="15:0" rst="0">
          <comment>DLPF reserved control bit.
[15:3] reserved
[1] IIR2 bypass
[0] IIR1 bypass</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir3_ctrl_reg" protect="rw">
        <bits access="r" name="dlpf_iir3_val_reg" pos="14" rst="0">
          <comment>DLPF IIR3 output valid</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_data_sel" pos="13" rst="0">
          <comment>input data select: 1'b0: gro output 1'b1: dlpf notch output</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_load_reg" pos="12" rst="0">
          <comment>load DLPF IIR3 output</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_dsc_cnt" pos="11:4" rst="0">
          <comment>decimator start point in dnsc</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_dsc_bypass" pos="3" rst="1">
          <comment>bypass 256 dnsc</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_clk_inv" pos="2" rst="0">
          <comment>DLPF IIR3 input clock inverse</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_data_valid" pos="1" rst="0">
          <comment>enable DLPF IIR3</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_rstn" pos="0" rst="0">
          <comment>reset DLPF IIR3, active low</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir3_a11_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_iir3_a11_lsb" pos="15:0" rst="0">
          <comment>a11[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir3_a12_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_iir3_a12_lsb" pos="15:0" rst="0">
          <comment>a12[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir3_a21_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_iir3_a21_lsb" pos="15:0" rst="0">
          <comment>a21[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir3_a_msb_reg" protect="rw">
        <bits access="rw" name="dlpf_iir3_a21_msb" pos="11:8" rst="0">
          <comment>a21[19:16]</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_a12_msb" pos="7:4" rst="0">
          <comment>a12[19:16]</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_a11_msb" pos="3:0" rst="0">
          <comment>a11[19:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir3_g1_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_iir3_g1_lsb" pos="15:0" rst="0">
          <comment>g1[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir3_g2_lsb_reg" protect="rw">
        <bits access="rw" name="dlpf_iir3_g2_lsb" pos="15:0" rst="0">
          <comment>g2[15:0]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir3_g_msb_reg" protect="rw">
        <bits access="rw" name="dlpf_iir3_g1_msb" pos="7:4" rst="0">
          <comment>g2[19:16]</comment>
        </bits>
        <bits access="rw" name="dlpf_iir3_g2_msb" pos="3:0" rst="0">
          <comment>g1[19:16]</comment>
        </bits>
      </reg>
      <reg name="dlpf_iir3_data" protect="r">
        <bits access="r" name="dlpf_iir3_data_reg" pos="15:0" rst="0">
          <comment>IIR3 output</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rf_et.xml">
    <module category="RF_Dig" name="RF_ET">
      <reg name="mod_sel" protect="rw">
        <bits access="rw" name="datarate_sel" pos="15:9" rst="0">
          <comment>input iq_in and clk_in rate ratio
          0: 1:1
          1: 1:2
          2: 1:3
          ....</comment>
        </bits>
        <bits access="rw" name="vidwide_sel" pos="8:2" rst="0">
          <comment>input ET_CLK signal:
          0: wide half clk
          1: wide 1 clk
          2: wide 2 clk
          ...
          127: wide 127 clk</comment>
        </bits>
        <bits access="rw" name="databit_sel" pos="1:0" rst="0">
          <comment>0: IQ sel IQ_IN[13:2]
          1: IQ sel IQ_IN[12:1]
          2: IQ sel IQ_IN[11:0]</comment>
        </bits>
      </reg>
      <reg name="dly_cfg" protect="rw">
        <bits access="rw" name="dly_frac" pos="9:6" rst="0">
          <comment>data to ETAPC frac delay: 1/16 datarate step, 015</comment>
        </bits>
        <bits access="rw" name="dly_int" pos="5:0" rst="0">
          <comment>data to ETAPC int delay: 2us, 063</comment>
        </bits>
      </reg>
      <reg name="dtr_cfg0" protect="rw">
        <bits access="rw" name="dtr_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="dtr_index" pos="2:0" rst="0">
      </bits>
      </reg>
      <reg name="dtr_cfg1" protect="rw">
        <bits access="rw" name="dtr_norm" pos="10:0" rst="0">
          <comment>Q0</comment>
        </bits>
      </reg>
      <reg name="dtr_cfg2" protect="rw">
        <bits access="rw" name="dtr_denorm" pos="5:0" rst="0">
          <comment>Q15</comment>
        </bits>
      </reg>
      <reg name="fir_cfg" protect="rw">
        <bits access="rw" name="cic2_en" pos="2" rst="0">
          <comment>cic fir enable</comment>
        </bits>
        <bits access="rw" name="cic1_en" pos="1" rst="0">
          <comment>cic fir enable</comment>
        </bits>
        <bits access="rw" name="hb_en" pos="0" rst="0">
          <comment>hb fir enable</comment>
        </bits>
      </reg>
      <reg name="iir_cfg" protect="rw">
        <bits access="rw" name="iir_en" pos="5" rst="0">
      </bits>
        <bits access="rw" name="iir_step" pos="4:3" rst="0">
      </bits>
        <bits access="rw" name="iir_alpha" pos="2:0" rst="0">
      </bits>
      </reg>
      <reg name="notch_cfg0" protect="rw">
        <bits access="rw" name="notch_en" pos="4" rst="0">
      </bits>
        <bits access="rw" name="notch_k" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="notch_cfg1" protect="rw">
        <bits access="rw" name="notch_bq" pos="11:0" rst="0">
      </bits>
      </reg>
      <reg name="notch_cfg2" protect="rw">
        <bits access="rw" name="notch_bi" pos="11:0" rst="0">
      </bits>
      </reg>
      <reg name="modif_cfg0" protect="rw">
        <bits access="rw" name="modif_mfact" pos="13:0" rst="0">
      </bits>
      </reg>
      <reg name="modif_cfg1" protect="rw">
        <bits access="rw" name="modif_afacf" pos="13:0" rst="0">
      </bits>
      </reg>
      <reg name="tpc_cfg" protect="rw">
        <bits access="rw" name="tpc_fact0" pos="13:0" rst="0">
      </bits>
      </reg>
      <reg name="volt_cfg" protect="rw">
        <bits access="rw" name="volt_fact" pos="12:0" rst="0">
      </bits>
      </reg>
      <reg name="clip_cfg0" protect="rw">
        <bits access="rw" name="clip_factl" pos="12:0" rst="0">
      </bits>
      </reg>
      <reg name="clip_cfg1" protect="rw">
        <bits access="rw" name="clip_facth" pos="12:0" rst="0">
      </bits>
      </reg>
      <reg name="dump_cfg" protect="rw">
        <bits access="rw" name="dump_en" pos="12" rst="0">
      </bits>
        <bits access="rw" name="dump_dn_ph" pos="11:8" rst="0">
      </bits>
        <bits access="rw" name="dump_dn_sel" pos="7:4" rst="0">
      </bits>
        <bits access="rw" name="dump_sel" pos="3:0" rst="0">
          <comment>0  :   {iq_re       , iq_im[11:0]     }
          1  :   {hb_re       , hb_im[11:0]     }
          2  :   {env_dato    , 16'h0           }
          3  :   {dlyint_dato , 16'h0           }
          4  :   {dlyfrac_dato, 16'h0           }
          5  :   {dtr_dato    , 16'h0           }
          6  :   {iir_dato    , 16'h0           }
          7  :   {log_dato    , 16'h0           }
          8  :   {modif_dato  , 16'h0           }
          9  :   {tpc_dato    , 16'h0           }
          10 :   {p2v_dato    , 16'h0           }
          11 :   {volt_dato   , 16'h0           }
          12 :   {cic1_dato   , 16'h0           }
          13 :   {notch_dato  , 16'h0           }
          14 :   {cic2_dato   , 16'h0           }
          15 :   {clip_dato   , 16'h0           }</comment>
        </bits>
      </reg>
      <reg name="et_start_cfg" protect="rw">
        <bits access="rw" name="sw_cgen" pos="1" rst="0">
          <comment>0: hardware auto open clock
          1: software force open clock</comment>
        </bits>
        <bits access="rw" name="et_start" pos="0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_bb_ifc.xml">
    <module category="wcn" name="WCN_BB_IFC">
      <reg name="ch_0__control" protect="w">
        <bits access="w" name="auto_disable" pos="4" rst="0">
          <comment>Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt.</comment>
        </bits>
        <bits access="w" name="disable" pos="1" rst="0">
          <comment>Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled.</comment>
        </bits>
        <bits access="w" name="enable" pos="0" rst="0">
          <comment>Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.</comment>
        </bits>
      </reg>
      <reg name="ch_0__status" protect="r">
        <bits access="r" name="i3_4f" pos="19" rst="0">
          <comment>Three Quarter of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="i4f" pos="18" rst="0">
          <comment>Quarter of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="ihf" pos="17" rst="0">
          <comment>Half of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="ief" pos="16" rst="0">
          <comment>End of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="cause_i3_4f" pos="11" rst="0">
          <comment>Cause interrupt Three Quarter of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_i4f" pos="10" rst="0">
          <comment>Cause interrupt Quarter of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_ihf" pos="9" rst="0">
          <comment>Cause interrupt Half of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_ief" pos="8" rst="0">
          <comment>Cause interrupt End of FIFO.</comment>
        </bits>
        <bits access="r" name="fifo_empty" pos="4" rst="1">
          <comment>When 1 the fifo is empty</comment>
        </bits>
        <bits access="r" name="enable" pos="0" rst="0">
          <comment>When 1 the channel is enabled</comment>
        </bits>
      </reg>
      <reg name="ch_0__start_addr" protect="rw">
        <bits access="rw" name="start_addr" pos="31:2" rst="1073741823">
          <comment>AHB Start Address. This field represent the start address of the FIFO located in RAM.</comment>
        </bits>
      </reg>
      <reg name="ch_0__fifo_size" protect="rw">
        <bits access="rw" name="fifo_size" pos="14:4" rst="2047">
          <comment>Fifo size in bytes, max 32kBytes.
The size of the fifo must be a multiple of 16 (The four LSB are always zero).</comment>
        </bits>
      </reg>
      <reg name="ch_0__reserved" protect="r">
      </reg>
      <reg name="ch_0__int_mask" protect="rw">
        <bits access="rw" name="three_quarter_fifo" pos="11" rst="0">
          <comment>THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="quarter_fifo" pos="10" rst="0">
          <comment>QUARTER FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="half_fifo" pos="9" rst="0">
          <comment>HALF FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="end_fifo" pos="8" rst="0">
          <comment>END FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
      </reg>
      <reg name="ch_0__int_clear" protect="rw">
        <bits access="rc" name="three_quarter_fifo" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear Three Quarter fifo interrupt.</comment>
        </bits>
        <bits access="rc" name="quarter_fifo" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear Quarter fifo interrupt.</comment>
        </bits>
        <bits access="rc" name="half_fifo" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear half of fifo interrupt.</comment>
        </bits>
        <bits access="rc" name="end_fifo" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear end of fifo interrupt.</comment>
        </bits>
      </reg>
      <reg name="ch_0__cur_ahb_addr" protect="r">
        <bits access="r" name="cur_ahb_addr" pos="31:2" rst="1073741823">
          <comment>Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register.</comment>
        </bits>
      </reg>
      <reg name="ch_1__control" protect="w">
        <bits access="w" name="auto_disable" pos="4" rst="0">
          <comment>Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt.</comment>
        </bits>
        <bits access="w" name="disable" pos="1" rst="0">
          <comment>Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled.</comment>
        </bits>
        <bits access="w" name="enable" pos="0" rst="0">
          <comment>Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.</comment>
        </bits>
      </reg>
      <reg name="ch_1__status" protect="r">
        <bits access="r" name="i3_4f" pos="19" rst="0">
          <comment>Three Quarter of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="i4f" pos="18" rst="0">
          <comment>Quarter of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="ihf" pos="17" rst="0">
          <comment>Half of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="ief" pos="16" rst="0">
          <comment>End of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="cause_i3_4f" pos="11" rst="0">
          <comment>Cause interrupt Three Quarter of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_i4f" pos="10" rst="0">
          <comment>Cause interrupt Quarter of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_ihf" pos="9" rst="0">
          <comment>Cause interrupt Half of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_ief" pos="8" rst="0">
          <comment>Cause interrupt End of FIFO.</comment>
        </bits>
        <bits access="r" name="fifo_empty" pos="4" rst="1">
          <comment>When 1 the fifo is empty</comment>
        </bits>
        <bits access="r" name="enable" pos="0" rst="0">
          <comment>When 1 the channel is enabled</comment>
        </bits>
      </reg>
      <reg name="ch_1__start_addr" protect="rw">
        <bits access="rw" name="start_addr" pos="31:2" rst="1073741823">
          <comment>AHB Start Address. This field represent the start address of the FIFO located in RAM.</comment>
        </bits>
      </reg>
      <reg name="ch_1__fifo_size" protect="rw">
        <bits access="rw" name="fifo_size" pos="14:4" rst="2047">
          <comment>Fifo size in bytes, max 32kBytes.
The size of the fifo must be a multiple of 16 (The four LSB are always zero).</comment>
        </bits>
      </reg>
      <reg name="ch_1__reserved" protect="r">
      </reg>
      <reg name="ch_1__int_mask" protect="rw">
        <bits access="rw" name="three_quarter_fifo" pos="11" rst="0">
          <comment>THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="quarter_fifo" pos="10" rst="0">
          <comment>QUARTER FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="half_fifo" pos="9" rst="0">
          <comment>HALF FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="end_fifo" pos="8" rst="0">
          <comment>END FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
      </reg>
      <reg name="ch_1__int_clear" protect="rw">
        <bits access="rc" name="three_quarter_fifo" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear Three Quarter fifo interrupt.</comment>
        </bits>
        <bits access="rc" name="quarter_fifo" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear Quarter fifo interrupt.</comment>
        </bits>
        <bits access="rc" name="half_fifo" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear half of fifo interrupt.</comment>
        </bits>
        <bits access="rc" name="end_fifo" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear end of fifo interrupt.</comment>
        </bits>
      </reg>
      <reg name="ch_1__cur_ahb_addr" protect="r">
        <bits access="r" name="cur_ahb_addr" pos="31:2" rst="1073741823">
          <comment>Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register.</comment>
        </bits>
      </reg>
      <reg name="ch_2__control" protect="w">
        <bits access="w" name="auto_disable" pos="4" rst="0">
          <comment>Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt.</comment>
        </bits>
        <bits access="w" name="disable" pos="1" rst="0">
          <comment>Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled.</comment>
        </bits>
        <bits access="w" name="enable" pos="0" rst="0">
          <comment>Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.</comment>
        </bits>
      </reg>
      <reg name="ch_2__status" protect="r">
        <bits access="r" name="i3_4f" pos="19" rst="0">
          <comment>Three Quarter of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="i4f" pos="18" rst="0">
          <comment>Quarter of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="ihf" pos="17" rst="0">
          <comment>Half of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="ief" pos="16" rst="0">
          <comment>End of FIFO interrupt status bit.</comment>
        </bits>
        <bits access="r" name="cause_i3_4f" pos="11" rst="0">
          <comment>Cause interrupt Three Quarter of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_i4f" pos="10" rst="0">
          <comment>Cause interrupt Quarter of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_ihf" pos="9" rst="0">
          <comment>Cause interrupt Half of FIFO.</comment>
        </bits>
        <bits access="r" name="cause_ief" pos="8" rst="0">
          <comment>Cause interrupt End of FIFO.</comment>
        </bits>
        <bits access="r" name="fifo_empty" pos="4" rst="1">
          <comment>When 1 the fifo is empty</comment>
        </bits>
        <bits access="r" name="enable" pos="0" rst="0">
          <comment>When 1 the channel is enabled</comment>
        </bits>
      </reg>
      <reg name="ch_2__start_addr" protect="rw">
        <bits access="rw" name="start_addr" pos="31:2" rst="1073741823">
          <comment>AHB Start Address. This field represent the start address of the FIFO located in RAM.</comment>
        </bits>
      </reg>
      <reg name="ch_2__fifo_size" protect="rw">
        <bits access="rw" name="fifo_size" pos="14:4" rst="2047">
          <comment>Fifo size in bytes, max 32kBytes.
The size of the fifo must be a multiple of 16 (The four LSB are always zero).</comment>
        </bits>
      </reg>
      <reg name="ch_2__reserved" protect="r">
      </reg>
      <reg name="ch_2__int_mask" protect="rw">
        <bits access="rw" name="three_quarter_fifo" pos="11" rst="0">
          <comment>THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="quarter_fifo" pos="10" rst="0">
          <comment>QUARTER FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="half_fifo" pos="9" rst="0">
          <comment>HALF FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
        <bits access="rw" name="end_fifo" pos="8" rst="0">
          <comment>END FIFO Mask interrupt. When one this interrupt is enabled.</comment>
        </bits>
      </reg>
      <reg name="ch_2__int_clear" protect="rw">
        <bits access="rc" name="three_quarter_fifo" pos="11" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear Three Quarter fifo interrupt.</comment>
        </bits>
        <bits access="rc" name="quarter_fifo" pos="10" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear Quarter fifo interrupt.</comment>
        </bits>
        <bits access="rc" name="half_fifo" pos="9" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear half of fifo interrupt.</comment>
        </bits>
        <bits access="rc" name="end_fifo" pos="8" rst="0">
          <comment>bit type is changed from w1c to rc.
          Write one to clear end of fifo interrupt.</comment>
        </bits>
      </reg>
      <reg name="ch_2__cur_ahb_addr" protect="r">
        <bits access="r" name="cur_ahb_addr" pos="31:2" rst="1073741823">
          <comment>Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_ble_link.xml">
    <module category="wcn" name="WCN_BLE_LINK">
      <reg name="rwblecntl" protect="rw">
        <bits access="w" name="master_soft_rst" pos="31" rst="0">
          <comment>Reset the complete BLE Core except registers and timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
In case of Dual Mode implementation, reset also common blocks.</comment>
        </bits>
        <bits access="w" name="master_tgsoft_rst" pos="30" rst="0">
          <comment>Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="reg_soft_rst" pos="29" rst="0">
          <comment>Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="swint_req" pos="28" rst="0">
          <comment>Forces the generation of ble_sw_irq when written with a 1, and proper masking is set. Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="rftest_abort" pos="26" rst="0">
          <comment>Abort the current RF Testing defined as per CS-FORMAT when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
Note that when RFTEST_ABORT is requested
  1/ In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC.
  2/ In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF.</comment>
        </bits>
        <bits access="w" name="advert_abort" pos="25" rst="0">
          <comment>Abort the current Advertising event when written with a 1. Resets at 0 when action is performed.
No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="scan_abort" pos="24" rst="0">
          <comment>Abort the current scan window when written with a  1. Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="rw" name="md_dsb" pos="22" rst="0">
          <comment>0: Normal operation of MD bits management
1: Allow a single Tx/Rx exchange whatever the MD bits are.
-      value forced by SW from Tx Descriptor
-      value just saved in Rx Descriptor during reception</comment>
        </bits>
        <bits access="rw" name="sn_dsb" pos="21" rst="0">
          <comment>0: Normal operation of Sequence number
1: Sequence Number Management disabled:
-      value forced by SW from Tx Descriptor
-      value ignored in Rx -&gt; No SN error reported.</comment>
        </bits>
        <bits access="rw" name="nesn_dsb" pos="20" rst="0">
          <comment>0: Normal operation of Acknowledge
1: Acknowledge scheme disabled:
-      value forced by SW from Tx Descriptor
-      value ignored in Rx -&gt; No NESN error reported.</comment>
        </bits>
        <bits access="rw" name="crypt_dsb" pos="19" rst="0">
          <comment>0: Normal operation. Encryption / Decryption enabled.
1: Encryption / Decryption disabled.
Note  that  if  CS-CRYPT_EN  is  set,  then  MIC  is  generated,  and  only  data  encryption  is  disabled, meaning data sent are plain data.</comment>
        </bits>
        <bits access="rw" name="whit_dsb" pos="18" rst="0">
          <comment>0: Normal operation. Whitening enabled.
1: Whitening disabled.</comment>
        </bits>
        <bits access="rw" name="crc_dsb" pos="17" rst="0">
          <comment>0: Normal operation. CRC removed from data stream.
1: CRC stripping disabled on Rx packets, CRC replaced by 0x000 in Tx.</comment>
        </bits>
        <bits access="rw" name="hop_remap_dsb" pos="16" rst="0">
          <comment>0: Normal operation. Frequency Hopping Remapping algorithm enabled.
1: Frequency Hopping Remapping algorithm disabled</comment>
        </bits>
        <bits access="rw" name="advertfilt_en" pos="9" rst="0">
          <comment>Advertising Channels Error Filtering Enable control
0: RW-BLE Core reports all errors to RW-BLE Software
1: RW-BLE Core reports only correctly received packet, without error to RW-BLE Software</comment>
        </bits>
        <bits access="rw" name="rwble_en" pos="8" rst="0">
          <comment>0: Disable RW-BLE Core Exchange Table pre-fetch mechanism.
1: Enable RW-BLE Core Exchange table pre-fetch mechanism.</comment>
        </bits>
        <bits access="rw" name="rxwinszdef" pos="7:4" rst="15">
          <comment>Default Rx Window size in 2s. Used when device
-      is master connected
-      performs its second receipt.
0 is not a valid value. Recommended value is 10 (in decimal).</comment>
        </bits>
        <bits access="rw" name="syncerr" pos="2:0" rst="0">
          <comment>Indicates the maximum number of errors allowed to recognize the synchronization word.</comment>
        </bits>
      </reg>
      <reg name="version" protect="r">
        <bits access="r" name="typ" pos="31:24" rst="8">
          <comment>RW-BLE Core Type C 0x8 means BLE v4.2 (i.e. correspond LL version assigned number). Correspond to FS v8.0.10)</comment>
        </bits>
        <bits access="r" name="rel" pos="23:16" rst="0">
          <comment>RW-BLE Core version C Major release number. Correspond to FS v8.0.10</comment>
        </bits>
        <bits access="r" name="upg" pos="15:8" rst="10">
          <comment>RW-BLE Core upgrade C Upgrade number. Correspond to FS v8.0.10</comment>
        </bits>
        <bits access="r" name="build_num" pos="7:0" rst="0">
          <comment>RW-BLE Core Build C Build number</comment>
        </bits>
      </reg>
      <reg name="rwbleconf" protect="r">
        <bits access="r" name="dmmode" pos="31" rst="1">
          <comment>0: RW-BLE Core is used as a standalone BLE device
1: RW-BLE Core is used in a Dual Mode device</comment>
        </bits>
        <bits access="r" name="isoportnb" pos="25:24" rst="0">
          <comment>Number of supported Isochronous Channel (0 to 3)
00: No ISO/Audio Channel available
01: One ISO/Audio Channel available
10: Two ISO/Audio Channels available
11: Three ISO/Audio Channels available</comment>
        </bits>
        <bits access="r" name="decipher" pos="23" rst="1">
          <comment>0: AES deciphering not present
1: AES deciphering present</comment>
        </bits>
        <bits access="r" name="wlancoex" pos="21" rst="0">
          <comment>0: WLAN Coexistence mechanism not present
1: WLAN Coexistence mechanism present (Default Value)</comment>
        </bits>
        <bits access="r" name="rfif" pos="20:16" rst="1">
          <comment>RFIF[k]= 0: Control logic supporting radio k not present
RFIF[k]= 1: Control logic supporting radio k present
Index k values are:
 00001: Ripple RF.
 00010: External Radio Controller Support
 00100: IcyTRx Radio
xxx000: Reserved
Default value is 0000001</comment>
        </bits>
        <bits access="r" name="usedbg" pos="15" rst="1">
          <comment>0: Diagnostic port not instantiated
1: Diagnostic port instantiated (Default Value)</comment>
        </bits>
        <bits access="r" name="usecrypt" pos="14" rst="1">
          <comment>0: AES-CCM Encryption block not present
1: AES-CCM Encryption block present (Default Value)</comment>
        </bits>
        <bits access="r" name="clk_sel" pos="13:8" rst="13">
          <comment>Operating Frequency (in MHz)
Default value is 13MHz</comment>
        </bits>
        <bits access="r" name="intmode" pos="7" rst="1">
          <comment>0: Interrupts are edge level generated, i.e. pulse.
1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement (Default Value)</comment>
        </bits>
        <bits access="r" name="bus_type" pos="6" rst="0">
          <comment>Processor Bus Type
0: AHB Bus
1: X-Bar Bus</comment>
        </bits>
        <bits access="r" name="data_width" pos="5" rst="1">
          <comment>Processor bus width:
0: 16 bits (Default Value)
1: 32 bits</comment>
        </bits>
        <bits access="r" name="addr_width" pos="4:0" rst="16">
          <comment>Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary.
Default value is 13 (in decimal)</comment>
        </bits>
      </reg>
      <reg name="intcntl" protect="rw">
        <bits access="rw" name="cscntdevmsk" pos="15" rst="1">
          <comment>CSCNT  interrupt  mask  during  event.  This  bit  allows  to  enable  CSCNT  interrupt  generation  during events (i.e. advertising, scanning, initiating, and connection)
0: CSCNT Interrupt not generated during events.
1: CSCNT Interrupt generated during events.</comment>
        </bits>
        <bits access="rw" name="audioint2msk" pos="12" rst="0">
          <comment>Audio channel 2 interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="audioint1msk" pos="11" rst="0">
          <comment>Audio channel 1 interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="audioint0msk" pos="10" rst="0">
          <comment>Audio channel 0 interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="swintmsk" pos="9" rst="0">
          <comment>SW triggered interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="eventapfaintmsk" pos="8" rst="1">
          <comment>End of event / anticipated pre-fetch abort interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="finetgtimintmsk" pos="7" rst="0">
          <comment>Fine Target Timer Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="grosstgtimintmsk" pos="6" rst="0">
          <comment>Gross Target Timer Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="errorintmsk" pos="5" rst="0">
          <comment>Error Interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="cryptintmsk" pos="4" rst="1">
          <comment>Encryption engine Interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="eventintmsk" pos="3" rst="1">
          <comment>End of event Interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="slpintmsk" pos="2" rst="1">
          <comment>Sleep Mode Interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="rxintmsk" pos="1" rst="1">
          <comment>Rx Interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="cscntintmsk" pos="0" rst="1">
          <comment>625s Base Time Interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
      </reg>
      <reg name="intstat" protect="r">
        <bits access="r" name="audioint2stat" pos="12" rst="0">
          <comment>Audio channel 2 interrupt status
0: No Audio interrupt.
1: An Audio interrupt is pending.</comment>
        </bits>
        <bits access="r" name="audioint1stat" pos="11" rst="0">
          <comment>Audio channel 1 interrupt status
0: No Audio interrupt.
1: An Audio interrupt is pending.</comment>
        </bits>
        <bits access="r" name="audioint0stat" pos="10" rst="0">
          <comment>Audio channel 0 interrupt status
0: No Audio interrupt.
1: An Audio interrupt is pending.</comment>
        </bits>
        <bits access="r" name="swintstat" pos="9" rst="0">
          <comment>SW triggered interrupt status
0: No SW triggered interrupt.
1: A SW triggered interrupt is pending.</comment>
        </bits>
        <bits access="r" name="eventapfaintstat" pos="8" rst="0">
          <comment>End of event / Anticipated Pre-Fetch Abort interrupt status
0: No End of Event interrupt.
1: An End of Event interrupt is pending.</comment>
        </bits>
        <bits access="r" name="finetgtimintstat" pos="7" rst="0">
          <comment>Masked Fine Target Timer Error interrupt status
0: No Fine Target Timer interrupt.
1: A Fine Target Timer interrupt is pending.</comment>
        </bits>
        <bits access="r" name="grosstgtimintstat" pos="6" rst="0">
          <comment>Masked Gross Target Timer interrupt status
0: No Gross Target Timer interrupt.
1: A Gross Target Timer interrupt is pending.</comment>
        </bits>
        <bits access="r" name="errorintstat" pos="5" rst="0">
          <comment>Masked Error interrupt status
0: No Error interrupt.
1: An Error interrupt is pending.</comment>
        </bits>
        <bits access="r" name="cryptintstat" pos="4" rst="0">
          <comment>Masked Encryption engine interrupt status
0: No Encryption / Decryption interrupt.
1: An Encryption / Decryption interrupt is pending.</comment>
        </bits>
        <bits access="r" name="eventintstat" pos="3" rst="0">
          <comment>Masked End of Event interrupt status
0: No End of Advertising / Scanning / Connection interrupt.
1: An End of Advertising / Scanning / Connection interrupt is pending.</comment>
        </bits>
        <bits access="r" name="slpintstat" pos="2" rst="0">
          <comment>Masked Sleep interrupt status
0: No End of Sleep Mode interrupt.
1: An End of Sleep Mode interrupt is pending.</comment>
        </bits>
        <bits access="r" name="rxintstat" pos="1" rst="0">
          <comment>Masked Packet Reception interrupt status
0: No Rx interrupt.
1: An Rx interrupt is pending.</comment>
        </bits>
        <bits access="r" name="cscntintstat" pos="0" rst="0">
          <comment>Masked 625s base time reference interrupt status</comment>
        </bits>
      </reg>
      <reg name="intrawstat" protect="r">
        <bits access="r" name="audioint2rawstat" pos="12" rst="0">
          <comment>Audio channel 2 interrupt raw status
0: No Audio interrupt.
1: An Audio interrupt is pending.</comment>
        </bits>
        <bits access="r" name="audioint1rawstat" pos="11" rst="0">
          <comment>Audio channel 1 interrupt raw status
0: No Audio interrupt.
1: An Audio interrupt is pending.</comment>
        </bits>
        <bits access="r" name="audioint0rawstat" pos="10" rst="0">
          <comment>Audio channel 0 interrupt raw status
0: No Audio interrupt.
1: An Audio interrupt is pending.</comment>
        </bits>
        <bits access="r" name="swintrawstat" pos="9" rst="0">
          <comment>SW triggered interrupt raw status
0: No SW triggered interrupt.
1: A SW triggered interrupt is pending.</comment>
        </bits>
        <bits access="r" name="eventapfaintrawstat" pos="8" rst="0">
          <comment>End of event / Anticipated Pre-Fetch Abort interrupt raw status
0: No End of Event interrupt.
1: An End of Event interrupt is pending.</comment>
        </bits>
        <bits access="r" name="finetgtimintrawstat" pos="7" rst="0">
          <comment>Fine Target Timer Error interrupt raw status
0: No Fine Target Timer interrupt.
1: A Fine Target Timer interrupt is pending.</comment>
        </bits>
        <bits access="r" name="grosstgtimintrawstat" pos="6" rst="0">
          <comment>Gross Target Timer interrupt raw status
0: No Gross Target Timer interrupt.
1: A Gross Target Timer interrupt is pending.</comment>
        </bits>
        <bits access="r" name="errorintrawstat" pos="5" rst="0">
          <comment>Error interrupt raw status
0: No Error interrupt.
1: An Error interrupt is pending.</comment>
        </bits>
        <bits access="r" name="cryptintrawstat" pos="4" rst="0">
          <comment>Encryption engine interrupt raw status
0: No Encryption / Decryption interrupt.
1: An Encryption / Decryption interrupt is pending.</comment>
        </bits>
        <bits access="r" name="eventintrawstat" pos="3" rst="0">
          <comment>End of Event interrupt raw status
0: No End of Advertising / Scanning / Connection interrupt.
1: An End of Advertising / Scanning / Connection interrupt is pending.</comment>
        </bits>
        <bits access="r" name="slpintrawstat" pos="2" rst="0">
          <comment>Sleep interrupt raw status
0: No End of Sleep Mode interrupt.
1: An End of Sleep Mode interrupt is pending.</comment>
        </bits>
        <bits access="r" name="rxintrawstat" pos="1" rst="0">
          <comment>Packet Reception interrupt raw status
0: No Rx interrupt.
1: An Rx interrupt is pending.</comment>
        </bits>
        <bits access="r" name="cscntintrawstat" pos="0" rst="0">
          <comment>625s base time reference interrupt raw status
0: No 625s Base Time interrupt.
1: A 625s Base Time interrupt is pending.</comment>
        </bits>
      </reg>
      <reg name="intack" protect="rw">
        <bits access="s" name="audioint2ack" pos="12" rst="0">
          <comment>bit type is changed from wos to s.
          Audio channel 2 interrupt acknowledgement bit
Software  writing  1  acknowledges  the  Audio  channel  2  interrupt.  This  bit  resets  AUDIOINT2STAT  and AUDIOINT2RAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="audioint1ack" pos="11" rst="0">
          <comment>bit type is changed from wos to s.
          Audio channel 1 interrupt acknowledgement bit
Software  writing  1  acknowledges  the  Audio  channel  1  interrupt.  This  bit  resets  AUDIOINT1STAT  and AUDIOINT1RAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="audioint0ack" pos="10" rst="0">
          <comment>bit type is changed from wos to s.
          Audio channel 0 interrupt acknowledgement bit
Software  writing  1  acknowledges  the  Audio  channel  0  interrupt.  This  bit  resets  AUDIOINT0STAT  and AUDIOINT0RAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="swintack" pos="9" rst="0">
          <comment>bit type is changed from wos to s.
          SW triggered interrupt acknowledgement bit
Software   writing   1   acknowledges   the   SW   triggered   interrupt.   This   bit   resets   SWINTSTAT   and SWINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="eventapfaintack" pos="8" rst="0">
          <comment>bit type is changed from wos to s.
          End of event / Anticipated Pre-Fetch Abort interrupt acknowledgement bit
Software  writing  1  acknowledges  the  End  of  event  /  Anticipated  Pre-Fetch  Abort  interrupt.  This  bit resets EVENTAPFAINTSTAT and EVENTAPFAINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="finetgtimintack" pos="7" rst="0">
          <comment>bit type is changed from wos to s.
          Fine Target Timer interrupt acknowledgement bit
Software  writing  1  acknowledges  the  Fine  Timer  interrupt.  This  bit  resets  FINETGTIMINTSTAT  and FINETGTIMINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="grosstgtimintack" pos="6" rst="0">
          <comment>bit type is changed from wos to s.
          Gross Target Timer interrupt acknowledgement bit
Software writing  1 acknowledges the Gross Timer interrupt. This bit resets  GROSSTGTIMINTSTAT and GROSSTGTIMINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="errorintack" pos="5" rst="0">
          <comment>bit type is changed from wos to s.
          Error interrupt acknowledgement bit
Software   writing   1   acknowledges   the   Error   interrupt.   This   bit   resets   ERRORINTSTAT   and ERRORINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="cryptintack" pos="4" rst="0">
          <comment>bit type is changed from wos to s.
          Encryption  engine  interrupt  acknowledgement  bit  Software  writing  1  acknowledges  the  Encryption engine interrupt. This bit resets CRYPTINTSTAT and CRYPTINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="eventintack" pos="3" rst="0">
          <comment>bit type is changed from wos to s.
          End of Event interrupt acknowledgment bit
Software  writing  1  acknowledges  the  End  of  Advertising  /  Scanning  /  Connection  interrupt.  This  bit resets SLPINTSTAT and SLPINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="slpintack" pos="2" rst="0">
          <comment>bit type is changed from wos to s.
          End of Deep Sleep interrupt acknowledgment bit
Software  writing  1  acknowledges  the  End  of  Sleep  Mode  interrupt.  This  bit  resets  SLPINTSTAT  and SLPINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="rxintack" pos="1" rst="0">
          <comment>bit type is changed from wos to s.
          Packet Reception interrupt acknowledgment bit
Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="cscntintack" pos="0" rst="0">
          <comment>bit type is changed from wos to s.
          625s base time reference interrupt acknowledgment bit
Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
      </reg>
      <reg name="basetimecnt" protect="rw">
        <bits access="w" name="samp" pos="31" rst="0">
          <comment>Writing  a  1  samples  the  Base  Time  Counter  value  in  BASETIMECNT  register  field.  Resets  at  0  when action is performed</comment>
        </bits>
        <bits access="r" name="basetimecnt" pos="26:0" rst="0">
          <comment>Value of the 625s base time reference counter. Updated each time SAMP field is written. Used by the SW in order to synchronize with the HW</comment>
        </bits>
      </reg>
      <reg name="finetimecnt" protect="r">
        <bits access="r" name="finecnt" pos="9:0" rst="0">
          <comment>Value of the current s fine time reference counter. Updated each time SAMP field is written. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration</comment>
        </bits>
      </reg>
      <reg name="bdaddrl" protect="rw">
        <bits access="rw" name="bdaddrl" pos="31:0" rst="0">
          <comment>Bluetooth Low Energy Device Address. LSB part.</comment>
        </bits>
      </reg>
      <reg name="bdaddru" protect="rw">
        <bits access="rw" name="priv_npub" pos="16" rst="0">
          <comment>Bluetooth Low Energy Device Address privacy indicator
0: Public Bluetooth Device Address
1: Private Bluetooth Device Address</comment>
        </bits>
        <bits access="rw" name="bdaddru" pos="15:0" rst="0">
          <comment>Bluetooth Low Energy Device Address. MSB part.</comment>
        </bits>
      </reg>
      <reg name="et_currentrxdescptr" protect="rw">
        <bits access="rw" name="etptr" pos="31:16" rst="0">
          <comment>Exchange Table Pointer that determines the starting point of the Exchange Table</comment>
        </bits>
        <bits access="rw" name="currentrxdescptr" pos="14:0" rst="0">
          <comment>Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List</comment>
        </bits>
      </reg>
      <hole size="256"/>
      <reg name="diagcntl" protect="rw">
        <bits access="rw" name="diag3_en" pos="31" rst="0">
          <comment>0: Disable diagnostic port 3 output. All outputs are set to 0x0.
1: Enable diagnostic port 3 output.</comment>
        </bits>
        <bits access="rw" name="diag3" pos="29:24" rst="0">
          <comment>Only relevant when DIAGEN3 = 1.
Selection  of  the  outputs  that  must  be  driven  to  the  diagnostic  port  3.  See  section  2.16  for  a  detailed description.</comment>
        </bits>
        <bits access="rw" name="diag2_en" pos="23" rst="0">
          <comment>0: Disable diagnostic port 2 output. All outputs are set to 0x0.
1: Enable diagnostic port 2 output.</comment>
        </bits>
        <bits access="rw" name="diag2" pos="21:16" rst="0">
          <comment>Only relevant when DIAGEN2 = 1.
Selection  of  the  outputs  that  must  be  driven  to  the  diagnostic  port  2.  See  section  2.16  for  a  detailed description.</comment>
        </bits>
        <bits access="rw" name="diag1_en" pos="15" rst="0">
          <comment>0: Disable diagnostic port 1 output. All outputs are set to 0x0.
1: Enable diagnostic port 1 output.</comment>
        </bits>
        <bits access="rw" name="diag1" pos="13:8" rst="0">
          <comment>Only relevant when DIAGEN1 = 1.
Selection  of  the  outputs  that  must  be  driven  to  the  diagnostic  port  1.  See  section  2.16  for  a  detailed description.</comment>
        </bits>
        <bits access="rw" name="diag0_en" pos="7" rst="0">
          <comment>0: Disable diagnostic port 0 output. All outputs are set to 0x0.
1: Enable diagnostic port 0 output.</comment>
        </bits>
        <bits access="rw" name="diag0" pos="5:0" rst="0">
          <comment>Only relevant when DIAGEN0 = 1.
Selection  of  the  outputs  that  must  be  driven  to  the  diagnostic  port  0.  See  section  2.16  for  a  detailed description.</comment>
        </bits>
      </reg>
      <reg name="diagstat" protect="r">
        <bits access="r" name="diag3stat" pos="31:24" rst="0">
          <comment>Directly connected to ble_dbg3[7:0] output. Debug use only.</comment>
        </bits>
        <bits access="r" name="diag2stat" pos="23:16" rst="0">
          <comment>Directly connected to ble_dbg2[7:0] output. Debug use only.</comment>
        </bits>
        <bits access="r" name="diag1stat" pos="15:8" rst="0">
          <comment>Directly connected to ble_dbg1[7:0] output. Debug use only.</comment>
        </bits>
        <bits access="r" name="diag0stat" pos="7:0" rst="0">
          <comment>Directly connected to ble_dbg0[7:0] output. Debug use only.</comment>
        </bits>
      </reg>
      <reg name="debugaddmax" protect="rw">
        <bits access="rw" name="reg_addmax" pos="31:16" rst="0">
          <comment>Upper limit for the Register zone indicated by the reg_inzone flag (see section 2.16)</comment>
        </bits>
        <bits access="rw" name="em_addmax" pos="15:0" rst="0">
          <comment>Upper limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.16)</comment>
        </bits>
      </reg>
      <reg name="debugaddmin" protect="rw">
        <bits access="rw" name="reg_addmin" pos="31:16" rst="0">
          <comment>Lower limit for the Register zone indicated by the reg_inzone flag (see section 2.16)</comment>
        </bits>
        <bits access="rw" name="em_addmin" pos="15:0" rst="0">
          <comment>Lower limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.16)</comment>
        </bits>
      </reg>
      <reg name="errortypestat" protect="r">
        <bits access="r" name="ral_underrun" pos="19" rst="0">
          <comment>Indicates  Resolving  Address  List  engine  Under  run  issue,  happens  when  RAL  List  parsing  not finished on time
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="ral_error" pos="18" rst="0">
          <comment>Indicates Resolving Address List engine faced a bad setting (e.g CS-RAL_EN = 1 and null RALPTR, or RALPTR &gt; CS-PEER_RALPTR).
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="concevtirq_error" pos="17" rst="0">
          <comment>Indicates whether two consecutive and concurrent ble_event_irq have been generated, and not acknowledged in time by the RW-BLE Software.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="rxdata_ptr_error" pos="16" rst="0">
          <comment>Indicates whether Rx data buffer pointer value programmed is null: this is a major programming failure.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="txdata_ptr_error" pos="15" rst="0">
          <comment>Indicates whether Tx data buffer pointer value programmed is null during Advertising / Scanning /  Initiating  events,  or  during  Master  /  Slave  connections  with  non-null  packet  length:  this  is  a major programming failure.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="rxdesc_empty_error" pos="14" rst="0">
          <comment>Indicates  whether  Rx  Descriptor  pointer  value  programmed  in  register  is  null:  this  is  a  major programming failure.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="txdesc_empty_error" pos="13" rst="0">
          <comment>Indicates  whether  Tx  Descriptor  pointer  value  programmed  in  Control  Structure  is  null  during Advertising / Scanning / Initiating events: this is a major programming failure.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="csformat_error" pos="12" rst="0">
          <comment>Indicates  whether  CS-FORMAT  has  been  programmed  with  an  invalid  value:  this  is  a  major software programming failure.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="llchmap_error" pos="11" rst="0">
          <comment>Indicates Link Layer Channel Map error, happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="adv_underrun" pos="10" rst="0">
          <comment>Indicates  Advertising  Interval  Under  run,  occurs  if  time  between  two  consecutive  Advertising packet (in Advertising mode) is lower than described in Table 3-11.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="ifs_underrun" pos="9" rst="0">
          <comment>Indicates  Inter  Frame  Space  Under  run,  occurs  if  IFS  time  is  not  enough  to  update  and  read Control Structure/Descriptors, and/or White List parsing is not finished and/or Decryption time is too long to be finished on time
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="whitelist_error" pos="8" rst="0">
          <comment>Indicates White List Timeout error, occurs if White List parsing is not finished on time
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="evt_cntl_apfm_error" pos="7" rst="0">
          <comment>Indicates  Anticipated  Pre-Fetch  Mechanism  error:  happens  when  2  consecutive  events  are programmed, and when the first event is not completely finished while second pre-fetch instant is reached.
0: No error
1: Error occured</comment>
        </bits>
        <bits access="r" name="evt_schdl_apfm_error" pos="6" rst="0">
          <comment>Indicates  Anticipated  Pre-Fetch  Mechanism  error:  happens  when  2  consecutive  events  are programmed, and when the first event is not completely finished while second pre-fetch instant is reached.
0: No error
1: Error occured</comment>
        </bits>
        <bits access="r" name="evt_schdl_entry_error" pos="5" rst="0">
          <comment>Indicates Event Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset)
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="evt_schdl_emacc_error" pos="4" rst="0">
          <comment>Indicates Event Scheduler Exchange Memory access error, happens when Exchange Memory accesses are not served in time, and blocks the Exchange Table entry read
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="radio_emacc_error" pos="3" rst="0">
          <comment>Indicates  Radio  Controller  Exchange  Memory  access  error,  happens  when  Exchange  Memory accesses are not served in time and data are corrupted.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="pktcntl_emacc_error" pos="2" rst="0">
          <comment>Indicates  Packet  Controller  Exchange  Memory  access  error,  happens  when  Exchange  Memory accesses are not served in time and Tx/Rx data are corrupted
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="rxcrypt_error" pos="1" rst="0">
          <comment>Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to  Packet  Controller  requests.  A  16-bytes  block  has  to  be  decrypted  prior  the  next  block  is received by the Packet Controller
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="txcrypt_error" pos="0" rst="0">
          <comment>Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to  Packet  Controller  requests.  A  16-bytes  block  has  to  be  encrypted  and  prepared  on  Packet Controller request, and needs to be ready before the Packet Controller has to send ti
0: No error
1: Error occurred</comment>
        </bits>
      </reg>
      <reg name="swprofiling" protect="rw">
        <bits access="rw" name="swprof" pos="31:0" rst="0">
          <comment>Software Profiling register: used by RW-BLE Software for profiling purpose: this value is copied on Diagnostic port (Please refer to section 2.16 for details)</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="radiocntl0" protect="rw">
        <bits access="rw" name="sync_pulse_mode" pos="23" rst="0">
          <comment>Determines whether SYNC_P output will be dragged as pulse or level maintained till end of the Packet.
0: Access Code detection indicator provided as pulse
1: Access Code detection indicator provided as level</comment>
        </bits>
        <bits access="rw" name="dpcorr_en" pos="22" rst="0">
          <comment>Enables the use of the delayed DC offset compensated data path in Radio Correlator block.
1: Enable
0: Disable</comment>
        </bits>
        <bits access="rw" name="forceagc_en" pos="21" rst="0">
          <comment>Control Ripple AGC force mode based on RADIOCNTL2-FORCEAGC_LENGTH value
1: Enable
0: Disable</comment>
        </bits>
        <bits access="rw" name="forcebleiq" pos="20" rst="0">
          <comment>Control Ripple modulation mode in between FM and I&amp;Q
1: I&amp;Q modulation mode
0: FM modulation mode</comment>
        </bits>
        <bits access="rw" name="jef_select" pos="19" rst="0">
          <comment>Selects Jitter Elimination FIFO</comment>
        </bits>
        <bits access="rw" name="spifreq" pos="6:5" rst="0">
          <comment>Frequency of the SPI clock
00: SPI clock frequency is baseband master clock frequency divided by 2 (i.e 6.5MHz @ 13MHz)
01: SPI clock frequency is baseband master clock frequency divided by 4 (i.e 3.25MHz @ 13MHz)
10: SPI clock frequency is baseband master clock frequency divided by 8 (i.e 1.67MHz @ 13MHz)
11: Do not use</comment>
        </bits>
        <bits access="r" name="spicomp" pos="1" rst="1">
          <comment>This bit is READ ONLY.
0: Indicates that the SPI transfer is in progress.
1: Indicates that the SPI transfer is complete. The RW-BT Dual Mode is ready to start another transfer.</comment>
        </bits>
        <bits access="w" name="spigo" pos="0" rst="0">
          <comment>Software writing 1 triggers the SPI access. This bit is always read as 0.</comment>
        </bits>
      </reg>
      <reg name="radiocntl1" protect="rw">
        <bits access="rw" name="subversion" pos="27:24" rst="0">
          <comment>Has no effect on Radio Controller</comment>
        </bits>
        <bits access="rw" name="xrfsel" pos="20:16" rst="1">
          <comment>Extended radio selection field
5'b00000: No radio selected
5'b00001: RivieraWaves Ripple RF (BT4.0)
5'b00010: External Radio controller support
5'b00011-5'b11111: reserved</comment>
        </bits>
        <bits access="rw" name="spiptr" pos="15:0" rst="144">
          <comment>Pointer to the buffer containing data to be transferred to or received from the SPI port.</comment>
        </bits>
      </reg>
      <reg name="radiocntl2" protect="rw">
        <bits access="rw" name="rfrxtmda" pos="31:28" rst="0">
          <comment>RF Rx Test Mode Delay Adjustment</comment>
        </bits>
        <bits access="rw" name="tx_delay" pos="27:24" rst="0">
          <comment>Used to compensate Modem&amp;RF Tx delay. When used, rtrip_delay should be set as Rx delay</comment>
        </bits>
        <bits access="rw" name="sync_position" pos="22:16" rst="39">
          <comment>Expected bit offset when rx symbol flag found. Used to compensate Modem&amp;RF Rx delay.</comment>
        </bits>
        <bits access="rw" name="forceagc_length" pos="11:0" rst="0">
          <comment>Defines Rx window time threshold that forces Ripple AGC to max gain</comment>
        </bits>
      </reg>
      <reg name="radiocntl3" protect="rw">
        <bits access="rw" name="freqtable_ptr" pos="15:0" rst="64">
          <comment>BR/EDR Frequency Table pointer</comment>
        </bits>
      </reg>
      <reg name="radiopwrupdn" protect="rw">
        <bits access="rw" name="rtrip_delay" pos="30:24" rst="30">
          <comment>Defines round trip delay value. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in s</comment>
        </bits>
        <bits access="rw" name="rxpwrup" pos="23:16" rst="80">
          <comment>This register holds the  length in us of the RX power  up  phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio.</comment>
        </bits>
        <bits access="rw" name="txpwrdn" pos="12:8" rst="5">
          <comment>This  register  extends  the  length  in us  of  the  TX  power  down  phase  for  the  current  radio  device. Default value is 3us (reset value). Operating range depends on the selected radio.</comment>
        </bits>
        <bits access="rw" name="txpwrup" pos="7:0" rst="60">
          <comment>This  register  holds  the  length  in us  of  the  TX  power  up  phase  for  the  current  radio  device.  Default value is 210us (reset value). Operating range depends on the selected radio.</comment>
        </bits>
      </reg>
      <reg name="radiocntl2m" protect="rw">
        <bits access="rw" name="rtrip_delay_2m" pos="30:24" rst="15">
          <comment>Defines round trip delay value for 2M mode. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in s</comment>
        </bits>
        <bits access="rw" name="sync_position_2m" pos="22:16" rst="23">
          <comment>Expected bit offset when rx symbol flag found for 2M mode. Used to compensate Modem&amp;RF Rx delay.</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="advchmap" protect="rw">
        <bits access="rw" name="advchmap" pos="2:0" rst="7">
          <comment>Advertising  Channel  Map,  defined  as  per  the  advertising  connection  settings.  Contains  advertising channels index 37 to 39. If ADVCHMAP[i] equals:
0: Do not use data channel i+37.
1: Use data channel i+37.</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="advtim" protect="rw">
        <bits access="rw" name="advint" pos="13:0" rst="0">
          <comment>Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent.
Value is in s.
Value  to  program  depends  on  the  used  Advertising  Packet  type  and  the  device  filtering  policy.
Please refer to Table 3-11 for details about ADVINT programming range.</comment>
        </bits>
      </reg>
      <reg name="actscanstat" protect="r">
        <bits access="r" name="backoff" pos="24:16" rst="1">
          <comment>Active scan mode back-off counter initialization value.</comment>
        </bits>
        <bits access="r" name="upperlimit" pos="8:0" rst="1">
          <comment>Active scan mode upper limit counter value.</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="wlpubaddptr" protect="rw">
        <bits access="rw" name="wlpubaddptr" pos="15:0" rst="0">
          <comment>Start address pointer of the public devices white list.</comment>
        </bits>
      </reg>
      <reg name="wlprivaddptr" protect="rw">
        <bits access="rw" name="wlprivaddptr" pos="15:0" rst="0">
          <comment>Start address pointer of the private devices white list.</comment>
        </bits>
      </reg>
      <reg name="wlnbdev" protect="rw">
        <bits access="rw" name="nbprivdev" pos="15:8" rst="0">
          <comment>Number of private devices in the white list.</comment>
        </bits>
        <bits access="rw" name="nbpubdev" pos="7:0" rst="0">
          <comment>Number of public devices in the white list.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="aescntl" protect="rw">
        <bits access="rw" name="aes_mode" pos="1" rst="0">
          <comment>0: Cipher mode
1: Decipher mode</comment>
        </bits>
        <bits access="w" name="aes_start" pos="0" rst="0">
          <comment>Writing a 1 starts AES-128 ciphering/deciphering process.
This bit is reset once the process is finished (i.e. ble_crypt_irq interrupt occurs, even masked)</comment>
        </bits>
      </reg>
      <reg name="aeskey31_0" protect="rw">
        <bits access="rw" name="aeskey31_0" pos="31:0" rst="0">
          <comment>AES encryption 128-bit key. Bit 31 down to 0</comment>
        </bits>
      </reg>
      <reg name="aeskey63_32" protect="rw">
        <bits access="rw" name="aeskey63_32" pos="31:0" rst="0">
          <comment>AES encryption 128-bit key. Bit 63 down to 32</comment>
        </bits>
      </reg>
      <reg name="aeskey95_64" protect="rw">
        <bits access="rw" name="aeskey95_64" pos="31:0" rst="0">
          <comment>AES encryption 128-bit key. Bit 95 down to 64</comment>
        </bits>
      </reg>
      <reg name="aeskey127_96" protect="rw">
        <bits access="rw" name="aeskey127_96" pos="31:0" rst="0">
          <comment>AES encryption 128-bit key. Bit 127 down to 96</comment>
        </bits>
      </reg>
      <reg name="aesptr" protect="rw">
        <bits access="rw" name="aesptr" pos="15:0" rst="0">
          <comment>Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored.</comment>
        </bits>
      </reg>
      <reg name="txmicval" protect="r">
        <bits access="r" name="txmicval" pos="31:0" rst="0">
          <comment>AES-CCM plain MIC value. Valid on when MIC has been calculated (in Tx)</comment>
        </bits>
      </reg>
      <reg name="rxmicval" protect="r">
        <bits access="r" name="rxmicval" pos="31:0" rst="0">
          <comment>AES-CCM plain MIC value. Valid on once MIC has been extracted from Rx packet.</comment>
        </bits>
      </reg>
      <reg name="rftestcntl" protect="rw">
        <bits access="rw" name="infiniterx" pos="31" rst="0">
          <comment>Applicable to all event type
0: Normal mode of operation
1: Infinite Rx window</comment>
        </bits>
        <bits access="rw" name="rxpktcnten" pos="27" rst="0">
          <comment>Applicable in RF Direct Rx Test mode only
0: Rx packet count disabled
1:  Rx  packet  count  enabled,  and  reported  in  CS-RXCCMPKTCNT  and  RFTESTRXSTAT-RXPKTCNT  on RF abort command</comment>
        </bits>
        <bits access="rw" name="infinitetx" pos="15" rst="0">
          <comment>Applicable to all event type
0: Normal mode of operation.
1: Infinite Tx packet / Normal start of a packet but endless payload</comment>
        </bits>
        <bits access="rw" name="txlengthsrc" pos="14" rst="0">
          <comment>Applicable to all event type
0: Normal mode of operation: TxDESC-&lt;TXADVLEN/TXLEN&gt; controls the Tx packet payload size
1: Uses RFTESTCNTL-TXLENGTH packet length (can support up to 512 bytes transmit)</comment>
        </bits>
        <bits access="rw" name="prbstype" pos="13" rst="0">
          <comment>Defines the PRBS in use
0: Tx Packet Payload are PRBS9 type
1: Tx Packet Payload are PRBS15 type</comment>
        </bits>
        <bits access="rw" name="txpldsrc" pos="12" rst="0">
          <comment>Applicable to all event type
0: Tx Packet Payload source is the Control Structure
1: Tx Packet Payload are PRBS generator</comment>
        </bits>
        <bits access="rw" name="txpktcnten" pos="11" rst="0">
          <comment>Applicable in RF Direct Tx Test mode only
0: Tx packet count disabled
1: Tx packet count enabled, and reported in CS-TXCCMPKTCNT and RFTESTTXSTAT-TXPKTCNT on RF abort command</comment>
        </bits>
        <bits access="rw" name="txlength" pos="8:0" rst="0">
          <comment>Applicable to all event type, valid when RFTESTCNTL-TXLENGTHSRC = 1
Tx packet length in number of byte</comment>
        </bits>
      </reg>
      <reg name="rftesttxstat" protect="r">
        <bits access="r" name="txpktcnt" pos="31:0" rst="0">
          <comment>Reports number of transmitted packet during Test Modes.
Value is valid if RFTESTCNTL-TXPKTCNTEN is set</comment>
        </bits>
      </reg>
      <reg name="rftestrxstat" protect="r">
        <bits access="r" name="rxpktcnt" pos="31:0" rst="0">
          <comment>Reports number of correctly received packet during Test Modes (no sync error, no CRC error).
Value is valid if RFTESTCNTL-RXPKTCNTEN is set</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="timgencntl" protect="rw">
        <bits access="rw" name="apfm_en" pos="31" rst="1">
          <comment>Controls the Anticipated pre-Fetch Abort mechanism
0: Disabled
1: Enabled</comment>
        </bits>
        <bits access="rw" name="prefetchabort_time" pos="25:16" rst="510">
          <comment>Defines the instant in s at which immediate abort is required after anticipated pre-fetch abort</comment>
        </bits>
        <bits access="rw" name="prefetch_time" pos="8:0" rst="150">
          <comment>Defines Exchange Table pre-fetch instant in s</comment>
        </bits>
      </reg>
      <reg name="grosstimtgt" protect="rw">
        <bits access="rw" name="grosstarget" pos="22:0" rst="0">
          <comment>Gross  Timer  Target  value  on  which  a  ble_grosstgtim_irq  must  be  generated.  This  timer  has  a precision  of  10ms:  interrupt  is  generated  only  when  GROSSTARGET[22:0]  =  BASETIMECNT[26:4] and BASETIMECNT[3:0] = 0.</comment>
        </bits>
      </reg>
      <reg name="finetimtgt" protect="rw">
        <bits access="rw" name="finetarget" pos="26:0" rst="0">
          <comment>Fine Timer Target value on which a ble_finetgtim_irq must be generated. This timer has a precision of 625s: interrupt is generated only when FINETARGET = BASETIMECNT</comment>
        </bits>
      </reg>
      <hole size="288"/>
      <reg name="ralptr" protect="rw">
        <bits access="rw" name="ralptr" pos="15:0" rst="0">
          <comment>Start address pointer of the RAL structure</comment>
        </bits>
      </reg>
      <reg name="ralnbdev" protect="rw">
        <bits access="rw" name="nbraldev" pos="7:0" rst="0">
          <comment>Number of devices in RAL Structure</comment>
        </bits>
      </reg>
      <reg name="ral_local_rnd" protect="rw">
        <bits access="w" name="lrnd_init" pos="31" rst="0">
          <comment>Writing a 1 initializes of Local RPA random number generation LFSR
This bit is reset once the LFSR is loaded</comment>
        </bits>
        <bits access="rw" name="lrnd_val" pos="21:0" rst="4132623">
          <comment>Initialization value for  Local RPA random generation when LRDN_INIT is set to 1, else reports the current Local RPA random number LFSR value</comment>
        </bits>
      </reg>
      <reg name="ral_peer_rnd" protect="rw">
        <bits access="w" name="prnd_init" pos="31" rst="0">
          <comment>Writing a 1 initializes of Peer RPA random number generation LFSR
This bit is reset once the LFSR is loaded</comment>
        </bits>
        <bits access="rw" name="prnd_val" pos="21:0" rst="3207408">
          <comment>Initialization  value  for  Peer  RPA  random  generation  when  PRDN_INIT  is  set  to  1,  else  reports the current Peer RPA random number LFSR value</comment>
        </bits>
      </reg>
      <hole size="768"/>
      <reg name="bleprioscharb" protect="rw">
        <bits access="rw" name="blepriomode" pos="15" rst="0">
          <comment>Determine BLE Priority Scheduling Arbitration Mode
0: BLE Decision instant not used
1: BLE Decision instant used</comment>
        </bits>
        <bits access="rw" name="blemargin" pos="7:0" rst="0">
          <comment>Determine the decision instant margin for Priority Scheduling Arbitration.
Decision instant is defined as per formula of section 3.6</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_bt_core.xml">
    <module category="wcn" name="WCN_BT_CORE">
      <reg name="common_ctrl" protect="rw">
        <bits access="r" name="typ" pos="31:28" rst="2">
          <comment>Version type of bt_core. 1 for BTDM old version. 2 for BTDM new version. 3 for BLE only.</comment>
        </bits>
        <bits access="r" name="rel" pos="27:24" rst="2">
          <comment>Major release number of bt_core</comment>
        </bits>
        <bits access="r" name="upg" pos="23:20" rst="0">
          <comment>Upgrade number of bt_core</comment>
        </bits>
        <bits access="rw" name="rf_ext_slave" pos="1" rst="0">
          <comment>Set to 1 when working as a plug-in RF&amp;modem board. Set to 0 in all other modes</comment>
        </bits>
        <bits access="rw" name="rf_ext_master" pos="0" rst="0">
          <comment>Set to 1 when using plug-in RF&amp;modem board. Set to 0 in all other modes</comment>
        </bits>
      </reg>
      <reg name="tport_ctrl" protect="rw">
        <bits access="rw" name="tport_clk_sel" pos="27:24" rst="0">
          <comment>select tport clock</comment>
        </bits>
        <bits access="rw" name="tport_trig_sel" pos="19:16" rst="0">
          <comment>select tport trigger</comment>
        </bits>
        <bits access="rw" name="tport_data1_sel" pos="11:8" rst="0">
          <comment>select tport data1</comment>
        </bits>
        <bits access="rw" name="tport_data0_sel" pos="3:0" rst="9">
          <comment>select tport data0</comment>
        </bits>
      </reg>
      <reg name="rf_pllfreq_sel_0" protect="rw">
        <bits access="rw" name="pllfreq_sel_31_0" pos="31:0" rst="0">
          <comment>select pll frequency for rf/modem for channel 0~31
1 for 214.5MHz and 0 for 208MHz</comment>
        </bits>
      </reg>
      <reg name="rf_pllfreq_sel_1" protect="rw">
        <bits access="rw" name="pllfreq_sel_63_32" pos="31:0" rst="0">
          <comment>select pll frequency for rf/modem for channel 32~63
1 for 214.5MHz and 0 for 208MHz</comment>
        </bits>
      </reg>
      <reg name="rf_pllfreq_sel_2" protect="rw">
        <bits access="rw" name="pllfreq_sel_78_64" pos="14:0" rst="0">
          <comment>select pll frequency for rf/modem for channel 64~78
1 for 214.5MHz and 0 for 208MHz</comment>
        </bits>
      </reg>
      <reg name="trx_on_force" protect="rw">
        <bits access="rw" name="tx_cal_en" pos="5" rst="0">
          <comment>tx calibration enable</comment>
        </bits>
        <bits access="rw" name="rx_cal_en" pos="4" rst="0">
          <comment>rx calibration enable</comment>
        </bits>
        <bits access="rw" name="txon_force" pos="3" rst="0">
          <comment>force txon for rf to txon_value when txon_force is 1</comment>
        </bits>
        <bits access="rw" name="txon_value" pos="2" rst="0">
      </bits>
        <bits access="rw" name="rxon_force" pos="1" rst="0">
          <comment>force rxon for rf to rxon_value when rxon_force is 1</comment>
        </bits>
        <bits access="rw" name="rxon_value" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="trx_on_timing" protect="rw">
        <bits access="rw" name="modem_txon_delay" pos="31:24" rst="32">
          <comment>delay time in us to enable modem tx after link layer txon enable</comment>
        </bits>
        <bits access="rw" name="modem_rf_txoff_delay" pos="23:16" rst="5">
          <comment>delay time in us to disable modem&amp;rf tx after link layer txon disable</comment>
        </bits>
        <bits access="rw" name="modem_rxon_delay" pos="15:8" rst="32">
          <comment>delay time in us to enable modem rx after link layer rxon enable</comment>
        </bits>
        <bits access="rw" name="modem_rf_rxoff_delay" pos="7:0" rst="0">
          <comment>delay time in us to disable modem&amp;rf rx after link layer rxon disable</comment>
        </bits>
      </reg>
      <reg name="rccal_ctrl" protect="rw">
        <bits access="rw" name="rccal_length" pos="15:8" rst="32">
          <comment>number of rc clock cycles when doing rc calibration</comment>
        </bits>
        <bits access="rw" name="rccal_auto" pos="1" rst="1">
          <comment>enable automatic rc calibration when BT wakeup</comment>
        </bits>
        <bits access="rs" name="rccal_start" pos="0" rst="0">
          <comment>bit type is changed from w1s to rs.
          rc calibration start by software</comment>
        </bits>
      </reg>
      <reg name="rccal_output" protect="r">
        <bits access="r" name="rccal_done" pos="31" rst="0">
          <comment>indicate rc caliration done</comment>
        </bits>
        <bits access="r" name="rccal_result" pos="17:0" rst="0">
          <comment>number of reference clock cycles when doing rc calibration.
F(rc) = F(ref) * rccal_length / rccal_result</comment>
        </bits>
      </reg>
      <reg name="coex_ctrl" protect="rw">
        <bits access="rw" name="bt_active_mode" pos="5:4" rst="0">
          <comment>BT active indicater:
0: rf_txon
1: rf_rxon
2: rf_txon | rf_rxon
3: modem_txon | modem_rxon</comment>
        </bits>
        <bits access="rw" name="mws_mask_bt_en" pos="2" rst="0">
          <comment>0: BT tx will not be masked
1: BT tx will be masked</comment>
        </bits>
        <bits access="rw" name="mws_mask_bt_mode" pos="1:0" rst="0">
          <comment>BT tx will be masked when:
0: mws_tx
1: mws_rx
2: mws_tx | mws_rx
3: mws_tx &amp; mws_rx</comment>
        </bits>
      </reg>
      <reg name="osc_en_ctrl" protect="rw">
        <bits access="r" name="osc_en_stat" pos="1" rst="1">
          <comment>status of osc_en. 1 means BT is using clock derived from oscillator</comment>
        </bits>
        <bits access="rw" name="osc_en_mask" pos="0" rst="0">
          <comment>when set to 1, mask bt2pmu_wakeup output to 0 to avoid unnecessary wakeup</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_bt_link.xml">
    <module category="wcn" name="WCN_BT_LINK">
      <reg name="rwbtcnt" protect="rw">
        <bits access="w" name="master_soft_rst" pos="31" rst="0">
          <comment>Reset the complete RW-BT Core except timing generator and register blocks, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. In case of Dual Mode implementation, reset also common blocks.</comment>
        </bits>
        <bits access="w" name="master_tgsoft_rst" pos="30" rst="0">
          <comment>Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="reg_soft_rst" pos="29" rst="0">
          <comment>Reset the complete register block, when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="swint_req" pos="28" rst="0">
          <comment>Forces  the  generation  of  bt_sw_irq  when  written  with  a  1,  and  proper  masking  is  set.  Resets  at  0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="scan_abort" pos="27" rst="0">
          <comment>Abort the current Inquiry / Page / Broadcast scan window when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="rftest_abort" pos="26" rst="0">
          <comment>Abort the current RF Testing when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.
Note that when RFTEST_ABORT is requested
1/ In case of infinite Tx, the Packet Controller FSM stops at the  end of the  current byte in process, and processes accordingly the packet CRC.
2/  In  case  of  Infinite  Rx,  the  Packet  Controller  FSM  either  stops  as  the  end  of  the  current  Packet reception (if Access address has been detected), or simply stop the processing switching off the RF.</comment>
        </bits>
        <bits access="w" name="pageinq_abort" pos="25" rst="0">
          <comment>Abort the current Inquiry Mode or Page Mode when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="sniff_abort" pos="24" rst="0">
          <comment>Abort the current Sniff Mode when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="rw" name="flowdsb" pos="23" rst="0">
          <comment>0: FLOW verification on Rx packets is activated.
1: Packets are accepted regardless of FLOW value (test mode).</comment>
        </bits>
        <bits access="rw" name="lmpflowdsb" pos="21" rst="0">
          <comment>0: When FLOW = 0, LMP messages can be sent.
1: When FLOW = 0, LMP messages are not sent.</comment>
        </bits>
        <bits access="rw" name="cryptdsb" pos="20" rst="0">
          <comment>0: Normal operation. Encryption enabled when required.
1: Encryption disabled.
Note this works for both E0 and AES-CCM encryption mechanism</comment>
        </bits>
        <bits access="rw" name="whitdsb" pos="19" rst="0">
          <comment>0: Normal operation. Whitening enabled.
1: Whitening disabled.</comment>
        </bits>
        <bits access="rw" name="arqndsb" pos="18" rst="0">
          <comment>0: ARQN verification on Rx packets is activated.
1: Packets are accepted regardless of ARQN value (test mode).</comment>
        </bits>
        <bits access="rw" name="crcdsb" pos="17" rst="0">
          <comment>0: Normal operation. CRC removed from incoming data stream.
1: CRC stripping disabled on Rx packets.</comment>
        </bits>
        <bits access="rw" name="hopdsb" pos="16" rst="0">
          <comment>0: Normal operation. Hopping enabled.
1: Hopping disabled, the frequency is set either by CS-FREQ or by RFTESTFREQ register fields.</comment>
        </bits>
        <bits access="rw" name="seqndsb" pos="15" rst="0">
          <comment>0: SEQN verification on Rx packets is activated.
1: Packets are accepted regardless of SEQN value (test mode).</comment>
        </bits>
        <bits access="rw" name="cx_txbsyena" pos="14" rst="1">
          <comment>This    field    updates    the    CS-TXBSY_EN    field    in    the    control    structure    when    ends    a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame.</comment>
        </bits>
        <bits access="rw" name="cx_rxbsyena" pos="13" rst="1">
          <comment>This    field    updates    the    CS-RXBSY_EN    field    in    the    control    structure    when    ends    a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame.</comment>
        </bits>
        <bits access="rw" name="cx_dnabort" pos="12" rst="1">
          <comment>This    field    updates    the    CS-DNABORT    field    in    the    control    structure    when    ends    a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame.</comment>
        </bits>
        <bits access="rw" name="rwbten" pos="8" rst="0">
          <comment>0: Disable RW-BT Core.
1: Enable RW-BT Core.</comment>
        </bits>
        <bits access="rw" name="syncerr" pos="3:0" rst="0">
          <comment>Indicate the maximum number of errors allowed to recognize the Access Code.</comment>
        </bits>
      </reg>
      <reg name="version" protect="r">
        <bits access="r" name="typ" pos="31:24" rst="8">
          <comment>RW-BT Core Type C 0x8 means BT v4.2 (i.e. correspond LM version assigned  number). Correspond to FS v8.0.11</comment>
        </bits>
        <bits access="r" name="rel" pos="23:16" rst="0">
          <comment>Version of the RW-BT Core C Major release number. Correspond to FS v8.0.11.</comment>
        </bits>
        <bits access="r" name="upg" pos="15:8" rst="11">
          <comment>Version of the RW-BT Core C Upgrade number. Correspond to FS v8.0.11</comment>
        </bits>
        <bits access="r" name="build_num" pos="7:0" rst="0">
          <comment>RW-BT Core Build number</comment>
        </bits>
      </reg>
      <reg name="rwbtconf" protect="r">
        <bits access="r" name="dmmode" pos="31" rst="1">
          <comment>0: RW-BT Core is used as a standalone BR/EDR device
1: RW-BT Core is used in a Dual Mode device</comment>
        </bits>
        <bits access="r" name="mwswci2" pos="27" rst="0">
          <comment>0: MWS Coexistence 2-Wire Interface not supported
1: MWS Coexistence 2-Wire Interface supported</comment>
        </bits>
        <bits access="r" name="mwswci1" pos="26" rst="0">
          <comment>0: MWS Coexistence 1-Wire Interface not supported
1: MWS Coexistence 1-Wire Interface supported</comment>
        </bits>
        <bits access="r" name="vxportnb" pos="25:24" rst="3">
          <comment>Number of supported Audio Channel (0 to 3)
00: No Audio Channel / No PCM.
01: One Audio Channel
10: Two Audio Channels
11: Three Audio Channels.</comment>
        </bits>
        <bits access="r" name="pcm" pos="23" rst="1">
          <comment>0: PCM Not Instantiated
1: PCM Instantiated</comment>
        </bits>
        <bits access="r" name="mwscoex" pos="22" rst="0">
          <comment>0: MWS Coexistence mechanism not present
1: MWS Coexistence mechanism present</comment>
        </bits>
        <bits access="r" name="wlancoex" pos="21" rst="0">
          <comment>0: WLAN Coexistence mechanism not present
1: WLAN Coexistence mechanism present</comment>
        </bits>
        <bits access="r" name="rfif" pos="20:16" rst="1">
          <comment>RFIF[k]= 0: Control logic supporting radio k not present
RFIF[k]= 1: Control logic supporting radio k present
Index k values are:
00001: RW-BT Ripple RF.
00010: External Radio Controller Support
xxxx00: Reserved</comment>
        </bits>
        <bits access="r" name="usedbg" pos="15" rst="1">
          <comment>0: Diagnostics port not present
1: Diagnostics port present</comment>
        </bits>
        <bits access="r" name="usecrypt" pos="14" rst="1">
          <comment>0: AES-CCM Encryption block not present
1: AES-CCM Encryption block present</comment>
        </bits>
        <bits access="r" name="clk_sel" pos="13:8" rst="13">
          <comment>Operating Frequency (in MHz)
Default is 13 MHz</comment>
        </bits>
        <bits access="r" name="intmode" pos="7" rst="1">
          <comment>0: Interrupts are edge level generated, i.e. pulse.
1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement</comment>
        </bits>
        <bits access="r" name="bus_type" pos="6" rst="0">
          <comment>Processor Bus Type
0: AHB Bus
1: X-Bar Bus</comment>
        </bits>
        <bits access="r" name="data_width" pos="5" rst="1">
          <comment>Processor Data bus width:
0 16 bits
1: 32 bits</comment>
        </bits>
        <bits access="r" name="addr_width" pos="4:0" rst="16">
          <comment>Value of the RW_BT_ADDRESS_WIDTH parameter converted into binary.</comment>
        </bits>
      </reg>
      <reg name="intcntl" protect="rw">
        <bits access="rw" name="sketintmsk" pos="17" rst="0">
          <comment>Skipped Exchange Table entry Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="swintmsk" pos="16" rst="0">
          <comment>SW triggered Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="frameapfaintmsk" pos="15" rst="0">
          <comment>End of Frame Interrupt / Anticipated Pre-Fetch Abort mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="frameintmsk" pos="14" rst="0">
          <comment>End of Frame Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="mwswcirxintmsk" pos="13" rst="0">
          <comment>MWS Serial Interface Rx Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="mwswcitxintmsk" pos="12" rst="0">
          <comment>MWS Serial Interface Tx Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="errorintmsk" pos="11" rst="0">
          <comment>Error Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="grosstgtintmsk" pos="10" rst="0">
          <comment>Gross Target Timer Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="finetgtintmsk" pos="9" rst="0">
          <comment>Fine Target Timer Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="mtoffint1msk" pos="8" rst="0">
          <comment>Momentary Offset 1 event Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="mtoffint0msk" pos="7" rst="0">
          <comment>Momentary Offset 0 event Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="frsyncintmsk" pos="6" rst="0">
          <comment>Frame Synchronization Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="audioint2msk" pos="5" rst="0">
          <comment>Audio Channel 2 Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="audioint1msk" pos="4" rst="0">
          <comment>Audio Channel 1 Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="audioint0msk" pos="3" rst="0">
          <comment>Audio Channel 0 Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="slpintmsk" pos="2" rst="1">
          <comment>End of Sleep Interrupt Mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="rxintmsk" pos="1" rst="1">
          <comment>Packet Receipt Interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
        <bits access="rw" name="clknintmsk" pos="0" rst="1">
          <comment>CLKN / Slot interrupt mask
0: Interrupt not generated
1: Interrupt generated</comment>
        </bits>
      </reg>
      <reg name="intstat" protect="r">
        <bits access="r" name="sketintstat" pos="17" rst="0">
          <comment>Skipped Exchange Table entry Interrupt status
0: No Skipped Exchange Table entry Interrupt
1: Skipped Exchange Table entry Interrupt is pending</comment>
        </bits>
        <bits access="r" name="swintstat" pos="16" rst="0">
          <comment>SW Triggered Interrupt status
0: No SW triggered Interrupt
1: SW Triggered Interrupt is pending</comment>
        </bits>
        <bits access="r" name="frameapfaintstat" pos="15" rst="0">
          <comment>End of Frame / Anticipated Pre-Fetch Abort Interrupt status
0: No End of Frame Interrupt
1: End of Frame Interrupt is pending</comment>
        </bits>
        <bits access="r" name="frameintstat" pos="14" rst="0">
          <comment>End of Frame Interrupt status
0: No End of Frame Interrupt
1: End of Frame Interrupt is pending</comment>
        </bits>
        <bits access="r" name="mwswcirxintstat" pos="13" rst="0">
          <comment>MWS Serial Interface Rx Interrupt status
0: No MWS WCI Interrupt
1: MWS WCI Interrupt is pending</comment>
        </bits>
        <bits access="r" name="mwswcitxintstat" pos="12" rst="0">
          <comment>MWS Serial Interface Tx Interrupt status
0: No MWS WCI Interrupt
1: MWS WCI Interrupt is pending</comment>
        </bits>
        <bits access="r" name="errorintstat" pos="11" rst="0">
          <comment>Error Interrupt status.
0: No Error interrupt.
1: Error interrupt is pending.</comment>
        </bits>
        <bits access="r" name="grosstgtintstat" pos="10" rst="0">
          <comment>Gross Timer Interrupt status.
0: No Gross Timer interrupt.
1: Gross Timer interrupt is pending.</comment>
        </bits>
        <bits access="r" name="finetgtintstat" pos="9" rst="0">
          <comment>Fine Timer Interrupt status.
0: No Fine Timer interrupt.
1: Fine Timer interrupt is pending.</comment>
        </bits>
        <bits access="r" name="mtoffint1stat" pos="8" rst="0">
          <comment>Momentary Offset 1 Interrupt status.
0: No Momentary Offset interrupt.
1: Momentary offset interrupt is pending and the newly calculated momentary offset is lower than the correction step</comment>
        </bits>
        <bits access="r" name="mtoffint0stat" pos="7" rst="0">
          <comment>Momentary Offset 0 Interrupt status.
0: No Momentary Offset interrupt.
1: Momentary offset interrupt is pending and the newly calculated momentary offset is greater than the correction step</comment>
        </bits>
        <bits access="r" name="frsyncintstat" pos="6" rst="0">
          <comment>MWS Frame Synchronization Interrupt status.
0: No frame_sync interrupt.
1: A frame_sync interrupt is pending.</comment>
        </bits>
        <bits access="r" name="audioint2stat" pos="5" rst="0">
          <comment>Audio Channel 2 Interrupt status.
0: No eSCO SW Transport interrupt.
1: An eSCO SW Transport interrupt is pending.</comment>
        </bits>
        <bits access="r" name="audioint1stat" pos="4" rst="0">
          <comment>Audio Channel 1 Interrupt status.
0: No eSCO SW Transport interrupt.
1: An eSCO SW Transport interrupt is pending.</comment>
        </bits>
        <bits access="r" name="audioint0stat" pos="3" rst="0">
          <comment>Audio Channel 0 Interrupt status.
0: No eSCO SW Transport interrupt.
1: An eSCO SW Transport interrupt is pending.</comment>
        </bits>
        <bits access="r" name="slpintstat" pos="2" rst="0">
          <comment>end of Sleep Interrupt Status.
0: No End of Sleep Mode interrupt.
1: An End of Sleep Mode interrupt is pending.</comment>
        </bits>
        <bits access="r" name="rxintstat" pos="1" rst="0">
          <comment>Packet Reception Interrupt status.
0: No Rx interrupt.
1: An Rx interrupt is pending.</comment>
        </bits>
        <bits access="r" name="clknintstat" pos="0" rst="0">
          <comment>Slot Interrupt status.
0: No CLKN interrupt.
1: A CLKN interrupt is pending.</comment>
        </bits>
      </reg>
      <reg name="intrawstat" protect="r">
        <bits access="r" name="sketintrawstat" pos="17" rst="0">
          <comment>Skipped Exchange Table entry Interrupt raw status
0: No Skipped Exchange Table entry Interrupt
1: Skipped Exchange Table entry Interrupt is pending</comment>
        </bits>
        <bits access="r" name="swintrawstat" pos="16" rst="0">
          <comment>SW Triggered Interrupt raw status
0: No SW Triggered Interrupt
1: SW Triggered Interrupt is pending</comment>
        </bits>
        <bits access="r" name="frameapfaintrawstat" pos="15" rst="0">
          <comment>End of Frame / Anticipated Pre-Fetch Abort Interrupt raw status
0: No End of Frame Interrupt
1: End of Frame Interrupt is pending</comment>
        </bits>
        <bits access="r" name="frameintrawstat" pos="14" rst="0">
          <comment>End of Frame Interrupt raw status
0: No End of Frame Interrupt
1: End of Frame Interrupt is pending</comment>
        </bits>
        <bits access="r" name="mwswcirxintrawstat" pos="13" rst="0">
          <comment>MWS Serial Interface Rx Interrupt raw status
0: No MWS WCI Interrupt
1: MWS WCI Interrupt is pending</comment>
        </bits>
        <bits access="r" name="mwswcitxintrawstat" pos="12" rst="0">
          <comment>MWS Serial Interface Tx Interrupt raw status
0: No MWS WCI Interrupt
1: MWS WCI Interrupt is pending</comment>
        </bits>
        <bits access="r" name="errorintrawstat" pos="11" rst="0">
          <comment>Error Interrupt raw status.
0: No Error interrupt.
1: Error interrupt is pending.</comment>
        </bits>
        <bits access="r" name="grosstgtintrawstat" pos="10" rst="0">
          <comment>Gross Timer Interrupt raw status.
0: No Gross Timer interrupt.
1: Gross Timer interrupt is pending.</comment>
        </bits>
        <bits access="r" name="finetgtintrawstat" pos="9" rst="0">
          <comment>Fine Timer Interrupt raw status.
0: No Fine Timer interrupt.
1: Fine Timer interrupt is pending.</comment>
        </bits>
        <bits access="r" name="mtoffint1rawstat" pos="8" rst="0">
          <comment>Momentary Offset 1 Interrupt raw status.
0: No Momentary Offset interrupt.
1:  Momentary  offset  interrupt  is  pending  and  the  newly  calculated  momentary  offset  is  lower than the correction step</comment>
        </bits>
        <bits access="r" name="mtoffint0rawstat" pos="7" rst="0">
          <comment>Momentary Offset 0 Interrupt raw status.
0: No Momentary Offset interrupt.
1: Momentary offset interrupt is pending and the newly calculated momentary offset is greater than the correction step</comment>
        </bits>
        <bits access="r" name="frsyncintrawstat" pos="6" rst="0">
          <comment>MWS Frame Synchronization Interrupt raw status.
0: No frame_sync interrupt.
1: A frame_sync interrupt is pending.</comment>
        </bits>
        <bits access="r" name="audioint2rawstat" pos="5" rst="0">
          <comment>Audio Channel 2 Interrupt raw status.
0: No eSCO SW Transport interrupt.
1: An eSCO SW Transport interrupt is pending.</comment>
        </bits>
        <bits access="r" name="audioint1rawstat" pos="4" rst="0">
          <comment>Audio Channel 1 Interrupt raw status.
0: No eSCO SW Transport interrupt.
1: An eSCO SW Transport interrupt is pending.</comment>
        </bits>
        <bits access="r" name="audioint0rawstat" pos="3" rst="0">
          <comment>Audio Channel 0 Interrupt raw status.
0: No eSCO SW Transport interrupt.
1: An eSCO SW Transport interrupt is pending.</comment>
        </bits>
        <bits access="r" name="slpintrawstat" pos="2" rst="0">
          <comment>End of Sleep Interrupt raw Status.
0: No End of Sleep Mode interrupt.
1: An End of Sleep Mode interrupt is pending.</comment>
        </bits>
        <bits access="r" name="rxintrawstat" pos="1" rst="0">
          <comment>Packet Reception Interrupt raw status.
0: No Rx interrupt.
1: An Rx interrupt is pending.</comment>
        </bits>
        <bits access="r" name="clknintrawstat" pos="0" rst="0">
          <comment>Slot Interrupt raw status.
0: No CLKN interrupt.
1: A CLKN interrupt is pending.</comment>
        </bits>
      </reg>
      <reg name="intack" protect="rw">
        <bits access="s" name="sketintack" pos="17" rst="0">
          <comment>bit type is changed from wos to s.
          Skipped Exchange Table entry Interrupt acknowledgment.
Software  writing  1  acknowledges  the   Skipped  Exchange  Table  entry   interrupt.  This  bit  resets SKETINTSTAT and SKETINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="swintack" pos="16" rst="0">
          <comment>bit type is changed from wos to s.
          SW triggered Interrupt acknowledgment.
Software   writing   1   acknowledges   the   SW   triggered   interrupt.   This   bit   resets   SWINTSTAT   and SWINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="frameapfaintack" pos="15" rst="0">
          <comment>bit type is changed from wos to s.
          End of Frame / Anticipated Pre-Fetch Abort Interrupt acknowledgment.
Software writing 1 acknowledges the End of Frame interrupt. This bit resets FRAMEAPFAINTSTAT and FRAMEAPFAINTRWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="frameintack" pos="14" rst="0">
          <comment>bit type is changed from wos to s.
          End of Frame Interrupt acknowledgment.
Software  writing  1  acknowledges  the  End  of  Frame  interrupt.  This  bit  resets  FRAMEINTSTAT  and FRAMEINTRWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="mwswcirxintack" pos="13" rst="0">
          <comment>bit type is changed from wos to s.
          MWS Serial Interface Rx Interrupt acknowledgment.
Software writing 1 acknowledges the MWS Serial Interface interrupt. This bit resets MWSWCIINTSTAT and MWSWCIINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="mwswcitxintack" pos="12" rst="0">
          <comment>bit type is changed from wos to s.
          MWS Serial Interface Tx Interrupt acknowledgment.
Software writing 1 acknowledges the MWS Serial Interface interrupt. This bit resets MWSWCIINTSTAT and MWSWCIINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="errorintack" pos="11" rst="0">
          <comment>bit type is changed from wos to s.
          Error Interrupt acknowledgment.
Software   writing   1   acknowledges   the   Error   interrupt.   This   bit   resets   ERRORINTSTAT   and ERRORINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="grosstgtintack" pos="10" rst="0">
          <comment>bit type is changed from wos to s.
          Gross Timer Interrupt acknowledgment.
Software  writing  1  acknowledges  the  Gross  Timer  interrupt.  This  bit  resets  GROSSTGTINTSTAT  and GROSSTGTINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="finetgtintack" pos="9" rst="0">
          <comment>bit type is changed from wos to s.
          Fine Timer Interrupt acknowledgment.
Software  writing  1  acknowledges  the  Fine  Timer  interrupt.  This  bit  resets  FINETGTINTSTAT  and FINETGTINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="mtoffint1ack" pos="8" rst="0">
          <comment>bit type is changed from wos to s.
          Momentary Offset 1 Interrupt acknowledgment.
Software    writing    1    acknowledges    the    Momentary    offset    event    interrupt.    This    bit    resets MTOFFINT1STAT and MTOFFINT1RAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="mtoffint0ack" pos="7" rst="0">
          <comment>bit type is changed from wos to s.
          Momentary Offset 0 Interrupt acknowledgment.
Software    writing    1    acknowledges    the    Momentary    offset    event    interrupt.    This    bit    resets MTOFFINT0STAT and MTOFFINT0RAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="frsyncintack" pos="6" rst="0">
          <comment>bit type is changed from wos to s.
          MWS Frame Synchronization Interrupt acknowledgement.
Software writing 1 acknowledges the  frame_sync event interrupt. This bit resets FRSYNCINTSTAT and FRSYNCINTRAWSTAT flag.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="audioint2ack" pos="5" rst="0">
          <comment>bit type is changed from wos to s.
          Audio Channel 2 Interrupt acknowledgement.
Software  writing  1  acknowledges  the  Audio  Channel  2  interrupt.  This  bit  resets  AUDIOINT2STAT  and AUDIOINT2RAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="audioint1ack" pos="4" rst="0">
          <comment>bit type is changed from wos to s.
          Audio Channel 1 Interrupt acknowledgement.
Software  writing  1  acknowledges  the  Audio  Channel  1  interrupt.  This  bit  resets  AUDIOINT1STAT  and AUDIOINT1RAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="audioint0ack" pos="3" rst="0">
          <comment>bit type is changed from wos to s.
          Audio Channel 0 Interrupt acknowledgement.
Software  writing  1  acknowledges  the  Audio  Channel  0  interrupt.  This  bit  resets  AUDIOINT0STAT  and AUDIOINT0RAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="slpintack" pos="2" rst="0">
          <comment>bit type is changed from wos to s.
          End of Sleep Interrupt acknowledgement.
Software  writing  1  acknowledges  the  End  of  Sleep  Mode  interrupt.  This  bit  resets  SLPINTSTAT  and SLPINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="rxintack" pos="1" rst="0">
          <comment>bit type is changed from wos to s.
          Packet Reception Interrupt acknowledgement.
Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
        <bits access="s" name="clknintack" pos="0" rst="0">
          <comment>bit type is changed from wos to s.
          Slot Interrupt acknowledgement.
Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags.
Resets at 0 when action is performed</comment>
        </bits>
      </reg>
      <reg name="slotclk" protect="rw">
        <bits access="w" name="samp" pos="31" rst="0">
          <comment>Writing a 1 samples the CLKN[27:0] value in SLOTCLK-SCLK register field.
Resets at 0 when action is performed. No action happens if it is written with 0</comment>
        </bits>
        <bits access="w" name="clkn_upd" pos="30" rst="0">
          <comment>Update the Native Bluetooth counter CLKN[27:1] (CLKN[0] is not considered), when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="rw" name="sclk" pos="27:0" rst="0">
          <comment>Native Bluetooth counter CLKN sampled at the time the processor has written the SAMP bit (precsision of 312.5s).  This  value  does  not  change  until  the  next  writing  of  SAMP  bit,  and  can  therefore  be  safely accessed with 8-, 16- or 32-bits accesses.</comment>
        </bits>
      </reg>
      <reg name="finetimecnt" protect="r">
        <bits access="r" name="finecnt" pos="9:0" rst="0">
          <comment>Value of the current s fine time reference counter sampled at the time the processor has written the SAMP bit. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration</comment>
        </bits>
      </reg>
      <reg name="abtraincnt" protect="rw">
        <bits access="rw" name="abtpageen" pos="31" rst="0">
          <comment>Enable automatic A-train/B-train switch during Page procedure.
0: Page procedure A-train/B-train counter disabled
1: Page procedure A-train/B-train counter enabled</comment>
        </bits>
        <bits access="rw" name="abtpagestartvalue" pos="30" rst="0">
          <comment>Starting train value of Page procedure
0:Start with A-train
1:Start with B-train</comment>
        </bits>
        <bits access="w" name="abtpageload" pos="28" rst="0">
          <comment>Load A-train/B-train Page procedure conter, when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="rw" name="abtpagetime" pos="26:16" rst="256">
          <comment>Defines A-train/B-train duration time during Page procedure, counted by 16-slots.
Loaded when ABTPAGELOAD is set. Start when Page procedure starts and ABTPAGEEN is set. Stops when  ABTPAGEEN is reset. Switch of train when wrapping.</comment>
        </bits>
        <bits access="rw" name="abtinqen" pos="15" rst="0">
          <comment>Enable automatic A-train/B-train switch during Inquiry procedure.
0: Inquiry procedure A-train/B-train counter disabled
1: Inquiry procedure A-train/B-train counter enabled</comment>
        </bits>
        <bits access="rw" name="abtinqstartvalue" pos="14" rst="0">
          <comment>Starting train value of Inquiry procedure
0:Start with A-train
1:Start with B-train</comment>
        </bits>
        <bits access="w" name="abtinqload" pos="12" rst="0">
          <comment>Load A-train/B-train Inquiry procedure conter, when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="rw" name="abtinqtime" pos="10:0" rst="256">
          <comment>Defines A-train/B-train duration time during Inquiry procedure, counted by 16-slots.
Loaded when ABTINQLOAD is set. Start when Inquiry procedure starts and ABTINQEN is set. Stops when  ABTINQEN is reset. Switch of train when wrapping.</comment>
        </bits>
      </reg>
      <reg name="edrcntl_nwinsize" protect="rw">
        <bits access="rw" name="nwinsize" pos="31:24" rst="26">
          <comment>Default value equals d26. Should not exceed 'h88.
Applies when ET-SNIFF = 1 on first access code detection, in order to process the new bit offset (See section 3.5.5)</comment>
        </bits>
        <bits access="rw" name="edrbcast" pos="16" rst="0">
          <comment>0: Broadcast @ 1Mbps / normal mode
1: Broadcast operation in EDR Mode (@ 2/3 Mbps) / special features
The EDRCNTL-EDRBCAST bit is used in reception (slave side) as following:
if RXLTADDR= 0 (i.e. broadcast packet is received)
    if  EDRCNTL-EDRBCAST=0  ,  we consider  the  currently  received packet  is  not  an  EDR-packet. The 1Mbps modulation is used.
    if EDRCNTL-EDRBCAST=1, then apply EDR modulation or not depending on the control structure bit &quot; ACLEDR&quot; set in MISCNTL field.</comment>
        </bits>
        <bits access="rw" name="rxguarddsb" pos="15" rst="0">
          <comment>0: normal operation, EDR Rx guard window detection activated
1: EDR Rx guard window detection disabled.</comment>
        </bits>
        <bits access="rw" name="tx_swap" pos="14" rst="1">
          <comment>0: Direct order EDR Payload data transmit
1: Reverse order EDR Payload data transmit</comment>
        </bits>
        <bits access="rw" name="rx_swap" pos="13" rst="1">
          <comment>0: Direct order EDR Payload data receive
1: Reverse order EDR Payload data receive</comment>
        </bits>
        <bits access="rw" name="rxgrd_timeout" pos="9:0" rst="1023">
          <comment>Time out value before EDR packet reception that allow ending the Rx transaction if an EDR packet is not correctly detected.
Default value is set to 212 clock cycles @ 13MHz &lt;-&gt; 16.3us. Timing between Packet Header and EDR packet is defined as 5us+-0.25us + 11 synchronization symbol = 16.25us in the worst case</comment>
        </bits>
      </reg>
      <reg name="et_currentrxdescptr" protect="rw">
        <bits access="rw" name="etptr" pos="31:16" rst="0">
          <comment>Exchange Table pointer value</comment>
        </bits>
        <bits access="rw" name="currentrxdescptr" pos="14:0" rst="0">
          <comment>Rx Descriptor current pointer value</comment>
        </bits>
      </reg>
      <reg name="deepslcntl" protect="rw">
        <bits access="rw" name="extwkupdsb" pos="31" rst="0">
          <comment>External Wake-Up disable
0: RW-BT Core can be woken by external wake-up
1: RW-BT Core cannot be woken up by external wake-up</comment>
        </bits>
        <bits access="rw" name="ext_high_wakeup_en" pos="30" rst="0">
          <comment>Enable external pin high level wakeup</comment>
        </bits>
        <bits access="rw" name="ext_low_wakeup_en" pos="29" rst="0">
          <comment>Enable external pin low level wakeup</comment>
        </bits>
        <bits access="rw" name="ext_activity_wakeup_en" pos="28" rst="0">
          <comment>Enable external pin activity wakeup</comment>
        </bits>
        <bits access="r" name="deep_sleep_stat" pos="15" rst="0">
          <comment>Indicator of current Deep Sleep clock mux status:
0: RW-BT Core is not yet in Deep Sleep Mode
1: RW-BT Core is in Deep Sleep Mode (only low_power_clk is running)</comment>
        </bits>
        <bits access="w" name="soft_wakeup_req" pos="4" rst="0">
          <comment>Wake Up Request from RW-BT Software. Applies when system is in Deep Sleep Mode. It wakes up the RW-BT Core when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="deep_sleep_corr_en" pos="3" rst="0">
          <comment>CLKN  integer  and  fractional  part  correction  (i.e.  CLKN  Counter  and  Fine  Counter).  Applies  when system has been woken-up from Deep Sleep Mode. It enables Fine Counter and Base Time counter when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="w" name="deep_sleep_on" pos="2" rst="0">
          <comment>RW-BT Core sleep mode request control
0: RW-BT Core in normal active mode
1: Request RW-BT Core to switch in deep sleep mode.
This bit is reset on DEEP_SLEEP_STAT falling edge.</comment>
        </bits>
        <bits access="rw" name="radio_sleep_en" pos="1" rst="0">
          <comment>Controls the Radio module
0: Radio stands in normal active mode
1: Allow to disable Radio</comment>
        </bits>
        <bits access="rw" name="osc_sleep_en" pos="0" rst="1">
          <comment>Controls the RF High frequency crystal oscillator
0: High frequency crystal oscillator stands in normal active mode
1: Allow to disable High frequency crystal oscillator</comment>
        </bits>
      </reg>
      <reg name="deepslwkup" protect="rw">
        <bits access="rw" name="deepsltime" pos="31:0" rst="0">
          <comment>Determines the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device. This ensures a maximum of 37 hours and 16mn sleep mode capabilities at 32kHz. This ensures a maximum of 36 hours and 16mn sleep mode capabilities at 32.768kHz</comment>
        </bits>
      </reg>
      <reg name="deepslstat" protect="r">
        <bits access="r" name="deepsldur" pos="31:0" rst="0">
          <comment>Actual duration of the last deep sleep phase measured in low power oscillator cycles. DEEPSLDUR is set to zero at the beginning of the deep sleep phase, and is incremented at each low power clock tick until the end of the deep sleep phase.</comment>
        </bits>
      </reg>
      <reg name="enbpreset" protect="rw">
        <bits access="rw" name="twext" pos="31:21" rst="160">
          <comment>Time in low power oscillator cycles allowed for stabilization of the high frequency oscillator following an external wake-up request (signal wakeup_req) [064ms for 32kHz)</comment>
        </bits>
        <bits access="rw" name="twosc" pos="20:10" rst="160">
          <comment>Time  in  low  power  oscillator  cycles  allowed  for  stabilization  of  the  high  frequency  oscillator  when  the deep-sleep mode has been left due to sleep-timer expiry (DEEPSLWKUP) [064ms for 32kHz)</comment>
        </bits>
        <bits access="rw" name="twrm" pos="9:0" rst="32">
          <comment>Time in low power oscillator cycles allowed for the radio module to leave low-power mode  [032ms for 32kHz)</comment>
        </bits>
      </reg>
      <reg name="finecntcorr" protect="rw">
        <bits access="rw" name="finecntcorr" pos="9:0" rst="0">
          <comment>Phase correction value for the CLKN counter in s.</comment>
        </bits>
      </reg>
      <reg name="clkncntcorr" protect="rw">
        <bits access="rw" name="abs_delta" pos="31" rst="0">
          <comment>Determines whether CLNCNTCORR is an absolute correction or a signed delta increment correction
0: Absolute correction
1: Signed delta increment correction</comment>
        </bits>
        <bits access="rw" name="clkncntcorr" pos="27:0" rst="0">
          <comment>CLKN Counter correction value / signed delta increment</comment>
        </bits>
      </reg>
      <reg name="tokencntl" protect="rw">
        <bits access="rw" name="token_tx_delay" pos="29:24" rst="5">
          <comment>Token Tx delay time after Slave receive completed</comment>
        </bits>
        <bits access="rw" name="token_rx_delay" pos="21:16" rst="5">
          <comment>Token Rx delay time after Slave receive completed</comment>
        </bits>
        <bits access="rw" name="token_quick_sync" pos="15" rst="1">
          <comment>0: Use normal sync pulse for token ID
1: Use quick sync pulse for token ID</comment>
        </bits>
        <bits access="rw" name="token_rxwin" pos="14:8" rst="8">
          <comment>Size of Token Rx Window</comment>
        </bits>
        <bits access="rw" name="arbiter_bypass" pos="3" rst="0">
          <comment>Slave arbiter receive token ID but bypass arbitration</comment>
        </bits>
        <bits access="rw" name="arbiter_en" pos="2" rst="0">
          <comment>Slave arbiter enable</comment>
        </bits>
        <bits access="rw" name="observer_active" pos="1" rst="0">
          <comment>Slave observer will respond to master</comment>
        </bits>
        <bits access="rw" name="observer_en" pos="0" rst="0">
          <comment>Slave observer enable</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="diagcntl" protect="rw">
        <bits access="rw" name="diag3_en" pos="31" rst="0">
          <comment>0: Disable diagnostic port 3 output. All outputs are set to 0.
1: Enable diagnostic port 3 output.</comment>
        </bits>
        <bits access="rw" name="diag3" pos="29:24" rst="0">
          <comment>Only relevant when DIAGEN3 = 1.
Selection of the outputs that are driven to the diagnostic port 3.</comment>
        </bits>
        <bits access="rw" name="diag2_en" pos="23" rst="0">
          <comment>0: Disable diagnostic port 2 output. All outputs are set to 0.
1: Enable diagnostic port 2 output.</comment>
        </bits>
        <bits access="rw" name="diag2" pos="21:16" rst="0">
          <comment>Only relevant when DIAGEN2 = 1.
Selection of the outputs that are driven to the diagnostic port 2.</comment>
        </bits>
        <bits access="rw" name="diag1_en" pos="15" rst="0">
          <comment>0: Disable diagnostic port 1 output. All outputs are set to 0.
1: Enable diagnostic port 1 output.</comment>
        </bits>
        <bits access="rw" name="diag1" pos="13:8" rst="0">
          <comment>Only relevant when DIAGEN1 = 1.
Selection of the outputs that are driven to the diagnostic port 1.</comment>
        </bits>
        <bits access="rw" name="diag0_en" pos="7" rst="0">
          <comment>0: Disable diagnostic port 0 output. All outputs are set to 0.
1: Enable diagnostic port 0 output.</comment>
        </bits>
        <bits access="rw" name="diag0" pos="5:0" rst="0">
          <comment>Only relevant when DIAGEN0 = 1.
Selection of the outputs that are driven to the diagnostic port 0.</comment>
        </bits>
      </reg>
      <reg name="diagstat" protect="r">
        <bits access="r" name="diag3stat" pos="31:24" rst="0">
          <comment>Directly connected to bt_dbg0[7:0] output. Debug use only</comment>
        </bits>
        <bits access="r" name="diag2stat" pos="23:16" rst="0">
          <comment>Directly connected to bt_dbg1[7:0] output. Debug use only</comment>
        </bits>
        <bits access="r" name="diag1stat" pos="15:8" rst="0">
          <comment>Directly connected to bt_dbg2[7:0] output. Debug use only</comment>
        </bits>
        <bits access="r" name="diag0stat" pos="7:0" rst="0">
          <comment>Directly connected to bt_dbg3[7:0] output. Debug use only</comment>
        </bits>
      </reg>
      <reg name="debugaddmax" protect="rw">
        <bits access="rw" name="reg_addmax" pos="31:16" rst="0">
          <comment>Upper limit for the Register zone indicated by the reg_inzone flag (see section 2.19).</comment>
        </bits>
        <bits access="rw" name="em_addmax" pos="15:0" rst="0">
          <comment>Upper limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.19).</comment>
        </bits>
      </reg>
      <reg name="debugaddmin" protect="rw">
        <bits access="rw" name="reg_addmin" pos="31:16" rst="0">
          <comment>Lower limit for the Register zone indicated by the reg_inzone flag (see section 2.19)</comment>
        </bits>
        <bits access="rw" name="em_addmin" pos="15:0" rst="0">
          <comment>Lower limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.19)</comment>
        </bits>
      </reg>
      <reg name="errortypestat" protect="r">
        <bits access="r" name="rxbuf_ptr_error" pos="21" rst="0">
          <comment>Indicates  whether  the  Rx  eSCO  (during  Voice  over  HCI  operations)  or  Rx  LM  buffer  pointer value programmed is null: this is a major programming failure.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="txbuf_ptr_error" pos="20" rst="0">
          <comment>Indicates  whether  Tx  eSCO  (during  Voice  over  HCI  operations)  or  Tx  LM  buffer  pointer  value programmed  is  null,  or  if  an  ACL  Tx  packet  is  set  with  a  non  null  length  while  no  buffer  is associated: this is a major programming failure.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="rxdesc_empty_error" pos="19" rst="0">
          <comment>Indicates  whether  Rx  Descriptor  pointer  value  programmed  in  register  is  null:  this  is  a  major programming failure / Valid for non-connected states and Broadcast Scan mode
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="txdesc_empty_error" pos="18" rst="0">
          <comment>Indicates whether Tx Descriptor pointer value programmed in Control Structure is null: this is a major programming failure / Valid for non-connected states and Broadcast mode
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="csattnb_error" pos="17" rst="0">
          <comment>Indicates  whether  ATT_NB  field  in  Control  Structure  is  null,  or  when  during  eSCO  that eSCOLTCNLT&lt;0/1/2&gt;-RETXNB&lt;0/1/2&gt; register field is null: this is a major programming failure
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="csformat_error" pos="16" rst="0">
          <comment>Indicates  whether  CS-FORMAT  has  been  programmed  with  an  invalid  value:  this  is  a  major software programming failure.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="chmap_error" pos="15" rst="0">
          <comment>Channel Map error, happens when actual number of bits set to one in selected CS-CHMAP is different from corresponding CS-NBCHGOOD at the beginning of Frequency Hopping process.
Note this is valid only if CS-AFHENA=1
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="hopunderrun_error" pos="14" rst="0">
          <comment>Calculation of the hopping frequency not done before Tx/Rx EN is asserted
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="frm_cntl_timer_error" pos="13" rst="0">
          <comment>Indicates an Frame Controller internal timing error
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="frm_cntl_emacc_error" pos="12" rst="0">
          <comment>Indicate a Frame Controller Exchange Memory Access error.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="frm_cntl_apfm_error" pos="11" rst="0">
          <comment>Indicates  Anticipated  Pre-Fetch  Mechanism  error  in  Frame  Controller:  happens  when  2 consecutive frames are programmed, and when the first frame is not completely finished while second pre-fetch instant is reached.
0: No error
1: Error occured</comment>
        </bits>
        <bits access="r" name="frm_schdl_apfm_error" pos="10" rst="0">
          <comment>Indicates  Anticipated  Pre-Fetch  Mechanism  error  in  Frame  Scheduler:  happens  when  2 consecutive frames are programmed, and when the first frame is not completely finished while second pre-fetch instant is reached.
0: No error
1: Error occured</comment>
        </bits>
        <bits access="r" name="frm_schdl_entry_error" pos="9" rst="0">
          <comment>Indicates Frame Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset)
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="mwswci_emacc_error" pos="8" rst="0">
          <comment>MWS  WCI  Exchange  Memory  access  error,  happens  when  Exchange  Memory  access  are  not served in time and Audio samples are corrupted
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="frm_schdl_emacc_error" pos="7" rst="0">
          <comment>Frame Scheduler Exchange Memory access error, happens when Exchange Memory access are not served in time and Audio samples are corrupted
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="pcm_emacc_error" pos="6" rst="0">
          <comment>PCM  Exchange  Memory  request  access  error,  happens  when  Exchange  Memory  access requests are not served in time and PCM samples are corrupted
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="audio_emacc_error" pos="5" rst="0">
          <comment>Audio EM Access Manager Exchange Memory access error, happens when Exchange Memory access are not served in time and Audio samples are corrupted
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="radiocntl_emacc_error" pos="4" rst="0">
          <comment>Radio Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and data are corrupted.
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="pktcntl_emacc_error" pos="3" rst="0">
          <comment>Packet Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and Tx/Rx data are corrupted
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="cryptmode_error" pos="2" rst="0">
          <comment>Indicates when the Encryption  mode is enabled with Connectionless Slave Broadcast (Master or Slave)
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="rxcrypt_error" pos="1" rst="0">
          <comment>Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to  Packet  Controller  requests.  A  16-bytes  block  has  to  be  decrypted  prior  the  next  block  is received by the Packet Controller
0: No error
1: Error occurred</comment>
        </bits>
        <bits access="r" name="txcrypt_error" pos="0" rst="0">
          <comment>Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to Packet Controller requests. A 16-bytes block has to be encrypted and prepared on Packet Controller request, and needs to be ready before the Packet Controller has to send ti
0: No error
1: Error occurred</comment>
        </bits>
      </reg>
      <reg name="swprofiling" protect="rw">
        <bits access="rw" name="swprof" pos="31:0" rst="0">
          <comment>Software Profiling register: used by RW-BT Software for profiling purpose: this value is copied on Diagnostic port</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="radiocntl0" protect="rw">
        <bits access="rw" name="sync_pulse_mode" pos="23" rst="0">
          <comment>Determines whether SYNC_P output will be dragged as pulse or level maintained till end of the Packet.
0: Access Code detection indicator provided as pulse
1: Access Code detection indicator provided as level</comment>
        </bits>
        <bits access="rw" name="dpcorr_en" pos="22" rst="0">
          <comment>Enables the use of the delayed DC offset compensated data path in Radio Correlator block.
1: Enable
0: Disable</comment>
        </bits>
        <bits access="rw" name="forceagc_en" pos="21" rst="0">
          <comment>Control Ripple AGC force mode based on RADIOCNTL2-FORCEAGC_LENGTH value
1: Enable
0: Disable</comment>
        </bits>
        <bits access="rw" name="spifreq" pos="6:5" rst="0">
          <comment>Frequency of the SPI clock
00: SPI clock frequency is baseband master clock frequency divided by 2 (i.e 6.5MHz @ 13MHz)
01: SPI clock frequency is baseband master clock frequency divided by 4 (i.e 3.25MHz @ 13MHz)
10: SPI clock frequency is baseband master clock frequency divided by 8 (i.e 1.67MHz @ 13MHz)
11: Do not use</comment>
        </bits>
        <bits access="r" name="spicomp" pos="1" rst="1">
          <comment>This bit is READ ONLY.
0: Indicates that the SPI transfer is in progress.
1: Indicates that the SPI transfer is complete. The RW-BT Dual Mode is ready to start another transfer.</comment>
        </bits>
        <bits access="w" name="spigo" pos="0" rst="0">
          <comment>Software writing 1 triggers the SPI access. This bit is always read as 0.</comment>
        </bits>
      </reg>
      <reg name="radiocntl1" protect="rw">
        <bits access="rw" name="xrfsel" pos="20:16" rst="1">
          <comment>Extended radio selection field
5'h00000: No radio selected
5'h00001: RivieraWaves Ripple RF (BT4.0)
5'h00010: External Radio controller support
5'h00011-5'b11111: reserved</comment>
        </bits>
        <bits access="rw" name="spiptr" pos="15:0" rst="144">
          <comment>Pointer to the buffer containing data to be transferred to or received from the SPI port.</comment>
        </bits>
      </reg>
      <reg name="radiocntl2" protect="rw">
        <bits access="rw" name="tx_delay" pos="31:24" rst="0">
          <comment>Used to compensate Modem&amp;RF Tx delay. When used, rtrip_delay should be set as Rx delay</comment>
        </bits>
        <bits access="rw" name="sync_position" pos="22:16" rst="16">
          <comment>Defines sync_p instant when provided to the Modem.</comment>
        </bits>
        <bits access="rw" name="forceagc_length" pos="11:0" rst="0">
          <comment>Defines Rx window time threshold that forces Ripple AGC to max gain</comment>
        </bits>
      </reg>
      <reg name="radiocntl3" protect="rw">
        <bits access="rw" name="freqtable_ptr" pos="15:0" rst="64">
          <comment>BR/EDR Frequency Table pointer</comment>
        </bits>
      </reg>
      <reg name="radiopwrupdn" protect="rw">
        <bits access="rw" name="rtrip_delay" pos="30:24" rst="21">
          <comment>Round Trip Delay. This correspond to the cumulated Tx plus Rx latency of the radio (in us)</comment>
        </bits>
        <bits access="rw" name="rxpwrupct" pos="23:16" rst="60">
          <comment>This register holds the  length in us of the RX power  up  phase for the current radio device. Default value is 210 us (reset value). Operating range depends on supported radio.</comment>
        </bits>
        <bits access="rw" name="txpwrdnct" pos="12:8" rst="5">
          <comment>This  register  extends  the  length  in us of the  TX  power  down  phase  for  the  current  radio  device.
Default value is 3us (reset value). Operating range depends on supported radio.</comment>
        </bits>
        <bits access="rw" name="txpwrupct" pos="7:0" rst="60">
          <comment>This  register  holds  the  length  in us of  the  TX  power  up  phase  for  the  current  radio  device.  Default value is 210 us (reset value). Operating range is depends on supported radio.</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="txmicval" protect="r">
        <bits access="r" name="txmicval" pos="31:0" rst="0">
          <comment>AES-CCM plain MIC value.</comment>
        </bits>
      </reg>
      <reg name="rxmicval" protect="r">
        <bits access="r" name="rxmicval" pos="31:0" rst="0">
          <comment>AES-CCM plain MIC value.</comment>
        </bits>
      </reg>
      <reg name="e0ptr" protect="rw">
        <bits access="rw" name="e0ptr" pos="15:0" rst="0">
          <comment>E0 Address pointer</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="rftestcntl" protect="rw">
        <bits access="rw" name="sserrren" pos="17" rst="0">
          <comment>Applicable in Slave eSCO reserved slot only
0: Normal mode of operation
1: Allow reply on Sync Error</comment>
        </bits>
        <bits access="rw" name="herrren" pos="16" rst="0">
          <comment>Applicable in Slave eSCO reserved slot only
0: Normal mode of operation
1: Allow reply on HEC Error</comment>
        </bits>
        <bits access="rw" name="infiniterx" pos="7" rst="0">
          <comment>Applicable for all frame format
0: Normal mode of operation
1: Infinite Rx window</comment>
        </bits>
        <bits access="rw" name="infinite_entry" pos="3" rst="0">
          <comment>Set to 1 to force status of exchange table entry to be ready. Used  for repeated tx</comment>
        </bits>
        <bits access="rw" name="infinitetx" pos="2" rst="0">
          <comment>Applicable for all frame format
0: Normal mode of operation
1: Infinite Tx window</comment>
        </bits>
        <bits access="rw" name="prbstype" pos="1" rst="0">
          <comment>Defines the PRBS type in use
0: Tx Packet Payload are PRBS9 type
1: Tx Packet Payload are PRBS15 type</comment>
        </bits>
        <bits access="rw" name="txpldsrc" pos="0" rst="0">
          <comment>Applicable for all frame format
0: Tx Packet Payload source is the Control Structure
1: Tx Packet Payload are PRBS generator</comment>
        </bits>
      </reg>
      <reg name="rftestfreq" protect="rw">
        <bits access="rw" name="directlopbacken" pos="17" rst="0">
          <comment>Direct Loopback Test Mode enable control
0: Normal mode of operation
1: Direct Loopback Mode enabled (Received Packet Header, Payload Header, and Payload data directly re-transmitted in the next slot)</comment>
        </bits>
        <bits access="rw" name="testmodeen" pos="16" rst="0">
          <comment>Test Mode enable control, applicable if CS-FH_EN=0
0: Normal mode of operation
1: Test Mode enable, use &lt;TX/RX&gt;FREQ during Tx/Rx operations.</comment>
        </bits>
        <bits access="rw" name="rxfreq" pos="14:8" rst="0">
          <comment>Frequency Table index to be used during Rx operation</comment>
        </bits>
        <bits access="rw" name="txfreq" pos="6:0" rst="0">
          <comment>Frequency Table index to be used during Tx operation</comment>
        </bits>
      </reg>
      <hole size="64"/>
      <reg name="timgencntl" protect="rw">
        <bits access="rw" name="apfm_en" pos="31" rst="1">
          <comment>Controls the Anticipated pre-Fetch Abort mechanism
0: Disabled
1: Enabled</comment>
        </bits>
        <bits access="rw" name="prefetchabort_time" pos="25:16" rst="479">
          <comment>Defines the instant in s at which immediate abort is required after anticipated pre-fetch abort</comment>
        </bits>
        <bits access="rw" name="prefetch_time" pos="8:0" rst="189">
          <comment>Defines Exchange Table pre-fetch instant in s</comment>
        </bits>
      </reg>
      <reg name="grosstimtgt" protect="rw">
        <bits access="rw" name="grosstarget" pos="22:0" rst="0">
          <comment>Gross Timer Target value on which an Interrupt must be generated.
This timer has a precision of 10ms: interrupt is generated only when GROSSTARGET = CLKN[27:5] and CLKN[4:0] = 0.</comment>
        </bits>
      </reg>
      <reg name="finetimtgt" protect="rw">
        <bits access="rw" name="finetarget" pos="26:0" rst="0">
          <comment>Fine Timer Target value on which an interrupt must be generated.
This timer has a precision of 625s: interrupt is generated only when FINETARGET = CLKN[27:1]</comment>
        </bits>
      </reg>
      <reg name="sketclkn" protect="r">
        <bits access="r" name="sketclkn" pos="27:0" rst="0">
          <comment>Returns the CLKN[27:0] value on each bt_sket_irq generation.</comment>
        </bits>
      </reg>
      <reg name="pcacntl0" protect="rw">
        <bits access="rw" name="target_offset" pos="26:16" rst="0">
          <comment>Signed  number,  time  offset  to  the  current  frame_sync  position  in  s.  Valid  range  is  [-625, 625]s. When SYNC_SOURCE=1, the following formula must apply:
TARGET_OFFSET = 559 C RF round trip delay C desired CS-BITOFF</comment>
        </bits>
        <bits access="rw" name="slvlbl" pos="12:8" rst="0">
          <comment>Applies only when SYNC_SOURCE equals 1. Defines which connection to align piconet clock on.
The  connection  is  labelled  using  CS-LINKLBL  the  piconet  clock  is  aligned  when  CS-LINKLBL  = SLVLBL field
Note  the  RW-BT  Software  must  ensure  the  labelled  connection  is  a  slave  connection,  else  it cannot work properly</comment>
        </bits>
        <bits access="rw" name="corr_step" pos="7:4" rst="1">
          <comment>Maximum shift size during incremental phase shift. Must be programmed to 1s (0x1)
Note  CORR_STEP  is  considered  as  a  signed  value  when  BLINDCORR_EN  is  set  (allows  to  drift forward and backward)</comment>
        </bits>
        <bits access="rw" name="blindcorr_en" pos="3" rst="0">
          <comment>0: Align piconet clock on frame_sync rising edge (when CORR_INTERVAL is reached)
1: Align piconet clock when CORR_INTERVAL is reached, without frame_sync rising edge</comment>
        </bits>
        <bits access="rw" name="frsync_pol" pos="2" rst="0">
          <comment>Frame sync signal polarity.
  0 : rising edge events sensitive
  1 : falling edge events sensitive</comment>
        </bits>
        <bits access="rw" name="sync_source" pos="1" rst="0">
          <comment>Defines synchronization signal source
0: MWS frame synchronization
1: Scatternet network scheduling optimization (See section 2.17)</comment>
        </bits>
        <bits access="rw" name="phase_shift_en" pos="0" rst="0">
          <comment>Enable incremental phase shift</comment>
        </bits>
      </reg>
      <reg name="pcacntl1" protect="rw">
        <bits access="rw" name="corr_interval" pos="23:16" rst="40">
          <comment>Correction interval time in slot interval.
Default value is 40 (i.e. 40x625s = 25ms)</comment>
        </bits>
        <bits access="w" name="clock_shift_en" pos="12" rst="0">
          <comment>Performs immediate clock shift update using CLOCK_SHIFT[10:0], when written with a 1.
Resets at 0 when action is performed. No action happens if it is written with 0.</comment>
        </bits>
        <bits access="rw" name="clock_shift" pos="10:0" rst="0">
          <comment>Signed value of the clock shift to apply when CLOCK_SHIFT_EN is written with a 1 in [-625, 625]s range</comment>
        </bits>
      </reg>
      <reg name="pcastat" protect="r">
        <bits access="r" name="shift_phase" pos="26:16" rst="0">
          <comment>Indicate  the  value  of  the  phase  when  an  immediate  shift  has  been  programmed  or  when  a frame_sync event occurs, [-625, 625]s</comment>
        </bits>
        <bits access="r" name="moment_offset" pos="10:0" rst="0">
          <comment>Momentary  offset,  signed  number  which  indicate  the  time  between  target_offset  and  the nearest alignment point, in [-625, 625]s range</comment>
        </bits>
      </reg>
      <hole size="928"/>
      <reg name="escochancntl0" protect="rw">
        <bits access="r" name="tog0" pos="31" rst="0">
          <comment>Toggle command for Voice Channel 0.
Driven by TeSCO/TSCO toggling instant. Used to perform selection of PCM pointers and Tx/Rx Descriptor
Please refer to section 2.18.5 for details.</comment>
        </bits>
        <bits access="rw" name="escochanswen0" pos="15" rst="0">
          <comment>Enables  eSCO  Channel  0  SW  Transport  (Enable  Audio  data  to  be  routed  directly  to  EM  (or  through AES-CCM if encrypted link), used by Voice Transparent Modes:
0: Disabled.
1: Enabled.</comment>
        </bits>
        <bits access="rw" name="escochanen0" pos="14" rst="0">
          <comment>Enables eSCO Channel 0 (controls Audio Path EM Access controller voice channel 0):
0: Disabled.
1: Enabled.</comment>
        </bits>
        <bits access="rw" name="itmode0" pos="13" rst="0">
          <comment>0: bt_audio0_irq is generated on TeSCO/TSCO instant
1: bt_audio0_irq is generated INTDELAY0[5:0] slots after TeSCO/TSCO instant</comment>
        </bits>
        <bits access="rw" name="intdelay0" pos="12:8" rst="0">
          <comment>Valid if ITMODE0 = 1
Determines the slot number to wait before generating bt_audio0_irq</comment>
        </bits>
        <bits access="rw" name="tesco0" pos="7:0" rst="0">
          <comment>eSCO interval (in slots).
Support  a  [2:16]  range  in  slots  so  as  to  support  both  SCO  and  eSCO  mandatory  LMP  parameters range (see [1])</comment>
        </bits>
      </reg>
      <reg name="escomutecntl0" protect="rw">
        <bits access="rw" name="mute_sink0" pos="23" rst="0">
          <comment>HW mute control:
0: Do not mute on bad reception of an (e)SCO packet.
1: Mute after data or bad reception, with the pattern stored in MUTEPATT0
Note: See Table 2-34 for mute pattern value to apply</comment>
        </bits>
        <bits access="rw" name="mute_source0" pos="22" rst="0">
          <comment>HW mute control:
0: Provides Source buffer to the Packet Controller for Tx operations
1: Forces POLL/NULL to be sent as a replacement of Audio Packets</comment>
        </bits>
        <bits access="rw" name="invl0_1" pos="19:18" rst="2">
          <comment>SW mute status for Audio buffer 1 (i.e updated when TOG0=1):
Mute if not null. Please refer to Table 2-35 for details</comment>
        </bits>
        <bits access="rw" name="invl0_0" pos="17:16" rst="2">
          <comment>SW mute status for Audio buffer 0 (i.e updated when TOG0=0):
Mute if not null. Please refer to Table 2-35 for details</comment>
        </bits>
        <bits access="rw" name="mutepatt0" pos="15:0" rst="0">
          <comment>Value of the null pattern used when HW muting is enabled.</comment>
        </bits>
      </reg>
      <reg name="escocurrenttxptr0" protect="rw">
        <bits access="rw" name="esco0ptrtx1" pos="31:16" rst="0">
          <comment>Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 0.
Used when eSCOCHANCNTL0-TOG0 = 1</comment>
        </bits>
        <bits access="rw" name="esco0ptrtx0" pos="15:0" rst="0">
          <comment>Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 0.
Used when eSCOCHANCNTL0-TOG0 = 0</comment>
        </bits>
      </reg>
      <reg name="escocurrentrxptr0" protect="rw">
        <bits access="rw" name="esco0ptrrx1" pos="31:16" rst="0">
          <comment>Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 0.
Used when eSCOCHANCNTL0-TOG0 = 1</comment>
        </bits>
        <bits access="rw" name="esco0ptrrx0" pos="15:0" rst="0">
          <comment>Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 0.
Used when eSCOCHANCNTL0-TOG0 = 0</comment>
        </bits>
      </reg>
      <reg name="escoltcntl0" protect="rw">
        <bits access="rw" name="retxnb0" pos="23:16" rst="1">
          <comment>Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots).
Default value is 1</comment>
        </bits>
        <bits access="rw" name="escoedrrx0" pos="5" rst="0">
          <comment>1: eSCO EDR Mode (2/3 Mbps) in reception
0: eSCO 1Mbps in reception</comment>
        </bits>
        <bits access="rw" name="escoedrtx0" pos="4" rst="0">
          <comment>1: eSCO EDR Mode (2/3 Mbps) in transmission
0: eSCO 1Mbps in transmission</comment>
        </bits>
        <bits access="rw" name="syntype0" pos="3" rst="0">
          <comment>Synchronous packet type:
0: SCO packet
1: eSCO packet</comment>
        </bits>
        <bits access="rw" name="synltaddr0" pos="2:0" rst="0">
          <comment>LT_ADDR of the Synchronous link (eSCO), used for TX.</comment>
        </bits>
      </reg>
      <reg name="escotrcntl0" protect="rw">
        <bits access="rw" name="txseqn0" pos="31" rst="0">
          <comment>Value of the SEQN bit in eSCO TX packets. Used as follows:
-      Initialized by SW during eSCO link establishment
-      Toggled by HW on each TSCO/TeSCO, written back afterwards</comment>
        </bits>
        <bits access="rw" name="txlen0" pos="29:20" rst="0">
          <comment>Negotiated, maximum number of bytes for eSCO Tx payloads.</comment>
        </bits>
        <bits access="rw" name="txtype0" pos="19:16" rst="0">
          <comment>Negotiated Tx packet type, as defined in [1].</comment>
        </bits>
        <bits access="rw" name="rxlen0" pos="13:4" rst="0">
          <comment>Negotiated,  maximum  number  of  bytes  for  eSCO  Rx  payloads.  The  reception  of  the  payload  is automatically aborted if this buffer size is exceeded.</comment>
        </bits>
        <bits access="rw" name="rxtype0" pos="3:0" rst="0">
          <comment>Negotiated Rx packet type, as defined in [1].</comment>
        </bits>
      </reg>
      <reg name="escodaycnt0" protect="rw">
        <bits access="rw" name="daycounter0" pos="10:0" rst="0">
          <comment>Day Counter for AES-CCM nonce.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="escochancntl1" protect="rw">
        <bits access="r" name="tog1" pos="31" rst="0">
          <comment>Toggle command for Voice Channel 1.
Driven  by  TeSCO/TSCO  toggling  instant.  Used  to  perform  selection  of  PCM  pointers  and  Tx/Rx Descriptor.
Please refer to section 2.18.5 for details.</comment>
        </bits>
        <bits access="rw" name="escochanswen1" pos="15" rst="0">
          <comment>Enables  eSCO  Channel  1  SW  Transport  (Enable  Audio  data  to  be  routed  directly  to  EM  (or  through AES-CCM if encrypted link), used by Voice Transparent Modes:
0: Disabled.
1: Enabled.</comment>
        </bits>
        <bits access="rw" name="escochanen1" pos="14" rst="0">
          <comment>Enables eSCO Channel 1 (controls Audio Path EM Access controller voice channel 1):
0: Disabled.
1: Enabled.</comment>
        </bits>
        <bits access="rw" name="itmode1" pos="13" rst="0">
          <comment>0: bt_audio1_irq is generated on TeSCO/TSCO instant
1: bt_audio1_irq is generated INTDELAY1[5:0] slots after TeSCO/TSCO instant</comment>
        </bits>
        <bits access="rw" name="intdelay1" pos="12:8" rst="0">
          <comment>Valid if ITMODE1 = 1
Determines the slot number to wait before generating bt_audio1_irq</comment>
        </bits>
        <bits access="rw" name="tesco1" pos="7:0" rst="0">
          <comment>eSCO interval (in slots).
Support  a  [2:16]  range  in  slots  so  as  to  support  both  SCO  and  eSCO  mandatory  LMP  parameters range (see [1])</comment>
        </bits>
      </reg>
      <reg name="escomutecntl1" protect="rw">
        <bits access="rw" name="mute_sink1" pos="23" rst="0">
          <comment>HW mute control:
0: Do not mute on bad reception of an (e)SCO packet.
1: Mute after data or bad reception, with the pattern stored in MUTEPATT1
Note: See Table 2-34 for mute pattern value to apply</comment>
        </bits>
        <bits access="rw" name="mute_source1" pos="22" rst="0">
          <comment>HW mute control:
0: Provides Source buffer to the Packet Controller for Tx operations
1: Forces POLL/NULL to be sent as a replacement of Audio Packets</comment>
        </bits>
        <bits access="rw" name="invl1_1" pos="19:18" rst="2">
          <comment>SW mute status for Audio buffer 1 (i.e updated when TOG1=1):
Mute if not null. Please refer to Table 2-35 for details</comment>
        </bits>
        <bits access="rw" name="invl1_0" pos="17:16" rst="2">
          <comment>SW mute status for Audio buffer 0 (i.e updated when TOG1=0):
Mute if not null. Please refer to Table 2-35 for details</comment>
        </bits>
        <bits access="rw" name="mutepatt1" pos="15:0" rst="0">
          <comment>Value of the null pattern used when HW muting is enabled.</comment>
        </bits>
      </reg>
      <reg name="escocurrenttxptr1" protect="rw">
        <bits access="rw" name="esco1ptrtx1" pos="31:16" rst="0">
          <comment>Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 1.
Used when eSCOCHANCNTL1-TOG1 = 1</comment>
        </bits>
        <bits access="rw" name="esco1ptrtx0" pos="15:0" rst="0">
          <comment>Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 1.
Used when eSCOCHANCNTL1-TOG1 = 0</comment>
        </bits>
      </reg>
      <reg name="escocurrentrxptr1" protect="rw">
        <bits access="rw" name="esco1ptrrx1" pos="31:16" rst="0">
          <comment>Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 1.
Used when eSCOCHANCNTL1-TOG1 = 1</comment>
        </bits>
        <bits access="rw" name="esco1ptrrx0" pos="15:0" rst="0">
          <comment>Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 1.
Used when eSCOCHANCNTL1-TOG1 = 0</comment>
        </bits>
      </reg>
      <reg name="escoltcntl1" protect="rw">
        <bits access="rw" name="retxnb1" pos="23:16" rst="1">
          <comment>Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots).
Default value is 1</comment>
        </bits>
        <bits access="rw" name="escoedrrx1" pos="5" rst="0">
          <comment>1: eSCO EDR Mode (2/3 Mbps) in reception
0: eSCO 1Mbps in reception</comment>
        </bits>
        <bits access="rw" name="escoedrtx1" pos="4" rst="0">
          <comment>1: eSCO EDR Mode (2/3 Mbps) in transmission
0: eSCO 1Mbps in transmission</comment>
        </bits>
        <bits access="rw" name="syntype1" pos="3" rst="0">
          <comment>Synchronous packet type:
0: SCO packet
1: eSCO packet</comment>
        </bits>
        <bits access="rw" name="syntaddr1" pos="2:0" rst="0">
          <comment>LT_ADDR of the Synchronous link (eSCO), used for TX.</comment>
        </bits>
      </reg>
      <reg name="escotrcntl1" protect="rw">
        <bits access="rw" name="txseqn1" pos="31" rst="0">
          <comment>Value of the SEQN bit in eSCO TX packets. Used as follows:
-      Initialized by SW during eSCO link establishment
-      Toggled by HW each TSCO/TeSCO, written back afterwards</comment>
        </bits>
        <bits access="rw" name="txlen1" pos="29:20" rst="0">
          <comment>Negotiated, maximum number of bytes for eSCO Tx payloads.</comment>
        </bits>
        <bits access="rw" name="txtype1" pos="19:16" rst="0">
          <comment>Negotiated Tx packet type, as defined in [1].</comment>
        </bits>
        <bits access="rw" name="rxlen1" pos="13:4" rst="0">
          <comment>Negotiated,  maximum  number  of  bytes  for  eSCO  Rx  payloads.  The  reception  of  the  payload  is automatically aborted if this buffer size is exceeded.</comment>
        </bits>
        <bits access="rw" name="rxtype1" pos="3:0" rst="0">
          <comment>Negotiated Rx packet type, as defined in [1].</comment>
        </bits>
      </reg>
      <reg name="escodaycnt1" protect="rw">
        <bits access="rw" name="daycounter1" pos="10:0" rst="0">
          <comment>Day Counter for AES-CCM nonce.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="escochancntl2" protect="rw">
        <bits access="r" name="tog2" pos="31" rst="0">
          <comment>Toggle command for Voice Channel 2.
Driven by TeSCO/TSCO toggling instant. Used to perform selection of PCM pointers and Tx/Rx Descriptor
Please refer to section 2.18.5 for details.</comment>
        </bits>
        <bits access="rw" name="escochanswen2" pos="15" rst="0">
          <comment>Enables  eSCO  Channel  2  SW  Transport  (Enable  Audio  data  to  be  routed  directly  to  EM  (or  through AES-CCM if encrypted link), used by Voice Transparent Modes:
0: Disabled.
1: Enabled.</comment>
        </bits>
        <bits access="rw" name="escochanen2" pos="14" rst="0">
          <comment>Enables eSCO Channel 2 (controls Audio Path EM Access controller voice channel 2):
0: Disabled.
1: Enabled.</comment>
        </bits>
        <bits access="rw" name="itmode2" pos="13" rst="0">
          <comment>0: bt_audio2_irq is generated on TeSCO/TSCO instant
1: bt_audio2_irq is generated INTDELAY1[5:0] slots after TeSCO/TSCO instant</comment>
        </bits>
        <bits access="rw" name="intdelay2" pos="12:8" rst="0">
          <comment>Valid if ITMODE2 = 1
Determines the slot number to wait before generating bt_audio2_irq</comment>
        </bits>
        <bits access="rw" name="tesco2" pos="7:0" rst="0">
          <comment>eSCO interval (in slots).
Support  a  [2:16]  range  in  slots  so  as  to  support  both  SCO  and  eSCO  mandatory  LMP  parameters range (see [1])</comment>
        </bits>
      </reg>
      <reg name="escomutecntl2" protect="rw">
        <bits access="rw" name="mute_sink2" pos="23" rst="0">
          <comment>HW mute control:
0: Do not mute on bad reception of an (e)SCO packet.
1: Mute after data or bad reception, with the pattern stored in MUTEPATT2
Note: See Table 2-34 for mute pattern value to apply</comment>
        </bits>
        <bits access="rw" name="mute_source2" pos="22" rst="0">
          <comment>HW mute control:
0: Provides Source buffer to the Packet Controller for Tx operations
1: Forces POLL/NULL to be sent as a replacement of Audio Packets</comment>
        </bits>
        <bits access="rw" name="invl2_1" pos="19:18" rst="2">
          <comment>SW mute status for Audio buffer 1 (i.e updated when TOG2=1):
Mute if not null. Please refer to Table 2-35 for details</comment>
        </bits>
        <bits access="rw" name="invl2_0" pos="17:16" rst="2">
          <comment>SW mute status for Audio buffer 0 (i.e updated when TOG2=0):
Mute if not null. Please refer to Table 2-35 for details</comment>
        </bits>
        <bits access="rw" name="mutepatt2" pos="15:0" rst="0">
          <comment>Value of the null pattern used when HW muting is enabled.</comment>
        </bits>
      </reg>
      <reg name="escocurrenttxptr2" protect="rw">
        <bits access="rw" name="esco2ptrtx1" pos="31:16" rst="0">
          <comment>Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 2.
Used when eSCOCHANCNTL2-TOG2 = 1</comment>
        </bits>
        <bits access="rw" name="esco2ptrtx0" pos="15:0" rst="0">
          <comment>Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 2.
Used when eSCOCHANCNTL2-TOG2 = 0</comment>
        </bits>
      </reg>
      <reg name="escocurrentrxptr2" protect="rw">
        <bits access="rw" name="esco2ptrrx1" pos="31:16" rst="0">
          <comment>Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 2.
Used when eSCOCHANCNTL2-TOG2 = 1</comment>
        </bits>
        <bits access="rw" name="esco2ptrrx0" pos="15:0" rst="0">
          <comment>Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 2.
Used when eSCOCHANCNTL2-TOG2 = 0</comment>
        </bits>
      </reg>
      <reg name="escoltcntl2" protect="rw">
        <bits access="rw" name="retxnb2" pos="23:16" rst="1">
          <comment>Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots).
Default value is 1</comment>
        </bits>
        <bits access="rw" name="escoedrrx2" pos="5" rst="0">
          <comment>1: eSCO EDR Mode (2/3 Mbps) in reception
0: eSCO 1Mbps in reception</comment>
        </bits>
        <bits access="rw" name="escoedrtx2" pos="4" rst="0">
          <comment>1: eSCO EDR Mode (2/3 Mbps) in transmission
0: eSCO 1Mbps in transmission</comment>
        </bits>
        <bits access="rw" name="syntype2" pos="3" rst="0">
          <comment>Synchronous packet type:
0: SCO packet
1: eSCO packet</comment>
        </bits>
        <bits access="rw" name="syntaddr2" pos="2:0" rst="0">
          <comment>LT_ADDR of the Synchronous link (eSCO), used for TX.</comment>
        </bits>
      </reg>
      <reg name="escotrcntl2" protect="rw">
        <bits access="rw" name="txseqn2" pos="31" rst="0">
          <comment>Value of the SEQN bit in eSCO TX packets. Used as follows:
-      Initialized by SW during eSCO link establishment
-      Toggled by HW each TSCO/TeSCO, written back afterwards</comment>
        </bits>
        <bits access="rw" name="txlen2" pos="29:20" rst="0">
          <comment>Negotiated, maximum number of bytes for eSCO Tx payloads.</comment>
        </bits>
        <bits access="rw" name="txtype2" pos="19:16" rst="0">
          <comment>Negotiated Tx packet type, as defined in [1].</comment>
        </bits>
        <bits access="rw" name="rxlen2" pos="13:4" rst="0">
          <comment>Negotiated,  maximum  number  of  bytes  for  eSCO  Rx  payloads.  The  reception  of  the  payload  is automatically aborted if this buffer size is exceeded.</comment>
        </bits>
        <bits access="rw" name="rxtype2" pos="3:0" rst="0">
          <comment>Negotiated Rx packet type, as defined in [1].</comment>
        </bits>
      </reg>
      <reg name="escodaycnt2" protect="rw">
        <bits access="rw" name="daycounter2" pos="10:0" rst="0">
          <comment>Day Counter for AES-CCM nonce.</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="audiocntl0" protect="rw">
        <bits access="rw" name="linear_format0" pos="21:20" rst="3">
          <comment>Sample Linear format for voice channel 0
00: 8-bit samples
01: 13-bit samples
10: 14-bit samples
11: 16-bit samples</comment>
        </bits>
        <bits access="rw" name="sample_type0" pos="17:16" rst="1">
          <comment>PCM / VoHCI Sample Type on Audio Path Channel 0
00: Signed 1s complement
01: Signed 2s complement
10: Signed magnitude
11: Unsigned</comment>
        </bits>
        <bits access="rw" name="aulawen0" pos="15" rst="0">
          <comment>a/-Law control for voice channel 0
1: Enables a/-Law transcoding
0: Disables a/-Law transcoding / bypass mode</comment>
        </bits>
        <bits access="rw" name="aulaw_code0" pos="11:8" rst="0">
          <comment>a/-Law configuration code for voice channel 0. (See Table 2-40)</comment>
        </bits>
        <bits access="rw" name="cvsden0" pos="7" rst="0">
          <comment>CVSD control for voice channel 0
1: Enables CVSD transcoding
0: Disables CVSD transcoding / bypass mode</comment>
        </bits>
        <bits access="rw" name="cvsd_bitorder0" pos="0" rst="0">
          <comment>Bit ordering at Byte interface for voice channel 0
0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder.
1:  MSB  First.  Compatible  to  BT  spec.  1.0B  (ref.  to  [1])  The  bits  are  sent  in  the  reverse  order (maintains backward compatibility).</comment>
        </bits>
      </reg>
      <reg name="audiocntl1" protect="rw">
        <bits access="rw" name="linear_format1" pos="21:20" rst="3">
          <comment>Sample Linear format for voice channel 1
00: 8-bit samples
01: 13-bit samples
10: 14-bit samples
11: 16-bit samples</comment>
        </bits>
        <bits access="rw" name="sample_type1" pos="17:16" rst="1">
          <comment>PCM / VoHCI Sample Type on Audio Path Channel 1
00: Signed 1s complement
01: Signed 2s complement
10: Signed magnitude
11: Unsigned</comment>
        </bits>
        <bits access="rw" name="aulawen1" pos="15" rst="0">
          <comment>a/-Law control for voice channel 1
1: Enables a/-Law transcoding
0: Disables a/-Law transcoding / bypass mode</comment>
        </bits>
        <bits access="rw" name="aulaw_code1" pos="11:8" rst="0">
          <comment>a/-Law configuration code for voice channel 1. (See Table 2-40)</comment>
        </bits>
        <bits access="rw" name="cvsden1" pos="7" rst="0">
          <comment>CVSD control for voice channel 1
1: Enables CVSD transcoding
0: Disables CVSD transcoding / bypass mode</comment>
        </bits>
        <bits access="rw" name="cvsd_bitorder1" pos="0" rst="0">
          <comment>Bit ordering at Byte interface for voice channel 1
0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder.
1:  MSB  First.  Compatible  to  BT  spec.  1.0B  (ref.  to  [1])  The  bits  are  sent  in  the  reverse  order (maintains backward compatibility).</comment>
        </bits>
      </reg>
      <reg name="audiocntl2" protect="rw">
        <bits access="rw" name="linear_format2" pos="21:20" rst="3">
          <comment>Sample Linear format for voice channel 2
00: 8-bit samples
01: 13-bit samples
10: 14-bit samples
11: 16-bit samples</comment>
        </bits>
        <bits access="rw" name="sample_type2" pos="17:16" rst="1">
          <comment>PCM / VoHCI Sample Format on Audio Path Channel 2
00: Signed 1s complement
01: Signed 2s complement
10: Signed magnitude
11: Unsigned</comment>
        </bits>
        <bits access="rw" name="aulawen2" pos="15" rst="0">
          <comment>a/-Law control for voice channel 2
1: Enables a/-Law transcoding
0: Disables a/-Law transcoding / bypass mode</comment>
        </bits>
        <bits access="rw" name="aulaw_code2" pos="11:8" rst="0">
          <comment>a/-Law configuration code for voice channel 2. (See Table 2-40)</comment>
        </bits>
        <bits access="rw" name="cvsden2" pos="7" rst="0">
          <comment>CVSD control for voice channel 2
1: Enables CVSD transcoding
0: Disables CVSD transcoding / bypass mode</comment>
        </bits>
        <bits access="rw" name="cvsd_bitorder2" pos="0" rst="0">
          <comment>Bit ordering at Byte interface for voice channel 2
0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder.
1:  MSB  First.  Compatible  to  BT  spec.  1.0B  (ref.  to  [1])  The  bits  are  sent  in  the  reverse  order (maintains backward compatibility).</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="pcmgencntl" protect="rw">
        <bits access="rw" name="vxchsel" pos="9:8" rst="0">
          <comment>Voice channel Selection. Select the voice channel to be routed to the PCM
00: Voice Channel 0 routed to PCM
01: Voice Channel 1 routed to PCM
10: Voice Channel 2 routed to PCM
11: Reserved</comment>
        </bits>
        <bits access="rw" name="loopback" pos="6" rst="0">
          <comment>Loopback Test mode control
1: Loopback Mode enabled
0: Loopback Mode disabled / Normal operations</comment>
        </bits>
        <bits access="rw" name="mono_lr_sel" pos="5" rst="0">
          <comment>Valid when SAMPTYPE is set to Stereo mode, else not applicable
0: Select Left channel audio samples for Mono operation
1: Select Right channel audio samples for Mono operation</comment>
        </bits>
        <bits access="rw" name="mono_stereo" pos="4" rst="0">
          <comment>Audio channel Mono/Stereo mode control
0: Audio channel carries Mono samples
1: Audio channel carries Stereo samples</comment>
        </bits>
        <bits access="rw" name="mstslv" pos="3" rst="0">
          <comment>Master/Slave mode control
0: PCM is master (i.e. PCM generates pcmclk_out and pcmfsync_out from PLL)
1: PCM is slave (i.e. PLL disabled and pcmclk_in and pcmfsync_in are used)</comment>
        </bits>
        <bits access="rw" name="byteswap" pos="2" rst="0">
          <comment>Byte swapping control, valid only SAMPSZ is set to 16-bits
0: Samples to be sent used as-is
1: MSB and LSB bytes are swapped within samples</comment>
        </bits>
        <bits access="rw" name="lrswap" pos="1" rst="0">
          <comment>Valid in Stereo mode only, defines the Left / Right channel order
0: Left channel then Right channel
1: Right channel then Left channel</comment>
        </bits>
        <bits access="rw" name="pcmen" pos="0" rst="0">
          <comment>PCM main control
0: PCM disabled (i.e. pcm_gclk clock not enabled)
1: PCM enabled (i.e. pcm_gclk clock enabled)</comment>
        </bits>
      </reg>
      <reg name="pcmphyscntl0" protect="rw">
        <bits access="rw" name="firstactslot" pos="21:20" rst="0">
          <comment>Configures the first active slot of the frame, in [0:3] range
00: first active slot is slot 0
01: first active slot is slot 1
10: first active slot is slot 2
11: first active slot is slot 3
The maximum value this field can be configured to is determined by the SLOTNB-1 parameters.</comment>
        </bits>
        <bits access="rw" name="slotnb" pos="18:16" rst="0">
          <comment>Number of slots within a PCM frame
Valid values are in [1:4] range.
Other values are meaningless</comment>
        </bits>
        <bits access="rw" name="samptype" pos="13" rst="0">
          <comment>PCM Codec Sample type
0: PCM codec supports Mono operation
1: PCM codec supports Stereo operation</comment>
        </bits>
        <bits access="rw" name="sampsz" pos="12" rst="0">
          <comment>PCM codec Sample size
0: PCM Frame carries 8-bit samples
1: PCM Frame carries 16-bit samples</comment>
        </bits>
        <bits access="rw" name="lsb1st" pos="10" rst="0">
          <comment>Bit ordering within a PCM Frame
0: Sample are sent/received MSB first
1: Samples are sent/received LSB first</comment>
        </bits>
        <bits access="rw" name="pcm_iom" pos="9" rst="0">
          <comment>PCM / IOM mode selection
0: PCM mode (single clocking)
1: IOM mode (double clocking)</comment>
        </bits>
        <bits access="rw" name="lrchpol" pos="8" rst="0">
          <comment>Selection  of  the  PCM  Frame  Synchronization  polarity  (Valid  when  SAMPTYPE  is  set  to  Stereo mode, else not applicable)
0: Right channel when = 0, Left channel when = 1
1: Right channel when = 1, Left channel when = 0</comment>
        </bits>
        <bits access="rw" name="doutcfg" pos="5:4" rst="0">
          <comment>Physical configuration of the pcmd_out pad.
00: Open-drain, hi-Z outside transmission
01: Push-pull, hi-Z outside transmission
10: Push-pull, driven to 0 outside transmission
11: Reserved</comment>
        </bits>
        <bits access="rw" name="fsyncshp" pos="2:0" rst="0">
          <comment>Physical shape of the PCM Frame Synchronization signal.
000: LF enclosing the last falling PCM Interface Clock edge in frame (Mono only)
001: FR enclosing the first rising PCM Interface Clock edge in frame (Mono only)
010: FF enclosing the first falling PCM Interface Clock edge in frame (Mono only)
011: LONG enclosing the first slot (8 bits) of the frame (Mono / Stereo 8-bits only)
100: LONG_16 enclosing first two slots (16 bits) of the frame (Mono 16 bits / Stereo 16-bits only)
101:  STEREO  Left/Right  Frame  differentiating  (Stereo  only,  covers  left  or  right  channel  only, polarity is set according to LRCHPOL)</comment>
        </bits>
      </reg>
      <reg name="pcmphyscntl1" protect="rw">
        <bits access="rw" name="clkinv" pos="31" rst="0">
          <comment>Selection of the PCM Interface Clock polarity
0: Data is clocked out with the rising edge (standard)
1: Data is clocked out with the falling edge</comment>
        </bits>
        <bits access="rw" name="pcmclklimit" pos="23:16" rst="0">
          <comment>PCM Clock counter limit</comment>
        </bits>
        <bits access="rw" name="pcmclkval" pos="8:0" rst="0">
          <comment>PCM Clock Counter value.</comment>
        </bits>
      </reg>
      <reg name="pcmpadding" protect="rw">
        <bits access="rw" name="rsamppad" pos="31:16" rst="0">
          <comment>Right channel sample padding / to be used when non 16-bits PCM sample configuration is used. (LSB are used first)</comment>
        </bits>
        <bits access="rw" name="lsamppad" pos="15:0" rst="0">
          <comment>Left channel sample padding / to be used when non 16-bits PCM sample configuration is used. (LSB are used first)</comment>
        </bits>
      </reg>
      <reg name="pcmpllcntl0" protect="rw">
        <bits access="rw" name="rl" pos="19:0" rst="0">
          <comment>PLL control word, see equation below.</comment>
        </bits>
      </reg>
      <reg name="pcmpllcntl1" protect="rw">
        <bits access="rw" name="olc" pos="30:20" rst="0">
          <comment>Open Loop Correction value, see equation below.</comment>
        </bits>
        <bits access="rw" name="a" pos="18:0" rst="0">
          <comment>PLL control word, see equation below.</comment>
        </bits>
      </reg>
      <reg name="pcmpllcntl2" protect="rw">
        <bits access="rw" name="w" pos="18:0" rst="0">
          <comment>PLL control word, see equation below.</comment>
        </bits>
      </reg>
      <reg name="pcmsourceptr" protect="rw">
        <bits access="rw" name="pcmsourceptr1" pos="31:16" rst="0">
          <comment>PCM Source Pointer 1 / Air to PCM direction</comment>
        </bits>
        <bits access="rw" name="pcmsourceptr0" pos="15:0" rst="0">
          <comment>PCM Source Pointer 0 / Air to PCM direction</comment>
        </bits>
      </reg>
      <reg name="pcmsinkptr" protect="rw">
        <bits access="rw" name="pcmsinkptr1" pos="31:16" rst="0">
          <comment>PCM Sink Pointer 1 / PCM to Air direction</comment>
        </bits>
        <bits access="rw" name="pcmsinkptr0" pos="15:0" rst="0">
          <comment>PCM Sink Pointer 0 / PCM to Air direction</comment>
        </bits>
      </reg>
      <hole size="96"/>
      <reg name="bredrprioscharb" protect="rw">
        <bits access="rw" name="bredrpriomode" pos="15" rst="0">
          <comment>Determine BR/EDR Priority Scheduling Arbitration Mode
0: BR/EDR Decision instant not used
1: BR/EDR Decision instant used</comment>
        </bits>
        <bits access="rw" name="bredrmargin" pos="7:0" rst="0">
          <comment>Determine the decision instant margin for Priority Scheduling Arbitration. Decision instant is defined as per formula of section 3.6</comment>
        </bits>
      </reg>
      <reg name="plcaddr01" protect="rw">
        <bits access="rw" name="plcbaseaddr1" pos="31:16" rst="0">
          <comment>PLC Pool Base Addr</comment>
        </bits>
        <bits access="rw" name="plcbaseaddr0" pos="15:0" rst="0">
          <comment>PLC Pool Base Addr</comment>
        </bits>
      </reg>
      <reg name="plcaddr23" protect="rw">
        <bits access="rw" name="plcbaseaddr3" pos="31:16" rst="0">
          <comment>PLC Pool Base Addr</comment>
        </bits>
        <bits access="rw" name="plcbaseaddr2" pos="15:0" rst="0">
          <comment>PLC Pool Base Addr</comment>
        </bits>
      </reg>
      <reg name="plcaddr45" protect="rw">
        <bits access="rw" name="plcbaseaddr5" pos="31:16" rst="0">
          <comment>PLC Pool Base Addr</comment>
        </bits>
        <bits access="rw" name="plcbaseaddr4" pos="15:0" rst="0">
          <comment>PLC Pool Base Addr</comment>
        </bits>
      </reg>
      <reg name="plcaddr67" protect="rw">
        <bits access="rw" name="plcbaseaddr7" pos="31:16" rst="0">
          <comment>PLC Pool Base Addr</comment>
        </bits>
        <bits access="rw" name="plcbaseaddr6" pos="15:0" rst="0">
          <comment>PLC Pool Base Addr</comment>
        </bits>
      </reg>
      <reg name="plcaddr89" protect="rw">
        <bits access="rw" name="plcbaseaddr9" pos="31:16" rst="0">
          <comment>PLC Pool Base Addr</comment>
        </bits>
        <bits access="rw" name="plcbaseaddr8" pos="15:0" rst="0">
          <comment>PLC Pool Base Addr</comment>
        </bits>
      </reg>
      <reg name="plcaddrb" protect="rw">
        <bits access="rw" name="plcbufaddr" pos="15:0" rst="0">
          <comment>PLC Pool buf Addr</comment>
        </bits>
      </reg>
      <reg name="plcconf" protect="rw">
        <bits access="s" name="plc_int_clr" pos="31" rst="0">
          <comment>bit type is changed from wos to s.
          plc interrput clear pulse</comment>
        </bits>
        <bits access="r" name="plc_int" pos="30" rst="0">
          <comment>plc interrput</comment>
        </bits>
        <bits access="r" name="plc_fsm_state" pos="29:26" rst="0">
          <comment>plc ctrl fsm state</comment>
        </bits>
        <bits access="s" name="conf_plc_start" pos="25" rst="0">
          <comment>bit type is changed from wos to s.
          plc_start</comment>
        </bits>
        <bits access="rw" name="conf_plc_ctrl_sw" pos="24" rst="0">
          <comment>0: hardware auto 1: software ctrl</comment>
        </bits>
        <bits access="rw" name="conf_plc_int_mask" pos="23" rst="0">
          <comment>mask for plc interrupt</comment>
        </bits>
        <bits access="rw" name="conf_diag0_sel" pos="22:21" rst="0">
          <comment>diag0 selection</comment>
        </bits>
        <bits access="rw" name="conf_scaling_mode" pos="20" rst="1">
          <comment>plc scaling mode</comment>
        </bits>
        <bits access="rw" name="conf_frame_mode" pos="19:18" rst="0">
          <comment>frame_mode length_x000D_
0: 120_x000D_  1: 90 2:60_x000D_ 3:30</comment>
        </bits>
        <bits access="rw" name="conf_plc_type" pos="17" rst="0">
          <comment>indicate current farme bad or good</comment>
        </bits>
        <bits access="rw" name="conf_plc_en" pos="16" rst="0">
          <comment>enable for PLC</comment>
        </bits>
        <bits access="rw" name="conf_plc_except" pos="15" rst="0">
          <comment>plc exception</comment>
        </bits>
        <bits access="rw" name="conf_pool_mem_word_swap" pos="14" rst="1">
          <comment>swap word order</comment>
        </bits>
        <bits access="rw" name="conf_no_pitch_find_ref_threshold_dist" pos="13:0" rst="11">
          <comment>threshold for finding pitch</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_bt_modem.xml">
    <module category="wcn" name="WCN_BT_MODEM">
      <reg name="bypass_ctrl" protect="rw">
        <bits access="rw" name="bypass_dccancel" pos="15" rst="0">
          <comment>Bypass DC Cancel
1'h0:: not_bypass: RX DC Cancel is not bypassed
1'h1:: bypass: RX DC Cancel is bypassed</comment>
        </bits>
        <bits access="rw" name="bypass_dccancel2" pos="14" rst="1">
          <comment>RESERVED</comment>
        </bits>
        <bits access="rw" name="bypass_mixer" pos="13" rst="0">
          <comment>Bypass Mixer
1'h0:: not_bypass: RX Mixer is not bypassed
1'h1:: bypass: RX Mixer is bypassed</comment>
        </bits>
        <bits access="rw" name="bypass_srrc" pos="12" rst="0">
          <comment>Bypass Square-root-raised-cosine Filter
1'h0:: not_bypass: RX SRRC filter is not bypassed
1'h1:: bypass: RX SRRC filter is bypassed</comment>
        </bits>
        <bits access="rw" name="bypass_derr1_gfsk" pos="8" rst="0">
          <comment>Bypass GFSK Derr1
1'h0:: not_bypass: RX GFSK Derr1 is not bypassed
1'h1:: bypass: RX GFSK Derr1 is bypassed</comment>
        </bits>
        <bits access="rw" name="bypass_derr2_gfsk" pos="7" rst="0">
          <comment>Bypass GFSK Derr2
1'h0:: not_bypass: RX GFSK Derr2 is not bypassed
1'h1:: bypass: RX GFSK Derr2 is bypassed</comment>
        </bits>
        <bits access="rw" name="bypass_patch_gfsk" pos="6" rst="0">
          <comment>Bypass GFSK Patch
1'h0:: not_bypass: GFSK Patch is not bypassed
1'h1:: bypass: GFSK Patch is bypassed</comment>
        </bits>
        <bits access="rw" name="bypass_smppt_gfsk" pos="5" rst="0">
          <comment>Bypass GFSK Sample Step
1'h0:: not_bypass: RX GFSK Sample Step is 1
1'h1:: bypass: RX GFSK Sample Step is 0</comment>
        </bits>
        <bits access="rw" name="bypass_derr1_dpsk" pos="4" rst="0">
          <comment>Bypass DPSK Derr1
1'h0:: not_bypass: RX DPSK Derr1 is not bypassed
1'h1:: bypass: RX DPSK Derr1 is bypassed</comment>
        </bits>
        <bits access="rw" name="bypass_derr2_dpsk" pos="3" rst="0">
          <comment>Bypass DPSK Derr2
1'h0:: not_bypass: RX DPSK Derr2 is not bypassed
1'h1:: bypass: RX DPSK Derr2 is bypassed</comment>
        </bits>
        <bits access="rw" name="bypass_patch_dpsk" pos="2" rst="0">
          <comment>Bypass DPSK Patch
1'h0:: not_bypass: DPSK Patch is not bypassed
1'h1:: bypass: DPSK Patch is bypassed</comment>
        </bits>
        <bits access="rw" name="bypass_smppt_dpsk" pos="1" rst="0">
          <comment>Bypass DPSK Sample Step
1'h0:: not_bypass: RX DPSK Sample Step is 1
1'h1:: bypass: RX DPSK Sample Step is 0</comment>
        </bits>
      </reg>
      <reg name="sw_swap_dccal" protect="rw">
        <bits access="rw" name="swch_clk_adc" pos="14" rst="0">
          <comment>Switch ADC Clock Edge
1'h0:: not_switch: ADC clock edge is not switched
1'h1:: switch: ADC clock edge is switched</comment>
        </bits>
        <bits access="rw" name="sel_sync" pos="13" rst="0">
          <comment>Select New Packet
1'h0:: from_LL: newpacket_dsp is from baseband
1'h1:: from_reg: newpacket_dsp is from newpacket_reg</comment>
        </bits>
        <bits access="rw" name="swch_clk_dac" pos="12" rst="1">
          <comment>Switch DAC Clock Edge
1'h0:: not_switch: DAC clock edge is not switched
1'h1:: switch: DAC clock edge is switched</comment>
        </bits>
        <bits access="rw" name="rsvd0" pos="11" rst="0">
          <comment>RESERVED</comment>
        </bits>
        <bits access="rw" name="lpf_dwidth_sel" pos="10:9" rst="1">
          <comment>LPF Data Width Select
2'h0:: shift_9bits
2'h1:: shift_8bits
2'h2:: shift_7bits
2'h3:: shift_6bits</comment>
        </bits>
        <bits access="rw" name="swch_sign_i_tx" pos="8" rst="0">
          <comment>Switch TX DAC datai sign
1'h0:: unsigned: TX DAC datai is unsigned; analog common format
1'h1:: signed: TX DAC datai is signed</comment>
        </bits>
        <bits access="rw" name="swch_sign_q_tx" pos="7" rst="0">
          <comment>Switch TX DAC dataq sign
1'h0:: unsigned: TX DAC dataq is unsigned; analog common format
1'h1:: signed: TX DAC dataq is signed</comment>
        </bits>
        <bits access="rw" name="swch_sign_rx" pos="6" rst="0">
          <comment>Switch RX ADC IQ data sign
1'h0:: unsigned: RX ADC data is unsigned; analog common format
1'h1:: signed: RX ADC data is signed</comment>
        </bits>
        <bits access="rw" name="iq_sel_pol" pos="5" rst="0">
          <comment>SRRC IQ_SEL Polarity
1'h0:: iq_sel_inv
1'h1:: iq_sel_raw</comment>
        </bits>
        <bits access="rw" name="sel_sumerr_range" pos="2:0" rst="3">
          <comment>Sum Error Range Control
3'h0 Left shift 3 bits of sum err and limit sumerr within [-2^-4, 2^-4]
3'h1 Left shift 2 bits of sum err and limit sumerr within [-2^-3, 2^-3]
3'h2 Left shift 1 bits of sum err and limit sumerr within [-2^-2, 2^-2]
3'h3 Hold the sum err
3'h4 Right shift 1 bits of sum err
3'h5 Right shift 2 bits of sum err
3'h6 Right shift 3 bits of sum err
3'h7 Right shift 4 bits of sum err;</comment>
        </bits>
      </reg>
      <reg name="dem750_afc_freq" protect="rw">
        <bits access="rw" name="afc_smtif" pos="15:0" rst="58075">
          <comment>Set the AFC frequency of dem750 of rx link
dec2hex(2^16-round(2*740/13e3*2^16))</comment>
        </bits>
      </reg>
      <reg name="dpsk_gfsk_tx_ctrl" protect="rw">
        <bits access="rw" name="tx_gain_dpsk" pos="15:8" rst="208">
          <comment>DPSK TX Gain in EDR</comment>
        </bits>
        <bits access="rw" name="delay_gfsk" pos="7:4" rst="4">
          <comment>Set the delay of input gfsk symbol, delay unit is 13MHz clock cycle.</comment>
        </bits>
        <bits access="rw" name="delay_dpsk" pos="3:0" rst="8">
          <comment>Set the delay of input dpsk symbol, delay unit is 13MHz clock cycle.</comment>
        </bits>
      </reg>
      <reg name="tx_gain_ctrl" protect="rw">
        <bits access="rw" name="cnt_guard_ini" pos="15:10" rst="40">
          <comment>Control the guard time length of bt frame
Guard time = (55-cnt_guard_ini)*T13Mclk</comment>
        </bits>
        <bits access="rw" name="tx_power_gain_sel" pos="9" rst="1">
          <comment>LL tx_power and debug tx_apc selection.
1'h1:: selected LL tx_power
1'h0::selected debug tx_apc</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_bypass" pos="8" rst="0">
          <comment>according to tx_power mapping digital gain.
1'h1:: bypass auto gain mapping function
1'h0:: no bypass</comment>
        </bits>
        <bits access="rw" name="tx_gain_gfsk" pos="7:0" rst="152">
          <comment>GFSK TX Gain in BR</comment>
        </bits>
      </reg>
      <reg name="rssi_out1" protect="r">
        <bits access="r" name="rssi_out_post" pos="25:16" rst="0">
          <comment>after SRRC RSSI Output</comment>
        </bits>
        <bits access="r" name="rssi_out_pre" pos="9:0" rst="0">
          <comment>after mixer before SRRC RSSI Output.</comment>
        </bits>
      </reg>
      <reg name="sw_ctrl" protect="rw">
        <bits access="rw" name="rssi_lock_by_agc_post" pos="16" rst="0">
          <comment>after SRRC RSSI Receiver Strength Signal Indicator lock by agc done signal</comment>
        </bits>
        <bits access="rw" name="rssi_lock_by_agc_pre" pos="15" rst="0">
          <comment>befor SRRC RSSI Receiver Strength Signal Indicator lock by agc done signal</comment>
        </bits>
        <bits access="rw" name="swap_iq" pos="14" rst="0">
          <comment>Swap I/Q
1'h0:: no_swap: I/Q is not swaped
1'h1:: swap: I/Q is swaped</comment>
        </bits>
        <bits access="rw" name="swap_iq_dccl_0" pos="13" rst="0">
          <comment>Swap I/Q of ddcl input data
1'h0:: no_swap: I/Q of ddcl input data is not swaped
1'h1:: swap: I/Q of ddcl input data is swaped</comment>
        </bits>
        <bits access="rw" name="swap_iq_smtif_0" pos="12" rst="0">
          <comment>RESERVED</comment>
        </bits>
        <bits access="rw" name="swap_iq_mixer_0" pos="11" rst="0">
          <comment>Swap I/Q of Mixer output data
1'h0:: no_swap: I/Q of mixer output data is not swaped
1'h1:: swap: I/Q of mixer output data is swaped</comment>
        </bits>
        <bits access="rw" name="swap_pn_i_dccl_0" pos="10" rst="0">
          <comment>Swap ddcl input I data polarity
1'h0:: no_swap: I data polarity of ddcl input is not swaped
1'h1:: swap: I data polarity of ddcl input is swaped</comment>
        </bits>
        <bits access="rw" name="swap_pn_q_dccl_0" pos="9" rst="0">
          <comment>Swap ddcl input Q data polarity
1'h0:: no_swap: Q data polarity of ddcl input is not swaped
1'h1:: swap: Q data polarity of ddcl input is swaped</comment>
        </bits>
        <bits access="rw" name="notch_disb" pos="8" rst="1">
          <comment>Disable the ramping for edr guard time in ramp_gain_tx</comment>
        </bits>
        <bits access="rw" name="tx_gain_gfsk_edr" pos="7:0" rst="112">
          <comment>GFSK TX Gain in EDR</comment>
        </bits>
      </reg>
      <reg name="adcclk_sw_ctrl" protect="rw">
        <bits access="rw" name="en_bbpkg_flg" pos="14" rst="1">
          <comment>BB Newpacket flag enable
1'h0:: Disable: the BB Newpacket flag enable
1'h1:: Enable: the BB Newpacket flag enable</comment>
        </bits>
        <bits access="rw" name="pckt_sel" pos="13" rst="0">
          <comment>Packet select
1'h0:: packet72
1'h1:: new_packet</comment>
        </bits>
        <bits access="rw" name="ct_u_gfsk" pos="12:9" rst="10">
          <comment>gfsk u_err 10/32</comment>
        </bits>
        <bits access="rw" name="ct_u_1_gfsk" pos="8:4" rst="28">
          <comment>gfsk u_dc 4/512</comment>
        </bits>
        <bits access="rw" name="ct_u_sp_gfsk" pos="3:0" rst="9">
          <comment>gfsk ct_u_sp for rx demod</comment>
        </bits>
      </reg>
      <reg name="dpsk_demod_sw" protect="rw">
        <bits access="rw" name="ct_u_patch" pos="15:13" rst="1">
          <comment>Switch err_in_patch for bt_dsp rx demod</comment>
        </bits>
        <bits access="rw" name="ct_u_dpsk" pos="12:9" rst="8">
          <comment>dpsk u_err 8/32</comment>
        </bits>
        <bits access="rw" name="ct_u_1_dpsk" pos="8:4" rst="5">
          <comment>dpsk u_dc 5/64</comment>
        </bits>
        <bits access="rw" name="ct_u_sp_dpsk" pos="3:0" rst="9">
          <comment>Switch dpsk ct_u for bt_dsp rx demod</comment>
        </bits>
      </reg>
      <reg name="min_phase_err" protect="rw">
        <bits access="rw" name="min_error_th" pos="15:0" rst="3318">
          <comment>Set the minimum phase error for  rx demod.</comment>
        </bits>
      </reg>
      <reg name="afc_ctrl" protect="rw">
        <bits access="rw" name="sel_afc_gfskdem" pos="15:14" rst="2">
          <comment>Select the GFSK AFC of demod</comment>
        </bits>
        <bits access="rw" name="sel_afc_dpskseek" pos="13:12" rst="2">
          <comment>Select the DPSK AFC of demod</comment>
        </bits>
        <bits access="rw" name="rsvd1" pos="11:10" rst="0">
          <comment>RESERVED</comment>
        </bits>
        <bits access="rw" name="th_gfsk_dem" pos="9:0" rst="41">
          <comment>GFSK demod threshold</comment>
        </bits>
      </reg>
      <reg name="dpsk_gfsk_smp_th" protect="rw">
        <bits access="rw" name="diff_enable_dpsk" pos="15" rst="0">
          <comment>DPSK diff enable
1'h0:: Disable
1'h1:: Enable</comment>
        </bits>
        <bits access="rw" name="diff_enable_gfsk" pos="14" rst="0">
          <comment>GFSK diff enable
1'h0:: Disable
1'h1:: Enable</comment>
        </bits>
        <bits access="rw" name="sp_th_sel_dpsk" pos="13:12" rst="0">
          <comment>DPSK sample threshold for demod</comment>
        </bits>
        <bits access="rw" name="sp_th_sel_gfsk" pos="11:10" rst="0">
          <comment>GFSK sample threshold for demod</comment>
        </bits>
        <bits access="rw" name="th_gfsk_dem2" pos="9:0" rst="10">
          <comment>GFSK sample 2nd threshold for demod</comment>
        </bits>
      </reg>
      <reg name="dpsk_gfsk_smp_th_1" protect="rw">
        <bits access="rw" name="ref_a2_sek" pos="9:0" rst="111">
          <comment>gfsk sample reference a2 for demod</comment>
        </bits>
      </reg>
      <reg name="gfsk_smp_ref_ctrl" protect="rw">
        <bits access="rw" name="ref_a1_sek" pos="15:8" rst="25">
          <comment>GFSK sample reference a1 for demod</comment>
        </bits>
        <bits access="rw" name="ref_a3_sek" pos="7:0" rst="25">
          <comment>GFSK sample reference a3 for demod</comment>
        </bits>
      </reg>
      <reg name="gfsk_smp_ref_ctrl_1" protect="rw">
        <bits access="rw" name="rsvd2" pos="15:14" rst="1">
          <comment>RESERVED</comment>
        </bits>
        <bits access="rw" name="guard_time_conf" pos="13:9" rst="1">
          <comment>tx guard timing delay to switch amp in ramp_gain_tx; counter in 13M</comment>
        </bits>
        <bits access="rw" name="dc_ct2" pos="8:0" rst="32">
          <comment>RESERVED</comment>
        </bits>
      </reg>
      <reg name="rateconv_ctrl1" protect="rw">
        <bits access="rw" name="dc_ct" pos="15:7" rst="136">
          <comment>DC Cancle ct code for demod</comment>
        </bits>
        <bits access="rw" name="dac_test_en" pos="6" rst="0">
          <comment>DAC Test Enable
1'h0 dac data is 52m_tx IQ
1'h1 dac data depends on dac_data_sel</comment>
        </bits>
        <bits access="rw" name="dac_data_sel" pos="5:0" rst="0">
          <comment>DAC Data Mux Select
6'b000000:: tx_52m_i:      tx_52m_q
6'b000001:: tx_26m_i:     tx_26m_q
6'b000010:: iqim_cancel_i:      iqim_cancel_q
6'b000011:: tx_13m_i:      tx_13m_q
6'b000100:: mixer_tx_i:      mixer_tx_q
6'b000101:: accu_tx:     blend_tx
6'b000110:: gfilter_tx:     diff_tx
6'b000111:: ampm_am:     ampm_pm
6'b001000:: cordic_tx_amp:     cordic_tx_ang
6'b001001:: symbol2iq_tx_i:     symbol2iq_tx_q
6'b001010:: tx_test_data0:      tx_test_data1
6'b100000:: angle:       angle_rc
6'b100001:: adc_data_i:       adc_data_q
6'b100010:: adc_din_i:       adc_din_q
6'b100011:: lpf_i:       lpf_q
6'b100100:: rateconv_i:      rateconv_q
6'b100101:: calib_i:         calib_q
6'b100110:: dc_calib_i:      dc_calib_q
6'b100111:: cancel_flt_i:       cancel_flt_q
6'b101000:: notch_i:       notch_q
6'b101001:: gain_i:        gain_q
6'b101010:: ble_mux_i:     ble_mux_q
6'b101011:: mixer_i:      mixer_q
6'b101100:: srrc_i:     srrc_q
6'b101101:: mixer_i_13_0:    mixer_q[13:0]
6'b101110:: srrc_i_11_0:     srrc_q[11:0]
6'b101111:: err_gfsk:       err_dpsk
6'b110000:: afc_gfsk:       afc_in
6'b110001:: angle_offset:      angle_offset1
6'b110010:: rssi_out:      rssi_out
6'b110011:: rx_test_data0:       rx_test_data1
6'b110100:: rx_test_data2:      rx_test_data3</comment>
        </bits>
      </reg>
      <reg name="rateconv_ctrl2" protect="rw">
        <bits access="rw" name="sel_rssi_src_post" pos="16" rst="0">
          <comment>1'b1::SRRC RSSI input data from mixer output data
1'b0::SRRC RSSI input data from SRRC output data</comment>
        </bits>
        <bits access="rw" name="sel_rssi_src_pre" pos="15" rst="1">
          <comment>1'b1::mixer RSSI input data from mixer output data
1'b0::mixer RSSI input data from SRRC output data</comment>
        </bits>
        <bits access="rw" name="rssi_sel" pos="14:13" rst="0">
          <comment>2'h0::rssi_out = rssi_out_noise_pre
2'h1::rssi_out = rssi_out_noise_post
2'h2::rssi_out = rssi_out_pre
2'h3::rssi_out = rssi_out_post</comment>
        </bits>
        <bits access="rw" name="rssi_tm_th_post" pos="12:7" rst="60">
          <comment>after SRRC RSSI threshold</comment>
        </bits>
        <bits access="rw" name="dc_hold_edr_en" pos="6" rst="1">
          <comment>DC cancle1 edr dc hold enable</comment>
        </bits>
        <bits access="rw" name="rssi_tm_th_pre" pos="5:0" rst="60">
          <comment>before SRRC RSSI threshold</comment>
        </bits>
      </reg>
      <reg name="demod_smp_ctrl" protect="rw">
        <bits access="rw" name="ini_rst_th" pos="15:10" rst="1">
          <comment>Count sample threshold reset for demod.</comment>
        </bits>
        <bits access="rw" name="ref_ready_th" pos="9:4" rst="0">
          <comment>GFSK iph th reference for demod.</comment>
        </bits>
        <bits access="rw" name="cnt_sample_ini" pos="3:0" rst="5">
          <comment>Sample point initial value</comment>
        </bits>
      </reg>
      <reg name="agc_ctrl" protect="rw">
        <bits access="rw" name="mix_guard_th" pos="15:10" rst="1">
          <comment>Guard time length threshold for demod</comment>
        </bits>
        <bits access="rw" name="dpsk_seek_st_cnt" pos="9:5" rst="10">
          <comment>DPSK Seek Start Count</comment>
        </bits>
        <bits access="rw" name="agc_en_fix7" pos="4" rst="1">
          <comment>Fix7 enable during demod
1'h0:: Disable
1'h1:: Enable</comment>
        </bits>
        <bits access="rw" name="agc_mod_fix7" pos="3" rst="0">
          <comment>Fix7 mode select during bt dsp demod
1'h0:: threshold_2
1'h1:: threshold_3</comment>
        </bits>
        <bits access="rw" name="agc_sinc_over_en" pos="2" rst="0">
          <comment>Rounding enable after sinc.
1'h0:: Disable
1'h1:: Enable</comment>
        </bits>
        <bits access="rw" name="agc_sinc_over_th" pos="1:0" rst="1">
          <comment>Threshold of Rounding after sinc.</comment>
        </bits>
      </reg>
      <reg name="agc_th_ctrl1" protect="rw">
        <bits access="rw" name="agc_th_max" pos="15:8" rst="96">
          <comment>AGC maximum threshold for demod</comment>
        </bits>
        <bits access="rw" name="agc_th_min" pos="7:0" rst="24">
          <comment>AGC minimum threshold for demod</comment>
        </bits>
      </reg>
      <reg name="agc_th_ctrl2" protect="rw">
        <bits access="rw" name="agc_th_max_lg" pos="15:8" rst="220">
          <comment>AGC maximum large threshold for demod</comment>
        </bits>
        <bits access="rw" name="agc_th_min_lg" pos="7:0" rst="40">
          <comment>AGC minimum large threshold for demod</comment>
        </bits>
      </reg>
      <reg name="agc_ctrl1" protect="rw">
        <bits access="rw" name="agc_ct_th_min" pos="14" rst="0">
          <comment>AGC minimum threshold for demod</comment>
        </bits>
        <bits access="rw" name="agc_en_lg_stp" pos="13" rst="1">
          <comment>AGC logarithmic step enable for demod
1'h0:: Disable
1'h1:: Enable</comment>
        </bits>
        <bits access="rw" name="agc_step_mode" pos="12:11" rst="1">
          <comment>AGC step mode for demod
2'b00:: AGC_step_1
2'b01:: AGC_step_2
2'b10:: AGC_step_3
2'b11:: AGC_step_4</comment>
        </bits>
        <bits access="rw" name="agc_step_over" pos="10:9" rst="2">
          <comment>AGC step over</comment>
        </bits>
        <bits access="rw" name="agc_en_dly" pos="8:6" rst="6">
          <comment>Delay timer count enable
3'b000:: Delay_0us
3'b001:: Delay_0p5us
3'b010:: Delay_1us
3'b011:: Delay_2us
3'b100:: Delay_3us
3'b101:: Delay_4us
3'b110:: Delay_6us
3'b111:: Delay_8us</comment>
        </bits>
        <bits access="rw" name="agc_index_ini_dsp" pos="5:2" rst="15">
          <comment>AGC gain index initial value for bt dsp</comment>
        </bits>
        <bits access="rw" name="agc_mod_dem" pos="1:0" rst="3">
          <comment>Demod mode select</comment>
        </bits>
      </reg>
      <reg name="agc_ctrl2" protect="rw">
        <bits access="rw" name="agc_th_min_gn" pos="15:14" rst="1">
          <comment>AGC minimum threshold gain select for demod
2'b00:: Gain_2
2'b01:: Gain_4
2'b10:: Gain_8
2'b11:: Gain_16</comment>
        </bits>
        <bits access="rw" name="agc_tm_intv" pos="13:7" rst="24">
          <comment>AGCtm_intv_int initial value for demod</comment>
        </bits>
        <bits access="rw" name="agc_tm_intv_lg" pos="6:0" rst="48">
          <comment>AGC tm_intv_int logarithmic initial value for demod</comment>
        </bits>
      </reg>
      <reg name="agc_dgc_ctrl" protect="rw">
        <bits access="rw" name="sel_reg_agc" pos="15" rst="1">
          <comment>AGC index select
1'h0:: dgc_index_dsp
1'h1:: dgc_index_mx</comment>
        </bits>
        <bits access="rw" name="dgc_index_dsp" pos="14:12" rst="0">
          <comment>DGC gain index</comment>
        </bits>
        <bits access="rw" name="dgc_index_max" pos="11:9" rst="4">
          <comment>Maximum agc gain index</comment>
        </bits>
        <bits access="rw" name="pass_newpacket_sel" pos="8" rst="0">
          <comment>Newpacket select for demod
1'h0 If newpacket from BB has one zero byte, select GID for demod, else select newpacket from BB
1'h1 Select newpacket from BB</comment>
        </bits>
        <bits access="rw" name="newpacket_zero_wd_cnt" pos="7:6" rst="0">
          <comment>Newpacket zero bytes number
2'b00 If the 1st  byte of newpacket  is zero,
newpacket_bb_sel is logic high, else low
2'b01 If the 1st &amp; 2nd  byte of newpacket  is zero,
newpacket_bb_sel is logic high, else low
2'b10 If the 1st &amp; 2nd &amp; 3rd byte of newpacket  is zero,
newpacket_bb_sel is logic high, else low
2'b11 If the 1st &amp; 2nd &amp; 3rd &amp;4th byte of newpacket  is zero, newpacket_bb_sel is logic high, else low</comment>
        </bits>
        <bits access="rw" name="agc_mode_dsp" pos="2:0" rst="4">
          <comment>AGC mode for dsp
3'h0:: Normal
3'h1:: RESERVED
3'h2:: Hold_after_timer
3'h3:: fix_to_index_ini
3'h4:: Hold_by_FSM
3'h5:: Th_large_mode: select by FSM
others RESERVED</comment>
        </bits>
      </reg>
      <reg name="agc_dccal_ctrl" protect="rw">
        <bits access="rw" name="agc_tm_wait" pos="15:11" rst="7">
          <comment>AGC hold waiting time length</comment>
        </bits>
        <bits access="rw" name="agc_tm_hold" pos="10:6" rst="10">
          <comment>AGC hold time length</comment>
        </bits>
        <bits access="r" name="rx_dc_cal_done" pos="3" rst="0">
          <comment>RX DC Calibration Done</comment>
        </bits>
        <bits access="rw" name="dc_cal_rx_dly" pos="2:1" rst="1">
          <comment>RX DC Calibration Delay for 1 loop
2'h0:: 0p6ms
2'h1:: 1p2ms
2'h2:: 2p4ms
2'h3:: 4p8ms</comment>
        </bits>
        <bits access="rw" name="rx_fix_dcofst" pos="0" rst="0">
          <comment>DC offset fix select for rx
1'h0:: by_calib: DC offset data set by calibration
1'h1:: by_reg: DC offset data set by register</comment>
        </bits>
      </reg>
      <reg name="rx_dccal_ctrl" protect="rw">
        <bits access="rw" name="rx_dc_cali_i_fix" pos="25:16" rst="0">
          <comment>RX DC fixed offset data for I path when if_fix_dcofst is 1; otherwise use the auto calc values.</comment>
        </bits>
        <bits access="rw" name="rx_dc_cali_q_fix" pos="9:0" rst="0">
          <comment>RX DC fixed offset data for Q path when if_fix_dcofst is 1; otherwise use the auto calc values.</comment>
        </bits>
      </reg>
      <reg name="rx_dcofst_inuse" protect="r">
        <bits access="r" name="rx_dcoffset_i" pos="25:16" rst="0">
          <comment>rx dc offset for dc calibration; selected from dc_cali_i_fix &amp; dc_i2d_work_i</comment>
        </bits>
        <bits access="r" name="rx_dcoffset_q" pos="9:0" rst="0">
          <comment>rx dc offset for dc calibration; selected from dc_cali_q_fix &amp; dc_i2d_work_q</comment>
        </bits>
      </reg>
      <reg name="tx_dc_calib" protect="rw">
        <bits access="r" name="tx_dc_cal_done" pos="15" rst="0">
          <comment>TX Calibration Done</comment>
        </bits>
        <bits access="r" name="tx_cal_out_i" pos="14" rst="0">
          <comment>tx calib out i</comment>
        </bits>
        <bits access="r" name="tx_cal_out_q" pos="13" rst="0">
          <comment>tx calib out q</comment>
        </bits>
        <bits access="rw" name="tx_fix_dcofst" pos="12" rst="0">
          <comment>Fix TX DC Offset</comment>
        </bits>
        <bits access="rw" name="tx_cal_cnt" pos="11:10" rst="2">
          <comment>TX Calibration Step Counters for 25KHz
2'b00:: 0p125_range
2'b01:: 0p25_range
2'b10:: 0p5_range
2'b11:: full_range</comment>
        </bits>
        <bits access="rw" name="tx_cal_cmp_pol" pos="9" rst="0">
          <comment>TX Calibration Comparison Polarity</comment>
        </bits>
        <bits access="rw" name="tx_cal_pol" pos="8" rst="1">
          <comment>TX Calibration Offset Polarity
0:: no_switch: the polarity of TX calibration offset
1:: switch: the polarity of TX calibration offset</comment>
        </bits>
        <bits access="rw" name="tx_cal_sel" pos="7:6" rst="0">
          <comment>TX Calibration Selection
2'b00:: mean: (tx_cal1 + tx_cal2)/2
2'b01:: tx_cal1
2'b10:: tx_cal2</comment>
        </bits>
        <bits access="rw" name="tx_cal_shift" pos="5:4" rst="2">
          <comment>TX Calibration Offset Shift
2'b00:: x4: left shift by 2 bits
2'b01:: x2: left shift by 1 bit
2'b10:: x1: no shift</comment>
        </bits>
        <bits access="rw" name="tx_apc" pos="3:1" rst="7">
          <comment>TX Gain Table Pointer during work</comment>
        </bits>
        <bits access="rw" name="bypass_tx_cal" pos="0" rst="0">
          <comment>Bypass TX Calibration Offset
1'b0:: not_bypass
1'b1:: bypass</comment>
        </bits>
      </reg>
      <reg name="tx_fix_i_dcofst" protect="rw">
        <bits access="rw" name="tx_dc_idata_fix" pos="11:0" rst="0">
          <comment>Fixed TX I Signed Data for DC offset</comment>
        </bits>
      </reg>
      <reg name="tx_fix_q_dcofst" protect="rw">
        <bits access="rw" name="tx_dc_qdata_fix" pos="11:0" rst="0">
          <comment>TX Q Signed Data for DC offset</comment>
        </bits>
      </reg>
      <reg name="tx_i_dcofst_inuse" protect="r">
        <bits access="r" name="dc_cal_tx_idata" pos="11:0" rst="0">
          <comment>TX I Signed Data offset in use</comment>
        </bits>
      </reg>
      <reg name="tx_q_dcofst_inuse" protect="r">
        <bits access="r" name="dc_cal_tx_qdata" pos="11:0" rst="0">
          <comment>TX Q Signed Data offset in use</comment>
        </bits>
      </reg>
      <reg name="rssi_gain_ctrl1" protect="rw">
        <bits access="rw" name="rssi_ana_gain0000" pos="15:8" rst="9">
          <comment>RSSI gain 0000</comment>
        </bits>
        <bits access="rw" name="rssi_ana_gain0001" pos="7:0" rst="19">
          <comment>ARSSI gain 0001</comment>
        </bits>
      </reg>
      <reg name="rssi_gain_ctrl2" protect="rw">
        <bits access="rw" name="rssi_ana_gain0010" pos="15:8" rst="27">
          <comment>RSSI gain 0010</comment>
        </bits>
        <bits access="rw" name="rssi_ana_gain0011" pos="7:0" rst="35">
          <comment>ARSSI gain 0011</comment>
        </bits>
      </reg>
      <reg name="rssi_gain_ctrl3" protect="rw">
        <bits access="rw" name="rssi_ana_gain0100" pos="15:8" rst="41">
          <comment>RSSI gain 0100</comment>
        </bits>
        <bits access="rw" name="rssi_ana_gain0101" pos="7:0" rst="49">
          <comment>ARSSI gain 0101</comment>
        </bits>
      </reg>
      <reg name="rssi_gain_ctrl4" protect="rw">
        <bits access="rw" name="rssi_ana_gain0110" pos="15:8" rst="55">
          <comment>RSSI gain 0110</comment>
        </bits>
        <bits access="rw" name="rssi_ana_gain0111" pos="7:0" rst="63">
          <comment>ARSSI gain 0111</comment>
        </bits>
      </reg>
      <reg name="rssi_gain_ctrl5" protect="rw">
        <bits access="rw" name="rssi_ana_gain1000" pos="15:8" rst="9">
          <comment>RSSI gain 1000</comment>
        </bits>
        <bits access="rw" name="rssi_ana_gain1001" pos="7:0" rst="19">
          <comment>ARSSI gain 1001</comment>
        </bits>
      </reg>
      <reg name="rssi_gain_ctrl6" protect="rw">
        <bits access="rw" name="rssi_ana_gain1010" pos="15:8" rst="27">
          <comment>RSSI gain 1010</comment>
        </bits>
        <bits access="rw" name="rssi_ana_gain1011" pos="7:0" rst="35">
          <comment>ARSSI gain 1011</comment>
        </bits>
      </reg>
      <reg name="rssi_gain_ctrl7" protect="rw">
        <bits access="rw" name="rssi_ana_gain1100" pos="15:8" rst="41">
          <comment>RSSI gain 1100</comment>
        </bits>
        <bits access="rw" name="rssi_ana_gain1101" pos="7:0" rst="49">
          <comment>ARSSI gain 1101</comment>
        </bits>
      </reg>
      <reg name="rssi_gain_ctrl8" protect="rw">
        <bits access="rw" name="rssi_ana_gain1110" pos="15:8" rst="55">
          <comment>RSSI gain 1110</comment>
        </bits>
        <bits access="rw" name="rssi_ana_gain1111" pos="7:0" rst="63">
          <comment>ARSSI gain 1111</comment>
        </bits>
      </reg>
      <reg name="modem_tpd_sel" protect="rw">
        <bits access="rw" name="dac_clk_force_en" pos="9" rst="0">
          <comment>DAC Clock Force Enable while rx data to dac</comment>
        </bits>
        <bits access="rw" name="tpd_clk_sel" pos="8" rst="0">
          <comment>Test Ports Clock Select
0:: clk_rx
1:: clk_tx</comment>
        </bits>
        <bits access="rw" name="tpd_data_sel" pos="7:4" rst="0">
          <comment>Test Ports Data Select
4'h0::  dac_data_i
4'h1::  dac_data_q
4'h2::  dout_tx_i_sum
4'h3::  dout_tx_q_sum
4'h4::  dout_tx_dac_i: depends on dac_data_sel
4'h5::  dout_tx_dac_q
4'h6::  dout_rx_dac_i
4'h7::  dout_rx_dac_q
4'h8::  dout_tx_dac_i_13m: by en_tx_13m
4'h9::  dout_tx_dac_q_13m: by en_tx_13m
4'ha::  dout_rx_dac_i_13m: by en_rx_13m
4'hb::  dout_rx_dac_q_13m: by en_rx_13m
4'hc::  dout_rx_dac_i_14m: by en_rx_14m
4'hd::  dout_rx_dac_q_14m: by en_rx_14m
4'he::  dout_tx_dac_i_26m: by en_tx_26m
4'hf::  dout_tx_dac_q_26m: by en_tx_26m</comment>
        </bits>
        <bits access="rw" name="tpd_trig_sel" pos="3:0" rst="0">
          <comment>Test Ports Trigger Select
4'h0::  dem_st_chg
4'h1::  agc_st_chg
4'h2::  agc_flg_dem
4'h3::  ble_access_rb
4'h4::  if_peak
4'h5::  if_seeked_all
4'h6::  seek_en
4'h7::  flg_getsymbol
4'h8::  tx_symbol_off_gfsk
4'h9::  tx_amp_sel
4'ha::  tx_flg_start</comment>
        </bits>
      </reg>
      <reg name="demod_smp_th_ctrl" protect="rw">
        <bits access="rw" name="dem_sp_th2" pos="15:8" rst="162">
          <comment>Demod sample threshold2</comment>
        </bits>
        <bits access="rw" name="dem_sp_th1" pos="7:0" rst="64">
          <comment>Demod sample threshold1</comment>
        </bits>
      </reg>
      <reg name="newpacket_byte4" protect="rw">
        <bits access="rw" name="newpacket_4" pos="15:0" rst="49152">
          <comment>The 4th byte newpacket for demod when sel_sync(register_41[13]) is 1</comment>
        </bits>
      </reg>
      <reg name="newpacket_byte3" protect="rw">
        <bits access="rw" name="newpacket_3" pos="15:0" rst="26214">
          <comment>The 3rd byte newpacket for demod when sel_sync(register_41[13]) is 1</comment>
        </bits>
      </reg>
      <reg name="newpacket_byte2" protect="rw">
        <bits access="rw" name="newpacket_2" pos="15:0" rst="13107">
          <comment>The 2nd byte newpacket for demod when sel_sync(register_41[13]) is 1</comment>
        </bits>
      </reg>
      <reg name="newpacket_byte1" protect="rw">
        <bits access="rw" name="newpacket_1" pos="15:0" rst="21845">
          <comment>The 1st byte newpacket for demod when sel_sync(register_41[13]) is 1</comment>
        </bits>
      </reg>
      <reg name="gfsk_mod_ctrl" protect="rw">
        <bits access="rw" name="rssi_ct_u_post" pos="18:16" rst="4">
          <comment>SRRC RSSI gain control</comment>
        </bits>
        <bits access="rw" name="bt_mod" pos="15" rst="1">
          <comment>Bluetooth GFSK modulation filter select</comment>
        </bits>
        <bits access="rw" name="rssi_ct_u_pre" pos="14:12" rst="4">
          <comment>MIXER RSSI gain control</comment>
        </bits>
        <bits access="rw" name="ref_a2_dem" pos="9:0" rst="117">
          <comment>GFSK demod a2 reference for rx demod</comment>
        </bits>
      </reg>
      <reg name="gfsk_mod_ref_ctrl" protect="rw">
        <bits access="rw" name="ref_a1_dem" pos="15:8" rst="22">
          <comment>GFSK demod a1 reference for rx demod</comment>
        </bits>
        <bits access="rw" name="ref_a3_dem" pos="7:0" rst="22">
          <comment>GFSK demod a3 reference for rx demod</comment>
        </bits>
      </reg>
      <reg name="sym_dly_ctrl" protect="rw">
        <bits access="rw" name="ramp_speed_gfsk" pos="13" rst="0">
          <comment>GFSK ramp speed select
1'h0:: Slow
1'h1:: Fast</comment>
        </bits>
        <bits access="rw" name="delay_gfsk_off" pos="12:9" rst="8">
          <comment>GFSK symbol end flag delay, with 13MHz clk step</comment>
        </bits>
        <bits access="rw" name="delay_gfsk_off_1m" pos="8:6" rst="4">
          <comment>GFSK symbol end flag delay, with 1MHz clk step</comment>
        </bits>
        <bits access="rw" name="delay_dpsk_1m" pos="5:3" rst="0">
          <comment>DPSK symbol delay, with 1MHz clk step</comment>
        </bits>
        <bits access="rw" name="delay_gfsk_1m" pos="2:0" rst="0">
          <comment>GFSK symbol delay, with 1MHz clk step</comment>
        </bits>
      </reg>
      <reg name="rssi_out2" protect="r">
        <bits access="r" name="rssi_noise_out_post" pos="25:16" rst="0">
          <comment>after SRRC RSSI noise out</comment>
        </bits>
        <bits access="r" name="rssi_noise_out_pre" pos="9:0" rst="0">
          <comment>after mixer before SRRC RSSI noise out</comment>
        </bits>
      </reg>
      <reg name="trx_clk_ctrl" protect="rw">
        <bits access="rw" name="swch_clk_52m_rx" pos="14" rst="0">
          <comment>Switch the clk edge to sample rf ADC data
1'h0:: negedge: to sample the RF ADC data
1'h1:: posedge: to sample the RF ADC data</comment>
        </bits>
        <bits access="rw" name="tx_rx_dir" pos="13" rst="0">
          <comment>TX/RX direction
1'h0:: by_hw: TX/RX flag setting by deleying resetn_dsp_tx
1'h1:: by_reg: TX/RX flag setting by register</comment>
        </bits>
        <bits access="rw" name="tx_rx_reg" pos="12" rst="0">
          <comment>TX/RX flag
1'h0:: RX
1'h1:: TX</comment>
        </bits>
        <bits access="rw" name="apc_switch_mode" pos="9:6" rst="3">
          <comment>RESERVED</comment>
        </bits>
      </reg>
      <reg name="iq_swap_ctrl" protect="rw">
        <bits access="rw" name="swch_clk_52m_tx" pos="15" rst="1">
          <comment>TX link 52M clk edge switch
1'h0:: Not_Switch
1'h1:: Switch</comment>
        </bits>
        <bits access="rw" name="iq_swap_gain2" pos="14" rst="0">
          <comment>Digital gain2 output I/Q swap
1'h0:: Not_Swap
1'h1:: Swap</comment>
        </bits>
        <bits access="rw" name="iq_swap_lpf" pos="13" rst="0">
          <comment>Rate converter LPF filter output I/Q swap
1'h0:: Not_Swap
1'h1:: Swap</comment>
        </bits>
        <bits access="rw" name="iq_swap_srrc" pos="12" rst="0">
          <comment>SRRC filter output I/Q swap
1'h0:: Not_Swap
1'h1:: Swap</comment>
        </bits>
        <bits access="rw" name="lpf_en_1" pos="6" rst="1">
          <comment>Low Pass Filter Enable in Channel Group1
1'h0:: bypass
1'h1:: enable</comment>
        </bits>
        <bits access="rw" name="rate_conv_en_1" pos="5" rst="1">
          <comment>Rate Converter Enable in Channel Group1
1'h0:: bypass
1'h1:: enable</comment>
        </bits>
        <bits access="rw" name="notch_en_1" pos="4" rst="1">
          <comment>Notch Filter Enable in Channel Group1
1'h0:: bypass
1'h1:: enable</comment>
        </bits>
        <bits access="rw" name="lpf_en_0" pos="2" rst="1">
          <comment>Low Pass Filter Enable in Channel Group0
1'h0:: bypass
1'h1:: enable</comment>
        </bits>
        <bits access="rw" name="rate_conv_en_0" pos="1" rst="0">
          <comment>Rate Converter Enable in Channel Group0
1'h0:: bypass
1'h1:: enable</comment>
        </bits>
        <bits access="rw" name="notch_en_0" pos="0" rst="0">
          <comment>Notch Filter Enable in Channel Group0
1'h0:: bypass
1'h1:: enable</comment>
        </bits>
      </reg>
      <reg name="gfsk_sync_ctrl" protect="rw">
        <bits access="rw" name="dynamic_sync_en" pos="10" rst="0">
          <comment>Dynamic sync enable for demod of rx link
1'h0:: static
1'h1:: Dynamic</comment>
        </bits>
        <bits access="rw" name="dynamic_sync_th" pos="9:0" rst="0">
          <comment>Dynamic sync threshold</comment>
        </bits>
      </reg>
      <reg name="gfsk_demod_ctrl" protect="rw">
        <bits access="rw" name="min_error_th2" pos="15:0" rst="0">
          <comment>The 2nd minimum sync phase error threshold</comment>
        </bits>
      </reg>
      <reg name="gfsk_mod_idx" protect="rw">
        <bits access="rw" name="h_gain" pos="15:0" rst="12704">
          <comment>GFSK modulation index</comment>
        </bits>
      </reg>
      <reg name="dpsk_gfsk_misc_ctrl" protect="rw">
        <bits access="rw" name="iq_swap_tx" pos="15" rst="0">
          <comment>Tx link IQ swap
1'h0:: Not_swap
1'h1:: Swap</comment>
        </bits>
        <bits access="rw" name="dly_ct_gfsk" pos="11:9" rst="7">
          <comment>GFSK delay after gfsk modulation</comment>
        </bits>
        <bits access="rw" name="dly_ct_dpsk" pos="8:6" rst="1">
          <comment>DPSK delay after dpsk modulation</comment>
        </bits>
        <bits access="rw" name="dly_ct_amp" pos="5:3" rst="4">
          <comment>DPSK amplitude delay after dpsk modulation</comment>
        </bits>
      </reg>
      <reg name="modem_dbm_sel" protect="rw">
        <bits access="rw" name="dbm_data_sel" pos="4:0" rst="0">
          <comment>Debug Master Data Select
5'h0::  gfilter_tx_dout
5'h1::  symbol2iq_tx_dout_q: symbol2iq_tx_dout_i
5'h2::  cordic_tx_amp_dout: cordic_tx_angle_dout
5'h3::  ampm_tx_dout_am: ampm_tx_dout_pm
5'h4::  diff_tx_dout
5'h5::  freq_blend_tx_dout
5'h6::  intigrate_tx_dout
5'h7::  cordic_iq_tx_dout_q: cordic_iq_tx_dout_i
5'h8::  dout_tx_13m_q: dout_tx_13m_i
5'h9::  iqim_cancel_dout_q: iqim_cancel_dout_i
5'ha::  dout_tx_26m_q: dout_tx_26m_i
5'hb::  dout_tx_52m_q: dout_tx_52m_i
5'hc:: dac_grp_bit_q_outp: dac_grp_bit_i_outp
5'h10:: adc_data_q: adc_data_i
5'h11:: adc_din_q: adc_din_i
5'h12:: lpf_q: lpf_i
5'h13:: rateconv_q: rateconv_i
5'h14:: calib_q: calib_i
5'h15:: dc_calib_q: dc_calib_i
5'h16:: cancel_flt_i: cancel_flt_q
5'h17:: notch_q: notch_i
5'h18:: gain_q: gain_i
5'h19:: ble_mux_q: ble_mux_i
5'h1a:: mixer_q: mixer_i
5'h1b:: srrc_q: srrc_i
5'h1c:: rssi_out
5'h1d:: angle_rc: angle
5'h1e:: angle_offset1: angle_offset
5'h1f:: err_dpsk: err_gfsk</comment>
        </bits>
      </reg>
      <reg name="gfsk_mod_idx_le" protect="rw">
        <bits access="rw" name="h_gain_le" pos="15:0" rst="20165">
          <comment>GFSK modulation index for BLE mode</comment>
        </bits>
      </reg>
      <reg name="newpacket_byte4_inuse" protect="r">
        <bits access="r" name="newpacket_dsp4" pos="15:0" rst="32368">
          <comment>newpacket byte 4 inuse; selected from newpacket_reg, GID &amp; newpacket_bb</comment>
        </bits>
      </reg>
      <reg name="newpacket_byte3_inuse" protect="r">
        <bits access="r" name="newpacket_dsp3" pos="15:0" rst="16867">
          <comment>newpacket byte 3 inuse; selected from newpacket_reg, GID &amp; newpacket_bb</comment>
        </bits>
      </reg>
      <reg name="newpacket_byte2_inuse" protect="r">
        <bits access="r" name="newpacket_dsp2" pos="15:0" rst="16384">
          <comment>newpacket byte 2 inuse; selected from newpacket_reg, GID &amp; newpacket_bb</comment>
        </bits>
      </reg>
      <reg name="newpacket_byte1_inuse" protect="r">
        <bits access="r" name="newpacket_dsp1" pos="15:0" rst="13">
          <comment>newpacket byte 1 inuse; selected from newpacket_reg, GID &amp; newpacket_bb</comment>
        </bits>
      </reg>
      <reg name="le_mode_ctrl1" protect="rw">
        <bits access="rw" name="ref_a1_sek_le" pos="15:8" rst="40">
          <comment>??</comment>
        </bits>
        <bits access="rw" name="ref_a1_dem_le" pos="7:0" rst="35">
          <comment>??</comment>
        </bits>
      </reg>
      <reg name="le_mode_ctrl2" protect="rw">
        <bits access="rw" name="ref_a2_sek_le" pos="15:8" rst="176">
          <comment>??</comment>
        </bits>
        <bits access="rw" name="ref_a2_dem_le" pos="7:0" rst="186">
          <comment>??</comment>
        </bits>
      </reg>
      <reg name="le_mode_ctrl3" protect="rw">
        <bits access="rw" name="ref_a3_sek_le" pos="15:8" rst="40">
          <comment>??</comment>
        </bits>
        <bits access="rw" name="ref_a3_dem_le" pos="7:0" rst="35">
          <comment>??</comment>
        </bits>
      </reg>
      <reg name="le_mode_ctrl4" protect="rw">
        <bits access="rw" name="min_error_th_le" pos="15:0" rst="2334">
          <comment>??</comment>
        </bits>
      </reg>
      <reg name="le_mode_ctrl5" protect="rw">
        <bits access="rw" name="rsvd5" pos="15:14" rst="0">
          <comment>RESERVED</comment>
        </bits>
        <bits access="rw" name="ref_point_sel_le" pos="13:12" rst="2">
          <comment>??</comment>
        </bits>
        <bits access="rw" name="mix_guard_th_le" pos="11:6" rst="4">
          <comment>??</comment>
        </bits>
        <bits access="rw" name="ref_ready_th_le" pos="5:0" rst="3">
          <comment>??</comment>
        </bits>
      </reg>
      <reg name="rf_ctrl" protect="rw">
        <bits access="rw" name="sync_shift_mode" pos="0" rst="0">
          <comment>??</comment>
        </bits>
      </reg>
      <reg name="tx_q_im" protect="rw">
        <bits access="rw" name="tx_iqim_phase_err" pos="14:0" rst="0">
          <comment>Error on Q to reduce IQ mismatch Image</comment>
        </bits>
      </reg>
      <reg name="tx_i_im" protect="rw">
        <bits access="rw" name="tx_iqim_amp_err" pos="14:0" rst="0">
          <comment>Error on I to reduce IQ mismatch Image</comment>
        </bits>
      </reg>
      <reg name="tx_am_p0" protect="rw">
        <bits access="rw" name="pm_shift" pos="14:12" rst="0">
          <comment>PM Compensation Shift</comment>
        </bits>
        <bits access="rw" name="pm_comp_bypass" pos="11" rst="1">
          <comment>PM Compensation Bypass
1'b0:: enable
1'b1:: bypass</comment>
        </bits>
        <bits access="rw" name="am_comp_bypass" pos="10" rst="1">
          <comment>AM Compensation Bypass
1'b0:: enable
1'b1:: bypass</comment>
        </bits>
        <bits access="rw" name="am_p0" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef0</comment>
        </bits>
      </reg>
      <reg name="tx_am_p1" protect="rw">
        <bits access="rw" name="am_p1" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef1</comment>
        </bits>
      </reg>
      <reg name="tx_am_p2" protect="rw">
        <bits access="rw" name="am_p2" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef2</comment>
        </bits>
      </reg>
      <reg name="tx_am_p3" protect="rw">
        <bits access="rw" name="am_p3" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef3</comment>
        </bits>
      </reg>
      <reg name="tx_am_p4" protect="rw">
        <bits access="rw" name="am_p4" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef4</comment>
        </bits>
      </reg>
      <reg name="tx_am_p5" protect="rw">
        <bits access="rw" name="am_p5" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef5</comment>
        </bits>
      </reg>
      <reg name="tx_am_p6" protect="rw">
        <bits access="rw" name="am_p6" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef6</comment>
        </bits>
      </reg>
      <reg name="tx_am_p7" protect="rw">
        <bits access="rw" name="am_p7" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef7</comment>
        </bits>
      </reg>
      <reg name="tx_am_p8" protect="rw">
        <bits access="rw" name="am_p8" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef8</comment>
        </bits>
      </reg>
      <reg name="tx_am_p9" protect="rw">
        <bits access="rw" name="am_p9" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef9</comment>
        </bits>
      </reg>
      <reg name="tx_am_p10" protect="rw">
        <bits access="rw" name="am_p10" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef10</comment>
        </bits>
      </reg>
      <reg name="tx_am_p11" protect="rw">
        <bits access="rw" name="am_p11" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef11</comment>
        </bits>
      </reg>
      <reg name="tx_am_p12" protect="rw">
        <bits access="rw" name="am_p12" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef12</comment>
        </bits>
      </reg>
      <reg name="tx_am_p13" protect="rw">
        <bits access="rw" name="am_p13" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef13</comment>
        </bits>
      </reg>
      <reg name="tx_am_p14" protect="rw">
        <bits access="rw" name="am_p14" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef14</comment>
        </bits>
      </reg>
      <reg name="tx_am_p15" protect="rw">
        <bits access="rw" name="am_p15" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef15</comment>
        </bits>
      </reg>
      <reg name="tx_am_p16" protect="rw">
        <bits access="rw" name="am_p16" pos="9:0" rst="0">
          <comment>AMAM Compensation Coef16</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p0" protect="rw">
        <bits access="rw" name="pm_p0" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef0</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p1" protect="rw">
        <bits access="rw" name="pm_p1" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef1</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p2" protect="rw">
        <bits access="rw" name="pm_p2" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef2</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p3" protect="rw">
        <bits access="rw" name="pm_p3" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef3</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p4" protect="rw">
        <bits access="rw" name="pm_p4" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef4</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p5" protect="rw">
        <bits access="rw" name="pm_p5" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef5</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p6" protect="rw">
        <bits access="rw" name="pm_p6" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef6</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p7" protect="rw">
        <bits access="rw" name="pm_p7" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef7</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p8" protect="rw">
        <bits access="rw" name="pm_p8" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef8</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p9" protect="rw">
        <bits access="rw" name="pm_p9" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef9</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p10" protect="rw">
        <bits access="rw" name="pm_p10" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef10</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p11" protect="rw">
        <bits access="rw" name="pm_p11" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef11</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p12" protect="rw">
        <bits access="rw" name="pm_p12" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef12</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p13" protect="rw">
        <bits access="rw" name="pm_p13" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef13</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p14" protect="rw">
        <bits access="rw" name="pm_p14" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef14</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p15" protect="rw">
        <bits access="rw" name="pm_p15" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef15</comment>
        </bits>
      </reg>
      <reg name="tx_pm_p16" protect="rw">
        <bits access="rw" name="pm_p16" pos="9:0" rst="0">
          <comment>AMPM Compensation Coef16</comment>
        </bits>
      </reg>
      <reg name="notch_coef" protect="rw">
        <bits access="rw" name="notch_b" pos="13:0" rst="15347">
          <comment>Notch Filter Coefficient B</comment>
        </bits>
      </reg>
      <reg name="adapt_edr3_demod" protect="rw">
        <bits access="rw" name="notch_a" pos="15:12" rst="12">
          <comment>Notch Filter Coefficient A</comment>
        </bits>
        <bits access="rw" name="edr3_adapt_en" pos="9" rst="0">
          <comment>EDR3 Adapt Demodulation Enable
1'b0:: disable
1'b1:: enable</comment>
        </bits>
        <bits access="rw" name="ct_u_dpsk1" pos="8:5" rst="2">
          <comment>second u_err of the dpsk 2/32</comment>
        </bits>
        <bits access="rw" name="ct_u_1_dpsk1" pos="4:0" rst="26">
          <comment>second u_dc of the dpsk 2/512</comment>
        </bits>
      </reg>
      <reg name="adapt_edr3_thresh" protect="rw">
        <bits access="rw" name="edr3_adapt_th" pos="11:0" rst="20">
          <comment>EDR3 Adapt Demodulation Threshold</comment>
        </bits>
      </reg>
      <reg name="tx_auto_gain1_gfsk" protect="rw">
        <bits access="rw" name="tx_auto_gain_gfsk7" pos="15:12" rst="9">
          <comment>auto gfsk digital gain high 4bits. Tx_power=3'h7</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk6" pos="11:8" rst="9">
          <comment>auto gfsk digital gain high 4bits. Tx_power=3'h6</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk5" pos="7:4" rst="9">
          <comment>auto gfsk digital gain high 4bits. Tx_power=3'h5</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk4" pos="3:0" rst="9">
          <comment>auto gfsk digital gain high 4bits. Tx_power=3'h4</comment>
        </bits>
      </reg>
      <reg name="tx_auto_gain0_gfsk" protect="rw">
        <bits access="rw" name="tx_auto_gain_gfsk3" pos="15:12" rst="9">
          <comment>auto gfsk digital gain high 4bits. Tx_power=3'h3</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk2" pos="11:8" rst="9">
          <comment>auto gfsk digital gain high 4bits. Tx_power=3'h2</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk1" pos="7:4" rst="9">
          <comment>auto gfsk digital gain high 4bits. Tx_power=3'h1</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk0" pos="3:0" rst="9">
          <comment>auto gfsk digital gain high 4bits. Tx_power=3'h0</comment>
        </bits>
      </reg>
      <reg name="tx_auto_gain1_gfsk_edr" protect="rw">
        <bits access="rw" name="tx_auto_gain_gfsk_edr7" pos="15:12" rst="7">
          <comment>auto gfsk edr digital gain high 4bits. Tx_power=3'h7</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk_edr6" pos="11:8" rst="7">
          <comment>auto gfsk edr digital gain high 4bits. Tx_power=3'h6</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk_edr5" pos="7:4" rst="7">
          <comment>auto gfsk edr digital gain high 4bits. Tx_power=3'h5</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk_edr4" pos="3:0" rst="7">
          <comment>auto gfsk edr digital gain high 4bits. Tx_power=3'h4</comment>
        </bits>
      </reg>
      <reg name="tx_auto_gain0_gfsk_edr" protect="rw">
        <bits access="rw" name="tx_auto_gain_gfsk_edr3" pos="15:12" rst="7">
          <comment>auto gfsk edr digital gain high 4bits. Tx_power=3'h3</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk_edr2" pos="11:8" rst="7">
          <comment>auto gfsk edr digital gain high 4bits. Tx_power=3'h2</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk_edr1" pos="7:4" rst="7">
          <comment>auto gfsk edr digital gain high 4bits. Tx_power=3'h1</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_gfsk_edr0" pos="3:0" rst="7">
          <comment>auto gfsk edr digital gain high 4bits. Tx_power=3'h0</comment>
        </bits>
      </reg>
      <reg name="tx_auto_gain1_dpsk" protect="rw">
        <bits access="rw" name="tx_auto_gain_dpsk7" pos="15:12" rst="13">
          <comment>auto dpsk digital gain high 4bits. Tx_power=3'h7</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_dpsk6" pos="11:8" rst="13">
          <comment>auto dpsk digital gain high 4bits. Tx_power=3'h6</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_dpsk5" pos="7:4" rst="13">
          <comment>auto dpsk digital gain high 4bits. Tx_power=3'h5</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_dpsk4" pos="3:0" rst="13">
          <comment>auto dpsk digital gain high 4bits. Tx_power=3'h4</comment>
        </bits>
      </reg>
      <reg name="tx_auto_gain0_dpsk" protect="rw">
        <bits access="rw" name="tx_auto_gain_dpsk3" pos="15:12" rst="13">
          <comment>auto dpsk digital gain high 4bits. Tx_power=3'h3</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_dpsk2" pos="11:8" rst="13">
          <comment>auto dpsk digital gain high 4bits. Tx_power=3'h2</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_dpsk1" pos="7:4" rst="13">
          <comment>auto dpsk digital gain high 4bits. Tx_power=3'h1</comment>
        </bits>
        <bits access="rw" name="tx_auto_gain_dpsk0" pos="3:0" rst="13">
          <comment>auto dpsk digital gain high 4bits. Tx_power=3'h0</comment>
        </bits>
      </reg>
      <reg name="gfsk_mod_eql_gain" protect="rw">
        <bits access="rw" name="equ_g_gfsk" pos="15:0" rst="807">
          <comment>GFSK modulation equalization gain</comment>
        </bits>
      </reg>
      <reg name="tx_lfp_delay_ctrl" protect="rw">
        <bits access="rw" name="dly_ct_freq2" pos="14:12" rst="5">
          <comment>Phase path delay number 2, with 26MHz clk step</comment>
        </bits>
        <bits access="rw" name="dly_ct_freq1" pos="10:8" rst="5">
          <comment>Phase path delay number 1, with 26MHz clk step</comment>
        </bits>
        <bits access="rw" name="lpfil_freq_tx_bypass" pos="6" rst="0">
          <comment>GFSK Low pass filter bypass
1'h0 Not bypass
1'h1 bypass
Note:
IQ Tx mode: register_c9[5:4]=00
Polar Loop &amp; IQ Tx mode: register_c9[5:4]=01
All Polar Loop Tx mode: register_c9[5:4]=11</comment>
        </bits>
        <bits access="rw" name="lpfil_freq_tx_enable" pos="5" rst="0">
          <comment>GFSK low pass filter enable
1'h0: Enable LPFil, output low pass gfsk signal
1'h1: Disable LPFil, output is zero</comment>
        </bits>
        <bits access="rw" name="lpfil_freq_tx_bw_ct" pos="4:0" rst="8">
          <comment>GFSK low pass filter pass band width select
1: lpfil_freq_tx_bw_ct[4]=0
BW = 100K + lpfil_freq_tx_bw_ct* 20
2: lpfil_freq_tx_bw_ct[4]=1
BW = 50K</comment>
        </bits>
      </reg>
      <reg name="tx_hfp_delay" protect="rw">
        <bits access="rw" name="dly_sel_freq" pos="14:12" rst="5">
          <comment>Delay of the gfsk and dpsk mixed phase</comment>
        </bits>
        <bits access="rw" name="dly_ct_iq1" pos="10:8" rst="5">
          <comment>I/Q path delay number 1, with 26MHz clk step</comment>
        </bits>
        <bits access="rw" name="dly_ct_iq2" pos="6:4" rst="5">
          <comment>I/Q path delay number 2, with 26MHz clk step</comment>
        </bits>
        <bits access="rw" name="dly_ct_freq_high" pos="2:0" rst="3">
          <comment>High frequency path delay</comment>
        </bits>
      </reg>
      <reg name="tx_polar_mode_ctl" protect="rw">
        <bits access="rw" name="tx_tmp_dly" pos="4:2" rst="3">
          <comment>amp tmp delay</comment>
        </bits>
        <bits access="rw" name="tx_polar_mode_sel" pos="1" rst="1">
          <comment>tx polar modulation mode selected
1'b0::phase mode
1'b1::frequency mode</comment>
        </bits>
        <bits access="rw" name="tx_apf_bypass" pos="0" rst="1">
          <comment>tx polar modulation all pass filter bypass ctl
1'b1::bypass
1'b0::no bypass</comment>
        </bits>
      </reg>
      <reg name="tx_apf_num_b1" protect="rw">
        <bits access="rw" name="num_coe_b1" pos="13:0" rst="2273">
          <comment>tx polar modulation apf num coe-2.14</comment>
        </bits>
      </reg>
      <reg name="tx_apf_num_b2" protect="rw">
        <bits access="rw" name="num_coe_b2" pos="13:0" rst="2273">
          <comment>tx polar modulation apf num coe</comment>
        </bits>
      </reg>
      <reg name="tx_apf_num_b3" protect="rw">
        <bits access="rw" name="num_coe_b3" pos="13:0" rst="2273">
          <comment>tx polar modulation apf num coe</comment>
        </bits>
      </reg>
      <reg name="tx_apf_num_b4" protect="rw">
        <bits access="rw" name="num_coe_b4" pos="13:0" rst="4096">
          <comment>tx polar modulation apf num coe</comment>
        </bits>
      </reg>
      <reg name="tx_apf_den_a2" protect="rw">
        <bits access="rw" name="den_coe_a2" pos="13:0" rst="2273">
          <comment>tx polar modulation apf den coe-2.14</comment>
        </bits>
      </reg>
      <reg name="tx_apf_den_a3" protect="rw">
        <bits access="rw" name="den_coe_a3" pos="13:0" rst="2273">
          <comment>tx polar modulation apf den coe</comment>
        </bits>
      </reg>
      <reg name="tx_apf_den_a4" protect="rw">
        <bits access="rw" name="den_coe_a4" pos="13:0" rst="2273">
          <comment>tx polar modulation apf den coe</comment>
        </bits>
      </reg>
      <reg name="adapt_edr3_cci" protect="rw">
        <bits access="rw" name="ct_u_errsum" pos="15:13" rst="4">
          <comment>ErrSum beta coef
3'h0:: 1div2
3'h1:: 1div4
3'h2:: 1div8
3'h3:: 1div16
3'h4:: 1div32
3'h5:: 1div64</comment>
        </bits>
        <bits access="rw" name="ct_u_dpsk2" pos="8:5" rst="8">
          <comment>third u_err of the dpsk 8/32</comment>
        </bits>
        <bits access="rw" name="ct_u_1_dpsk2" pos="4:0" rst="25">
          <comment>third u_dc of the dpsk 1/512</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_cache_ctrl.xml">
    <module category="wcn" name="WCN_CACHE_CTRL">
      <reg name="bus_cfg0" protect="rw">
        <bits access="rw" name="rf_blk_prot_en7" pos="23" rst="0">
          <comment>0: block7, protect disabled or access permitted
1: block7, protect enabled or access forbidden</comment>
        </bits>
        <bits access="rw" name="rf_blk_prot_en6" pos="22" rst="0">
          <comment>0: block6, protect disabled or access permitted
1: block6, protect enabled or access forbidden</comment>
        </bits>
        <bits access="rw" name="rf_blk_prot_en5" pos="21" rst="0">
          <comment>0: block5, protect disabled or access permitted
1: block5, protect enabled or access forbidden</comment>
        </bits>
        <bits access="rw" name="rf_blk_prot_en4" pos="20" rst="0">
          <comment>0: block4, protect disabled or access permitted
1: block4, protect enabled or access forbidden</comment>
        </bits>
        <bits access="rw" name="rf_blk_prot_en3" pos="19" rst="0">
          <comment>0: block3, protect disabled or access permitted
1: block3, protect enabled or access forbidden</comment>
        </bits>
        <bits access="rw" name="rf_blk_prot_en2" pos="18" rst="0">
          <comment>0: block2, protect disabled or access permitted
1: block2, protect enabled or access forbidden</comment>
        </bits>
        <bits access="rw" name="rf_blk_prot_en1" pos="17" rst="0">
          <comment>0: block1, protect disabled or access permitted
1: block1, protect enabled or access forbidden</comment>
        </bits>
        <bits access="rw" name="rf_blk_prot_en0" pos="16" rst="0">
          <comment>0: block0, protect disabled or access permitted
1: block0, protect enabled or access forbidden</comment>
        </bits>
        <bits access="rw" name="rf_blk_remap_en7" pos="15" rst="0">
          <comment>0: block7, cache remap disabled
1: block7, cache remap enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_remap_en6" pos="14" rst="0">
          <comment>0: block6, cache remap disabled
1: block6, cache remap enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_remap_en5" pos="13" rst="0">
          <comment>0: block5, cache remap disabled
1: block5, cache remap enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_remap_en4" pos="12" rst="0">
          <comment>0: block4, cache remap disabled
1: block4, cache remap enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_remap_en3" pos="11" rst="0">
          <comment>0: block3, cache remap disabled
1: block3, cache remap enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_remap_en2" pos="10" rst="0">
          <comment>0: block2, cache remap disabled
1: block2, cache remap enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_remap_en1" pos="9" rst="0">
          <comment>0: block1, cache remap disabled
1: block1, cache remap enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_remap_en0" pos="8" rst="0">
          <comment>0: block0, cache remap disabled
1: block0, cache remap enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_cache_en7" pos="7" rst="0">
          <comment>0: block7, cache disabled
1: block7, cache enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_cache_en6" pos="6" rst="0">
          <comment>0: block6, cache disabled
1: block6, cache enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_cache_en5" pos="5" rst="0">
          <comment>0: block5, cache disabled
1: block5, cache enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_cache_en4" pos="4" rst="0">
          <comment>0: block4, cache disabled
1: block4, cache enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_cache_en3" pos="3" rst="0">
          <comment>0: block3, cache disabled
1: block3, cache enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_cache_en2" pos="2" rst="0">
          <comment>0: block2, cache disabled
1: block2, cache enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_cache_en1" pos="1" rst="0">
          <comment>0: block1, cache disabled
1: block1, cache enabled</comment>
        </bits>
        <bits access="rw" name="rf_blk_cache_en0" pos="0" rst="0">
          <comment>0: block0, cache disabled
1: block0, cache enabled</comment>
        </bits>
      </reg>
      <reg name="bus_cfg1" protect="rw">
        <bits access="rw" name="rf_blk_base_addr1" pos="27:12" rst="0">
          <comment>block 1 start address</comment>
        </bits>
      </reg>
      <reg name="bus_cfg2" protect="rw">
        <bits access="rw" name="rf_blk_base_addr2" pos="27:12" rst="0">
          <comment>block 2 start address</comment>
        </bits>
      </reg>
      <reg name="bus_cfg3" protect="rw">
        <bits access="rw" name="rf_blk_base_addr3" pos="27:12" rst="0">
          <comment>block 3 start address</comment>
        </bits>
      </reg>
      <reg name="bus_cfg4" protect="rw">
        <bits access="rw" name="rf_blk_base_addr4" pos="27:12" rst="0">
          <comment>block 4 start address</comment>
        </bits>
      </reg>
      <reg name="bus_cfg5" protect="rw">
        <bits access="rw" name="rf_blk_base_addr5" pos="27:12" rst="0">
          <comment>block 5 start address</comment>
        </bits>
      </reg>
      <reg name="bus_cfg6" protect="rw">
        <bits access="rw" name="rf_blk_base_addr6" pos="27:12" rst="0">
          <comment>block 6 start address</comment>
        </bits>
      </reg>
      <reg name="bus_cfg7" protect="rw">
        <bits access="rw" name="rf_blk_base_addr7" pos="27:12" rst="0">
          <comment>block 7 start address</comment>
        </bits>
      </reg>
      <reg name="bus_remap0" protect="rw">
        <bits access="rw" name="rf_blk0_remap_offset0" pos="31:12" rst="0">
          <comment>block 0 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk0_remap_offset</comment>
        </bits>
      </reg>
      <reg name="bus_remap1" protect="rw">
        <bits access="rw" name="rf_blk1_remap_offset1" pos="31:12" rst="0">
          <comment>block 1 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk1_remap_offset</comment>
        </bits>
      </reg>
      <reg name="bus_remap2" protect="rw">
        <bits access="rw" name="rf_blk2_remap_offset2" pos="31:12" rst="0">
          <comment>block 2 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk2_remap_offset</comment>
        </bits>
      </reg>
      <reg name="bus_remap3" protect="rw">
        <bits access="rw" name="rf_blk3_remap_offset3" pos="31:12" rst="0">
          <comment>block 3 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk3_remap_offset</comment>
        </bits>
      </reg>
      <reg name="bus_remap4" protect="rw">
        <bits access="rw" name="rf_blk4_remap_offset4" pos="31:12" rst="0">
          <comment>block 4 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk4_remap_offset</comment>
        </bits>
      </reg>
      <reg name="bus_remap5" protect="rw">
        <bits access="rw" name="rf_blk5_remap_offset5" pos="31:12" rst="0">
          <comment>block 5 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk5_remap_offset</comment>
        </bits>
      </reg>
      <reg name="bus_remap6" protect="rw">
        <bits access="rw" name="rf_blk6_remap_offset6" pos="31:12" rst="0">
          <comment>block 6 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk6_remap_offset</comment>
        </bits>
      </reg>
      <reg name="bus_remap7" protect="rw">
        <bits access="rw" name="rf_blk7_remap_offset7" pos="31:12" rst="0">
          <comment>block 7 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk7_remap_offset</comment>
        </bits>
      </reg>
      <reg name="cache_cfg0" protect="rw">
        <bits access="rw" name="rf_debug_en" pos="31" rst="0">
          <comment>cache debug mode enable:
0: normal mode
1: debug mode
This bit MUST always be cleared during cache operating</comment>
        </bits>
        <bits access="rw" name="rf_cmd_exec_mode" pos="30" rst="0">
          <comment>0: (recommended) software can run in cacheable region during software command processing
1: software cannot run in cacheable region during software command processing</comment>
        </bits>
        <bits access="rw" name="rf_cache_size_sel" pos="29:28" rst="0">
          <comment>cache size selection:
0: 4K Byte
1: 8K Byte
2: 16K Byte
3: 32K Byte</comment>
        </bits>
        <bits access="rw" name="rf_hprot_cache_reg" pos="13:10" rst="11">
          <comment>hprot control register which provide 4bit hprot for cache ctrl AHB?</comment>
        </bits>
        <bits access="rw" name="rf_hprot_bus_reg" pos="9:6" rst="3">
          <comment>hprot control register which provide 4bit hprot for cache bus AHB</comment>
        </bits>
        <bits access="rw" name="rf_hprot_byp" pos="5:2" rst="0">
          <comment>Bit [5]:
1b1: hprot[3] from CM4 go through cache controller without modification
1b0: hprot[3] is provided by cache controller register
Bit [4]:
1b1: hprot[2] from CM4 go through cache controller without modification
1b0: hprot[2] is provided by cache controller register
Bit [3]:
1b1: hprot[1] from CM4 go through cache controller without modification
1b0: hprot[1] is provided by cache controller register
Bit [2]:
1b1: hprot[0] from CM4 go through cache controller without modification
1b0: hprot[0] is provided by cache controller register</comment>
        </bits>
        <bits access="rw" name="rf_write_mode" pos="1:0" rst="0">
          <comment>cache write operation mode
2b00: write through
2b01: write back, no write allocate
2b10: write back, write allocate</comment>
        </bits>
      </reg>
      <reg name="bus_sts0" protect="r">
        <bits access="r" name="rf_prot_detect_addr" pos="27:0" rst="0">
          <comment>trigging address for protect block?</comment>
        </bits>
      </reg>
      <reg name="cache_sts0" protect="r">
        <bits access="r" name="rf_write_ongoing" pos="7" rst="0">
          <comment>rf_write_ongoing, this is a status register for write through mode to avoid potential coherence issue.
1b1: the cache is still doing AHB write transaction to the main memory and the data is not written into the main memory.
1b0: the cache has finished AHB write transaction and the data is written into the main memory.</comment>
        </bits>
        <bits access="r" name="rf_cmd_st" pos="6:4" rst="0">
          <comment>rf_cmd_st</comment>
        </bits>
        <bits access="r" name="rf_cache_st" pos="3:0" rst="0">
          <comment>rf_cache_st</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="cmd_cfg0" protect="rw">
        <bits access="rw" name="rf_cmd_str_addr" pos="27:0" rst="0">
          <comment>cmd_all : not used
cmd_range : start address
cmd_entry : entry address</comment>
        </bits>
      </reg>
      <reg name="cmd_cfg1" protect="rw">
        <bits access="rw" name="rf_cmd_end_addr" pos="27:0" rst="0">
          <comment>cmd_all : not used
cmd_range : start address
cmd_entry : entry address</comment>
        </bits>
      </reg>
      <reg name="cmd_cfg2" protect="rw">
        <bits access="w" name="rf_cmd_str" pos="31" rst="0">
          <comment>software command start:
write 1 to this bit to issue one command</comment>
        </bits>
        <bits access="rw" name="rf_cmd_type" pos="5:0" rst="0">
          <comment>software command type:
6h0 : clean all
6h1 : clean range
6h2 : clean entry
6h3 : reserved
6h4 : invalid all
6h5 : invalid range
6h6 : invalid entry
6h7 : reserved
6h8 : clean and invalid all
6h9 : clean and invalid range
6hA : clean and invalid entry
6hB : reserved</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="int_en" protect="rw">
        <bits access="rw" name="rf_prot_irq_en" pos="1" rst="0">
          <comment>interrupt enable for protect block trigging?</comment>
        </bits>
        <bits access="rw" name="rf_cmd_irq_en" pos="0" rst="0">
          <comment>interrupt enable for software command done</comment>
        </bits>
      </reg>
      <reg name="int_raw" protect="r">
        <bits access="r" name="rf_prot_irq_raw" pos="1" rst="0">
          <comment>interrupt raw status for protect block trigging</comment>
        </bits>
        <bits access="r" name="rf_cmd_irq_raw" pos="0" rst="0">
          <comment>interrupt raw status for software command done?</comment>
        </bits>
      </reg>
      <reg name="int_mask" protect="r">
        <bits access="r" name="rf_prot_irq_mask" pos="1" rst="0">
          <comment>interrupt masked status for protect block trigging</comment>
        </bits>
        <bits access="r" name="rf_cmd_irq_mask" pos="0" rst="0">
          <comment>interrupt masked status for software command done?</comment>
        </bits>
      </reg>
      <reg name="int_clr" protect="rw">
        <bits access="w" name="rf_prot_irq_clr" pos="1" rst="0">
          <comment>interrupt clear for protect block trigging</comment>
        </bits>
        <bits access="w" name="rf_cmd_irq_clr" pos="0" rst="0">
          <comment>interrupt clear for software command done?</comment>
        </bits>
      </reg>
      <reg name="cache_write_hit_cnt" protect="r">
        <bits access="r" name="rf_write_hit_cnt" pos="31:0" rst="0">
          <comment>Cache write hit times. When cache write hit, the counter value increment by 1</comment>
        </bits>
      </reg>
      <reg name="cache_write_miss_cnt" protect="rw">
        <bits access="w" name="rf_write_cnt_clr" pos="31" rst="0">
          <comment>clear write counter values to zero?</comment>
        </bits>
        <bits access="rw" name="rf_write_cnt_run" pos="30" rst="0">
          <comment>1: write hit/miss counter will run
0: write hit/miss counter will stop</comment>
        </bits>
        <bits access="r" name="rf_write_miss_cnt" pos="29:0" rst="0">
          <comment>Cache write hit times. When cache write hit, the counter value increment by 1</comment>
        </bits>
      </reg>
      <reg name="cache_read_hit_cnt" protect="r">
        <bits access="r" name="rf_read_hit_cnt" pos="31:0" rst="0">
          <comment>Cache read hit times. When cache read hit, the counter value increment by 1?</comment>
        </bits>
      </reg>
      <reg name="cache_read_miss_cnt" protect="rw">
        <bits access="w" name="rf_read_cnt_clr" pos="31" rst="0">
          <comment>clear read counter values to zero?</comment>
        </bits>
        <bits access="rw" name="rf_read_cnt_run" pos="30" rst="0">
          <comment>1: read hit/miss counter will run
0: read hit/miss counter will stop</comment>
        </bits>
        <bits access="r" name="rf_read_miss_cnt" pos="29:0" rst="0">
          <comment>Cache read miss times. When cache read miss, the counter value increment by 1</comment>
        </bits>
      </reg>
      <reg name="cache_hact_cnt" protect="r">
        <bits access="r" name="rf_hact_cnt" pos="31:0" rst="0">
          <comment>Cache master AHB active cycles in total. When master AHB is active (hsel and htrans[1]), the counter value increment by 1?</comment>
        </bits>
      </reg>
      <reg name="cache_hrdy_cnt" protect="rw">
        <bits access="w" name="rf_hact_hrdy_clr" pos="31" rst="0">
          <comment>clear HACT and HRDY counter values to zero</comment>
        </bits>
        <bits access="rw" name="rf_hact_hrdy_run" pos="30" rst="0">
          <comment>1: HACT and HRDY counters will run
0: HACT and HRDY counters will stop</comment>
        </bits>
        <bits access="r" name="rf_hrdys_cnt" pos="29:0" rst="0">
          <comment>The HRDY counter counts the valid cycles of HREADY signal from the cache controller to the master when the master AHB is active. When HREADY signal to the master is high and the master AHB is active, the counter value increment by 1?</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_comregs.xml">
    <module category="wcn" name="WCN_COMREGS">
      <reg name="snapshot" protect="r">
        <bits access="r" name="snapshot" pos="1:0" rst="0">
          <comment>Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg</comment>
        </bits>
      </reg>
      <reg name="snapshot_cfg" protect="rw">
        <bits access="r" name="snapshot_cfg_rd" pos="1" rst="0">
      </bits>
        <bits access="rw" name="snapshot_cfg" pos="0" rst="0">
          <comment>number of snapshot</comment>
        </bits>
      </reg>
      <reg name="cause" protect="r">
        <bits access="r" name="irq1_cause" pos="15:8" rst="0">
          <comment>When read from the Xcpu, this return the cause of interruption, basically the set/clear register X_Irq1 part masked with X_Irq1_Mask
When read from the Bcpu, this return the cause of interruption, basically the set/clear register Irq1 part masked with Irq1_Mask</comment>
        </bits>
        <bits access="r" name="irq0_cause" pos="7:0" rst="0">
          <comment>When read from the Xcpu, this return the cause of interruption, basically the set/clear register Irq0 part masked with Irq0_Mask
When read from the Bcpu, this return the cause of interruption, basically the set/clear register Irq1 part masked with Irq1_Mask</comment>
        </bits>
      </reg>
      <reg name="mask_set" protect="rw">
        <bits access="r" name="irq1_mask_set" pos="15:8" rst="0">
          <comment>bit type is changed from rs to r.
          When read: returns the value of the Irq1_Mask register.
                When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged.
                The Irq1_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0</comment>
        </bits>
        <bits access="r" name="irq0_mask_set" pos="7:0" rst="0">
          <comment>bit type is changed from rs to r.
          When read: returns the value of the Irq0_Mask register.
                When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged.
                The Irq0_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0</comment>
        </bits>
      </reg>
      <reg name="mask_clr" protect="rw">
        <bits access="r" name="irq1_mask_clr" pos="15:8" rst="0">
          <comment>bit type is changed from rc to r.
          When read: returns the value of the Irq1_Mask register.
                When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged.
                The Irq1_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 1</comment>
        </bits>
        <bits access="r" name="irq0_mask_clr" pos="7:0" rst="0">
          <comment>bit type is changed from rc to r.
          When read: returns the value of the Irq0_Mask register.
                When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged.
                The Irq0_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0</comment>
        </bits>
      </reg>
      <reg name="itreg_set" protect="rw">
        <bits access="r" name="irq1_set" pos="15:8" rst="0">
          <comment>bit type is changed from rs to r.
          When read, returns the value of the set/clear register.
                When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                These bits can also trigger interrupts on the XCPU/BCPU if enabled</comment>
        </bits>
        <bits access="r" name="irq0_set" pos="7:0" rst="0">
          <comment>bit type is changed from rs to r.
          When read, returns the value of the set/clear register.
                When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                These bits can also trigger interrupts on the XCPU/BCPU if enabled.</comment>
        </bits>
      </reg>
      <reg name="itreg_clr" protect="rw">
        <bits access="r" name="irq1_clr" pos="15:8" rst="0">
          <comment>bit type is changed from rc to r.
          When read, returns the value of the set/clear register.
                When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                These bits can also trigger interrupts on the XCPU/BCPU if enabled.</comment>
        </bits>
        <bits access="r" name="irq0_clr" pos="7:0" rst="0">
          <comment>bit type is changed from rc to r.
          When read, returns the value of the set/clear register.
                When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged.
                These bits can also trigger interrupts on the XCPU/BCPU if enabled</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_dbm.xml">
    <module category="wcn" name="WCN_DBM">
      <reg name="sel" protect="rw">
        <bits access="rw" name="dbm_en" pos="0" rst="0">
          <comment>debug bus master enable</comment>
        </bits>
      </reg>
      <reg name="trans" protect="rw">
        <bits access="rw" name="word_len" pos="31:12" rst="0">
          <comment>transfer word length</comment>
        </bits>
        <bits access="rw" name="data_sel" pos="11:8" rst="0">
          <comment>data selection</comment>
        </bits>
        <bits access="rw" name="dump_trig_sel" pos="7" rst="0">
          <comment>dump trigger selection
select trigger from soft or hardware</comment>
        </bits>
        <bits access="rw" name="wrap_en" pos="6" rst="0">
          <comment>wrap the whole fifo, when EOF, keep on write by the start addr</comment>
        </bits>
        <bits access="rw" name="burst_type" pos="5:4" rst="0">
          <comment>burst type
2'b00:: single
2'b01:: incr4
2'b10:: incr8
2'b11:: incrx</comment>
        </bits>
        <bits access="rw" name="burst_len" pos="3:0" rst="0">
          <comment>length of burst when incrx
max incr16</comment>
        </bits>
      </reg>
      <reg name="start_addr" protect="rw">
        <bits access="rw" name="start_addr" pos="31:0" rst="0">
          <comment>start address of transfer</comment>
        </bits>
      </reg>
      <reg name="mask" protect="rw">
        <bits access="rw" name="mask_trans_err" pos="3" rst="0">
          <comment>mask for transfer error</comment>
        </bits>
        <bits access="rw" name="mask_ovfl" pos="2" rst="0">
          <comment>mask for ovfl</comment>
        </bits>
        <bits access="rw" name="mask_comp_half" pos="1" rst="0">
          <comment>mask for comp half</comment>
        </bits>
        <bits access="rw" name="mask_comp_end" pos="0" rst="0">
          <comment>mask for comp end</comment>
        </bits>
      </reg>
      <reg name="status" protect="rw">
        <bits access="rc" name="int_trans_err_status" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.
          interrupt for ahb transfer error</comment>
        </bits>
        <bits access="rc" name="int_ovfl_status" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          interrupt from fifo overfolw</comment>
        </bits>
        <bits access="rc" name="int_comp_half_status" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          half interrupt from transfer complete</comment>
        </bits>
        <bits access="rc" name="int_comp_end_status" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          end interrupt from transfer complete</comment>
        </bits>
        <bits access="rc" name="srst_done_status" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          data_packer soft reset done</comment>
        </bits>
      </reg>
      <reg name="soft_reset" protect="rw">
        <bits access="s" name="s_reset" pos="0" rst="0">
          <comment>bit type is changed from wos to s.
          soft reset</comment>
        </bits>
      </reg>
      <reg name="soft_trig" protect="rw">
        <bits access="s" name="s_dp_trig" pos="0" rst="0">
          <comment>bit type is changed from wos to s.
          dump trigger from soft</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_fm_dsp.xml">
    <module category="wcn" name="WCN_FM_DSP">
      <reg name="tx_fifo_rdata" protect="r">
        <bits access="r" name="tx_data_i" pos="31:16" rst="0">
          <comment>TX data I. Everytime this register is read, the data will be popped out of the tx_data_fifo.</comment>
        </bits>
        <bits access="r" name="tx_data_q" pos="15:0" rst="0">
          <comment>TX data Q. Everytime this register is read, the data will be popped out of the tx_data_fifo.</comment>
        </bits>
      </reg>
      <reg name="revision" protect="r">
        <bits access="r" name="rev_id" pos="3:0" rst="4">
          <comment>revision id.</comment>
        </bits>
      </reg>
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="dbg_out_en" pos="28" rst="1">
          <comment>debug output enable.</comment>
        </bits>
        <bits access="rw" name="adc_data_format" pos="27" rst="1">
          <comment>1'd0:: unsigned
1'd1:: 2s_complementary</comment>
        </bits>
        <bits access="rw" name="force_clk_on" pos="26" rst="1">
          <comment>force clock on.</comment>
        </bits>
        <bits access="rw" name="tx_en" pos="25" rst="1">
          <comment>tx data enable.
1'd0:: disable
1'd1:: enable</comment>
        </bits>
        <bits access="rw" name="i2s_delay_1t" pos="24" rst="1">
          <comment>i2s delay 1t enable.</comment>
        </bits>
        <bits access="rw" name="i2s_en" pos="23" rst="1">
          <comment>i2s enable.
1'd0:: disable
1'd1:: enable</comment>
        </bits>
        <bits access="rw" name="fmdem_src_sel" pos="22" rst="1">
          <comment>coherent fmdemsource selection.
1'd0:: output_lpfil
1'd1:: output_dig_gain</comment>
        </bits>
        <bits access="rw" name="seek_offset_src_sel" pos="21" rst="1">
          <comment>offset source selection.
1'd0:: output_afc
1'd1:: output_offset_filter</comment>
        </bits>
        <bits access="rw" name="seek_rssi_src_sel" pos="20" rst="1">
          <comment>rssi source during seek seelction.
1'd0:: rssi_db1
1'd1:: signal_db1</comment>
        </bits>
        <bits access="rw" name="noise_cancel_src_sel" pos="19" rst="1">
          <comment>noise cancel source source selection.
1'd0:: noise_db2
1'd1:: rssi_db2</comment>
        </bits>
        <bits access="rw" name="noise_src_sel" pos="18:17" rst="2">
          <comment>noise source selection.
2'd0:: dangle0
2'd1:: dangle1
2'd2:: dangle 2</comment>
        </bits>
        <bits access="rw" name="adc_clk_invert" pos="16" rst="1">
          <comment>adc clock invert.</comment>
        </bits>
        <bits access="rw" name="pilot_cosine" pos="15" rst="1">
          <comment>pilot phase.
1'd0:: sin
1'd1:: cos</comment>
        </bits>
        <bits access="rw" name="deemph_bypass" pos="14" rst="1">
          <comment>bypass deemphasis.</comment>
        </bits>
        <bits access="rw" name="lpf_bypass" pos="13" rst="1">
          <comment>bypass 15KHz LPF.</comment>
        </bits>
        <bits access="rw" name="fircut_bypass_sk" pos="12" rst="1">
          <comment>bypass fircut during seeking.</comment>
        </bits>
        <bits access="rw" name="fircut_bypass" pos="11" rst="1">
          <comment>bypass fircut.</comment>
        </bits>
        <bits access="rw" name="lr_swap" pos="10" rst="1">
          <comment>LR swap.</comment>
        </bits>
        <bits access="rw" name="plldem_swap" pos="9" rst="1">
          <comment>IQ swap for fmdem.</comment>
        </bits>
        <bits access="rw" name="iq_swap" pos="8" rst="1">
          <comment>IQ swap after 125KHz mixer.</comment>
        </bits>
        <bits access="rw" name="imgrej_dsp" pos="7" rst="1">
          <comment>IQ swap before 125KHz mixer.</comment>
        </bits>
        <bits access="rw" name="imgrej" pos="6" rst="1">
          <comment>lo selection.
1'd0:: low
low if; Default is +125KHz.
1'd1:: high
high if. Default is -125KHz</comment>
        </bits>
        <bits access="rw" name="afc_disable" pos="5" rst="1">
          <comment>AFC disable.
1'd0:: enable
1'd1:: disable</comment>
        </bits>
        <bits access="rw" name="softblend_off" pos="4" rst="1">
          <comment>soft blend off.
1'd0:: enable
1'd1:: disable</comment>
        </bits>
        <bits access="rw" name="softmute_en" pos="3" rst="1">
          <comment>soft mute enable.
1'd0:: disable
1'd1:: enable</comment>
        </bits>
        <bits access="rw" name="deemph_mode" pos="2" rst="1">
          <comment>de-emphasis.
1'd0:: 75us
1'd1:: 50us</comment>
        </bits>
        <bits access="rw" name="stereo_in" pos="1" rst="1">
          <comment>mono select.
1'd0:: force : mono
1'd1:: stereo</comment>
        </bits>
        <bits access="rw" name="mute" pos="0" rst="1">
          <comment>mute.
1'd0:: normal
1'd1:: mute</comment>
        </bits>
      </reg>
      <reg name="tx_ctrl" protect="rw">
        <bits access="r" name="tx_fifo_usedw" pos="10:8" rst="3">
          <comment>the number of data words in tx fifowhich are valid for read.</comment>
        </bits>
        <bits access="r" name="tx_fifo_underflow" pos="7" rst="1">
          <comment>tx fifo underflow. User reads tx_fifo_rdata while no data valid in it.</comment>
        </bits>
        <bits access="r" name="tx_fifo_overflow" pos="6" rst="1">
          <comment>tx fifo overflow. User is not able to read tx_fifo_rdata in time so that fm_dsp discard valid data.</comment>
        </bits>
        <bits access="rw" name="tx_fifo_clr" pos="5" rst="1">
          <comment>clear tx fifo.</comment>
        </bits>
        <bits access="rw" name="tx_sel" pos="4:0" rst="5">
          <comment>tx data selection.</comment>
        </bits>
      </reg>
      <reg name="seek_ctrl0" protect="rw">
        <bits access="rw" name="snr_cnt_th" pos="29:26" rst="4">
          <comment>SNR counter threshold.</comment>
        </bits>
        <bits access="rw" name="delta_rssi_th" pos="25:20" rst="12">
          <comment>delta rssi threshold during UPPER/LOWER seeking. Unit is db.</comment>
        </bits>
        <bits access="rw" name="snr_th" pos="19:14" rst="6">
          <comment>threshold for SNR. Unit is db.</comment>
        </bits>
        <bits access="rw" name="seek_range" pos="13:9" rst="5">
          <comment>seek upper/lower adjacent freq setting. Unit is 5.12KHz.</comment>
        </bits>
        <bits access="rw" name="seek_afc_on" pos="8" rst="1">
          <comment>1'd0:: disable
disable afc during seeking;
1'd1:: enable
enable afc during seeking.</comment>
        </bits>
        <bits access="rw" name="seek_mode" pos="7:5" rst="0">
          <comment>seek mode.
3'd0:: seek_current_only
3'd1:: seek_current_or_adjacent
success when either current or adjacent freq is successful;
3'd2:: seek_current_and_adjacent
success when both current and adjacent freq are successful;
3'd3:: snr_st
test mode. stop at SNR_ST;
3'd4:: center_st
test mode. stop at CENTER_ST;
3'd5:: upper_st
test mode. stop at UPPER_ST;
3'd6:: lower_st
testmode. stop at LOWER_ST;
3'd7:: seek_bypass</comment>
        </bits>
        <bits access="rw" name="sk_cmp_grp_en" pos="4:0" rst="27">
          <comment>1'd0: disable
1'd1: enable
[4]: seek with  pilot;
[3]: seek with offset;
[2]: seek with snr;
[1]: seek with rssi;
[0]: seek with noise.</comment>
        </bits>
      </reg>
      <reg name="seek_ctrl1" protect="rw">
        <bits access="rw" name="pilot_cnt_th" pos="31:24" rst="0">
          <comment>pilot counter threshold.</comment>
        </bits>
        <bits access="rw" name="rssi_cnt_th" pos="23:16" rst="0">
          <comment>rssi counter threshold.</comment>
        </bits>
        <bits access="rw" name="noise_cnt_th" pos="15:8" rst="0">
          <comment>noise counter threshold.</comment>
        </bits>
        <bits access="rw" name="offset_cnt_th" pos="7:0" rst="0">
          <comment>offset counter threshold.</comment>
        </bits>
      </reg>
      <reg name="seek_ctrl2" protect="rw">
        <bits access="rw" name="noise_l_th" pos="27:21" rst="7">
          <comment>noise low threshold. Unit is db.</comment>
        </bits>
        <bits access="rw" name="noise_h_th" pos="20:14" rst="7">
          <comment>noise high threshold. Unit is db.</comment>
        </bits>
        <bits access="rw" name="rssi_l_th" pos="13:7" rst="7">
          <comment>RSSI low threshold. Unit is db.</comment>
        </bits>
        <bits access="rw" name="rssi_h_th" pos="6:0" rst="7">
          <comment>RSSI high threshold. Unit is db.</comment>
        </bits>
      </reg>
      <reg name="seek_ctrl3" protect="rw">
        <bits access="rw" name="offset_l_th" pos="27:21" rst="7">
          <comment>offset low threshold. Unit is db.</comment>
        </bits>
        <bits access="rw" name="offset_h_th" pos="20:14" rst="7">
          <comment>offset high threshold. Unit is db.</comment>
        </bits>
        <bits access="rw" name="pilot_l_th" pos="13:7" rst="7">
          <comment>pilot low threshold. Unit is db.</comment>
        </bits>
        <bits access="rw" name="pilot_h_th" pos="6:0" rst="7">
          <comment>pilot high threshold. Unit is db.</comment>
        </bits>
      </reg>
      <reg name="seek_ctrl4" protect="rw">
        <bits access="rw" name="sk_timer4" pos="21:16" rst="6">
          <comment>seek time for SNR detect. Unit is 0.75ms.</comment>
        </bits>
        <bits access="rw" name="sk_timer3" pos="15:10" rst="6">
          <comment>seek time for upper/lower adjacent freq. Unit is 0.75ms.</comment>
        </bits>
        <bits access="rw" name="sk_timer2" pos="9:4" rst="6">
          <comment>seek time for current freq. Unit is 0.75ms.</comment>
        </bits>
        <bits access="rw" name="sk_timer1" pos="3:0" rst="4">
          <comment>seek time for agc/afc stable. Unit is 0.75ms.</comment>
        </bits>
      </reg>
      <reg name="afc_ctrl" protect="rw">
        <bits access="rw" name="afc_ct_sk" pos="18:13" rst="6">
          <comment>[5:3]: afc dc filter bandwidth setting during seeking.
[2:0]: afc acc step setting during seeking.</comment>
        </bits>
        <bits access="rw" name="afc_ct" pos="12:7" rst="6">
          <comment>[5:3]: afc dc filter bandwidth setting during seek is ready.
[2:0]: afc acc step setting during seek is ready.</comment>
        </bits>
        <bits access="rw" name="afc_range" pos="6:1" rst="6">
          <comment>afc following range. Unit is 2.5KHz.</comment>
        </bits>
        <bits access="rw" name="afc_inv" pos="0" rst="1">
          <comment>inverse afc adjust value.</comment>
        </bits>
      </reg>
      <reg name="agc_ctrl0" protect="rw">
        <bits access="rw" name="agc_target_pwr" pos="30:25" rst="6">
          <comment>agc target power. Unit is 2db.</comment>
        </bits>
        <bits access="rw" name="agc_test" pos="24" rst="1">
          <comment>agc test mode. Fix gain.</comment>
        </bits>
        <bits access="rw" name="agc_loop_gain1" pos="23:21" rst="3">
          <comment>agc loop gain during normal.</comment>
        </bits>
        <bits access="rw" name="agc_loop_gain0" pos="20:18" rst="3">
          <comment>agc loop gian during seeking.</comment>
        </bits>
        <bits access="rw" name="agc_update1" pos="17:15" rst="3">
          <comment>agc update time during normal.</comment>
        </bits>
        <bits access="rw" name="agc_update0" pos="14:12" rst="3">
          <comment>agc update time during seeking.</comment>
        </bits>
        <bits access="rw" name="agc_thd" pos="11:7" rst="5">
          <comment>agc digital gain threshold. Unit is 2db.</comment>
        </bits>
        <bits access="rw" name="agc_index_in" pos="6:3" rst="4">
          <comment>agc initial index.</comment>
        </bits>
        <bits access="rw" name="ct_endelay" pos="2:0" rst="3">
          <comment>agc enable delay time after reset.
3'd0:: 0 : 0.375us
3'd1:: 1 : 3us
3'd2:: 2 : 6us
3'd3:: 3 : 9.74us
3'd4:: 4 : 13.875us
3'd5:: 5 : 18us
3'd6:: 6 : 21us
3'd7: 7 : 24us</comment>
        </bits>
      </reg>
      <reg name="agc_ctrl1" protect="rw">
        <bits access="rw" name="dig_gain_in" pos="19:15" rst="5">
          <comment>basic dig gain. Unit is db.</comment>
        </bits>
        <bits access="rw" name="agc_ct_u" pos="14:13" rst="2">
          <comment>agc IIR bandwidth.</comment>
        </bits>
        <bits access="rw" name="over_step" pos="12:7" rst="6">
          <comment>[5:3]: agc loop sub step when sinc_over or log_agc&gt;log_agc_th
[2:0]: agc loop sub step when acc I saturation.</comment>
        </bits>
        <bits access="rw" name="log_agc_th" pos="6:1" rst="6">
          <comment>threshold for agc lopp adjust. Unit is 1db.</comment>
        </bits>
        <bits access="rw" name="log_over_sel" pos="0" rst="1">
          <comment>if 1, adjust agc_index sub step when log_agc&gt;log_agc_th</comment>
        </bits>
      </reg>
      <reg name="ana_gain_rssi_tb0" protect="rw">
        <bits access="rw" name="ana_gain_rssi_3" pos="31:24" rst="0">
          <comment>ana gain rssi for agc_index=3</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_2" pos="23:16" rst="0">
          <comment>ana gain rssi for agc_index=2</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_1" pos="15:8" rst="0">
          <comment>ana gain rssi for agc_index=1</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_0" pos="7:0" rst="0">
          <comment>ana gain rssi for agc_index=0</comment>
        </bits>
      </reg>
      <reg name="ana_gain_rssi_tb1" protect="rw">
        <bits access="rw" name="ana_gain_rssi_7" pos="31:24" rst="0">
          <comment>ana gain rssi for agc_index=7</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_6" pos="23:16" rst="0">
          <comment>ana gain rssi for agc_index=6</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_5" pos="15:8" rst="0">
          <comment>ana gain rssi for agc_index=5</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_4" pos="7:0" rst="0">
          <comment>ana gain rssi for agc_index=4</comment>
        </bits>
      </reg>
      <reg name="ana_gain_rssi_tb2" protect="rw">
        <bits access="rw" name="ana_gain_rssi_b" pos="31:24" rst="0">
          <comment>ana gain rssi for agc_index=b</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_a" pos="23:16" rst="0">
          <comment>ana gain rssi for agc_index=a</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_9" pos="15:8" rst="0">
          <comment>ana gain rssi for agc_index=9</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_8" pos="7:0" rst="0">
          <comment>ana gain rssi for agc_index=8</comment>
        </bits>
      </reg>
      <reg name="ana_gain_rssi_tb3" protect="rw">
        <bits access="rw" name="ana_gain_rssi_f" pos="31:24" rst="0">
          <comment>ana gain rssi for agc_index=f</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_e" pos="23:16" rst="0">
          <comment>ana gain rssi for agc_index=e</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_d" pos="15:8" rst="0">
          <comment>ana gain rssi for agc_index=d</comment>
        </bits>
        <bits access="rw" name="ana_gain_rssi_c" pos="7:0" rst="0">
          <comment>ana gain rssi for agc_index=c</comment>
        </bits>
      </reg>
      <reg name="noise_cancel_ctrl0" protect="rw">
        <bits access="rw" name="th_min_bw" pos="28:22" rst="7">
          <comment>fircut/gain38k change low threshold for RSSI. Unit is 1db.</comment>
        </bits>
        <bits access="rw" name="th_max_bw" pos="21:15" rst="7">
          <comment>fircut/gain38k change high threshold for RSSI. Unit is 1db.</comment>
        </bits>
        <bits access="rw" name="plldem_th_min" pos="14:9" rst="6">
          <comment>threshold. Unit is 2db.</comment>
        </bits>
        <bits access="rw" name="plldem_th_max" pos="8:3" rst="6">
          <comment>threshold. Unit is 2db.</comment>
        </bits>
        <bits access="rw" name="fmdem_sel_grp" pos="2:0" rst="3">
          <comment>1'd0: select cordic fmdem
1'd1: select dpll fmdem.
[2]: for seeing;
[1]: for nosie&lt;th_min;
[0]: for noise&gt;th_max.</comment>
        </bits>
      </reg>
      <reg name="noise_cancel_ctrl1" protect="rw">
        <bits access="rw" name="fircut_sel_force_on" pos="21" rst="1">
          <comment>fircut/gain38k change force on</comment>
        </bits>
        <bits access="rw" name="sel_fircut_sk" pos="20:15" rst="9">
          <comment>fircut bandwidth select during seeking UPPER/LOWER[2:0] and CENTER[5:3]. [40KHz:20KHz:180KHz]</comment>
        </bits>
        <bits access="rw" name="sel_fircut3" pos="14:12" rst="3">
          <comment>fircut bandwidth select during seeready and bad conditiong. Offset is over th. CENTER. [40KHz:20KHz:180KHz]</comment>
        </bits>
        <bits access="rw" name="sel_fircut2" pos="11:9" rst="3">
          <comment>fircut bandwidth select during seek ready and bad condition.  Offset is under th. [40KHz:20KHz:180KHz]</comment>
        </bits>
        <bits access="rw" name="sel_fircut1" pos="8:6" rst="3">
          <comment>fircut bandwidth select during seek ready and good condition. [40KHz:20KHz:180KHz]</comment>
        </bits>
        <bits access="rw" name="th_min_hcc" pos="5:0" rst="6">
          <comment>bandwidth threshold. Unit is 2db</comment>
        </bits>
      </reg>
      <reg name="noise_cancel_ctrl2" protect="rw">
        <bits access="rw" name="gain_38k2" pos="29:15" rst="20045">
          <comment>fircut bandwidth select during bad condition. [40KHz:20KHz:180KHz]</comment>
        </bits>
        <bits access="rw" name="gain_38k1" pos="14:0" rst="20045">
          <comment>bandwidth threshold. Unit is 2db</comment>
        </bits>
      </reg>
      <reg name="datapath_ctrl0" protect="rw">
        <bits access="rw" name="hbf1_bypass" pos="25" rst="1">
      </bits>
        <bits access="rw" name="hbf2_bypass" pos="24" rst="1">
      </bits>
        <bits access="rw" name="gainct" pos="23:15" rst="134">
          <comment>[8:6]: gain for mpx signal.
[5:0]: gain for stereo. [5:3]:6db;[2:1]:2db;[0]:1db.</comment>
        </bits>
        <bits access="rw" name="dig_delayct" pos="14:10" rst="5">
          <comment>dig gain change delay setting. Unit is 0.375us</comment>
        </bits>
        <bits access="rw" name="sinc_limit_gain" pos="9:8" rst="2">
          <comment>dig gain for signal before 125KHz mixer.
2'd0:: 0db
2'd1:: 6db
2'd2:: 12db
3'd3:: 18db</comment>
        </bits>
        <bits access="rw" name="over_th_sel" pos="7:5" rst="4">
          <comment>[2]: enable over threshold detection.
[1:0]: over threshold selection.
2'd0:: 0 : 0.75
2'd1:: 1 : 0.9
2'd2:: 2 : 0.95
2'd3:: 3 : 1</comment>
        </bits>
        <bits access="rw" name="limit_sel" pos="4" rst="1">
          <comment>1'd0: *0.75
1'd1: *1
for sinc_limit.</comment>
        </bits>
        <bits access="rw" name="dc_ct" pos="3:0" rst="11">
          <comment>dc cancel control.
[3]: dccancel mode. 1'd0: bypass; 1'd1: enable
[2:0]: bandwidth.</comment>
        </bits>
      </reg>
      <reg name="datapath_ctrl1" protect="rw">
        <bits access="rw" name="nco_ct_u_dt" pos="30:28" rst="3">
          <comment>19kHz tone detect bandwidthduring normal.</comment>
        </bits>
        <bits access="rw" name="nco_ct_u_dt_sk" pos="27:25" rst="3">
          <comment>19kHz tone detect bandwidth during seeking.</comment>
        </bits>
        <bits access="rw" name="nco_ct_bw" pos="24:21" rst="4">
          <comment>nco 2ord bandwidth.</comment>
        </bits>
        <bits access="rw" name="nco_ct_u" pos="20:18" rst="3">
          <comment>nco dc bandwidth.</comment>
        </bits>
        <bits access="rw" name="softmute_th1" pos="17:12" rst="6">
          <comment>softmute threshold for RSSI.</comment>
        </bits>
        <bits access="rw" name="softmute_th2" pos="11:6" rst="6">
          <comment>softmute threshold for noise.</comment>
        </bits>
        <bits access="rw" name="softmute_th3" pos="5:0" rst="6">
          <comment>softmute threshold for SNR.</comment>
        </bits>
      </reg>
      <reg name="datapath_ctrl2" protect="rw">
        <bits access="rw" name="softmute_th4" pos="31:26" rst="6">
          <comment>softmute threshold for offset.</comment>
        </bits>
        <bits access="rw" name="sm_rate" pos="25:24" rst="2">
          <comment>softmute rate. Fast-&gt;slow.</comment>
        </bits>
        <bits access="rw" name="sm_attenu" pos="23:20" rst="4">
          <comment>softmute attenu setting.</comment>
        </bits>
        <bits access="rw" name="th_softblend1" pos="19:14" rst="6">
          <comment>softblend threshold for RSSI.</comment>
        </bits>
        <bits access="rw" name="th_softblend2" pos="13:8" rst="6">
          <comment>softblend threshold for noise.</comment>
        </bits>
        <bits access="rw" name="offset_flt_ct_u" pos="7:6" rst="2">
          <comment>offset filter bandwidth.</comment>
        </bits>
        <bits access="rw" name="lpf_bw_dr" pos="5" rst="1">
      </bits>
        <bits access="rw" name="lpf_bw_reg" pos="4:2" rst="3">
      </bits>
        <bits access="rw" name="deemph_hcc" pos="1:0" rst="2">
          <comment>direct deemphasis hcc reg.</comment>
        </bits>
      </reg>
      <reg name="datapath_ctrl3" protect="rw">
        <bits access="rw" name="step19k_reg" pos="30:16" rst="13">
          <comment>step 19k value</comment>
        </bits>
        <bits access="rw" name="interval_reg" pos="15:0" rst="14">
          <comment>interval value</comment>
        </bits>
      </reg>
      <reg name="datapath_ctrl4" protect="rw">
        <bits access="rw" name="notch_flt_bypass" pos="22" rst="1">
      </bits>
        <bits access="rw" name="notch_flt_ka" pos="21:20" rst="2">
      </bits>
        <bits access="rw" name="notch_flt_z0_i" pos="19:0" rst="0">
      </bits>
      </reg>
      <reg name="datapath_ctrl5" protect="rw">
        <bits access="rw" name="notch_flt_z0_q" pos="19:0" rst="0">
      </bits>
      </reg>
      <reg name="log_ctrl0" protect="rw">
        <bits access="rw" name="ct_u_noise" pos="23:18" rst="28">
          <comment>[5:3]: noise_db1 bandwidth
[2:0]: noise_db2 bandwidth</comment>
        </bits>
        <bits access="rw" name="ct_u_signal" pos="17:12" rst="28">
          <comment>[5:3]: signal_db1 bandwidth
[2:0]: signal_db2 bandwidth</comment>
        </bits>
        <bits access="rw" name="ct_u_rssi" pos="11:6" rst="28">
          <comment>[5:3]: rssi_db1 bandwidth
[2:0]: rssi_db2 bandwidth</comment>
        </bits>
        <bits access="rw" name="ct_u_pilot" pos="5:0" rst="28">
          <comment>[5:3]: pilot_db1 bandwidth
[2:0]: pilot_db2 bandwitdh</comment>
        </bits>
      </reg>
      <reg name="status0" protect="r">
        <bits access="r" name="seek_ready" pos="29" rst="1">
      </bits>
        <bits access="r" name="seek_done" pos="28" rst="1">
      </bits>
        <bits access="r" name="rssi_db2" pos="27:21" rst="7">
          <comment>rssi. Unit is db.</comment>
        </bits>
        <bits access="r" name="snr_out" pos="20:15" rst="6">
          <comment>snr. Unit is db.</comment>
        </bits>
        <bits access="r" name="signal_db2" pos="14:8" rst="7">
          <comment>signal. Unit is db.</comment>
        </bits>
        <bits access="r" name="offset2" pos="7:0" rst="0">
          <comment>frequency offset. Unit is db.</comment>
        </bits>
      </reg>
      <reg name="status1" protect="r">
        <bits access="r" name="noise_db2" pos="28:22" rst="7">
      </bits>
        <bits access="r" name="snr19k_out" pos="21:16" rst="6">
      </bits>
        <bits access="r" name="pilot_db2" pos="15:9" rst="7">
      </bits>
        <bits access="r" name="sk_cmp_grp_flag" pos="8:4" rst="5">
          <comment>[4]: 19k pilot flag
[3]: offset flag
[2]: snr flag
[1]: rssi flag
[0]: noise flag</comment>
        </bits>
        <bits access="r" name="snr_cnt" pos="3:0" rst="4">
      </bits>
      </reg>
      <reg name="status2" protect="r">
        <bits access="r" name="rssi_cnt" pos="31:24" rst="0">
      </bits>
        <bits access="r" name="noise_cnt" pos="23:16" rst="0">
      </bits>
        <bits access="r" name="pilot_cnt" pos="15:8" rst="0">
      </bits>
        <bits access="r" name="offset_cnt" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="status3" protect="r">
        <bits access="r" name="ct_hcc" pos="18:16" rst="3">
      </bits>
        <bits access="r" name="fircut_bw" pos="15:13" rst="3">
      </bits>
        <bits access="r" name="fmdem_sel" pos="12" rst="1">
      </bits>
        <bits access="r" name="dig_gainct" pos="11:4" rst="0">
      </bits>
        <bits access="r" name="agc_index" pos="3:0" rst="4">
      </bits>
      </reg>
      <reg name="rsvd_reg" protect="rw">
        <bits access="r" name="rsvd_in" pos="31:16" rst="14">
      </bits>
        <bits access="rw" name="rsvd_out" pos="15:0" rst="65280">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_pulp_irq.xml">
    <module category="wcn" name="WCN_PULP_IRQ">
      <reg name="enable" protect="rw">
        <bits access="rw" name="enable" pos="31:0" rst="0">
          <comment>interrupt enable</comment>
        </bits>
      </reg>
      <reg name="pending" protect="rw">
        <bits access="rw" name="pending" pos="31:0" rst="0">
          <comment>interrupt pending</comment>
        </bits>
      </reg>
      <reg name="set_pending" protect="rw">
        <bits access="rs" name="set_pending" pos="31:0" rst="0">
          <comment>bit type is changed from w1s to rs.
          set interrupt pending</comment>
        </bits>
      </reg>
      <reg name="clear_pending" protect="rw">
        <bits access="rc" name="clear_pending" pos="31:0" rst="0">
          <comment>bit type is changed from w1c to rc.
          clear interrupt pending</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_pulp_sleep.xml">
    <module category="wcn" name="WCN_PULP_SLEEP">
      <reg name="sleep_ctrl" protect="rw">
        <bits access="rw" name="sleep_enable" pos="0" rst="0">
          <comment>Enable sleep</comment>
        </bits>
      </reg>
      <reg name="sleep_status" protect="rw">
        <bits access="rw" name="sleep" pos="0" rst="0">
          <comment>sleep stauts
0: not_sleep
1: sleep</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_pulp_debug_unit.xml">
    <module category="wcn" name="WCN_PULP_DEBUG_UNIT">
      <reg name="dbg_ctrl" protect="rw">
        <bits access="rw" name="halt" pos="16" rst="0">
          <comment>when 1 written,core enters debug mode, when 0 written, core exits debug mode
when read, 1 means core is in debug mode</comment>
        </bits>
        <bits access="rw" name="sste" pos="0" rst="0">
          <comment>single step enable</comment>
        </bits>
      </reg>
      <reg name="dbg_hit" protect="rw">
        <bits access="r" name="sleep" pos="16" rst="0">
          <comment>set when the core is a sleeping state and wait for an event</comment>
        </bits>
        <bits access="rw" name="ssth" pos="0" rst="0">
          <comment>single-step hit, sticky bit that must be cleared by external debugger</comment>
        </bits>
      </reg>
      <reg name="dbg_ie" protect="rw">
        <bits access="rw" name="ecall" pos="11" rst="0">
          <comment>environment call for M-mode</comment>
        </bits>
        <bits access="rw" name="saf" pos="7" rst="0">
          <comment>store access fault (together with laf)</comment>
        </bits>
        <bits access="rw" name="sam" pos="6" rst="0">
          <comment>store address Misaligned (never traps)</comment>
        </bits>
        <bits access="rw" name="laf" pos="5" rst="0">
          <comment>load access fault (together with saf)</comment>
        </bits>
        <bits access="rw" name="lam" pos="4" rst="0">
          <comment>load access Misaligned (never traps)</comment>
        </bits>
        <bits access="rw" name="bp" pos="3" rst="0">
          <comment>ebreak instruction causes trap</comment>
        </bits>
        <bits access="rw" name="ill" pos="2" rst="0">
          <comment>illegal instruction</comment>
        </bits>
        <bits access="rw" name="iaf" pos="1" rst="0">
          <comment>instruction access fault (not implemented)</comment>
        </bits>
        <bits access="rw" name="iam" pos="0" rst="0">
          <comment>instruction address misaligned (never traps)</comment>
        </bits>
      </reg>
      <reg name="dbg_cause" protect="r">
        <bits access="r" name="irq" pos="31" rst="0">
          <comment>interrupt caused us to enter debug mode</comment>
        </bits>
        <bits access="r" name="cause" pos="4:0" rst="0">
          <comment>exception/interrupt number</comment>
        </bits>
      </reg>
      <hole size="8064"/>
      <reg name="dbg_gpr0" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr1" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr2" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr3" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr4" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr5" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr6" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr7" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr8" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr9" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr10" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr11" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr12" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr13" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr14" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr15" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr16" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr17" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr18" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr19" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr20" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr21" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr22" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr23" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr24" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr25" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr26" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr27" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr28" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr29" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr30" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <reg name="dbg_gpr31" protect="rw">
        <bits access="rw" name="gpr_reg" pos="31:0" rst="0">
          <comment>general purpose register</comment>
        </bits>
      </reg>
      <hole size="56320"/>
      <reg name="dbg_npc" protect="rw">
        <bits access="rw" name="npc" pos="31:0" rst="0">
          <comment>Next PC to be executed</comment>
        </bits>
      </reg>
      <reg name="dbg_ppc" protect="r">
        <bits access="r" name="ppc" pos="31:0" rst="0">
          <comment>previous PC, already executed</comment>
        </bits>
      </reg>
      <hole size="90048"/>
      <reg name="dbg_mstatus" protect="rw">
        <bits access="r" name="prv" pos="2:1" rst="3">
          <comment>Statically 2'b11 and cannot be altered</comment>
        </bits>
        <bits access="rw" name="int_en" pos="0" rst="0">
          <comment>Interrupt enable:
When an exception is encountered, Interrupt Enable will be set to 1'b0.
When the eret instruction is executed, the original value of the Interrupt Enable will be restored, as MESTATUS will replace MSTATUS.
If you want to be enable interrupt handling in your exception handler, set the Interrupt Enable to 1'b1 inside your handler code.</comment>
        </bits>
      </reg>
      <hole size="2048"/>
      <reg name="dbg_mepc" protect="rw">
        <bits access="rw" name="mepc" pos="31:0" rst="0">
          <comment>When an exception is encountered, the current program counter is saved in MEPC, and the core jumps to the exception address.
When an eret instruction is executed, the value from MEPC replaces the current program counter.</comment>
        </bits>
      </reg>
      <reg name="dbg_mcause" protect="r">
        <bits access="r" name="interrupt" pos="31" rst="0">
          <comment>this bit is  set when the exception was triggerd by an interrupt</comment>
        </bits>
        <bits access="r" name="excp_code" pos="4:0" rst="0">
          <comment>exception code</comment>
        </bits>
      </reg>
      <hole size="36256"/>
      <reg name="dbg_loop_start0" protect="rw">
        <bits access="rw" name="lpstart0" pos="31:0" rst="0">
          <comment>hardware loop 0 start</comment>
        </bits>
      </reg>
      <reg name="dbg_loop_end0" protect="rw">
        <bits access="rw" name="lpend0" pos="31:0" rst="0">
          <comment>hardware loop 0 end</comment>
        </bits>
      </reg>
      <reg name="dbg_loop_cnt0" protect="rw">
        <bits access="rw" name="lpcount0" pos="31:0" rst="0">
          <comment>hardware loop 0 counter</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="dbg_loop_start1" protect="rw">
        <bits access="rw" name="lpstart1" pos="31:0" rst="0">
          <comment>hardware loop 1 start</comment>
        </bits>
      </reg>
      <reg name="dbg_loop_end1" protect="rw">
        <bits access="rw" name="lpend1" pos="31:0" rst="0">
          <comment>hardware loop 1 end</comment>
        </bits>
      </reg>
      <reg name="dbg_loop_cnt1" protect="rw">
        <bits access="rw" name="lpcount1" pos="31:0" rst="0">
          <comment>hardware loop 1 counter</comment>
        </bits>
      </reg>
      <hole size="288"/>
      <reg name="dbg_mestatus" protect="rw">
        <bits access="r" name="prv" pos="2:1" rst="3">
          <comment>Statically 2'b11 and cannot be altered</comment>
        </bits>
        <bits access="rw" name="int_en" pos="0" rst="0">
          <comment>Interrupt enable:
When an exception is encountered, the current value of MSTATUS is saved in MESTATUS.
When an eret instruction is executed, the value from MESTATUS replaces MSTATUS register.</comment>
        </bits>
      </reg>
      <hole size="59360"/>
      <reg name="dbg_mcpuid" protect="r">
        <bits access="r" name="base" pos="31:30" rst="0">
          <comment>read as 0, which means RV32I</comment>
        </bits>
        <bits access="r" name="extension" pos="25:0" rst="8392960">
          <comment>RI5CY only supports the I and M extension, plus the RI5CY non-standard extensions. This means bits 8(I), 12(M) and 23(X) are 1, the rest is 0.</comment>
        </bits>
      </reg>
      <reg name="dbg_mimpid" protect="r">
        <bits access="r" name="implementation" pos="31:16" rst="0">
      </bits>
        <bits access="r" name="source" pos="15:0" rst="32768">
      </bits>
      </reg>
      <hole size="448"/>
      <reg name="dbg_hartid" protect="r">
        <bits access="r" name="cluster_id" pos="10:5" rst="0">
          <comment>ID of the cluster</comment>
        </bits>
        <bits access="r" name="core_id" pos="3:0" rst="0">
          <comment>ID of the within the cluster</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_rf_if.xml">
    <module category="wcn" name="WCN_RF_IF">
      <reg name="revision" protect="r">
        <bits access="r" name="revid" pos="3:0" rst="3">
          <comment>Revision ID.</comment>
        </bits>
      </reg>
      <reg name="sys_control" protect="rw">
        <bits access="rw" name="bt_tx_type" pos="9" rst="0">
      </bits>
        <bits access="rw" name="bt_ch_ctrl_src_sel" pos="8" rst="0">
          <comment>BT channel control selection.
1'h0:: bt
1'h1:: reg</comment>
        </bits>
        <bits access="rw" name="fm_adc_clk_mode" pos="7" rst="0">
          <comment>fm adc clock mode.
1'd0:: divider
divider of pll
1'd1:: adpll
43.008MHz</comment>
        </bits>
        <bits access="rw" name="bt_hopping_en" pos="6" rst="1">
          <comment>enable bt hopping while channel is muliplier of 26MHz during rx procedure.
If this bit is set to 1'd1, rf_interface will change the ADC clock to 28/56MHz generated by adpll instead of 26/52MHz crystal clock to avoid the receiving interference caused by 26MHz adc clock.</comment>
        </bits>
        <bits access="rw" name="bt_tune_diff_en" pos="5" rst="1">
          <comment>enable BT ARFCN tune diff mode.
If this bit is set to 1'd1, rf_interface will redo the rx/tx procedure (including pll calibration process) if ARFCN changes during one rx/tx procedure.</comment>
        </bits>
        <bits access="rw" name="clk_digital_enable_reg" pos="4" rst="0">
          <comment>enable all digital clock.
If this bit is set to 1'd1, all digital clocks including gating ones will be forcely on.</comment>
        </bits>
        <bits access="rw" name="rf_mode" pos="3:2" rst="0">
          <comment>RF mode.
2'd0:: BT
2'd1:: WIFI
2'd2:: FM</comment>
        </bits>
        <bits access="rw" name="chip_self_cal_enable" pos="1" rst="0">
          <comment>Chip self_cal enable.
Self cal process will be triggered at posedge of chip_self_cal_enable.</comment>
        </bits>
        <bits access="rw" name="soft_resetn" pos="0" rst="1">
          <comment>soft reset. Active low.</comment>
        </bits>
      </reg>
      <reg name="bt_control" protect="rw">
        <bits access="rw" name="bt_ch_type" pos="7" rst="0">
          <comment>BT channel type.
1'd0:: normal
1'd1:: multiplier
Multiplier of 26MHz. _x000D_</comment>
        </bits>
        <bits access="rw" name="bt_arfcn" pos="6:0" rst="39">
          <comment>BT Channel number. _x000D_
7'h00 : Channel0 _x000D_
7'h4E : Channel78</comment>
        </bits>
      </reg>
      <reg name="wf_control" protect="rw">
        <bits access="rw" name="wf_freq_direct" pos="22:6" rst="0">
          <comment>frequency direct reg. u7.10, unit is MHz</comment>
        </bits>
        <bits access="rw" name="wf_freq_mode" pos="5" rst="0">
          <comment>WIFI freq mode.
1'd0:: channel
channel number mode. Channel Freq = 2407MHz + 5MH*wf_chn
1'd1:: direct
direct mode. Channel Freq = 2412MH + wf_freq_direct</comment>
        </bits>
        <bits access="rw" name="wf_chn" pos="4:1" rst="1">
          <comment>WIFI channel.</comment>
        </bits>
        <bits access="rw" name="wf_tune" pos="0" rst="0">
          <comment>Start tune.
WIFI will be started at the posedge of wf_tune.</comment>
        </bits>
      </reg>
      <reg name="fm_control" protect="rw">
        <bits access="rw" name="fm_freq_direct" pos="31:16" rst="0">
          <comment>frequency direct reg. u6.10, unit is MHz</comment>
        </bits>
        <bits access="rw" name="fm_band_sel" pos="14:13" rst="2">
          <comment>FM band select.
2'd0:: 87_108MHz : (US/Europe)
2'd1:: 76_91MHz : (Japan)
2'd2:: 76_108MHz : (World Wide)
2'd3:: 65_76MHz : (East Europe)</comment>
        </bits>
        <bits access="rw" name="fm_freq_mode" pos="12" rst="0">
          <comment>FM freq mode.
1'd0:: channel
channel number mode. Channel Freq = 25KHz*fm_chan_reg + bottom freq
1'd1:: direct
direct mode. Channel Freq = bottom freq + fm_freq_direct</comment>
        </bits>
        <bits access="rw" name="fm_chan_reg" pos="11:1" rst="1028">
          <comment>FM channel.</comment>
        </bits>
        <bits access="rw" name="fm_tune" pos="0" rst="0">
          <comment>Start tune.
FM will be started at the posedge of fm_tune.</comment>
        </bits>
      </reg>
      <reg name="inter_freq_setting" protect="rw">
        <bits access="rw" name="fm_imgrej" pos="27" rst="0">
          <comment>FM intermediate frequency mode.
1'd0:: positive
1'd1:: negtive</comment>
        </bits>
        <bits access="rw" name="fm_if" pos="26:16" rst="128">
          <comment>FM intermediate freqeuncy. u1.10. Unit is Mhz. Default is 125KHz. _x000D_</comment>
        </bits>
        <bits access="rw" name="bt_zif" pos="12" rst="0">
          <comment>enable zero intermediate frequency.
1'd0:: use_bt_freq
use intermediate frequency defined by bt_digital_lo_freq;
1'd1:: use_0hz
use 0Hz intermediate frequency.</comment>
        </bits>
        <bits access="rw" name="bt_imgrej" pos="11" rst="0">
          <comment>BT intermediate frequency mode.
1'd0:: positive
1'd1:: negtive</comment>
        </bits>
        <bits access="rw" name="bt_if" pos="10:0" rst="758">
          <comment>BT intermediate freqeuncy. u1.10. Unit is Mhz. Default is740KHz.</comment>
        </bits>
      </reg>
      <reg name="bandgap_setting" protect="rw">
        <bits access="rw" name="sel_bg" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="lna_rmx_setting" protect="rw">
        <bits access="rw" name="bt_lna_input_short_rx" pos="25" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_input_short_tx" pos="24" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_en" pos="23" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_vcas_bit" pos="22:21" rst="0">
      </bits>
        <bits access="rw" name="bt_tia_bypass" pos="20" rst="0">
      </bits>
        <bits access="rw" name="bt_rmx_disable" pos="19" rst="0">
      </bits>
        <bits access="rw" name="wf_tia_rin_bit" pos="18:17" rst="0">
      </bits>
        <bits access="rw" name="bt_tia_rin_bit" pos="16:15" rst="2">
      </bits>
        <bits access="rw" name="bt_rmx_lo_vcom_bit" pos="14:13" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_reg_ictrl" pos="12" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_port_sel" pos="8:7" rst="0">
      </bits>
        <bits access="rw" name="fm_rmx_harm_rej_en" pos="6" rst="1">
      </bits>
        <bits access="rw" name="fm_rmx_lobias_bit" pos="5:4" rst="1">
      </bits>
        <bits access="rw" name="fm_rmx_reg_bit" pos="3:1" rst="4">
      </bits>
        <bits access="rw" name="fm_rmx_rshort_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pga_setting0" protect="rw">
        <bits access="rw" name="pga_fm_en_dr" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pga_fm_en_reg" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pga_blk_mode" pos="14" rst="0">
      </bits>
        <bits access="rw" name="pga_bw_tun_bit" pos="13:11" rst="3">
      </bits>
        <bits access="rw" name="pga_cf_bit" pos="10:6" rst="0">
      </bits>
        <bits access="rw" name="pga_iq_sw" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pga_rs_bit" pos="4:0" rst="0">
      </bits>
      </reg>
      <reg name="pga_setting1" protect="rw">
        <bits access="rw" name="fm_pga_gain_bit" pos="22:20" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_bw_mode_1m" pos="19:18" rst="1">
      </bits>
        <bits access="rw" name="bt_pga_bw_mode_2m" pos="17:16" rst="2">
      </bits>
        <bits access="rw" name="wf_pga_bw_mode" pos="15:14" rst="3">
      </bits>
        <bits access="rw" name="fm_pga_bw_mode" pos="13:12" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_ibit" pos="11:10" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_ibit" pos="9:8" rst="2">
      </bits>
        <bits access="rw" name="fm_pga_ibit" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_if_mode" pos="5:4" rst="2">
      </bits>
        <bits access="rw" name="wf_pga_if_mode" pos="3:2" rst="0">
      </bits>
        <bits access="rw" name="fm_pga_if_mode" pos="1:0" rst="2">
      </bits>
      </reg>
      <reg name="rxflt_setting" protect="rw">
        <bits access="rw" name="rxflt_rstn_dr" pos="30" rst="0">
      </bits>
        <bits access="rw" name="rxflt_rstn_reg" pos="29" rst="0">
      </bits>
        <bits access="rw" name="rxflt_aux_en" pos="28" rst="0">
      </bits>
        <bits access="rw" name="rxflt_iqswap" pos="27" rst="0">
      </bits>
        <bits access="rw" name="rxflt_cap_bit" pos="26:23" rst="6">
      </bits>
        <bits access="rw" name="bt_rxflt_mode_sel_1m" pos="22:21" rst="1">
      </bits>
        <bits access="rw" name="bt_rxflt_mode_sel_2m" pos="20:19" rst="2">
      </bits>
        <bits access="rw" name="wf_rxflt_mode_sel" pos="18:17" rst="3">
      </bits>
        <bits access="rw" name="fm_rxflt_mode_sel" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="bt_rxflt_ibit" pos="14:13" rst="0">
      </bits>
        <bits access="rw" name="wf_rxflt_ibit" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="fm_rxflt_ibit" pos="10:9" rst="0">
      </bits>
        <bits access="rw" name="bt_rxflt_if_mode" pos="8:7" rst="2">
      </bits>
        <bits access="rw" name="wf_rxflt_if_mode" pos="6:5" rst="0">
      </bits>
        <bits access="rw" name="fm_rxflt_if_mode" pos="4:3" rst="2">
      </bits>
        <bits access="rw" name="bt_rxflt_wifi_hp" pos="2" rst="0">
      </bits>
        <bits access="rw" name="wf_rxflt_wifi_hp" pos="1" rst="1">
      </bits>
        <bits access="rw" name="fm_rxflt_wifi_hp" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="adc_setting0" protect="rw">
        <bits access="rw" name="adc_delay_bit" pos="12:9" rst="3">
      </bits>
        <bits access="rw" name="adc_dly_in_ctrl" pos="8" rst="0">
      </bits>
        <bits access="rw" name="adc_vcm_sel" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="adc_clk_edge" pos="5" rst="1">
      </bits>
        <bits access="rw" name="adc_clk_div2" pos="4" rst="0">
      </bits>
        <bits access="rw" name="adc_clk_sel_dr" pos="3" rst="0">
      </bits>
        <bits access="rw" name="adc_clk_sel_reg" pos="2:0" rst="0">
      </bits>
      </reg>
      <reg name="adc_setting1" protect="rw">
        <bits access="rw" name="bt_adc_ref_ibit_1m" pos="23:21" rst="0">
      </bits>
        <bits access="rw" name="bt_adc_ref_ibit_2m" pos="20:18" rst="0">
      </bits>
        <bits access="rw" name="wf_adc_ref_ibit" pos="17:15" rst="0">
      </bits>
        <bits access="rw" name="fm_adc_ref_ibit" pos="14:12" rst="0">
      </bits>
        <bits access="rw" name="bt_adc_reg_ibit_1m" pos="11:9" rst="0">
      </bits>
        <bits access="rw" name="bt_adc_reg_ibit_2m" pos="8:6" rst="0">
      </bits>
        <bits access="rw" name="wf_adc_reg_ibit" pos="5:3" rst="0">
      </bits>
        <bits access="rw" name="fm_adc_reg_ibit" pos="2:0" rst="0">
      </bits>
      </reg>
      <reg name="bt_dac_setting" protect="rw">
        <bits access="rw" name="bt_tmx_cal_clk_edge" pos="31" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_bw_tune_bit_1m" pos="30:27" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_bw_tune_bit_2m" pos="26:23" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_filter_ibias_bit" pos="22:21" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_low_mag" pos="20" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_rstn_dr" pos="19" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_rstn_reg" pos="18" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_clk_edge" pos="17" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_vlow_ctrl_bit" pos="16:14" rst="4">
      </bits>
        <bits access="rw" name="bt_dac_vtr_sel" pos="13" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_auxout_en" pos="12:10" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_cm_bit" pos="9:8" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_core_bit" pos="7:5" rst="4">
      </bits>
        <bits access="rw" name="bt_dac_iout_enable" pos="4" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_lpwr_mode" pos="3" rst="1">
      </bits>
        <bits access="rw" name="bt_dac_mux_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="bt_dac_range_bit" pos="1:0" rst="2">
      </bits>
      </reg>
      <reg name="bt_txrf_setting" protect="rw">
        <bits access="rw" name="bt_delay_padrv" pos="31:24" rst="30">
      </bits>
        <bits access="rw" name="txrf_captune_bit_rx_lo" pos="23:20" rst="7">
      </bits>
        <bits access="rw" name="txrf_captune_bit_rx_md" pos="19:16" rst="7">
      </bits>
        <bits access="rw" name="txrf_captune_bit_rx_hi" pos="15:12" rst="7">
      </bits>
        <bits access="rw" name="txrf_captune_bit_tx_lo" pos="11:8" rst="7">
      </bits>
        <bits access="rw" name="txrf_captune_bit_tx_md" pos="7:4" rst="7">
      </bits>
        <bits access="rw" name="txrf_captune_bit_tx_hi" pos="3:0" rst="7">
      </bits>
      </reg>
      <reg name="fm_dsp_setting" protect="rw">
        <bits access="rw" name="fm_dsp_resetn_delay" pos="3:2" rst="0">
      </bits>
        <bits access="rw" name="fm_dsp_resetn_dr" pos="1" rst="0">
      </bits>
        <bits access="rw" name="fm_dsp_resetn_reg" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="vco_setting" protect="rw">
        <bits access="rw" name="vco_regcap_selh" pos="26" rst="0">
      </bits>
        <bits access="rw" name="vco_buf_ibit" pos="25:22" rst="6">
      </bits>
        <bits access="rw" name="vco_div2_bias_bit" pos="21:19" rst="2">
      </bits>
        <bits access="rw" name="vco_buf_bias_bit" pos="18:17" rst="3">
      </bits>
        <bits access="rw" name="vco_var_bit" pos="16:14" rst="3">
      </bits>
        <bits access="rw" name="vco_var_reverse" pos="13" rst="0">
      </bits>
        <bits access="rw" name="vco_var_short" pos="12" rst="0">
      </bits>
        <bits access="rw" name="vco_var_vcom" pos="11:9" rst="4">
      </bits>
        <bits access="rw" name="vco_vmode_bit" pos="8:6" rst="0">
      </bits>
        <bits access="rw" name="bt_vco_imode" pos="5" rst="1">
      </bits>
        <bits access="rw" name="wf_vco_imode" pos="4" rst="1">
      </bits>
        <bits access="rw" name="fm_vco_imode" pos="3" rst="1">
      </bits>
        <bits access="rw" name="bt_vco_vmode" pos="2" rst="0">
      </bits>
        <bits access="rw" name="wf_vco_vmode" pos="1" rst="0">
      </bits>
        <bits access="rw" name="fm_vco_vmode" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pll_setting0" protect="rw">
        <bits access="rw" name="pll_test_en" pos="30" rst="0">
      </bits>
        <bits access="rw" name="pll_reg_peri_bit" pos="29:26" rst="8">
      </bits>
        <bits access="rw" name="pll_reg_presc" pos="25:22" rst="8">
      </bits>
        <bits access="rw" name="pll_reg_presc_rc" pos="21:20" rst="2">
      </bits>
        <bits access="rw" name="pll_open_en" pos="19" rst="0">
      </bits>
        <bits access="rw" name="pll_fbc_sel" pos="18:16" rst="1">
      </bits>
        <bits access="rw" name="pll_sinc_mode" pos="15:13" rst="1">
      </bits>
        <bits access="rw" name="pll_xfer_aux_en" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pll_bypass_notch" pos="11" rst="0">
      </bits>
        <bits access="rw" name="pll_div_fm_lo_clk_dr" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pll_div_fm_lo_clk_reg" pos="9:6" rst="6">
      </bits>
        <bits access="rw" name="pll_div_fm_adc_clk_dr" pos="5" rst="0">
      </bits>
        <bits access="rw" name="pll_div_fm_adc_clk_reg" pos="4:0" rst="28">
      </bits>
      </reg>
      <reg name="pll_setting1" protect="rw">
        <bits access="rw" name="pll_lowpwr_mode_rx" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pll_lowpwr_mode_tx" pos="30" rst="0">
      </bits>
        <bits access="rw" name="pll_cp_r_bit_rx" pos="29:26" rst="8">
      </bits>
        <bits access="rw" name="pll_cp_r_bit_tx" pos="25:22" rst="8">
      </bits>
        <bits access="rw" name="pll_gain_bit_rx" pos="21:18" rst="7">
      </bits>
        <bits access="rw" name="pll_gain_bit_tx" pos="17:14" rst="7">
      </bits>
        <bits access="rw" name="pll_lpf_gain_rx" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pll_lpf_gain_tx" pos="9:6" rst="2">
      </bits>
        <bits access="rw" name="pll_r_bit_rx" pos="5:4" rst="2">
      </bits>
        <bits access="rw" name="pll_r_bit_tx" pos="3:2" rst="2">
      </bits>
        <bits access="rw" name="pll_refmulti2_en_rx" pos="1" rst="1">
      </bits>
        <bits access="rw" name="pll_refmulti2_en_tx" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="pll_setting2" protect="rw">
        <bits access="rw" name="pll_bt_adc_clk_en_dr" pos="31" rst="0">
      </bits>
        <bits access="rw" name="pll_bt_adc_clk_en_reg" pos="30" rst="0">
      </bits>
        <bits access="rw" name="pll_clk_dig52m_en_dr" pos="29" rst="0">
      </bits>
        <bits access="rw" name="pll_clk_dig52m_en_reg" pos="28" rst="0">
      </bits>
        <bits access="rw" name="pll_mdll_refclk_en_dr" pos="27" rst="0">
      </bits>
        <bits access="rw" name="pll_mdll_refclk_en_reg" pos="26" rst="0">
      </bits>
        <bits access="rw" name="pll_ref_mode_rx" pos="25" rst="0">
      </bits>
        <bits access="rw" name="pll_ref_mode_tx" pos="24" rst="1">
      </bits>
        <bits access="rw" name="pll_pfd_res_bit_rx" pos="23:18" rst="0">
      </bits>
        <bits access="rw" name="pll_pfd_res_bit_tx" pos="17:12" rst="0">
      </bits>
        <bits access="rw" name="pll_phase_ctrl_dly_rx" pos="11:10" rst="0">
      </bits>
        <bits access="rw" name="pll_phase_ctrl_dly_tx" pos="9:8" rst="0">
      </bits>
        <bits access="rw" name="mdll_div_rx" pos="7:4" rst="2">
      </bits>
        <bits access="rw" name="mdll_div_tx" pos="3:0" rst="2">
      </bits>
      </reg>
      <reg name="pll_status" protect="rw">
        <bits access="rw" name="pll_lock_flag_timer_delay_sel" pos="5:4" rst="0">
      </bits>
        <bits access="rw" name="pll_lock_det_timer_delay_sel" pos="3:2" rst="0">
      </bits>
        <bits access="r" name="pll_lock_flag" pos="1" rst="0">
      </bits>
        <bits access="r" name="pll_lock_det" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="adpll_setting0" protect="rw">
        <bits access="rw" name="adpll_sdm_clk_sel_timer_delay" pos="29:27" rst="5">
      </bits>
        <bits access="rw" name="adpll_rstn_timer_delay" pos="26:20" rst="49">
      </bits>
        <bits access="rw" name="adpll_clk_en_timer_delay" pos="19" rst="0">
      </bits>
        <bits access="rw" name="adpll_rstn_dr" pos="18" rst="0">
      </bits>
        <bits access="rw" name="adpll_rstn_reg" pos="17" rst="0">
      </bits>
        <bits access="rw" name="adpll_cp_ibit" pos="16:14" rst="4">
      </bits>
        <bits access="rw" name="adpll_reg_res_bit" pos="13:12" rst="0">
      </bits>
        <bits access="rw" name="adpll_res_bit" pos="11:10" rst="2">
      </bits>
        <bits access="rw" name="adpll_test_en" pos="9" rst="0">
      </bits>
        <bits access="rw" name="adpll_vreg_bit" pos="8:5" rst="8">
      </bits>
        <bits access="rw" name="adpll_pcon_mode" pos="4" rst="0">
      </bits>
        <bits access="rw" name="adpll_refmulti2_en" pos="3" rst="1">
      </bits>
        <bits access="rw" name="adpll_vco_high_test" pos="2" rst="0">
      </bits>
        <bits access="rw" name="adpll_vco_low_test" pos="1" rst="0">
      </bits>
        <bits access="rw" name="adpll_sdm_clk_test_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="adpll_setting1" protect="rw">
        <bits access="rw" name="adpll_clk2bt_dig_en" pos="13" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2bt_dig_sel" pos="12" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2bt_adc_en_dr" pos="11" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2bt_adc_en_reg" pos="10" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2bt_adc_sel_dr" pos="9" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2bt_adc_sel_reg" pos="8" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2fmwf_adc_en_dr" pos="7" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2fmwf_adc_en_reg" pos="6" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2fmwf_adc_sel_dr" pos="5" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2fmwf_adc_sel_reg" pos="4" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2wf_dig_en_dr" pos="3" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2wf_dig_en_reg" pos="2" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2wf_dig_sel_dr" pos="1" rst="0">
      </bits>
        <bits access="rw" name="adpll_clk2wf_dig_sel_reg" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="adpll_status" protect="rw">
        <bits access="rw" name="adpll_lock_flag_timer_delay_sel" pos="5:4" rst="0">
      </bits>
        <bits access="rw" name="adpll_lock_det_timer_delay_sel" pos="3:2" rst="0">
      </bits>
        <bits access="r" name="adpll_lock_flag" pos="1" rst="0">
      </bits>
        <bits access="r" name="adpll_lock_det" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="mdll_setting" protect="rw">
        <bits access="rw" name="mdll_rstn_dr" pos="17" rst="0">
      </bits>
        <bits access="rw" name="mdll_rstn_reg" pos="16" rst="0">
      </bits>
        <bits access="rw" name="disable_refclk_pll" pos="15" rst="0">
      </bits>
        <bits access="rw" name="mdll_startup_bit" pos="14:12" rst="6">
      </bits>
        <bits access="rw" name="mdll_cp_ibit" pos="11:9" rst="0">
      </bits>
        <bits access="rw" name="mdll_band_bit" pos="8:6" rst="7">
      </bits>
        <bits access="rw" name="mdll_band_sel" pos="5" rst="0">
      </bits>
        <bits access="rw" name="mdll_div_bit" pos="4:0" rst="5">
      </bits>
      </reg>
      <reg name="pll_sdm_setting0" protect="rw">
        <bits access="rw" name="pll_freq_former_shift_ct" pos="20:18" rst="5">
      </bits>
        <bits access="rw" name="pll_freq_former_bypass" pos="17" rst="0">
      </bits>
        <bits access="rw" name="pll_div_dr" pos="16" rst="0">
      </bits>
        <bits access="rw" name="pll_sdm_clk_sel_0" pos="15" rst="0">
      </bits>
        <bits access="rw" name="pll_sdm_clk_sel_1" pos="14" rst="1">
      </bits>
        <bits access="rw" name="reset_pll_sdm_timer_delay" pos="13:10" rst="2">
      </bits>
        <bits access="rw" name="pll_sdm_resetn_dr" pos="9" rst="0">
      </bits>
        <bits access="rw" name="pll_sdm_resetn_reg" pos="8" rst="0">
      </bits>
        <bits access="rw" name="pll_sdm_clk_edge" pos="7" rst="0">
      </bits>
        <bits access="rw" name="pll_sdm_int_dec_sel" pos="6:5" rst="2">
      </bits>
        <bits access="rw" name="pll_sdm_dither_bypass" pos="4" rst="0">
      </bits>
        <bits access="rw" name="pll_sdm_delay_sel" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="pll_sdm_setting1" protect="rw">
        <bits access="rw" name="pll_div_reg" pos="30:0" rst="787561236">
          <comment>To be used when pll_pll_freq_dr=1._x000D_
Fomula is freq*2^24/(mdll_div*crystal_clk)</comment>
        </bits>
      </reg>
      <reg name="adpll_sdm_setting0" protect="rw">
        <bits access="rw" name="adpll_sdm_freq_dr" pos="13" rst="0">
          <comment>If 1, pll frequency is decided by freq register;_x000D_</comment>
        </bits>
        <bits access="rw" name="adpll_sdm_clk_sel_0" pos="12" rst="0">
      </bits>
        <bits access="rw" name="adpll_sdm_clk_sel_1" pos="11" rst="1">
      </bits>
        <bits access="rw" name="reset_adpll_sdm_timer_delay" pos="10:7" rst="2">
      </bits>
        <bits access="rw" name="adpll_sdm_resetn_dr" pos="6" rst="0">
          <comment>If 1, adpll sdm resetn uses sdm_resetn_reg; _x000D_
if 0, use logic value.</comment>
        </bits>
        <bits access="rw" name="adpll_sdm_resetn_reg" pos="5" rst="0">
          <comment>adpll Sdm modulator module reset register</comment>
        </bits>
        <bits access="rw" name="adpll_sdm_clk_fbc_inv" pos="4" rst="0">
          <comment>Invert SDM clock edge.</comment>
        </bits>
        <bits access="rw" name="adpll_sdm_int_dec_sel" pos="3:1" rst="3">
      </bits>
        <bits access="rw" name="adpll_sdm_dither_bypass" pos="0" rst="0">
          <comment>SDM dither bypass enable.</comment>
        </bits>
      </reg>
      <reg name="adpll_sdm_setting1" protect="rw">
        <bits access="rw" name="adpll_sdm_freq_reg" pos="31:0" rst="0">
          <comment>To be used when adpll_sdm_freq_dr=1._x000D_
Fomula is freq*2^23/crystal_clk</comment>
        </bits>
      </reg>
      <reg name="adpll_sdm_setting2" protect="rw">
        <bits access="rw" name="adpll_sdm_ss_en" pos="28" rst="0">
      </bits>
        <bits access="rw" name="adpll_sdm_ss_devi" pos="27:16" rst="0">
      </bits>
        <bits access="rw" name="adpll_sdm_ss_devi_step" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="rxflt_cal_setting0" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_loop_coef" pos="30:16" rst="1209">
      </bits>
        <bits access="rw" name="rxflt_cal_cycles" pos="15:14" rst="0">
      </bits>
        <bits access="rw" name="rxflt_cal_clk_edge" pos="13" rst="0">
      </bits>
        <bits access="rw" name="rxflt_cal_clk_edge_sel" pos="12" rst="0">
      </bits>
        <bits access="rw" name="rxflt_cal_mode_sel" pos="11:10" rst="0">
      </bits>
        <bits access="rw" name="rxflt_cal_polarity" pos="9" rst="0">
      </bits>
        <bits access="rw" name="rxflt_cal_iqswap" pos="8" rst="0">
      </bits>
        <bits access="rw" name="rxflt_cal_cnt" pos="7:4" rst="7">
      </bits>
        <bits access="rw" name="rxflt_cal_init_delay" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="rxflt_cal_setting1" protect="rw">
        <bits access="rw" name="rxflt_cal_bit_dr" pos="31" rst="0">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_resolv_enhance" pos="30" rst="0">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_resolv_enhance" pos="29" rst="0">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_resolv_enhance" pos="28" rst="0">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_loop_en" pos="27" rst="0">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_loop_pol" pos="26" rst="0">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_loop_adc_rng" pos="25:16" rst="750">
      </bits>
        <bits access="rw" name="rxflt_cal_i_bit_reg" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="rxflt_cal_q_bit_reg" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="rxflt_cal_setting2" protect="rw">
        <bits access="rw" name="rxflt_cal_range_bit" pos="30:29" rst="2">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_inter_en" pos="28" rst="0">
      </bits>
        <bits access="rw" name="wf_chn_md" pos="27:24" rst="7">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_inter_coef_lo" pos="23:16" rst="43">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_inter_coef_hi" pos="15:8" rst="43">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_inter_en" pos="7" rst="0">
      </bits>
        <bits access="rw" name="bt_chn_md" pos="6:0" rst="39">
      </bits>
      </reg>
      <reg name="rxflt_cal_setting3" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_inter_coef_lo" pos="30:16" rst="840">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_inter_coef_hi" pos="14:0" rst="840">
      </bits>
      </reg>
      <reg name="vco_pkd_cal_setting" protect="rw">
        <bits access="rw" name="vco_ibit_dr" pos="17" rst="0">
      </bits>
        <bits access="rw" name="vco_ibit_reg" pos="16:13" rst="8">
      </bits>
        <bits access="rw" name="vco_vbit_dr" pos="12" rst="0">
      </bits>
        <bits access="rw" name="vco_vbit_reg" pos="11:8" rst="8">
      </bits>
        <bits access="rw" name="vco_pkd_ref_bit" pos="7:5" rst="3">
      </bits>
        <bits access="rw" name="vco_pkd_cal_init_delay" pos="4:1" rst="0">
      </bits>
        <bits access="rw" name="vco_pkd_cal_polarity" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="pll_cal_setting0" protect="rw">
        <bits access="rw" name="pll_cal_clk_sel" pos="24" rst="0">
      </bits>
        <bits access="rw" name="pll_cal_bit" pos="23:22" rst="2">
      </bits>
        <bits access="rw" name="vco_band_dr" pos="21" rst="0">
          <comment>Pll_vco_band_reg direct reg enable.</comment>
        </bits>
        <bits access="rw" name="vco_band_reg" pos="20:11" rst="512">
          <comment>VCO band  setting.</comment>
        </bits>
        <bits access="rw" name="pll_cal_freq_dr" pos="10" rst="0">
      </bits>
        <bits access="rw" name="pll_vco_bit_hold_time" pos="9:7" rst="0">
          <comment>Vco bit hold time when vco bit changed during pll vco band calibration._x000D_
3'd0:: vco_bit_hold_time_0 : 0.25us_x000D_
3'd1:: vco_bit_hold_time_1 : 0.5us_x000D_
3'd2:: vco_bit_hold_time_2 : 0.75us_x000D_
3'd3:: vco_bit_hold_time_3 : 1us_x000D_
3'd4:: vco_bit_hold_time_4 : 1.25us_x000D_
3'd5:: vco_bit_hold_time_5 : 1.5us_x000D_
3'd6:: vco_bit_hold_time_6 : 1.75us_x000D_
3'd7:: vco_bit_hold_time_7 : 2us</comment>
        </bits>
        <bits access="rw" name="pll_cal_opt" pos="6" rst="1">
          <comment>If 1, select the best vco band bit</comment>
        </bits>
        <bits access="rw" name="pll_cal_cnt_sel" pos="5:3" rst="1">
          <comment>pll cal count time select_x000D_
3'd0:: each_cnt_time_0 : 0.5us_x000D_
3'd1:: each_cnt_time_1 : 1us_x000D_
3'd2:: each_cnt_time_2 : 2us_x000D_
3'd4:: each_cnt_time_3 : 4us_x000D_
3'd5:: each_cnt_time_4 : 8us</comment>
        </bits>
        <bits access="rw" name="pll_init_delay" pos="2:0" rst="0">
          <comment>Define pll_cal initial delay, which is the  time between RXON(TXON) and rxpll_cal_enable._x000D_ Unit is us.</comment>
        </bits>
      </reg>
      <reg name="pll_cal_setting1" protect="rw">
        <bits access="rw" name="pll_cal_freq_reg" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="adc_cal_setting" protect="rw">
        <bits access="rw" name="adc_cal_rstn_dr" pos="19" rst="0">
      </bits>
        <bits access="rw" name="adc_cal_rstn_reg" pos="18" rst="0">
      </bits>
        <bits access="rw" name="adc_ref_cal_init_delay" pos="17:14" rst="0">
      </bits>
        <bits access="rw" name="adc_ref_cal_polarity" pos="13" rst="0">
      </bits>
        <bits access="rw" name="adc_vref_vbit_dr" pos="12" rst="0">
      </bits>
        <bits access="rw" name="adc_vref_vbit_reg" pos="11:9" rst="0">
      </bits>
        <bits access="rw" name="adc_reg_cal_init_delay" pos="8:5" rst="0">
      </bits>
        <bits access="rw" name="adc_reg_cal_polarity" pos="4" rst="0">
      </bits>
        <bits access="rw" name="adc_vreg_vbit_dr" pos="3" rst="0">
      </bits>
        <bits access="rw" name="adc_vreg_vbit_reg" pos="2:0" rst="0">
      </bits>
      </reg>
      <reg name="cal_dr_setting" protect="rw">
        <bits access="rw" name="vco_pkd_cal_en_dr" pos="9" rst="0">
      </bits>
        <bits access="rw" name="vco_pkd_cal_en_reg" pos="8" rst="0">
      </bits>
        <bits access="rw" name="adc_ref_cal_en_dr" pos="7" rst="0">
      </bits>
        <bits access="rw" name="adc_ref_cal_en_reg" pos="6" rst="0">
      </bits>
        <bits access="rw" name="adc_reg_cal_en_dr" pos="5" rst="0">
      </bits>
        <bits access="rw" name="adc_reg_cal_en_reg" pos="4" rst="0">
      </bits>
        <bits access="rw" name="rxflt_cal_en_dr" pos="3" rst="0">
      </bits>
        <bits access="rw" name="rxflt_cal_en_reg" pos="2" rst="0">
      </bits>
        <bits access="rw" name="pll_cal_en_dr" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pll_cal_en_reg" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="cal_status" protect="r">
        <bits access="r" name="vco_pkd_cal_ready" pos="7" rst="0">
      </bits>
        <bits access="r" name="adc_ref_cal_ready" pos="6" rst="0">
      </bits>
        <bits access="r" name="adc_reg_cal_ready" pos="5" rst="0">
      </bits>
        <bits access="r" name="rxflt_cal_ready" pos="4" rst="0">
      </bits>
        <bits access="r" name="pll_cal_ready" pos="3" rst="0">
      </bits>
        <bits access="r" name="fm_self_cal_ready" pos="2" rst="0">
      </bits>
        <bits access="r" name="wf_self_cal_ready" pos="1" rst="0">
      </bits>
        <bits access="r" name="bt_self_cal_ready" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="cal_results0" protect="r">
        <bits access="r" name="vco_ibit" pos="29:26" rst="15">
      </bits>
        <bits access="r" name="vco_vbit" pos="25:22" rst="15">
      </bits>
        <bits access="r" name="adc_vref_vbit" pos="21:19" rst="0">
      </bits>
        <bits access="r" name="adc_vreg_vbit" pos="18:16" rst="0">
      </bits>
        <bits access="r" name="rxflt_cal_i_bit" pos="15:8" rst="128">
      </bits>
        <bits access="r" name="rxflt_cal_q_bit" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="cal_results1" protect="r">
        <bits access="r" name="vco_pkd_cal_out" pos="14" rst="0">
      </bits>
        <bits access="r" name="adc_cal_reg_out" pos="13" rst="0">
      </bits>
        <bits access="r" name="adc_cal_ref_out" pos="12" rst="0">
      </bits>
        <bits access="r" name="rxflt_cal_out_i" pos="11" rst="0">
      </bits>
        <bits access="r" name="rxflt_cal_out_q" pos="10" rst="0">
      </bits>
        <bits access="r" name="vco_band" pos="9:0" rst="512">
      </bits>
      </reg>
      <reg name="power_dr" protect="rw">
        <bits access="rw" name="pu_bg_dr" pos="21" rst="1">
      </bits>
        <bits access="rw" name="pu_fm_lna_dr" pos="20" rst="1">
      </bits>
        <bits access="rw" name="pu_fm_rmx_dr" pos="19" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_lna_dr" pos="18" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_tia_dr" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pu_pga_dr" pos="16" rst="1">
      </bits>
        <bits access="rw" name="pu_rxflt_dr" pos="15" rst="1">
      </bits>
        <bits access="rw" name="pu_adc_dr" pos="14" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_dac_dr" pos="13" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_padrv_dr" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_tmx_dr" pos="11" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_txrf_dr" pos="10" rst="1">
      </bits>
        <bits access="rw" name="pu_vco_dr" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pu_vco_txlo_dr" pos="8" rst="1">
      </bits>
        <bits access="rw" name="pu_vco_rxlo_dr" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pu_vco_pkd_dr" pos="6" rst="1">
      </bits>
        <bits access="rw" name="pu_pll_peri_dr" pos="5" rst="1">
      </bits>
        <bits access="rw" name="pu_pll_presc_dr" pos="4" rst="1">
      </bits>
        <bits access="rw" name="pu_pll_fm_lo_clk_dr" pos="3" rst="1">
      </bits>
        <bits access="rw" name="pu_pll_fm_adc_clk_dr" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pu_adpll_dr" pos="1" rst="1">
      </bits>
        <bits access="rw" name="pu_mdll_dr" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="power_reg" protect="rw">
        <bits access="rw" name="pu_bg_reg" pos="21" rst="1">
      </bits>
        <bits access="rw" name="pu_fm_lna_reg" pos="20" rst="1">
      </bits>
        <bits access="rw" name="pu_fm_rmx_reg" pos="19" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_lna_reg" pos="18" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_tia_reg" pos="17" rst="1">
      </bits>
        <bits access="rw" name="pu_pga_reg" pos="16" rst="1">
      </bits>
        <bits access="rw" name="pu_rxflt_reg" pos="15" rst="1">
      </bits>
        <bits access="rw" name="pu_adc_reg" pos="14" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_dac_reg" pos="13" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_padrv_reg" pos="12" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_tmx_reg" pos="11" rst="1">
      </bits>
        <bits access="rw" name="pu_bt_txrf_reg" pos="10" rst="1">
      </bits>
        <bits access="rw" name="pu_vco_reg" pos="9" rst="1">
      </bits>
        <bits access="rw" name="pu_vco_txlo_reg" pos="8" rst="1">
      </bits>
        <bits access="rw" name="pu_vco_rxlo_reg" pos="7" rst="1">
      </bits>
        <bits access="rw" name="pu_vco_pkd_reg" pos="6" rst="1">
      </bits>
        <bits access="rw" name="pu_pll_peri_reg" pos="5" rst="1">
      </bits>
        <bits access="rw" name="pu_pll_presc_reg" pos="4" rst="1">
      </bits>
        <bits access="rw" name="pu_pll_fm_lo_clk_reg" pos="3" rst="1">
      </bits>
        <bits access="rw" name="pu_pll_fm_adc_clk_reg" pos="2" rst="1">
      </bits>
        <bits access="rw" name="pu_adpll_reg" pos="1" rst="1">
      </bits>
        <bits access="rw" name="pu_mdll_reg" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="power_status" protect="r">
        <bits access="r" name="pu_bg" pos="21" rst="1">
      </bits>
        <bits access="r" name="pu_fm_lna" pos="20" rst="1">
      </bits>
        <bits access="r" name="pu_fm_rmx" pos="19" rst="1">
      </bits>
        <bits access="r" name="pu_bt_lna" pos="18" rst="1">
      </bits>
        <bits access="r" name="pu_bt_tia" pos="17" rst="1">
      </bits>
        <bits access="r" name="pu_pga" pos="16" rst="1">
      </bits>
        <bits access="r" name="pu_rxflt" pos="15" rst="1">
      </bits>
        <bits access="r" name="pu_adc" pos="14" rst="1">
      </bits>
        <bits access="r" name="pu_bt_dac" pos="13" rst="1">
      </bits>
        <bits access="r" name="pu_bt_padrv" pos="12" rst="1">
      </bits>
        <bits access="r" name="pu_bt_tmx" pos="11" rst="1">
      </bits>
        <bits access="r" name="pu_bt_txrf" pos="10" rst="1">
      </bits>
        <bits access="r" name="pu_vco" pos="9" rst="1">
      </bits>
        <bits access="r" name="pu_vco_txlo" pos="8" rst="1">
      </bits>
        <bits access="r" name="pu_vco_rxlo" pos="7" rst="1">
      </bits>
        <bits access="r" name="pu_vco_pkd" pos="6" rst="1">
      </bits>
        <bits access="r" name="pu_pll_peri" pos="5" rst="1">
      </bits>
        <bits access="r" name="pu_pll_presc" pos="4" rst="1">
      </bits>
        <bits access="r" name="pu_pll_fm_lo_clk" pos="3" rst="1">
      </bits>
        <bits access="r" name="pu_pll_fm_adc_clk" pos="2" rst="1">
      </bits>
        <bits access="r" name="pu_adpll" pos="1" rst="1">
      </bits>
        <bits access="r" name="pu_mdll" pos="0" rst="1">
      </bits>
      </reg>
      <reg name="bt_gain_table_0" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_0" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_0" pos="14:13" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_0" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_0" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_0" pos="6:4" rst="0">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_0" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="bt_gain_table_1" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_1" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_1" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_1" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_1" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_1" pos="6:4" rst="0">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_1" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="bt_gain_table_2" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_2" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_2" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_2" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_2" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_2" pos="6:4" rst="1">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_2" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="bt_gain_table_3" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_3" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_3" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_3" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_3" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_3" pos="6:4" rst="2">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_3" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="bt_gain_table_4" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_4" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_4" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_4" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_4" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_4" pos="6:4" rst="3">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_4" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="bt_gain_table_5" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_5" pos="16:15" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_5" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_5" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_5" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_5" pos="6:4" rst="3">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_5" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="bt_gain_table_6" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_6" pos="16:15" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_6" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_6" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_6" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_6" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_6" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="bt_gain_table_7" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_7" pos="16:15" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_7" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_7" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_7" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_7" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_7" pos="3:0" rst="1">
      </bits>
      </reg>
      <reg name="bt_gain_table_8" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_8" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_8" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_8" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_8" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_8" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_8" pos="3:0" rst="1">
      </bits>
      </reg>
      <reg name="bt_gain_table_9" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_9" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_9" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_9" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_9" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_9" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_9" pos="3:0" rst="3">
      </bits>
      </reg>
      <reg name="bt_gain_table_a" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_a" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_a" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_a" pos="12:11" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_a" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_a" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_a" pos="3:0" rst="3">
      </bits>
      </reg>
      <reg name="bt_gain_table_b" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_b" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_b" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_b" pos="12:11" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_b" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_b" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_b" pos="3:0" rst="7">
      </bits>
      </reg>
      <reg name="bt_gain_table_c" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_c" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_c" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_c" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_c" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_c" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_c" pos="3:0" rst="7">
      </bits>
      </reg>
      <reg name="bt_gain_table_d" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_d" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_d" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_d" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_d" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_d" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_d" pos="3:0" rst="11">
      </bits>
      </reg>
      <reg name="bt_gain_table_e" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_e" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_e" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_e" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_e" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_e" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_e" pos="3:0" rst="15">
      </bits>
      </reg>
      <reg name="bt_gain_table_f" protect="rw">
        <bits access="rw" name="bt_lna_gain1_bit_f" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="bt_lna_gain2_bit_f" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="bt_lna_gain3_bit_f" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="bt_lna_resf_bit_f" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="bt_pga_gain_bit_f" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="bt_rxflt_bt_gain_bit_f" pos="3:0" rst="15">
      </bits>
      </reg>
      <reg name="wf_gain_table_0" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_0" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_0" pos="14:13" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_0" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_0" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_0" pos="6:4" rst="0">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_0" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="wf_gain_table_1" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_1" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_1" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_1" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_1" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_1" pos="6:4" rst="0">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_1" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="wf_gain_table_2" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_2" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_2" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_2" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_2" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_2" pos="6:4" rst="1">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_2" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="wf_gain_table_3" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_3" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_3" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_3" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_3" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_3" pos="6:4" rst="2">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_3" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="wf_gain_table_4" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_4" pos="16:15" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_4" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_4" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_4" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_4" pos="6:4" rst="3">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_4" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="wf_gain_table_5" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_5" pos="16:15" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_5" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_5" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_5" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_5" pos="6:4" rst="3">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_5" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="wf_gain_table_6" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_6" pos="16:15" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_6" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_6" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_6" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_6" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_6" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="wf_gain_table_7" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_7" pos="16:15" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_7" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_7" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_7" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_7" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_7" pos="3:0" rst="1">
      </bits>
      </reg>
      <reg name="wf_gain_table_8" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_8" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_8" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_8" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_8" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_8" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_8" pos="3:0" rst="1">
      </bits>
      </reg>
      <reg name="wf_gain_table_9" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_9" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_9" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_9" pos="12:11" rst="0">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_9" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_9" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_9" pos="3:0" rst="3">
      </bits>
      </reg>
      <reg name="wf_gain_table_a" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_a" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_a" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_a" pos="12:11" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_a" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_a" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_a" pos="3:0" rst="3">
      </bits>
      </reg>
      <reg name="wf_gain_table_b" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_b" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_b" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_b" pos="12:11" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_b" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_b" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_b" pos="3:0" rst="7">
      </bits>
      </reg>
      <reg name="wf_gain_table_c" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_c" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_c" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_c" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_c" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_c" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_c" pos="3:0" rst="7">
      </bits>
      </reg>
      <reg name="wf_gain_table_d" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_d" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_d" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_d" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_d" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_d" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_d" pos="3:0" rst="11">
      </bits>
      </reg>
      <reg name="wf_gain_table_e" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_e" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_e" pos="14:13" rst="1">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_e" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_e" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_e" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_e" pos="3:0" rst="15">
      </bits>
      </reg>
      <reg name="wf_gain_table_f" protect="rw">
        <bits access="rw" name="wf_lna_gain1_bit_f" pos="16:15" rst="3">
      </bits>
        <bits access="rw" name="wf_lna_gain2_bit_f" pos="14:13" rst="2">
      </bits>
        <bits access="rw" name="wf_lna_gain3_bit_f" pos="12:11" rst="2">
      </bits>
        <bits access="rw" name="wf_lna_resf_bit_f" pos="10:7" rst="0">
      </bits>
        <bits access="rw" name="wf_pga_gain_bit_f" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="wf_rxflt_bt_gain_bit_f" pos="3:0" rst="15">
      </bits>
      </reg>
      <reg name="bt_tx_gain_table_0" protect="rw">
        <bits access="rw" name="txrf_pad_mode_0" pos="28" rst="0">
      </bits>
        <bits access="rw" name="txrf_gain_bit_0" pos="27:24" rst="0">
      </bits>
        <bits access="rw" name="txrf_att_en_0" pos="23:22" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_bias_ibit_0" pos="21:20" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_aux_vbit_0" pos="19:18" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_cas_vbit_0" pos="17:16" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_mode_1" pos="12" rst="0">
      </bits>
        <bits access="rw" name="txrf_gain_bit_1" pos="11:8" rst="0">
      </bits>
        <bits access="rw" name="txrf_att_en_1" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_bias_ibit_1" pos="5:4" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_aux_vbit_1" pos="3:2" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_cas_vbit_1" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="bt_tx_gain_table_1" protect="rw">
        <bits access="rw" name="txrf_pad_mode_2" pos="28" rst="0">
      </bits>
        <bits access="rw" name="txrf_gain_bit_2" pos="27:24" rst="1">
      </bits>
        <bits access="rw" name="txrf_att_en_2" pos="23:22" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_bias_ibit_2" pos="21:20" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_aux_vbit_2" pos="19:18" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_cas_vbit_2" pos="17:16" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_mode_3" pos="12" rst="0">
      </bits>
        <bits access="rw" name="txrf_gain_bit_3" pos="11:8" rst="3">
      </bits>
        <bits access="rw" name="txrf_att_en_3" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_bias_ibit_3" pos="5:4" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_aux_vbit_3" pos="3:2" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_cas_vbit_3" pos="1:0" rst="1">
      </bits>
      </reg>
      <reg name="bt_tx_gain_table_2" protect="rw">
        <bits access="rw" name="txrf_pad_mode_4" pos="28" rst="0">
      </bits>
        <bits access="rw" name="txrf_gain_bit_4" pos="27:24" rst="6">
      </bits>
        <bits access="rw" name="txrf_att_en_4" pos="23:22" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_bias_ibit_4" pos="21:20" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_aux_vbit_4" pos="19:18" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_cas_vbit_4" pos="17:16" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_mode_5" pos="12" rst="0">
      </bits>
        <bits access="rw" name="txrf_gain_bit_5" pos="11:8" rst="7">
      </bits>
        <bits access="rw" name="txrf_att_en_5" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_bias_ibit_5" pos="5:4" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_aux_vbit_5" pos="3:2" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_cas_vbit_5" pos="1:0" rst="1">
      </bits>
      </reg>
      <reg name="bt_tx_gain_table_3" protect="rw">
        <bits access="rw" name="txrf_pad_mode_6" pos="28" rst="0">
      </bits>
        <bits access="rw" name="txrf_gain_bit_6" pos="27:24" rst="11">
      </bits>
        <bits access="rw" name="txrf_att_en_6" pos="23:22" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_bias_ibit_6" pos="21:20" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_aux_vbit_6" pos="19:18" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_cas_vbit_6" pos="17:16" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_mode_7" pos="12" rst="0">
      </bits>
        <bits access="rw" name="txrf_gain_bit_7" pos="11:8" rst="15">
      </bits>
        <bits access="rw" name="txrf_att_en_7" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="txrf_pad_bias_ibit_7" pos="5:4" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_aux_vbit_7" pos="3:2" rst="1">
      </bits>
        <bits access="rw" name="txrf_pad_cas_vbit_7" pos="1:0" rst="1">
      </bits>
      </reg>
      <reg name="fm_gain_table_0" protect="rw">
        <bits access="rw" name="fm_lna_reg_ibit_0" pos="29:27" rst="2">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_0" pos="26:25" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_0" pos="24:23" rst="0">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_0" pos="22:20" rst="2">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_0" pos="19:16" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_reg_ibit_1" pos="13:11" rst="2">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_1" pos="10:9" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_1" pos="8:7" rst="0">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_1" pos="6:4" rst="3">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_1" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="fm_gain_table_1" protect="rw">
        <bits access="rw" name="fm_lna_reg_ibit_2" pos="29:27" rst="2">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_2" pos="26:25" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_2" pos="24:23" rst="0">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_2" pos="22:20" rst="4">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_2" pos="19:16" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_reg_ibit_3" pos="13:11" rst="2">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_3" pos="10:9" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_3" pos="8:7" rst="1">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_3" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_3" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="fm_gain_table_2" protect="rw">
        <bits access="rw" name="fm_lna_reg_ibit_4" pos="29:27" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_4" pos="26:25" rst="1">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_4" pos="24:23" rst="1">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_4" pos="22:20" rst="4">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_4" pos="19:16" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_reg_ibit_5" pos="13:11" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_5" pos="10:9" rst="1">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_5" pos="8:7" rst="2">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_5" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_5" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="fm_gain_table_3" protect="rw">
        <bits access="rw" name="fm_lna_reg_ibit_6" pos="29:27" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_6" pos="26:25" rst="2">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_6" pos="24:23" rst="2">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_6" pos="22:20" rst="4">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_6" pos="19:16" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_reg_ibit_7" pos="13:11" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_7" pos="10:9" rst="2">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_7" pos="8:7" rst="3">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_7" pos="6:4" rst="4">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_7" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="fm_gain_table_4" protect="rw">
        <bits access="rw" name="fm_lna_reg_ibit_8" pos="29:27" rst="4">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_8" pos="26:25" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_8" pos="24:23" rst="3">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_8" pos="22:20" rst="4">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_8" pos="19:16" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_reg_ibit_9" pos="13:11" rst="4">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_9" pos="10:9" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_9" pos="8:7" rst="3">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_9" pos="6:4" rst="5">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_9" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="fm_gain_table_5" protect="rw">
        <bits access="rw" name="fm_lna_reg_ibit_a" pos="29:27" rst="4">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_a" pos="26:25" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_a" pos="24:23" rst="3">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_a" pos="22:20" rst="6">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_a" pos="19:16" rst="0">
      </bits>
        <bits access="rw" name="fm_lna_reg_ibit_b" pos="13:11" rst="4">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_b" pos="10:9" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_b" pos="8:7" rst="3">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_b" pos="6:4" rst="7">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_b" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="fm_gain_table_6" protect="rw">
        <bits access="rw" name="fm_lna_reg_ibit_c" pos="29:27" rst="5">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_c" pos="26:25" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_c" pos="24:23" rst="3">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_c" pos="22:20" rst="7">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_c" pos="19:16" rst="4">
      </bits>
        <bits access="rw" name="fm_lna_reg_ibit_d" pos="13:11" rst="5">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_d" pos="10:9" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_d" pos="8:7" rst="3">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_d" pos="6:4" rst="7">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_d" pos="3:0" rst="8">
      </bits>
      </reg>
      <reg name="fm_gain_table_7" protect="rw">
        <bits access="rw" name="fm_lna_reg_ibit_e" pos="29:27" rst="5">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_e" pos="26:25" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_e" pos="24:23" rst="3">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_e" pos="22:20" rst="7">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_e" pos="19:16" rst="12">
      </bits>
        <bits access="rw" name="fm_lna_reg_ibit_f" pos="13:11" rst="5">
      </bits>
        <bits access="rw" name="fm_lna_gain_bit_f" pos="10:9" rst="3">
      </bits>
        <bits access="rw" name="fm_lna_rload_bit_f" pos="8:7" rst="3">
      </bits>
        <bits access="rw" name="fm_rmx_gain_bit_f" pos="6:4" rst="7">
      </bits>
        <bits access="rw" name="fm_rxflt_bt_gain_bit_f" pos="3:0" rst="14">
      </bits>
      </reg>
      <reg name="direct_gain_setting" protect="rw">
        <bits access="rw" name="bt_agc_gain_dr" pos="20" rst="0">
      </bits>
        <bits access="rw" name="bt_agc_gain_reg" pos="19:16" rst="15">
      </bits>
        <bits access="rw" name="wf_agc_gain_dr" pos="12" rst="0">
      </bits>
        <bits access="rw" name="wf_agc_gain_reg" pos="11:8" rst="15">
      </bits>
        <bits access="rw" name="fm_agc_gain_dr" pos="4" rst="0">
      </bits>
        <bits access="rw" name="fm_agc_gain_reg" pos="3:0" rst="15">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_reg0" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_0" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_0" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_1" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_1" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_reg1" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_2" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_2" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_3" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_3" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_reg2" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_4" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_4" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_5" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_5" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_reg3" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_6" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_6" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_7" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_7" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_reg4" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_8" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_8" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_9" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_9" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_reg5" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_a" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_a" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_b" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_b" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_reg6" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_c" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_c" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_d" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_d" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_reg7" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_e" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_e" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_f" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_f" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_reg8" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_c_lo" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_c_lo" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_d_lo" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_d_lo" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_reg9" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_e_lo" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_e_lo" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_f_lo" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_f_lo" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_rega" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_c_hi" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_c_hi" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_d_hi" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_d_hi" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="bt_rxflt_cal_bit_regb" protect="rw">
        <bits access="rw" name="bt_rxflt_cal_i_bit_e_hi" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_e_hi" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_i_bit_f_hi" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="bt_rxflt_cal_q_bit_f_hi" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_reg0" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_0" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_0" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_1" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_1" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_reg1" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_2" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_2" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_3" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_3" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_reg2" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_4" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_4" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_5" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_5" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_reg3" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_6" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_6" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_7" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_7" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_reg4" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_8" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_8" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_9" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_9" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_reg5" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_a" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_a" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_b" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_b" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_reg6" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_c" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_c" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_d" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_d" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_reg7" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_e" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_e" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_f" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_f" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_reg8" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_c_lo" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_c_lo" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_d_lo" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_d_lo" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_reg9" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_e_lo" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_e_lo" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_f_lo" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_f_lo" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_rega" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_c_hi" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_c_hi" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_d_hi" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_d_hi" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="wf_rxflt_cal_bit_regb" protect="rw">
        <bits access="rw" name="wf_rxflt_cal_i_bit_e_hi" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_e_hi" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_i_bit_f_hi" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="wf_rxflt_cal_q_bit_f_hi" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="fm_rxflt_cal_bit_reg0" protect="rw">
        <bits access="rw" name="fm_rxflt_cal_i_bit_0" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_0" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_i_bit_1" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_1" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="fm_rxflt_cal_bit_reg1" protect="rw">
        <bits access="rw" name="fm_rxflt_cal_i_bit_2" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_2" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_i_bit_3" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_3" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="fm_rxflt_cal_bit_reg2" protect="rw">
        <bits access="rw" name="fm_rxflt_cal_i_bit_4" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_4" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_i_bit_5" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_5" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="fm_rxflt_cal_bit_reg3" protect="rw">
        <bits access="rw" name="fm_rxflt_cal_i_bit_6" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_6" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_i_bit_7" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_7" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="fm_rxflt_cal_bit_reg4" protect="rw">
        <bits access="rw" name="fm_rxflt_cal_i_bit_8" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_8" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_i_bit_9" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_9" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="fm_rxflt_cal_bit_reg5" protect="rw">
        <bits access="rw" name="fm_rxflt_cal_i_bit_a" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_a" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_i_bit_b" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_b" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="fm_rxflt_cal_bit_reg6" protect="rw">
        <bits access="rw" name="fm_rxflt_cal_i_bit_c" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_c" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_i_bit_d" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_d" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="fm_rxflt_cal_bit_reg7" protect="rw">
        <bits access="rw" name="fm_rxflt_cal_i_bit_e" pos="31:24" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_e" pos="23:16" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_i_bit_f" pos="15:8" rst="128">
      </bits>
        <bits access="rw" name="fm_rxflt_cal_q_bit_f" pos="7:0" rst="128">
      </bits>
      </reg>
      <reg name="test_buf" protect="rw">
        <bits access="rw" name="refclk_lvds_en" pos="3" rst="0">
      </bits>
        <bits access="rw" name="tx_if_en" pos="2" rst="0">
      </bits>
        <bits access="rw" name="dac_out_en" pos="1" rst="0">
      </bits>
        <bits access="rw" name="pll_test_out_en" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="ana_reserved" protect="rw">
        <bits access="r" name="bw_rsvd_out" pos="31:24" rst="0">
      </bits>
        <bits access="rw" name="adpll_rsvd_in" pos="23:16" rst="240">
      </bits>
        <bits access="rw" name="bw_rsvd_in" pos="15:0" rst="65280">
      </bits>
      </reg>
      <reg name="dig_reserved" protect="rw">
        <bits access="rw" name="dig_rsvd" pos="15:0" rst="65280">
      </bits>
      </reg>
      <reg name="new_add" protect="rw">
        <bits access="rw" name="bt_dac_lp_mode2" pos="7:6" rst="0">
      </bits>
        <bits access="rw" name="pll_reg_digi_bit" pos="5:2" rst="8">
      </bits>
        <bits access="rw" name="txrf_capbank_en_dr" pos="1" rst="0">
      </bits>
        <bits access="rw" name="txrf_capbank_en_reg" pos="0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_sys_ctrl.xml">
    <module category="wcn" name="WCN_SYS_CTRL">
      <reg name="soft_reset" protect="rw">
        <bits access="rw" name="reg_sys_resetb" pos="31" rst="1">
          <comment>Global reset.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_dbg_hst_uart_rstb" pos="15" rst="1">
          <comment>debug host uart clock domain reset, active low</comment>
        </bits>
        <bits access="rw" name="reg_pulp_dbg_rstb" pos="14" rst="1">
          <comment>riscv debug unit rstb. Active low.</comment>
        </bits>
        <bits access="rw" name="reg_wdt_rst_sys_en" pos="13" rst="1">
          <comment>watch dog reset wcn system enable, 1 enable the reset, else no.</comment>
        </bits>
        <bits access="rw" name="reg_wakeup_ctrl_rstb" pos="12" rst="1">
          <comment>wake up logic reset.</comment>
        </bits>
        <bits access="rw" name="reg_bt_hresetn" pos="11" rst="1">
          <comment>for bt hclk reset.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_low_power_rstb" pos="10" rst="1">
          <comment>for bt 32k clock reset.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_uart_clk_rstb" pos="9" rst="1">
          <comment>uart clock domain reset.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_wdt_clk_rstb" pos="8" rst="1">
          <comment>watch dog clock domain reset, 32k actually.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_bt_master_rstb" pos="7" rst="1">
          <comment>bt master clock reset.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_bt_dbm_hresetn" pos="6" rst="1">
          <comment>bt core's debug master bus reset.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_aud_ifc_hresetn" pos="5" rst="1">
          <comment>AUDIFC function reset. Active low.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_sys_ifc_hresetn" pos="4" rst="1">
          <comment>sys_ifc module bus reset.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_jtag_hresetn" pos="3" rst="1">
          <comment>riscv jtag-&gt; ahb protocol bus reset.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_pulp_mcu_hresetn" pos="2" rst="0">
          <comment>riscv reset.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_mem_hresetn" pos="1" rst="1">
          <comment>bt_dig memory datapath reset.
1:: unreset
0:: reset</comment>
        </bits>
        <bits access="rw" name="reg_apb_presetn" pos="0" rst="1">
          <comment>not used, reserved</comment>
        </bits>
      </reg>
      <reg name="clk_cfg" protect="rw">
        <bits access="rw" name="reg_bus_clk_sel" pos="31:29" rst="0">
          <comment>bus clock selection: 0 sel hclk, 1 sel 26m, others sel 32k</comment>
        </bits>
        <bits access="rw" name="reg_wakeup_ctrl_clk_en" pos="28" rst="1">
          <comment>wake up logic clock enable</comment>
        </bits>
        <bits access="rw" name="bt_clksel" pos="27:22" rst="13">
          <comment>bt core master clock indicator, 13M as default.</comment>
        </bits>
        <bits access="rw" name="reg_bt_master_clk_denom" pos="21:18" rst="4">
          <comment>bt master clock divider's denom,  bt_master_clk = bus_clk/reg_bt_master_clk_denom</comment>
        </bits>
        <bits access="rs" name="reg_bt_master_clk_ld" pos="17" rst="0">
          <comment>bit type is changed from w1s to rs.
          load the bt_master_clk_denom into the clock divider.</comment>
        </bits>
        <bits access="rw" name="reg_master_clk_en" pos="16" rst="0">
          <comment>bt master clock divider enable, this divider source is hclk.</comment>
        </bits>
        <bits access="rw" name="reg_low_power_clk_en" pos="15" rst="1">
          <comment>low power clock enable for bt</comment>
        </bits>
        <bits access="rw" name="reg_jtag_hclk_en" pos="14" rst="1">
          <comment>jtag bus clock enable</comment>
        </bits>
        <bits access="rw" name="reg_sys_ifc_hclk_force_on" pos="13" rst="0">
          <comment>manually to set the sys_ifc bus clock to be open always.</comment>
        </bits>
        <bits access="rw" name="reg_sys_ifc_ch_hclk_force_on" pos="12:11" rst="0">
          <comment>manually to set the sys_ifc channels' clock to be open always.</comment>
        </bits>
        <bits access="rw" name="reg_aud_ifc_hclk_force_on" pos="10" rst="0">
          <comment>manually to set the aud_ifc bus clock to be open always.</comment>
        </bits>
        <bits access="rw" name="reg_aud_ifc_ch2_hclk_force_on" pos="9" rst="0">
          <comment>manually to set the aud_ifc channel 0' clock to be open always.</comment>
        </bits>
        <bits access="rw" name="reg_mem_hclk_en" pos="8" rst="1">
          <comment>bt_dig memory module's bus clock enable</comment>
        </bits>
        <bits access="rw" name="reg_bt_hclk_en" pos="7" rst="1">
          <comment>bt core's bus clock enable</comment>
        </bits>
        <bits access="rw" name="reg_bt_dbm_hclk_en" pos="6" rst="0">
          <comment>debug master bus clock enable</comment>
        </bits>
        <bits access="rw" name="reg_uart_clk_force_on" pos="5" rst="0">
          <comment>manually to set the uart clock to be open always.</comment>
        </bits>
        <bits access="rw" name="reg_uart_sys_clk_force_on" pos="4" rst="0">
          <comment>manually to set the uart sys(function) clock to be open always.</comment>
        </bits>
        <bits access="rw" name="reg_wdt_clk_en" pos="3" rst="1">
          <comment>watch dog clock enable</comment>
        </bits>
        <bits access="rw" name="reg_pulp_mcu_hclk_en" pos="2" rst="1">
          <comment>riscv bus clock enable</comment>
        </bits>
        <bits access="rw" name="reg_apb_reg_clk_force_on" pos="1" rst="0">
          <comment>apb bus clock to be open always.</comment>
        </bits>
        <bits access="rw" name="reg_mem_auto_ckg" pos="0" rst="1">
          <comment>memory access with clock enable.</comment>
        </bits>
      </reg>
      <reg name="clk_cfg1" protect="rw">
        <bits access="rw" name="reg_bt_13m_clk_en" pos="22" rst="1">
          <comment>13m from osc 26m, for bt master clock sel.</comment>
        </bits>
        <bits access="rw" name="reg_bt_master_clk_sel" pos="21:20" rst="2">
          <comment>bit[21] when 1 sel the result of bit[20], otherwise from hclk divider; bit [20] when 1 sel 26m otherwise 13m</comment>
        </bits>
        <bits access="rw" name="reg_bt_clk_en" pos="19" rst="0">
          <comment>bt_master_clk to bt core.</comment>
        </bits>
        <bits access="rw" name="sysifc_dbg_hclk_clk_en_force_on" pos="18" rst="1">
          <comment>ifc debug host dma hclk force on.</comment>
        </bits>
        <bits access="rw" name="dbg_hst_sys_clk_en_force_on" pos="17" rst="1">
          <comment>debug host pclk force enable</comment>
        </bits>
        <bits access="rw" name="dbg_uart_sys_clk_en_force_on" pos="16" rst="1">
          <comment>debug uart pclk force enable</comment>
        </bits>
        <bits access="rw" name="dbg_hst_uart_clk_en_force_on" pos="15" rst="1">
          <comment>debug host sclk force enable</comment>
        </bits>
        <bits access="rs" name="reg_uart_clk_div_ld_cfg" pos="14" rst="0">
          <comment>bit type is changed from w1s to rs.
          use new div parameters for divider.</comment>
        </bits>
        <bits access="rw" name="reg_uart_clk_div_en" pos="13" rst="1">
          <comment>uart clock divider enable.</comment>
        </bits>
        <bits access="rw" name="reg_uart_clk_denom" pos="12:0" rst="1">
          <comment>uart clock divider denom's configuration</comment>
        </bits>
      </reg>
      <reg name="clk_208m_cfg" protect="rw">
        <bits access="rs" name="reg_dbg_hst_uart_clk_ld_cfg" pos="31" rst="0">
          <comment>bit type is changed from w1s to rs.
          Debug host uart clock load configuration</comment>
        </bits>
        <bits access="rw" name="reg_dbg_hst_uart_clk_num" pos="30:21" rst="1">
          <comment>Debug host uart clock numerator</comment>
        </bits>
        <bits access="rw" name="reg_dbg_hst_uart_clk_denom" pos="20:11" rst="7">
          <comment>Debug host uart clock denominator</comment>
        </bits>
        <bits access="rw" name="reg_dbg_hst_div_en" pos="10" rst="1">
          <comment>Debug host clock divider enable</comment>
        </bits>
        <bits access="rs" name="reg_clk_208m_div_ld_cfg" pos="9" rst="0">
          <comment>bit type is changed from w1s to rs.
          use new div parameters for divider.</comment>
        </bits>
        <bits access="rw" name="reg_clk_208m_div_en" pos="8" rst="1">
          <comment>clock 208m divider enable.</comment>
        </bits>
        <bits access="rw" name="reg_clk_208m_num" pos="7:4" rst="1">
          <comment>clock 208m divider num's configuration</comment>
        </bits>
        <bits access="rw" name="reg_clk_208m_denom" pos="3:0" rst="2">
          <comment>clock 208m divider denom's configuration</comment>
        </bits>
      </reg>
      <reg name="sys_conn" protect="rw">
        <bits access="r" name="sys2bt_irq" pos="3" rst="0">
          <comment>sys to bt irq, read only for check</comment>
        </bits>
        <bits access="rw" name="reg_wdt_gen_irq2sys_en" pos="2" rst="1">
          <comment>wdt gen irq to system enable control, 1 indicates enable.</comment>
        </bits>
        <bits access="rw" name="bt2sys_wakeup" pos="1" rst="0">
          <comment>reserved for future use, the wakeup to sys now use comregs's.</comment>
        </bits>
        <bits access="rw" name="bt2sys_soft_int" pos="0" rst="0">
          <comment>generate interrupt to system</comment>
        </bits>
      </reg>
      <reg name="riscv_boot_addr" protect="rw">
        <bits access="rw" name="pulp_mcu_boot_addr" pos="31:0" rst="0">
          <comment>the start address for riscv</comment>
        </bits>
      </reg>
      <reg name="rf_cfg" protect="rw">
        <bits access="rw" name="rf_reg_src_sel" pos="0" rst="0">
          <comment>RF Register Interface Selection
1:: SPI
0:: APB</comment>
        </bits>
      </reg>
      <reg name="lvds_cfg" protect="rw">
        <bits access="rw" name="sdm_clk_div_sel" pos="6" rst="0">
          <comment>tx clk sel
1'b1::selected sdm div clk as tx clk</comment>
        </bits>
        <bits access="rw" name="sdm_clk_sel" pos="5" rst="0">
          <comment>tx clk sel
1'b1::selected sdm ref clk as tx clk</comment>
        </bits>
        <bits access="rw" name="reg_lvds_rx_mode" pos="4:3" rst="0">
          <comment>RX Mode
0:: BT
1:: FM
2:: WLAN</comment>
        </bits>
        <bits access="rw" name="reg_lvds_out_sel" pos="2" rst="0">
          <comment>Data Source for LVDS Output
1:: internal DFE TX
0:: internal ADC</comment>
        </bits>
        <bits access="rw" name="reg_lvds_dac" pos="1" rst="0">
          <comment>Data Source for Internal DAC
1:: external DFE TX
0:: internal DFE TX</comment>
        </bits>
        <bits access="rw" name="reg_lvds_adc" pos="0" rst="0">
          <comment>Data Source for Internal DFE RX
1:: external ADC
0:: internal ADC</comment>
        </bits>
      </reg>
      <reg name="debug_config" protect="rw">
        <bits access="rw" name="reg_dbg_trig_sel" pos="31:28" rst="0">
          <comment>Debug trigger selection</comment>
        </bits>
        <bits access="rw" name="reg_dbg_trig_en" pos="27" rst="0">
          <comment>The triger is forced to 0 when disabled.</comment>
        </bits>
        <bits access="rw" name="reg_dbg_clk_sel" pos="26:23" rst="0">
          <comment>Debug clock selection</comment>
        </bits>
        <bits access="rw" name="reg_dbg_clk_en" pos="22" rst="0">
          <comment>The debug clock is forced to 0 when disabled.</comment>
        </bits>
        <bits access="rw" name="reg_dbg_out_nibble_shift_mode" pos="8" rst="0">
          <comment>nibble shift mode
0:: nibble_shift_mode0
Ouptut is {dbg_out[11::0], dbg_out[15::12]}
1:: nibble_shift_mode1
Ouptut is {dbg_out[15::12], dbg_out[7::4], dbg_out[11::8], dbg_out[3::0]}</comment>
        </bits>
        <bits access="rw" name="reg_dbg_out_nibble_shift" pos="7" rst="0">
          <comment>nibble shift enable
0:: nibble_shift_disable
Output is dbg_out[15::0]
1:: nibble_shift_en
Output is prcoess according dbg_out_nibble_mode</comment>
        </bits>
        <bits access="rw" name="reg_dbg_out_byte_swap" pos="6" rst="0">
          <comment>Byte swap of dbg_out</comment>
        </bits>
        <bits access="rw" name="reg_dbg_out_nibble_swap" pos="5" rst="0">
          <comment>Half Byte swap of dbg_out</comment>
        </bits>
        <bits access="rw" name="reg_dbg_out_en" pos="4" rst="0">
          <comment>when 0, all the mux data is forced to be 0.</comment>
        </bits>
        <bits access="rw" name="reg_dbg_out_sel" pos="3:0" rst="0">
          <comment>Debug out selection</comment>
        </bits>
      </reg>
      <reg name="wakeup_ctrl_0" protect="rw">
        <bits access="rw" name="host2bt_ext_wakeup_en" pos="13" rst="0">
          <comment>enable external wakeup request</comment>
        </bits>
        <bits access="rw" name="host2bt_hci_break_wakeup_en" pos="12" rst="0">
          <comment>enable hci uart break wakeup request</comment>
        </bits>
        <bits access="rw" name="host2bt_hci_activity_wakeup_en" pos="11" rst="0">
          <comment>enable hci activity wakeup request</comment>
        </bits>
        <bits access="rw" name="bt2host_wakeup_mode" pos="10" rst="1">
          <comment>bt2host wakeup mode
1::level mode
0::pulse mode</comment>
        </bits>
        <bits access="rw" name="bt2host_wakeup_period" pos="9:0" rst="255">
          <comment>bt2host wakeup level mode active cycle</comment>
        </bits>
      </reg>
      <reg name="wakeup_ctrl_1" protect="rw">
        <bits access="s" name="bt2host_wakeup_trig" pos="0" rst="1">
          <comment>bit type is changed from wos to s.
          bt2host wakeup trigger</comment>
        </bits>
      </reg>
      <reg name="wakeup_status" protect="r">
        <bits access="r" name="bt2host_wakeup_status" pos="0" rst="0">
          <comment>bt2host wakeup status</comment>
        </bits>
      </reg>
      <reg name="extmem_offset" protect="rw">
        <bits access="rw" name="reg_extmem_offset_addr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="wcn2sys_offset" protect="rw">
        <bits access="rw" name="reg_wcn2sys_offset_addr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="audio_out_cfg" protect="rw">
        <bits access="rw" name="reg_i2s_sel" pos="0" rst="0">
          <comment>i2s_sel when 1, select the i2s output, else select the pcm.</comment>
        </bits>
      </reg>
      <reg name="pulp_tag_mem_cfg" protect="rw">
        <bits access="rw" name="tag_mem_cfg_shrink" pos="11:0" rst="162">
          <comment>LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)</comment>
        </bits>
      </reg>
      <reg name="pulp_data_mem_cfg" protect="rw">
        <bits access="rw" name="data_mem_cfg_shrink" pos="11:0" rst="162">
          <comment>LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)</comment>
        </bits>
      </reg>
      <reg name="wcn_rom_mem_cfg" protect="rw">
        <bits access="rw" name="rom_mem_cfg_shrink" pos="10:0" rst="74">
          <comment>LS+RME+RM(4Bits) + PGEN +KEN +EMA(3Bits)</comment>
        </bits>
      </reg>
      <reg name="wcn_dram_mem_cfg" protect="rw">
        <bits access="rw" name="dram_mem_cfg_shrink" pos="11:0" rst="162">
          <comment>LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)</comment>
        </bits>
      </reg>
      <reg name="wcn_bram_mem_cfg" protect="rw">
        <bits access="rw" name="bram_mem_cfg_shrink" pos="11:0" rst="162">
          <comment>LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)</comment>
        </bits>
      </reg>
      <reg name="bt_link_mem_cfg" protect="rw">
        <bits access="rw" name="bt_link_mem_cfg_shrink" pos="11:0" rst="162">
          <comment>LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)</comment>
        </bits>
      </reg>
      <reg name="bt_modem_mem_cfg" protect="rw">
        <bits access="rw" name="bt_modem_mem_cfg_shrink" pos="11:0" rst="162">
          <comment>LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)</comment>
        </bits>
      </reg>
      <reg name="wlan_mem_cfg" protect="rw">
        <bits access="rw" name="wlan_mem_cfg_shrink" pos="16:0" rst="2090">
          <comment>dual port: LS + RMEB + TEST1B + RMB(4Bits)+RMEA+TEST1A+RMA(4Bits)+RET1N+EMAA/EMB(3Bits)</comment>
        </bits>
      </reg>
      <reg name="plc_mem_cfg" protect="rw">
        <bits access="rw" name="plc_mem_cfg_shrink" pos="11:0" rst="162">
          <comment>LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits)</comment>
        </bits>
      </reg>
      <reg name="hclk_freq" protect="rw">
        <bits access="rw" name="wcn_hclk_freq" pos="7:0" rst="48">
          <comment>the unit is 1M, 48M in 8910m as default.</comment>
        </bits>
      </reg>
      <reg name="branch_addr" protect="rw">
        <bits access="rw" name="risc_branch_addr" pos="31:0" rst="570425344">
          <comment>the address for riscv branch from rom, configured by ap</comment>
        </bits>
      </reg>
      <reg name="revision_id" protect="r">
        <bits access="r" name="wcn_id" pos="7:0" rst="0">
      </bits>
      </reg>
      <hole size="32"/>
      <reg name="simu_rsvd" protect="rw">
        <bits access="rw" name="simu_rsvd_1" pos="15:8" rst="0">
          <comment>CPU Interactive reg1</comment>
        </bits>
        <bits access="rw" name="simu_rsvd_0" pos="7:0" rst="0">
          <comment>CPU Interactive reg0</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_sys_ifc.xml">
    <module category="wcn" name="WCN_SYS_IFC">
      <reg name="get_ch" protect="">
        <bits access="r" name="ch_to_use" pos="3:0" rst="0">
          <comment>This field indicates which standard channel to use.
Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy.
After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable_ in the control register of the channel to release the channel.
4'h0::use_ch0:   use Channel0
4'h1::use_ch1:   use Channel1
4'h2::use_ch2:   use Channel2
4'h3::use_ch3:   use Channel3
4'h4::use_ch4:   use Channel4
4'h5::use_ch5:   use Channel5
4'h6::use_ch6:   use Channel6
4'h7::use_ch7:   use Channel7
4'hf::all_busy:       all channels are busy</comment>
        </bits>
      </reg>
      <reg name="dma_status" protect="r">
        <bits access="r" name="ch_busy" pos="22:16" rst="0">
          <comment>This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is eNonebled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel</comment>
        </bits>
        <bits access="r" name="ch_enable" pos="7:0" rst="0">
          <comment>This register indicates which channel is eNonebled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example::
8'h00::all_ch_disabled:      all channel disabled
8'h01::ch0_enabled:          Ch0 enabled
8'h02::ch1_enabled:           Ch1 enabled
8'h04::ch2_enabled:           Ch2 enabled
8'h05::ch_0_2_enabled:     Ch0 and Ch2 enabled
8'h07::ch_0_1_2_enabled: Ch0, Ch1 and Ch2 enabled
8'hff::ch_all_enabled:          all channels eNonebled</comment>
        </bits>
      </reg>
      <reg name="debug_status" protect="r">
        <bits access="r" name="dbg_status" pos="0" rst="1">
          <comment>Debug Channel Status .
0:: dbg_ch_run: The debug channel is running (not idle)
1::dbg_ch_idle: The debug channel is in idle mode</comment>
        </bits>
      </reg>
      <hole size="32"/>
      <reg name="std_ch_0__std_ch_ctrl" protect="rw">
        <bits access="rw" name="flush" pos="16" rst="0">
          <comment>When one, flush the interNonel FIFO channel.
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel.
Before writting back this bit to zero the interNonel fifo must empty.</comment>
        </bits>
        <bits access="rw" name="req_src" pos="10:8" rst="7">
          <comment>Select DMA Request source
0:: SYS_ID_TX_UART
1:: SYS_ID_RX_UART
2:: SYS_ID_TX_SDMMC
3:: SYS_ID_RX_SDMMC
4:: SYS_ID_TX_SPI1
5:: SYS_ID_RX_SPI1
6:: SYS_ID_TX_DEBUG_UART
7:: SYS_ID_RX_DEBUG_UART</comment>
        </bits>
        <bits access="rw" name="size" pos="5" rst="0">
          <comment>Peripheral Size
0::per_size_8:   8-bit peripheral
1::per_size_32: 32-bit peripheral</comment>
        </bits>
        <bits access="rw" name="autodisable" pos="4" rst="1">
          <comment>Set Auto-disable_ mode
0::auto_disable_close:  when TC reach zero the channel is not automatically released.
1::auto_disable_open:  At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released.</comment>
        </bits>
        <bits access="rw" name="ch_wr_hw_exch" pos="3" rst="0">
          <comment>Set Auto-disable_ mode
0:: auto_dis_mode0:  when TC reach zero the channel is not automatically released.
1:: auto_dis_mode1:  At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released.</comment>
        </bits>
        <bits access="rw" name="ch_rd_hw_exch" pos="2" rst="0">
          <comment>Read FIFO data exchange high 8-bit and low 8-bit.
0:: Exchange
1:: No_exchange</comment>
        </bits>
        <bits access="rc" name="disable" pos="1" rst="0">
          <comment>bit type is changed from wrc to rc.
          Channel Disable, write one in this bit disable_ the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disable_d.</comment>
        </bits>
        <bits access="rc" name="enable" pos="0" rst="0">
          <comment>bit type is changed from wrc to rc.
          Channel Enable, write one in this bit eNoneble the channel.
When the channel is eNonebled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.</comment>
        </bits>
      </reg>
      <reg name="std_ch_0__std_ch_status" protect="r">
        <bits access="r" name="fifo_empty" pos="4" rst="1">
          <comment>The internal channel fifo is empty</comment>
        </bits>
        <bits access="r" name="enable" pos="0" rst="0">
          <comment>Enable bit, when '1' the channel is running</comment>
        </bits>
      </reg>
      <reg name="std_ch_0__std_ch_start_addr" protect="rw">
        <bits access="rw" name="start_addr" pos="31:0" rst="4294967295">
          <comment>AHB Address. This field represent the start address of the transfer.
For a 32-bit peripheral, this address must be aligned 32-bit.</comment>
        </bits>
      </reg>
      <reg name="std_ch_0__std_ch_tc" protect="rw">
        <bits access="rw" name="tc" pos="22:0" rst="8388607">
          <comment>Transfer Count, this field indicated the transfer size_ in bytes to perform.
During a transfer a write in this register add the new value to the current TC.
A read of this register return the current current transfer count.</comment>
        </bits>
      </reg>
      <reg name="std_ch_1__std_ch_ctrl" protect="rw">
        <bits access="rw" name="flush" pos="16" rst="0">
          <comment>When one, flush the interNonel FIFO channel.
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel.
Before writting back this bit to zero the interNonel fifo must empty.</comment>
        </bits>
        <bits access="rw" name="req_src" pos="10:8" rst="7">
          <comment>Select DMA Request source
0:: SYS_ID_TX_UART
1:: SYS_ID_RX_UART
2:: SYS_ID_TX_SDMMC
3:: SYS_ID_RX_SDMMC
4:: SYS_ID_TX_SPI1
5:: SYS_ID_RX_SPI1
6:: SYS_ID_TX_DEBUG_UART
7:: SYS_ID_RX_DEBUG_UART</comment>
        </bits>
        <bits access="rw" name="size" pos="5" rst="0">
          <comment>Peripheral Size
0::per_size_8:   8-bit peripheral
1::per_size_32: 32-bit peripheral</comment>
        </bits>
        <bits access="rw" name="autodisable" pos="4" rst="1">
          <comment>Set Auto-disable_ mode
0::auto_disable_close:  when TC reach zero the channel is not automatically released.
1::auto_disable_open:  At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released.</comment>
        </bits>
        <bits access="rw" name="ch_wr_hw_exch" pos="3" rst="0">
          <comment>Set Auto-disable_ mode
0:: auto_dis_mode0:  when TC reach zero the channel is not automatically released.
1:: auto_dis_mode1:  At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released.</comment>
        </bits>
        <bits access="rw" name="ch_rd_hw_exch" pos="2" rst="0">
          <comment>Read FIFO data exchange high 8-bit and low 8-bit.
0:: Exchange
1:: No_exchange</comment>
        </bits>
        <bits access="rc" name="disable" pos="1" rst="0">
          <comment>bit type is changed from wrc to rc.
          Channel Disable, write one in this bit disable_ the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disable_d.</comment>
        </bits>
        <bits access="rc" name="enable" pos="0" rst="0">
          <comment>bit type is changed from wrc to rc.
          Channel Enable, write one in this bit eNoneble the channel.
When the channel is eNonebled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer.</comment>
        </bits>
      </reg>
      <reg name="std_ch_1__std_ch_status" protect="r">
        <bits access="r" name="fifo_empty" pos="4" rst="1">
          <comment>The internal channel fifo is empty</comment>
        </bits>
        <bits access="r" name="enable" pos="0" rst="0">
          <comment>Enable bit, when '1' the channel is running</comment>
        </bits>
      </reg>
      <reg name="std_ch_1__std_ch_start_addr" protect="rw">
        <bits access="rw" name="start_addr" pos="31:0" rst="4294967295">
          <comment>AHB Address. This field represent the start address of the transfer.
For a 32-bit peripheral, this address must be aligned 32-bit.</comment>
        </bits>
      </reg>
      <reg name="std_ch_1__std_ch_tc" protect="rw">
        <bits access="rw" name="tc" pos="22:0" rst="8388607">
          <comment>Transfer Count, this field indicated the transfer size_ in bytes to perform.
During a transfer a write in this register add the new value to the current TC.
A read of this register return the current current transfer count.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_systick.xml">
    <module category="wcn" name="WCN_SYSTICK">
      <reg name="csr" protect="rw">
        <bits access="r" name="countflag" pos="16" rst="0">
          <comment>indicates the counter decreasing to 0.</comment>
        </bits>
        <bits access="rw" name="clksrc" pos="2" rst="1">
          <comment>indicates clock source, 0 is reference clock, 1 is mcu clk.</comment>
        </bits>
        <bits access="rw" name="tickint" pos="1" rst="0">
          <comment>interrupte enable</comment>
        </bits>
        <bits access="rw" name="enable" pos="0" rst="0">
          <comment>systick counter enable</comment>
        </bits>
      </reg>
      <reg name="rvr" protect="rw">
        <bits access="rw" name="val" pos="23:0" rst="0">
          <comment>the value to load into cvr when counter decreases to 0.</comment>
        </bits>
      </reg>
      <reg name="cvr" protect="rw">
        <bits access="rw" name="val" pos="23:0" rst="0">
          <comment>the current cvr value.</comment>
        </bits>
      </reg>
      <reg name="calib" protect="rw">
        <bits access="rw" name="noref" pos="31" rst="0">
          <comment>indicates whether ref clk is implemented. 0 means implemented.</comment>
        </bits>
        <bits access="rw" name="skew" pos="30" rst="0">
          <comment>indicates whether 10ms calibration value is exact.</comment>
        </bits>
        <bits access="rw" name="tenms" pos="23:0" rst="0">
          <comment>calibration value of the reload value to be used for 10ms timing</comment>
        </bits>
      </reg>
      <reg name="clr" protect="rw">
        <bits access="w" name="en" pos="0" rst="0">
          <comment>clear the interrupte.</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_trap.xml">
    <module category="wcn" name="WCN_TRAP">
      <reg name="addr_in_0" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_1" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_2" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_3" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_4" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_5" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_6" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_7" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_8" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_9" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_10" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_11" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_12" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_13" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_14" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_15" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_16" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_17" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_18" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_19" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_20" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_21" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_22" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_23" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_24" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_25" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_26" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_27" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_28" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_29" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_30" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="addr_in_31" protect="rw">
        <bits access="rw" name="addr_in" pos="17:0" rst="0">
          <comment>address to be trapped. Range 0x00000000~0x0003fffc</comment>
        </bits>
      </reg>
      <reg name="trap_en" protect="rw">
        <bits access="rw" name="en" pos="31:0" rst="0">
          <comment>trap enable for 32 channels</comment>
        </bits>
      </reg>
      <reg name="addr_out" protect="rw">
        <bits access="rw" name="addr_out_base" pos="31:0" rst="0">
          <comment>base address to trapped to. Should be 32 words aligned (such as 0x00053e80 or 0x0004ff00).For the nth patch, the actual address is trap_out_base+4n</comment>
        </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_uart.xml">
    <module category="wcn" name="WCN_UART">
      <reg name="ctrl" protect="rw">
        <bits access="rw" name="rx_break_length" pos="31:28" rst="15">
          <comment>Length of a break, in number of bits.</comment>
        </bits>
        <bits access="rw" name="rx_lock_err" pos="25" rst="0">
          <comment>Allow to stop the data receiving when an error is detected (framing, parity or break). The data in the fifo are kept.</comment>
        </bits>
        <bits access="rw" name="loop_back_mode" pos="24" rst="0">
          <comment>When set, data on the Uart_Tx line is held high, while the serial output is looped back to the serial input line, internally. In this mode all the interrupts are fully functional. This feature is used for diagnostic purposes. Also, in loop back mode, the modem control input Uart_CTS is disconnected and the modem control output Uart_RTS are looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is inverted (see IrDA SIR Mode Support).</comment>
        </bits>
        <bits access="rw" name="auto_flow_control" pos="23" rst="0">
          <comment>Enables the auto flow control. Uart_RTS is controlled by the Rx RTS bit and the UART Auto Control Flow System. If Uart_CTS become inactive high, the Tx data flow is stopped.
1::ENABLE
0:: DISABLE</comment>
        </bits>
        <bits access="rw" name="dma_mode" pos="22" rst="0">
          <comment>Enables the DMA signaling for the Uart_Dma_Tx_Req_H and Uart_Dma_Rx_Req_H to the IFC.
0:: DISABLE
1::ENABLE</comment>
        </bits>
        <bits access="rw" name="irda_enable" pos="21" rst="0">
          <comment>When set, the UART is in IrDA mode and the baud rate divisor used is 16 (see UART Operation for details).</comment>
        </bits>
        <bits access="rw" name="divisor_mode" pos="20" rst="0">
          <comment>Selects the divisor value used to generate the baud rate frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA is enable, this bit is ignored and the divisor used will be 16.
0 = (BCLK = SCLK / 4)
1 = (BCLK = SCLK / 16)
0:div_4
1:div_16</comment>
        </bits>
        <bits access="rw" name="parity_select" pos="5:4" rst="0">
          <comment>Controls the parity format when parity is enabled:
0::odd: an odd number of received 1 bits is checked, or transmitted (the parity bit is included).
1::even: an even number of received 1 bits is checked or transmitted (the parity bit is included).
2::space: space a space is generated and received as parity bit.
3::mark: a mark is generated and received as parity bit.</comment>
        </bits>
        <bits access="rw" name="parity_enable" pos="3" rst="0">
          <comment>Parity is enabled when this bit is set.
0::NO
1:: YES</comment>
        </bits>
        <bits access="rw" name="tx_stop_bits" pos="2" rst="0">
          <comment>Stop bits controls the number of stop bits transmitted. Can receive with one stop bit (more inaccuracy can be compensated with two stop bits when divisor mode is set to 0).
0::1_bit :one stop bit is transmitted in the serial data.
1:: 2_bits:two stop bits are generated and transmitted in the serial data out.</comment>
        </bits>
        <bits access="rw" name="data_bits" pos="1" rst="0">
          <comment>Number of data bits per character (least significant bit first):
0::7_bits
1::8_bits</comment>
        </bits>
        <bits access="rw" name="enable" pos="0" rst="0">
          <comment>Allows to turn off the UART:
0:: Disable
1::Enable</comment>
        </bits>
      </reg>
      <reg name="status" protect="r">
        <bits access="r" name="clk_enabled" pos="31" rst="0">
          <comment>This bit is set when Uart Clk has been enabled and received by UART after Need Uart Clock becomes active. It serves to avoid enabling RTS too early.</comment>
        </bits>
        <bits access="r" name="dtr" pos="28" rst="0">
          <comment>Current value of the DTR line.</comment>
        </bits>
        <bits access="r" name="cts" pos="25" rst="1">
          <comment>current value of the Uart_CTS line.
1::Tx_allow_n:Tx not allowed.
0::Tx_alllow:Tx allowed.</comment>
        </bits>
        <bits access="r" name="dcts" pos="24" rst="0">
          <comment>This bit is set when the Uart_CTS line changed since the last time this register has been written. This bit is cleared when the UART_STATUS register is written with any value.</comment>
        </bits>
        <bits access="r" name="rx_break_int" pos="20" rst="0">
          <comment>This bit is set whenever the serial input is held in a logic 0 state for longer than the length of x bits, where x is the value programmed Rx Break Length. A null word will be written in the Rx Fifo. This bit is cleared when the UART_STATUS register is written with any value.</comment>
        </bits>
        <bits access="r" name="rx_framing_err" pos="19" rst="0">
          <comment>This bit is set whenever there is a framing error occured. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. This bit is cleared when the UART_STATUS register is written with any value.</comment>
        </bits>
        <bits access="r" name="rx_parity_err" pos="18" rst="0">
          <comment>This bit is set if the parity is enabled and a parity error occurred in the received data. This bit is cleared when the UART_STATUS register is written with any value.</comment>
        </bits>
        <bits access="r" name="tx_overflow_err" pos="17" rst="0">
          <comment>This bit indicates that the user tried to write a character when fifo was already full. The written data will not be kept. This bit is cleared when the UART_STATUS register is written with any value.</comment>
        </bits>
        <bits access="r" name="rx_overflow_err" pos="16" rst="0">
          <comment>This bit indicates that the receiver received a new character when the fifo was already full. The new character is discarded. This bit is cleared when the UART_STATUS register is written with any value.</comment>
        </bits>
        <bits access="r" name="rx_active" pos="15" rst="0">
          <comment>This bit indicates that the UART is receiving a byte.</comment>
        </bits>
        <bits access="r" name="tx_active" pos="14" rst="0">
          <comment>This bit indicates that the UART is sending data. If no data is in the fifo, the UART is currently sending the last one through the serial interface.</comment>
        </bits>
        <bits access="r" name="tx_fifo_space" pos="12:8" rst="0">
          <comment>Those bits indicate the number of space available in the Tx Fifo.</comment>
        </bits>
        <bits access="r" name="rx_fifo_level" pos="6:0" rst="0">
          <comment>Those bits indicate the number of data available in the Rx Fifo. Those data can be read.</comment>
        </bits>
      </reg>
      <reg name="rxtx_buffer" protect="rw">
        <bits access="rw" name="data" pos="7:0" rst="0">
          <comment>The UART_TRANSMIT_HOLDING register is a write-only register that contains data to be transmitted on the serial output port. 16 characters of data may be written to the UART_TRANSMIT_HOLDING register before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost.</comment>
        </bits>
      </reg>
      <reg name="irq_mask" protect="rw">
        <bits access="rw" name="dtr_fall" pos="9" rst="0">
          <comment>Falling edge detected on the UART_DTR signal.</comment>
        </bits>
        <bits access="rw" name="dtr_rise" pos="8" rst="0">
          <comment>Rising edge detected on the UART_DTR signal.</comment>
        </bits>
        <bits access="rw" name="rx_dma_timeout" pos="7" rst="0">
          <comment>In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times.</comment>
        </bits>
        <bits access="rw" name="rx_dma_done" pos="6" rst="0">
          <comment>Pulse detected on Uart_Dma_Rx_Done_H signal</comment>
        </bits>
        <bits access="rw" name="tx_dma_done" pos="5" rst="0">
          <comment>Pulse detected on Uart_Dma_Tx_Done_H signal.</comment>
        </bits>
        <bits access="rw" name="rx_line_err" pos="4" rst="0">
          <comment>Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt.</comment>
        </bits>
        <bits access="rw" name="rx_timeout" pos="3" rst="0">
          <comment>No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time.</comment>
        </bits>
        <bits access="rw" name="tx_data_needed" pos="2" rst="0">
          <comment>Tx Fifo at or below threshold level (current level &lt;= Tx Fifo trigger level).</comment>
        </bits>
        <bits access="rw" name="rx_data_available" pos="1" rst="0">
          <comment>Rx Fifo at or upper threshold level (current level &gt;= Rx Fifo trigger level).</comment>
        </bits>
        <bits access="rw" name="tx_modem_status" pos="0" rst="0">
          <comment>Clear to send signal change detected.</comment>
        </bits>
      </reg>
      <reg name="irq_cause" protect="r">
        <bits access="r" name="dtr_fall_u" pos="25" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="dtr_rise_u" pos="24" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="rx_dma_timeout_u" pos="23" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="rx_dma_done_u" pos="22" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="tx_dma_done_u" pos="21" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="rx_line_err_u" pos="20" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="rx_timeout_u" pos="19" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="tx_data_needed_u" pos="18" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="rx_data_available_u" pos="17" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="tx_modem_status_u" pos="16" rst="0">
          <comment>Same as previous, not masked.</comment>
        </bits>
        <bits access="r" name="dtr_fall" pos="9" rst="0">
          <comment>This interrupt is generated when a falling edge is detected on the UART_DTR signal. Reset control: Write one in this register.</comment>
        </bits>
        <bits access="r" name="dtr_rise" pos="8" rst="0">
          <comment>This interrupt is generated when a rising edge is detected on the UART_DTR signal. Reset control: Write one in this register.</comment>
        </bits>
        <bits access="r" name="rx_dma_timeout" pos="7" rst="0">
          <comment>In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times.</comment>
        </bits>
        <bits access="r" name="rx_dma_done" pos="6" rst="0">
          <comment>This interrupt is generated when a pulse is detected on the Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register.</comment>
        </bits>
        <bits access="r" name="tx_dma_done" pos="5" rst="0">
          <comment>This interrupt is generated when a pulse is detected on the Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register.</comment>
        </bits>
        <bits access="r" name="rx_line_err" pos="4" rst="0">
          <comment>Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Reset control: This bit is cleared when the UART_STATUS register is written with any value.</comment>
        </bits>
        <bits access="r" name="rx_timeout" pos="3" rst="0">
          <comment>No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Reset control: Reading from the UART_RECEIVE_BUFFER register.</comment>
        </bits>
        <bits access="r" name="tx_data_needed" pos="2" rst="0">
          <comment>Tx Fifo at or below threshold level (current level &lt;= Tx Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING register above threshold level.</comment>
        </bits>
        <bits access="r" name="rx_data_available" pos="1" rst="0">
          <comment>Rx Fifo at or upper threshold level (current level &gt;= Rx Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER until the Fifo drops below the trigger level.</comment>
        </bits>
        <bits access="r" name="tx_modem_status" pos="0" rst="0">
          <comment>Clear to send signal detected. Reset control: This bit is cleared when the UART_STATUS register is written with any value.</comment>
        </bits>
      </reg>
      <reg name="triggers" protect="rw">
        <bits access="rw" name="afc_level" pos="21:16" rst="0">
          <comment>Controls the Rx Fifo level at which the Uart_RTS Auto Flow Control will be set inactive high (see UART Operation for more details on AFC).
The Uart_RTS Auto Flow Control will be set inactive high when quantity of data in Rx Fifo &gt; AFC Level.</comment>
        </bits>
        <bits access="rw" name="tx_trigger" pos="11:8" rst="0">
          <comment>Defines the empty threshold level at which the Data Needed Interrupt will be generated.
The Data Needed Interrupt is generated when quantity of data in Tx Fifo &lt;= Tx Trigger.</comment>
        </bits>
        <bits access="rw" name="rx_trigger" pos="5:0" rst="0">
          <comment>Defines the empty threshold level at which the Data Available Interrupt will be generated.
The Data Available interrupt is generated when quantity of data in Rx Fifo &gt; Rx Trigger.</comment>
        </bits>
      </reg>
      <reg name="cmd_set" protect="rw">
        <bits access="w" name="tx_fifo_reset" pos="7" rst="0">
          <comment>Writing a 1 to this bit resets and flushes the Transmit Fifo. This bit does not need to be cleared.</comment>
        </bits>
        <bits access="w" name="rx_fifo_reset" pos="6" rst="0">
          <comment>Writing a 1 to this bit resets and flushes the Receive Fifo. This bit does not need to be cleared.</comment>
        </bits>
        <bits access="rs" name="rx_rts" pos="5" rst="0">
          <comment>bit type is changed from w1s to rs.
          this bit is set to 1 when writing 1, cleared to 0 when corresponding filed is cleared in UART_CMD_CLR</comment>
        </bits>
        <bits access="rs" name="tx_finish_n_wait" pos="4" rst="0">
          <comment>bit type is changed from w1s to rs.
          refer to bit [5]</comment>
        </bits>
        <bits access="rs" name="tx_break_control" pos="3" rst="0">
          <comment>bit type is changed from w1s to rs.
          refer to bit [5]</comment>
        </bits>
        <bits access="rs" name="dsr" pos="2" rst="0">
          <comment>bit type is changed from w1s to rs.
          refer to bit [5]</comment>
        </bits>
        <bits access="rs" name="dcd" pos="1" rst="0">
          <comment>bit type is changed from w1s to rs.
          refer to bit [5]</comment>
        </bits>
        <bits access="rs" name="ri" pos="0" rst="0">
          <comment>bit type is changed from w1s to rs.
          refer to bit [5]</comment>
        </bits>
      </reg>
      <reg name="cmd_clr" protect="rw">
        <bits access="rc" name="rx_cpu_rts" pos="5" rst="0">
          <comment>bit type is changed from w1c to rc.
          this bit is cleared to 0 when writing 1, set to 1 when corresponding filed is set in UART_CMD_SET</comment>
        </bits>
        <bits access="rc" name="tx_finish_n_wait" pos="4" rst="0">
          <comment>bit type is changed from w1c to rc.
          refer to bit [5]</comment>
        </bits>
        <bits access="rc" name="tx_break_control" pos="3" rst="0">
          <comment>bit type is changed from w1c to rc.
          refer to bit [5]</comment>
        </bits>
        <bits access="rc" name="dsr" pos="2" rst="0">
          <comment>bit type is changed from w1c to rc.
          refer to bit [5]</comment>
        </bits>
        <bits access="rc" name="dcr" pos="1" rst="0">
          <comment>bit type is changed from w1c to rc.
          refer to bit [5]</comment>
        </bits>
        <bits access="rc" name="ri" pos="0" rst="0">
          <comment>bit type is changed from w1c to rc.
          refer to bit [5]</comment>
        </bits>
      </reg>
      <reg name="auto_baud" protect="rw">
        <bits access="rw" name="verify_char1" pos="23:16" rst="84">
      </bits>
        <bits access="rw" name="verify_char0" pos="15:8" rst="65">
      </bits>
        <bits access="rw" name="verify_2byte" pos="2" rst="0">
      </bits>
        <bits access="rw" name="auto_tracking" pos="1" rst="0">
      </bits>
        <bits access="rw" name="auto_enable" pos="0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_wdt.xml">
    <module category="wcn" name="WCN_WDT">
      <reg name="wdt_cvr0" protect="rw">
        <bits access="rw" name="count_vaule_0" pos="23:0" rst="16777215">
          <comment>wdt_cvr0_count_value_0</comment>
        </bits>
      </reg>
      <reg name="wdt_cvr1" protect="rw">
        <bits access="rw" name="count_vaule_1" pos="23:0" rst="16777215">
          <comment>wdt_cvr1_count_value_1</comment>
        </bits>
      </reg>
      <reg name="wdt_cr" protect="rw">
        <bits access="rw" name="cr_mode" pos="4" rst="0">
      </bits>
        <bits access="rw" name="cr_reset_length" pos="2:0" rst="0">
      </bits>
      </reg>
      <reg name="wdt_cmd" protect="rw">
        <bits access="rw" name="cmd_cmd" pos="7:0" rst="0">
      </bits>
      </reg>
      <reg name="wdt_icr" protect="rw">
        <bits access="rw" name="int_clr" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="wdt_sr" protect="r">
        <bits access="r" name="wdt_active" pos="1" rst="0">
      </bits>
        <bits access="r" name="int_assert" pos="0" rst="0">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="wcn_wlan.xml">
    <module category="wcn" name="WCN_WLAN">
      <hole size="32"/>
      <reg name="phy_reg_bank_addr" protect="rw">
        <bits access="rw" name="phy_reg_bank_addr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="phy_reg_offset_addr" protect="rw">
        <bits access="rw" name="phy_reg_offset_addr" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="phy_reg_write_data" protect="rw">
        <bits access="rw" name="phy_reg_write_data" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="phy_reg_read_data" protect="rw">
        <bits access="rw" name="phy_reg_read_data" pos="31:0" rst="135">
      </bits>
      </reg>
      <reg name="protocol_version" protect="r">
        <bits access="r" name="protocol_version" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="type" protect="r">
        <bits access="r" name="tp" pos="1:0" rst="0">
      </bits>
      </reg>
      <reg name="sub_type" protect="r">
        <bits access="r" name="sub_type" pos="3:0" rst="0">
      </bits>
      </reg>
      <reg name="desaddr_l" protect="r">
        <bits access="r" name="desaddr_l" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="desaddr_h" protect="r">
        <bits access="r" name="desaddr_h" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="srcaddr_l" protect="r">
        <bits access="r" name="srcaddr_l" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="srcaddr_h" protect="r">
        <bits access="r" name="srcaddr_h" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="bssidaddr_l" protect="r">
        <bits access="r" name="bssidaddr_l" pos="31:0" rst="0">
      </bits>
      </reg>
      <reg name="bssidaddr_h" protect="r">
        <bits access="r" name="bssidaddr_h" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="seqcontrol" protect="r">
        <bits access="r" name="seqcontrol" pos="15:0" rst="0">
      </bits>
      </reg>
      <reg name="rssival" protect="r">
        <bits access="r" name="rssival" pos="7:0" rst="0">
      </bits>
      </reg>
      <hole size="512"/>
      <reg name="config_reg" protect="rw">
        <bits access="rw" name="phyrx_en_b" pos="16" rst="1">
          <comment>0: enalbe, 1: disable</comment>
        </bits>
        <bits access="rw" name="type_config_reg" pos="13:12" rst="0">
      </bits>
        <bits access="rw" name="subtype_config_reg" pos="11:8" rst="8">
      </bits>
        <bits access="rw" name="apb_hold" pos="1" rst="1">
      </bits>
        <bits access="rw" name="apb_clear" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="datardyint" protect="r">
        <bits access="r" name="datardyint" pos="0" rst="0">
      </bits>
      </reg>
      <reg name="phy_sel_set0" protect="rw">
        <bits access="rw" name="phy_sel_3_reg" pos="29:24" rst="3">
      </bits>
        <bits access="rw" name="phy_sel_2_reg" pos="21:16" rst="2">
      </bits>
        <bits access="rw" name="phy_sel_1_reg" pos="13:8" rst="1">
      </bits>
        <bits access="rw" name="phy_sel_0_reg" pos="5:0" rst="0">
      </bits>
      </reg>
      <reg name="phy_sel_set2" protect="rw">
        <bits access="rw" name="phy_sel_7_reg" pos="29:24" rst="7">
      </bits>
        <bits access="rw" name="phy_sel_6_reg" pos="21:16" rst="6">
      </bits>
        <bits access="rw" name="phy_sel_5_reg" pos="13:8" rst="5">
      </bits>
        <bits access="rw" name="phy_sel_4_reg" pos="5:0" rst="4">
      </bits>
      </reg>
      <reg name="phy_sel_set3" protect="rw">
        <bits access="rw" name="phy_sel_11_reg" pos="29:24" rst="11">
      </bits>
        <bits access="rw" name="phy_sel_10_reg" pos="21:16" rst="10">
      </bits>
        <bits access="rw" name="phy_sel_9_reg" pos="13:8" rst="9">
      </bits>
        <bits access="rw" name="phy_sel_8_reg" pos="5:0" rst="8">
      </bits>
      </reg>
      <reg name="phy_sel_set4" protect="rw">
        <bits access="rw" name="phy_sel_15_reg" pos="29:24" rst="15">
      </bits>
        <bits access="rw" name="phy_sel_14_reg" pos="21:16" rst="14">
      </bits>
        <bits access="rw" name="phy_sel_13_reg" pos="13:8" rst="13">
      </bits>
        <bits access="rw" name="phy_sel_12_reg" pos="5:0" rst="12">
      </bits>
      </reg>
      <reg name="phy_sel_set5" protect="rw">
        <bits access="rw" name="phy_sel_19_reg" pos="29:24" rst="19">
      </bits>
        <bits access="rw" name="phy_sel_18_reg" pos="21:16" rst="18">
      </bits>
        <bits access="rw" name="phy_sel_17_reg" pos="13:8" rst="17">
      </bits>
        <bits access="rw" name="phy_sel_16_reg" pos="5:0" rst="16">
      </bits>
      </reg>
      <reg name="phy_sel_set6" protect="rw">
        <bits access="rw" name="phy_sel_23_reg" pos="29:24" rst="23">
      </bits>
        <bits access="rw" name="phy_sel_22_reg" pos="21:16" rst="22">
      </bits>
        <bits access="rw" name="phy_sel_21_reg" pos="13:8" rst="21">
      </bits>
        <bits access="rw" name="phy_sel_20_reg" pos="5:0" rst="20">
      </bits>
      </reg>
      <reg name="phy_sel_set7" protect="rw">
        <bits access="rw" name="phy_sel_27_reg" pos="29:24" rst="27">
      </bits>
        <bits access="rw" name="phy_sel_26_reg" pos="21:16" rst="26">
      </bits>
        <bits access="rw" name="phy_sel_25_reg" pos="13:8" rst="25">
      </bits>
        <bits access="rw" name="phy_sel_24_reg" pos="5:0" rst="24">
      </bits>
      </reg>
      <reg name="phy_sel_set8" protect="rw">
        <bits access="rw" name="phy_sel_31_reg" pos="29:24" rst="31">
      </bits>
        <bits access="rw" name="phy_sel_30_reg" pos="21:16" rst="30">
      </bits>
        <bits access="rw" name="phy_sel_29_reg" pos="13:8" rst="29">
      </bits>
        <bits access="rw" name="phy_sel_28_reg" pos="5:0" rst="28">
      </bits>
      </reg>
    </module>
  </archive>
  <archive relative="rda8910m_hard.xml">
    <include file="globals.xml"/>
    <include file="global_macros.xml"/>
    <include file="gallite_generic_config.xml"/>
    <include file="debug_host.xml"/>
    <include file="debug_host_internals.xml"/>
    <include file="debug_uart.xml"/>
    <include file="arm_axidma.xml"/>
    <include file="aes.xml"/>
    <include file="lzma.xml"/>
    <include file="f8.xml"/>
    <include file="fpi3_gprs.xml"/>
    <include file="gouda.xml"/>
    <include file="lcdc.xml"/>
    <include file="spi_flash.xml"/>
    <include file="gic400_reg.xml"/>
    <include file="gpio.xml"/>
    <include file="i2c_master.xml"/>
    <include file="pagespy_dmc.xml"/>
    <include file="vad.xml"/>
    <include file="sci.xml"/>
    <include file="lps.xml"/>
    <include file="spi.xml"/>
    <include file="sys_ctrl.xml"/>
    <include file="iomux.xml"/>
    <include file="spinlock.xml"/>
    <include file="efuse_ctrl.xml"/>
    <include file="ap_ifc.xml"/>
    <include file="aon_ifc.xml"/>
    <include file="timer.xml"/>
    <include file="timer_ap.xml"/>
    <include file="arm_uart.xml"/>
    <include file="keypad.xml"/>
    <include file="pwm.xml"/>
    <include file="calendar.xml"/>
    <include file="aif.xml"/>
    <include file="aud_2ad.xml"/>
    <include file="usbc.xml"/>
    <include file="usbc11.xml"/>
    <include file="sdmmc.xml"/>
    <include file="camera.xml"/>
    <include file="adi_mst.xml"/>
    <include file="analog_reg.xml"/>
    <include file="lvds.xml"/>
    <include file="sys_imem.xml"/>
    <include file="sys_axi_cfg.xml"/>
    <include file="dmc400.xml"/>
    <include file="lpddr_phy.xml"/>
    <include file="psram_phy.xml"/>
    <include file="lpddr_psram.xml"/>
    <include file="dbg_a5.xml"/>
    <include file="pmu_a5.xml"/>
    <include file="etm_a5.xml"/>
    <include file="cti.xml"/>
    <include file="etb.xml"/>
    <include file="atb_funnel.xml"/>
    <include file="timestamp.xml"/>
    <include file="cp_zsp_uart.xml"/>
    <include file="rda2720m_adc.xml"/>
    <include file="rda2720m_aud.xml"/>
    <include file="rda2720m_aud_codec.xml"/>
    <include file="rda2720m_aud_ifa.xml"/>
    <include file="rda2720m_bltc.xml"/>
    <include file="rda2720m_cal.xml"/>
    <include file="rda2720m_rf_mode.xml"/>
    <include file="rda2720m_eic.xml"/>
    <include file="rda2720m_efs.xml"/>
    <include file="rda2720m_fgu.xml"/>
    <include file="rda2720m_global.xml"/>
    <include file="rda2720m_int.xml"/>
    <include file="rda2720m_pin.xml"/>
    <include file="rda2720m_psm.xml"/>
    <include file="rda2720m_rtc.xml"/>
    <include file="rda2720m_tmr.xml"/>
    <include file="rda2720m_wdg.xml"/>
    <include file="cp_idle.xml"/>
    <include file="cp_mailbox.xml"/>
    <include file="cp_clkrst.xml"/>
    <include file="cp_pwrctrl.xml"/>
    <include file="cp_sysreg.xml"/>
    <include file="cp_monitor.xml"/>
    <include file="cp_bb_wd.xml"/>
    <include file="cp_zsp_irqh.xml"/>
    <include file="cp_zsp_axidma.xml"/>
    <include file="cp_zsp_aud_dft.xml"/>
    <include file="cp_zsp_busmon.xml"/>
    <include file="cp_zsp_wd.xml"/>
    <include file="cp_lte_pusch.xml"/>
    <include file="cp_lte_ldtc1.xml"/>
    <include file="cp_lte_ldtc.xml"/>
    <include file="cp_lte_dlfft.xml"/>
    <include file="cp_lte_coeff.xml"/>
    <include file="cp_lte_rfad.xml"/>
    <include file="cp_lte_uldft.xml"/>
    <include file="cp_lte_txrx.xml"/>
    <include file="cp_lte_measpwr.xml"/>
    <include file="cp_lte_iddet.xml"/>
    <include file="cp_lte_csirs.xml"/>
    <include file="cp_lte_ulpcdci.xml"/>
    <include file="cp_lte_corr.xml"/>
    <include file="cp_lte_otdoa.xml"/>
    <include file="cp_lte_rxcapt.xml"/>
    <include file="bb2g_ram.xml"/>
    <include file="bb_cp2.xml"/>
    <include file="bb_irq.xml"/>
    <include file="bb_rom.xml"/>
    <include file="cholk.xml"/>
    <include file="cipher.xml"/>
    <include file="cipher_a53.xml"/>
    <include file="cordic.xml"/>
    <include file="excor.xml"/>
    <include file="itlv.xml"/>
    <include file="rf_if.xml"/>
    <include file="rf_spi.xml"/>
    <include file="sys_ifc.xml"/>
    <include file="gge_sys_ctrl.xml"/>
    <include file="tcu.xml"/>
    <include file="vitac.xml"/>
    <include file="wdt.xml"/>
    <include file="xcor.xml"/>
    <include file="mips32r6.xml"/>
    <include file="ela.xml"/>
    <include file="evitac.xml"/>
    <include file="dma.xml"/>
    <include file="nb_cell_search.xml"/>
    <include file="nb_common.xml"/>
    <include file="nb_ctrl.xml"/>
    <include file="nb_ds_bsel.xml"/>
    <include file="nb_fft_rsrp.xml"/>
    <include file="nb_intc.xml"/>
    <include file="nb_meas.xml"/>
    <include file="nb_tx_chsc.xml"/>
    <include file="nb_tx_frontend.xml"/>
    <include file="nb_tx_pusch_encoder.xml"/>
    <include file="nb_viterbi.xml"/>
    <include file="rf_registers.xml"/>
    <include file="rf_timer.xml"/>
    <include file="rf_uart.xml"/>
    <include file="rf_wdt.xml"/>
    <include file="rf_sys_ctrl.xml"/>
    <include file="rffe_reg.xml"/>
    <include file="rf_pulp_irq.xml"/>
    <include file="rf_pulp_sleep.xml"/>
    <include file="rf_pulp_debug_unit.xml"/>
    <include file="rf_rtc.xml"/>
    <include file="tsen_adc.xml"/>
    <include file="dfe.xml"/>
    <include file="rf_dlpf.xml"/>
    <include file="rf_et.xml"/>
    <include file="wcn_bb_ifc.xml"/>
    <include file="wcn_ble_link.xml"/>
    <include file="wcn_bt_core.xml"/>
    <include file="wcn_bt_link.xml"/>
    <include file="wcn_bt_modem.xml"/>
    <include file="wcn_cache_ctrl.xml"/>
    <include file="wcn_comregs.xml"/>
    <include file="wcn_dbm.xml"/>
    <include file="wcn_fm_dsp.xml"/>
    <include file="wcn_pulp_irq.xml"/>
    <include file="wcn_pulp_sleep.xml"/>
    <include file="wcn_pulp_debug_unit.xml"/>
    <include file="wcn_rf_if.xml"/>
    <include file="wcn_sys_ctrl.xml"/>
    <include file="wcn_sys_ifc.xml"/>
    <include file="wcn_systick.xml"/>
    <include file="wcn_trap.xml"/>
    <include file="wcn_uart.xml"/>
    <include file="wcn_wdt.xml"/>
    <include file="wcn_wlan.xml"/>
    <instance address="0x00000000" name="INT_ROM" type="INT_ROM"/>
    <instance address="0x00800000" name="INT_SRAM" type="INT_SRAM"/>
    <instance address="0x08200000" name="GIC400" type="GIC400"/>
    <instance address="0x08300000" name="SYS_AXI_CFG" type="SYS_AXI_CFG"/>
    <var name="REG_AP_APB_BASE" value="0x08800000">
      <comment>Ap APB base</comment>
    </var>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_IRQH" name="CP_IRQH" type="CP_ZSP_IRQH"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_IRQH + 0x800" name="CP_IRQH1" type="CP_ZSP_IRQH"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_DMC_CTRL" name="DMC_CTRL" type="DMC400"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_LPDDR_PSRAM_CTRL" name="LPDDR_PHY" type="LPDDR_PHY"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_LPDDR_PSRAM_CTRL + AP_APB_STEP/2" name="PSRAM_PHY" type="PSRAM_PHY"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_PAGESPY" name="PAGESPY_DMC" type="PAGESPY_DMC"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_SYSIMEM" name="SYS_IMEM" type="SYS_IMEM"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_LZMA" name="LZMA" type="LZMA"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_GOUDA" name="GOUDA" type="GOUDA"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_LCDC" name="LCDC" type="LCDC"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_TIMER_1" name="TIMER1" type="TIMER"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_TIMER_2" name="TIMER2" type="TIMER"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_I2C_M1" name="I2C_MASTER1" type="I2C_MASTER"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_I2C_M3" name="I2C_MASTER3" type="I2C_MASTER"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_TIMER_4" name="TIMER4" type="TIMER_AP"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_AP_IFC + AUDIO_IFC_APB_STEP" name="AUDIO_IFC" type="AUDIO_IFC"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_AP_IFC" name="AP_IFC" type="AP_IFC"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_SDMMC1" name="SDMMC" type="SDMMC"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_SDMMC2" name="SDMMC2" type="SDMMC"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_SPI_1" name="SPI1" type="SPI"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_SPI_2" name="SPI2" type="SPI"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_SCI_1" name="SCI1" type="SCI"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_SCI_2" name="SCI2" type="SCI"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_ZSP_UART" name="ZSP_UART" type="CP_ZSP_UART"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_UART_2" name="UART2" type="ARM_UART"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_UART_3" name="UART3" type="ARM_UART"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_CAMERA" name="CAMERA" type="CAMERA"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB1_ID_AIF" name="AIF1" type="AIF"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB1_ID_AIF2" name="AIF2" type="AIF"/>
    <instance address="REG_AP_APB_BASE + AP_APB_STEP * AP_APB_ID_AUD_2AD" name="AUD_2AD" type="AUD_2AD"/>
    <instance address="0x00880000" name="SPI_FLASH" type="SPI_FLASH"/>
    <instance address="0x00881000" name="SPI_FLASH_EXT" type="SPI_FLASH"/>
    <var name="REG_SYS_AHB_BASE" value="0x09000000">
      <comments>System AHB base</comments>
    </var>
    <instance address="REG_SYS_AHB_BASE + SYS_AHB_STEP * (SYS_AHB_ID_F8-1)" name="F8" type="F8"/>
    <instance address="REG_SYS_AHB_BASE + SYS_AHB_STEP * (SYS_AHB_ID_USBC-1)" name="USBC" type="USBC"/>
    <instance address="REG_SYS_AHB_BASE + SYS_AHB_STEP * (SYS_AHB_ID_GOUDA-1)" name="GOUDA_SRAM" type="GOUDA_SRAM"/>
    <instance address="REG_SYS_AHB_BASE + SYS_AHB_STEP * (SYS_AHB_ID_AXIDMA-1)" name="DMA" type="ARM_AXIDMA"/>
    <instance address="REG_SYS_AHB_BASE + SYS_AHB_STEP * (SYS_AHB_ID_GEA3-1)" name="GEA3" type="FPI3_GPRS"/>
    <instance address="REG_SYS_AHB_BASE + SYS_AHB_STEP * (SYS_AHB_ID_AES-1)" name="AES" type="AES"/>
    <instance address="REG_SYS_AHB_BASE + SYS_AHB_STEP * (SYS_AHB_ID_USB11-1)" name="USBC11" type="USBC11"/>
    <var name="LPDDR_BASE" value="0x80000000">
      <comment>PSRAM base</comment>
    </var>
    <var name="LPDDR_BASE_FOR_GGE" value="0x08000000"/>
    <instance address="LPDDR_BASE" name="LPDDR_MEM" type="LPDDR_MEM">
      <altaddress address="LPDDR_BASE_FOR_GGE" name="GGE"/>
    </instance>
    <var name="PSRAM_BASE" value="0x80000000">
      <comment>PSRAM base</comment>
    </var>
    <var name="PSRAM_BASE_FOR_GGE" value="0x08000000"/>
    <instance address="PSRAM_BASE" name="PSRAM_MEM" type="PSRAM_MEM">
      <altaddress address="PSRAM_BASE_FOR_GGE" name="GGE"/>
    </instance>
    <var name="AON_ADI_MST_BASE" value="0x50300000">
      <comment>ADI mst base</comment>
    </var>
    <instance address="AON_ADI_MST_BASE" name="ADI_MST" type="ADI_MST">
      <altaddress address="0x05300000" name="GGE"/>
    </instance>
    <instance address="AON_ADI_MST_BASE + 0x8000" name="RDA2720M_TMR" type="RDA2720M_TMR"/>
    <instance address="AON_ADI_MST_BASE + 0x8040" name="RDA2720M_WDG" type="RDA2720M_WDG"/>
    <instance address="AON_ADI_MST_BASE + 0x80c0" name="RDA2720M_INT" type="RDA2720M_INT"/>
    <instance address="AON_ADI_MST_BASE + 0x8100" name="RDA2720M_CAL" type="RDA2720M_CAL"/>
    <instance address="AON_ADI_MST_BASE + 0x8140" name="RDA2720M_AUD_IFA" type="RDA2720M_AUD_IFA"/>
    <instance address="AON_ADI_MST_BASE + 0x8180" name="RDA2720M_BLTC" type="RDA2720M_BLTC"/>
    <instance address="AON_ADI_MST_BASE + 0x8200" name="RDA2720M_RTC" type="RDA2720M_RTC"/>
    <instance address="AON_ADI_MST_BASE + 0x8280" name="RDA2720M_EIC" type="RDA2720M_EIC"/>
    <instance address="AON_ADI_MST_BASE + 0x8300" name="RDA2720M_EFS" type="RDA2720M_EFS"/>
    <instance address="AON_ADI_MST_BASE + 0x8400" name="RDA2720M_ADC" type="RDA2720M_ADC"/>
    <instance address="AON_ADI_MST_BASE + 0x8500" name="RDA2720M_RF_MODE" type="RDA2720M_RF_MODE"/>
    <instance address="AON_ADI_MST_BASE + 0x8600" name="RDA2720M_PIN" type="RDA2720M_PIN"/>
    <instance address="AON_ADI_MST_BASE + 0x8700" name="RDA2720M_AUD_CODEC" type="RDA2720M_AUD_CODEC"/>
    <instance address="AON_ADI_MST_BASE + 0x8800" name="RDA2720M_AUD" type="RDA2720M_AUD"/>
    <instance address="AON_ADI_MST_BASE + 0x8900" name="RDA2720M_PSM" type="RDA2720M_PSM"/>
    <instance address="AON_ADI_MST_BASE + 0x8a00" name="RDA2720M_FGU" type="RDA2720M_FGU"/>
    <instance address="AON_ADI_MST_BASE + 0x8c00" name="RDA2720M_GLOBAL" type="RDA2720M_GLOBAL"/>
    <var name="REG_AON_APB_BASE" value="0x50100000">
      <comment>System AON APB base</comment>
    </var>
    <var name="REG_AON_APB_BASE_FOR_GGE" value="0x05100000"/>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_SYS_CTRL" name="SYS_CTRL" type="SYS_CTRL">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_SYS_CTRL" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_IOMUX" name="IOMUX" type="IOMUX">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_IOMUX" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_SPINLOCK" name="SPINLOCK" type="SPINLOCK">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_SPINLOCK" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_EFUSE" name="EFUSE_CTRL" type="EFUSE_CTRL">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_EFUSE" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_LVDS" name="LVDS" type="LVDS">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_LVDS" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_GSM_LPS" name="GSM_LPS" type="LPS">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_GSM_LPS" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_I2C_M2" name="I2C_MASTER2" type="I2C_MASTER">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_I2C_M2" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_MAILBOX" name="MAILBOX" type="CP_MAILBOX">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_MAILBOX" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_TIMER_3" name="TIMER3" type="TIMER_AP">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_TIMER_3" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_KEYPAD" name="KEYPAD" type="KEYPAD">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_KEYPAD" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_GPIO_1" name="GPIO1" type="GPIO">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_GPIO_1" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_PWM" name="PWM" type="PWM">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_PWM" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_ANALOG_REG" name="ANALOG_REG" type="ANALOG_REG">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_ANALOG_REG" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_AON_IFC" name="AON_IFC" type="AON_IFC">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_AON_IFC" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_NB_LPS" name="NB_LPS" type="LPS">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_NB_LPS" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_DEBUG_UART" name="DEBUG_UART" type="DEBUG_UART">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_DEBUG_UART" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_VAD" name="VAD" type="VAD">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_VAD" name="GGE"/>
    </instance>
    <instance address="REG_AON_APB_BASE + AON_APB_STEP * AON_APB_ID_DEBUG_HOST" name="DEBUG_HOST" type="DEBUG_HOST">
      <altaddress address="REG_AON_APB_BASE_FOR_GGE + AON_APB_STEP * AON_APB_ID_DEBUG_HOST" name="GGE"/>
    </instance>
    <var name="AON_CORESIGHT_BASE" value="0x50400000">
      <comment>COREISHGT Base</comment>
    </var>
    <instance address="AON_CORESIGHT_BASE + 0xA000" name="DBG_AP_A5" type="DBG_A5">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0xB000" name="PMU_AP_A5" type="PMU_A5">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0xC000" name="CTI_AP_A5" type="CTI">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0xD000" name="ETM_AP_A5" type="ETM_A5">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0x12000" name="DBG_CP_A5" type="DBG_A5">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0x13000" name="PMU_CP_A5" type="PMU_A5">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0x14000" name="CTI_CP_A5" type="CTI">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0x15000" name="ETM_CP_A5" type="ETM_A5">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0x18000" name="ATB_FUNNEL" type="ATB_FUNNEL">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0x19000" name="CTI" type="CTI">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0x1A000" name="ETB" type="ETB">
  </instance>
    <instance address="AON_CORESIGHT_BASE + 0x1B000" name="TIME_STAMP" type="TIMESTAMP">
  </instance>
    <instance address="0x00000000" name="INT_REG_DBG_HOST" type="DEBUG_HOST_INTERNAL_REGISTERS"/>
    <var name="BB_SYS_ADDR_BASE" value="0x50080000">
      <comments>BB_SYS ADDR base</comments>
    </var>
    <var name="BB_SYS_ADDR_BASE_FOR_GGE" value="0x05080000"/>
    <instance address="BB_SYS_ADDR_BASE + BB_SYS_STEP * BB_SYSCTRL_ID_SYSREG" name="SYSREG" type="CP_SYSREG">
      <altaddress address="BB_SYS_ADDR_BASE_FOR_GGE + BB_SYS_STEP * BB_SYSCTRL_ID_SYSREG" name="GGE"/>
    </instance>
    <instance address="BB_SYS_ADDR_BASE + BB_SYS_STEP * BB_SYSCTRL_ID_CLKRST" name="CLKRST" type="CP_CLKRST">
      <altaddress address="BB_SYS_ADDR_BASE_FOR_GGE + BB_SYS_STEP * BB_SYSCTRL_ID_CLKRST" name="GGE"/>
    </instance>
    <instance address="BB_SYS_ADDR_BASE + BB_SYS_STEP * BB_SYSCTRL_ID_MONITOR" name="MONITOR" type="CP_MONITOR">
      <altaddress address="BB_SYS_ADDR_BASE_FOR_GGE + BB_SYS_STEP * BB_SYSCTRL_ID_MONITOR" name="GGE"/>
    </instance>
    <instance address="BB_SYS_ADDR_BASE + BB_SYS_STEP * BB_SYSCTRL_ID_CP_WD_TIMER" name="CP_BB_WD" type="CP_BB_WD">
      <altaddress address="BB_SYS_ADDR_BASE_FOR_GGE + BB_SYS_STEP * BB_SYSCTRL_ID_CP_WD_TIMER" name="GGE"/>
    </instance>
    <instance address="BB_SYS_ADDR_BASE + BB_SYS_STEP * BB_SYSCTRL_ID_IDLE" name="IDLE" type="CP_IDLE">
      <altaddress address="BB_SYS_ADDR_BASE_FOR_GGE + BB_SYS_STEP * BB_SYSCTRL_ID_IDLE" name="GGE"/>
    </instance>
    <instance address="BB_SYS_ADDR_BASE + BB_SYS_STEP * BB_SYSCTRL_ID_UART1" name="UART1" type="ARM_UART">
      <altaddress address="BB_SYS_ADDR_BASE_FOR_GGE + BB_SYS_STEP * BB_SYSCTRL_ID_UART1" name="GGE"/>
    </instance>
    <instance address="BB_SYS_ADDR_BASE + BB_SYS_STEP * BB_SYSCTRL_ID_PWRCTRL" name="PWRCTRL" type="CP_PWRCTRL">
      <altaddress address="BB_SYS_ADDR_BASE_FOR_GGE + BB_SYS_STEP * BB_SYSCTRL_ID_PWRCTRL" name="GGE"/>
    </instance>
    <var name="ZSP_SYS_ADDR_BASE" value="0x22000000">
      <comments>ZSP_SYS ADDR base</comments>
    </var>
    <instance address="ZSP_SYS_ADDR_BASE+CP_ZSP_SYS_STEP*CP_ZSP_SYS_ID_ZSP_AXIDMA" name="ZSP_AXIDMA" type="CP_ZSP_AXIDMA">
  </instance>
    <instance address="ZSP_SYS_ADDR_BASE+CP_ZSP_SYS_STEP*CP_ZSP_SYS_ID_ZSP_AUD_DFT" name="ZSP_AUD_DFT" type="CP_ZSP_AUD_DFT">
  </instance>
    <instance address="ZSP_SYS_ADDR_BASE+CP_ZSP_SYS_STEP*CP_ZSP_SYS_ID_ZSP_WD" name="ZSP_WD" type="CP_ZSP_WD">
  </instance>
    <instance address="ZSP_SYS_ADDR_BASE+CP_ZSP_SYS_STEP*CP_ZSP_SYS_ID_ZSP_IRQH" name="ZSP_IRQH" type="CP_ZSP_IRQH">
  </instance>
    <instance address="ZSP_SYS_ADDR_BASE+CP_ZSP_SYS_STEP*CP_ZSP_SYS_ID_BUSMON" name="BUSMON" type="CP_ZSP_BUSMON">
  </instance>
    <var name="LTE_SYS_ADDR_BASE" value="0x25000000"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_TXRX" name="TXRX" type="CP_LTE_TXRX"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_RFAD" name="RFAD" type="CP_LTE_RFAD"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_COEFF" name="COEFF" type="CP_LTE_COEFF"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_LDTC" name="LDTC" type="CP_LTE_LDTC"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_OTDOA" name="OTDOA" type="CP_LTE_OTDOA"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_MEASPWR" name="MEASPWR" type="CP_LTE_MEASPWR"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_IDDET" name="IDDET" type="CP_LTE_IDDET"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_ULDFT" name="ULDFT" type="CP_LTE_ULDFT"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_PUSCH" name="PUSCH" type="CP_LTE_PUSCH"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_ULPCDCI" name="ULPCDCI" type="CP_LTE_ULPCDCI"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_DLFFT" name="DLFFT" type="CP_LTE_DLFFT"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_CSIRS" name="CSIRS" type="CP_LTE_CSIRS"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_LDTC1" name="LDTC1" type="CP_LTE_LDTC1"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_LDTC1+0x800" name="CORR" type="CP_LTE_CORR"/>
    <instance address="LTE_SYS_ADDR_BASE+CP_LTE_SYS_STEP*CP_LTE_SYS_ID_RXCAPT" name="RXCAPT" type="CP_LTE_RXCAPT"/>
    <var name="GGE_BB_APB_ADDR_BASE" value="0x40000000">
      <comments>GGE_BB_APB ADDR base</comments>
    </var>
    <var name="GGE_BB_APB_ADDR_BASE_FOR_GGE" value="0x00000000"/>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_XCOR" name="XCOR" type="XCOR">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_XCOR" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_CORDIC" name="CORDIC" type="CORDIC">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_CORDIC" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_ITLV" name="ITLV" type="ITLV">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_ITLV" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_VITAC" name="VITAC" type="VITAC">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_VITAC" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_EXCOR" name="EXCOR" type="EXCOR">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_EXCOR" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_CHOLK" name="CHOLK" type="CHOLK">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_CHOLK" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_CIPHER" name="CIPHER" type="CIPHER">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_CIPHER" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_EVITAC" name="EVITAC" type="EVITAC">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_EVITAC" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_CP2" name="BB_CP2" type="BB_CP2">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_CP2" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_BCPU_DBG" name="BCPU_DBG" type="ELA">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_BCPU_DBG" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_BCPU_CORE" name="BCPU_CORE" type="MIPS32R6">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_BCPU_CORE" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_ROM" name="BB_ROM_CTRL" type="BB_ROM_CTRL">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_ROM" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_RF_IF" name="RF_IF" type="RF_IF">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_RF_IF" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_IRQ" name="BB_IRQ" type="BB_IRQ">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_IRQ" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_SYSCTRL" name="GGE_SYS_CTRL" type="GGE_SYS_CTRL">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_SYSCTRL" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_A53" name="CIPHER_A53" type="CIPHER_A53">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_A53" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_CTRL" name="NB_CTRL" type="NB_CTRL">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_CTRL" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_COMMON" name="NB_COMMON" type="NB_COMMON">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_COMMON" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_INTC" name="NB_INTC" type="NB_INTC">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_INTC" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_CELL_SEARCH" name="NB_CELL_SEARCH" type="NB_CELL_SEARCH">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_CELL_SEARCH" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_FFT_RSRP" name="NB_FFT_RSRP" type="NB_FFT_RSRP">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_FFT_RSRP" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_VITERBI" name="NB_VITERBI" type="NB_VITERBI">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_VITERBI" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_MEAS" name="NB_MEAS" type="NB_MEAS">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_MEAS" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_DS_BSEL" name="NB_DS_BSEL" type="NB_DS_BSEL">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_DS_BSEL" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_TX_PUSCH_ENC" name="NB_TX_PUSCH_ENC" type="NB_TX_PUSCH_ENCODER">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_TX_PUSCH_ENC" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_TX_CHSC" name="NB_TX_CHSC" type="NB_TX_CHSC">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_TX_CHSC" name="GGE"/>
    </instance>
    <instance address="GGE_BB_APB_ADDR_BASE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_TX_FRONTEND" name="NB_TX_FRONTEND" type="NB_TX_FRONTEND">
      <altaddress address="GGE_BB_APB_ADDR_BASE_FOR_GGE + GGE_BB_APB_STEP * GGE_BB_APB_ID_NB_TX_FRONTEND" name="GGE"/>
    </instance>
    <var name="GGE_SYS_APB_ADDR_BASE" value="0x40020000">
      <comments>GGE_SYS_APB ADDR base</comments>
    </var>
    <var name="GGE_SYS_APB_ADDR_BASE_FOR_GGE" value="0x00020000"/>
    <instance address="GGE_SYS_APB_ADDR_BASE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_TCU_GSM" name="TCU_GSM" type="TCU">
      <altaddress address="GGE_SYS_APB_ADDR_BASE_FOR_GGE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_TCU_GSM" name="GGE"/>
    </instance>
    <instance address="GGE_SYS_APB_ADDR_BASE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_TCU_NB" name="TCU_NB" type="TCU">
      <altaddress address="GGE_SYS_APB_ADDR_BASE_FOR_GGE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_TCU_NB" name="GGE"/>
    </instance>
    <instance address="GGE_SYS_APB_ADDR_BASE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_BB_DMA" name="BB_DMA" type="DMA">
      <altaddress address="GGE_SYS_APB_ADDR_BASE_FOR_GGE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_BB_DMA" name="GGE"/>
    </instance>
    <instance address="GGE_SYS_APB_ADDR_BASE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_WDT" name="WDT" type="WDT">
      <altaddress address="GGE_SYS_APB_ADDR_BASE_FOR_GGE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_WDT" name="GGE"/>
    </instance>
    <instance address="GGE_SYS_APB_ADDR_BASE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_GGE_IFC" name="SYS_IFC" type="SYS_IFC">
      <altaddress address="GGE_SYS_APB_ADDR_BASE_FOR_GGE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_GGE_IFC" name="GGE"/>
    </instance>
    <instance address="GGE_SYS_APB_ADDR_BASE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_RFSPI_GSM" name="RF_SPI_GSM" type="RF_SPI">
      <altaddress address="GGE_SYS_APB_ADDR_BASE_FOR_GGE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_RFSPI_GSM" name="GGE"/>
    </instance>
    <instance address="GGE_SYS_APB_ADDR_BASE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_RFSPI_NB" name="RF_SPI_NB" type="RF_SPI">
      <altaddress address="GGE_SYS_APB_ADDR_BASE_FOR_GGE + GGE_SYS_APB_STEP * GGE_SYS_APB_ID_RFSPI_NB" name="GGE"/>
    </instance>
    <instance address="0x40080000" name="BB2G_RAM" type="BB2G_RAM">
      <altaddress address="0x00080000" name="GGE"/>
    </instance>
    <instance address="0x400a0000" name="BB_ROM" type="BB_ROM">
      <altaddress address="0x000a0000" name="GGE"/>
    </instance>
    <instance address="0x50020000" name="RF_PULP_DEBUG" type="RF_PULP_DEBUG_UNIT">
      <altaddress address="0x05020000" name="GGE"/>
    </instance>
    <instance address="0x50028000" name="RF_PULP_IRQ" type="RF_PULP_IRQ">
      <altaddress address="0x05028000" name="GGE"/>
    </instance>
    <instance address="0x5002c000" name="RF_PULP_SLEEP" type="RF_PULP_SLEEP">
      <altaddress address="0x0502C000" name="GGE"/>
    </instance>
    <var name="RF_APB_ADDR_BASE" value="0x50030000">
      <comments>RF_APB ADDR base</comments>
    </var>
    <var name="RF_APB_ADDR_BASE_FOR_GGE" value="0x05030000"/>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_CTRL_1" name="RF_REG" type="RF_REGISTERS">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_CTRL_1" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_DFE" name="DFE" type="DFE">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_DFE" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_DFE + 0xa00" name="RF_DLPF" type="RF_DLPF">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_DFE + 0xa00" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_ET" name="RF_ET" type="RF_ET">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_ET" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_RTC" name="RF_RTC" type="RF_RTC">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_RTC" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_SYS_CTRL" name="RF_SYS_CTRL" type="RF_SYS_CTRL">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_SYS_CTRL" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_TIMER_1" name="RF_TIMER_1" type="RF_TIMER">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_TIMER_1" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_TIMER_2" name="RF_TIMER_2" type="RF_TIMER">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_TIMER_2" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_TIMER_3" name="RF_TIMER_3" type="RF_TIMER">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_TIMER_3" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_UART" name="RF_UART" type="RF_UART">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_UART" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_WATCHDOG" name="RF_WDT" type="RF_WDT">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_WATCHDOG" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_TSEN_ADC" name="TSEN_ADC" type="TSEN_ADC_TOP">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_TSEN_ADC" name="GGE"/>
    </instance>
    <instance address="RF_APB_ADDR_BASE + RF_APB_STEP * RF_APB_ID_RFFE" name="RFFE_REG" type="RFFE_REG">
      <altaddress address="RF_APB_ADDR_BASE_FOR_GGE + RF_APB_STEP * RF_APB_ID_RFFE" name="GGE"/>
    </instance>
    <instance address="0x14000000" name="WCN_PULP_DEBUG" type="WCN_PULP_DEBUG_UNIT"/>
    <instance address="0x14008000" name="WCN_PULP_IRQ" type="WCN_PULP_IRQ"/>
    <instance address="0x1400c000" name="WCN_PULP_SLEEP" type="WCN_PULP_SLEEP"/>
    <instance address="0x14020000" name="WCN_ICACHE_CTRL" type="WCN_CACHE_CTRL"/>
    <instance address="0x14040000" name="WCN_DCACHE_CTRL" type="WCN_CACHE_CTRL"/>
    <instance address="0x14100000" name="WCN_BT_REG" type="WCN_BT_LINK"/>
    <instance address="0x14100200" name="WCN_BLE_REG" type="WCN_BLE_LINK"/>
    <var name="WCN_SYS_APB_ADDR_BASE" value="0x15000000">
      <comments>WCN SYS APB ADDR base</comments>
    </var>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_SYS_CTRL" name="WCN_SYS_CTRL" type="WCN_SYS_CTRL"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_DBM" name="WCN_DBM" type="WCN_DBM"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_SYS_IFC" name="WCN_SYS_IFC" type="WCN_SYS_IFC"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_BT_CORE" name="WCN_BT_CORE" type="WCN_BT_CORE"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_UART" name="WCN_UART" type="WCN_UART"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_RF_IF" name="WCN_RF_IF" type="WCN_RF_IF"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_MODEM" name="WCN_MODEM" type="WCN_BT_MODEM"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_WLAN" name="WCN_WLAN" type="WCN_WLAN"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_WDT" name="WCN_WDT" type="WCN_WDT"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_TRAP" name="WCN_TRAP" type="WCN_TRAP"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_SYSTICK" name="WCN_SYSTICK" type="WCN_SYSTICK"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_COMREGS_WCN" name="WCN_COMREGS_WCN" type="WCN_COMREGS"/>
    <instance address="WCN_SYS_APB_ADDR_BASE + WCN_SYS_APB_STEP * WCN_SYS_APB_ID_COMREGS_AP" name="WCN_COMREGS_AP" type="WCN_COMREGS"/>
    <instance address="0x15100000" name="WCN_AUD_IFC" type="WCN_BB_IFC"/>
    <instance address="0x15102000" name="WCN_FM_DSP" type="WCN_FM_DSP"/>
  </archive>
</bigarchive>