Kconfig 9.0 KB

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  1. # Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
  2. # All rights reserved.
  3. #
  4. # This software is supplied "AS IS" without any warranties.
  5. # RDA assumes no responsibility or liability for the use of the software,
  6. # conveys no license or title under any patent, copyright, or mask work
  7. # right to the product. RDA reserves the right to make changes in the
  8. # software without notification. RDA also make no representation or
  9. # warranty that such application will be suitable for the specified use
  10. # without further testing or modification.
  11. menu "bootloader"
  12. config BOOT_LOG_ENABLED
  13. bool "Enable log in bootloader"
  14. default y if KERNEL_HOST_TRACE
  15. default y if SOC_8811
  16. default y if SOC_8850
  17. default n
  18. help
  19. When host trace is enabled, log will be output through debughost.
  20. When diag trace is enabled, log will be output through diag uart.
  21. Usually, there are no reason to disable log through debughost.
  22. However, there are cases that diag uart is expected to be "silent"
  23. during bootloader.
  24. config FDL_LOG_ENABLED
  25. bool "Enable log in fdl"
  26. default y if KERNEL_HOST_TRACE
  27. default y
  28. help
  29. When host trace is enabled, log will be output through debughost.
  30. When diag trace is enabled, log will be output through diag uart.
  31. When download is performed through diag uart, log will be disabled
  32. forcedly.
  33. Usually, there are no reason to disable log through debughost.
  34. However, there are cases that diag uart is expected to be "silent"
  35. during bootloader.
  36. if SOC_8910
  37. config FDL_FLASH_SIGCHECK_BEFORE_WRITE
  38. bool "signature check before flash write"
  39. default n
  40. help
  41. When it is enabled, flash download will perform signature check
  42. before erase and write flash. When the new image is not valid,
  43. the existed content on flash won't be modified.
  44. Download will be slower when it is enabled and secure boot is
  45. enabled.
  46. config FDL1_IMAGE_START
  47. hex "FDL1 uimage SRAM start"
  48. default 0x8000c0
  49. help
  50. FDL1 uimage SRAM start (not the code start address).
  51. config FDL1_IMAGE_SIZE
  52. hex "FDL1 uimage SRAM size"
  53. default 0xff40
  54. help
  55. FDL1 sram size (including uimage header), including uimage header
  56. and non-romed sram
  57. config FDL2_IMAGE_START
  58. hex "FDL2 uimage SRAM start"
  59. default 0x810000
  60. help
  61. FDL2 uimage SRAM start (not the code start address).
  62. config FDL2_IMAGE_SIZE
  63. hex "FDL2 uimage SRAM size"
  64. default 0x30000
  65. help
  66. FDL2 sram size (including uimage header), including uimage header
  67. and non-romed sram
  68. config BOOT2_IMAGE_START
  69. hex "Bootloader stage2 SRAM start"
  70. default 0x810000
  71. help
  72. Bootloader stage2 SRAM start (not the code start address).
  73. Usually, it is the same as FDL2 to reuse SRAM.
  74. config BOOT2_IMAGE_SIZE
  75. hex "Bootloader stage2 SRAM size"
  76. default 0x30000
  77. help
  78. Bootloader stage2 sram size, including uimage header and
  79. non-romed sram. Usually, it is the same as FDL2 to reuse SRAM.
  80. config BOOT_SYS_STACK_SIZE
  81. hex "Boot/boot2/FDL1/FDL2 SYS stack size"
  82. default 0x1800
  83. help
  84. Boot/boot2/FDL1/FDL2 are running in SYS mode. This is the
  85. stack size. All modes share the same stack.
  86. config BOOT_IRQ_STACK_SIZE
  87. hex "Boot/boot2/FDL1/FDL2 SVC stack size"
  88. default 0x800
  89. help
  90. Boot/boot2/FDL1/FDL2 IRQ stack size. All modes share the same
  91. IRQ stack.
  92. config BOOT_BLUE_SCREEN_SIZE
  93. hex "Boot/boot2/FDL1/FDL2 blue screen stack size"
  94. default 0x800
  95. config BOOT_SMPL_ENABLE
  96. bool "enblae SMPL(Sudden Momentary Power Loss)"
  97. default n
  98. help
  99. Enable SMPL. If it occurs that battery is dropped below UVLO
  100. threshold, all supplies will be shutdown simultaneously.
  101. config BOOT_SMPL_THRESHOLD
  102. int "SMPL(Sudden Momentary Power Loss)"
  103. default 7
  104. help
  105. The SMPL programmable timer.If the timer has expired by the
  106. time system supply recovers the PMIC does not auto boot and
  107. remains in power down state. When the system supply recovers
  108. before the timer expired the PMIC will boot up automatically.
  109. SMPL timer threshold value is three bits: 0: 0.25s; 1: 0.5s;
  110. 2: 0.75s; ... 7: 2s
  111. config BOOT_PB_7S_RESET_ENABLE
  112. bool "support pb 7s reset"
  113. default n
  114. config BOOT_UART1_PDL_ENABLE
  115. bool "enable uart1 download"
  116. default n
  117. help
  118. When enabled, bootloader will use PDL protocol to support
  119. download. The baud rate is fixed to 921600, and only Limited
  120. PDL commands are supported.
  121. endif
  122. config DUAL_BOOTLOADER_ENABLE
  123. bool "enable dual bootloader"
  124. depends on SOC_8811 || SOC_8850
  125. default n #quectel update
  126. help
  127. When enabled, there will exist two copies of bootloader at the
  128. beginning of FLASH.
  129. 8811 and 8850 should always enable dual bootloader.
  130. if SOC_8850
  131. config BOOT_SYS_STACK_SIZE
  132. hex "Boot/boot2/FDL1/FDL2 SYS stack size"
  133. default 0x1800
  134. help
  135. Boot/boot2/FDL1/FDL2 are running in SYS mode. This is the
  136. stack size. All modes share the same stack.
  137. config BOOT_IRQ_STACK_SIZE
  138. hex "Boot/boot2/FDL1/FDL2 SVC stack size"
  139. default 0x800
  140. help
  141. Boot/boot2/FDL1/FDL2 IRQ stack size. All modes share the same
  142. IRQ stack.
  143. config BOOT_BLUE_SCREEN_SIZE
  144. hex "Boot/boot2/FDL1/FDL2 blue screen stack size"
  145. default 0x800
  146. config BOOT_PB_7S_RESET_ENABLE
  147. bool "support pb 7s reset"
  148. default n
  149. config BOOT_UART1_PDL_ENABLE
  150. bool "enable uart1 download"
  151. default n
  152. help
  153. When enabled, bootloader will use PDL protocol to support
  154. download. The baud rate is fixed to 921600, and only Limited
  155. PDL commands are supported.
  156. endif
  157. if SOC_8811
  158. config BOOT_MAIN_STACK_SIZE
  159. hex "bootloader/fdl main stack size"
  160. default 0x2000
  161. help
  162. Main stack size of bootloader and fdl.
  163. config BOOT_PROCESS_STACK_SIZE
  164. hex "bootloader/fdl process stack size"
  165. default 0x2000
  166. help
  167. Process stack size of bootloader and fdl.
  168. endif
  169. config BOOT_TIMER_IRQ_ENABLE
  170. bool "enable timer IRQ"
  171. default n
  172. help
  173. When enabled, interrupt will be enabled in bootloader, and timer
  174. IRQ will be enabled. It is only used to feed external watchdog.
  175. if BOOT_TIMER_IRQ_ENABLE
  176. config BOOT_TIMER_PERIOD
  177. int "boot timer period (ms)"
  178. default 500
  179. help
  180. Bootloader timer period, in milliseconds.
  181. endif
  182. config FDL1_PACKET_MAX_LEN
  183. hex "Maximum FDL1 packet length"
  184. default 0x840
  185. help
  186. Maximum FDL1 packet length. It should match configuration in
  187. ResearchDownload.
  188. config FDL_PACKET_MAX_LEN
  189. hex "Maximum FDL packet length"
  190. default 0x3000
  191. help
  192. Maximum FDL packet length. It should match configuration in
  193. ResearchDownload.
  194. config NVBIN_FIXED_SIZE
  195. hex "NV bin fixed size"
  196. depends on SOC_8910 || SOC_8811 || SOC_8850
  197. default 0x20000 if SOC_8910
  198. default 0x28000 if SOC_8850
  199. default 0x14000 if SOC_8811
  200. help
  201. At nv backup, fixed size is needed for nv bin read and write.
  202. This size should be large enough to hold all fixed nv bin.
  203. if SOC_8910
  204. config FDL_UART_BAUD
  205. int "Baud rate of default FDL UART"
  206. default 921600 if SOC_8910
  207. choice
  208. prompt "FDL default UART"
  209. default FDL_DEFAULT_UART2
  210. config FDL_DEFAULT_UART1
  211. bool "UART1"
  212. config FDL_DEFAULT_UART2
  213. bool "UART2"
  214. config FDL_DEFAULT_UART3
  215. bool "UART3"
  216. endchoice
  217. config FDL_DEFAULT_UART
  218. string
  219. default "DRV_NAME_UART1" if FDL_DEFAULT_UART1
  220. default "DRV_NAME_UART2" if FDL_DEFAULT_UART2
  221. default "DRV_NAME_UART3" if FDL_DEFAULT_UART3
  222. default ""
  223. endif
  224. config BOOT_UNITY_OUTPUT_UART
  225. bool "bootloader unity output to uart"
  226. default y
  227. help
  228. Send unity output to uart. When unselected, unity output will be
  229. mixed into log.
  230. if BOOT_UNITY_OUTPUT_UART
  231. choice
  232. prompt "bootloader unity unit test uart"
  233. default BOOT_UNITY_UART1
  234. config BOOT_UNITY_UART1
  235. bool "UART1"
  236. config BOOT_UNITY_UART2
  237. bool "UART2"
  238. config BOOT_UNITY_UART3
  239. bool "UART3"
  240. config BOOT_UNITY_UART4
  241. bool "UART4"
  242. config BOOT_UNITY_UART5
  243. bool "UART5"
  244. endchoice
  245. config BOOT_UNITY_UART_NAME
  246. string
  247. default "DRV_NAME_UART1" if BOOT_UNITY_UART1
  248. default "DRV_NAME_UART2" if BOOT_UNITY_UART2
  249. default "DRV_NAME_UART3" if BOOT_UNITY_UART3
  250. default "DRV_NAME_UART4" if BOOT_UNITY_UART4
  251. default "DRV_NAME_UART5" if BOOT_UNITY_UART5
  252. default ""
  253. config BOOT_UNITY_UART_BAUD
  254. int "unity unit test uart baud rate"
  255. default 115200
  256. endif
  257. endmenu