EC600G/components/hal/include/hwregs/8850/analog_g1.h

/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _ANALOG_G1_H_
#define _ANALOG_G1_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_ANALOG_G1_SET_OFFSET (1024)
#define REG_ANALOG_G1_CLR_OFFSET (2048)

#define REG_ANALOG_G1_BASE (0x51501000)

typedef volatile struct
{
    uint32_t analog_apll_apll_ctrl1;              // 0x00000000
    uint32_t analog_apll_apll_ctrl2;              // 0x00000004
    uint32_t analog_apll_apll_int_value;          // 0x00000008
    uint32_t analog_apll_apll_ccs_ctrl;           // 0x0000000c
    uint32_t analog_apll_apll_kstep;              // 0x00000010
    uint32_t analog_apll_ana_bias;                // 0x00000014
    uint32_t analog_apll_ana_bias1;               // 0x00000018
    uint32_t analog_apll_reg_sel_cfg_0;           // 0x0000001c
    uint32_t analog_mpll_apll_ctrl1;              // 0x00000020
    uint32_t analog_mpll_apll_ctrl2;              // 0x00000024
    uint32_t analog_mpll_apll_int_value;          // 0x00000028
    uint32_t analog_mpll_apll_ccs_ctrl;           // 0x0000002c
    uint32_t analog_mpll_apll_kstep;              // 0x00000030
    uint32_t analog_mpll_ana_bias;                // 0x00000034
    uint32_t analog_mpll_ana_bias1;               // 0x00000038
    uint32_t analog_mpll_reg_sel_cfg_0;           // 0x0000003c
    uint32_t analog_iis_pll_apll_ctrl1;           // 0x00000040
    uint32_t analog_iis_pll_apll_ctrl2;           // 0x00000044
    uint32_t analog_iis_pll_apll_int_value;       // 0x00000048
    uint32_t analog_iis_pll_apll_ccs_ctrl;        // 0x0000004c
    uint32_t analog_iis_pll_apll_kstep;           // 0x00000050
    uint32_t analog_iis_pll_ana_bias;             // 0x00000054
    uint32_t analog_iis_pll_ana_bias1;            // 0x00000058
    uint32_t analog_iis_pll_reg_sel_cfg_0;        // 0x0000005c
    uint32_t analog_efuse4k_efuse_pin_pw_ctl;     // 0x00000060
    uint32_t analog_efuse4k_reg_sel_cfg_0;        // 0x00000064
    uint32_t analog_efuse2k_efuse_pin_pw_ctl;     // 0x00000068
    uint32_t analog_efuse2k_reg_sel_cfg_0;        // 0x0000006c
    uint32_t __112[228];                          // 0x00000070
    uint32_t analog_apll_apll_ctrl1_set;          // 0x00000400
    uint32_t analog_apll_apll_ctrl2_set;          // 0x00000404
    uint32_t __1032[3];                           // 0x00000408
    uint32_t analog_apll_ana_bias_set;            // 0x00000414
    uint32_t analog_apll_ana_bias1_set;           // 0x00000418
    uint32_t analog_apll_reg_sel_cfg_0_set;       // 0x0000041c
    uint32_t analog_mpll_apll_ctrl1_set;          // 0x00000420
    uint32_t analog_mpll_apll_ctrl2_set;          // 0x00000424
    uint32_t __1064[3];                           // 0x00000428
    uint32_t analog_mpll_ana_bias_set;            // 0x00000434
    uint32_t analog_mpll_ana_bias1_set;           // 0x00000438
    uint32_t analog_mpll_reg_sel_cfg_0_set;       // 0x0000043c
    uint32_t analog_iis_pll_apll_ctrl1_set;       // 0x00000440
    uint32_t analog_iis_pll_apll_ctrl2_set;       // 0x00000444
    uint32_t __1096[3];                           // 0x00000448
    uint32_t analog_iis_pll_ana_bias_set;         // 0x00000454
    uint32_t analog_iis_pll_ana_bias1_set;        // 0x00000458
    uint32_t analog_iis_pll_reg_sel_cfg_0_set;    // 0x0000045c
    uint32_t analog_efuse4k_efuse_pin_pw_ctl_set; // 0x00000460
    uint32_t analog_efuse4k_reg_sel_cfg_0_set;    // 0x00000464
    uint32_t analog_efuse2k_efuse_pin_pw_ctl_set; // 0x00000468
    uint32_t analog_efuse2k_reg_sel_cfg_0_set;    // 0x0000046c
    uint32_t __1136[228];                         // 0x00000470
    uint32_t analog_apll_apll_ctrl1_clr;          // 0x00000800
    uint32_t analog_apll_apll_ctrl2_clr;          // 0x00000804
    uint32_t __2056[3];                           // 0x00000808
    uint32_t analog_apll_ana_bias_clr;            // 0x00000814
    uint32_t analog_apll_ana_bias1_clr;           // 0x00000818
    uint32_t analog_apll_reg_sel_cfg_0_clr;       // 0x0000081c
    uint32_t analog_mpll_apll_ctrl1_clr;          // 0x00000820
    uint32_t analog_mpll_apll_ctrl2_clr;          // 0x00000824
    uint32_t __2088[3];                           // 0x00000828
    uint32_t analog_mpll_ana_bias_clr;            // 0x00000834
    uint32_t analog_mpll_ana_bias1_clr;           // 0x00000838
    uint32_t analog_mpll_reg_sel_cfg_0_clr;       // 0x0000083c
    uint32_t analog_iis_pll_apll_ctrl1_clr;       // 0x00000840
    uint32_t analog_iis_pll_apll_ctrl2_clr;       // 0x00000844
    uint32_t __2120[3];                           // 0x00000848
    uint32_t analog_iis_pll_ana_bias_clr;         // 0x00000854
    uint32_t analog_iis_pll_ana_bias1_clr;        // 0x00000858
    uint32_t analog_iis_pll_reg_sel_cfg_0_clr;    // 0x0000085c
    uint32_t analog_efuse4k_efuse_pin_pw_ctl_clr; // 0x00000860
    uint32_t analog_efuse4k_reg_sel_cfg_0_clr;    // 0x00000864
    uint32_t analog_efuse2k_efuse_pin_pw_ctl_clr; // 0x00000868
    uint32_t analog_efuse2k_reg_sel_cfg_0_clr;    // 0x0000086c
} HWP_ANALOG_G1_T;

#define hwp_analogG1 ((HWP_ANALOG_G1_T *)REG_ACCESS_ADDRESS(REG_ANALOG_G1_BASE))

// analog_apll_apll_ctrl1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_apll_apll_il_div2 : 1;   // [0]
        uint32_t analog_apll_apll_n : 11;        // [11:1]
        uint32_t analog_apll_apll_ref_sel : 1;   // [12]
        uint32_t analog_apll_apll_lpf : 3;       // [15:13]
        uint32_t analog_apll_apll_ibias : 2;     // [17:16]
        uint32_t analog_apll_apll_clkout_en : 1; // [18]
        uint32_t __31_19 : 13;                   // [31:19]
    } b;
} REG_ANALOG_G1_ANALOG_APLL_APLL_CTRL1_T;

// analog_apll_apll_ctrl2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_apll_apll_pd : 1;        // [0]
        uint32_t analog_apll_apll_rst : 1;       // [1]
        uint32_t analog_apll_apll_lock_done : 1; // [2], read only
        uint32_t analog_apll_apll_hop_trig : 1;  // [3]
        uint32_t analog_apll_apll_hop_en : 1;    // [4]
        uint32_t analog_apll_apll_divn : 3;      // [7:5]
        uint32_t analog_apll_apll_mod_en : 1;    // [8]
        uint32_t analog_apll_apll_sdm_en : 1;    // [9]
        uint32_t analog_apll_apll_div_s : 1;     // [10]
        uint32_t analog_apll_apll_ol_div2 : 3;   // [13:11]
        uint32_t __31_14 : 18;                   // [31:14]
    } b;
} REG_ANALOG_G1_ANALOG_APLL_APLL_CTRL2_T;

// analog_apll_apll_int_value
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_apll_apll_kint : 20; // [19:0]
        uint32_t analog_apll_apll_nint : 7;  // [26:20]
        uint32_t __31_27 : 5;                // [31:27]
    } b;
} REG_ANALOG_G1_ANALOG_APLL_APLL_INT_VALUE_T;

// analog_apll_apll_ccs_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_apll_apll_ccs_ctrl : 16; // [15:0]
        uint32_t __31_16 : 16;                   // [31:16]
    } b;
} REG_ANALOG_G1_ANALOG_APLL_APLL_CCS_CTRL_T;

// analog_apll_apll_kstep
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_apll_apll_kstep : 19; // [18:0]
        uint32_t __31_19 : 13;                // [31:19]
    } b;
} REG_ANALOG_G1_ANALOG_APLL_APLL_KSTEP_T;

// analog_apll_ana_bias
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_apll_apll_test_en : 1;    // [0]
        uint32_t analog_apll_apll_bist_en : 1;    // [1]
        uint32_t analog_apll_apll_bist_ctrl : 10; // [11:2]
        uint32_t analog_apll_apll_bias_top : 5;   // [16:12]
        uint32_t __31_17 : 15;                    // [31:17]
    } b;
} REG_ANALOG_G1_ANALOG_APLL_ANA_BIAS_T;

// analog_apll_ana_bias1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_apll_apll_dvddiso : 1;   // [0]
        uint32_t analog_apll_apll_precharge : 1; // [1]
        uint32_t analog_apll_apll_dutyfix : 1;   // [2]
        uint32_t analog_apll_apll_bist_cnt : 16; // [18:3], read only
        uint32_t __31_19 : 13;                   // [31:19]
    } b;
} REG_ANALOG_G1_ANALOG_APLL_ANA_BIAS1_T;

// analog_apll_reg_sel_cfg_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbg_sel_analog_apll_apll_dvddiso : 1;   // [0]
        uint32_t dbg_sel_analog_apll_apll_precharge : 1; // [1]
        uint32_t dbg_sel_analog_apll_apll_pd : 1;        // [2]
        uint32_t dbg_sel_analog_apll_apll_rst : 1;       // [3]
        uint32_t dbg_sel_analog_apll_apll_clkout_en : 1; // [4]
        uint32_t __31_5 : 27;                            // [31:5]
    } b;
} REG_ANALOG_G1_ANALOG_APLL_REG_SEL_CFG_0_T;

// analog_mpll_apll_ctrl1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_mpll_apll_il_div2 : 1;   // [0]
        uint32_t analog_mpll_apll_n : 11;        // [11:1]
        uint32_t analog_mpll_apll_ref_sel : 1;   // [12]
        uint32_t analog_mpll_apll_lpf : 3;       // [15:13]
        uint32_t analog_mpll_apll_ibias : 2;     // [17:16]
        uint32_t analog_mpll_apll_clkout_en : 1; // [18]
        uint32_t __31_19 : 13;                   // [31:19]
    } b;
} REG_ANALOG_G1_ANALOG_MPLL_APLL_CTRL1_T;

// analog_mpll_apll_ctrl2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_mpll_apll_pd : 1;        // [0]
        uint32_t analog_mpll_apll_rst : 1;       // [1]
        uint32_t analog_mpll_apll_lock_done : 1; // [2], read only
        uint32_t analog_mpll_apll_hop_trig : 1;  // [3]
        uint32_t analog_mpll_apll_hop_en : 1;    // [4]
        uint32_t analog_mpll_apll_divn : 3;      // [7:5]
        uint32_t analog_mpll_apll_mod_en : 1;    // [8]
        uint32_t analog_mpll_apll_sdm_en : 1;    // [9]
        uint32_t analog_mpll_apll_div_s : 1;     // [10]
        uint32_t analog_mpll_apll_ol_div2 : 3;   // [13:11]
        uint32_t __31_14 : 18;                   // [31:14]
    } b;
} REG_ANALOG_G1_ANALOG_MPLL_APLL_CTRL2_T;

// analog_mpll_apll_int_value
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_mpll_apll_kint : 20; // [19:0]
        uint32_t analog_mpll_apll_nint : 7;  // [26:20]
        uint32_t __31_27 : 5;                // [31:27]
    } b;
} REG_ANALOG_G1_ANALOG_MPLL_APLL_INT_VALUE_T;

// analog_mpll_apll_ccs_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_mpll_apll_ccs_ctrl : 16; // [15:0]
        uint32_t __31_16 : 16;                   // [31:16]
    } b;
} REG_ANALOG_G1_ANALOG_MPLL_APLL_CCS_CTRL_T;

// analog_mpll_apll_kstep
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_mpll_apll_kstep : 19; // [18:0]
        uint32_t __31_19 : 13;                // [31:19]
    } b;
} REG_ANALOG_G1_ANALOG_MPLL_APLL_KSTEP_T;

// analog_mpll_ana_bias
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_mpll_apll_test_en : 1;    // [0]
        uint32_t analog_mpll_apll_bist_en : 1;    // [1]
        uint32_t analog_mpll_apll_bist_ctrl : 10; // [11:2]
        uint32_t analog_mpll_apll_bias_top : 5;   // [16:12]
        uint32_t __31_17 : 15;                    // [31:17]
    } b;
} REG_ANALOG_G1_ANALOG_MPLL_ANA_BIAS_T;

// analog_mpll_ana_bias1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_mpll_apll_dvddiso : 1;   // [0]
        uint32_t analog_mpll_apll_precharge : 1; // [1]
        uint32_t analog_mpll_apll_dutyfix : 1;   // [2]
        uint32_t analog_mpll_apll_bist_cnt : 16; // [18:3], read only
        uint32_t __31_19 : 13;                   // [31:19]
    } b;
} REG_ANALOG_G1_ANALOG_MPLL_ANA_BIAS1_T;

// analog_mpll_reg_sel_cfg_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbg_sel_analog_mpll_apll_dvddiso : 1;   // [0]
        uint32_t dbg_sel_analog_mpll_apll_precharge : 1; // [1]
        uint32_t dbg_sel_analog_mpll_apll_pd : 1;        // [2]
        uint32_t dbg_sel_analog_mpll_apll_rst : 1;       // [3]
        uint32_t dbg_sel_analog_mpll_apll_clkout_en : 1; // [4]
        uint32_t __31_5 : 27;                            // [31:5]
    } b;
} REG_ANALOG_G1_ANALOG_MPLL_REG_SEL_CFG_0_T;

// analog_iis_pll_apll_ctrl1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_iis_pll_apll_il_div2 : 1;   // [0]
        uint32_t analog_iis_pll_apll_n : 11;        // [11:1]
        uint32_t analog_iis_pll_apll_ref_sel : 1;   // [12]
        uint32_t analog_iis_pll_apll_lpf : 3;       // [15:13]
        uint32_t analog_iis_pll_apll_ibias : 2;     // [17:16]
        uint32_t analog_iis_pll_apll_clkout_en : 1; // [18]
        uint32_t __31_19 : 13;                      // [31:19]
    } b;
} REG_ANALOG_G1_ANALOG_IIS_PLL_APLL_CTRL1_T;

// analog_iis_pll_apll_ctrl2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_iis_pll_apll_pd : 1;        // [0]
        uint32_t analog_iis_pll_apll_rst : 1;       // [1]
        uint32_t analog_iis_pll_apll_lock_done : 1; // [2], read only
        uint32_t analog_iis_pll_apll_hop_trig : 1;  // [3]
        uint32_t analog_iis_pll_apll_hop_en : 1;    // [4]
        uint32_t analog_iis_pll_apll_divn : 3;      // [7:5]
        uint32_t analog_iis_pll_apll_mod_en : 1;    // [8]
        uint32_t analog_iis_pll_apll_sdm_en : 1;    // [9]
        uint32_t analog_iis_pll_apll_div_s : 1;     // [10]
        uint32_t analog_iis_pll_apll_ol_div2 : 3;   // [13:11]
        uint32_t __31_14 : 18;                      // [31:14]
    } b;
} REG_ANALOG_G1_ANALOG_IIS_PLL_APLL_CTRL2_T;

// analog_iis_pll_apll_int_value
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_iis_pll_apll_kint : 20; // [19:0]
        uint32_t analog_iis_pll_apll_nint : 7;  // [26:20]
        uint32_t __31_27 : 5;                   // [31:27]
    } b;
} REG_ANALOG_G1_ANALOG_IIS_PLL_APLL_INT_VALUE_T;

// analog_iis_pll_apll_ccs_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_iis_pll_apll_ccs_ctrl : 16; // [15:0]
        uint32_t __31_16 : 16;                      // [31:16]
    } b;
} REG_ANALOG_G1_ANALOG_IIS_PLL_APLL_CCS_CTRL_T;

// analog_iis_pll_apll_kstep
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_iis_pll_apll_kstep : 19; // [18:0]
        uint32_t __31_19 : 13;                   // [31:19]
    } b;
} REG_ANALOG_G1_ANALOG_IIS_PLL_APLL_KSTEP_T;

// analog_iis_pll_ana_bias
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_iis_pll_apll_test_en : 1;    // [0]
        uint32_t analog_iis_pll_apll_bist_en : 1;    // [1]
        uint32_t analog_iis_pll_apll_bist_ctrl : 10; // [11:2]
        uint32_t analog_iis_pll_apll_bias_top : 5;   // [16:12]
        uint32_t __31_17 : 15;                       // [31:17]
    } b;
} REG_ANALOG_G1_ANALOG_IIS_PLL_ANA_BIAS_T;

// analog_iis_pll_ana_bias1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_iis_pll_apll_dvddiso : 1;   // [0]
        uint32_t analog_iis_pll_apll_precharge : 1; // [1]
        uint32_t analog_iis_pll_apll_dutyfix : 1;   // [2]
        uint32_t analog_iis_pll_apll_bist_cnt : 16; // [18:3], read only
        uint32_t __31_19 : 13;                      // [31:19]
    } b;
} REG_ANALOG_G1_ANALOG_IIS_PLL_ANA_BIAS1_T;

// analog_iis_pll_reg_sel_cfg_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbg_sel_analog_iis_pll_apll_dvddiso : 1;   // [0]
        uint32_t dbg_sel_analog_iis_pll_apll_precharge : 1; // [1]
        uint32_t dbg_sel_analog_iis_pll_apll_pd : 1;        // [2]
        uint32_t dbg_sel_analog_iis_pll_apll_rst : 1;       // [3]
        uint32_t dbg_sel_analog_iis_pll_apll_clkout_en : 1; // [4]
        uint32_t __31_5 : 27;                               // [31:5]
    } b;
} REG_ANALOG_G1_ANALOG_IIS_PLL_REG_SEL_CFG_0_T;

// analog_efuse4k_efuse_pin_pw_ctl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_efuse4k_efs_enk2 : 1; // [0]
        uint32_t analog_efuse4k_efs_enk1 : 1; // [1]
        uint32_t __31_2 : 30;                 // [31:2]
    } b;
} REG_ANALOG_G1_ANALOG_EFUSE4K_EFUSE_PIN_PW_CTL_T;

// analog_efuse4k_reg_sel_cfg_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbg_sel_analog_efuse4k_efs_enk2 : 1; // [0]
        uint32_t dbg_sel_analog_efuse4k_efs_enk1 : 1; // [1]
        uint32_t __31_2 : 30;                         // [31:2]
    } b;
} REG_ANALOG_G1_ANALOG_EFUSE4K_REG_SEL_CFG_0_T;

// analog_efuse2k_efuse_pin_pw_ctl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_efuse2k_efs_enk2 : 1; // [0]
        uint32_t analog_efuse2k_efs_enk1 : 1; // [1]
        uint32_t __31_2 : 30;                 // [31:2]
    } b;
} REG_ANALOG_G1_ANALOG_EFUSE2K_EFUSE_PIN_PW_CTL_T;

// analog_efuse2k_reg_sel_cfg_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbg_sel_analog_efuse2k_efs_enk2 : 1; // [0]
        uint32_t dbg_sel_analog_efuse2k_efs_enk1 : 1; // [1]
        uint32_t __31_2 : 30;                         // [31:2]
    } b;
} REG_ANALOG_G1_ANALOG_EFUSE2K_REG_SEL_CFG_0_T;

// analog_apll_apll_ctrl1
#define ANALOG_G1_ANALOG_APLL_APLL_IL_DIV2 (1 << 0)
#define ANALOG_G1_ANALOG_APLL_APLL_N(n) (((n)&0x7ff) << 1)
#define ANALOG_G1_ANALOG_APLL_APLL_REF_SEL (1 << 12)
#define ANALOG_G1_ANALOG_APLL_APLL_LPF(n) (((n)&0x7) << 13)
#define ANALOG_G1_ANALOG_APLL_APLL_IBIAS(n) (((n)&0x3) << 16)
#define ANALOG_G1_ANALOG_APLL_APLL_CLKOUT_EN (1 << 18)

// analog_apll_apll_ctrl2
#define ANALOG_G1_ANALOG_APLL_APLL_PD (1 << 0)
#define ANALOG_G1_ANALOG_APLL_APLL_RST (1 << 1)
#define ANALOG_G1_ANALOG_APLL_APLL_LOCK_DONE (1 << 2)
#define ANALOG_G1_ANALOG_APLL_APLL_HOP_TRIG (1 << 3)
#define ANALOG_G1_ANALOG_APLL_APLL_HOP_EN (1 << 4)
#define ANALOG_G1_ANALOG_APLL_APLL_DIVN(n) (((n)&0x7) << 5)
#define ANALOG_G1_ANALOG_APLL_APLL_MOD_EN (1 << 8)
#define ANALOG_G1_ANALOG_APLL_APLL_SDM_EN (1 << 9)
#define ANALOG_G1_ANALOG_APLL_APLL_DIV_S (1 << 10)
#define ANALOG_G1_ANALOG_APLL_APLL_OL_DIV2(n) (((n)&0x7) << 11)

// analog_apll_apll_int_value
#define ANALOG_G1_ANALOG_APLL_APLL_KINT(n) (((n)&0xfffff) << 0)
#define ANALOG_G1_ANALOG_APLL_APLL_NINT(n) (((n)&0x7f) << 20)

// analog_apll_apll_ccs_ctrl
#define ANALOG_G1_ANALOG_APLL_APLL_CCS_CTRL(n) (((n)&0xffff) << 0)

// analog_apll_apll_kstep
#define ANALOG_G1_ANALOG_APLL_APLL_KSTEP(n) (((n)&0x7ffff) << 0)

// analog_apll_ana_bias
#define ANALOG_G1_ANALOG_APLL_APLL_TEST_EN (1 << 0)
#define ANALOG_G1_ANALOG_APLL_APLL_BIST_EN (1 << 1)
#define ANALOG_G1_ANALOG_APLL_APLL_BIST_CTRL(n) (((n)&0x3ff) << 2)
#define ANALOG_G1_ANALOG_APLL_APLL_BIAS_TOP(n) (((n)&0x1f) << 12)

// analog_apll_ana_bias1
#define ANALOG_G1_ANALOG_APLL_APLL_DVDDISO (1 << 0)
#define ANALOG_G1_ANALOG_APLL_APLL_PRECHARGE (1 << 1)
#define ANALOG_G1_ANALOG_APLL_APLL_DUTYFIX (1 << 2)
#define ANALOG_G1_ANALOG_APLL_APLL_BIST_CNT(n) (((n)&0xffff) << 3)

// analog_apll_reg_sel_cfg_0
#define ANALOG_G1_DBG_SEL_ANALOG_APLL_APLL_DVDDISO (1 << 0)
#define ANALOG_G1_DBG_SEL_ANALOG_APLL_APLL_PRECHARGE (1 << 1)
#define ANALOG_G1_DBG_SEL_ANALOG_APLL_APLL_PD (1 << 2)
#define ANALOG_G1_DBG_SEL_ANALOG_APLL_APLL_RST (1 << 3)
#define ANALOG_G1_DBG_SEL_ANALOG_APLL_APLL_CLKOUT_EN (1 << 4)

// analog_mpll_apll_ctrl1
#define ANALOG_G1_ANALOG_MPLL_APLL_IL_DIV2 (1 << 0)
#define ANALOG_G1_ANALOG_MPLL_APLL_N(n) (((n)&0x7ff) << 1)
#define ANALOG_G1_ANALOG_MPLL_APLL_REF_SEL (1 << 12)
#define ANALOG_G1_ANALOG_MPLL_APLL_LPF(n) (((n)&0x7) << 13)
#define ANALOG_G1_ANALOG_MPLL_APLL_IBIAS(n) (((n)&0x3) << 16)
#define ANALOG_G1_ANALOG_MPLL_APLL_CLKOUT_EN (1 << 18)

// analog_mpll_apll_ctrl2
#define ANALOG_G1_ANALOG_MPLL_APLL_PD (1 << 0)
#define ANALOG_G1_ANALOG_MPLL_APLL_RST (1 << 1)
#define ANALOG_G1_ANALOG_MPLL_APLL_LOCK_DONE (1 << 2)
#define ANALOG_G1_ANALOG_MPLL_APLL_HOP_TRIG (1 << 3)
#define ANALOG_G1_ANALOG_MPLL_APLL_HOP_EN (1 << 4)
#define ANALOG_G1_ANALOG_MPLL_APLL_DIVN(n) (((n)&0x7) << 5)
#define ANALOG_G1_ANALOG_MPLL_APLL_MOD_EN (1 << 8)
#define ANALOG_G1_ANALOG_MPLL_APLL_SDM_EN (1 << 9)
#define ANALOG_G1_ANALOG_MPLL_APLL_DIV_S (1 << 10)
#define ANALOG_G1_ANALOG_MPLL_APLL_OL_DIV2(n) (((n)&0x7) << 11)

// analog_mpll_apll_int_value
#define ANALOG_G1_ANALOG_MPLL_APLL_KINT(n) (((n)&0xfffff) << 0)
#define ANALOG_G1_ANALOG_MPLL_APLL_NINT(n) (((n)&0x7f) << 20)

// analog_mpll_apll_ccs_ctrl
#define ANALOG_G1_ANALOG_MPLL_APLL_CCS_CTRL(n) (((n)&0xffff) << 0)

// analog_mpll_apll_kstep
#define ANALOG_G1_ANALOG_MPLL_APLL_KSTEP(n) (((n)&0x7ffff) << 0)

// analog_mpll_ana_bias
#define ANALOG_G1_ANALOG_MPLL_APLL_TEST_EN (1 << 0)
#define ANALOG_G1_ANALOG_MPLL_APLL_BIST_EN (1 << 1)
#define ANALOG_G1_ANALOG_MPLL_APLL_BIST_CTRL(n) (((n)&0x3ff) << 2)
#define ANALOG_G1_ANALOG_MPLL_APLL_BIAS_TOP(n) (((n)&0x1f) << 12)

// analog_mpll_ana_bias1
#define ANALOG_G1_ANALOG_MPLL_APLL_DVDDISO (1 << 0)
#define ANALOG_G1_ANALOG_MPLL_APLL_PRECHARGE (1 << 1)
#define ANALOG_G1_ANALOG_MPLL_APLL_DUTYFIX (1 << 2)
#define ANALOG_G1_ANALOG_MPLL_APLL_BIST_CNT(n) (((n)&0xffff) << 3)

// analog_mpll_reg_sel_cfg_0
#define ANALOG_G1_DBG_SEL_ANALOG_MPLL_APLL_DVDDISO (1 << 0)
#define ANALOG_G1_DBG_SEL_ANALOG_MPLL_APLL_PRECHARGE (1 << 1)
#define ANALOG_G1_DBG_SEL_ANALOG_MPLL_APLL_PD (1 << 2)
#define ANALOG_G1_DBG_SEL_ANALOG_MPLL_APLL_RST (1 << 3)
#define ANALOG_G1_DBG_SEL_ANALOG_MPLL_APLL_CLKOUT_EN (1 << 4)

// analog_iis_pll_apll_ctrl1
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_IL_DIV2 (1 << 0)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_N(n) (((n)&0x7ff) << 1)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_REF_SEL (1 << 12)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_LPF(n) (((n)&0x7) << 13)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_IBIAS(n) (((n)&0x3) << 16)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_CLKOUT_EN (1 << 18)

// analog_iis_pll_apll_ctrl2
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_PD (1 << 0)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_RST (1 << 1)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_LOCK_DONE (1 << 2)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_HOP_TRIG (1 << 3)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_HOP_EN (1 << 4)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_DIVN(n) (((n)&0x7) << 5)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_MOD_EN (1 << 8)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_SDM_EN (1 << 9)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_DIV_S (1 << 10)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_OL_DIV2(n) (((n)&0x7) << 11)

// analog_iis_pll_apll_int_value
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_KINT(n) (((n)&0xfffff) << 0)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_NINT(n) (((n)&0x7f) << 20)

// analog_iis_pll_apll_ccs_ctrl
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_CCS_CTRL(n) (((n)&0xffff) << 0)

// analog_iis_pll_apll_kstep
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_KSTEP(n) (((n)&0x7ffff) << 0)

// analog_iis_pll_ana_bias
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_TEST_EN (1 << 0)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_BIST_EN (1 << 1)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_BIST_CTRL(n) (((n)&0x3ff) << 2)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_BIAS_TOP(n) (((n)&0x1f) << 12)

// analog_iis_pll_ana_bias1
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_DVDDISO (1 << 0)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_PRECHARGE (1 << 1)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_DUTYFIX (1 << 2)
#define ANALOG_G1_ANALOG_IIS_PLL_APLL_BIST_CNT(n) (((n)&0xffff) << 3)

// analog_iis_pll_reg_sel_cfg_0
#define ANALOG_G1_DBG_SEL_ANALOG_IIS_PLL_APLL_DVDDISO (1 << 0)
#define ANALOG_G1_DBG_SEL_ANALOG_IIS_PLL_APLL_PRECHARGE (1 << 1)
#define ANALOG_G1_DBG_SEL_ANALOG_IIS_PLL_APLL_PD (1 << 2)
#define ANALOG_G1_DBG_SEL_ANALOG_IIS_PLL_APLL_RST (1 << 3)
#define ANALOG_G1_DBG_SEL_ANALOG_IIS_PLL_APLL_CLKOUT_EN (1 << 4)

// analog_efuse4k_efuse_pin_pw_ctl
#define ANALOG_G1_ANALOG_EFUSE4K_EFS_ENK2 (1 << 0)
#define ANALOG_G1_ANALOG_EFUSE4K_EFS_ENK1 (1 << 1)

// analog_efuse4k_reg_sel_cfg_0
#define ANALOG_G1_DBG_SEL_ANALOG_EFUSE4K_EFS_ENK2 (1 << 0)
#define ANALOG_G1_DBG_SEL_ANALOG_EFUSE4K_EFS_ENK1 (1 << 1)

// analog_efuse2k_efuse_pin_pw_ctl
#define ANALOG_G1_ANALOG_EFUSE2K_EFS_ENK2 (1 << 0)
#define ANALOG_G1_ANALOG_EFUSE2K_EFS_ENK1 (1 << 1)

// analog_efuse2k_reg_sel_cfg_0
#define ANALOG_G1_DBG_SEL_ANALOG_EFUSE2K_EFS_ENK2 (1 << 0)
#define ANALOG_G1_DBG_SEL_ANALOG_EFUSE2K_EFS_ENK1 (1 << 1)

#endif // _ANALOG_G1_H_