EC600G/components/hal/include/hwregs/8850/aon_clk.h

/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _AON_CLK_H_
#define _AON_CLK_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_AON_CLK_BASE (0x51508800)

typedef volatile struct
{
    uint32_t __0[9];                        // 0x00000000
    uint32_t cgm_aon_ahb_div_cfg;           // 0x00000024
    uint32_t cgm_aon_ahb_sel_cfg;           // 0x00000028
    uint32_t __44[2];                       // 0x0000002c
    uint32_t cgm_uart2_bf_div_sel_cfg;      // 0x00000034
    uint32_t __56[2];                       // 0x00000038
    uint32_t cgm_uart3_bf_div_sel_cfg;      // 0x00000040
    uint32_t __68[2];                       // 0x00000044
    uint32_t cgm_debug_host_bf_div_sel_cfg; // 0x0000004c
    uint32_t __80[1];                       // 0x00000050
    uint32_t cgm_audio_div_cfg;             // 0x00000054
    uint32_t cgm_audio_sel_cfg;             // 0x00000058
    uint32_t __92[1];                       // 0x0000005c
    uint32_t cgm_codec_mclock_div_cfg;      // 0x00000060
    uint32_t cgm_codec_mclock_sel_cfg;      // 0x00000064
    uint32_t __104[1];                      // 0x00000068
    uint32_t cgm_i2s_bck_bf_div_div_cfg;    // 0x0000006c
    uint32_t cgm_i2s_bck_bf_div_sel_cfg;    // 0x00000070
    uint32_t __116[1];                      // 0x00000074
    uint32_t cgm_out_div_cfg;               // 0x00000078
    uint32_t cgm_out_sel_cfg;               // 0x0000007c
    uint32_t __128[2];                      // 0x00000080
    uint32_t cgm_efuse_sel_cfg;             // 0x00000088
    uint32_t __140[2];                      // 0x0000008c
    uint32_t cgm_adi_sel_cfg;               // 0x00000094
    uint32_t __152[2];                      // 0x00000098
    uint32_t cgm_dap_sel_cfg;               // 0x000000a0
    uint32_t __164[11];                     // 0x000000a4
    uint32_t cgm_djtag_tck_sel_cfg;         // 0x000000d0
    uint32_t __212[2];                      // 0x000000d4
    uint32_t cgm_swcgm_hw_sel_cfg;          // 0x000000dc
    uint32_t __224[2];                      // 0x000000e0
    uint32_t cgm_gpt2_sel_cfg;              // 0x000000e8
    uint32_t __236[2];                      // 0x000000ec
    uint32_t cgm_i2c3_sel_cfg;              // 0x000000f4
    uint32_t __248[5];                      // 0x000000f8
    uint32_t cgm_usb_ref_sel_cfg;           // 0x0000010c
    uint32_t __272[1];                      // 0x00000110
    uint32_t cgm_usb_ahb_div_cfg;           // 0x00000114
    uint32_t cgm_usb_ahb_sel_cfg;           // 0x00000118
    uint32_t __284[1];                      // 0x0000011c
    uint32_t cgm_spi2_div_cfg;              // 0x00000120
    uint32_t cgm_spi2_sel_cfg;              // 0x00000124
    uint32_t __296[2];                      // 0x00000128
    uint32_t cgm_scc_sel_cfg;               // 0x00000130
    uint32_t __308[1];                      // 0x00000134
    uint32_t cgm_sdio_2x_div_cfg;           // 0x00000138
    uint32_t cgm_sdio_2x_sel_cfg;           // 0x0000013c
    uint32_t __320[1];                      // 0x00000140
    uint32_t cgm_sdio_1x_div_cfg;           // 0x00000144
    uint32_t __328[19];                     // 0x00000148
    uint32_t cgm_busy_src_monitor_cfg0;     // 0x00000194
    uint32_t cgm_busy_src_monitor_cfg1;     // 0x00000198
    uint32_t cgm_busy_src_monitor_cfg2;     // 0x0000019c
    uint32_t cgm_busy_src_monitor_cfg3;     // 0x000001a0
} HWP_AON_CLK_T;

#define hwp_aonClk ((HWP_AON_CLK_T *)REG_ACCESS_ADDRESS(REG_AON_CLK_BASE))

// cgm_aon_ahb_div_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_aon_ahb_div : 2; // [1:0]
        uint32_t __31_2 : 30;         // [31:2]
    } b;
} REG_AON_CLK_CGM_AON_AHB_DIV_CFG_T;

// cgm_aon_ahb_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_aon_ahb_sel : 3; // [2:0]
        uint32_t __31_3 : 29;         // [31:3]
    } b;
} REG_AON_CLK_CGM_AON_AHB_SEL_CFG_T;

// cgm_uart2_bf_div_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_uart2_bf_div_sel : 3; // [2:0]
        uint32_t __31_3 : 29;              // [31:3]
    } b;
} REG_AON_CLK_CGM_UART2_BF_DIV_SEL_CFG_T;

// cgm_uart3_bf_div_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_uart3_bf_div_sel : 3; // [2:0]
        uint32_t __31_3 : 29;              // [31:3]
    } b;
} REG_AON_CLK_CGM_UART3_BF_DIV_SEL_CFG_T;

// cgm_debug_host_bf_div_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_debug_host_bf_div_sel : 2; // [1:0]
        uint32_t __31_2 : 30;                   // [31:2]
    } b;
} REG_AON_CLK_CGM_DEBUG_HOST_BF_DIV_SEL_CFG_T;

// cgm_audio_div_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_audio_div : 4; // [3:0]
        uint32_t __31_4 : 28;       // [31:4]
    } b;
} REG_AON_CLK_CGM_AUDIO_DIV_CFG_T;

// cgm_audio_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_audio_sel : 3; // [2:0]
        uint32_t __31_3 : 29;       // [31:3]
    } b;
} REG_AON_CLK_CGM_AUDIO_SEL_CFG_T;

// cgm_codec_mclock_div_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_codec_mclock_div : 4; // [3:0]
        uint32_t __31_4 : 28;              // [31:4]
    } b;
} REG_AON_CLK_CGM_CODEC_MCLOCK_DIV_CFG_T;

// cgm_codec_mclock_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_codec_mclock_sel : 3; // [2:0]
        uint32_t __31_3 : 29;              // [31:3]
    } b;
} REG_AON_CLK_CGM_CODEC_MCLOCK_SEL_CFG_T;

// cgm_i2s_bck_bf_div_div_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_i2s_bck_bf_div_div : 12; // [11:0]
        uint32_t __31_12 : 20;                // [31:12]
    } b;
} REG_AON_CLK_CGM_I2S_BCK_BF_DIV_DIV_CFG_T;

// cgm_i2s_bck_bf_div_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_i2s_bck_bf_div_sel : 3;     // [2:0]
        uint32_t __15_3 : 13;                    // [15:3]
        uint32_t cgm_i2s_bck_bf_div_pad_sel : 1; // [16]
        uint32_t __31_17 : 15;                   // [31:17]
    } b;
} REG_AON_CLK_CGM_I2S_BCK_BF_DIV_SEL_CFG_T;

// cgm_out_div_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_out_div : 8; // [7:0]
        uint32_t __31_8 : 24;     // [31:8]
    } b;
} REG_AON_CLK_CGM_OUT_DIV_CFG_T;

// cgm_out_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_out_sel : 3; // [2:0]
        uint32_t __31_3 : 29;     // [31:3]
    } b;
} REG_AON_CLK_CGM_OUT_SEL_CFG_T;

// cgm_efuse_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_efuse_sel : 2; // [1:0]
        uint32_t __31_2 : 30;       // [31:2]
    } b;
} REG_AON_CLK_CGM_EFUSE_SEL_CFG_T;

// cgm_adi_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_adi_sel : 2; // [1:0]
        uint32_t __31_2 : 30;     // [31:2]
    } b;
} REG_AON_CLK_CGM_ADI_SEL_CFG_T;

// cgm_dap_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_dap_sel : 3; // [2:0]
        uint32_t __31_3 : 29;     // [31:3]
    } b;
} REG_AON_CLK_CGM_DAP_SEL_CFG_T;

// cgm_djtag_tck_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_djtag_tck_sel : 1;     // [0]
        uint32_t __15_1 : 15;               // [15:1]
        uint32_t cgm_djtag_tck_pad_sel : 1; // [16]
        uint32_t __31_17 : 15;              // [31:17]
    } b;
} REG_AON_CLK_CGM_DJTAG_TCK_SEL_CFG_T;

// cgm_swcgm_hw_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __15_0 : 16;              // [15:0]
        uint32_t cgm_swcgm_hw_pad_sel : 1; // [16]
        uint32_t __31_17 : 15;             // [31:17]
    } b;
} REG_AON_CLK_CGM_SWCGM_HW_SEL_CFG_T;

// cgm_gpt2_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_gpt2_sel : 3; // [2:0]
        uint32_t __31_3 : 29;      // [31:3]
    } b;
} REG_AON_CLK_CGM_GPT2_SEL_CFG_T;

// cgm_i2c3_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_i2c3_sel : 3; // [2:0]
        uint32_t __31_3 : 29;      // [31:3]
    } b;
} REG_AON_CLK_CGM_I2C3_SEL_CFG_T;

// cgm_usb_ref_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_usb_ref_sel : 1; // [0]
        uint32_t __31_1 : 31;         // [31:1]
    } b;
} REG_AON_CLK_CGM_USB_REF_SEL_CFG_T;

// cgm_usb_ahb_div_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_usb_ahb_div : 2; // [1:0]
        uint32_t __31_2 : 30;         // [31:2]
    } b;
} REG_AON_CLK_CGM_USB_AHB_DIV_CFG_T;

// cgm_usb_ahb_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_usb_ahb_sel : 3; // [2:0]
        uint32_t __31_3 : 29;         // [31:3]
    } b;
} REG_AON_CLK_CGM_USB_AHB_SEL_CFG_T;

// cgm_spi2_div_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_spi2_div : 3; // [2:0]
        uint32_t __31_3 : 29;      // [31:3]
    } b;
} REG_AON_CLK_CGM_SPI2_DIV_CFG_T;

// cgm_spi2_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_spi2_sel : 3;     // [2:0]
        uint32_t __15_3 : 13;          // [15:3]
        uint32_t cgm_spi2_pad_sel : 1; // [16]
        uint32_t __31_17 : 15;         // [31:17]
    } b;
} REG_AON_CLK_CGM_SPI2_SEL_CFG_T;

// cgm_scc_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __15_0 : 16;         // [15:0]
        uint32_t cgm_scc_pad_sel : 1; // [16]
        uint32_t __31_17 : 15;        // [31:17]
    } b;
} REG_AON_CLK_CGM_SCC_SEL_CFG_T;

// cgm_sdio_2x_div_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_sdio_2x_div : 11; // [10:0]
        uint32_t __31_11 : 21;         // [31:11]
    } b;
} REG_AON_CLK_CGM_SDIO_2X_DIV_CFG_T;

// cgm_sdio_2x_sel_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_sdio_2x_sel : 3; // [2:0]
        uint32_t __31_3 : 29;         // [31:3]
    } b;
} REG_AON_CLK_CGM_SDIO_2X_SEL_CFG_T;

// cgm_sdio_1x_div_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_sdio_1x_div : 1; // [0]
        uint32_t __31_1 : 31;         // [31:1]
    } b;
} REG_AON_CLK_CGM_SDIO_1X_DIV_CFG_T;

// cgm_aon_ahb_div_cfg
#define AON_CLK_CGM_AON_AHB_DIV(n) (((n)&0x3) << 0)

// cgm_aon_ahb_sel_cfg
#define AON_CLK_CGM_AON_AHB_SEL(n) (((n)&0x7) << 0)

// cgm_uart2_bf_div_sel_cfg
#define AON_CLK_CGM_UART2_BF_DIV_SEL(n) (((n)&0x7) << 0)

// cgm_uart3_bf_div_sel_cfg
#define AON_CLK_CGM_UART3_BF_DIV_SEL(n) (((n)&0x7) << 0)

// cgm_debug_host_bf_div_sel_cfg
#define AON_CLK_CGM_DEBUG_HOST_BF_DIV_SEL(n) (((n)&0x3) << 0)

// cgm_audio_div_cfg
#define AON_CLK_CGM_AUDIO_DIV(n) (((n)&0xf) << 0)

// cgm_audio_sel_cfg
#define AON_CLK_CGM_AUDIO_SEL(n) (((n)&0x7) << 0)

// cgm_codec_mclock_div_cfg
#define AON_CLK_CGM_CODEC_MCLOCK_DIV(n) (((n)&0xf) << 0)

// cgm_codec_mclock_sel_cfg
#define AON_CLK_CGM_CODEC_MCLOCK_SEL(n) (((n)&0x7) << 0)

// cgm_i2s_bck_bf_div_div_cfg
#define AON_CLK_CGM_I2S_BCK_BF_DIV_DIV(n) (((n)&0xfff) << 0)

// cgm_i2s_bck_bf_div_sel_cfg
#define AON_CLK_CGM_I2S_BCK_BF_DIV_SEL(n) (((n)&0x7) << 0)
#define AON_CLK_CGM_I2S_BCK_BF_DIV_PAD_SEL (1 << 16)

// cgm_out_div_cfg
#define AON_CLK_CGM_OUT_DIV(n) (((n)&0xff) << 0)

// cgm_out_sel_cfg
#define AON_CLK_CGM_OUT_SEL(n) (((n)&0x7) << 0)

// cgm_efuse_sel_cfg
#define AON_CLK_CGM_EFUSE_SEL(n) (((n)&0x3) << 0)

// cgm_adi_sel_cfg
#define AON_CLK_CGM_ADI_SEL(n) (((n)&0x3) << 0)

// cgm_dap_sel_cfg
#define AON_CLK_CGM_DAP_SEL(n) (((n)&0x7) << 0)

// cgm_djtag_tck_sel_cfg
#define AON_CLK_CGM_DJTAG_TCK_SEL (1 << 0)
#define AON_CLK_CGM_DJTAG_TCK_PAD_SEL (1 << 16)

// cgm_swcgm_hw_sel_cfg
#define AON_CLK_CGM_SWCGM_HW_PAD_SEL (1 << 16)

// cgm_gpt2_sel_cfg
#define AON_CLK_CGM_GPT2_SEL(n) (((n)&0x7) << 0)

// cgm_i2c3_sel_cfg
#define AON_CLK_CGM_I2C3_SEL(n) (((n)&0x7) << 0)

// cgm_usb_ref_sel_cfg
#define AON_CLK_CGM_USB_REF_SEL (1 << 0)

// cgm_usb_ahb_div_cfg
#define AON_CLK_CGM_USB_AHB_DIV(n) (((n)&0x3) << 0)

// cgm_usb_ahb_sel_cfg
#define AON_CLK_CGM_USB_AHB_SEL(n) (((n)&0x7) << 0)

// cgm_spi2_div_cfg
#define AON_CLK_CGM_SPI2_DIV(n) (((n)&0x7) << 0)

// cgm_spi2_sel_cfg
#define AON_CLK_CGM_SPI2_SEL(n) (((n)&0x7) << 0)
#define AON_CLK_CGM_SPI2_PAD_SEL (1 << 16)

// cgm_scc_sel_cfg
#define AON_CLK_CGM_SCC_PAD_SEL (1 << 16)

// cgm_sdio_2x_div_cfg
#define AON_CLK_CGM_SDIO_2X_DIV(n) (((n)&0x7ff) << 0)

// cgm_sdio_2x_sel_cfg
#define AON_CLK_CGM_SDIO_2X_SEL(n) (((n)&0x7) << 0)

// cgm_sdio_1x_div_cfg
#define AON_CLK_CGM_SDIO_1X_DIV (1 << 0)

#endif // _AON_CLK_H_