EC600G/components/hal/include/hwregs/8850/cp_sysram_patch.h

/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _CP_SYSRAM_PATCH_H_
#define _CP_SYSRAM_PATCH_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_CP_SYSRAM_PATCH_BASE (0x14003000)

typedef volatile struct
{
    uint32_t patch00;       // 0x00000000
    uint32_t patch01;       // 0x00000004
    uint32_t patch02;       // 0x00000008
    uint32_t patch03;       // 0x0000000c
    uint32_t patch04;       // 0x00000010
    uint32_t patch05;       // 0x00000014
    uint32_t patch06;       // 0x00000018
    uint32_t patch07;       // 0x0000001c
    uint32_t patch08;       // 0x00000020
    uint32_t patch09;       // 0x00000024
    uint32_t patch10;       // 0x00000028
    uint32_t patch11;       // 0x0000002c
    uint32_t patch12;       // 0x00000030
    uint32_t patch13;       // 0x00000034
    uint32_t patch14;       // 0x00000038
    uint32_t patch15;       // 0x0000003c
    uint32_t patch16;       // 0x00000040
    uint32_t patch17;       // 0x00000044
    uint32_t patch18;       // 0x00000048
    uint32_t patch19;       // 0x0000004c
    uint32_t patch20;       // 0x00000050
    uint32_t patch21;       // 0x00000054
    uint32_t patch22;       // 0x00000058
    uint32_t patch23;       // 0x0000005c
    uint32_t patch24;       // 0x00000060
    uint32_t patch25;       // 0x00000064
    uint32_t patch26;       // 0x00000068
    uint32_t patch27;       // 0x0000006c
    uint32_t patch28;       // 0x00000070
    uint32_t patch29;       // 0x00000074
    uint32_t patch30;       // 0x00000078
    uint32_t patch31;       // 0x0000007c
    uint32_t pagespy0_cfg0; // 0x00000080
    uint32_t pagespy0_cfg1; // 0x00000084
    uint32_t pagespy1_cfg0; // 0x00000088
    uint32_t pagespy1_cfg1; // 0x0000008c
    uint32_t pagespy2_cfg0; // 0x00000090
    uint32_t pagespy2_cfg1; // 0x00000094
    uint32_t pagespy3_cfg0; // 0x00000098
    uint32_t pagespy3_cfg1; // 0x0000009c
    uint32_t pagespy0_sta0; // 0x000000a0
    uint32_t pagespy0_sta1; // 0x000000a4
    uint32_t pagespy1_sta0; // 0x000000a8
    uint32_t pagespy1_sta1; // 0x000000ac
    uint32_t pagespy2_sta0; // 0x000000b0
    uint32_t pagespy2_sta1; // 0x000000b4
    uint32_t pagespy3_sta0; // 0x000000b8
    uint32_t pagespy3_sta1; // 0x000000bc
} HWP_CP_SYSRAM_PATCH_T;

#define hwp_cpSysramPatch ((HWP_CP_SYSRAM_PATCH_T *)REG_ACCESS_ADDRESS(REG_CP_SYSRAM_PATCH_BASE))

// patch00
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs00 : 28; // [27:0]
        uint32_t patch_valid00 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH00_T;

// patch01
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs01 : 28; // [27:0]
        uint32_t patch_valid01 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH01_T;

// patch02
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs02 : 28; // [27:0]
        uint32_t patch_valid02 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH02_T;

// patch03
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs03 : 28; // [27:0]
        uint32_t patch_valid03 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH03_T;

// patch04
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs04 : 28; // [27:0]
        uint32_t patch_valid04 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH04_T;

// patch05
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs05 : 28; // [27:0]
        uint32_t patch_valid05 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH05_T;

// patch06
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs06 : 28; // [27:0]
        uint32_t patch_valid06 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH06_T;

// patch07
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs07 : 28; // [27:0]
        uint32_t patch_valid07 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH07_T;

// patch08
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs08 : 28; // [27:0]
        uint32_t patch_valid08 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH08_T;

// patch09
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs09 : 28; // [27:0]
        uint32_t patch_valid09 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH09_T;

// patch10
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs10 : 28; // [27:0]
        uint32_t patch_valid10 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH10_T;

// patch11
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs11 : 28; // [27:0]
        uint32_t patch_valid11 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH11_T;

// patch12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs12 : 28; // [27:0]
        uint32_t patch_valid12 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH12_T;

// patch13
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs13 : 28; // [27:0]
        uint32_t patch_valid13 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH13_T;

// patch14
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs14 : 28; // [27:0]
        uint32_t patch_valid14 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH14_T;

// patch15
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs15 : 28; // [27:0]
        uint32_t patch_valid15 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH15_T;

// patch16
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs16 : 28; // [27:0]
        uint32_t patch_valid16 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH16_T;

// patch17
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs17 : 28; // [27:0]
        uint32_t patch_valid17 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH17_T;

// patch18
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs18 : 28; // [27:0]
        uint32_t patch_valid18 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH18_T;

// patch19
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs19 : 28; // [27:0]
        uint32_t patch_valid19 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH19_T;

// patch20
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs20 : 28; // [27:0]
        uint32_t patch_valid20 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH20_T;

// patch21
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs21 : 28; // [27:0]
        uint32_t patch_valid21 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH21_T;

// patch22
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs22 : 28; // [27:0]
        uint32_t patch_valid22 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH22_T;

// patch23
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs23 : 28; // [27:0]
        uint32_t patch_valid23 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH23_T;

// patch24
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs24 : 28; // [27:0]
        uint32_t patch_valid24 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH24_T;

// patch25
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs25 : 28; // [27:0]
        uint32_t patch_valid25 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH25_T;

// patch26
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs26 : 28; // [27:0]
        uint32_t patch_valid26 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH26_T;

// patch27
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs27 : 28; // [27:0]
        uint32_t patch_valid27 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH27_T;

// patch28
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs28 : 28; // [27:0]
        uint32_t patch_valid28 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH28_T;

// patch29
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs29 : 28; // [27:0]
        uint32_t patch_valid29 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH29_T;

// patch30
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs30 : 28; // [27:0]
        uint32_t patch_valid30 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH30_T;

// patch31
typedef union {
    uint32_t v;
    struct
    {
        uint32_t patch_addrs31 : 28; // [27:0]
        uint32_t patch_valid31 : 1;  // [28]
        uint32_t __31_29 : 3;        // [31:29]
    } b;
} REG_CP_SYSRAM_PATCH_PATCH31_T;

// pagespy0_cfg0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_sta_addr0 : 28; // [27:0]
        uint32_t pagespy_detectw0 : 1;   // [28]
        uint32_t pagespy_detectr0 : 1;   // [29]
        uint32_t pagespy_enable0 : 1;    // [30]
        uint32_t __31_31 : 1;            // [31]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY0_CFG0_T;

// pagespy0_cfg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_end_addr0 : 28; // [27:0]
        uint32_t __31_28 : 4;            // [31:28]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY0_CFG1_T;

// pagespy1_cfg0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_sta_addr1 : 28; // [27:0]
        uint32_t pagespy_detectw1 : 1;   // [28]
        uint32_t pagespy_detectr1 : 1;   // [29]
        uint32_t pagespy_enable1 : 1;    // [30]
        uint32_t __31_31 : 1;            // [31]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY1_CFG0_T;

// pagespy1_cfg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_end_addr1 : 28; // [27:0]
        uint32_t __31_28 : 4;            // [31:28]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY1_CFG1_T;

// pagespy2_cfg0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_sta_addr2 : 28; // [27:0]
        uint32_t pagespy_detectw2 : 1;   // [28]
        uint32_t pagespy_detectr2 : 1;   // [29]
        uint32_t pagespy_enable2 : 1;    // [30]
        uint32_t __31_31 : 1;            // [31]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY2_CFG0_T;

// pagespy2_cfg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_end_addr2 : 28; // [27:0]
        uint32_t __31_28 : 4;            // [31:28]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY2_CFG1_T;

// pagespy3_cfg0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_sta_addr3 : 28; // [27:0]
        uint32_t pagespy_detectw3 : 1;   // [28]
        uint32_t pagespy_detectr3 : 1;   // [29]
        uint32_t pagespy_enable3 : 1;    // [30]
        uint32_t __31_31 : 1;            // [31]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY3_CFG0_T;

// pagespy3_cfg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_end_addr3 : 28; // [27:0]
        uint32_t __31_28 : 4;            // [31:28]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY3_CFG1_T;

// pagespy0_sta0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_aid0 : 16;   // [15:0], read only
        uint32_t pagespy_hitw0 : 1;   // [16], read only
        uint32_t pagespy_hitr0 : 1;   // [17], read only
        uint32_t pagespy_status0 : 1; // [18], read only
        uint32_t __31_19 : 13;        // [31:19]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY0_STA0_T;

// pagespy1_sta0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_aid1 : 16;   // [15:0], read only
        uint32_t pagespy_hitw1 : 1;   // [16], read only
        uint32_t pagespy_hitr1 : 1;   // [17], read only
        uint32_t pagespy_status1 : 1; // [18], read only
        uint32_t __31_19 : 13;        // [31:19]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY1_STA0_T;

// pagespy2_sta0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_aid2 : 16;   // [15:0], read only
        uint32_t pagespy_hitw2 : 1;   // [16], read only
        uint32_t pagespy_hitr2 : 1;   // [17], read only
        uint32_t pagespy_status2 : 1; // [18], read only
        uint32_t __31_19 : 13;        // [31:19]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY2_STA0_T;

// pagespy3_sta0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pagespy_aid3 : 16;   // [15:0], read only
        uint32_t pagespy_hitw3 : 1;   // [16], read only
        uint32_t pagespy_hitr3 : 1;   // [17], read only
        uint32_t pagespy_status3 : 1; // [18], read only
        uint32_t __31_19 : 13;        // [31:19]
    } b;
} REG_CP_SYSRAM_PATCH_PAGESPY3_STA0_T;

// patch00
#define CP_SYSRAM_PATCH_PATCH_ADDRS00(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID00 (1 << 28)

// patch01
#define CP_SYSRAM_PATCH_PATCH_ADDRS01(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID01 (1 << 28)

// patch02
#define CP_SYSRAM_PATCH_PATCH_ADDRS02(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID02 (1 << 28)

// patch03
#define CP_SYSRAM_PATCH_PATCH_ADDRS03(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID03 (1 << 28)

// patch04
#define CP_SYSRAM_PATCH_PATCH_ADDRS04(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID04 (1 << 28)

// patch05
#define CP_SYSRAM_PATCH_PATCH_ADDRS05(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID05 (1 << 28)

// patch06
#define CP_SYSRAM_PATCH_PATCH_ADDRS06(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID06 (1 << 28)

// patch07
#define CP_SYSRAM_PATCH_PATCH_ADDRS07(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID07 (1 << 28)

// patch08
#define CP_SYSRAM_PATCH_PATCH_ADDRS08(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID08 (1 << 28)

// patch09
#define CP_SYSRAM_PATCH_PATCH_ADDRS09(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID09 (1 << 28)

// patch10
#define CP_SYSRAM_PATCH_PATCH_ADDRS10(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID10 (1 << 28)

// patch11
#define CP_SYSRAM_PATCH_PATCH_ADDRS11(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID11 (1 << 28)

// patch12
#define CP_SYSRAM_PATCH_PATCH_ADDRS12(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID12 (1 << 28)

// patch13
#define CP_SYSRAM_PATCH_PATCH_ADDRS13(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID13 (1 << 28)

// patch14
#define CP_SYSRAM_PATCH_PATCH_ADDRS14(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID14 (1 << 28)

// patch15
#define CP_SYSRAM_PATCH_PATCH_ADDRS15(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID15 (1 << 28)

// patch16
#define CP_SYSRAM_PATCH_PATCH_ADDRS16(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID16 (1 << 28)

// patch17
#define CP_SYSRAM_PATCH_PATCH_ADDRS17(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID17 (1 << 28)

// patch18
#define CP_SYSRAM_PATCH_PATCH_ADDRS18(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID18 (1 << 28)

// patch19
#define CP_SYSRAM_PATCH_PATCH_ADDRS19(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID19 (1 << 28)

// patch20
#define CP_SYSRAM_PATCH_PATCH_ADDRS20(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID20 (1 << 28)

// patch21
#define CP_SYSRAM_PATCH_PATCH_ADDRS21(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID21 (1 << 28)

// patch22
#define CP_SYSRAM_PATCH_PATCH_ADDRS22(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID22 (1 << 28)

// patch23
#define CP_SYSRAM_PATCH_PATCH_ADDRS23(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID23 (1 << 28)

// patch24
#define CP_SYSRAM_PATCH_PATCH_ADDRS24(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID24 (1 << 28)

// patch25
#define CP_SYSRAM_PATCH_PATCH_ADDRS25(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID25 (1 << 28)

// patch26
#define CP_SYSRAM_PATCH_PATCH_ADDRS26(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID26 (1 << 28)

// patch27
#define CP_SYSRAM_PATCH_PATCH_ADDRS27(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID27 (1 << 28)

// patch28
#define CP_SYSRAM_PATCH_PATCH_ADDRS28(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID28 (1 << 28)

// patch29
#define CP_SYSRAM_PATCH_PATCH_ADDRS29(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID29 (1 << 28)

// patch30
#define CP_SYSRAM_PATCH_PATCH_ADDRS30(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID30 (1 << 28)

// patch31
#define CP_SYSRAM_PATCH_PATCH_ADDRS31(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PATCH_VALID31 (1 << 28)

// pagespy0_cfg0
#define CP_SYSRAM_PATCH_PAGESPY_STA_ADDR0(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PAGESPY_DETECTW0 (1 << 28)
#define CP_SYSRAM_PATCH_PAGESPY_DETECTR0 (1 << 29)
#define CP_SYSRAM_PATCH_PAGESPY_ENABLE0 (1 << 30)

// pagespy0_cfg1
#define CP_SYSRAM_PATCH_PAGESPY_END_ADDR0(n) (((n)&0xfffffff) << 0)

// pagespy1_cfg0
#define CP_SYSRAM_PATCH_PAGESPY_STA_ADDR1(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PAGESPY_DETECTW1 (1 << 28)
#define CP_SYSRAM_PATCH_PAGESPY_DETECTR1 (1 << 29)
#define CP_SYSRAM_PATCH_PAGESPY_ENABLE1 (1 << 30)

// pagespy1_cfg1
#define CP_SYSRAM_PATCH_PAGESPY_END_ADDR1(n) (((n)&0xfffffff) << 0)

// pagespy2_cfg0
#define CP_SYSRAM_PATCH_PAGESPY_STA_ADDR2(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PAGESPY_DETECTW2 (1 << 28)
#define CP_SYSRAM_PATCH_PAGESPY_DETECTR2 (1 << 29)
#define CP_SYSRAM_PATCH_PAGESPY_ENABLE2 (1 << 30)

// pagespy2_cfg1
#define CP_SYSRAM_PATCH_PAGESPY_END_ADDR2(n) (((n)&0xfffffff) << 0)

// pagespy3_cfg0
#define CP_SYSRAM_PATCH_PAGESPY_STA_ADDR3(n) (((n)&0xfffffff) << 0)
#define CP_SYSRAM_PATCH_PAGESPY_DETECTW3 (1 << 28)
#define CP_SYSRAM_PATCH_PAGESPY_DETECTR3 (1 << 29)
#define CP_SYSRAM_PATCH_PAGESPY_ENABLE3 (1 << 30)

// pagespy3_cfg1
#define CP_SYSRAM_PATCH_PAGESPY_END_ADDR3(n) (((n)&0xfffffff) << 0)

// pagespy0_sta0
#define CP_SYSRAM_PATCH_PAGESPY_AID0(n) (((n)&0xffff) << 0)
#define CP_SYSRAM_PATCH_PAGESPY_HITW0 (1 << 16)
#define CP_SYSRAM_PATCH_PAGESPY_HITR0 (1 << 17)
#define CP_SYSRAM_PATCH_PAGESPY_STATUS0 (1 << 18)

// pagespy1_sta0
#define CP_SYSRAM_PATCH_PAGESPY_AID1(n) (((n)&0xffff) << 0)
#define CP_SYSRAM_PATCH_PAGESPY_HITW1 (1 << 16)
#define CP_SYSRAM_PATCH_PAGESPY_HITR1 (1 << 17)
#define CP_SYSRAM_PATCH_PAGESPY_STATUS1 (1 << 18)

// pagespy2_sta0
#define CP_SYSRAM_PATCH_PAGESPY_AID2(n) (((n)&0xffff) << 0)
#define CP_SYSRAM_PATCH_PAGESPY_HITW2 (1 << 16)
#define CP_SYSRAM_PATCH_PAGESPY_HITR2 (1 << 17)
#define CP_SYSRAM_PATCH_PAGESPY_STATUS2 (1 << 18)

// pagespy3_sta0
#define CP_SYSRAM_PATCH_PAGESPY_AID3(n) (((n)&0xffff) << 0)
#define CP_SYSRAM_PATCH_PAGESPY_HITW3 (1 << 16)
#define CP_SYSRAM_PATCH_PAGESPY_HITR3 (1 << 17)
#define CP_SYSRAM_PATCH_PAGESPY_STATUS3 (1 << 18)

#endif // _CP_SYSRAM_PATCH_H_