EC600G/components/hal/include/hwregs/8850/rf_txdlpf.h

/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _RF_TXDLPF_H_
#define _RF_TXDLPF_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_RF_TXDLPF_SET_OFFSET (1024)
#define REG_RF_TXDLPF_CLR_OFFSET (2048)

#define REG_RF_TXDLPF_BASE (0x50033000)

typedef volatile struct
{
    uint32_t dlpf_ctrl_reg;                   // 0x00000000
    uint32_t dlpf_dr_reg;                     // 0x00000004
    uint32_t dlpf_afc_pha_offset_reg;         // 0x00000008
    uint32_t dlpf_kdco_pha_offset_reg;        // 0x0000000c
    uint32_t dlpf_gain_kp_afc_reg;            // 0x00000010
    uint32_t dlpf_gain_ki_afc_reg;            // 0x00000014
    uint32_t dlpf_gain_kp_2m_reg;             // 0x00000018
    uint32_t dlpf_gain_ki_2m_reg;             // 0x0000001c
    uint32_t dlpf_gain_kp_200k_reg;           // 0x00000020
    uint32_t dlpf_gain_ki_200k_reg;           // 0x00000024
    uint32_t dlpf_iir0_gain0_reg;             // 0x00000028
    uint32_t dlpf_iir0_gain1_reg;             // 0x0000002c
    uint32_t dlpf_iir1_gain0_reg;             // 0x00000030
    uint32_t dlpf_iir1_gain1_reg;             // 0x00000034
    uint32_t dlpf_iir_gain_msb_reg;           // 0x00000038
    uint32_t dlpf_diff_sel_reg;               // 0x0000003c
    uint32_t dlpf_afc_diff_thr_lsb_reg;       // 0x00000040
    uint32_t dlpf_afc_diff_thr_msb_reg;       // 0x00000044
    uint32_t dlpf_afc_cnt_thr_reg;            // 0x00000048
    uint32_t dlpf_lock_2m_diff_thr_lsb_reg;   // 0x0000004c
    uint32_t dlpf_lock_2m_diff_thr_msb_reg;   // 0x00000050
    uint32_t dlpf_lock_2m_cnt_thr_reg;        // 0x00000054
    uint32_t dlpf_lock_200k_diff_thr_lsb_reg; // 0x00000058
    uint32_t dlpf_lock_200k_diff_thr_msb_reg; // 0x0000005c
    uint32_t dlpf_lock_200k_cnt_thr_reg;      // 0x00000060
    uint32_t dlpf_timer0_cnt_lsb_reg;         // 0x00000064
    uint32_t dlpf_timer0_cnt_msb_reg;         // 0x00000068
    uint32_t dlpf_timer1_cnt_lsb_reg;         // 0x0000006c
    uint32_t dlpf_timer1_cnt_msb_reg;         // 0x00000070
    uint32_t dlpf_timer2_cnt_lsb_reg;         // 0x00000074
    uint32_t dlpf_timer2_cnt_msb_reg;         // 0x00000078
    uint32_t dlpf_capture_reg;                // 0x0000007c
    uint32_t dlpf_status0_reg;                // 0x00000080
    uint32_t dlpf_status1_reg;                // 0x00000084
    uint32_t dlpf_afc_code_status;            // 0x00000088
    uint32_t dlpf_kdco_code_status;           // 0x0000008c
    uint32_t dlpf_tdc_code_reg;               // 0x00000090
    uint32_t dlpf_sum0_l_reg;                 // 0x00000094
    uint32_t dlpf_sum0_m_reg;                 // 0x00000098
    uint32_t dlpf_sum0_h_reg;                 // 0x0000009c
    uint32_t dlpf_iir0_data_lsb_reg;          // 0x000000a0
    uint32_t dlpf_iir0_data_msb_reg;          // 0x000000a4
    uint32_t dlpf_iir1_data_lsb_reg;          // 0x000000a8
    uint32_t dlpf_iir1_data_msb_reg;          // 0x000000ac
    uint32_t dlpf_ctrl_bit_reg;               // 0x000000b0
    uint32_t gro_phase_tdc_cal;               // 0x000000b4
    uint32_t __184[210];                      // 0x000000b8
    uint32_t dlpf_ctrl_reg_set;               // 0x00000400
    uint32_t __1028[43];                      // 0x00000404
    uint32_t dlpf_ctrl_bit_reg_set;           // 0x000004b0
    uint32_t __1204[211];                     // 0x000004b4
    uint32_t dlpf_ctrl_reg_clr;               // 0x00000800
    uint32_t __2052[43];                      // 0x00000804
    uint32_t dlpf_ctrl_bit_reg_clr;           // 0x000008b0
} HWP_RF_TXDLPF_T;

#define hwp_rfTxdlpf ((HWP_RF_TXDLPF_T *)REG_ACCESS_ADDRESS(REG_RF_TXDLPF_BASE))

// dlpf_ctrl_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __0_0 : 1;                // [0]
        uint32_t dlpf_en : 1;              // [1]
        uint32_t dlpf_lock_mode : 1;       // [2]
        uint32_t dlpf_clk_inv0_reg : 1;    // [3]
        uint32_t dlpf_clk_inv1_reg : 1;    // [4]
        uint32_t dlpf_notch_bypass : 1;    // [5]
        uint32_t dlpf_mdll_num : 3;        // [8:6]
        uint32_t pha_dout_clk_inv : 1;     // [9]
        uint32_t tdc_dout_clk_inv : 1;     // [10]
        uint32_t pha_err_clk_inv : 1;      // [11]
        uint32_t tdc_cal_clk_inv : 1;      // [12]
        uint32_t notch_en_sel_status2 : 1; // [13]
        uint32_t sdm_bypass : 1;           // [14]
        uint32_t notch_en_sel_status3 : 1; // [15]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_CTRL_REG_T;

// dlpf_dr_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_dr_value : 14; // [13:0]
        uint32_t dlpf_dr_mode : 1;   // [14]
        uint32_t __31_15 : 17;       // [31:15]
    } b;
} REG_RF_TXDLPF_DLPF_DR_REG_T;

// dlpf_afc_pha_offset_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_afc_pha_offset : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_AFC_PHA_OFFSET_REG_T;

// dlpf_kdco_pha_offset_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_kdco_pha_offset : 16; // [15:0]
        uint32_t __31_16 : 16;              // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_KDCO_PHA_OFFSET_REG_T;

// dlpf_gain_kp_afc_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_gain_kp_afc : 13; // [12:0]
        uint32_t __31_13 : 19;          // [31:13]
    } b;
} REG_RF_TXDLPF_DLPF_GAIN_KP_AFC_REG_T;

// dlpf_gain_ki_afc_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_gain_ki_afc : 16; // [15:0]
        uint32_t __31_16 : 16;          // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_GAIN_KI_AFC_REG_T;

// dlpf_gain_kp_2m_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_gain_kp_2m : 13; // [12:0]
        uint32_t __31_13 : 19;         // [31:13]
    } b;
} REG_RF_TXDLPF_DLPF_GAIN_KP_2M_REG_T;

// dlpf_gain_ki_2m_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_gain_ki_2m : 16; // [15:0]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_GAIN_KI_2M_REG_T;

// dlpf_gain_kp_200k_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_gain_kp_200k : 13; // [12:0]
        uint32_t __31_13 : 19;           // [31:13]
    } b;
} REG_RF_TXDLPF_DLPF_GAIN_KP_200K_REG_T;

// dlpf_gain_ki_200k_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_gain_ki_200k : 16; // [15:0]
        uint32_t __31_16 : 16;           // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_GAIN_KI_200K_REG_T;

// dlpf_iir0_gain0_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_iir0_gain0 : 16; // [15:0]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_IIR0_GAIN0_REG_T;

// dlpf_iir0_gain1_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_iir0_gain1 : 16; // [15:0]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_IIR0_GAIN1_REG_T;

// dlpf_iir1_gain0_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_iir1_gain0 : 16; // [15:0]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_IIR1_GAIN0_REG_T;

// dlpf_iir1_gain1_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_iir1_gain1 : 16; // [15:0]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_IIR1_GAIN1_REG_T;

// dlpf_iir_gain_msb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_iir0_gain0_msb : 1; // [0]
        uint32_t dlpf_iir0_gain1_msb : 1; // [1]
        uint32_t dlpf_iir1_gain0_msb : 1; // [2]
        uint32_t dlpf_iir1_gain1_msb : 1; // [3]
        uint32_t __31_4 : 28;             // [31:4]
    } b;
} REG_RF_TXDLPF_DLPF_IIR_GAIN_MSB_REG_T;

// dlpf_diff_sel_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_diff_sel : 3; // [2:0]
        uint32_t __31_3 : 29;       // [31:3]
    } b;
} REG_RF_TXDLPF_DLPF_DIFF_SEL_REG_T;

// dlpf_afc_diff_thr_lsb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_afc_diff_thr_lsb : 16; // [15:0]
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_AFC_DIFF_THR_LSB_REG_T;

// dlpf_afc_diff_thr_msb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_afc_diff_thr_msb : 16; // [15:0]
        uint32_t __31_16 : 16;               // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_AFC_DIFF_THR_MSB_REG_T;

// dlpf_afc_cnt_thr_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_afc_cnt_thr : 16; // [15:0]
        uint32_t __31_16 : 16;          // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_AFC_CNT_THR_REG_T;

// dlpf_lock_2m_diff_thr_lsb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_lock_2m_diff_thr_lsb : 16; // [15:0]
        uint32_t __31_16 : 16;                   // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_LOCK_2M_DIFF_THR_LSB_REG_T;

// dlpf_lock_2m_diff_thr_msb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_lock_2m_diff_thr_msb : 16; // [15:0]
        uint32_t __31_16 : 16;                   // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_LOCK_2M_DIFF_THR_MSB_REG_T;

// dlpf_lock_2m_cnt_thr_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_lock_2m_cnt_thr : 16; // [15:0]
        uint32_t __31_16 : 16;              // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_LOCK_2M_CNT_THR_REG_T;

// dlpf_lock_200k_diff_thr_lsb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_lock_200k_diff_thr_lsb : 16; // [15:0]
        uint32_t __31_16 : 16;                     // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_LOCK_200K_DIFF_THR_LSB_REG_T;

// dlpf_lock_200k_diff_thr_msb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_lock_200k_diff_thr_msb : 16; // [15:0]
        uint32_t __31_16 : 16;                     // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_LOCK_200K_DIFF_THR_MSB_REG_T;

// dlpf_lock_200k_cnt_thr_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_lock_200k_cnt_thr : 16; // [15:0]
        uint32_t __31_16 : 16;                // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_LOCK_200K_CNT_THR_REG_T;

// dlpf_timer0_cnt_lsb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_timer0_cnt_lsb : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_TIMER0_CNT_LSB_REG_T;

// dlpf_timer0_cnt_msb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_timer0_cnt_msb : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_TIMER0_CNT_MSB_REG_T;

// dlpf_timer1_cnt_lsb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_timer1_cnt_lsb : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_TIMER1_CNT_LSB_REG_T;

// dlpf_timer1_cnt_msb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_timer1_cnt_msb : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_TIMER1_CNT_MSB_REG_T;

// dlpf_timer2_cnt_lsb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_timer2_cnt_lsb : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_TIMER2_CNT_LSB_REG_T;

// dlpf_timer2_cnt_msb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_timer2_cnt_msb : 16; // [15:0]
        uint32_t __31_16 : 16;             // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_TIMER2_CNT_MSB_REG_T;

// dlpf_capture_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_capture_en : 1; // [0]
        uint32_t __31_1 : 31;         // [31:1]
    } b;
} REG_RF_TXDLPF_DLPF_CAPTURE_REG_T;

// dlpf_status0_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_det_status : 2; // [1:0], read only
        uint32_t dlpf_afc_code : 11;  // [12:2], read only
        uint32_t __31_13 : 19;        // [31:13]
    } b;
} REG_RF_TXDLPF_DLPF_STATUS0_REG_T;

// dlpf_status1_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_kdco_code : 14; // [13:0], read only
        uint32_t __31_14 : 18;        // [31:14]
    } b;
} REG_RF_TXDLPF_DLPF_STATUS1_REG_T;

// dlpf_afc_code_status
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_afc_code_reg : 11; // [10:0], read only
        uint32_t __31_11 : 21;           // [31:11]
    } b;
} REG_RF_TXDLPF_DLPF_AFC_CODE_STATUS_T;

// dlpf_kdco_code_status
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_kdco_code_reg : 14; // [13:0], read only
        uint32_t __31_14 : 18;            // [31:14]
    } b;
} REG_RF_TXDLPF_DLPF_KDCO_CODE_STATUS_T;

// dlpf_tdc_code_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_tdc_code : 16; // [15:0], read only
        uint32_t __31_16 : 16;       // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_TDC_CODE_REG_T;

// dlpf_sum0_l_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_sum0_l : 16; // [15:0], read only
        uint32_t __31_16 : 16;     // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_SUM0_L_REG_T;

// dlpf_sum0_m_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_sum0_m : 16; // [15:0], read only
        uint32_t __31_16 : 16;     // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_SUM0_M_REG_T;

// dlpf_sum0_h_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_sum0_h : 7; // [6:0], read only
        uint32_t __31_7 : 25;     // [31:7]
    } b;
} REG_RF_TXDLPF_DLPF_SUM0_H_REG_T;

// dlpf_iir0_data_lsb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_iir0_data_lsb : 16; // [15:0], read only
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_IIR0_DATA_LSB_REG_T;

// dlpf_iir0_data_msb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_iir0_data_msb : 16; // [15:0], read only
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_IIR0_DATA_MSB_REG_T;

// dlpf_iir1_data_lsb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_iir1_data_lsb : 16; // [15:0], read only
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_IIR1_DATA_LSB_REG_T;

// dlpf_iir1_data_msb_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlpf_iir1_data_msb : 16; // [15:0], read only
        uint32_t __31_16 : 16;            // [31:16]
    } b;
} REG_RF_TXDLPF_DLPF_IIR1_DATA_MSB_REG_T;

// dlpf_ctrl_bit_reg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t iir0_bypass : 1;          // [0]
        uint32_t iir1_bypass : 1;          // [1]
        uint32_t afc_bypass : 1;           // [2]
        uint32_t 2m_lock_bypass : 1;       // [3]
        uint32_t kdco_agc_mode : 1;        // [4]
        uint32_t kdco_polar_sel : 1;       // [5]
        uint32_t sel_clk_out1_inv : 1;     // [6]
        uint32_t sel_clk_out2_inv : 1;     // [7]
        uint32_t capture_data_sel_tdc : 1; // [8]
        uint32_t __31_9 : 23;              // [31:9]
    } b;
} REG_RF_TXDLPF_DLPF_CTRL_BIT_REG_T;

// gro_phase_tdc_cal
typedef union {
    uint32_t v;
    struct
    {
        uint32_t phase_tdc_cal : 16; // [15:0], read only
        uint32_t __31_16 : 16;       // [31:16]
    } b;
} REG_RF_TXDLPF_GRO_PHASE_TDC_CAL_T;

// dlpf_ctrl_reg
#define RF_TXDLPF_DLPF_EN (1 << 1)
#define RF_TXDLPF_DLPF_LOCK_MODE (1 << 2)
#define RF_TXDLPF_DLPF_CLK_INV0_REG (1 << 3)
#define RF_TXDLPF_DLPF_CLK_INV1_REG (1 << 4)
#define RF_TXDLPF_DLPF_NOTCH_BYPASS (1 << 5)
#define RF_TXDLPF_DLPF_MDLL_NUM(n) (((n)&0x7) << 6)
#define RF_TXDLPF_PHA_DOUT_CLK_INV (1 << 9)
#define RF_TXDLPF_TDC_DOUT_CLK_INV (1 << 10)
#define RF_TXDLPF_PHA_ERR_CLK_INV (1 << 11)
#define RF_TXDLPF_TDC_CAL_CLK_INV (1 << 12)
#define RF_TXDLPF_NOTCH_EN_SEL_STATUS2 (1 << 13)
#define RF_TXDLPF_SDM_BYPASS (1 << 14)
#define RF_TXDLPF_NOTCH_EN_SEL_STATUS3 (1 << 15)

// dlpf_dr_reg
#define RF_TXDLPF_DLPF_DR_VALUE(n) (((n)&0x3fff) << 0)
#define RF_TXDLPF_DLPF_DR_MODE (1 << 14)

// dlpf_afc_pha_offset_reg
#define RF_TXDLPF_DLPF_AFC_PHA_OFFSET(n) (((n)&0xffff) << 0)

// dlpf_kdco_pha_offset_reg
#define RF_TXDLPF_DLPF_KDCO_PHA_OFFSET(n) (((n)&0xffff) << 0)

// dlpf_gain_kp_afc_reg
#define RF_TXDLPF_DLPF_GAIN_KP_AFC(n) (((n)&0x1fff) << 0)

// dlpf_gain_ki_afc_reg
#define RF_TXDLPF_DLPF_GAIN_KI_AFC(n) (((n)&0xffff) << 0)

// dlpf_gain_kp_2m_reg
#define RF_TXDLPF_DLPF_GAIN_KP_2M(n) (((n)&0x1fff) << 0)

// dlpf_gain_ki_2m_reg
#define RF_TXDLPF_DLPF_GAIN_KI_2M(n) (((n)&0xffff) << 0)

// dlpf_gain_kp_200k_reg
#define RF_TXDLPF_DLPF_GAIN_KP_200K(n) (((n)&0x1fff) << 0)

// dlpf_gain_ki_200k_reg
#define RF_TXDLPF_DLPF_GAIN_KI_200K(n) (((n)&0xffff) << 0)

// dlpf_iir0_gain0_reg
#define RF_TXDLPF_DLPF_IIR0_GAIN0(n) (((n)&0xffff) << 0)

// dlpf_iir0_gain1_reg
#define RF_TXDLPF_DLPF_IIR0_GAIN1(n) (((n)&0xffff) << 0)

// dlpf_iir1_gain0_reg
#define RF_TXDLPF_DLPF_IIR1_GAIN0(n) (((n)&0xffff) << 0)

// dlpf_iir1_gain1_reg
#define RF_TXDLPF_DLPF_IIR1_GAIN1(n) (((n)&0xffff) << 0)

// dlpf_iir_gain_msb_reg
#define RF_TXDLPF_DLPF_IIR0_GAIN0_MSB (1 << 0)
#define RF_TXDLPF_DLPF_IIR0_GAIN1_MSB (1 << 1)
#define RF_TXDLPF_DLPF_IIR1_GAIN0_MSB (1 << 2)
#define RF_TXDLPF_DLPF_IIR1_GAIN1_MSB (1 << 3)

// dlpf_diff_sel_reg
#define RF_TXDLPF_DLPF_DIFF_SEL(n) (((n)&0x7) << 0)

// dlpf_afc_diff_thr_lsb_reg
#define RF_TXDLPF_DLPF_AFC_DIFF_THR_LSB(n) (((n)&0xffff) << 0)

// dlpf_afc_diff_thr_msb_reg
#define RF_TXDLPF_DLPF_AFC_DIFF_THR_MSB(n) (((n)&0xffff) << 0)

// dlpf_afc_cnt_thr_reg
#define RF_TXDLPF_DLPF_AFC_CNT_THR(n) (((n)&0xffff) << 0)

// dlpf_lock_2m_diff_thr_lsb_reg
#define RF_TXDLPF_DLPF_LOCK_2M_DIFF_THR_LSB(n) (((n)&0xffff) << 0)

// dlpf_lock_2m_diff_thr_msb_reg
#define RF_TXDLPF_DLPF_LOCK_2M_DIFF_THR_MSB(n) (((n)&0xffff) << 0)

// dlpf_lock_2m_cnt_thr_reg
#define RF_TXDLPF_DLPF_LOCK_2M_CNT_THR(n) (((n)&0xffff) << 0)

// dlpf_lock_200k_diff_thr_lsb_reg
#define RF_TXDLPF_DLPF_LOCK_200K_DIFF_THR_LSB(n) (((n)&0xffff) << 0)

// dlpf_lock_200k_diff_thr_msb_reg
#define RF_TXDLPF_DLPF_LOCK_200K_DIFF_THR_MSB(n) (((n)&0xffff) << 0)

// dlpf_lock_200k_cnt_thr_reg
#define RF_TXDLPF_DLPF_LOCK_200K_CNT_THR(n) (((n)&0xffff) << 0)

// dlpf_timer0_cnt_lsb_reg
#define RF_TXDLPF_DLPF_TIMER0_CNT_LSB(n) (((n)&0xffff) << 0)

// dlpf_timer0_cnt_msb_reg
#define RF_TXDLPF_DLPF_TIMER0_CNT_MSB(n) (((n)&0xffff) << 0)

// dlpf_timer1_cnt_lsb_reg
#define RF_TXDLPF_DLPF_TIMER1_CNT_LSB(n) (((n)&0xffff) << 0)

// dlpf_timer1_cnt_msb_reg
#define RF_TXDLPF_DLPF_TIMER1_CNT_MSB(n) (((n)&0xffff) << 0)

// dlpf_timer2_cnt_lsb_reg
#define RF_TXDLPF_DLPF_TIMER2_CNT_LSB(n) (((n)&0xffff) << 0)

// dlpf_timer2_cnt_msb_reg
#define RF_TXDLPF_DLPF_TIMER2_CNT_MSB(n) (((n)&0xffff) << 0)

// dlpf_capture_reg
#define RF_TXDLPF_DLPF_CAPTURE_EN (1 << 0)

// dlpf_status0_reg
#define RF_TXDLPF_DLPF_DET_STATUS(n) (((n)&0x3) << 0)
#define RF_TXDLPF_DLPF_AFC_CODE(n) (((n)&0x7ff) << 2)

// dlpf_status1_reg
#define RF_TXDLPF_DLPF_KDCO_CODE(n) (((n)&0x3fff) << 0)

// dlpf_afc_code_status
#define RF_TXDLPF_DLPF_AFC_CODE_REG(n) (((n)&0x7ff) << 0)

// dlpf_kdco_code_status
#define RF_TXDLPF_DLPF_KDCO_CODE_REG(n) (((n)&0x3fff) << 0)

// dlpf_tdc_code_reg
#define RF_TXDLPF_DLPF_TDC_CODE(n) (((n)&0xffff) << 0)

// dlpf_sum0_l_reg
#define RF_TXDLPF_DLPF_SUM0_L(n) (((n)&0xffff) << 0)

// dlpf_sum0_m_reg
#define RF_TXDLPF_DLPF_SUM0_M(n) (((n)&0xffff) << 0)

// dlpf_sum0_h_reg
#define RF_TXDLPF_DLPF_SUM0_H(n) (((n)&0x7f) << 0)

// dlpf_iir0_data_lsb_reg
#define RF_TXDLPF_DLPF_IIR0_DATA_LSB(n) (((n)&0xffff) << 0)

// dlpf_iir0_data_msb_reg
#define RF_TXDLPF_DLPF_IIR0_DATA_MSB(n) (((n)&0xffff) << 0)

// dlpf_iir1_data_lsb_reg
#define RF_TXDLPF_DLPF_IIR1_DATA_LSB(n) (((n)&0xffff) << 0)

// dlpf_iir1_data_msb_reg
#define RF_TXDLPF_DLPF_IIR1_DATA_MSB(n) (((n)&0xffff) << 0)

// dlpf_ctrl_bit_reg
#define RF_TXDLPF_IIR0_BYPASS (1 << 0)
#define RF_TXDLPF_IIR1_BYPASS (1 << 1)
#define RF_TXDLPF_AFC_BYPASS (1 << 2)
#define RF_TXDLPF_2M_LOCK_BYPASS (1 << 3)
#define RF_TXDLPF_KDCO_AGC_MODE (1 << 4)
#define RF_TXDLPF_KDCO_POLAR_SEL (1 << 5)
#define RF_TXDLPF_SEL_CLK_OUT1_INV (1 << 6)
#define RF_TXDLPF_SEL_CLK_OUT2_INV (1 << 7)
#define RF_TXDLPF_CAPTURE_DATA_SEL_TDC (1 << 8)

// gro_phase_tdc_cal
#define RF_TXDLPF_PHASE_TDC_CAL(n) (((n)&0xffff) << 0)

#endif // _RF_TXDLPF_H_