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EC600G
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ql-kernel
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drivers
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quec_pin_cfg_EC600G.c

quec_pin_cfg_EC600G.c 14 KB
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  1. 

  2. /*================================================================
    3. 

  3.   Copyright (c) 2021, Quectel Wireless Solutions Co., Ltd. All rights reserved.
    4. 

  4.   Quectel Wireless Solutions Proprietary and Confidential.
    5. 

  5. =================================================================*/
    6. 

  6.     
    7. 

  7. /*=================================================================
    8. 

  8. 

  9. 						EDIT HISTORY FOR MODULE
    10. 

  10. 

  11. This section contains comments describing changes made to the module.
    12. 

  12. Notice that changes are listed in reverse chronological order.
    13. 

  13. 

  14. WHEN			  WHO		  WHAT, WHERE, WHY
    15. 

  15. ------------	 -------	 -------------------------------------------------------------------------------
    16. 

  16. 

  17. =================================================================*/
    18. 

  18. 

  19. 

  20. /*===========================================================================
    21. 

  21.  * include files
    22. 

  22.  ===========================================================================*/
    23. 

  23. #include "quec_pin_cfg.h"
    24. 

  24. 

  25. #include "hwregs.h"
    26. 

  26. 

  27. /*===========================================================================
    28. 

  28.  * GPIO Map
    29. 

  29.  ===========================================================================*/
    30. 

  30. #ifdef CONFIG_QL_OPEN_EXPORT_PKG /* Open */
    31. 

  31. const quec_pin_cfg_t quec_pin_cfg_map[] = /* pin initialize */
    32. 

  32. {              /* pin_num  default_func     gpio_func    gpio_num       gpio_dir         gpio_pull          gpio_lvl              reg                  		  anareg					 drv_bits*/
    33. 

  33. /*NET_MODE     */{  52 ,        0,              0,        GPIO_0,    GPIO_OUTPUT,      QUEC_PIN_NONE,    LVL_LOW,          &hwp_iomux->gpio_0,          &hwp_iomux->pad_gpio_0,              4},
    34. 

  34. /*SLEEP_IND    */{  53 ,        0,              0,        GPIO_1,    GPIO_OUTPUT,      QUEC_PIN_NONE,    LVL_LOW,          &hwp_iomux->gpio_1,          &hwp_iomux->pad_gpio_1,              4},
    35. 

  35. /*NET_STATUS   */{  54 ,        5,              0,        GPIO_2,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->gpio_2,          &hwp_iomux->pad_gpio_2,              4},//pwm function
    36. 

  36. /*W_DISABLE#   */{  51 ,        0,              0,        GPIO_3,    GPIO_INPUT,       PULL_DOWN,        QUEC_PIN_NONE,    &hwp_iomux->gpio_3,          &hwp_iomux->pad_gpio_3,              4},
    37. 

  37. /*USIM1_DET    */{  9  ,        0,              0,        GPIO_6,    GPIO_INPUT,       PULL_DOWN,        QUEC_PIN_NONE,    &hwp_iomux->gpio_6,          &hwp_iomux->pad_gpio_6,              4},
    38. 

  38. /*PSM_EXT_INT  */{  116,        0,              0,        GPIO_7,    GPIO_INPUT,       PULL_DOWN,        QUEC_PIN_NONE,    &hwp_iomux->gpio_7,          &hwp_iomux->pad_gpio_7,              4},
    39. 

  39. /*KEYIN4       */{  126,        0,              1,        GPIO_8,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyin_4,         &hwp_iomux->pad_keyin_4,             4},
    40. 

  40. /*KEYIN5       */{  125,        0,              1,        GPIO_9,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyin_5,         &hwp_iomux->pad_keyin_5,             4},
    41. 

  41. /*KEYOUT4      */{  104,        0,              1,        GPIO_10,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyout_4,        &hwp_iomux->pad_keyout_4,            4},
    42. 

  42. /*KEYOUT5      */{  103,        0,              1,        GPIO_11,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyout_5,        &hwp_iomux->pad_keyout_5,            4},
    43. 

  43. /*MAIN_RXD     */{  31 ,        0,              1,        GPIO_12,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_1_rxd,      &hwp_iomux->pad_uart_1_rxd,          4},
    44. 

  44. /*MAIN_TXD     */{  32 ,        0,              1,        GPIO_13,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_1_txd,      &hwp_iomux->pad_uart_1_txd,          4},
    45. 

  45. /*MAIN_RTS     */{  34 ,        0,              1,        GPIO_14,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_1_cts,      &hwp_iomux->pad_uart_1_cts,          4},
    46. 

  46. /*MAIN_CTS     */{  33 ,        0,              4,        GPIO_15,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_1_rts,      &hwp_iomux->pad_uart_1_rts,          4},
    47. 

  47. /*SDIO1_CLK    */{  132,        0,              1,        GPIO_16,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sdmmc1_clk,      &hwp_iomux->pad_sdmmc1_clk,          4},
    48. 

  48. /*MAIN_DCD     */{  48 ,        1,              1,        GPIO_17,   GPIO_INPUT,       PULL_UP,          QUEC_PIN_NONE,    &hwp_iomux->sdmmc1_cmd,      &hwp_iomux->pad_sdmmc1_cmd,          4},
    49. 

  49. /*MAIN_DTR     */{  39 ,        1,              1,        GPIO_18,   GPIO_INPUT,       PULL_UP,          QUEC_PIN_NONE,    &hwp_iomux->sdmmc1_data_0,   &hwp_iomux->pad_sdmmc1_data_0,       4},
    50. 

  50. /*CAM_SPI_CLK  */{  13 ,        0,              2,        GPIO_18,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_camera_sck,  &hwp_iomux->pad_spi_camera_sck,      2},
    51. 

  51. /*MAIN_RI      */{  40 ,        1,              1,        GPIO_19,   GPIO_INPUT,       PULL_UP,          QUEC_PIN_NONE,    &hwp_iomux->sdmmc1_data_1,   &hwp_iomux->pad_sdmmc1_data_1,       4},
    52. 

  52. /*PCM_CLK      */{  61 ,        0,              2,        GPIO_19,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->i2s1_bck,        &hwp_iomux->pad_i2s1_bck,            2},
    53. 

  53. /*PCM_SYNC     */{  58 ,        0,              2,        GPIO_20,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->i2s1_lrck,       &hwp_iomux->pad_i2s1_lrck,           2},
    54. 

  54. /*WAKEUP_IN    */{  49 ,        1,              1,        GPIO_20,   GPIO_INPUT,       PULL_UP,          QUEC_PIN_NONE,    &hwp_iomux->sdmmc1_data_2,   &hwp_iomux->pad_sdmmc1_data_2,       4},
    55. 

  55. /*AP_READY     */{  50 ,        1,              1,        GPIO_21,   GPIO_INPUT,       PULL_UP,          QUEC_PIN_NONE,    &hwp_iomux->sdmmc1_data_3,   &hwp_iomux->pad_sdmmc1_data_3,       4},
    56. 

  56. /*PCM_DIN      */{  59 ,        0,              2,        GPIO_21,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->i2s_sdat_i,      &hwp_iomux->pad_i2s_sdat_i,          2},
    57. 

  57. /*PCM_DOUT     */{  60 ,        0,              2,        GPIO_22,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->i2s1_sdat_o,     &hwp_iomux->pad_i2s1_sdat_o,         2},
    58. 

  58. /*SPI_CLK      */{  1  ,        3,              1,        GPIO_24,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sw_clk,          &hwp_iomux->pad_sw_clk,              2},
    59. 

  59. /*GPIO1        */{  69 ,        1,              1,        GPIO_24,   GPIO_INPUT,       PULL_UP,          QUEC_PIN_NONE,    &hwp_iomux->sdmmc1_data_4,   &hwp_iomux->pad_sdmmc1_data_4,       4},
    60. 

  60. /*SPI_CS       */{  4  ,        3,              1,        GPIO_25,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sw_dio,          &hwp_iomux->pad_sw_dio,              2},
    61. 

  61. /*GPIO2        */{  70 ,        1,              1,        GPIO_25,   GPIO_INPUT,       PULL_UP,          QUEC_PIN_NONE,    &hwp_iomux->sdmmc1_data_5,   &hwp_iomux->pad_sdmmc1_data_5,       4},
    62. 

  62. /*SPI_TXD      */{  3  ,        3,              1,        GPIO_26,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->debug_host_rx,   &hwp_iomux->pad_debug_host_rx,       2},
    63. 

  63. /*SPI_RXD      */{  2  ,        3,              1,        GPIO_27,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->debug_host_tx,   &hwp_iomux->pad_debug_host_tx,       2},
    64. 

  64. /*CAM_I2C_SCL  */{  11 ,        0,              1,        GPIO_29,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->i2c_m1_scl,      &hwp_iomux->pad_i2c_m1_scl,          2},
    65. 

  65. /*CAM_I2C_SDA  */{  12 ,        0,              1,        GPIO_30,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->i2c_m1_sda,      &hwp_iomux->pad_i2c_m1_sda,          2},
    66. 

  66. /*USIM2_CLK    */{  147,        0,              1,        GPIO_30,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sim_1_clk,       &hwp_iomux->pad_sim_1_clk,           4},
    67. 

  67. /*USIM2_DATA   */{  146,        0,              1,        GPIO_31,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sim_1_dio,       &hwp_iomux->pad_sim_1_dio,           4},
    68. 

  68. /*USIM2_RST    */{  145,        0,              1,        GPIO_32,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sim_1_rst,       &hwp_iomux->pad_sim_1_rst,           4},
    69. 

  69. /*UART2_RXD    */{  123,        0,              3,        GPIO_31,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_2_rxd,      &hwp_iomux->pad_uart_2_rxd,          2},
    70. 

  70. /*KEYIN3       */{  127,        0,              1,        GPIO_31,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyin_3,         &hwp_iomux->pad_keyin_3,             4},
    71. 

  71. /*UART2_TXD    */{  124,        0,              3,        GPIO_32,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_2_txd,      &hwp_iomux->pad_uart_2_txd,          2},
    72. 

  72. /*KEYOUT0      */{  105,        0,              1,        GPIO_32,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyout_0,        &hwp_iomux->pad_keyout_0,            4},
    73. 

  73. /*DBG_RXD      */{  72 ,        4,              1,        GPIO_33,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_2_cts,      &hwp_iomux->pad_uart_2_cts,          2},
    74. 

  74. /*KEYOUT1      */{  106,        0,              1,        GPIO_33,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyout_1,        &hwp_iomux->pad_keyout_1,            4},
    75. 

  75. /*DBG_TXD      */{  71 ,        4,              1,        GPIO_34,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_2_rts,      &hwp_iomux->pad_uart_2_rts,          2},
    76. 

  76. /*KEYOUT2      */{  107,        0,              1,        GPIO_34,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyout_2,        &hwp_iomux->pad_keyout_2,            4},
    77. 

  77. /*LCD_SPI_DOUT */{  66 ,        0,              2,        GPIO_35,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_lcd_sio,     &hwp_iomux->pad_spi_lcd_sio,         4},
    78. 

  78. /*KEYOUT3      */{  108,        0,              1,        GPIO_35,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyout_3,        &hwp_iomux->pad_keyout_3,            4},
    79. 

  79. /*LCD_SPI_RS   */{  63 ,        0,              2,        GPIO_36,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_lcd_sdc,     &hwp_iomux->pad_spi_lcd_sdc,         4},
    80. 

  80. /*LCD_SPI_CLK  */{  67 ,        0,              2,        GPIO_37,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_lcd_clk,     &hwp_iomux->pad_spi_lcd_clk,         4},
    81. 

  81. /*LCD_SPI_CS   */{  65 ,        0,              2,        GPIO_38,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_lcd_cs,      &hwp_iomux->pad_spi_lcd_cs,          4},
    82. 

  82. /*LCD_SEL      */{  137,        0,              2,        GPIO_39,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_lcd_select,  &hwp_iomux->pad_spi_lcd_select,      4},
    83. 

  83. /*LCD_TE       */{  62 ,        0,              2,        GPIO_40,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->lcd_fmark,       &hwp_iomux->pad_lcd_fmark,           4},
    84. 

  84. /*LCD_RST      */{  64 ,        0,              2,        GPIO_41,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->lcd_rstb,        &hwp_iomux->pad_lcd_rstb,            4},
    85. 

  85. /*I2C_SCL      */{  57 ,        0,              2,        GPIO_42,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->i2c_m2_scl,      &hwp_iomux->pad_i2c_m2_scl,          2},
    86. 

  86. /*I2C_SDA      */{  56 ,        0,              2,        GPIO_43,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->i2c_m2_sda,      &hwp_iomux->pad_i2c_m2_sda,          2},
    87. 

  87. /*CAM__RST     */{  120,        0,              3,        GPIO_44,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->camera_rst_l,    &hwp_iomux->pad_camera_rst_l,        2},
    88. 

  88. /*CAM_PWDN     */{  16 ,        0,              3,        GPIO_45,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->camera_pwdn,     &hwp_iomux->pad_camera_pwdn,         2},
    89. 

  89. /*CAM_MCLK     */{  10 ,        0,              2,        GPIO_46,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->camera_ref_clk,  &hwp_iomux->pad_camera_ref_clk,      2},
    90. 

  90. /*CAM_SPI_DATA0*/{  14 ,        0,              3,        GPIO_47,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_camera_si_0, &hwp_iomux->pad_spi_camera_si_0,     2},
    91. 

  91. 

  92. //pinmux(not gpio part)
    93. 

  93. /*USB_BOOT     */{  55 ,        0,  QUEC_PIN_NONE,  QUEC_PIN_NONE,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyin_0,         &hwp_iomux->pad_keyin_0,             0},
    94. 

  94. /*CAM_SPI_DATA1*/{  15 ,        0,  QUEC_PIN_NONE,  QUEC_PIN_NONE,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_camera_si_1, &hwp_iomux->pad_spi_camera_si_1,     0},
    95. 

  95. /*KEYIN1       */{  129,        0,  QUEC_PIN_NONE,  QUEC_PIN_NONE,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyin_1,         &hwp_iomux->pad_keyin_1,             0},
    96. 

  96. /*KEYIN2       */{  128,        0,  QUEC_PIN_NONE,  QUEC_PIN_NONE,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyin_2,         &hwp_iomux->pad_keyin_2,             0},
    97. 

  97. 

  98. //               should before here!
    99. 

  99.                  {QUEC_PIN_NONE,-1,            -1,             -1,              -1,               -1,                      -1},
    100. 

  100. };
    101. 

  101. 

  102. #ifdef CONFIG_QUEC_PROJECT_FEATURE_PSM
    103. 

  103. const quec_psm_pin_cfg_t quec_psm_pin_cfg[] = 
    104. 

  104. {
    105. 

  105.     {GPIO_0,  LVL_HIGH, 0},
    106. 

  106.     {GPIO_1,  LVL_HIGH, 0},
    107. 

  107.     {GPIO_2,  LVL_HIGH, 0},
    108. 

  108.     {GPIO_3,  LVL_HIGH, 0},
    109. 

  109.     {GPIO_4,  LVL_HIGH, 0},
    110. 

  110.     {GPIO_5,  LVL_HIGH, 0},
    111. 

  111.     {GPIO_6,  LVL_HIGH, 0},
    112. 

  112.     {GPIO_7,  LVL_HIGH, 0},
    113. 

  113.     {GPIO_MAX,LVL_HIGH, 0},
    114. 

  114. };
    115. 

  115. #endif
    116. 

  116. 

  117. #endif/* CONFIG_QL_OPEN_EXPORT_PKG */
    118. 

  118.