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EC600G
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components
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ql-kernel
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drivers
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quec_pin_cfg_EG800G.c

quec_pin_cfg_EG800G.c 12 KB
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  1. 
    2. 

  2. /*================================================================
    3. 

  3.   Copyright (c) 2021, Quectel Wireless Solutions Co., Ltd. All rights reserved.
    4. 

  4.   Quectel Wireless Solutions Proprietary and Confidential.
    5. 

  5. =================================================================*/
    6. 

  6.     
    7. 

  7. /*=================================================================
    8. 

  8. 

  9. 						EDIT HISTORY FOR MODULE
    10. 

  10. 

  11. This section contains comments describing changes made to the module.
    12. 

  12. Notice that changes are listed in reverse chronological order.
    13. 

  13. 

  14. WHEN			  WHO		  WHAT, WHERE, WHY
    15. 

  15. ------------	 -------	 -------------------------------------------------------------------------------
    16. 

  16. 

  17. =================================================================*/
    18. 

  18. 

  19. 

  20. /*===========================================================================
    21. 

  21.  * include files
    22. 

  22.  ===========================================================================*/
    23. 

  23. #include "quec_pin_cfg.h"
    24. 

  24. 

  25. #include "hwregs.h"
    26. 

  26. 

  27. /*===========================================================================
    28. 

  28.  * GPIO Map
    29. 

  29.  ===========================================================================*/
    30. 

  30. #ifdef CONFIG_QL_OPEN_EXPORT_PKG /* Open */
    31. 

  31. const quec_pin_cfg_t quec_pin_cfg_map[] = /* pin initialize */
    32. 

  32. {            	/* pin_num  default_func     gpio_func    gpio_num       gpio_dir         gpio_pull          gpio_lvl              reg                  		  anareg				drv_bits*/
    33. 

  33. /*STATUS     	*/{  25 ,        0,              0,        GPIO_0,    GPIO_OUTPUT,       QUEC_PIN_NONE,    LVL_HIGH,         &hwp_iomux->gpio_0,          &hwp_iomux->pad_gpio_0,   		4},
    34. 

  34. /*MAIN_RI    	*/{  20,         0,              0,        GPIO_1,    GPIO_OUTPUT,       QUEC_PIN_NONE,    LVL_HIGH,         &hwp_iomux->gpio_1,          &hwp_iomux->pad_gpio_1,   		4},
    35. 

  35. /*NET_STATUS 	*/{  16 ,		 0,			  	 0,		   GPIO_2,    QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->gpio_2, 		  &hwp_iomux->pad_gpio_2,			4},//pwm function
    36. 

  36. /*MAIN_DCD	 	*/{  21,		 0,			  	 0,		   GPIO_3,    GPIO_OUTPUT,	     QUEC_PIN_NONE,    LVL_HIGH,	     &hwp_iomux->gpio_3,	      &hwp_iomux->pad_gpio_3,   	 	4},
    37. 

  37. /*MAIN_DTR	 	*/{  19 ,		 0,			  	 0,		   GPIO_4,    GPIO_INPUT,	     PULL_UP,          QUEC_PIN_NONE,	 &hwp_iomux->gpio_4, 		  &hwp_iomux->pad_gpio_4,			4},
    38. 

  38. /*AUX_RXD	 	*/{  28,		 4,			  	 0,		   GPIO_6,    QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->gpio_6,	      &hwp_iomux->pad_gpio_6,    		4},
    39. 

  39. /*AUX_TXD	 	*/{  29 ,		 4,			  	 0,		   GPIO_7,    QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->gpio_7, 		  &hwp_iomux->pad_gpio_7,			4},
    40. 

  40. /*KEYIN_4	 	*/{  84,		 0,			  	 1,		   GPIO_8,    QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->keyin_4, 	      &hwp_iomux->pad_keyin_4,			4},
    41. 

  41. /*KEYOUT_4	 	*/{  85 ,		 0,			  	 1,		   GPIO_10,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,	   QUEC_PIN_NONE,	 &hwp_iomux->keyout_4, 		  &hwp_iomux->pad_keyout_4,			4},
    42. 

  42. /*MAIN_RXD	 	*/{  17,		 0,			  	 1,		   GPIO_12,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->uart_1_rxd,      &hwp_iomux->pad_uart_1_rxd, 		4},
    43. 

  43. /*MAIN_TXD   	*/{  18,		 0,			  	 1,		   GPIO_13,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->uart_1_txd, 	  &hwp_iomux->pad_uart_1_txd,		4},
    44. 

  44. /*MAIN_RTS   	*/{  23,		 0,			  	 1,		   GPIO_14,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->uart_1_cts,	  &hwp_iomux->pad_uart_1_cts,    	4},
    45. 

  45. /*MAIN_CTS	 	*/{  22 ,		 0,			  	 4,		   GPIO_15,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->uart_1_rts, 	  &hwp_iomux->pad_uart_1_rts,		4},
    46. 

  46. /*I2C3_SCL   	*/{  68 ,        3,              0,        GPIO_16,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->gpio_16,         &hwp_iomux->pad_gpio_16,          2},
    47. 

  47. /*I2C3_SDA   	*/{  69 ,        3,              0,        GPIO_17,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->gpio_17,         &hwp_iomux->pad_gpio_17,          2},
    48. 

  48. /*SPI_CAM_SCK	*/{  80 ,		 0,			  	 2,		   GPIO_18,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->spi_camera_sck,  &hwp_iomux->pad_spi_camera_sck,	2},
    49. 

  49. /*SPI_FALSH_CLK */{  101,		 1, 			 0, 	   GPIO_18,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->gpio_18,		  &hwp_iomux->pad_gpio_18,			2},
    50. 

  50. /*PCM_CLK		*/{  30 ,		 0, 			 2, 	   GPIO_19,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->i2s1_bck,		  &hwp_iomux->pad_i2s1_bck,			2},
    51. 

  51. /*SPI_FLASH_CS	*/{  79,		 1,			  	 0,		   GPIO_19,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->gpio_19,	      &hwp_iomux->pad_gpio_19,			2},
    52. 

  52. /*PCM_SYNC	 	*/{  31,		 0,			  	 2,		   GPIO_20,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->i2s1_lrck,	      &hwp_iomux->pad_i2s1_lrck,		2},
    53. 

  53. /*SPI_FLASH_SIO0*/{  100 ,		 1,			 	 0,		   GPIO_20,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,	   QUEC_PIN_NONE,	 &hwp_iomux->gpio_20, 		  &hwp_iomux->pad_gpio_20,			2},
    54. 

  54. /*PCM_IN		*/{  32,		 0, 			 2, 	   GPIO_21,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->i2s_sdat_i,	  &hwp_iomux->pad_i2s_sdat_i,		2},
    55. 

  55. /*SPI_FLASH_SIO1*/{  108,		 1,			 	 0,		   GPIO_21,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->gpio_21,         &hwp_iomux->pad_gpio_21, 			2},
    56. 

  56. /*PCM_OUT		*/{  33 ,		 0, 			 2, 	   GPIO_22,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->i2s1_sdat_o,	  &hwp_iomux->pad_i2s1_sdat_o,		2},
    57. 

  57. /*SPI_FLASH_SIO2*/{  109,		 1,			 	 0,		   GPIO_22,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->gpio_22,		  &hwp_iomux->pad_gpio_22,			2},
    58. 

  58. /*SPI_FLASH_SIO3*/{  107,		 1,			 	 0,		   GPIO_23,   QUEC_PIN_NONE,	 QUEC_PIN_NONE,    QUEC_PIN_NONE,	 &hwp_iomux->gpio_23, 	      &hwp_iomux->pad_gpio_23,			2},
    59. 

  59. /*KEYIN_0   	*/{  82 ,        0,              1,        GPIO_28,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyin_0,         &hwp_iomux->pad_keyin_0, 			4},
    60. 

  60. /*KEYIN_1   	*/{  87 ,        0,              1,        GPIO_29,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyin_1,         &hwp_iomux->pad_keyin_1, 			4},
    61. 

  61. #if defined(CONFIG_QUEC_PROJECT_FEATURE_QDSIM) || defined(CONFIG_QUEC_PROJECT_FEATURE_DSSS)
    62. 

  62. /*USIM2_CLK   	*/{  62 ,        0,              1,        GPIO_30,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sim_1_clk,       &hwp_iomux->pad_sim_1_clk, 		4},
    63. 

  63. /*USIM2_DATA   	*/{  64 ,        0,              1,        GPIO_31,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sim_1_dio,       &hwp_iomux->pad_sim_1_dio, 		4},
    64. 

  64. /*USIM2_RST   	*/{  63 ,        0,              1,        GPIO_32,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sim_1_rst,       &hwp_iomux->pad_sim_1_rst, 		4},
    65. 

  65. #else
    66. 

  66. /*USIM2_CLK   	*/{  62 ,        0,              1,        GPIO_30,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sim_1_clk,       &hwp_iomux->pad_sim_1_clk, 		4},
    67. 

  67. /*USIM2_DATA   	*/{  64 ,        0,              1,        GPIO_31,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sim_1_dio,       &hwp_iomux->pad_sim_1_dio, 		4},
    68. 

  68. /*USIM2_RST   	*/{  63 ,        0,              1,        GPIO_32,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->sim_1_rst,       &hwp_iomux->pad_sim_1_rst, 		4},
    69. 

  69. #endif
    70. 

  70. /*KEYIN_2   	*/{  77 ,        0,              1,        GPIO_30,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyin_2,         &hwp_iomux->pad_keyin_2, 			4},
    71. 

  71. /*KEYIN_3   	*/{  75 ,        0,              1,        GPIO_31,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyin_3,         &hwp_iomux->pad_keyin_3, 			4},
    72. 

  72. /*I2C1_SCL   	*/{  57 ,        1,              3,        GPIO_31,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_2_rxd,      &hwp_iomux->pad_uart_2_rxd,       2},
    73. 

  73. /*KEYOUT_0   	*/{  83 ,        0,              1,        GPIO_32,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyout_0,        &hwp_iomux->pad_keyout_0, 		4},
    74. 

  74. /*I2C1_SDA   	*/{  58 ,        1,              3,        GPIO_32,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_2_txd,      &hwp_iomux->pad_uart_2_txd,       2},
    75. 

  75. /*DBG_RXD    	*/{  38 ,        4,              1,        GPIO_33,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_2_cts,      &hwp_iomux->pad_uart_2_cts,       2},
    76. 

  76. /*KEYOUT_1   	*/{  86 ,        0,              1,        GPIO_33,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyout_1,        &hwp_iomux->pad_keyout_1, 		4},
    77. 

  77. /*DBG_TXD    	*/{  39 ,        4,              1,        GPIO_34,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->uart_2_rts,      &hwp_iomux->pad_uart_2_rts,       2},
    78. 

  78. /*KEYOUT_2   	*/{  76 ,        0,              1,        GPIO_34,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyout_2,        &hwp_iomux->pad_keyout_2, 		4},
    79. 

  79. /*SPI_LCD_SIO   */{  50 ,        0,              2,        GPIO_35,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_lcd_sio,     &hwp_iomux->pad_spi_lcd_sio, 		4},
    80. 

  80. /*KEYOUT_3   	*/{  74 ,        0,              1,        GPIO_35,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->keyout_3,        &hwp_iomux->pad_keyout_3, 		4},
    81. 

  81. /*SPI_LCD_SDC   */{  51 ,        0,              2,        GPIO_36,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_lcd_sdc,     &hwp_iomux->pad_spi_lcd_sdc, 		4},
    82. 

  82. /*SPI_LCD_CLK   */{  53 ,        0,              2,        GPIO_37,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_lcd_clk,     &hwp_iomux->pad_spi_lcd_clk, 		4},
    83. 

  83. /*SPI_LCD_CS   	*/{  52 ,        0,              2,        GPIO_38,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_lcd_cs,      &hwp_iomux->pad_spi_lcd_cs, 		4},
    84. 

  84. /*LCD_FMARK   	*/{  78 ,        0,              2,        GPIO_40,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->lcd_fmark,       &hwp_iomux->pad_lcd_fmark, 		4},
    85. 

  85. /*LCD_RSTB   	*/{  49 ,        0,              2,        GPIO_41,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->lcd_rstb,        &hwp_iomux->pad_lcd_rstb, 		4},
    86. 

  86. 

  87. /*I2C_SCL    	*/{  67 ,        0,              2,        GPIO_42,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->i2c_m2_scl,      &hwp_iomux->pad_i2c_m2_scl, 		2},
    88. 

  88. /*I2C_SDA    	*/{  66 ,        0,              2,        GPIO_43,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->i2c_m2_sda,      &hwp_iomux->pad_i2c_m2_sda, 		2},
    89. 

  89. 

  90. /*CAM_RST   	*/{  103 ,       0,              3,        GPIO_44,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->camera_rst_l,    &hwp_iomux->pad_camera_rst_l, 	2},
    91. 

  91. /*CAM_PWDN   	*/{  81 ,        0,              3,        GPIO_45,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->camera_pwdn,     &hwp_iomux->pad_camera_pwdn, 		2},
    92. 

  92. /*CAM_REFCLK   	*/{  54 ,        0,              2,        GPIO_46,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->camera_ref_clk,  &hwp_iomux->pad_camera_ref_clk, 	2},
    93. 

  93. /*SPI_CAM_SI0	*/{  55 ,        0,              3,        GPIO_47,   QUEC_PIN_NONE,     QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_camera_si_0, &hwp_iomux->pad_spi_camera_si_0,	2},
    94. 

  94. 

  95. //pinmux(not gpio part)
    96. 

  96. /*SPI_CAM_SI1   */{  56 ,        0,  QUEC_PIN_NONE,  QUEC_PIN_NONE,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_camera_si_1, &hwp_iomux->pad_spi_camera_si_1,	0},
    97. 

  97. /*SPI_CAM_SCK   */{  80 ,        0,  QUEC_PIN_NONE,  QUEC_PIN_NONE,   QUEC_PIN_NONE,    QUEC_PIN_NONE,    QUEC_PIN_NONE,    &hwp_iomux->spi_camera_sck,  &hwp_iomux->pad_spi_camera_sck, 	0},
    98. 

  98. 

  99. //             should before here!
    100. 

  100.                {QUEC_PIN_NONE,-1,            -1,             -1,              -1,               -1,                      -1},
    101. 

  101. };
    102. 

  102. 

  103. #ifdef CONFIG_QUEC_PROJECT_FEATURE_PSM
    104. 

  104. const quec_psm_pin_cfg_t quec_psm_pin_cfg[] = 
    105. 

  105. {
    106. 

  106.     {GPIO_0,  LVL_HIGH, 0},
    107. 

  107.     {GPIO_1,  LVL_HIGH, 0},
    108. 

  108.     {GPIO_2,  LVL_HIGH, 0},
    109. 

  109.     {GPIO_3,  LVL_HIGH, 0},
    110. 

  110.     {GPIO_4,  LVL_HIGH, 0},
    111. 

  111.     {GPIO_5,  LVL_HIGH, 0},
    112. 

  112.     {GPIO_6,  LVL_HIGH, 0},
    113. 

  113.     {GPIO_7,  LVL_HIGH, 0},
    114. 

  114.     {GPIO_MAX,LVL_HIGH, 0},
    115. 

  115. };
    116. 

  116. #endif
    117. 

  117. 

  118. #endif/* CONFIG_QL_OPEN_EXPORT_PKG */
    119. 

  119.