zhengchao

zhengchao pushed to 4G_ZK_01B_V1.2 at RuiLiWuLian/4G

  • 92e3b4d127 【测试】增加定时休眠唤醒功能,增加sy6970驱动(未开发完成)
  • ce0b394598 休眠时不断开ups本身的供电使能端口
  • 4be086924b 新增内置电源管理相关的端口配置
  • 198e3d5875 SOH修正指令数据长度修改(1个字节)
  • 9aa2e94df8 V0.2.0.13-MS 【重要】1、修复OTA更新未及时删除模组中升级文件(.bin/.zl),导致后期无法远程升级的bug; 2、修改BcuApp的存储量(增加SOH),并预留部分uint8、uint16和float量,同时修改将原有的CRC8改为CRC16,提升可靠性;3、添加BcuAppSaveInfo默认值,除SOH为100,其余值为0;4、增加SOH标定值下发链路,下发SOH精度0.1,真实值范围1-100;5、调试信息内容调整:删除三轴数据,增加BCU相关内容

1 year ago

zhengchao created new branch 4G_ZK_01B_V1.2 at RuiLiWuLian/4G

1 year ago

zhengchao pushed to 4G01B at zhengchao/S32K1_EB_TRESOS_MCAL

1 year ago

zhengchao pushed to 4G01B at zhengchao/S32K1_EB_TRESOS_MCAL

  • 257374e5ac 修改了工程路径
  • dc822bcc1b 4G01B适配启源丰都项目 1、调整ADC顺序 2、增加lptmr计时器
  • e699af858c 1、增加ADC配置,使能ADC1 采用中断模式 2、使能MCU中的ADC1时钟 3、在Platform中增加Adc_1_Isr中断
  • 5d9c3a47d9 1、使能DIO flip API 2、优化PLL配置,scg_clk_out 配置为SLOW_CLK
  • 1d16ea4a84 1、配置PLL,内核时钟采用PLL_CLK(80M),LSPI使用PLL时钟,UART、CAN使用SOSC时钟(16M) 2、删除FlexIO在UART中的应用,仅保留uart0-2

1 year ago

zhengchao created new branch 4G01B at zhengchao/S32K1_EB_TRESOS_MCAL

1 year ago

zhengchao pushed to 4G_ZK_01B-Debug at RuiLiWuLian/4G

  • 3511a0e61b V0.2.0.5版本更新 1、调整ADC 温度采集通道顺序,依次为TP1、TP2、TP3、TP4、TP_SYS 2、增加ADC初始化校准,提升ADC采集精度 3、增加LPTMR计时器模块(以备定时唤醒功能,尚未开发完成,4G01B暂无定时唤醒功能) 4、休眠条件增加(wakeup1和wakeup2通道为高电平时,系统不休眠) 5、指令重启方式由softwareReset改为wdgReset,以便减少bootloader跳转app时间(bootloader中,如RCM重启条件为wdg则等待升级指令,power on和softwareReset则直接跳转到app)

1 year ago

zhengchao pushed to Zhengchao at RuiLiWuLian/4G

2 years ago

zhengchao pushed to Zhengchao at RuiLiWuLian/BLE

  • df1d72e059 1、使能DIO flip API 2、优化PLL配置,scg_clk_out 配置为SLOW_CLK
  • ee5e153b2f Refresh adding .gitignore file.
  • f503f17b2e 增加过滤
  • c78f1bae92 【V1.1.1.1】蓝牙模块软件测试完成
  • c9ac152c3a 蓝牙调试初步完成,Uart的延时时间和串口未优化

2 years ago

zhengchao created new branch Zhengchao at RuiLiWuLian/BLE

2 years ago

zhengchao pushed to 4G at zhengchao/S32K1_EB_TRESOS_MCAL

2 years ago

zhengchao pushed to Zhengchao at RuiLiWuLian/4G

2 years ago

zhengchao pushed to Zhengchao at Chenjie/4G

  • 655a66e37d 1、使能DIO flip API 2、优化PLL配置,scg_clk_out 配置为SLOW_CLK
  • ee68385e00 1、增加SPI底层驱动 2、配置PLL,内核时钟采用PLL_CLK(80M),LSPI使用PLL时钟,UART、CAN使用SOSC时钟(16M) 3、删除FlexIO在UART中的应用,仅保留uart0-2
  • dec9542560 GPS上传测试完成
  • 20c663dbdd 4G联网及数据发送测试完成
  • f8994b3143 新建4G

2 years ago

zhengchao created new branch Zhengchao at Chenjie/4G

2 years ago

zhengchao pushed to 4G at zhengchao/S32K1_EB_TRESOS_MCAL

  • 1d16ea4a84 1、配置PLL,内核时钟采用PLL_CLK(80M),LSPI使用PLL时钟,UART、CAN使用SOSC时钟(16M) 2、删除FlexIO在UART中的应用,仅保留uart0-2

2 years ago

zhengchao pushed to BLE at zhengchao/S32K1_EB_TRESOS_MCAL

2 years ago

zhengchao pushed to Chenjie at Chenjie/4G

  • ee68385e00 1、增加SPI底层驱动 2、配置PLL,内核时钟采用PLL_CLK(80M),LSPI使用PLL时钟,UART、CAN使用SOSC时钟(16M) 3、删除FlexIO在UART中的应用,仅保留uart0-2

2 years ago

zhengchao pushed to 4G at zhengchao/S32K1_EB_TRESOS_MCAL

2 years ago

zhengchao pushed to master at Chenjie/BLE

2 years ago

zhengchao pushed to 4G at zhengchao/S32K1_EB_TRESOS_MCAL

  • c7ed392aa4 1、修改Port和DIO配置;2、优化mcl DMA配置

2 years ago

zhengchao pushed to 4G at zhengchao/S32K1_EB_TRESOS_MCAL

2 years ago